4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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19 * from this software without specific prior written permission.
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define NSEC_PER_SEC 1000000000L
130 #define IXGBE_INCVAL_10GB 0x66666666
131 #define IXGBE_INCVAL_1GB 0x40000000
132 #define IXGBE_INCVAL_100 0x50000000
133 #define IXGBE_INCVAL_SHIFT_10GB 28
134 #define IXGBE_INCVAL_SHIFT_1GB 24
135 #define IXGBE_INCVAL_SHIFT_100 21
136 #define IXGBE_INCVAL_SHIFT_82599 7
137 #define IXGBE_INCPER_SHIFT_82599 24
139 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
141 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
143 #define DEFAULT_ETAG_ETYPE 0x893f
144 #define IXGBE_ETAG_ETYPE 0x00005084
145 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
146 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
147 #define IXGBE_RAH_ADTYPE 0x40000000
148 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
149 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
152 #define IXGBE_QDE_STRIP_TAG 0x00000004
154 enum ixgbevf_xcast_modes {
155 IXGBEVF_XCAST_MODE_NONE = 0,
156 IXGBEVF_XCAST_MODE_MULTI,
157 IXGBEVF_XCAST_MODE_ALLMULTI,
160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
162 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
163 static int ixgbe_dev_start(struct rte_eth_dev *dev);
164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
165 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
166 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
173 int wait_to_complete);
174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
175 struct rte_eth_stats *stats);
176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
177 struct rte_eth_xstats *xstats, unsigned n);
178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
179 struct rte_eth_xstats *xstats, unsigned n);
180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
187 struct rte_eth_dev_info *dev_info);
188 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
189 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
190 struct rte_eth_dev_info *dev_info);
191 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
193 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
194 uint16_t vlan_id, int on);
195 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
196 enum rte_vlan_type vlan_type,
198 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
199 uint16_t queue, bool on);
200 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
202 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
203 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
204 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
205 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
206 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
208 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
209 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
210 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
211 struct rte_eth_fc_conf *fc_conf);
212 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_pfc_conf *pfc_conf);
216 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
217 struct rte_eth_rss_reta_entry64 *reta_conf,
219 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
220 struct rte_eth_rss_reta_entry64 *reta_conf,
222 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
223 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
224 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
225 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
226 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
227 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
229 static void ixgbe_dev_interrupt_delayed_handler(void *param);
230 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
231 uint32_t index, uint32_t pool);
232 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
233 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
234 struct ether_addr *mac_addr);
235 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
237 /* For Virtual Function support */
238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
240 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
241 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
246 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
247 struct rte_eth_stats *stats);
248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
250 uint16_t vlan_id, int on);
251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
252 uint16_t queue, int on);
253 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
260 uint8_t queue, uint8_t msix_vector);
261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
265 /* For Eth VMDQ APIs support */
266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
267 ether_addr* mac_addr,uint8_t on);
268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
269 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
270 uint16_t rx_mask, uint8_t on);
271 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
272 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
273 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
274 uint64_t pool_mask,uint8_t vlan_on);
275 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
276 struct rte_eth_mirror_conf *mirror_conf,
277 uint8_t rule_id, uint8_t on);
278 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
280 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
282 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
284 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
285 uint8_t queue, uint8_t msix_vector);
286 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
288 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
289 uint16_t queue_idx, uint16_t tx_rate);
290 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
291 uint16_t tx_rate, uint64_t q_msk);
293 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
294 struct ether_addr *mac_addr,
295 uint32_t index, uint32_t pool);
296 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
297 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
298 struct ether_addr *mac_addr);
299 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
300 struct rte_eth_syn_filter *filter,
302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
303 struct rte_eth_syn_filter *filter);
304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
305 enum rte_filter_op filter_op,
307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
308 struct ixgbe_5tuple_filter *filter);
309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
310 struct ixgbe_5tuple_filter *filter);
311 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
312 struct rte_eth_ntuple_filter *filter,
314 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
315 enum rte_filter_op filter_op,
317 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
318 struct rte_eth_ntuple_filter *filter);
319 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
320 struct rte_eth_ethertype_filter *filter,
322 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
323 enum rte_filter_op filter_op,
325 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
326 struct rte_eth_ethertype_filter *filter);
327 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
328 enum rte_filter_type filter_type,
329 enum rte_filter_op filter_op,
331 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
333 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
334 struct ether_addr *mc_addr_set,
335 uint32_t nb_mc_addr);
336 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
337 struct rte_eth_dcb_info *dcb_info);
339 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
340 static int ixgbe_get_regs(struct rte_eth_dev *dev,
341 struct rte_dev_reg_info *regs);
342 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
343 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
344 struct rte_dev_eeprom_info *eeprom);
345 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
346 struct rte_dev_eeprom_info *eeprom);
348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
350 struct rte_dev_reg_info *regs);
352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
355 struct timespec *timestamp,
357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
358 struct timespec *timestamp);
359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
361 struct timespec *timestamp);
362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
363 const struct timespec *timestamp);
365 static int ixgbe_dev_l2_tunnel_eth_type_conf
366 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
367 static int ixgbe_dev_l2_tunnel_offload_set
368 (struct rte_eth_dev *dev,
369 struct rte_eth_l2_tunnel_conf *l2_tunnel,
372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
373 enum rte_filter_op filter_op,
376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
377 struct rte_eth_udp_tunnel *udp_tunnel);
378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
379 struct rte_eth_udp_tunnel *udp_tunnel);
382 * Define VF Stats MACRO for Non "cleared on read" register
384 #define UPDATE_VF_STAT(reg, last, cur) \
386 uint32_t latest = IXGBE_READ_REG(hw, reg); \
387 cur += (latest - last) & UINT_MAX; \
391 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
393 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
394 u64 new_msb = IXGBE_READ_REG(hw, msb); \
395 u64 latest = ((new_msb << 32) | new_lsb); \
396 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
400 #define IXGBE_SET_HWSTRIP(h, q) do{\
401 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
402 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
403 (h)->bitmap[idx] |= 1 << bit;\
406 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
407 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
408 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
409 (h)->bitmap[idx] &= ~(1 << bit);\
412 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
413 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
414 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
415 (r) = (h)->bitmap[idx] >> bit & 1;\
419 * The set of PCI devices this driver supports
421 static const struct rte_pci_id pci_id_ixgbe_map[] = {
423 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
424 #include "rte_pci_dev_ids.h"
426 { .vendor_id = 0, /* sentinel */ },
431 * The set of PCI devices this driver supports (for 82599 VF)
433 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
435 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
436 #include "rte_pci_dev_ids.h"
437 { .vendor_id = 0, /* sentinel */ },
441 static const struct rte_eth_desc_lim rx_desc_lim = {
442 .nb_max = IXGBE_MAX_RING_DESC,
443 .nb_min = IXGBE_MIN_RING_DESC,
444 .nb_align = IXGBE_RXD_ALIGN,
447 static const struct rte_eth_desc_lim tx_desc_lim = {
448 .nb_max = IXGBE_MAX_RING_DESC,
449 .nb_min = IXGBE_MIN_RING_DESC,
450 .nb_align = IXGBE_TXD_ALIGN,
453 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
454 .dev_configure = ixgbe_dev_configure,
455 .dev_start = ixgbe_dev_start,
456 .dev_stop = ixgbe_dev_stop,
457 .dev_set_link_up = ixgbe_dev_set_link_up,
458 .dev_set_link_down = ixgbe_dev_set_link_down,
459 .dev_close = ixgbe_dev_close,
460 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
461 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
462 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
463 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
464 .link_update = ixgbe_dev_link_update,
465 .stats_get = ixgbe_dev_stats_get,
466 .xstats_get = ixgbe_dev_xstats_get,
467 .stats_reset = ixgbe_dev_stats_reset,
468 .xstats_reset = ixgbe_dev_xstats_reset,
469 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
470 .dev_infos_get = ixgbe_dev_info_get,
471 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
472 .mtu_set = ixgbe_dev_mtu_set,
473 .vlan_filter_set = ixgbe_vlan_filter_set,
474 .vlan_tpid_set = ixgbe_vlan_tpid_set,
475 .vlan_offload_set = ixgbe_vlan_offload_set,
476 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
477 .rx_queue_start = ixgbe_dev_rx_queue_start,
478 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
479 .tx_queue_start = ixgbe_dev_tx_queue_start,
480 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
481 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
482 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
483 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
484 .rx_queue_release = ixgbe_dev_rx_queue_release,
485 .rx_queue_count = ixgbe_dev_rx_queue_count,
486 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
487 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
488 .tx_queue_release = ixgbe_dev_tx_queue_release,
489 .dev_led_on = ixgbe_dev_led_on,
490 .dev_led_off = ixgbe_dev_led_off,
491 .flow_ctrl_get = ixgbe_flow_ctrl_get,
492 .flow_ctrl_set = ixgbe_flow_ctrl_set,
493 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
494 .mac_addr_add = ixgbe_add_rar,
495 .mac_addr_remove = ixgbe_remove_rar,
496 .mac_addr_set = ixgbe_set_default_mac_addr,
497 .uc_hash_table_set = ixgbe_uc_hash_table_set,
498 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
499 .mirror_rule_set = ixgbe_mirror_rule_set,
500 .mirror_rule_reset = ixgbe_mirror_rule_reset,
501 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
502 .set_vf_rx = ixgbe_set_pool_rx,
503 .set_vf_tx = ixgbe_set_pool_tx,
504 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
505 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
506 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
507 .reta_update = ixgbe_dev_rss_reta_update,
508 .reta_query = ixgbe_dev_rss_reta_query,
509 #ifdef RTE_NIC_BYPASS
510 .bypass_init = ixgbe_bypass_init,
511 .bypass_state_set = ixgbe_bypass_state_store,
512 .bypass_state_show = ixgbe_bypass_state_show,
513 .bypass_event_set = ixgbe_bypass_event_store,
514 .bypass_event_show = ixgbe_bypass_event_show,
515 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
516 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
517 .bypass_ver_show = ixgbe_bypass_ver_show,
518 .bypass_wd_reset = ixgbe_bypass_wd_reset,
519 #endif /* RTE_NIC_BYPASS */
520 .rss_hash_update = ixgbe_dev_rss_hash_update,
521 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
522 .filter_ctrl = ixgbe_dev_filter_ctrl,
523 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
524 .rxq_info_get = ixgbe_rxq_info_get,
525 .txq_info_get = ixgbe_txq_info_get,
526 .timesync_enable = ixgbe_timesync_enable,
527 .timesync_disable = ixgbe_timesync_disable,
528 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
529 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
530 .get_reg_length = ixgbe_get_reg_length,
531 .get_reg = ixgbe_get_regs,
532 .get_eeprom_length = ixgbe_get_eeprom_length,
533 .get_eeprom = ixgbe_get_eeprom,
534 .set_eeprom = ixgbe_set_eeprom,
535 .get_dcb_info = ixgbe_dev_get_dcb_info,
536 .timesync_adjust_time = ixgbe_timesync_adjust_time,
537 .timesync_read_time = ixgbe_timesync_read_time,
538 .timesync_write_time = ixgbe_timesync_write_time,
539 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
540 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
541 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
542 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
546 * dev_ops for virtual function, bare necessities for basic vf
547 * operation have been implemented
549 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
550 .dev_configure = ixgbevf_dev_configure,
551 .dev_start = ixgbevf_dev_start,
552 .dev_stop = ixgbevf_dev_stop,
553 .link_update = ixgbe_dev_link_update,
554 .stats_get = ixgbevf_dev_stats_get,
555 .xstats_get = ixgbevf_dev_xstats_get,
556 .stats_reset = ixgbevf_dev_stats_reset,
557 .xstats_reset = ixgbevf_dev_stats_reset,
558 .dev_close = ixgbevf_dev_close,
559 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
560 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
561 .dev_infos_get = ixgbevf_dev_info_get,
562 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
563 .mtu_set = ixgbevf_dev_set_mtu,
564 .vlan_filter_set = ixgbevf_vlan_filter_set,
565 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
566 .vlan_offload_set = ixgbevf_vlan_offload_set,
567 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
568 .rx_queue_release = ixgbe_dev_rx_queue_release,
569 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
570 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
571 .tx_queue_release = ixgbe_dev_tx_queue_release,
572 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
573 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
574 .mac_addr_add = ixgbevf_add_mac_addr,
575 .mac_addr_remove = ixgbevf_remove_mac_addr,
576 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
577 .rxq_info_get = ixgbe_rxq_info_get,
578 .txq_info_get = ixgbe_txq_info_get,
579 .mac_addr_set = ixgbevf_set_default_mac_addr,
580 .get_reg_length = ixgbevf_get_reg_length,
581 .get_reg = ixgbevf_get_regs,
582 .reta_update = ixgbe_dev_rss_reta_update,
583 .reta_query = ixgbe_dev_rss_reta_query,
584 .rss_hash_update = ixgbe_dev_rss_hash_update,
585 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
588 /* store statistics names and its offset in stats structure */
589 struct rte_ixgbe_xstats_name_off {
590 char name[RTE_ETH_XSTATS_NAME_SIZE];
594 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
595 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
596 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
597 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
598 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
599 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
600 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
601 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
602 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
603 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
604 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
605 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
606 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
607 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
608 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
609 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
611 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
613 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
614 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
615 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
616 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
617 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
618 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
619 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
620 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
621 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
622 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
623 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
624 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
625 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
626 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
627 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
628 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
629 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
631 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
633 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
634 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
635 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
636 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
638 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
640 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
642 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
644 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
646 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
648 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
651 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
652 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
653 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
655 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
656 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
657 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
658 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
659 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
661 {"rx_fcoe_no_direct_data_placement_ext_buff",
662 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
664 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
666 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
668 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
670 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
672 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
675 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
676 sizeof(rte_ixgbe_stats_strings[0]))
678 /* Per-queue statistics */
679 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
680 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
681 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
682 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
683 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
686 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
687 sizeof(rte_ixgbe_rxq_strings[0]))
689 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
690 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
691 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
692 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
696 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
697 sizeof(rte_ixgbe_txq_strings[0]))
699 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
700 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
703 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
704 sizeof(rte_ixgbevf_stats_strings[0]))
707 * Atomically reads the link status information from global
708 * structure rte_eth_dev.
711 * - Pointer to the structure rte_eth_dev to read from.
712 * - Pointer to the buffer to be saved with the link status.
715 * - On success, zero.
716 * - On failure, negative value.
719 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
720 struct rte_eth_link *link)
722 struct rte_eth_link *dst = link;
723 struct rte_eth_link *src = &(dev->data->dev_link);
725 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
726 *(uint64_t *)src) == 0)
733 * Atomically writes the link status information into global
734 * structure rte_eth_dev.
737 * - Pointer to the structure rte_eth_dev to read from.
738 * - Pointer to the buffer to be saved with the link status.
741 * - On success, zero.
742 * - On failure, negative value.
745 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
746 struct rte_eth_link *link)
748 struct rte_eth_link *dst = &(dev->data->dev_link);
749 struct rte_eth_link *src = link;
751 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
752 *(uint64_t *)src) == 0)
759 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
762 ixgbe_is_sfp(struct ixgbe_hw *hw)
764 switch (hw->phy.type) {
765 case ixgbe_phy_sfp_avago:
766 case ixgbe_phy_sfp_ftl:
767 case ixgbe_phy_sfp_intel:
768 case ixgbe_phy_sfp_unknown:
769 case ixgbe_phy_sfp_passive_tyco:
770 case ixgbe_phy_sfp_passive_unknown:
777 static inline int32_t
778 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
783 status = ixgbe_reset_hw(hw);
785 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
786 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
787 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
788 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
789 IXGBE_WRITE_FLUSH(hw);
795 ixgbe_enable_intr(struct rte_eth_dev *dev)
797 struct ixgbe_interrupt *intr =
798 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
799 struct ixgbe_hw *hw =
800 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
802 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
803 IXGBE_WRITE_FLUSH(hw);
807 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
810 ixgbe_disable_intr(struct ixgbe_hw *hw)
812 PMD_INIT_FUNC_TRACE();
814 if (hw->mac.type == ixgbe_mac_82598EB) {
815 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
817 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
818 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
819 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
821 IXGBE_WRITE_FLUSH(hw);
825 * This function resets queue statistics mapping registers.
826 * From Niantic datasheet, Initialization of Statistics section:
827 * "...if software requires the queue counters, the RQSMR and TQSM registers
828 * must be re-programmed following a device reset.
831 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
835 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
836 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
837 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
843 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
848 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
849 #define NB_QMAP_FIELDS_PER_QSM_REG 4
850 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
852 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
853 struct ixgbe_stat_mapping_registers *stat_mappings =
854 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
855 uint32_t qsmr_mask = 0;
856 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
860 if ((hw->mac.type != ixgbe_mac_82599EB) &&
861 (hw->mac.type != ixgbe_mac_X540) &&
862 (hw->mac.type != ixgbe_mac_X550) &&
863 (hw->mac.type != ixgbe_mac_X550EM_x) &&
864 (hw->mac.type != ixgbe_mac_X550EM_a))
867 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
868 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
871 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
872 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
873 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
876 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
878 /* Now clear any previous stat_idx set */
879 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
881 stat_mappings->tqsm[n] &= ~clearing_mask;
883 stat_mappings->rqsmr[n] &= ~clearing_mask;
885 q_map = (uint32_t)stat_idx;
886 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
887 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
889 stat_mappings->tqsm[n] |= qsmr_mask;
891 stat_mappings->rqsmr[n] |= qsmr_mask;
893 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
894 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
896 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
897 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
899 /* Now write the mapping in the appropriate register */
901 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
902 stat_mappings->rqsmr[n], n);
903 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
906 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
907 stat_mappings->tqsm[n], n);
908 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
914 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
916 struct ixgbe_stat_mapping_registers *stat_mappings =
917 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
918 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
921 /* write whatever was in stat mapping table to the NIC */
922 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
924 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
927 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
932 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
935 struct ixgbe_dcb_tc_config *tc;
936 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
938 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
939 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
940 for (i = 0; i < dcb_max_tc; i++) {
941 tc = &dcb_config->tc_config[i];
942 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
943 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
944 (uint8_t)(100/dcb_max_tc + (i & 1));
945 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
946 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
947 (uint8_t)(100/dcb_max_tc + (i & 1));
948 tc->pfc = ixgbe_dcb_pfc_disabled;
951 /* Initialize default user to priority mapping, UPx->TC0 */
952 tc = &dcb_config->tc_config[0];
953 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
954 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
955 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
956 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
957 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
959 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
960 dcb_config->pfc_mode_enable = false;
961 dcb_config->vt_mode = true;
962 dcb_config->round_robin_enable = false;
963 /* support all DCB capabilities in 82599 */
964 dcb_config->support.capabilities = 0xFF;
966 /*we only support 4 Tcs for X540, X550 */
967 if (hw->mac.type == ixgbe_mac_X540 ||
968 hw->mac.type == ixgbe_mac_X550 ||
969 hw->mac.type == ixgbe_mac_X550EM_x ||
970 hw->mac.type == ixgbe_mac_X550EM_a) {
971 dcb_config->num_tcs.pg_tcs = 4;
972 dcb_config->num_tcs.pfc_tcs = 4;
977 * Ensure that all locks are released before first NVM or PHY access
980 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
985 * Phy lock should not fail in this early stage. If this is the case,
986 * it is due to an improper exit of the application.
987 * So force the release of the faulty lock. Release of common lock
988 * is done automatically by swfw_sync function.
990 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
991 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
992 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
994 ixgbe_release_swfw_semaphore(hw, mask);
997 * These ones are more tricky since they are common to all ports; but
998 * swfw_sync retries last long enough (1s) to be almost sure that if
999 * lock can not be taken it is due to an improper lock of the
1002 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1003 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1004 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1006 ixgbe_release_swfw_semaphore(hw, mask);
1010 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1011 * It returns 0 on success.
1014 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1016 struct rte_pci_device *pci_dev;
1017 struct ixgbe_hw *hw =
1018 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1019 struct ixgbe_vfta * shadow_vfta =
1020 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1021 struct ixgbe_hwstrip *hwstrip =
1022 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1023 struct ixgbe_dcb_config *dcb_config =
1024 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1025 struct ixgbe_filter_info *filter_info =
1026 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1031 PMD_INIT_FUNC_TRACE();
1033 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1034 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1035 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1038 * For secondary processes, we don't initialise any further as primary
1039 * has already done this work. Only check we don't need a different
1040 * RX and TX function.
1042 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1043 struct ixgbe_tx_queue *txq;
1044 /* TX queue function in primary, set by last queue initialized
1045 * Tx queue may not initialized by primary process */
1046 if (eth_dev->data->tx_queues) {
1047 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1048 ixgbe_set_tx_function(eth_dev, txq);
1050 /* Use default TX function if we get here */
1051 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1052 "Using default TX function.");
1055 ixgbe_set_rx_function(eth_dev);
1059 pci_dev = eth_dev->pci_dev;
1061 rte_eth_copy_pci_info(eth_dev, pci_dev);
1063 /* Vendor and Device ID need to be set before init of shared code */
1064 hw->device_id = pci_dev->id.device_id;
1065 hw->vendor_id = pci_dev->id.vendor_id;
1066 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1067 hw->allow_unsupported_sfp = 1;
1069 /* Initialize the shared code (base driver) */
1070 #ifdef RTE_NIC_BYPASS
1071 diag = ixgbe_bypass_init_shared_code(hw);
1073 diag = ixgbe_init_shared_code(hw);
1074 #endif /* RTE_NIC_BYPASS */
1076 if (diag != IXGBE_SUCCESS) {
1077 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1081 /* pick up the PCI bus settings for reporting later */
1082 ixgbe_get_bus_info(hw);
1084 /* Unlock any pending hardware semaphore */
1085 ixgbe_swfw_lock_reset(hw);
1087 /* Initialize DCB configuration*/
1088 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1089 ixgbe_dcb_init(hw,dcb_config);
1090 /* Get Hardware Flow Control setting */
1091 hw->fc.requested_mode = ixgbe_fc_full;
1092 hw->fc.current_mode = ixgbe_fc_full;
1093 hw->fc.pause_time = IXGBE_FC_PAUSE;
1094 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1095 hw->fc.low_water[i] = IXGBE_FC_LO;
1096 hw->fc.high_water[i] = IXGBE_FC_HI;
1098 hw->fc.send_xon = 1;
1100 /* Make sure we have a good EEPROM before we read from it */
1101 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1102 if (diag != IXGBE_SUCCESS) {
1103 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1107 #ifdef RTE_NIC_BYPASS
1108 diag = ixgbe_bypass_init_hw(hw);
1110 diag = ixgbe_init_hw(hw);
1111 #endif /* RTE_NIC_BYPASS */
1114 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1115 * is called too soon after the kernel driver unbinding/binding occurs.
1116 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1117 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1118 * also called. See ixgbe_identify_phy_82599(). The reason for the
1119 * failure is not known, and only occuts when virtualisation features
1120 * are disabled in the bios. A delay of 100ms was found to be enough by
1121 * trial-and-error, and is doubled to be safe.
1123 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1125 diag = ixgbe_init_hw(hw);
1128 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1129 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1130 "LOM. Please be aware there may be issues associated "
1131 "with your hardware.");
1132 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1133 "please contact your Intel or hardware representative "
1134 "who provided you with this hardware.");
1135 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1136 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1138 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1142 /* Reset the hw statistics */
1143 ixgbe_dev_stats_reset(eth_dev);
1145 /* disable interrupt */
1146 ixgbe_disable_intr(hw);
1148 /* reset mappings for queue statistics hw counters*/
1149 ixgbe_reset_qstat_mappings(hw);
1151 /* Allocate memory for storing MAC addresses */
1152 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1153 hw->mac.num_rar_entries, 0);
1154 if (eth_dev->data->mac_addrs == NULL) {
1156 "Failed to allocate %u bytes needed to store "
1158 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1161 /* Copy the permanent MAC address */
1162 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1163 ð_dev->data->mac_addrs[0]);
1165 /* Allocate memory for storing hash filter MAC addresses */
1166 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167 IXGBE_VMDQ_NUM_UC_MAC, 0);
1168 if (eth_dev->data->hash_mac_addrs == NULL) {
1170 "Failed to allocate %d bytes needed to store MAC addresses",
1171 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1175 /* initialize the vfta */
1176 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1178 /* initialize the hw strip bitmap*/
1179 memset(hwstrip, 0, sizeof(*hwstrip));
1181 /* initialize PF if max_vfs not zero */
1182 ixgbe_pf_host_init(eth_dev);
1184 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1185 /* let hardware know driver is loaded */
1186 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1187 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1188 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1189 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1190 IXGBE_WRITE_FLUSH(hw);
1192 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1193 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1194 (int) hw->mac.type, (int) hw->phy.type,
1195 (int) hw->phy.sfp_type);
1197 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1198 (int) hw->mac.type, (int) hw->phy.type);
1200 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1201 eth_dev->data->port_id, pci_dev->id.vendor_id,
1202 pci_dev->id.device_id);
1204 rte_intr_callback_register(&pci_dev->intr_handle,
1205 ixgbe_dev_interrupt_handler,
1208 /* enable uio/vfio intr/eventfd mapping */
1209 rte_intr_enable(&pci_dev->intr_handle);
1211 /* enable support intr */
1212 ixgbe_enable_intr(eth_dev);
1214 /* initialize 5tuple filter list */
1215 TAILQ_INIT(&filter_info->fivetuple_list);
1216 memset(filter_info->fivetuple_mask, 0,
1217 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1223 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1225 struct rte_pci_device *pci_dev;
1226 struct ixgbe_hw *hw;
1228 PMD_INIT_FUNC_TRACE();
1230 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1233 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1234 pci_dev = eth_dev->pci_dev;
1236 if (hw->adapter_stopped == 0)
1237 ixgbe_dev_close(eth_dev);
1239 eth_dev->dev_ops = NULL;
1240 eth_dev->rx_pkt_burst = NULL;
1241 eth_dev->tx_pkt_burst = NULL;
1243 /* Unlock any pending hardware semaphore */
1244 ixgbe_swfw_lock_reset(hw);
1246 /* disable uio intr before callback unregister */
1247 rte_intr_disable(&(pci_dev->intr_handle));
1248 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1249 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1251 /* uninitialize PF if max_vfs not zero */
1252 ixgbe_pf_host_uninit(eth_dev);
1254 rte_free(eth_dev->data->mac_addrs);
1255 eth_dev->data->mac_addrs = NULL;
1257 rte_free(eth_dev->data->hash_mac_addrs);
1258 eth_dev->data->hash_mac_addrs = NULL;
1264 * Negotiate mailbox API version with the PF.
1265 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1266 * Then we try to negotiate starting with the most recent one.
1267 * If all negotiation attempts fail, then we will proceed with
1268 * the default one (ixgbe_mbox_api_10).
1271 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1275 /* start with highest supported, proceed down */
1276 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1283 i != RTE_DIM(sup_ver) &&
1284 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1290 generate_random_mac_addr(struct ether_addr *mac_addr)
1294 /* Set Organizationally Unique Identifier (OUI) prefix. */
1295 mac_addr->addr_bytes[0] = 0x00;
1296 mac_addr->addr_bytes[1] = 0x09;
1297 mac_addr->addr_bytes[2] = 0xC0;
1298 /* Force indication of locally assigned MAC address. */
1299 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1300 /* Generate the last 3 bytes of the MAC address with a random number. */
1301 random = rte_rand();
1302 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1306 * Virtual Function device init
1309 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1313 struct rte_pci_device *pci_dev;
1314 struct ixgbe_hw *hw =
1315 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316 struct ixgbe_vfta * shadow_vfta =
1317 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1318 struct ixgbe_hwstrip *hwstrip =
1319 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1320 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1322 PMD_INIT_FUNC_TRACE();
1324 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1325 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1326 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1328 /* for secondary processes, we don't initialise any further as primary
1329 * has already done this work. Only check we don't need a different
1331 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1332 struct ixgbe_tx_queue *txq;
1333 /* TX queue function in primary, set by last queue initialized
1334 * Tx queue may not initialized by primary process
1336 if (eth_dev->data->tx_queues) {
1337 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1338 ixgbe_set_tx_function(eth_dev, txq);
1340 /* Use default TX function if we get here */
1341 PMD_INIT_LOG(NOTICE,
1342 "No TX queues configured yet. Using default TX function.");
1345 ixgbe_set_rx_function(eth_dev);
1350 pci_dev = eth_dev->pci_dev;
1352 rte_eth_copy_pci_info(eth_dev, pci_dev);
1354 hw->device_id = pci_dev->id.device_id;
1355 hw->vendor_id = pci_dev->id.vendor_id;
1356 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1358 /* initialize the vfta */
1359 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1361 /* initialize the hw strip bitmap*/
1362 memset(hwstrip, 0, sizeof(*hwstrip));
1364 /* Initialize the shared code (base driver) */
1365 diag = ixgbe_init_shared_code(hw);
1366 if (diag != IXGBE_SUCCESS) {
1367 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1371 /* init_mailbox_params */
1372 hw->mbx.ops.init_params(hw);
1374 /* Reset the hw statistics */
1375 ixgbevf_dev_stats_reset(eth_dev);
1377 /* Disable the interrupts for VF */
1378 ixgbevf_intr_disable(hw);
1380 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1381 diag = hw->mac.ops.reset_hw(hw);
1384 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1385 * the underlying PF driver has not assigned a MAC address to the VF.
1386 * In this case, assign a random MAC address.
1388 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1389 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1393 /* negotiate mailbox API version to use with the PF. */
1394 ixgbevf_negotiate_api(hw);
1396 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1397 ixgbevf_get_queues(hw, &tcs, &tc);
1399 /* Allocate memory for storing MAC addresses */
1400 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1401 hw->mac.num_rar_entries, 0);
1402 if (eth_dev->data->mac_addrs == NULL) {
1404 "Failed to allocate %u bytes needed to store "
1406 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1410 /* Generate a random MAC address, if none was assigned by PF. */
1411 if (is_zero_ether_addr(perm_addr)) {
1412 generate_random_mac_addr(perm_addr);
1413 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1415 rte_free(eth_dev->data->mac_addrs);
1416 eth_dev->data->mac_addrs = NULL;
1419 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1420 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1421 "%02x:%02x:%02x:%02x:%02x:%02x",
1422 perm_addr->addr_bytes[0],
1423 perm_addr->addr_bytes[1],
1424 perm_addr->addr_bytes[2],
1425 perm_addr->addr_bytes[3],
1426 perm_addr->addr_bytes[4],
1427 perm_addr->addr_bytes[5]);
1430 /* Copy the permanent MAC address */
1431 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1433 /* reset the hardware with the new settings */
1434 diag = hw->mac.ops.start_hw(hw);
1440 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1444 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1445 eth_dev->data->port_id, pci_dev->id.vendor_id,
1446 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1451 /* Virtual Function device uninit */
1454 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1456 struct ixgbe_hw *hw;
1458 PMD_INIT_FUNC_TRACE();
1460 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1463 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1465 if (hw->adapter_stopped == 0)
1466 ixgbevf_dev_close(eth_dev);
1468 eth_dev->dev_ops = NULL;
1469 eth_dev->rx_pkt_burst = NULL;
1470 eth_dev->tx_pkt_burst = NULL;
1472 /* Disable the interrupts for VF */
1473 ixgbevf_intr_disable(hw);
1475 rte_free(eth_dev->data->mac_addrs);
1476 eth_dev->data->mac_addrs = NULL;
1481 static struct eth_driver rte_ixgbe_pmd = {
1483 .name = "rte_ixgbe_pmd",
1484 .id_table = pci_id_ixgbe_map,
1485 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1486 RTE_PCI_DRV_DETACHABLE,
1488 .eth_dev_init = eth_ixgbe_dev_init,
1489 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1490 .dev_private_size = sizeof(struct ixgbe_adapter),
1494 * virtual function driver struct
1496 static struct eth_driver rte_ixgbevf_pmd = {
1498 .name = "rte_ixgbevf_pmd",
1499 .id_table = pci_id_ixgbevf_map,
1500 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1502 .eth_dev_init = eth_ixgbevf_dev_init,
1503 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1504 .dev_private_size = sizeof(struct ixgbe_adapter),
1508 * Driver initialization routine.
1509 * Invoked once at EAL init time.
1510 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1513 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1515 PMD_INIT_FUNC_TRACE();
1517 rte_eth_driver_register(&rte_ixgbe_pmd);
1522 * VF Driver initialization routine.
1523 * Invoked one at EAL init time.
1524 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1527 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1529 PMD_INIT_FUNC_TRACE();
1531 rte_eth_driver_register(&rte_ixgbevf_pmd);
1536 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1538 struct ixgbe_hw *hw =
1539 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540 struct ixgbe_vfta * shadow_vfta =
1541 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1546 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1547 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1548 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1553 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1555 /* update local VFTA copy */
1556 shadow_vfta->vfta[vid_idx] = vfta;
1562 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1565 ixgbe_vlan_hw_strip_enable(dev, queue);
1567 ixgbe_vlan_hw_strip_disable(dev, queue);
1571 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1572 enum rte_vlan_type vlan_type,
1575 struct ixgbe_hw *hw =
1576 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579 switch (vlan_type) {
1580 case ETH_VLAN_TYPE_INNER:
1581 /* Only the high 16-bits is valid */
1582 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1586 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1594 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1596 struct ixgbe_hw *hw =
1597 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600 PMD_INIT_FUNC_TRACE();
1602 /* Filter Table Disable */
1603 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1604 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1606 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1610 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1612 struct ixgbe_hw *hw =
1613 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614 struct ixgbe_vfta * shadow_vfta =
1615 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1619 PMD_INIT_FUNC_TRACE();
1621 /* Filter Table Enable */
1622 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1623 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1624 vlnctrl |= IXGBE_VLNCTRL_VFE;
1626 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1628 /* write whatever is in local vfta copy */
1629 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1630 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1634 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1636 struct ixgbe_hwstrip *hwstrip =
1637 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1639 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1643 IXGBE_SET_HWSTRIP(hwstrip, queue);
1645 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1649 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1651 struct ixgbe_hw *hw =
1652 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655 PMD_INIT_FUNC_TRACE();
1657 if (hw->mac.type == ixgbe_mac_82598EB) {
1658 /* No queue level support */
1659 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1663 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1664 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1665 ctrl &= ~IXGBE_RXDCTL_VME;
1666 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1668 /* record those setting for HW strip per queue */
1669 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1673 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1675 struct ixgbe_hw *hw =
1676 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1679 PMD_INIT_FUNC_TRACE();
1681 if (hw->mac.type == ixgbe_mac_82598EB) {
1682 /* No queue level supported */
1683 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1687 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1688 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1689 ctrl |= IXGBE_RXDCTL_VME;
1690 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1692 /* record those setting for HW strip per queue */
1693 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1697 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1699 struct ixgbe_hw *hw =
1700 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 PMD_INIT_FUNC_TRACE();
1706 if (hw->mac.type == ixgbe_mac_82598EB) {
1707 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1708 ctrl &= ~IXGBE_VLNCTRL_VME;
1709 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1712 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1713 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1714 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1715 ctrl &= ~IXGBE_RXDCTL_VME;
1716 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1718 /* record those setting for HW strip per queue */
1719 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1725 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1727 struct ixgbe_hw *hw =
1728 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732 PMD_INIT_FUNC_TRACE();
1734 if (hw->mac.type == ixgbe_mac_82598EB) {
1735 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1736 ctrl |= IXGBE_VLNCTRL_VME;
1737 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1740 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1741 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1742 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1743 ctrl |= IXGBE_RXDCTL_VME;
1744 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1746 /* record those setting for HW strip per queue */
1747 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1753 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1755 struct ixgbe_hw *hw =
1756 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1759 PMD_INIT_FUNC_TRACE();
1761 /* DMATXCTRL: Geric Double VLAN Disable */
1762 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1763 ctrl &= ~IXGBE_DMATXCTL_GDV;
1764 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1766 /* CTRL_EXT: Global Double VLAN Disable */
1767 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1768 ctrl &= ~IXGBE_EXTENDED_VLAN;
1769 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1774 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1776 struct ixgbe_hw *hw =
1777 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1780 PMD_INIT_FUNC_TRACE();
1782 /* DMATXCTRL: Geric Double VLAN Enable */
1783 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1784 ctrl |= IXGBE_DMATXCTL_GDV;
1785 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1787 /* CTRL_EXT: Global Double VLAN Enable */
1788 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1789 ctrl |= IXGBE_EXTENDED_VLAN;
1790 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1792 /* Clear pooling mode of PFVTCTL. It's required by X550. */
1793 if (hw->mac.type == ixgbe_mac_X550 ||
1794 hw->mac.type == ixgbe_mac_X550EM_x ||
1795 hw->mac.type == ixgbe_mac_X550EM_a) {
1796 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1797 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1798 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1802 * VET EXT field in the EXVET register = 0x8100 by default
1803 * So no need to change. Same to VT field of DMATXCTL register
1808 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1810 if (mask & ETH_VLAN_STRIP_MASK) {
1811 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1812 ixgbe_vlan_hw_strip_enable_all(dev);
1814 ixgbe_vlan_hw_strip_disable_all(dev);
1817 if (mask & ETH_VLAN_FILTER_MASK) {
1818 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1819 ixgbe_vlan_hw_filter_enable(dev);
1821 ixgbe_vlan_hw_filter_disable(dev);
1824 if (mask & ETH_VLAN_EXTEND_MASK) {
1825 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1826 ixgbe_vlan_hw_extend_enable(dev);
1828 ixgbe_vlan_hw_extend_disable(dev);
1833 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1835 struct ixgbe_hw *hw =
1836 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1838 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1839 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1840 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1844 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1849 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1852 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1858 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1859 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1865 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1867 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1868 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1870 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1872 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1873 /* check multi-queue mode */
1874 switch (dev_conf->rxmode.mq_mode) {
1875 case ETH_MQ_RX_VMDQ_DCB:
1876 case ETH_MQ_RX_VMDQ_DCB_RSS:
1877 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1878 PMD_INIT_LOG(ERR, "SRIOV active,"
1879 " unsupported mq_mode rx %d.",
1880 dev_conf->rxmode.mq_mode);
1883 case ETH_MQ_RX_VMDQ_RSS:
1884 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1885 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1886 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1887 PMD_INIT_LOG(ERR, "SRIOV is active,"
1888 " invalid queue number"
1889 " for VMDQ RSS, allowed"
1890 " value are 1, 2 or 4.");
1894 case ETH_MQ_RX_VMDQ_ONLY:
1895 case ETH_MQ_RX_NONE:
1896 /* if nothing mq mode configure, use default scheme */
1897 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1898 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1899 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1901 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1902 /* SRIOV only works in VMDq enable mode */
1903 PMD_INIT_LOG(ERR, "SRIOV is active,"
1904 " wrong mq_mode rx %d.",
1905 dev_conf->rxmode.mq_mode);
1909 switch (dev_conf->txmode.mq_mode) {
1910 case ETH_MQ_TX_VMDQ_DCB:
1911 /* DCB VMDQ in SRIOV mode, not implement yet */
1912 PMD_INIT_LOG(ERR, "SRIOV is active,"
1913 " unsupported VMDQ mq_mode tx %d.",
1914 dev_conf->txmode.mq_mode);
1916 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1917 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1921 /* check valid queue number */
1922 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1923 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1924 PMD_INIT_LOG(ERR, "SRIOV is active,"
1925 " nb_rx_q=%d nb_tx_q=%d queue number"
1926 " must be less than or equal to %d.",
1928 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1932 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1933 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1937 /* check configuration for vmdb+dcb mode */
1938 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1939 const struct rte_eth_vmdq_dcb_conf *conf;
1941 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1942 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1943 IXGBE_VMDQ_DCB_NB_QUEUES);
1946 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1947 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1948 conf->nb_queue_pools == ETH_32_POOLS)) {
1949 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1950 " nb_queue_pools must be %d or %d.",
1951 ETH_16_POOLS, ETH_32_POOLS);
1955 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1956 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1958 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1959 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1960 IXGBE_VMDQ_DCB_NB_QUEUES);
1963 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1964 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1965 conf->nb_queue_pools == ETH_32_POOLS)) {
1966 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1967 " nb_queue_pools != %d and"
1968 " nb_queue_pools != %d.",
1969 ETH_16_POOLS, ETH_32_POOLS);
1974 /* For DCB mode check our configuration before we go further */
1975 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1976 const struct rte_eth_dcb_rx_conf *conf;
1978 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1979 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1980 IXGBE_DCB_NB_QUEUES);
1983 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1984 if (!(conf->nb_tcs == ETH_4_TCS ||
1985 conf->nb_tcs == ETH_8_TCS)) {
1986 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1987 " and nb_tcs != %d.",
1988 ETH_4_TCS, ETH_8_TCS);
1993 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1994 const struct rte_eth_dcb_tx_conf *conf;
1996 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1997 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1998 IXGBE_DCB_NB_QUEUES);
2001 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2002 if (!(conf->nb_tcs == ETH_4_TCS ||
2003 conf->nb_tcs == ETH_8_TCS)) {
2004 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2005 " and nb_tcs != %d.",
2006 ETH_4_TCS, ETH_8_TCS);
2012 * When DCB/VT is off, maximum number of queues changes,
2013 * except for 82598EB, which remains constant.
2015 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2016 hw->mac.type != ixgbe_mac_82598EB) {
2017 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2019 "Neither VT nor DCB are enabled, "
2021 IXGBE_NONE_MODE_TX_NB_QUEUES);
2030 ixgbe_dev_configure(struct rte_eth_dev *dev)
2032 struct ixgbe_interrupt *intr =
2033 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2034 struct ixgbe_adapter *adapter =
2035 (struct ixgbe_adapter *)dev->data->dev_private;
2038 PMD_INIT_FUNC_TRACE();
2039 /* multipe queue mode checking */
2040 ret = ixgbe_check_mq_mode(dev);
2042 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2047 /* set flag to update link status after init */
2048 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2051 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2052 * allocation or vector Rx preconditions we will reset it.
2054 adapter->rx_bulk_alloc_allowed = true;
2055 adapter->rx_vec_allowed = true;
2061 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2063 struct ixgbe_hw *hw =
2064 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065 struct ixgbe_interrupt *intr =
2066 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2069 /* only set up it on X550EM_X */
2070 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2071 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2072 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2073 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2074 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2075 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2080 * Configure device link speed and setup link.
2081 * It returns 0 on success.
2084 ixgbe_dev_start(struct rte_eth_dev *dev)
2086 struct ixgbe_hw *hw =
2087 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088 struct ixgbe_vf_info *vfinfo =
2089 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2090 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2091 uint32_t intr_vector = 0;
2092 int err, link_up = 0, negotiate = 0;
2098 PMD_INIT_FUNC_TRACE();
2100 /* IXGBE devices don't support half duplex */
2101 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2102 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2103 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2104 dev->data->dev_conf.link_duplex,
2105 dev->data->port_id);
2109 /* disable uio/vfio intr/eventfd mapping */
2110 rte_intr_disable(intr_handle);
2113 hw->adapter_stopped = 0;
2114 ixgbe_stop_adapter(hw);
2116 /* reinitialize adapter
2117 * this calls reset and start */
2118 status = ixgbe_pf_reset_hw(hw);
2121 hw->mac.ops.start_hw(hw);
2122 hw->mac.get_link_status = true;
2124 /* configure PF module if SRIOV enabled */
2125 ixgbe_pf_host_configure(dev);
2127 ixgbe_dev_phy_intr_setup(dev);
2129 /* check and configure queue intr-vector mapping */
2130 if ((rte_intr_cap_multiple(intr_handle) ||
2131 !RTE_ETH_DEV_SRIOV(dev).active) &&
2132 dev->data->dev_conf.intr_conf.rxq != 0) {
2133 intr_vector = dev->data->nb_rx_queues;
2134 if (rte_intr_efd_enable(intr_handle, intr_vector))
2138 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2139 intr_handle->intr_vec =
2140 rte_zmalloc("intr_vec",
2141 dev->data->nb_rx_queues * sizeof(int), 0);
2142 if (intr_handle->intr_vec == NULL) {
2143 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2144 " intr_vec\n", dev->data->nb_rx_queues);
2149 /* confiugre msix for sleep until rx interrupt */
2150 ixgbe_configure_msix(dev);
2152 /* initialize transmission unit */
2153 ixgbe_dev_tx_init(dev);
2155 /* This can fail when allocating mbufs for descriptor rings */
2156 err = ixgbe_dev_rx_init(dev);
2158 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2162 err = ixgbe_dev_rxtx_start(dev);
2164 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2168 /* Skip link setup if loopback mode is enabled for 82599. */
2169 if (hw->mac.type == ixgbe_mac_82599EB &&
2170 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2171 goto skip_link_setup;
2173 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2174 err = hw->mac.ops.setup_sfp(hw);
2179 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2180 /* Turn on the copper */
2181 ixgbe_set_phy_power(hw, true);
2183 /* Turn on the laser */
2184 ixgbe_enable_tx_laser(hw);
2187 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2190 dev->data->dev_link.link_status = link_up;
2192 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2196 switch(dev->data->dev_conf.link_speed) {
2197 case ETH_LINK_SPEED_AUTONEG:
2198 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2199 IXGBE_LINK_SPEED_82599_AUTONEG :
2200 IXGBE_LINK_SPEED_82598_AUTONEG;
2202 case ETH_LINK_SPEED_100:
2204 * Invalid for 82598 but error will be detected by
2205 * ixgbe_setup_link()
2207 speed = IXGBE_LINK_SPEED_100_FULL;
2209 case ETH_LINK_SPEED_1000:
2210 speed = IXGBE_LINK_SPEED_1GB_FULL;
2212 case ETH_LINK_SPEED_10000:
2213 speed = IXGBE_LINK_SPEED_10GB_FULL;
2216 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2217 dev->data->dev_conf.link_speed,
2218 dev->data->port_id);
2222 err = ixgbe_setup_link(hw, speed, link_up);
2228 if (rte_intr_allow_others(intr_handle)) {
2229 /* check if lsc interrupt is enabled */
2230 if (dev->data->dev_conf.intr_conf.lsc != 0)
2231 ixgbe_dev_lsc_interrupt_setup(dev);
2233 rte_intr_callback_unregister(intr_handle,
2234 ixgbe_dev_interrupt_handler,
2236 if (dev->data->dev_conf.intr_conf.lsc != 0)
2237 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2238 " no intr multiplex\n");
2241 /* check if rxq interrupt is enabled */
2242 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2243 rte_intr_dp_is_en(intr_handle))
2244 ixgbe_dev_rxq_interrupt_setup(dev);
2246 /* enable uio/vfio intr/eventfd mapping */
2247 rte_intr_enable(intr_handle);
2249 /* resume enabled intr since hw reset */
2250 ixgbe_enable_intr(dev);
2252 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2253 ETH_VLAN_EXTEND_MASK;
2254 ixgbe_vlan_offload_set(dev, mask);
2256 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2257 /* Enable vlan filtering for VMDq */
2258 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2261 /* Configure DCB hw */
2262 ixgbe_configure_dcb(dev);
2264 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2265 err = ixgbe_fdir_configure(dev);
2270 /* Restore vf rate limit */
2271 if (vfinfo != NULL) {
2272 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2273 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2274 if (vfinfo[vf].tx_rate[idx] != 0)
2275 ixgbe_set_vf_rate_limit(dev, vf,
2276 vfinfo[vf].tx_rate[idx],
2280 ixgbe_restore_statistics_mapping(dev);
2285 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2286 ixgbe_dev_clear_queues(dev);
2291 * Stop device: disable rx and tx functions to allow for reconfiguring.
2294 ixgbe_dev_stop(struct rte_eth_dev *dev)
2296 struct rte_eth_link link;
2297 struct ixgbe_hw *hw =
2298 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2299 struct ixgbe_vf_info *vfinfo =
2300 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2301 struct ixgbe_filter_info *filter_info =
2302 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2303 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2304 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2307 PMD_INIT_FUNC_TRACE();
2309 /* disable interrupts */
2310 ixgbe_disable_intr(hw);
2313 ixgbe_pf_reset_hw(hw);
2314 hw->adapter_stopped = 0;
2317 ixgbe_stop_adapter(hw);
2319 for (vf = 0; vfinfo != NULL &&
2320 vf < dev->pci_dev->max_vfs; vf++)
2321 vfinfo[vf].clear_to_send = false;
2323 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2324 /* Turn off the copper */
2325 ixgbe_set_phy_power(hw, false);
2327 /* Turn off the laser */
2328 ixgbe_disable_tx_laser(hw);
2331 ixgbe_dev_clear_queues(dev);
2333 /* Clear stored conf */
2334 dev->data->scattered_rx = 0;
2337 /* Clear recorded link status */
2338 memset(&link, 0, sizeof(link));
2339 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2341 /* Remove all ntuple filters of the device */
2342 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2343 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2344 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2345 TAILQ_REMOVE(&filter_info->fivetuple_list,
2349 memset(filter_info->fivetuple_mask, 0,
2350 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2352 if (!rte_intr_allow_others(intr_handle))
2353 /* resume to the default handler */
2354 rte_intr_callback_register(intr_handle,
2355 ixgbe_dev_interrupt_handler,
2358 /* Clean datapath event and queue/vec mapping */
2359 rte_intr_efd_disable(intr_handle);
2360 if (intr_handle->intr_vec != NULL) {
2361 rte_free(intr_handle->intr_vec);
2362 intr_handle->intr_vec = NULL;
2367 * Set device link up: enable tx.
2370 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2372 struct ixgbe_hw *hw =
2373 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2374 if (hw->mac.type == ixgbe_mac_82599EB) {
2375 #ifdef RTE_NIC_BYPASS
2376 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2377 /* Not suported in bypass mode */
2378 PMD_INIT_LOG(ERR, "Set link up is not supported "
2379 "by device id 0x%x", hw->device_id);
2385 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2386 /* Turn on the copper */
2387 ixgbe_set_phy_power(hw, true);
2389 /* Turn on the laser */
2390 ixgbe_enable_tx_laser(hw);
2397 * Set device link down: disable tx.
2400 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2402 struct ixgbe_hw *hw =
2403 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404 if (hw->mac.type == ixgbe_mac_82599EB) {
2405 #ifdef RTE_NIC_BYPASS
2406 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2407 /* Not suported in bypass mode */
2408 PMD_INIT_LOG(ERR, "Set link down is not supported "
2409 "by device id 0x%x", hw->device_id);
2415 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2416 /* Turn off the copper */
2417 ixgbe_set_phy_power(hw, false);
2419 /* Turn off the laser */
2420 ixgbe_disable_tx_laser(hw);
2427 * Reest and stop device.
2430 ixgbe_dev_close(struct rte_eth_dev *dev)
2432 struct ixgbe_hw *hw =
2433 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435 PMD_INIT_FUNC_TRACE();
2437 ixgbe_pf_reset_hw(hw);
2439 ixgbe_dev_stop(dev);
2440 hw->adapter_stopped = 1;
2442 ixgbe_dev_free_queues(dev);
2444 ixgbe_disable_pcie_master(hw);
2446 /* reprogram the RAR[0] in case user changed it. */
2447 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2451 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2452 struct ixgbe_hw_stats *hw_stats,
2453 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2454 uint64_t *total_qprc, uint64_t *total_qprdc)
2456 uint32_t bprc, lxon, lxoff, total;
2457 uint32_t delta_gprc = 0;
2459 /* Workaround for RX byte count not including CRC bytes when CRC
2460 + * strip is enabled. CRC bytes are removed from counters when crc_strip
2463 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2464 IXGBE_HLREG0_RXCRCSTRP);
2466 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2467 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2468 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2469 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2471 for (i = 0; i < 8; i++) {
2473 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2474 /* global total per queue */
2475 hw_stats->mpc[i] += mp;
2476 /* Running comprehensive total for stats display */
2477 *total_missed_rx += hw_stats->mpc[i];
2478 if (hw->mac.type == ixgbe_mac_82598EB) {
2479 hw_stats->rnbc[i] +=
2480 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2481 hw_stats->pxonrxc[i] +=
2482 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2483 hw_stats->pxoffrxc[i] +=
2484 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2486 hw_stats->pxonrxc[i] +=
2487 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2488 hw_stats->pxoffrxc[i] +=
2489 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2490 hw_stats->pxon2offc[i] +=
2491 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2493 hw_stats->pxontxc[i] +=
2494 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2495 hw_stats->pxofftxc[i] +=
2496 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2498 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2499 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2500 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2501 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2503 delta_gprc += delta_qprc;
2505 hw_stats->qprc[i] += delta_qprc;
2506 hw_stats->qptc[i] += delta_qptc;
2508 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2509 hw_stats->qbrc[i] +=
2510 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2512 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2514 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2515 hw_stats->qbtc[i] +=
2516 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2518 hw_stats->qprdc[i] += delta_qprdc;
2519 *total_qprdc += hw_stats->qprdc[i];
2521 *total_qprc += hw_stats->qprc[i];
2522 *total_qbrc += hw_stats->qbrc[i];
2524 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2525 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2526 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2529 * An errata states that gprc actually counts good + missed packets:
2530 * Workaround to set gprc to summated queue packet receives
2532 hw_stats->gprc = *total_qprc;
2534 if (hw->mac.type != ixgbe_mac_82598EB) {
2535 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2536 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2537 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2538 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2539 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2540 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2541 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2542 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2544 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2545 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2546 /* 82598 only has a counter in the high register */
2547 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2548 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2549 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2551 uint64_t old_tpr = hw_stats->tpr;
2553 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2554 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2557 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2559 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2560 hw_stats->gptc += delta_gptc;
2561 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2562 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2565 * Workaround: mprc hardware is incorrectly counting
2566 * broadcasts, so for now we subtract those.
2568 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2569 hw_stats->bprc += bprc;
2570 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2571 if (hw->mac.type == ixgbe_mac_82598EB)
2572 hw_stats->mprc -= bprc;
2574 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2575 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2576 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2577 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2578 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2579 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2581 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2582 hw_stats->lxontxc += lxon;
2583 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2584 hw_stats->lxofftxc += lxoff;
2585 total = lxon + lxoff;
2587 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2588 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2589 hw_stats->gptc -= total;
2590 hw_stats->mptc -= total;
2591 hw_stats->ptc64 -= total;
2592 hw_stats->gotc -= total * ETHER_MIN_LEN;
2594 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2595 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2596 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2597 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2598 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2599 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2600 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2601 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2602 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2603 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2604 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2605 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2606 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2607 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2608 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2609 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2610 /* Only read FCOE on 82599 */
2611 if (hw->mac.type != ixgbe_mac_82598EB) {
2612 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2613 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2614 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2615 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2616 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2619 /* Flow Director Stats registers */
2620 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2621 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2625 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2628 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2630 struct ixgbe_hw *hw =
2631 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632 struct ixgbe_hw_stats *hw_stats =
2633 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2634 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2637 total_missed_rx = 0;
2642 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2643 &total_qprc, &total_qprdc);
2648 /* Fill out the rte_eth_stats statistics structure */
2649 stats->ipackets = total_qprc;
2650 stats->ibytes = total_qbrc;
2651 stats->opackets = hw_stats->gptc;
2652 stats->obytes = hw_stats->gotc;
2654 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2655 stats->q_ipackets[i] = hw_stats->qprc[i];
2656 stats->q_opackets[i] = hw_stats->qptc[i];
2657 stats->q_ibytes[i] = hw_stats->qbrc[i];
2658 stats->q_obytes[i] = hw_stats->qbtc[i];
2659 stats->q_errors[i] = hw_stats->qprdc[i];
2663 stats->imissed = total_missed_rx;
2664 stats->ierrors = hw_stats->crcerrs +
2680 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2682 struct ixgbe_hw_stats *stats =
2683 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2685 /* HW registers are cleared on read */
2686 ixgbe_dev_stats_get(dev, NULL);
2688 /* Reset software totals */
2689 memset(stats, 0, sizeof(*stats));
2692 /* This function calculates the number of xstats based on the current config */
2694 ixgbe_xstats_calc_num(void) {
2695 return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2696 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2700 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2703 struct ixgbe_hw *hw =
2704 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2705 struct ixgbe_hw_stats *hw_stats =
2706 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2707 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2708 unsigned i, stat, count = 0;
2710 count = ixgbe_xstats_calc_num();
2715 total_missed_rx = 0;
2720 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2721 &total_qprc, &total_qprdc);
2723 /* If this is a reset xstats is NULL, and we have cleared the
2724 * registers by reading them.
2729 /* Extended stats from ixgbe_hw_stats */
2731 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2732 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2733 rte_ixgbe_stats_strings[i].name);
2734 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2735 rte_ixgbe_stats_strings[i].offset);
2739 /* RX Priority Stats */
2740 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2741 for (i = 0; i < 8; i++) {
2742 snprintf(xstats[count].name, sizeof(xstats[count].name),
2743 "rx_priority%u_%s", i,
2744 rte_ixgbe_rxq_strings[stat].name);
2745 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2746 rte_ixgbe_rxq_strings[stat].offset +
2747 (sizeof(uint64_t) * i));
2752 /* TX Priority Stats */
2753 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2754 for (i = 0; i < 8; i++) {
2755 snprintf(xstats[count].name, sizeof(xstats[count].name),
2756 "tx_priority%u_%s", i,
2757 rte_ixgbe_txq_strings[stat].name);
2758 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2759 rte_ixgbe_txq_strings[stat].offset +
2760 (sizeof(uint64_t) * i));
2769 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2771 struct ixgbe_hw_stats *stats =
2772 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2774 unsigned count = ixgbe_xstats_calc_num();
2776 /* HW registers are cleared on read */
2777 ixgbe_dev_xstats_get(dev, NULL, count);
2779 /* Reset software totals */
2780 memset(stats, 0, sizeof(*stats));
2784 ixgbevf_update_stats(struct rte_eth_dev *dev)
2786 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2787 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2788 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2790 /* Good Rx packet, include VF loopback */
2791 UPDATE_VF_STAT(IXGBE_VFGPRC,
2792 hw_stats->last_vfgprc, hw_stats->vfgprc);
2794 /* Good Rx octets, include VF loopback */
2795 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2796 hw_stats->last_vfgorc, hw_stats->vfgorc);
2798 /* Good Tx packet, include VF loopback */
2799 UPDATE_VF_STAT(IXGBE_VFGPTC,
2800 hw_stats->last_vfgptc, hw_stats->vfgptc);
2802 /* Good Tx octets, include VF loopback */
2803 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2804 hw_stats->last_vfgotc, hw_stats->vfgotc);
2806 /* Rx Multicst Packet */
2807 UPDATE_VF_STAT(IXGBE_VFMPRC,
2808 hw_stats->last_vfmprc, hw_stats->vfmprc);
2812 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2815 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2816 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2819 if (n < IXGBEVF_NB_XSTATS)
2820 return IXGBEVF_NB_XSTATS;
2822 ixgbevf_update_stats(dev);
2827 /* Extended stats */
2828 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2829 snprintf(xstats[i].name, sizeof(xstats[i].name),
2830 "%s", rte_ixgbevf_stats_strings[i].name);
2831 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2832 rte_ixgbevf_stats_strings[i].offset);
2835 return IXGBEVF_NB_XSTATS;
2839 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2841 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2842 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2844 ixgbevf_update_stats(dev);
2849 stats->ipackets = hw_stats->vfgprc;
2850 stats->ibytes = hw_stats->vfgorc;
2851 stats->opackets = hw_stats->vfgptc;
2852 stats->obytes = hw_stats->vfgotc;
2853 stats->imcasts = hw_stats->vfmprc;
2854 /* stats->imcasts should be removed as imcasts is deprecated */
2858 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2860 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2861 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2863 /* Sync HW register to the last stats */
2864 ixgbevf_dev_stats_get(dev, NULL);
2866 /* reset HW current stats*/
2867 hw_stats->vfgprc = 0;
2868 hw_stats->vfgorc = 0;
2869 hw_stats->vfgptc = 0;
2870 hw_stats->vfgotc = 0;
2871 hw_stats->vfmprc = 0;
2876 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2878 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2879 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2881 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2882 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2883 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
2885 * When DCB/VT is off, maximum number of queues changes,
2886 * except for 82598EB, which remains constant.
2888 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2889 hw->mac.type != ixgbe_mac_82598EB)
2890 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
2892 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2893 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2894 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2895 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2896 dev_info->max_vfs = dev->pci_dev->max_vfs;
2897 if (hw->mac.type == ixgbe_mac_82598EB)
2898 dev_info->max_vmdq_pools = ETH_16_POOLS;
2900 dev_info->max_vmdq_pools = ETH_64_POOLS;
2901 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2902 dev_info->rx_offload_capa =
2903 DEV_RX_OFFLOAD_VLAN_STRIP |
2904 DEV_RX_OFFLOAD_IPV4_CKSUM |
2905 DEV_RX_OFFLOAD_UDP_CKSUM |
2906 DEV_RX_OFFLOAD_TCP_CKSUM;
2909 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2912 if ((hw->mac.type == ixgbe_mac_82599EB ||
2913 hw->mac.type == ixgbe_mac_X540) &&
2914 !RTE_ETH_DEV_SRIOV(dev).active)
2915 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2917 if (hw->mac.type == ixgbe_mac_X550 ||
2918 hw->mac.type == ixgbe_mac_X550EM_x ||
2919 hw->mac.type == ixgbe_mac_X550EM_a)
2920 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2922 dev_info->tx_offload_capa =
2923 DEV_TX_OFFLOAD_VLAN_INSERT |
2924 DEV_TX_OFFLOAD_IPV4_CKSUM |
2925 DEV_TX_OFFLOAD_UDP_CKSUM |
2926 DEV_TX_OFFLOAD_TCP_CKSUM |
2927 DEV_TX_OFFLOAD_SCTP_CKSUM |
2928 DEV_TX_OFFLOAD_TCP_TSO;
2930 if (hw->mac.type == ixgbe_mac_X550 ||
2931 hw->mac.type == ixgbe_mac_X550EM_x ||
2932 hw->mac.type == ixgbe_mac_X550EM_a)
2933 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2935 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2937 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2938 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2939 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2941 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2945 dev_info->default_txconf = (struct rte_eth_txconf) {
2947 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2948 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2949 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2951 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2952 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2953 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2954 ETH_TXQ_FLAGS_NOOFFLOADS,
2957 dev_info->rx_desc_lim = rx_desc_lim;
2958 dev_info->tx_desc_lim = tx_desc_lim;
2960 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2961 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2962 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2965 static const uint32_t *
2966 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2968 static const uint32_t ptypes[] = {
2969 /* For non-vec functions,
2970 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
2971 * for vec functions,
2972 * refers to _recv_raw_pkts_vec().
2976 RTE_PTYPE_L3_IPV4_EXT,
2978 RTE_PTYPE_L3_IPV6_EXT,
2982 RTE_PTYPE_TUNNEL_IP,
2983 RTE_PTYPE_INNER_L3_IPV6,
2984 RTE_PTYPE_INNER_L3_IPV6_EXT,
2985 RTE_PTYPE_INNER_L4_TCP,
2986 RTE_PTYPE_INNER_L4_UDP,
2990 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
2991 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
2992 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
2993 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
2999 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3000 struct rte_eth_dev_info *dev_info)
3002 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3005 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3006 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3007 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3008 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3009 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3010 dev_info->max_vfs = dev->pci_dev->max_vfs;
3011 if (hw->mac.type == ixgbe_mac_82598EB)
3012 dev_info->max_vmdq_pools = ETH_16_POOLS;
3014 dev_info->max_vmdq_pools = ETH_64_POOLS;
3015 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3016 DEV_RX_OFFLOAD_IPV4_CKSUM |
3017 DEV_RX_OFFLOAD_UDP_CKSUM |
3018 DEV_RX_OFFLOAD_TCP_CKSUM;
3019 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3020 DEV_TX_OFFLOAD_IPV4_CKSUM |
3021 DEV_TX_OFFLOAD_UDP_CKSUM |
3022 DEV_TX_OFFLOAD_TCP_CKSUM |
3023 DEV_TX_OFFLOAD_SCTP_CKSUM |
3024 DEV_TX_OFFLOAD_TCP_TSO;
3026 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3028 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3029 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3030 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3032 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3036 dev_info->default_txconf = (struct rte_eth_txconf) {
3038 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3039 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3040 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3042 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3043 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3044 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3045 ETH_TXQ_FLAGS_NOOFFLOADS,
3048 dev_info->rx_desc_lim = rx_desc_lim;
3049 dev_info->tx_desc_lim = tx_desc_lim;
3052 /* return 0 means link status changed, -1 means not changed */
3054 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3056 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3057 struct rte_eth_link link, old;
3058 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3062 link.link_status = 0;
3063 link.link_speed = 0;
3064 link.link_duplex = 0;
3065 memset(&old, 0, sizeof(old));
3066 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3068 hw->mac.get_link_status = true;
3070 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3071 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3072 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3074 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3077 link.link_speed = ETH_LINK_SPEED_100;
3078 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3079 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3080 if (link.link_status == old.link_status)
3086 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3087 if (link.link_status == old.link_status)
3091 link.link_status = 1;
3092 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3094 switch (link_speed) {
3096 case IXGBE_LINK_SPEED_UNKNOWN:
3097 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3098 link.link_speed = ETH_LINK_SPEED_100;
3101 case IXGBE_LINK_SPEED_100_FULL:
3102 link.link_speed = ETH_LINK_SPEED_100;
3105 case IXGBE_LINK_SPEED_1GB_FULL:
3106 link.link_speed = ETH_LINK_SPEED_1000;
3109 case IXGBE_LINK_SPEED_10GB_FULL:
3110 link.link_speed = ETH_LINK_SPEED_10000;
3113 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3115 if (link.link_status == old.link_status)
3122 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3124 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3127 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3128 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3129 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3133 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3135 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3139 fctrl &= (~IXGBE_FCTRL_UPE);
3140 if (dev->data->all_multicast == 1)
3141 fctrl |= IXGBE_FCTRL_MPE;
3143 fctrl &= (~IXGBE_FCTRL_MPE);
3144 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3148 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3150 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3153 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3154 fctrl |= IXGBE_FCTRL_MPE;
3155 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3159 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3161 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3164 if (dev->data->promiscuous == 1)
3165 return; /* must remain in all_multicast mode */
3167 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3168 fctrl &= (~IXGBE_FCTRL_MPE);
3169 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3173 * It clears the interrupt causes and enables the interrupt.
3174 * It will be called once only during nic initialized.
3177 * Pointer to struct rte_eth_dev.
3180 * - On success, zero.
3181 * - On failure, a negative value.
3184 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3186 struct ixgbe_interrupt *intr =
3187 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3189 ixgbe_dev_link_status_print(dev);
3190 intr->mask |= IXGBE_EICR_LSC;
3196 * It clears the interrupt causes and enables the interrupt.
3197 * It will be called once only during nic initialized.
3200 * Pointer to struct rte_eth_dev.
3203 * - On success, zero.
3204 * - On failure, a negative value.
3207 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3209 struct ixgbe_interrupt *intr =
3210 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3212 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3218 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3221 * Pointer to struct rte_eth_dev.
3224 * - On success, zero.
3225 * - On failure, a negative value.
3228 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3231 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3232 struct ixgbe_interrupt *intr =
3233 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3235 /* clear all cause mask */
3236 ixgbe_disable_intr(hw);
3238 /* read-on-clear nic registers here */
3239 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3240 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3244 /* set flag for async link update */
3245 if (eicr & IXGBE_EICR_LSC)
3246 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3248 if (eicr & IXGBE_EICR_MAILBOX)
3249 intr->flags |= IXGBE_FLAG_MAILBOX;
3251 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3252 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3253 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3254 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3260 * It gets and then prints the link status.
3263 * Pointer to struct rte_eth_dev.
3266 * - On success, zero.
3267 * - On failure, a negative value.
3270 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3272 struct rte_eth_link link;
3274 memset(&link, 0, sizeof(link));
3275 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3276 if (link.link_status) {
3277 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3278 (int)(dev->data->port_id),
3279 (unsigned)link.link_speed,
3280 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3281 "full-duplex" : "half-duplex");
3283 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3284 (int)(dev->data->port_id));
3286 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3287 dev->pci_dev->addr.domain,
3288 dev->pci_dev->addr.bus,
3289 dev->pci_dev->addr.devid,
3290 dev->pci_dev->addr.function);
3294 * It executes link_update after knowing an interrupt occurred.
3297 * Pointer to struct rte_eth_dev.
3300 * - On success, zero.
3301 * - On failure, a negative value.
3304 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3306 struct ixgbe_interrupt *intr =
3307 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3309 struct rte_eth_link link;
3310 int intr_enable_delay = false;
3311 struct ixgbe_hw *hw =
3312 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3314 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3316 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3317 ixgbe_pf_mbx_process(dev);
3318 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3321 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3322 ixgbe_handle_lasi(hw);
3323 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3326 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3327 /* get the link status before link update, for predicting later */
3328 memset(&link, 0, sizeof(link));
3329 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3331 ixgbe_dev_link_update(dev, 0);
3334 if (!link.link_status)
3335 /* handle it 1 sec later, wait it being stable */
3336 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3337 /* likely to down */
3339 /* handle it 4 sec later, wait it being stable */
3340 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3342 ixgbe_dev_link_status_print(dev);
3344 intr_enable_delay = true;
3347 if (intr_enable_delay) {
3348 if (rte_eal_alarm_set(timeout * 1000,
3349 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3350 PMD_DRV_LOG(ERR, "Error setting alarm");
3352 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3353 ixgbe_enable_intr(dev);
3354 rte_intr_enable(&(dev->pci_dev->intr_handle));
3362 * Interrupt handler which shall be registered for alarm callback for delayed
3363 * handling specific interrupt to wait for the stable nic state. As the
3364 * NIC interrupt state is not stable for ixgbe after link is just down,
3365 * it needs to wait 4 seconds to get the stable status.
3368 * Pointer to interrupt handle.
3370 * The address of parameter (struct rte_eth_dev *) regsitered before.
3376 ixgbe_dev_interrupt_delayed_handler(void *param)
3378 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3379 struct ixgbe_interrupt *intr =
3380 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3381 struct ixgbe_hw *hw =
3382 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3385 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3386 if (eicr & IXGBE_EICR_MAILBOX)
3387 ixgbe_pf_mbx_process(dev);
3389 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3390 ixgbe_handle_lasi(hw);
3391 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3394 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3395 ixgbe_dev_link_update(dev, 0);
3396 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3397 ixgbe_dev_link_status_print(dev);
3398 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3401 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3402 ixgbe_enable_intr(dev);
3403 rte_intr_enable(&(dev->pci_dev->intr_handle));
3407 * Interrupt handler triggered by NIC for handling
3408 * specific interrupt.
3411 * Pointer to interrupt handle.
3413 * The address of parameter (struct rte_eth_dev *) regsitered before.
3419 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3422 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3424 ixgbe_dev_interrupt_get_status(dev);
3425 ixgbe_dev_interrupt_action(dev);
3429 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3431 struct ixgbe_hw *hw;
3433 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3434 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3438 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3440 struct ixgbe_hw *hw;
3442 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3443 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3447 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3449 struct ixgbe_hw *hw;
3455 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3457 fc_conf->pause_time = hw->fc.pause_time;
3458 fc_conf->high_water = hw->fc.high_water[0];
3459 fc_conf->low_water = hw->fc.low_water[0];
3460 fc_conf->send_xon = hw->fc.send_xon;
3461 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3464 * Return rx_pause status according to actual setting of
3467 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3468 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3474 * Return tx_pause status according to actual setting of
3477 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3478 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3483 if (rx_pause && tx_pause)
3484 fc_conf->mode = RTE_FC_FULL;
3486 fc_conf->mode = RTE_FC_RX_PAUSE;
3488 fc_conf->mode = RTE_FC_TX_PAUSE;
3490 fc_conf->mode = RTE_FC_NONE;
3496 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3498 struct ixgbe_hw *hw;
3500 uint32_t rx_buf_size;
3501 uint32_t max_high_water;
3503 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3510 PMD_INIT_FUNC_TRACE();
3512 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3513 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3514 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3517 * At least reserve one Ethernet frame for watermark
3518 * high_water/low_water in kilo bytes for ixgbe
3520 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3521 if ((fc_conf->high_water > max_high_water) ||
3522 (fc_conf->high_water < fc_conf->low_water)) {
3523 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3524 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3528 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3529 hw->fc.pause_time = fc_conf->pause_time;
3530 hw->fc.high_water[0] = fc_conf->high_water;
3531 hw->fc.low_water[0] = fc_conf->low_water;
3532 hw->fc.send_xon = fc_conf->send_xon;
3533 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3535 err = ixgbe_fc_enable(hw);
3537 /* Not negotiated is not an error case */
3538 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3540 /* check if we want to forward MAC frames - driver doesn't have native
3541 * capability to do that, so we'll write the registers ourselves */
3543 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3545 /* set or clear MFLCN.PMCF bit depending on configuration */
3546 if (fc_conf->mac_ctrl_frame_fwd != 0)
3547 mflcn |= IXGBE_MFLCN_PMCF;
3549 mflcn &= ~IXGBE_MFLCN_PMCF;
3551 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3552 IXGBE_WRITE_FLUSH(hw);
3557 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3562 * ixgbe_pfc_enable_generic - Enable flow control
3563 * @hw: pointer to hardware structure
3564 * @tc_num: traffic class number
3565 * Enable flow control according to the current settings.
3568 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3571 uint32_t mflcn_reg, fccfg_reg;
3573 uint32_t fcrtl, fcrth;
3577 /* Validate the water mark configuration */
3578 if (!hw->fc.pause_time) {
3579 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3583 /* Low water mark of zero causes XOFF floods */
3584 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3585 /* High/Low water can not be 0 */
3586 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3587 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3588 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3592 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3593 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3594 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3598 /* Negotiate the fc mode to use */
3599 ixgbe_fc_autoneg(hw);
3601 /* Disable any previous flow control settings */
3602 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3603 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3605 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3606 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3608 switch (hw->fc.current_mode) {
3611 * If the count of enabled RX Priority Flow control >1,
3612 * and the TX pause can not be disabled
3615 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3616 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3617 if (reg & IXGBE_FCRTH_FCEN)
3621 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3623 case ixgbe_fc_rx_pause:
3625 * Rx Flow control is enabled and Tx Flow control is
3626 * disabled by software override. Since there really
3627 * isn't a way to advertise that we are capable of RX
3628 * Pause ONLY, we will advertise that we support both
3629 * symmetric and asymmetric Rx PAUSE. Later, we will
3630 * disable the adapter's ability to send PAUSE frames.
3632 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3634 * If the count of enabled RX Priority Flow control >1,
3635 * and the TX pause can not be disabled
3638 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3639 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3640 if (reg & IXGBE_FCRTH_FCEN)
3644 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3646 case ixgbe_fc_tx_pause:
3648 * Tx Flow control is enabled, and Rx Flow control is
3649 * disabled by software override.
3651 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3654 /* Flow control (both Rx and Tx) is enabled by SW override. */
3655 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3656 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3659 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3660 ret_val = IXGBE_ERR_CONFIG;
3665 /* Set 802.3x based flow control settings. */
3666 mflcn_reg |= IXGBE_MFLCN_DPF;
3667 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3668 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3670 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3671 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3672 hw->fc.high_water[tc_num]) {
3673 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3674 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3675 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3677 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3679 * In order to prevent Tx hangs when the internal Tx
3680 * switch is enabled we must set the high water mark
3681 * to the maximum FCRTH value. This allows the Tx
3682 * switch to function even under heavy Rx workloads.
3684 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3686 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3688 /* Configure pause time (2 TCs per register) */
3689 reg = hw->fc.pause_time * 0x00010001;
3690 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3691 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3693 /* Configure flow control refresh threshold value */
3694 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3701 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3703 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3704 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3706 if (hw->mac.type != ixgbe_mac_82598EB) {
3707 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3713 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3716 uint32_t rx_buf_size;
3717 uint32_t max_high_water;
3719 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3720 struct ixgbe_hw *hw =
3721 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3722 struct ixgbe_dcb_config *dcb_config =
3723 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3725 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3732 PMD_INIT_FUNC_TRACE();
3734 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3735 tc_num = map[pfc_conf->priority];
3736 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3737 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3739 * At least reserve one Ethernet frame for watermark
3740 * high_water/low_water in kilo bytes for ixgbe
3742 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3743 if ((pfc_conf->fc.high_water > max_high_water) ||
3744 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3745 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3746 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3750 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3751 hw->fc.pause_time = pfc_conf->fc.pause_time;
3752 hw->fc.send_xon = pfc_conf->fc.send_xon;
3753 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3754 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3756 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3758 /* Not negotiated is not an error case */
3759 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3762 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3767 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3768 struct rte_eth_rss_reta_entry64 *reta_conf,
3771 uint16_t i, sp_reta_size;
3774 uint16_t idx, shift;
3775 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3778 PMD_INIT_FUNC_TRACE();
3780 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3781 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3786 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3787 if (reta_size != sp_reta_size) {
3788 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3789 "(%d) doesn't match the number hardware can supported "
3790 "(%d)\n", reta_size, sp_reta_size);
3794 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3795 idx = i / RTE_RETA_GROUP_SIZE;
3796 shift = i % RTE_RETA_GROUP_SIZE;
3797 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3801 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3802 if (mask == IXGBE_4_BIT_MASK)
3805 r = IXGBE_READ_REG(hw, reta_reg);
3806 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3807 if (mask & (0x1 << j))
3808 reta |= reta_conf[idx].reta[shift + j] <<
3811 reta |= r & (IXGBE_8_BIT_MASK <<
3814 IXGBE_WRITE_REG(hw, reta_reg, reta);
3821 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3822 struct rte_eth_rss_reta_entry64 *reta_conf,
3825 uint16_t i, sp_reta_size;
3828 uint16_t idx, shift;
3829 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3832 PMD_INIT_FUNC_TRACE();
3833 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3834 if (reta_size != sp_reta_size) {
3835 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3836 "(%d) doesn't match the number hardware can supported "
3837 "(%d)\n", reta_size, sp_reta_size);
3841 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3842 idx = i / RTE_RETA_GROUP_SIZE;
3843 shift = i % RTE_RETA_GROUP_SIZE;
3844 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3849 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3850 reta = IXGBE_READ_REG(hw, reta_reg);
3851 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3852 if (mask & (0x1 << j))
3853 reta_conf[idx].reta[shift + j] =
3854 ((reta >> (CHAR_BIT * j)) &
3863 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3864 uint32_t index, uint32_t pool)
3866 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3867 uint32_t enable_addr = 1;
3869 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3873 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3875 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3877 ixgbe_clear_rar(hw, index);
3881 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3883 ixgbe_remove_rar(dev, 0);
3885 ixgbe_add_rar(dev, addr, 0, 0);
3889 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3893 struct ixgbe_hw *hw;
3894 struct rte_eth_dev_info dev_info;
3895 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3897 ixgbe_dev_info_get(dev, &dev_info);
3899 /* check that mtu is within the allowed range */
3900 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3903 /* refuse mtu that requires the support of scattered packets when this
3904 * feature has not been enabled before. */
3905 if (!dev->data->scattered_rx &&
3906 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3907 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3910 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3911 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3913 /* switch to jumbo mode if needed */
3914 if (frame_size > ETHER_MAX_LEN) {
3915 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3916 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3918 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3919 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3921 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3923 /* update max frame size */
3924 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3926 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3927 maxfrs &= 0x0000FFFF;
3928 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3929 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3935 * Virtual Function operations
3938 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3940 PMD_INIT_FUNC_TRACE();
3942 /* Clear interrupt mask to stop from interrupts being generated */
3943 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3945 IXGBE_WRITE_FLUSH(hw);
3949 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3951 PMD_INIT_FUNC_TRACE();
3953 /* VF enable interrupt autoclean */
3954 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3955 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3956 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3958 IXGBE_WRITE_FLUSH(hw);
3962 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3964 struct rte_eth_conf* conf = &dev->data->dev_conf;
3965 struct ixgbe_adapter *adapter =
3966 (struct ixgbe_adapter *)dev->data->dev_private;
3968 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3969 dev->data->port_id);
3972 * VF has no ability to enable/disable HW CRC
3973 * Keep the persistent behavior the same as Host PF
3975 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3976 if (!conf->rxmode.hw_strip_crc) {
3977 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3978 conf->rxmode.hw_strip_crc = 1;
3981 if (conf->rxmode.hw_strip_crc) {
3982 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3983 conf->rxmode.hw_strip_crc = 0;
3988 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3989 * allocation or vector Rx preconditions we will reset it.
3991 adapter->rx_bulk_alloc_allowed = true;
3992 adapter->rx_vec_allowed = true;
3998 ixgbevf_dev_start(struct rte_eth_dev *dev)
4000 struct ixgbe_hw *hw =
4001 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4002 uint32_t intr_vector = 0;
4003 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4007 PMD_INIT_FUNC_TRACE();
4009 hw->mac.ops.reset_hw(hw);
4010 hw->mac.get_link_status = true;
4012 /* negotiate mailbox API version to use with the PF. */
4013 ixgbevf_negotiate_api(hw);
4015 ixgbevf_dev_tx_init(dev);
4017 /* This can fail when allocating mbufs for descriptor rings */
4018 err = ixgbevf_dev_rx_init(dev);
4020 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4021 ixgbe_dev_clear_queues(dev);
4026 ixgbevf_set_vfta_all(dev,1);
4029 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
4030 ETH_VLAN_EXTEND_MASK;
4031 ixgbevf_vlan_offload_set(dev, mask);
4033 ixgbevf_dev_rxtx_start(dev);
4035 /* check and configure queue intr-vector mapping */
4036 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4037 intr_vector = dev->data->nb_rx_queues;
4038 if (rte_intr_efd_enable(intr_handle, intr_vector))
4042 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4043 intr_handle->intr_vec =
4044 rte_zmalloc("intr_vec",
4045 dev->data->nb_rx_queues * sizeof(int), 0);
4046 if (intr_handle->intr_vec == NULL) {
4047 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4048 " intr_vec\n", dev->data->nb_rx_queues);
4052 ixgbevf_configure_msix(dev);
4054 rte_intr_enable(intr_handle);
4056 /* Re-enable interrupt for VF */
4057 ixgbevf_intr_enable(hw);
4063 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4065 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4066 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4068 PMD_INIT_FUNC_TRACE();
4070 hw->adapter_stopped = 1;
4071 ixgbe_stop_adapter(hw);
4074 * Clear what we set, but we still keep shadow_vfta to
4075 * restore after device starts
4077 ixgbevf_set_vfta_all(dev,0);
4079 /* Clear stored conf */
4080 dev->data->scattered_rx = 0;
4082 ixgbe_dev_clear_queues(dev);
4084 /* Clean datapath event and queue/vec mapping */
4085 rte_intr_efd_disable(intr_handle);
4086 if (intr_handle->intr_vec != NULL) {
4087 rte_free(intr_handle->intr_vec);
4088 intr_handle->intr_vec = NULL;
4093 ixgbevf_dev_close(struct rte_eth_dev *dev)
4095 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4097 PMD_INIT_FUNC_TRACE();
4101 ixgbevf_dev_stop(dev);
4103 ixgbe_dev_free_queues(dev);
4106 * Remove the VF MAC address ro ensure
4107 * that the VF traffic goes to the PF
4108 * after stop, close and detach of the VF
4110 ixgbevf_remove_mac_addr(dev, 0);
4113 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4115 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4116 struct ixgbe_vfta * shadow_vfta =
4117 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4118 int i = 0, j = 0, vfta = 0, mask = 1;
4120 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4121 vfta = shadow_vfta->vfta[i];
4124 for (j = 0; j < 32; j++){
4126 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4135 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4137 struct ixgbe_hw *hw =
4138 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4139 struct ixgbe_vfta * shadow_vfta =
4140 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4141 uint32_t vid_idx = 0;
4142 uint32_t vid_bit = 0;
4145 PMD_INIT_FUNC_TRACE();
4147 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4148 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4150 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4153 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4154 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4156 /* Save what we set and retore it after device reset */
4158 shadow_vfta->vfta[vid_idx] |= vid_bit;
4160 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4166 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4168 struct ixgbe_hw *hw =
4169 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4172 PMD_INIT_FUNC_TRACE();
4174 if (queue >= hw->mac.max_rx_queues)
4177 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4179 ctrl |= IXGBE_RXDCTL_VME;
4181 ctrl &= ~IXGBE_RXDCTL_VME;
4182 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4184 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4188 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4190 struct ixgbe_hw *hw =
4191 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4195 /* VF function only support hw strip feature, others are not support */
4196 if (mask & ETH_VLAN_STRIP_MASK) {
4197 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4199 for (i = 0; i < hw->mac.max_rx_queues; i++)
4200 ixgbevf_vlan_strip_queue_set(dev,i,on);
4205 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4209 /* we only need to do this if VMDq is enabled */
4210 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4211 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4212 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4220 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4222 uint32_t vector = 0;
4223 switch (hw->mac.mc_filter_type) {
4224 case 0: /* use bits [47:36] of the address */
4225 vector = ((uc_addr->addr_bytes[4] >> 4) |
4226 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4228 case 1: /* use bits [46:35] of the address */
4229 vector = ((uc_addr->addr_bytes[4] >> 3) |
4230 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4232 case 2: /* use bits [45:34] of the address */
4233 vector = ((uc_addr->addr_bytes[4] >> 2) |
4234 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4236 case 3: /* use bits [43:32] of the address */
4237 vector = ((uc_addr->addr_bytes[4]) |
4238 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4240 default: /* Invalid mc_filter_type */
4244 /* vector can only be 12-bits or boundary will be exceeded */
4250 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4258 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4259 const uint32_t ixgbe_uta_bit_shift = 5;
4260 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4261 const uint32_t bit1 = 0x1;
4263 struct ixgbe_hw *hw =
4264 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4265 struct ixgbe_uta_info *uta_info =
4266 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4268 /* The UTA table only exists on 82599 hardware and newer */
4269 if (hw->mac.type < ixgbe_mac_82599EB)
4272 vector = ixgbe_uta_vector(hw,mac_addr);
4273 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4274 uta_shift = vector & ixgbe_uta_bit_mask;
4276 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4280 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4282 uta_info->uta_in_use++;
4283 reg_val |= (bit1 << uta_shift);
4284 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4286 uta_info->uta_in_use--;
4287 reg_val &= ~(bit1 << uta_shift);
4288 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4291 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4293 if (uta_info->uta_in_use > 0)
4294 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4295 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4297 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4303 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4306 struct ixgbe_hw *hw =
4307 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4308 struct ixgbe_uta_info *uta_info =
4309 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4311 /* The UTA table only exists on 82599 hardware and newer */
4312 if (hw->mac.type < ixgbe_mac_82599EB)
4316 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4317 uta_info->uta_shadow[i] = ~0;
4318 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4321 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4322 uta_info->uta_shadow[i] = 0;
4323 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4331 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4333 uint32_t new_val = orig_val;
4335 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4336 new_val |= IXGBE_VMOLR_AUPE;
4337 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4338 new_val |= IXGBE_VMOLR_ROMPE;
4339 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4340 new_val |= IXGBE_VMOLR_ROPE;
4341 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4342 new_val |= IXGBE_VMOLR_BAM;
4343 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4344 new_val |= IXGBE_VMOLR_MPE;
4350 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4351 uint16_t rx_mask, uint8_t on)
4355 struct ixgbe_hw *hw =
4356 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4357 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4359 if (hw->mac.type == ixgbe_mac_82598EB) {
4360 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4361 " on 82599 hardware and newer");
4364 if (ixgbe_vmdq_mode_check(hw) < 0)
4367 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4374 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4380 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4384 const uint8_t bit1 = 0x1;
4386 struct ixgbe_hw *hw =
4387 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4389 if (ixgbe_vmdq_mode_check(hw) < 0)
4392 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4393 reg = IXGBE_READ_REG(hw, addr);
4401 IXGBE_WRITE_REG(hw, addr,reg);
4407 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4411 const uint8_t bit1 = 0x1;
4413 struct ixgbe_hw *hw =
4414 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4416 if (ixgbe_vmdq_mode_check(hw) < 0)
4419 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4420 reg = IXGBE_READ_REG(hw, addr);
4428 IXGBE_WRITE_REG(hw, addr,reg);
4434 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4435 uint64_t pool_mask, uint8_t vlan_on)
4439 struct ixgbe_hw *hw =
4440 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4442 if (ixgbe_vmdq_mode_check(hw) < 0)
4444 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4445 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4446 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4454 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4455 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4456 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4457 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4458 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4459 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4460 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4463 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4464 struct rte_eth_mirror_conf *mirror_conf,
4465 uint8_t rule_id, uint8_t on)
4467 uint32_t mr_ctl,vlvf;
4468 uint32_t mp_lsb = 0;
4469 uint32_t mv_msb = 0;
4470 uint32_t mv_lsb = 0;
4471 uint32_t mp_msb = 0;
4474 uint64_t vlan_mask = 0;
4476 const uint8_t pool_mask_offset = 32;
4477 const uint8_t vlan_mask_offset = 32;
4478 const uint8_t dst_pool_offset = 8;
4479 const uint8_t rule_mr_offset = 4;
4480 const uint8_t mirror_rule_mask= 0x0F;
4482 struct ixgbe_mirror_info *mr_info =
4483 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4484 struct ixgbe_hw *hw =
4485 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4486 uint8_t mirror_type = 0;
4488 if (ixgbe_vmdq_mode_check(hw) < 0)
4491 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4494 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4495 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4496 mirror_conf->rule_type);
4500 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4501 mirror_type |= IXGBE_MRCTL_VLME;
4502 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4503 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4504 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4505 /* search vlan id related pool vlan filter index */
4506 reg_index = ixgbe_find_vlvf_slot(hw,
4507 mirror_conf->vlan.vlan_id[i]);
4510 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4511 if ((vlvf & IXGBE_VLVF_VIEN) &&
4512 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4513 mirror_conf->vlan.vlan_id[i]))
4514 vlan_mask |= (1ULL << reg_index);
4521 mv_lsb = vlan_mask & 0xFFFFFFFF;
4522 mv_msb = vlan_mask >> vlan_mask_offset;
4524 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4525 mirror_conf->vlan.vlan_mask;
4526 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4527 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4528 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4529 mirror_conf->vlan.vlan_id[i];
4534 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4535 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4536 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4541 * if enable pool mirror, write related pool mask register,if disable
4542 * pool mirror, clear PFMRVM register
4544 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4545 mirror_type |= IXGBE_MRCTL_VPME;
4547 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4548 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4549 mr_info->mr_conf[rule_id].pool_mask =
4550 mirror_conf->pool_mask;
4555 mr_info->mr_conf[rule_id].pool_mask = 0;
4558 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4559 mirror_type |= IXGBE_MRCTL_UPME;
4560 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4561 mirror_type |= IXGBE_MRCTL_DPME;
4563 /* read mirror control register and recalculate it */
4564 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4567 mr_ctl |= mirror_type;
4568 mr_ctl &= mirror_rule_mask;
4569 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4571 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4573 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4574 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4576 /* write mirrror control register */
4577 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4579 /* write pool mirrror control register */
4580 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4581 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4582 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4585 /* write VLAN mirrror control register */
4586 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4587 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4588 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4596 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4599 uint32_t lsb_val = 0;
4600 uint32_t msb_val = 0;
4601 const uint8_t rule_mr_offset = 4;
4603 struct ixgbe_hw *hw =
4604 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4605 struct ixgbe_mirror_info *mr_info =
4606 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4608 if (ixgbe_vmdq_mode_check(hw) < 0)
4611 memset(&mr_info->mr_conf[rule_id], 0,
4612 sizeof(struct rte_eth_mirror_conf));
4614 /* clear PFVMCTL register */
4615 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4617 /* clear pool mask register */
4618 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4619 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4621 /* clear vlan mask register */
4622 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4623 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4629 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4632 struct ixgbe_hw *hw =
4633 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4635 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4636 mask |= (1 << IXGBE_MISC_VEC_ID);
4637 RTE_SET_USED(queue_id);
4638 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4640 rte_intr_enable(&dev->pci_dev->intr_handle);
4646 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4649 struct ixgbe_hw *hw =
4650 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4652 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4653 mask &= ~(1 << IXGBE_MISC_VEC_ID);
4654 RTE_SET_USED(queue_id);
4655 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4661 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4664 struct ixgbe_hw *hw =
4665 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4666 struct ixgbe_interrupt *intr =
4667 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4669 if (queue_id < 16) {
4670 ixgbe_disable_intr(hw);
4671 intr->mask |= (1 << queue_id);
4672 ixgbe_enable_intr(dev);
4673 } else if (queue_id < 32) {
4674 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4675 mask &= (1 << queue_id);
4676 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4677 } else if (queue_id < 64) {
4678 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4679 mask &= (1 << (queue_id - 32));
4680 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4682 rte_intr_enable(&dev->pci_dev->intr_handle);
4688 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4691 struct ixgbe_hw *hw =
4692 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4693 struct ixgbe_interrupt *intr =
4694 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4696 if (queue_id < 16) {
4697 ixgbe_disable_intr(hw);
4698 intr->mask &= ~(1 << queue_id);
4699 ixgbe_enable_intr(dev);
4700 } else if (queue_id < 32) {
4701 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4702 mask &= ~(1 << queue_id);
4703 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4704 } else if (queue_id < 64) {
4705 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4706 mask &= ~(1 << (queue_id - 32));
4707 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4714 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4715 uint8_t queue, uint8_t msix_vector)
4719 if (direction == -1) {
4721 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4722 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4725 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4727 /* rx or tx cause */
4728 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4729 idx = ((16 * (queue & 1)) + (8 * direction));
4730 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4731 tmp &= ~(0xFF << idx);
4732 tmp |= (msix_vector << idx);
4733 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4738 * set the IVAR registers, mapping interrupt causes to vectors
4740 * pointer to ixgbe_hw struct
4742 * 0 for Rx, 1 for Tx, -1 for other causes
4744 * queue to map the corresponding interrupt to
4746 * the vector to map to the corresponding queue
4749 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4750 uint8_t queue, uint8_t msix_vector)
4754 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4755 if (hw->mac.type == ixgbe_mac_82598EB) {
4756 if (direction == -1)
4758 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4759 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4760 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4761 tmp |= (msix_vector << (8 * (queue & 0x3)));
4762 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4763 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4764 (hw->mac.type == ixgbe_mac_X540)) {
4765 if (direction == -1) {
4767 idx = ((queue & 1) * 8);
4768 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4769 tmp &= ~(0xFF << idx);
4770 tmp |= (msix_vector << idx);
4771 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4773 /* rx or tx causes */
4774 idx = ((16 * (queue & 1)) + (8 * direction));
4775 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4776 tmp &= ~(0xFF << idx);
4777 tmp |= (msix_vector << idx);
4778 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4784 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4786 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4787 struct ixgbe_hw *hw =
4788 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4790 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4792 /* won't configure msix register if no mapping is done
4793 * between intr vector and event fd.
4795 if (!rte_intr_dp_is_en(intr_handle))
4798 /* Configure all RX queues of VF */
4799 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4800 /* Force all queue use vector 0,
4801 * as IXGBE_VF_MAXMSIVECOTR = 1
4803 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4804 intr_handle->intr_vec[q_idx] = vector_idx;
4807 /* Configure VF other cause ivar */
4808 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4812 * Sets up the hardware to properly generate MSI-X interrupts
4814 * board private structure
4817 ixgbe_configure_msix(struct rte_eth_dev *dev)
4819 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4820 struct ixgbe_hw *hw =
4821 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4822 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4823 uint32_t vec = IXGBE_MISC_VEC_ID;
4827 /* won't configure msix register if no mapping is done
4828 * between intr vector and event fd
4830 if (!rte_intr_dp_is_en(intr_handle))
4833 if (rte_intr_allow_others(intr_handle))
4834 vec = base = IXGBE_RX_VEC_START;
4836 /* setup GPIE for MSI-x mode */
4837 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4838 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4839 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4840 /* auto clearing and auto setting corresponding bits in EIMS
4841 * when MSI-X interrupt is triggered
4843 if (hw->mac.type == ixgbe_mac_82598EB) {
4844 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4846 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4847 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4849 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4851 /* Populate the IVAR table and set the ITR values to the
4852 * corresponding register.
4854 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4856 /* by default, 1:1 mapping */
4857 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4858 intr_handle->intr_vec[queue_id] = vec;
4859 if (vec < base + intr_handle->nb_efd - 1)
4863 switch (hw->mac.type) {
4864 case ixgbe_mac_82598EB:
4865 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4868 case ixgbe_mac_82599EB:
4869 case ixgbe_mac_X540:
4870 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4875 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4876 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4878 /* set up to autoclear timer, and the vectors */
4879 mask = IXGBE_EIMS_ENABLE_MASK;
4880 mask &= ~(IXGBE_EIMS_OTHER |
4881 IXGBE_EIMS_MAILBOX |
4884 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4887 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4888 uint16_t queue_idx, uint16_t tx_rate)
4890 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4891 uint32_t rf_dec, rf_int;
4893 uint16_t link_speed = dev->data->dev_link.link_speed;
4895 if (queue_idx >= hw->mac.max_tx_queues)
4899 /* Calculate the rate factor values to set */
4900 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4901 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4902 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4904 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4905 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4906 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4907 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4913 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4914 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4917 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4918 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4919 IXGBE_MAX_JUMBO_FRAME_SIZE))
4920 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4921 IXGBE_MMW_SIZE_JUMBO_FRAME);
4923 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4924 IXGBE_MMW_SIZE_DEFAULT);
4926 /* Set RTTBCNRC of queue X */
4927 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4928 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4929 IXGBE_WRITE_FLUSH(hw);
4934 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4935 uint16_t tx_rate, uint64_t q_msk)
4937 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4938 struct ixgbe_vf_info *vfinfo =
4939 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4940 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4941 uint32_t queue_stride =
4942 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4943 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4944 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4945 uint16_t total_rate = 0;
4947 if (queue_end >= hw->mac.max_tx_queues)
4950 if (vfinfo != NULL) {
4951 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4954 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4956 total_rate += vfinfo[vf_idx].tx_rate[idx];
4961 /* Store tx_rate for this vf. */
4962 for (idx = 0; idx < nb_q_per_pool; idx++) {
4963 if (((uint64_t)0x1 << idx) & q_msk) {
4964 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4965 vfinfo[vf].tx_rate[idx] = tx_rate;
4966 total_rate += tx_rate;
4970 if (total_rate > dev->data->dev_link.link_speed) {
4972 * Reset stored TX rate of the VF if it causes exceed
4975 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4979 /* Set RTTBCNRC of each queue/pool for vf X */
4980 for (; queue_idx <= queue_end; queue_idx++) {
4982 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4990 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4991 __attribute__((unused)) uint32_t index,
4992 __attribute__((unused)) uint32_t pool)
4994 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4998 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4999 * operation. Trap this case to avoid exhausting the [very limited]
5000 * set of PF resources used to store VF MAC addresses.
5002 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5004 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5007 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5011 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5013 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5014 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5015 struct ether_addr *mac_addr;
5020 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5021 * not support the deletion of a given MAC address.
5022 * Instead, it imposes to delete all MAC addresses, then to add again
5023 * all MAC addresses with the exception of the one to be deleted.
5025 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5028 * Add again all MAC addresses, with the exception of the deleted one
5029 * and of the permanent MAC address.
5031 for (i = 0, mac_addr = dev->data->mac_addrs;
5032 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5033 /* Skip the deleted MAC address */
5036 /* Skip NULL MAC addresses */
5037 if (is_zero_ether_addr(mac_addr))
5039 /* Skip the permanent MAC address */
5040 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5042 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5045 "Adding again MAC address "
5046 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5048 mac_addr->addr_bytes[0],
5049 mac_addr->addr_bytes[1],
5050 mac_addr->addr_bytes[2],
5051 mac_addr->addr_bytes[3],
5052 mac_addr->addr_bytes[4],
5053 mac_addr->addr_bytes[5],
5059 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5061 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5063 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5066 #define MAC_TYPE_FILTER_SUP(type) do {\
5067 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5068 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5069 (type) != ixgbe_mac_X550EM_a)\
5074 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5075 struct rte_eth_syn_filter *filter,
5078 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5081 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5084 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5087 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5089 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5090 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5092 if (filter->hig_pri)
5093 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5095 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5097 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5099 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5101 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5102 IXGBE_WRITE_FLUSH(hw);
5107 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5108 struct rte_eth_syn_filter *filter)
5110 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5111 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5113 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5114 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5115 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5122 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5123 enum rte_filter_op filter_op,
5126 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5129 MAC_TYPE_FILTER_SUP(hw->mac.type);
5131 if (filter_op == RTE_ETH_FILTER_NOP)
5135 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5140 switch (filter_op) {
5141 case RTE_ETH_FILTER_ADD:
5142 ret = ixgbe_syn_filter_set(dev,
5143 (struct rte_eth_syn_filter *)arg,
5146 case RTE_ETH_FILTER_DELETE:
5147 ret = ixgbe_syn_filter_set(dev,
5148 (struct rte_eth_syn_filter *)arg,
5151 case RTE_ETH_FILTER_GET:
5152 ret = ixgbe_syn_filter_get(dev,
5153 (struct rte_eth_syn_filter *)arg);
5156 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5165 static inline enum ixgbe_5tuple_protocol
5166 convert_protocol_type(uint8_t protocol_value)
5168 if (protocol_value == IPPROTO_TCP)
5169 return IXGBE_FILTER_PROTOCOL_TCP;
5170 else if (protocol_value == IPPROTO_UDP)
5171 return IXGBE_FILTER_PROTOCOL_UDP;
5172 else if (protocol_value == IPPROTO_SCTP)
5173 return IXGBE_FILTER_PROTOCOL_SCTP;
5175 return IXGBE_FILTER_PROTOCOL_NONE;
5179 * add a 5tuple filter
5182 * dev: Pointer to struct rte_eth_dev.
5183 * index: the index the filter allocates.
5184 * filter: ponter to the filter that will be added.
5185 * rx_queue: the queue id the filter assigned to.
5188 * - On success, zero.
5189 * - On failure, a negative value.
5192 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5193 struct ixgbe_5tuple_filter *filter)
5195 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5196 struct ixgbe_filter_info *filter_info =
5197 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5199 uint32_t ftqf, sdpqf;
5200 uint32_t l34timir = 0;
5201 uint8_t mask = 0xff;
5204 * look for an unused 5tuple filter index,
5205 * and insert the filter to list.
5207 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5208 idx = i / (sizeof(uint32_t) * NBBY);
5209 shift = i % (sizeof(uint32_t) * NBBY);
5210 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5211 filter_info->fivetuple_mask[idx] |= 1 << shift;
5213 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5219 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5220 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5224 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5225 IXGBE_SDPQF_DSTPORT_SHIFT);
5226 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5228 ftqf = (uint32_t)(filter->filter_info.proto &
5229 IXGBE_FTQF_PROTOCOL_MASK);
5230 ftqf |= (uint32_t)((filter->filter_info.priority &
5231 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5232 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5233 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5234 if (filter->filter_info.dst_ip_mask == 0)
5235 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5236 if (filter->filter_info.src_port_mask == 0)
5237 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5238 if (filter->filter_info.dst_port_mask == 0)
5239 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5240 if (filter->filter_info.proto_mask == 0)
5241 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5242 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5243 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5244 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5246 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5247 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5248 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5249 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5251 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5252 l34timir |= (uint32_t)(filter->queue <<
5253 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5254 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5259 * remove a 5tuple filter
5262 * dev: Pointer to struct rte_eth_dev.
5263 * filter: the pointer of the filter will be removed.
5266 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5267 struct ixgbe_5tuple_filter *filter)
5269 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5270 struct ixgbe_filter_info *filter_info =
5271 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5272 uint16_t index = filter->index;
5274 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5275 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5276 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5279 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5280 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5281 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5282 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5283 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5287 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5289 struct ixgbe_hw *hw;
5290 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5292 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5294 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5297 /* refuse mtu that requires the support of scattered packets when this
5298 * feature has not been enabled before. */
5299 if (!dev->data->scattered_rx &&
5300 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5301 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5305 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5306 * request of the version 2.0 of the mailbox API.
5307 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5308 * of the mailbox API.
5309 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5310 * prior to 3.11.33 which contains the following change:
5311 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5313 ixgbevf_rlpml_set_vf(hw, max_frame);
5315 /* update max frame size */
5316 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5320 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5321 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5325 static inline struct ixgbe_5tuple_filter *
5326 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5327 struct ixgbe_5tuple_filter_info *key)
5329 struct ixgbe_5tuple_filter *it;
5331 TAILQ_FOREACH(it, filter_list, entries) {
5332 if (memcmp(key, &it->filter_info,
5333 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5340 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5342 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5343 struct ixgbe_5tuple_filter_info *filter_info)
5345 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5346 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5347 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5350 switch (filter->dst_ip_mask) {
5352 filter_info->dst_ip_mask = 0;
5353 filter_info->dst_ip = filter->dst_ip;
5356 filter_info->dst_ip_mask = 1;
5359 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5363 switch (filter->src_ip_mask) {
5365 filter_info->src_ip_mask = 0;
5366 filter_info->src_ip = filter->src_ip;
5369 filter_info->src_ip_mask = 1;
5372 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5376 switch (filter->dst_port_mask) {
5378 filter_info->dst_port_mask = 0;
5379 filter_info->dst_port = filter->dst_port;
5382 filter_info->dst_port_mask = 1;
5385 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5389 switch (filter->src_port_mask) {
5391 filter_info->src_port_mask = 0;
5392 filter_info->src_port = filter->src_port;
5395 filter_info->src_port_mask = 1;
5398 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5402 switch (filter->proto_mask) {
5404 filter_info->proto_mask = 0;
5405 filter_info->proto =
5406 convert_protocol_type(filter->proto);
5409 filter_info->proto_mask = 1;
5412 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5416 filter_info->priority = (uint8_t)filter->priority;
5421 * add or delete a ntuple filter
5424 * dev: Pointer to struct rte_eth_dev.
5425 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5426 * add: if true, add filter, if false, remove filter
5429 * - On success, zero.
5430 * - On failure, a negative value.
5433 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5434 struct rte_eth_ntuple_filter *ntuple_filter,
5437 struct ixgbe_filter_info *filter_info =
5438 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5439 struct ixgbe_5tuple_filter_info filter_5tuple;
5440 struct ixgbe_5tuple_filter *filter;
5443 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5444 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5448 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5449 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5453 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5455 if (filter != NULL && add) {
5456 PMD_DRV_LOG(ERR, "filter exists.");
5459 if (filter == NULL && !add) {
5460 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5465 filter = rte_zmalloc("ixgbe_5tuple_filter",
5466 sizeof(struct ixgbe_5tuple_filter), 0);
5469 (void)rte_memcpy(&filter->filter_info,
5471 sizeof(struct ixgbe_5tuple_filter_info));
5472 filter->queue = ntuple_filter->queue;
5473 ret = ixgbe_add_5tuple_filter(dev, filter);
5479 ixgbe_remove_5tuple_filter(dev, filter);
5485 * get a ntuple filter
5488 * dev: Pointer to struct rte_eth_dev.
5489 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5492 * - On success, zero.
5493 * - On failure, a negative value.
5496 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5497 struct rte_eth_ntuple_filter *ntuple_filter)
5499 struct ixgbe_filter_info *filter_info =
5500 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5501 struct ixgbe_5tuple_filter_info filter_5tuple;
5502 struct ixgbe_5tuple_filter *filter;
5505 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5506 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5510 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5511 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5515 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5517 if (filter == NULL) {
5518 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5521 ntuple_filter->queue = filter->queue;
5526 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5527 * @dev: pointer to rte_eth_dev structure
5528 * @filter_op:operation will be taken.
5529 * @arg: a pointer to specific structure corresponding to the filter_op
5532 * - On success, zero.
5533 * - On failure, a negative value.
5536 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5537 enum rte_filter_op filter_op,
5540 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5543 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5545 if (filter_op == RTE_ETH_FILTER_NOP)
5549 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5554 switch (filter_op) {
5555 case RTE_ETH_FILTER_ADD:
5556 ret = ixgbe_add_del_ntuple_filter(dev,
5557 (struct rte_eth_ntuple_filter *)arg,
5560 case RTE_ETH_FILTER_DELETE:
5561 ret = ixgbe_add_del_ntuple_filter(dev,
5562 (struct rte_eth_ntuple_filter *)arg,
5565 case RTE_ETH_FILTER_GET:
5566 ret = ixgbe_get_ntuple_filter(dev,
5567 (struct rte_eth_ntuple_filter *)arg);
5570 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5578 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5583 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5584 if (filter_info->ethertype_filters[i] == ethertype &&
5585 (filter_info->ethertype_mask & (1 << i)))
5592 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5597 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5598 if (!(filter_info->ethertype_mask & (1 << i))) {
5599 filter_info->ethertype_mask |= 1 << i;
5600 filter_info->ethertype_filters[i] = ethertype;
5608 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5611 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5613 filter_info->ethertype_mask &= ~(1 << idx);
5614 filter_info->ethertype_filters[idx] = 0;
5619 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5620 struct rte_eth_ethertype_filter *filter,
5623 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5624 struct ixgbe_filter_info *filter_info =
5625 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5630 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5633 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5634 filter->ether_type == ETHER_TYPE_IPv6) {
5635 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5636 " ethertype filter.", filter->ether_type);
5640 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5641 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5644 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5645 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5649 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5650 if (ret >= 0 && add) {
5651 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5652 filter->ether_type);
5655 if (ret < 0 && !add) {
5656 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5657 filter->ether_type);
5662 ret = ixgbe_ethertype_filter_insert(filter_info,
5663 filter->ether_type);
5665 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5668 etqf = IXGBE_ETQF_FILTER_EN;
5669 etqf |= (uint32_t)filter->ether_type;
5670 etqs |= (uint32_t)((filter->queue <<
5671 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5672 IXGBE_ETQS_RX_QUEUE);
5673 etqs |= IXGBE_ETQS_QUEUE_EN;
5675 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5679 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5680 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5681 IXGBE_WRITE_FLUSH(hw);
5687 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5688 struct rte_eth_ethertype_filter *filter)
5690 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5691 struct ixgbe_filter_info *filter_info =
5692 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5693 uint32_t etqf, etqs;
5696 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5698 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5699 filter->ether_type);
5703 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5704 if (etqf & IXGBE_ETQF_FILTER_EN) {
5705 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5706 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5708 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5709 IXGBE_ETQS_RX_QUEUE_SHIFT;
5716 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5717 * @dev: pointer to rte_eth_dev structure
5718 * @filter_op:operation will be taken.
5719 * @arg: a pointer to specific structure corresponding to the filter_op
5722 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5723 enum rte_filter_op filter_op,
5726 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5729 MAC_TYPE_FILTER_SUP(hw->mac.type);
5731 if (filter_op == RTE_ETH_FILTER_NOP)
5735 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5740 switch (filter_op) {
5741 case RTE_ETH_FILTER_ADD:
5742 ret = ixgbe_add_del_ethertype_filter(dev,
5743 (struct rte_eth_ethertype_filter *)arg,
5746 case RTE_ETH_FILTER_DELETE:
5747 ret = ixgbe_add_del_ethertype_filter(dev,
5748 (struct rte_eth_ethertype_filter *)arg,
5751 case RTE_ETH_FILTER_GET:
5752 ret = ixgbe_get_ethertype_filter(dev,
5753 (struct rte_eth_ethertype_filter *)arg);
5756 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5764 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5765 enum rte_filter_type filter_type,
5766 enum rte_filter_op filter_op,
5771 switch (filter_type) {
5772 case RTE_ETH_FILTER_NTUPLE:
5773 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5775 case RTE_ETH_FILTER_ETHERTYPE:
5776 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5778 case RTE_ETH_FILTER_SYN:
5779 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5781 case RTE_ETH_FILTER_FDIR:
5782 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5784 case RTE_ETH_FILTER_L2_TUNNEL:
5785 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5788 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5797 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5798 u8 **mc_addr_ptr, u32 *vmdq)
5803 mc_addr = *mc_addr_ptr;
5804 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5809 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5810 struct ether_addr *mc_addr_set,
5811 uint32_t nb_mc_addr)
5813 struct ixgbe_hw *hw;
5816 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5817 mc_addr_list = (u8 *)mc_addr_set;
5818 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5819 ixgbe_dev_addr_list_itr, TRUE);
5823 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5825 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5826 uint64_t systime_cycles;
5828 switch (hw->mac.type) {
5829 case ixgbe_mac_X550:
5830 case ixgbe_mac_X550EM_x:
5831 case ixgbe_mac_X550EM_a:
5832 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5833 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5834 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5838 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5839 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5843 return systime_cycles;
5847 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5849 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5850 uint64_t rx_tstamp_cycles;
5852 switch (hw->mac.type) {
5853 case ixgbe_mac_X550:
5854 case ixgbe_mac_X550EM_x:
5855 case ixgbe_mac_X550EM_a:
5856 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5857 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5858 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5862 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5863 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5864 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5868 return rx_tstamp_cycles;
5872 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5874 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5875 uint64_t tx_tstamp_cycles;
5877 switch (hw->mac.type) {
5878 case ixgbe_mac_X550:
5879 case ixgbe_mac_X550EM_x:
5880 case ixgbe_mac_X550EM_a:
5881 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5882 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5883 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5887 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5888 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5889 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5893 return tx_tstamp_cycles;
5897 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5899 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5900 struct ixgbe_adapter *adapter =
5901 (struct ixgbe_adapter *)dev->data->dev_private;
5902 struct rte_eth_link link;
5903 uint32_t incval = 0;
5906 /* Get current link speed. */
5907 memset(&link, 0, sizeof(link));
5908 ixgbe_dev_link_update(dev, 1);
5909 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5911 switch (link.link_speed) {
5912 case ETH_LINK_SPEED_100:
5913 incval = IXGBE_INCVAL_100;
5914 shift = IXGBE_INCVAL_SHIFT_100;
5916 case ETH_LINK_SPEED_1000:
5917 incval = IXGBE_INCVAL_1GB;
5918 shift = IXGBE_INCVAL_SHIFT_1GB;
5920 case ETH_LINK_SPEED_10000:
5922 incval = IXGBE_INCVAL_10GB;
5923 shift = IXGBE_INCVAL_SHIFT_10GB;
5927 switch (hw->mac.type) {
5928 case ixgbe_mac_X550:
5929 case ixgbe_mac_X550EM_x:
5930 case ixgbe_mac_X550EM_a:
5931 /* Independent of link speed. */
5933 /* Cycles read will be interpreted as ns. */
5936 case ixgbe_mac_X540:
5937 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5939 case ixgbe_mac_82599EB:
5940 incval >>= IXGBE_INCVAL_SHIFT_82599;
5941 shift -= IXGBE_INCVAL_SHIFT_82599;
5942 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5943 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5946 /* Not supported. */
5950 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5951 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5952 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5954 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5955 adapter->systime_tc.cc_shift = shift;
5956 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5958 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5959 adapter->rx_tstamp_tc.cc_shift = shift;
5960 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5962 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5963 adapter->tx_tstamp_tc.cc_shift = shift;
5964 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5968 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5970 struct ixgbe_adapter *adapter =
5971 (struct ixgbe_adapter *)dev->data->dev_private;
5973 adapter->systime_tc.nsec += delta;
5974 adapter->rx_tstamp_tc.nsec += delta;
5975 adapter->tx_tstamp_tc.nsec += delta;
5981 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5984 struct ixgbe_adapter *adapter =
5985 (struct ixgbe_adapter *)dev->data->dev_private;
5987 ns = rte_timespec_to_ns(ts);
5988 /* Set the timecounters to a new value. */
5989 adapter->systime_tc.nsec = ns;
5990 adapter->rx_tstamp_tc.nsec = ns;
5991 adapter->tx_tstamp_tc.nsec = ns;
5997 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5999 uint64_t ns, systime_cycles;
6000 struct ixgbe_adapter *adapter =
6001 (struct ixgbe_adapter *)dev->data->dev_private;
6003 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6004 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6005 *ts = rte_ns_to_timespec(ns);
6011 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6013 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6017 /* Stop the timesync system time. */
6018 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6019 /* Reset the timesync system time value. */
6020 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6021 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6023 /* Enable system time for platforms where it isn't on by default. */
6024 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6025 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6026 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6028 ixgbe_start_timecounters(dev);
6030 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6031 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6033 IXGBE_ETQF_FILTER_EN |
6036 /* Enable timestamping of received PTP packets. */
6037 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6038 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6039 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6041 /* Enable timestamping of transmitted PTP packets. */
6042 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6043 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6044 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6046 IXGBE_WRITE_FLUSH(hw);
6052 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6054 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6057 /* Disable timestamping of transmitted PTP packets. */
6058 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6059 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6060 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6062 /* Disable timestamping of received PTP packets. */
6063 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6064 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6065 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6067 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6068 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6070 /* Stop incrementating the System Time registers. */
6071 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6077 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6078 struct timespec *timestamp,
6079 uint32_t flags __rte_unused)
6081 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6082 struct ixgbe_adapter *adapter =
6083 (struct ixgbe_adapter *)dev->data->dev_private;
6084 uint32_t tsync_rxctl;
6085 uint64_t rx_tstamp_cycles;
6088 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6089 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6092 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6093 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6094 *timestamp = rte_ns_to_timespec(ns);
6100 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6101 struct timespec *timestamp)
6103 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6104 struct ixgbe_adapter *adapter =
6105 (struct ixgbe_adapter *)dev->data->dev_private;
6106 uint32_t tsync_txctl;
6107 uint64_t tx_tstamp_cycles;
6110 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6111 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6114 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6115 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6116 *timestamp = rte_ns_to_timespec(ns);
6122 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6124 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6127 const struct reg_info *reg_group;
6128 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6129 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6131 while ((reg_group = reg_set[g_ind++]))
6132 count += ixgbe_regs_group_count(reg_group);
6138 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6142 const struct reg_info *reg_group;
6144 while ((reg_group = ixgbevf_regs[g_ind++]))
6145 count += ixgbe_regs_group_count(reg_group);
6151 ixgbe_get_regs(struct rte_eth_dev *dev,
6152 struct rte_dev_reg_info *regs)
6154 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6155 uint32_t *data = regs->data;
6158 const struct reg_info *reg_group;
6159 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6160 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6162 /* Support only full register dump */
6163 if ((regs->length == 0) ||
6164 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6165 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6167 while ((reg_group = reg_set[g_ind++]))
6168 count += ixgbe_read_regs_group(dev, &data[count],
6177 ixgbevf_get_regs(struct rte_eth_dev *dev,
6178 struct rte_dev_reg_info *regs)
6180 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6181 uint32_t *data = regs->data;
6184 const struct reg_info *reg_group;
6186 /* Support only full register dump */
6187 if ((regs->length == 0) ||
6188 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6189 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6191 while ((reg_group = ixgbevf_regs[g_ind++]))
6192 count += ixgbe_read_regs_group(dev, &data[count],
6201 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6203 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6205 /* Return unit is byte count */
6206 return hw->eeprom.word_size * 2;
6210 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6211 struct rte_dev_eeprom_info *in_eeprom)
6213 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6214 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6215 uint16_t *data = in_eeprom->data;
6218 first = in_eeprom->offset >> 1;
6219 length = in_eeprom->length >> 1;
6220 if ((first > hw->eeprom.word_size) ||
6221 ((first + length) > hw->eeprom.word_size))
6224 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6226 return eeprom->ops.read_buffer(hw, first, length, data);
6230 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6231 struct rte_dev_eeprom_info *in_eeprom)
6233 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6234 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6235 uint16_t *data = in_eeprom->data;
6238 first = in_eeprom->offset >> 1;
6239 length = in_eeprom->length >> 1;
6240 if ((first > hw->eeprom.word_size) ||
6241 ((first + length) > hw->eeprom.word_size))
6244 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6246 return eeprom->ops.write_buffer(hw, first, length, data);
6250 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6252 case ixgbe_mac_X550:
6253 case ixgbe_mac_X550EM_x:
6254 case ixgbe_mac_X550EM_a:
6255 return ETH_RSS_RETA_SIZE_512;
6256 case ixgbe_mac_X550_vf:
6257 case ixgbe_mac_X550EM_x_vf:
6258 case ixgbe_mac_X550EM_a_vf:
6259 return ETH_RSS_RETA_SIZE_64;
6261 return ETH_RSS_RETA_SIZE_128;
6266 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6268 case ixgbe_mac_X550:
6269 case ixgbe_mac_X550EM_x:
6270 case ixgbe_mac_X550EM_a:
6271 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6272 return IXGBE_RETA(reta_idx >> 2);
6274 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6275 case ixgbe_mac_X550_vf:
6276 case ixgbe_mac_X550EM_x_vf:
6277 case ixgbe_mac_X550EM_a_vf:
6278 return IXGBE_VFRETA(reta_idx >> 2);
6280 return IXGBE_RETA(reta_idx >> 2);
6285 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6287 case ixgbe_mac_X550_vf:
6288 case ixgbe_mac_X550EM_x_vf:
6289 case ixgbe_mac_X550EM_a_vf:
6290 return IXGBE_VFMRQC;
6297 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6299 case ixgbe_mac_X550_vf:
6300 case ixgbe_mac_X550EM_x_vf:
6301 case ixgbe_mac_X550EM_a_vf:
6302 return IXGBE_VFRSSRK(i);
6304 return IXGBE_RSSRK(i);
6309 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6311 case ixgbe_mac_82599_vf:
6312 case ixgbe_mac_X540_vf:
6320 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6321 struct rte_eth_dcb_info *dcb_info)
6323 struct ixgbe_dcb_config *dcb_config =
6324 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6325 struct ixgbe_dcb_tc_config *tc;
6328 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6329 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6331 dcb_info->nb_tcs = 1;
6333 if (dcb_config->vt_mode) { /* vt is enabled*/
6334 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6335 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6336 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6337 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6338 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6339 for (j = 0; j < dcb_info->nb_tcs; j++) {
6340 dcb_info->tc_queue.tc_rxq[i][j].base =
6341 i * dcb_info->nb_tcs + j;
6342 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6343 dcb_info->tc_queue.tc_txq[i][j].base =
6344 i * dcb_info->nb_tcs + j;
6345 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6348 } else { /* vt is disabled*/
6349 struct rte_eth_dcb_rx_conf *rx_conf =
6350 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6351 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6352 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6353 if (dcb_info->nb_tcs == ETH_4_TCS) {
6354 for (i = 0; i < dcb_info->nb_tcs; i++) {
6355 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6356 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6358 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6359 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6360 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6361 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6362 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6363 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6364 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6365 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6366 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6367 for (i = 0; i < dcb_info->nb_tcs; i++) {
6368 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6369 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6371 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6372 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6373 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6374 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6375 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6376 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6377 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6378 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6379 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6380 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6381 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6382 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6383 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6384 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6385 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6386 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6389 for (i = 0; i < dcb_info->nb_tcs; i++) {
6390 tc = &dcb_config->tc_config[i];
6391 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6396 /* Update e-tag ether type */
6398 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6399 uint16_t ether_type)
6401 uint32_t etag_etype;
6403 if (hw->mac.type != ixgbe_mac_X550 &&
6404 hw->mac.type != ixgbe_mac_X550EM_x &&
6405 hw->mac.type != ixgbe_mac_X550EM_a) {
6409 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6410 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6411 etag_etype |= ether_type;
6412 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6413 IXGBE_WRITE_FLUSH(hw);
6418 /* Config l2 tunnel ether type */
6420 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6421 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6424 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6426 if (l2_tunnel == NULL)
6429 switch (l2_tunnel->l2_tunnel_type) {
6430 case RTE_L2_TUNNEL_TYPE_E_TAG:
6431 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6434 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6442 /* Enable e-tag tunnel */
6444 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6446 uint32_t etag_etype;
6448 if (hw->mac.type != ixgbe_mac_X550 &&
6449 hw->mac.type != ixgbe_mac_X550EM_x &&
6450 hw->mac.type != ixgbe_mac_X550EM_a) {
6454 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6455 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6456 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6457 IXGBE_WRITE_FLUSH(hw);
6462 /* Enable l2 tunnel */
6464 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6465 enum rte_eth_tunnel_type l2_tunnel_type)
6468 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6470 switch (l2_tunnel_type) {
6471 case RTE_L2_TUNNEL_TYPE_E_TAG:
6472 ret = ixgbe_e_tag_enable(hw);
6475 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6483 /* Disable e-tag tunnel */
6485 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6487 uint32_t etag_etype;
6489 if (hw->mac.type != ixgbe_mac_X550 &&
6490 hw->mac.type != ixgbe_mac_X550EM_x &&
6491 hw->mac.type != ixgbe_mac_X550EM_a) {
6495 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6496 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6497 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6498 IXGBE_WRITE_FLUSH(hw);
6503 /* Disable l2 tunnel */
6505 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6506 enum rte_eth_tunnel_type l2_tunnel_type)
6509 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6511 switch (l2_tunnel_type) {
6512 case RTE_L2_TUNNEL_TYPE_E_TAG:
6513 ret = ixgbe_e_tag_disable(hw);
6516 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6525 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6526 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6529 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6530 uint32_t i, rar_entries;
6531 uint32_t rar_low, rar_high;
6533 if (hw->mac.type != ixgbe_mac_X550 &&
6534 hw->mac.type != ixgbe_mac_X550EM_x &&
6535 hw->mac.type != ixgbe_mac_X550EM_a) {
6539 rar_entries = ixgbe_get_num_rx_addrs(hw);
6541 for (i = 1; i < rar_entries; i++) {
6542 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6543 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6544 if ((rar_high & IXGBE_RAH_AV) &&
6545 (rar_high & IXGBE_RAH_ADTYPE) &&
6546 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6547 l2_tunnel->tunnel_id)) {
6548 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6549 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6551 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6561 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6562 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6565 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6566 uint32_t i, rar_entries;
6567 uint32_t rar_low, rar_high;
6569 if (hw->mac.type != ixgbe_mac_X550 &&
6570 hw->mac.type != ixgbe_mac_X550EM_x &&
6571 hw->mac.type != ixgbe_mac_X550EM_a) {
6575 /* One entry for one tunnel. Try to remove potential existing entry. */
6576 ixgbe_e_tag_filter_del(dev, l2_tunnel);
6578 rar_entries = ixgbe_get_num_rx_addrs(hw);
6580 for (i = 1; i < rar_entries; i++) {
6581 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6582 if (rar_high & IXGBE_RAH_AV) {
6585 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6586 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6587 rar_low = l2_tunnel->tunnel_id;
6589 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6590 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6596 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6597 " Please remove a rule before adding a new one.");
6601 /* Add l2 tunnel filter */
6603 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6604 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6608 switch (l2_tunnel->l2_tunnel_type) {
6609 case RTE_L2_TUNNEL_TYPE_E_TAG:
6610 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6613 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6621 /* Delete l2 tunnel filter */
6623 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6624 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6628 switch (l2_tunnel->l2_tunnel_type) {
6629 case RTE_L2_TUNNEL_TYPE_E_TAG:
6630 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6633 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6642 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6643 * @dev: pointer to rte_eth_dev structure
6644 * @filter_op:operation will be taken.
6645 * @arg: a pointer to specific structure corresponding to the filter_op
6648 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6649 enum rte_filter_op filter_op,
6654 if (filter_op == RTE_ETH_FILTER_NOP)
6658 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6663 switch (filter_op) {
6664 case RTE_ETH_FILTER_ADD:
6665 ret = ixgbe_dev_l2_tunnel_filter_add
6667 (struct rte_eth_l2_tunnel_conf *)arg);
6669 case RTE_ETH_FILTER_DELETE:
6670 ret = ixgbe_dev_l2_tunnel_filter_del
6672 (struct rte_eth_l2_tunnel_conf *)arg);
6675 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6683 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6687 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6689 if (hw->mac.type != ixgbe_mac_X550 &&
6690 hw->mac.type != ixgbe_mac_X550EM_x &&
6691 hw->mac.type != ixgbe_mac_X550EM_a) {
6695 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6696 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6698 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6699 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6704 /* Enable l2 tunnel forwarding */
6706 ixgbe_dev_l2_tunnel_forwarding_enable
6707 (struct rte_eth_dev *dev,
6708 enum rte_eth_tunnel_type l2_tunnel_type)
6712 switch (l2_tunnel_type) {
6713 case RTE_L2_TUNNEL_TYPE_E_TAG:
6714 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6717 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6725 /* Disable l2 tunnel forwarding */
6727 ixgbe_dev_l2_tunnel_forwarding_disable
6728 (struct rte_eth_dev *dev,
6729 enum rte_eth_tunnel_type l2_tunnel_type)
6733 switch (l2_tunnel_type) {
6734 case RTE_L2_TUNNEL_TYPE_E_TAG:
6735 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6738 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6747 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6748 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6752 uint32_t vmtir, vmvir;
6753 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6755 if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6757 "VF id %u should be less than %u",
6759 dev->pci_dev->max_vfs);
6763 if (hw->mac.type != ixgbe_mac_X550 &&
6764 hw->mac.type != ixgbe_mac_X550EM_x &&
6765 hw->mac.type != ixgbe_mac_X550EM_a) {
6770 vmtir = l2_tunnel->tunnel_id;
6774 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6776 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6777 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6779 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6780 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6785 /* Enable l2 tunnel tag insertion */
6787 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6788 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6792 switch (l2_tunnel->l2_tunnel_type) {
6793 case RTE_L2_TUNNEL_TYPE_E_TAG:
6794 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6797 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6805 /* Disable l2 tunnel tag insertion */
6807 ixgbe_dev_l2_tunnel_insertion_disable
6808 (struct rte_eth_dev *dev,
6809 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6813 switch (l2_tunnel->l2_tunnel_type) {
6814 case RTE_L2_TUNNEL_TYPE_E_TAG:
6815 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6818 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6827 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6832 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6834 if (hw->mac.type != ixgbe_mac_X550 &&
6835 hw->mac.type != ixgbe_mac_X550EM_x &&
6836 hw->mac.type != ixgbe_mac_X550EM_a) {
6840 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6842 qde |= IXGBE_QDE_STRIP_TAG;
6844 qde &= ~IXGBE_QDE_STRIP_TAG;
6845 qde &= ~IXGBE_QDE_READ;
6846 qde |= IXGBE_QDE_WRITE;
6847 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6852 /* Enable l2 tunnel tag stripping */
6854 ixgbe_dev_l2_tunnel_stripping_enable
6855 (struct rte_eth_dev *dev,
6856 enum rte_eth_tunnel_type l2_tunnel_type)
6860 switch (l2_tunnel_type) {
6861 case RTE_L2_TUNNEL_TYPE_E_TAG:
6862 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6865 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6873 /* Disable l2 tunnel tag stripping */
6875 ixgbe_dev_l2_tunnel_stripping_disable
6876 (struct rte_eth_dev *dev,
6877 enum rte_eth_tunnel_type l2_tunnel_type)
6881 switch (l2_tunnel_type) {
6882 case RTE_L2_TUNNEL_TYPE_E_TAG:
6883 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6886 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6894 /* Enable/disable l2 tunnel offload functions */
6896 ixgbe_dev_l2_tunnel_offload_set
6897 (struct rte_eth_dev *dev,
6898 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6904 if (l2_tunnel == NULL)
6908 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6910 ret = ixgbe_dev_l2_tunnel_enable(
6912 l2_tunnel->l2_tunnel_type);
6914 ret = ixgbe_dev_l2_tunnel_disable(
6916 l2_tunnel->l2_tunnel_type);
6919 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6921 ret = ixgbe_dev_l2_tunnel_insertion_enable(
6925 ret = ixgbe_dev_l2_tunnel_insertion_disable(
6930 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6932 ret = ixgbe_dev_l2_tunnel_stripping_enable(
6934 l2_tunnel->l2_tunnel_type);
6936 ret = ixgbe_dev_l2_tunnel_stripping_disable(
6938 l2_tunnel->l2_tunnel_type);
6941 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6943 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6945 l2_tunnel->l2_tunnel_type);
6947 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6949 l2_tunnel->l2_tunnel_type);
6956 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6959 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6960 IXGBE_WRITE_FLUSH(hw);
6965 /* There's only one register for VxLAN UDP port.
6966 * So, we cannot add several ports. Will update it.
6969 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6973 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6977 return ixgbe_update_vxlan_port(hw, port);
6980 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6981 * UDP port, it must have a value.
6982 * So, will reset it to the original value 0.
6985 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6990 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6992 if (cur_port != port) {
6993 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6997 return ixgbe_update_vxlan_port(hw, 0);
7000 /* Add UDP tunneling port */
7002 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7003 struct rte_eth_udp_tunnel *udp_tunnel)
7006 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7008 if (hw->mac.type != ixgbe_mac_X550 &&
7009 hw->mac.type != ixgbe_mac_X550EM_x &&
7010 hw->mac.type != ixgbe_mac_X550EM_a) {
7014 if (udp_tunnel == NULL)
7017 switch (udp_tunnel->prot_type) {
7018 case RTE_TUNNEL_TYPE_VXLAN:
7019 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7022 case RTE_TUNNEL_TYPE_GENEVE:
7023 case RTE_TUNNEL_TYPE_TEREDO:
7024 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7029 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7037 /* Remove UDP tunneling port */
7039 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7040 struct rte_eth_udp_tunnel *udp_tunnel)
7043 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7045 if (hw->mac.type != ixgbe_mac_X550 &&
7046 hw->mac.type != ixgbe_mac_X550EM_x &&
7047 hw->mac.type != ixgbe_mac_X550EM_a) {
7051 if (udp_tunnel == NULL)
7054 switch (udp_tunnel->prot_type) {
7055 case RTE_TUNNEL_TYPE_VXLAN:
7056 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7058 case RTE_TUNNEL_TYPE_GENEVE:
7059 case RTE_TUNNEL_TYPE_TEREDO:
7060 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7064 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7072 /* ixgbevf_update_xcast_mode - Update Multicast mode
7073 * @hw: pointer to the HW structure
7074 * @netdev: pointer to net device structure
7075 * @xcast_mode: new multicast mode
7077 * Updates the Multicast Mode of VF.
7079 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7082 struct ixgbe_mbx_info *mbx = &hw->mbx;
7086 switch (hw->api_version) {
7087 case ixgbe_mbox_api_12:
7093 msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7094 msgbuf[1] = xcast_mode;
7096 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7100 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7104 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7105 if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7112 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7114 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7116 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7120 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7122 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7124 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7127 static struct rte_driver rte_ixgbe_driver = {
7129 .init = rte_ixgbe_pmd_init,
7132 static struct rte_driver rte_ixgbevf_driver = {
7134 .init = rte_ixgbevf_pmd_init,
7137 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7138 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);