drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 183         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 184 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 185         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 186 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 187                                              uint16_t queue_id,
 188                                              uint8_t stat_idx,
 189                                              uint8_t is_rx);
 190 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 191                                struct rte_eth_dev_info *dev_info);
 192 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 193 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 194                                  struct rte_eth_dev_info *dev_info);
 195 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 196
 197 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 198                 uint16_t vlan_id, int on);
 199 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 200                                enum rte_vlan_type vlan_type,
 201                                uint16_t tpid_id);
 202 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 203                 uint16_t queue, bool on);
 204 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 205                 int on);
 206 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 207 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 208 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 209 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 210 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 211
 212 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 213 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 214 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 217                                struct rte_eth_fc_conf *fc_conf);
 218 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 219                 struct rte_eth_pfc_conf *pfc_conf);
 220 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 221                         struct rte_eth_rss_reta_entry64 *reta_conf,
 222                         uint16_t reta_size);
 223 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 224                         struct rte_eth_rss_reta_entry64 *reta_conf,
 225                         uint16_t reta_size);
 226 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 230 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 231 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 232                 void *param);
 233 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 234 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 235                 uint32_t index, uint32_t pool);
 236 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 237 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 238                                            struct ether_addr *mac_addr);
 239 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 240
 241 /* For Virtual Function support */
 242 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 243 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 244 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 245 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 246 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 247 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 248 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 249 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 250 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 251                 struct rte_eth_stats *stats);
 252 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 253 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 254                 uint16_t vlan_id, int on);
 255 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 256                 uint16_t queue, int on);
 257 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 258 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 259 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 260                                             uint16_t queue_id);
 261 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 262                                              uint16_t queue_id);
 263 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 264                                  uint8_t queue, uint8_t msix_vector);
 265 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 267 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 268
 269 /* For Eth VMDQ APIs support */
 270 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 271                 ether_addr * mac_addr, uint8_t on);
 272 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 273 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 274                 uint16_t rx_mask, uint8_t on);
 275 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 276 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 277 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 278                 uint64_t pool_mask, uint8_t vlan_on);
 279 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 280                 struct rte_eth_mirror_conf *mirror_conf,
 281                 uint8_t rule_id, uint8_t on);
 282 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 283                 uint8_t rule_id);
 284 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 285                                           uint16_t queue_id);
 286 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 287                                            uint16_t queue_id);
 288 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 289                                uint8_t queue, uint8_t msix_vector);
 290 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 291
 292 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 293                 uint16_t queue_idx, uint16_t tx_rate);
 294 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 295                 uint16_t tx_rate, uint64_t q_msk);
 296
 297 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                  struct ether_addr *mac_addr,
 299                                  uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter,
 305                         bool add);
 306 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 307                         struct rte_eth_syn_filter *filter);
 308 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 309                         enum rte_filter_op filter_op,
 310                         void *arg);
 311 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 312                         struct ixgbe_5tuple_filter *filter);
 313 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 314                         struct ixgbe_5tuple_filter *filter);
 315 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter,
 317                         bool add);
 318 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 319                                 enum rte_filter_op filter_op,
 320                                 void *arg);
 321 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 322                         struct rte_eth_ntuple_filter *filter);
 323 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 324                         struct rte_eth_ethertype_filter *filter,
 325                         bool add);
 326 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 327                                 enum rte_filter_op filter_op,
 328                                 void *arg);
 329 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 330                         struct rte_eth_ethertype_filter *filter);
 331 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 332                      enum rte_filter_type filter_type,
 333                      enum rte_filter_op filter_op,
 334                      void *arg);
 335 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 336
 337 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 338                                       struct ether_addr *mc_addr_set,
 339                                       uint32_t nb_mc_addr);
 340 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 341                                    struct rte_eth_dcb_info *dcb_info);
 342
 343 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 344 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 345                             struct rte_dev_reg_info *regs);
 346 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 347 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 348                                 struct rte_dev_eeprom_info *eeprom);
 349 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351
 352 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 353 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 354                                 struct rte_dev_reg_info *regs);
 355
 356 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 357 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 358 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 359                                             struct timespec *timestamp,
 360                                             uint32_t flags);
 361 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 362                                             struct timespec *timestamp);
 363 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 364 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 365                                    struct timespec *timestamp);
 366 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 367                                    const struct timespec *timestamp);
 368
 369 static int ixgbe_dev_l2_tunnel_eth_type_conf
 370         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 371 static int ixgbe_dev_l2_tunnel_offload_set
 372         (struct rte_eth_dev *dev,
 373          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 374          uint32_t mask,
 375          uint8_t en);
 376 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 377                                              enum rte_filter_op filter_op,
 378                                              void *arg);
 379
 380 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 381                                          struct rte_eth_udp_tunnel *udp_tunnel);
 382 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 383                                          struct rte_eth_udp_tunnel *udp_tunnel);
 384
 385 /*
 386  * Define VF Stats MACRO for Non "cleared on read" register
 387  */
 388 #define UPDATE_VF_STAT(reg, last, cur)                          \
 389 {                                                               \
 390         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 391         cur += (latest - last) & UINT_MAX;                      \
 392         last = latest;                                          \
 393 }
 394
 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 396 {                                                                \
 397         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 398         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 399         u64 latest = ((new_msb << 32) | new_lsb);                \
 400         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 401         last = latest;                                           \
 402 }
 403
 404 #define IXGBE_SET_HWSTRIP(h, q) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (h)->bitmap[idx] |= 1 << bit;\
 408         } while (0)
 409
 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] &= ~(1 << bit);\
 414         } while (0)
 415
 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (r) = (h)->bitmap[idx] >> bit & 1;\
 420         } while (0)
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426
 427 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 428 #include "rte_pci_dev_ids.h"
 429
 430 { .vendor_id = 0, /* sentinel */ },
 431 };
 432
 433
 434 /*
 435  * The set of PCI devices this driver supports (for 82599 VF)
 436  */
 437 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 438
 439 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 440 #include "rte_pci_dev_ids.h"
 441 { .vendor_id = 0, /* sentinel */ },
 442
 443 };
 444
 445 static const struct rte_eth_desc_lim rx_desc_lim = {
 446         .nb_max = IXGBE_MAX_RING_DESC,
 447         .nb_min = IXGBE_MIN_RING_DESC,
 448         .nb_align = IXGBE_RXD_ALIGN,
 449 };
 450
 451 static const struct rte_eth_desc_lim tx_desc_lim = {
 452         .nb_max = IXGBE_MAX_RING_DESC,
 453         .nb_min = IXGBE_MIN_RING_DESC,
 454         .nb_align = IXGBE_TXD_ALIGN,
 455 };
 456
 457 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 458         .dev_configure        = ixgbe_dev_configure,
 459         .dev_start            = ixgbe_dev_start,
 460         .dev_stop             = ixgbe_dev_stop,
 461         .dev_set_link_up    = ixgbe_dev_set_link_up,
 462         .dev_set_link_down  = ixgbe_dev_set_link_down,
 463         .dev_close            = ixgbe_dev_close,
 464         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 465         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 466         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 467         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 468         .link_update          = ixgbe_dev_link_update,
 469         .stats_get            = ixgbe_dev_stats_get,
 470         .xstats_get           = ixgbe_dev_xstats_get,
 471         .stats_reset          = ixgbe_dev_stats_reset,
 472         .xstats_reset         = ixgbe_dev_xstats_reset,
 473         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 474         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 475         .dev_infos_get        = ixgbe_dev_info_get,
 476         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 477         .mtu_set              = ixgbe_dev_mtu_set,
 478         .vlan_filter_set      = ixgbe_vlan_filter_set,
 479         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 480         .vlan_offload_set     = ixgbe_vlan_offload_set,
 481         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 482         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 483         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 484         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 485         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 486         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 487         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 488         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 489         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 490         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 491         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 492         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 493         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 494         .dev_led_on           = ixgbe_dev_led_on,
 495         .dev_led_off          = ixgbe_dev_led_off,
 496         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 497         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 498         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 499         .mac_addr_add         = ixgbe_add_rar,
 500         .mac_addr_remove      = ixgbe_remove_rar,
 501         .mac_addr_set         = ixgbe_set_default_mac_addr,
 502         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 503         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 504         .mirror_rule_set      = ixgbe_mirror_rule_set,
 505         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 506         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 507         .set_vf_rx            = ixgbe_set_pool_rx,
 508         .set_vf_tx            = ixgbe_set_pool_tx,
 509         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 510         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 511         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 512         .reta_update          = ixgbe_dev_rss_reta_update,
 513         .reta_query           = ixgbe_dev_rss_reta_query,
 514 #ifdef RTE_NIC_BYPASS
 515         .bypass_init          = ixgbe_bypass_init,
 516         .bypass_state_set     = ixgbe_bypass_state_store,
 517         .bypass_state_show    = ixgbe_bypass_state_show,
 518         .bypass_event_set     = ixgbe_bypass_event_store,
 519         .bypass_event_show    = ixgbe_bypass_event_show,
 520         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 521         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 522         .bypass_ver_show      = ixgbe_bypass_ver_show,
 523         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 524 #endif /* RTE_NIC_BYPASS */
 525         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 526         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 527         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 528         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 529         .rxq_info_get         = ixgbe_rxq_info_get,
 530         .txq_info_get         = ixgbe_txq_info_get,
 531         .timesync_enable      = ixgbe_timesync_enable,
 532         .timesync_disable     = ixgbe_timesync_disable,
 533         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 534         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 535         .get_reg_length       = ixgbe_get_reg_length,
 536         .get_reg              = ixgbe_get_regs,
 537         .get_eeprom_length    = ixgbe_get_eeprom_length,
 538         .get_eeprom           = ixgbe_get_eeprom,
 539         .set_eeprom           = ixgbe_set_eeprom,
 540         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 541         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 542         .timesync_read_time   = ixgbe_timesync_read_time,
 543         .timesync_write_time  = ixgbe_timesync_write_time,
 544         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 545         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 546         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 547         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 548 };
 549
 550 /*
 551  * dev_ops for virtual function, bare necessities for basic vf
 552  * operation have been implemented
 553  */
 554 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 555         .dev_configure        = ixgbevf_dev_configure,
 556         .dev_start            = ixgbevf_dev_start,
 557         .dev_stop             = ixgbevf_dev_stop,
 558         .link_update          = ixgbe_dev_link_update,
 559         .stats_get            = ixgbevf_dev_stats_get,
 560         .xstats_get           = ixgbevf_dev_xstats_get,
 561         .stats_reset          = ixgbevf_dev_stats_reset,
 562         .xstats_reset         = ixgbevf_dev_stats_reset,
 563         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 564         .dev_close            = ixgbevf_dev_close,
 565         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 566         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 567         .dev_infos_get        = ixgbevf_dev_info_get,
 568         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 569         .mtu_set              = ixgbevf_dev_set_mtu,
 570         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 571         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 572         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 573         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 574         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 575         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 576         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 577         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 578         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 579         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 580         .mac_addr_add         = ixgbevf_add_mac_addr,
 581         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 582         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 583         .rxq_info_get         = ixgbe_rxq_info_get,
 584         .txq_info_get         = ixgbe_txq_info_get,
 585         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 586         .get_reg_length       = ixgbevf_get_reg_length,
 587         .get_reg              = ixgbevf_get_regs,
 588         .reta_update          = ixgbe_dev_rss_reta_update,
 589         .reta_query           = ixgbe_dev_rss_reta_query,
 590         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 591         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 592 };
 593
 594 /* store statistics names and its offset in stats structure */
 595 struct rte_ixgbe_xstats_name_off {
 596         char name[RTE_ETH_XSTATS_NAME_SIZE];
 597         unsigned offset;
 598 };
 599
 600 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 601         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 602         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 603         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 604         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 605         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 606         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 607         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 608         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 609         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 610         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 611         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 612         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 613         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 614         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 615         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 616                 prc1023)},
 617         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 618                 prc1522)},
 619         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 620         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 621         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 622         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 623         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 624         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 625         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 626         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 627         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 628         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 629         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 630         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 631         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 632         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 633         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 634         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 635         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 636                 ptc1023)},
 637         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 638                 ptc1522)},
 639         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 640         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 641         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 642         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 643
 644         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 645                 fdirustat_add)},
 646         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 647                 fdirustat_remove)},
 648         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 649                 fdirfstat_fadd)},
 650         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 651                 fdirfstat_fremove)},
 652         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 653                 fdirmatch)},
 654         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 655                 fdirmiss)},
 656
 657         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 658         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 659         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 660                 fclast)},
 661         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 662         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 663         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 664         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 665         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 666                 fcoe_noddp)},
 667         {"rx_fcoe_no_direct_data_placement_ext_buff",
 668                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 669
 670         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 671                 lxontxc)},
 672         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 673                 lxonrxc)},
 674         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 675                 lxofftxc)},
 676         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 677                 lxoffrxc)},
 678         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 679 };
 680
 681 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 682                            sizeof(rte_ixgbe_stats_strings[0]))
 683
 684 /* Per-queue statistics */
 685 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 686         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 687         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 688         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 689         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 690 };
 691
 692 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 693                            sizeof(rte_ixgbe_rxq_strings[0]))
 694 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 695
 696 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 697         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 698         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 699         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 700                 pxon2offc)},
 701 };
 702
 703 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 704                            sizeof(rte_ixgbe_txq_strings[0]))
 705 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 706
 707 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 708         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 709 };
 710
 711 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 712                 sizeof(rte_ixgbevf_stats_strings[0]))
 713
 714 /**
 715  * Atomically reads the link status information from global
 716  * structure rte_eth_dev.
 717  *
 718  * @param dev
 719  *   - Pointer to the structure rte_eth_dev to read from.
 720  *   - Pointer to the buffer to be saved with the link status.
 721  *
 722  * @return
 723  *   - On success, zero.
 724  *   - On failure, negative value.
 725  */
 726 static inline int
 727 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 728                                 struct rte_eth_link *link)
 729 {
 730         struct rte_eth_link *dst = link;
 731         struct rte_eth_link *src = &(dev->data->dev_link);
 732
 733         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 734                                         *(uint64_t *)src) == 0)
 735                 return -1;
 736
 737         return 0;
 738 }
 739
 740 /**
 741  * Atomically writes the link status information into global
 742  * structure rte_eth_dev.
 743  *
 744  * @param dev
 745  *   - Pointer to the structure rte_eth_dev to read from.
 746  *   - Pointer to the buffer to be saved with the link status.
 747  *
 748  * @return
 749  *   - On success, zero.
 750  *   - On failure, negative value.
 751  */
 752 static inline int
 753 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 754                                 struct rte_eth_link *link)
 755 {
 756         struct rte_eth_link *dst = &(dev->data->dev_link);
 757         struct rte_eth_link *src = link;
 758
 759         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 760                                         *(uint64_t *)src) == 0)
 761                 return -1;
 762
 763         return 0;
 764 }
 765
 766 /*
 767  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 768  */
 769 static inline int
 770 ixgbe_is_sfp(struct ixgbe_hw *hw)
 771 {
 772         switch (hw->phy.type) {
 773         case ixgbe_phy_sfp_avago:
 774         case ixgbe_phy_sfp_ftl:
 775         case ixgbe_phy_sfp_intel:
 776         case ixgbe_phy_sfp_unknown:
 777         case ixgbe_phy_sfp_passive_tyco:
 778         case ixgbe_phy_sfp_passive_unknown:
 779                 return 1;
 780         default:
 781                 return 0;
 782         }
 783 }
 784
 785 static inline int32_t
 786 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 787 {
 788         uint32_t ctrl_ext;
 789         int32_t status;
 790
 791         status = ixgbe_reset_hw(hw);
 792
 793         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 794         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 795         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 796         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 797         IXGBE_WRITE_FLUSH(hw);
 798
 799         return status;
 800 }
 801
 802 static inline void
 803 ixgbe_enable_intr(struct rte_eth_dev *dev)
 804 {
 805         struct ixgbe_interrupt *intr =
 806                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 807         struct ixgbe_hw *hw =
 808                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 809
 810         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 811         IXGBE_WRITE_FLUSH(hw);
 812 }
 813
 814 /*
 815  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 816  */
 817 static void
 818 ixgbe_disable_intr(struct ixgbe_hw *hw)
 819 {
 820         PMD_INIT_FUNC_TRACE();
 821
 822         if (hw->mac.type == ixgbe_mac_82598EB) {
 823                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 824         } else {
 825                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 826                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 827                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 828         }
 829         IXGBE_WRITE_FLUSH(hw);
 830 }
 831
 832 /*
 833  * This function resets queue statistics mapping registers.
 834  * From Niantic datasheet, Initialization of Statistics section:
 835  * "...if software requires the queue counters, the RQSMR and TQSM registers
 836  * must be re-programmed following a device reset.
 837  */
 838 static void
 839 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 840 {
 841         uint32_t i;
 842
 843         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 844                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 845                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 846         }
 847 }
 848
 849
 850 static int
 851 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 852                                   uint16_t queue_id,
 853                                   uint8_t stat_idx,
 854                                   uint8_t is_rx)
 855 {
 856 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 857 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 858 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 859
 860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 861         struct ixgbe_stat_mapping_registers *stat_mappings =
 862                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 863         uint32_t qsmr_mask = 0;
 864         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 865         uint32_t q_map;
 866         uint8_t n, offset;
 867
 868         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 869                 (hw->mac.type != ixgbe_mac_X540) &&
 870                 (hw->mac.type != ixgbe_mac_X550) &&
 871                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 872                 (hw->mac.type != ixgbe_mac_X550EM_a))
 873                 return -ENOSYS;
 874
 875         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 876                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 877                      queue_id, stat_idx);
 878
 879         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 880         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 881                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 882                 return -EIO;
 883         }
 884         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 885
 886         /* Now clear any previous stat_idx set */
 887         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 888         if (!is_rx)
 889                 stat_mappings->tqsm[n] &= ~clearing_mask;
 890         else
 891                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 892
 893         q_map = (uint32_t)stat_idx;
 894         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 895         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 896         if (!is_rx)
 897                 stat_mappings->tqsm[n] |= qsmr_mask;
 898         else
 899                 stat_mappings->rqsmr[n] |= qsmr_mask;
 900
 901         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 902                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 903                      queue_id, stat_idx);
 904         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 905                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 906
 907         /* Now write the mapping in the appropriate register */
 908         if (is_rx) {
 909                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 910                              stat_mappings->rqsmr[n], n);
 911                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 912         } else {
 913                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 914                              stat_mappings->tqsm[n], n);
 915                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 916         }
 917         return 0;
 918 }
 919
 920 static void
 921 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 922 {
 923         struct ixgbe_stat_mapping_registers *stat_mappings =
 924                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 926         int i;
 927
 928         /* write whatever was in stat mapping table to the NIC */
 929         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 930                 /* rx */
 931                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 932
 933                 /* tx */
 934                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 935         }
 936 }
 937
 938 static void
 939 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 940 {
 941         uint8_t i;
 942         struct ixgbe_dcb_tc_config *tc;
 943         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 944
 945         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 946         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 947         for (i = 0; i < dcb_max_tc; i++) {
 948                 tc = &dcb_config->tc_config[i];
 949                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 950                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 951                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 952                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 953                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 954                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 955                 tc->pfc = ixgbe_dcb_pfc_disabled;
 956         }
 957
 958         /* Initialize default user to priority mapping, UPx->TC0 */
 959         tc = &dcb_config->tc_config[0];
 960         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 961         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 962         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 963                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 964                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 965         }
 966         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 967         dcb_config->pfc_mode_enable = false;
 968         dcb_config->vt_mode = true;
 969         dcb_config->round_robin_enable = false;
 970         /* support all DCB capabilities in 82599 */
 971         dcb_config->support.capabilities = 0xFF;
 972
 973         /*we only support 4 Tcs for X540, X550 */
 974         if (hw->mac.type == ixgbe_mac_X540 ||
 975                 hw->mac.type == ixgbe_mac_X550 ||
 976                 hw->mac.type == ixgbe_mac_X550EM_x ||
 977                 hw->mac.type == ixgbe_mac_X550EM_a) {
 978                 dcb_config->num_tcs.pg_tcs = 4;
 979                 dcb_config->num_tcs.pfc_tcs = 4;
 980         }
 981 }
 982
 983 /*
 984  * Ensure that all locks are released before first NVM or PHY access
 985  */
 986 static void
 987 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 988 {
 989         uint16_t mask;
 990
 991         /*
 992          * Phy lock should not fail in this early stage. If this is the case,
 993          * it is due to an improper exit of the application.
 994          * So force the release of the faulty lock. Release of common lock
 995          * is done automatically by swfw_sync function.
 996          */
 997         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 998         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 999                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1000         }
1001         ixgbe_release_swfw_semaphore(hw, mask);
1002
1003         /*
1004          * These ones are more tricky since they are common to all ports; but
1005          * swfw_sync retries last long enough (1s) to be almost sure that if
1006          * lock can not be taken it is due to an improper lock of the
1007          * semaphore.
1008          */
1009         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1010         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1011                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1012         }
1013         ixgbe_release_swfw_semaphore(hw, mask);
1014 }
1015
1016 /*
1017  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1018  * It returns 0 on success.
1019  */
1020 static int
1021 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1022 {
1023         struct rte_pci_device *pci_dev;
1024         struct ixgbe_hw *hw =
1025                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1026         struct ixgbe_vfta *shadow_vfta =
1027                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1028         struct ixgbe_hwstrip *hwstrip =
1029                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1030         struct ixgbe_dcb_config *dcb_config =
1031                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1032         struct ixgbe_filter_info *filter_info =
1033                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1034         uint32_t ctrl_ext;
1035         uint16_t csum;
1036         int diag, i;
1037
1038         PMD_INIT_FUNC_TRACE();
1039
1040         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1041         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1042         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1043
1044         /*
1045          * For secondary processes, we don't initialise any further as primary
1046          * has already done this work. Only check we don't need a different
1047          * RX and TX function.
1048          */
1049         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1050                 struct ixgbe_tx_queue *txq;
1051                 /* TX queue function in primary, set by last queue initialized
1052                  * Tx queue may not initialized by primary process
1053                  */
1054                 if (eth_dev->data->tx_queues) {
1055                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1056                         ixgbe_set_tx_function(eth_dev, txq);
1057                 } else {
1058                         /* Use default TX function if we get here */
1059                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1060                                      "Using default TX function.");
1061                 }
1062
1063                 ixgbe_set_rx_function(eth_dev);
1064
1065                 return 0;
1066         }
1067         pci_dev = eth_dev->pci_dev;
1068
1069         rte_eth_copy_pci_info(eth_dev, pci_dev);
1070
1071         /* Vendor and Device ID need to be set before init of shared code */
1072         hw->device_id = pci_dev->id.device_id;
1073         hw->vendor_id = pci_dev->id.vendor_id;
1074         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1075         hw->allow_unsupported_sfp = 1;
1076
1077         /* Initialize the shared code (base driver) */
1078 #ifdef RTE_NIC_BYPASS
1079         diag = ixgbe_bypass_init_shared_code(hw);
1080 #else
1081         diag = ixgbe_init_shared_code(hw);
1082 #endif /* RTE_NIC_BYPASS */
1083
1084         if (diag != IXGBE_SUCCESS) {
1085                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1086                 return -EIO;
1087         }
1088
1089         /* pick up the PCI bus settings for reporting later */
1090         ixgbe_get_bus_info(hw);
1091
1092         /* Unlock any pending hardware semaphore */
1093         ixgbe_swfw_lock_reset(hw);
1094
1095         /* Initialize DCB configuration*/
1096         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1097         ixgbe_dcb_init(hw, dcb_config);
1098         /* Get Hardware Flow Control setting */
1099         hw->fc.requested_mode = ixgbe_fc_full;
1100         hw->fc.current_mode = ixgbe_fc_full;
1101         hw->fc.pause_time = IXGBE_FC_PAUSE;
1102         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1103                 hw->fc.low_water[i] = IXGBE_FC_LO;
1104                 hw->fc.high_water[i] = IXGBE_FC_HI;
1105         }
1106         hw->fc.send_xon = 1;
1107
1108         /* Make sure we have a good EEPROM before we read from it */
1109         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1110         if (diag != IXGBE_SUCCESS) {
1111                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1112                 return -EIO;
1113         }
1114
1115 #ifdef RTE_NIC_BYPASS
1116         diag = ixgbe_bypass_init_hw(hw);
1117 #else
1118         diag = ixgbe_init_hw(hw);
1119 #endif /* RTE_NIC_BYPASS */
1120
1121         /*
1122          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1123          * is called too soon after the kernel driver unbinding/binding occurs.
1124          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1125          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1126          * also called. See ixgbe_identify_phy_82599(). The reason for the
1127          * failure is not known, and only occuts when virtualisation features
1128          * are disabled in the bios. A delay of 100ms  was found to be enough by
1129          * trial-and-error, and is doubled to be safe.
1130          */
1131         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1132                 rte_delay_ms(200);
1133                 diag = ixgbe_init_hw(hw);
1134         }
1135
1136         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1137                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1138                              "LOM.  Please be aware there may be issues associated "
1139                              "with your hardware.");
1140                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1141                              "please contact your Intel or hardware representative "
1142                              "who provided you with this hardware.");
1143         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1144                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1145         if (diag) {
1146                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1147                 return -EIO;
1148         }
1149
1150         /* Reset the hw statistics */
1151         ixgbe_dev_stats_reset(eth_dev);
1152
1153         /* disable interrupt */
1154         ixgbe_disable_intr(hw);
1155
1156         /* reset mappings for queue statistics hw counters*/
1157         ixgbe_reset_qstat_mappings(hw);
1158
1159         /* Allocate memory for storing MAC addresses */
1160         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1161                                                hw->mac.num_rar_entries, 0);
1162         if (eth_dev->data->mac_addrs == NULL) {
1163                 PMD_INIT_LOG(ERR,
1164                              "Failed to allocate %u bytes needed to store "
1165                              "MAC addresses",
1166                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1167                 return -ENOMEM;
1168         }
1169         /* Copy the permanent MAC address */
1170         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1171                         &eth_dev->data->mac_addrs[0]);
1172
1173         /* Allocate memory for storing hash filter MAC addresses */
1174         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1175                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1176         if (eth_dev->data->hash_mac_addrs == NULL) {
1177                 PMD_INIT_LOG(ERR,
1178                              "Failed to allocate %d bytes needed to store MAC addresses",
1179                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1180                 return -ENOMEM;
1181         }
1182
1183         /* initialize the vfta */
1184         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1185
1186         /* initialize the hw strip bitmap*/
1187         memset(hwstrip, 0, sizeof(*hwstrip));
1188
1189         /* initialize PF if max_vfs not zero */
1190         ixgbe_pf_host_init(eth_dev);
1191
1192         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1193         /* let hardware know driver is loaded */
1194         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1195         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1196         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1197         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1198         IXGBE_WRITE_FLUSH(hw);
1199
1200         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1201                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1202                              (int) hw->mac.type, (int) hw->phy.type,
1203                              (int) hw->phy.sfp_type);
1204         else
1205                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1206                              (int) hw->mac.type, (int) hw->phy.type);
1207
1208         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1209                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1210                      pci_dev->id.device_id);
1211
1212         rte_intr_callback_register(&pci_dev->intr_handle,
1213                                    ixgbe_dev_interrupt_handler,
1214                                    (void *)eth_dev);
1215
1216         /* enable uio/vfio intr/eventfd mapping */
1217         rte_intr_enable(&pci_dev->intr_handle);
1218
1219         /* enable support intr */
1220         ixgbe_enable_intr(eth_dev);
1221
1222         /* initialize 5tuple filter list */
1223         TAILQ_INIT(&filter_info->fivetuple_list);
1224         memset(filter_info->fivetuple_mask, 0,
1225                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1226
1227         return 0;
1228 }
1229
1230 static int
1231 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1232 {
1233         struct rte_pci_device *pci_dev;
1234         struct ixgbe_hw *hw;
1235
1236         PMD_INIT_FUNC_TRACE();
1237
1238         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1239                 return -EPERM;
1240
1241         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1242         pci_dev = eth_dev->pci_dev;
1243
1244         if (hw->adapter_stopped == 0)
1245                 ixgbe_dev_close(eth_dev);
1246
1247         eth_dev->dev_ops = NULL;
1248         eth_dev->rx_pkt_burst = NULL;
1249         eth_dev->tx_pkt_burst = NULL;
1250
1251         /* Unlock any pending hardware semaphore */
1252         ixgbe_swfw_lock_reset(hw);
1253
1254         /* disable uio intr before callback unregister */
1255         rte_intr_disable(&(pci_dev->intr_handle));
1256         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1257                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1258
1259         /* uninitialize PF if max_vfs not zero */
1260         ixgbe_pf_host_uninit(eth_dev);
1261
1262         rte_free(eth_dev->data->mac_addrs);
1263         eth_dev->data->mac_addrs = NULL;
1264
1265         rte_free(eth_dev->data->hash_mac_addrs);
1266         eth_dev->data->hash_mac_addrs = NULL;
1267
1268         return 0;
1269 }
1270
1271 /*
1272  * Negotiate mailbox API version with the PF.
1273  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1274  * Then we try to negotiate starting with the most recent one.
1275  * If all negotiation attempts fail, then we will proceed with
1276  * the default one (ixgbe_mbox_api_10).
1277  */
1278 static void
1279 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1280 {
1281         int32_t i;
1282
1283         /* start with highest supported, proceed down */
1284         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1285                 ixgbe_mbox_api_12,
1286                 ixgbe_mbox_api_11,
1287                 ixgbe_mbox_api_10,
1288         };
1289
1290         for (i = 0;
1291                         i != RTE_DIM(sup_ver) &&
1292                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1293                         i++)
1294                 ;
1295 }
1296
1297 static void
1298 generate_random_mac_addr(struct ether_addr *mac_addr)
1299 {
1300         uint64_t random;
1301
1302         /* Set Organizationally Unique Identifier (OUI) prefix. */
1303         mac_addr->addr_bytes[0] = 0x00;
1304         mac_addr->addr_bytes[1] = 0x09;
1305         mac_addr->addr_bytes[2] = 0xC0;
1306         /* Force indication of locally assigned MAC address. */
1307         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1308         /* Generate the last 3 bytes of the MAC address with a random number. */
1309         random = rte_rand();
1310         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1311 }
1312
1313 /*
1314  * Virtual Function device init
1315  */
1316 static int
1317 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1318 {
1319         int diag;
1320         uint32_t tc, tcs;
1321         struct rte_pci_device *pci_dev;
1322         struct ixgbe_hw *hw =
1323                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1324         struct ixgbe_vfta *shadow_vfta =
1325                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1326         struct ixgbe_hwstrip *hwstrip =
1327                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1328         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1329
1330         PMD_INIT_FUNC_TRACE();
1331
1332         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1333         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1334         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1335
1336         /* for secondary processes, we don't initialise any further as primary
1337          * has already done this work. Only check we don't need a different
1338          * RX function
1339          */
1340         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1341                 struct ixgbe_tx_queue *txq;
1342                 /* TX queue function in primary, set by last queue initialized
1343                  * Tx queue may not initialized by primary process
1344                  */
1345                 if (eth_dev->data->tx_queues) {
1346                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1347                         ixgbe_set_tx_function(eth_dev, txq);
1348                 } else {
1349                         /* Use default TX function if we get here */
1350                         PMD_INIT_LOG(NOTICE,
1351                                      "No TX queues configured yet. Using default TX function.");
1352                 }
1353
1354                 ixgbe_set_rx_function(eth_dev);
1355
1356                 return 0;
1357         }
1358
1359         pci_dev = eth_dev->pci_dev;
1360
1361         rte_eth_copy_pci_info(eth_dev, pci_dev);
1362
1363         hw->device_id = pci_dev->id.device_id;
1364         hw->vendor_id = pci_dev->id.vendor_id;
1365         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1366
1367         /* initialize the vfta */
1368         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1369
1370         /* initialize the hw strip bitmap*/
1371         memset(hwstrip, 0, sizeof(*hwstrip));
1372
1373         /* Initialize the shared code (base driver) */
1374         diag = ixgbe_init_shared_code(hw);
1375         if (diag != IXGBE_SUCCESS) {
1376                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1377                 return -EIO;
1378         }
1379
1380         /* init_mailbox_params */
1381         hw->mbx.ops.init_params(hw);
1382
1383         /* Reset the hw statistics */
1384         ixgbevf_dev_stats_reset(eth_dev);
1385
1386         /* Disable the interrupts for VF */
1387         ixgbevf_intr_disable(hw);
1388
1389         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1390         diag = hw->mac.ops.reset_hw(hw);
1391
1392         /*
1393          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1394          * the underlying PF driver has not assigned a MAC address to the VF.
1395          * In this case, assign a random MAC address.
1396          */
1397         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1398                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1399                 return diag;
1400         }
1401
1402         /* negotiate mailbox API version to use with the PF. */
1403         ixgbevf_negotiate_api(hw);
1404
1405         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1406         ixgbevf_get_queues(hw, &tcs, &tc);
1407
1408         /* Allocate memory for storing MAC addresses */
1409         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1410                                                hw->mac.num_rar_entries, 0);
1411         if (eth_dev->data->mac_addrs == NULL) {
1412                 PMD_INIT_LOG(ERR,
1413                              "Failed to allocate %u bytes needed to store "
1414                              "MAC addresses",
1415                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1416                 return -ENOMEM;
1417         }
1418
1419         /* Generate a random MAC address, if none was assigned by PF. */
1420         if (is_zero_ether_addr(perm_addr)) {
1421                 generate_random_mac_addr(perm_addr);
1422                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1423                 if (diag) {
1424                         rte_free(eth_dev->data->mac_addrs);
1425                         eth_dev->data->mac_addrs = NULL;
1426                         return diag;
1427                 }
1428                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1429                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1430                              "%02x:%02x:%02x:%02x:%02x:%02x",
1431                              perm_addr->addr_bytes[0],
1432                              perm_addr->addr_bytes[1],
1433                              perm_addr->addr_bytes[2],
1434                              perm_addr->addr_bytes[3],
1435                              perm_addr->addr_bytes[4],
1436                              perm_addr->addr_bytes[5]);
1437         }
1438
1439         /* Copy the permanent MAC address */
1440         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1441
1442         /* reset the hardware with the new settings */
1443         diag = hw->mac.ops.start_hw(hw);
1444         switch (diag) {
1445         case  0:
1446                 break;
1447
1448         default:
1449                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1450                 return -EIO;
1451         }
1452
1453         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1454                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1455                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1456
1457         return 0;
1458 }
1459
1460 /* Virtual Function device uninit */
1461
1462 static int
1463 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1464 {
1465         struct ixgbe_hw *hw;
1466
1467         PMD_INIT_FUNC_TRACE();
1468
1469         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1470                 return -EPERM;
1471
1472         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1473
1474         if (hw->adapter_stopped == 0)
1475                 ixgbevf_dev_close(eth_dev);
1476
1477         eth_dev->dev_ops = NULL;
1478         eth_dev->rx_pkt_burst = NULL;
1479         eth_dev->tx_pkt_burst = NULL;
1480
1481         /* Disable the interrupts for VF */
1482         ixgbevf_intr_disable(hw);
1483
1484         rte_free(eth_dev->data->mac_addrs);
1485         eth_dev->data->mac_addrs = NULL;
1486
1487         return 0;
1488 }
1489
1490 static struct eth_driver rte_ixgbe_pmd = {
1491         .pci_drv = {
1492                 .name = "rte_ixgbe_pmd",
1493                 .id_table = pci_id_ixgbe_map,
1494                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1495                         RTE_PCI_DRV_DETACHABLE,
1496         },
1497         .eth_dev_init = eth_ixgbe_dev_init,
1498         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1499         .dev_private_size = sizeof(struct ixgbe_adapter),
1500 };
1501
1502 /*
1503  * virtual function driver struct
1504  */
1505 static struct eth_driver rte_ixgbevf_pmd = {
1506         .pci_drv = {
1507                 .name = "rte_ixgbevf_pmd",
1508                 .id_table = pci_id_ixgbevf_map,
1509                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1510         },
1511         .eth_dev_init = eth_ixgbevf_dev_init,
1512         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1513         .dev_private_size = sizeof(struct ixgbe_adapter),
1514 };
1515
1516 /*
1517  * Driver initialization routine.
1518  * Invoked once at EAL init time.
1519  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1520  */
1521 static int
1522 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1523 {
1524         PMD_INIT_FUNC_TRACE();
1525
1526         rte_eth_driver_register(&rte_ixgbe_pmd);
1527         return 0;
1528 }
1529
1530 /*
1531  * VF Driver initialization routine.
1532  * Invoked one at EAL init time.
1533  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1534  */
1535 static int
1536 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1537 {
1538         PMD_INIT_FUNC_TRACE();
1539
1540         rte_eth_driver_register(&rte_ixgbevf_pmd);
1541         return 0;
1542 }
1543
1544 static int
1545 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1546 {
1547         struct ixgbe_hw *hw =
1548                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1549         struct ixgbe_vfta *shadow_vfta =
1550                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1551         uint32_t vfta;
1552         uint32_t vid_idx;
1553         uint32_t vid_bit;
1554
1555         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1556         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1557         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1558         if (on)
1559                 vfta |= vid_bit;
1560         else
1561                 vfta &= ~vid_bit;
1562         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1563
1564         /* update local VFTA copy */
1565         shadow_vfta->vfta[vid_idx] = vfta;
1566
1567         return 0;
1568 }
1569
1570 static void
1571 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1572 {
1573         if (on)
1574                 ixgbe_vlan_hw_strip_enable(dev, queue);
1575         else
1576                 ixgbe_vlan_hw_strip_disable(dev, queue);
1577 }
1578
1579 static int
1580 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1581                     enum rte_vlan_type vlan_type,
1582                     uint16_t tpid)
1583 {
1584         struct ixgbe_hw *hw =
1585                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586         int ret = 0;
1587
1588         switch (vlan_type) {
1589         case ETH_VLAN_TYPE_INNER:
1590                 /* Only the high 16-bits is valid */
1591                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1592                 break;
1593         default:
1594                 ret = -EINVAL;
1595                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1596                 break;
1597         }
1598
1599         return ret;
1600 }
1601
1602 void
1603 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1604 {
1605         struct ixgbe_hw *hw =
1606                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1607         uint32_t vlnctrl;
1608
1609         PMD_INIT_FUNC_TRACE();
1610
1611         /* Filter Table Disable */
1612         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1613         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1614
1615         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1616 }
1617
1618 void
1619 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1620 {
1621         struct ixgbe_hw *hw =
1622                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623         struct ixgbe_vfta *shadow_vfta =
1624                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1625         uint32_t vlnctrl;
1626         uint16_t i;
1627
1628         PMD_INIT_FUNC_TRACE();
1629
1630         /* Filter Table Enable */
1631         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1632         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1633         vlnctrl |= IXGBE_VLNCTRL_VFE;
1634
1635         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1636
1637         /* write whatever is in local vfta copy */
1638         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1639                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1640 }
1641
1642 static void
1643 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1644 {
1645         struct ixgbe_hwstrip *hwstrip =
1646                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1647         struct ixgbe_rx_queue *rxq;
1648
1649         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1650                 return;
1651
1652         if (on)
1653                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1654         else
1655                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1656
1657         if (queue >= dev->data->nb_rx_queues)
1658                 return;
1659
1660         rxq = dev->data->rx_queues[queue];
1661
1662         if (on)
1663                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1664         else
1665                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1666 }
1667
1668 static void
1669 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1670 {
1671         struct ixgbe_hw *hw =
1672                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673         uint32_t ctrl;
1674
1675         PMD_INIT_FUNC_TRACE();
1676
1677         if (hw->mac.type == ixgbe_mac_82598EB) {
1678                 /* No queue level support */
1679                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1680                 return;
1681         }
1682
1683         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1684         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1685         ctrl &= ~IXGBE_RXDCTL_VME;
1686         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1687
1688         /* record those setting for HW strip per queue */
1689         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1690 }
1691
1692 static void
1693 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1694 {
1695         struct ixgbe_hw *hw =
1696                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1697         uint32_t ctrl;
1698
1699         PMD_INIT_FUNC_TRACE();
1700
1701         if (hw->mac.type == ixgbe_mac_82598EB) {
1702                 /* No queue level supported */
1703                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1704                 return;
1705         }
1706
1707         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1708         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1709         ctrl |= IXGBE_RXDCTL_VME;
1710         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1711
1712         /* record those setting for HW strip per queue */
1713         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1714 }
1715
1716 void
1717 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1718 {
1719         struct ixgbe_hw *hw =
1720                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1721         uint32_t ctrl;
1722         uint16_t i;
1723
1724         PMD_INIT_FUNC_TRACE();
1725
1726         if (hw->mac.type == ixgbe_mac_82598EB) {
1727                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1728                 ctrl &= ~IXGBE_VLNCTRL_VME;
1729                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1730         } else {
1731                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1732                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1733                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1734                         ctrl &= ~IXGBE_RXDCTL_VME;
1735                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1736
1737                         /* record those setting for HW strip per queue */
1738                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1739                 }
1740         }
1741 }
1742
1743 void
1744 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1745 {
1746         struct ixgbe_hw *hw =
1747                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1748         uint32_t ctrl;
1749         uint16_t i;
1750
1751         PMD_INIT_FUNC_TRACE();
1752
1753         if (hw->mac.type == ixgbe_mac_82598EB) {
1754                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1755                 ctrl |= IXGBE_VLNCTRL_VME;
1756                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1757         } else {
1758                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1759                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1760                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1761                         ctrl |= IXGBE_RXDCTL_VME;
1762                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1763
1764                         /* record those setting for HW strip per queue */
1765                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1766                 }
1767         }
1768 }
1769
1770 static void
1771 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1772 {
1773         struct ixgbe_hw *hw =
1774                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775         uint32_t ctrl;
1776
1777         PMD_INIT_FUNC_TRACE();
1778
1779         /* DMATXCTRL: Geric Double VLAN Disable */
1780         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1781         ctrl &= ~IXGBE_DMATXCTL_GDV;
1782         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1783
1784         /* CTRL_EXT: Global Double VLAN Disable */
1785         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1786         ctrl &= ~IXGBE_EXTENDED_VLAN;
1787         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1788
1789 }
1790
1791 static void
1792 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1793 {
1794         struct ixgbe_hw *hw =
1795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796         uint32_t ctrl;
1797
1798         PMD_INIT_FUNC_TRACE();
1799
1800         /* DMATXCTRL: Geric Double VLAN Enable */
1801         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1802         ctrl |= IXGBE_DMATXCTL_GDV;
1803         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1804
1805         /* CTRL_EXT: Global Double VLAN Enable */
1806         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1807         ctrl |= IXGBE_EXTENDED_VLAN;
1808         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1809
1810         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1811         if (hw->mac.type == ixgbe_mac_X550 ||
1812             hw->mac.type == ixgbe_mac_X550EM_x ||
1813             hw->mac.type == ixgbe_mac_X550EM_a) {
1814                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1815                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1816                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1817         }
1818
1819         /*
1820          * VET EXT field in the EXVET register = 0x8100 by default
1821          * So no need to change. Same to VT field of DMATXCTL register
1822          */
1823 }
1824
1825 static void
1826 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1827 {
1828         if (mask & ETH_VLAN_STRIP_MASK) {
1829                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1830                         ixgbe_vlan_hw_strip_enable_all(dev);
1831                 else
1832                         ixgbe_vlan_hw_strip_disable_all(dev);
1833         }
1834
1835         if (mask & ETH_VLAN_FILTER_MASK) {
1836                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1837                         ixgbe_vlan_hw_filter_enable(dev);
1838                 else
1839                         ixgbe_vlan_hw_filter_disable(dev);
1840         }
1841
1842         if (mask & ETH_VLAN_EXTEND_MASK) {
1843                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1844                         ixgbe_vlan_hw_extend_enable(dev);
1845                 else
1846                         ixgbe_vlan_hw_extend_disable(dev);
1847         }
1848 }
1849
1850 static void
1851 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1852 {
1853         struct ixgbe_hw *hw =
1854                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1856         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1857
1858         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1859         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1860 }
1861
1862 static int
1863 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1864 {
1865         switch (nb_rx_q) {
1866         case 1:
1867         case 2:
1868                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1869                 break;
1870         case 4:
1871                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1872                 break;
1873         default:
1874                 return -EINVAL;
1875         }
1876
1877         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1878         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1879
1880         return 0;
1881 }
1882
1883 static int
1884 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1885 {
1886         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1888         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1889         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1890
1891         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1892                 /* check multi-queue mode */
1893                 switch (dev_conf->rxmode.mq_mode) {
1894                 case ETH_MQ_RX_VMDQ_DCB:
1895                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1896                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1897                         PMD_INIT_LOG(ERR, "SRIOV active,"
1898                                         " unsupported mq_mode rx %d.",
1899                                         dev_conf->rxmode.mq_mode);
1900                         return -EINVAL;
1901                 case ETH_MQ_RX_RSS:
1902                 case ETH_MQ_RX_VMDQ_RSS:
1903                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1904                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1905                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1906                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1907                                                 " invalid queue number"
1908                                                 " for VMDQ RSS, allowed"
1909                                                 " value are 1, 2 or 4.");
1910                                         return -EINVAL;
1911                                 }
1912                         break;
1913                 case ETH_MQ_RX_VMDQ_ONLY:
1914                 case ETH_MQ_RX_NONE:
1915                         /* if nothing mq mode configure, use default scheme */
1916                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1917                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1918                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1919                         break;
1920                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1921                         /* SRIOV only works in VMDq enable mode */
1922                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1923                                         " wrong mq_mode rx %d.",
1924                                         dev_conf->rxmode.mq_mode);
1925                         return -EINVAL;
1926                 }
1927
1928                 switch (dev_conf->txmode.mq_mode) {
1929                 case ETH_MQ_TX_VMDQ_DCB:
1930                         /* DCB VMDQ in SRIOV mode, not implement yet */
1931                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1932                                         " unsupported VMDQ mq_mode tx %d.",
1933                                         dev_conf->txmode.mq_mode);
1934                         return -EINVAL;
1935                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1936                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1937                         break;
1938                 }
1939
1940                 /* check valid queue number */
1941                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1942                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1943                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1944                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1945                                         " must be less than or equal to %d.",
1946                                         nb_rx_q, nb_tx_q,
1947                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1948                         return -EINVAL;
1949                 }
1950         } else {
1951                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1952                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1953                                           " not supported.");
1954                         return -EINVAL;
1955                 }
1956                 /* check configuration for vmdb+dcb mode */
1957                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1958                         const struct rte_eth_vmdq_dcb_conf *conf;
1959
1960                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1961                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1962                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1963                                 return -EINVAL;
1964                         }
1965                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1966                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1967                                conf->nb_queue_pools == ETH_32_POOLS)) {
1968                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1969                                                 " nb_queue_pools must be %d or %d.",
1970                                                 ETH_16_POOLS, ETH_32_POOLS);
1971                                 return -EINVAL;
1972                         }
1973                 }
1974                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1975                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1976
1977                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1978                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1979                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1980                                 return -EINVAL;
1981                         }
1982                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1983                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1984                                conf->nb_queue_pools == ETH_32_POOLS)) {
1985                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1986                                                 " nb_queue_pools != %d and"
1987                                                 " nb_queue_pools != %d.",
1988                                                 ETH_16_POOLS, ETH_32_POOLS);
1989                                 return -EINVAL;
1990                         }
1991                 }
1992
1993                 /* For DCB mode check our configuration before we go further */
1994                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1995                         const struct rte_eth_dcb_rx_conf *conf;
1996
1997                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1998                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1999                                                  IXGBE_DCB_NB_QUEUES);
2000                                 return -EINVAL;
2001                         }
2002                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2003                         if (!(conf->nb_tcs == ETH_4_TCS ||
2004                                conf->nb_tcs == ETH_8_TCS)) {
2005                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2006                                                 " and nb_tcs != %d.",
2007                                                 ETH_4_TCS, ETH_8_TCS);
2008                                 return -EINVAL;
2009                         }
2010                 }
2011
2012                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2013                         const struct rte_eth_dcb_tx_conf *conf;
2014
2015                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2016                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2017                                                  IXGBE_DCB_NB_QUEUES);
2018                                 return -EINVAL;
2019                         }
2020                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2021                         if (!(conf->nb_tcs == ETH_4_TCS ||
2022                                conf->nb_tcs == ETH_8_TCS)) {
2023                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2024                                                 " and nb_tcs != %d.",
2025                                                 ETH_4_TCS, ETH_8_TCS);
2026                                 return -EINVAL;
2027                         }
2028                 }
2029
2030                 /*
2031                  * When DCB/VT is off, maximum number of queues changes,
2032                  * except for 82598EB, which remains constant.
2033                  */
2034                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2035                                 hw->mac.type != ixgbe_mac_82598EB) {
2036                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2037                                 PMD_INIT_LOG(ERR,
2038                                              "Neither VT nor DCB are enabled, "
2039                                              "nb_tx_q > %d.",
2040                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2041                                 return -EINVAL;
2042                         }
2043                 }
2044         }
2045         return 0;
2046 }
2047
2048 static int
2049 ixgbe_dev_configure(struct rte_eth_dev *dev)
2050 {
2051         struct ixgbe_interrupt *intr =
2052                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2053         struct ixgbe_adapter *adapter =
2054                 (struct ixgbe_adapter *)dev->data->dev_private;
2055         int ret;
2056
2057         PMD_INIT_FUNC_TRACE();
2058         /* multipe queue mode checking */
2059         ret  = ixgbe_check_mq_mode(dev);
2060         if (ret != 0) {
2061                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2062                             ret);
2063                 return ret;
2064         }
2065
2066         /* set flag to update link status after init */
2067         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2068
2069         /*
2070          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2071          * allocation or vector Rx preconditions we will reset it.
2072          */
2073         adapter->rx_bulk_alloc_allowed = true;
2074         adapter->rx_vec_allowed = true;
2075
2076         return 0;
2077 }
2078
2079 static void
2080 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2081 {
2082         struct ixgbe_hw *hw =
2083                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084         struct ixgbe_interrupt *intr =
2085                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2086         uint32_t gpie;
2087
2088         /* only set up it on X550EM_X */
2089         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2090                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2091                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2092                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2093                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2094                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2095         }
2096 }
2097
2098 /*
2099  * Configure device link speed and setup link.
2100  * It returns 0 on success.
2101  */
2102 static int
2103 ixgbe_dev_start(struct rte_eth_dev *dev)
2104 {
2105         struct ixgbe_hw *hw =
2106                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct ixgbe_vf_info *vfinfo =
2108                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2109         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2110         uint32_t intr_vector = 0;
2111         int err, link_up = 0, negotiate = 0;
2112         uint32_t speed = 0;
2113         int mask = 0;
2114         int status;
2115         uint16_t vf, idx;
2116         uint32_t *link_speeds;
2117
2118         PMD_INIT_FUNC_TRACE();
2119
2120         /* IXGBE devices don't support:
2121         *    - half duplex (checked afterwards for valid speeds)
2122         *    - fixed speed: TODO implement
2123         */
2124         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2125                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2126                              dev->data->port_id);
2127                 return -EINVAL;
2128         }
2129
2130         /* disable uio/vfio intr/eventfd mapping */
2131         rte_intr_disable(intr_handle);
2132
2133         /* stop adapter */
2134         hw->adapter_stopped = 0;
2135         ixgbe_stop_adapter(hw);
2136
2137         /* reinitialize adapter
2138          * this calls reset and start
2139          */
2140         status = ixgbe_pf_reset_hw(hw);
2141         if (status != 0)
2142                 return -1;
2143         hw->mac.ops.start_hw(hw);
2144         hw->mac.get_link_status = true;
2145
2146         /* configure PF module if SRIOV enabled */
2147         ixgbe_pf_host_configure(dev);
2148
2149         ixgbe_dev_phy_intr_setup(dev);
2150
2151         /* check and configure queue intr-vector mapping */
2152         if ((rte_intr_cap_multiple(intr_handle) ||
2153              !RTE_ETH_DEV_SRIOV(dev).active) &&
2154             dev->data->dev_conf.intr_conf.rxq != 0) {
2155                 intr_vector = dev->data->nb_rx_queues;
2156                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2157                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2158                                         IXGBE_MAX_INTR_QUEUE_NUM);
2159                         return -ENOTSUP;
2160                 }
2161                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2162                         return -1;
2163         }
2164
2165         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2166                 intr_handle->intr_vec =
2167                         rte_zmalloc("intr_vec",
2168                                     dev->data->nb_rx_queues * sizeof(int), 0);
2169                 if (intr_handle->intr_vec == NULL) {
2170                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2171                                      " intr_vec\n", dev->data->nb_rx_queues);
2172                         return -ENOMEM;
2173                 }
2174         }
2175
2176         /* confiugre msix for sleep until rx interrupt */
2177         ixgbe_configure_msix(dev);
2178
2179         /* initialize transmission unit */
2180         ixgbe_dev_tx_init(dev);
2181
2182         /* This can fail when allocating mbufs for descriptor rings */
2183         err = ixgbe_dev_rx_init(dev);
2184         if (err) {
2185                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2186                 goto error;
2187         }
2188
2189         err = ixgbe_dev_rxtx_start(dev);
2190         if (err < 0) {
2191                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2192                 goto error;
2193         }
2194
2195         /* Skip link setup if loopback mode is enabled for 82599. */
2196         if (hw->mac.type == ixgbe_mac_82599EB &&
2197                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2198                 goto skip_link_setup;
2199
2200         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2201                 err = hw->mac.ops.setup_sfp(hw);
2202                 if (err)
2203                         goto error;
2204         }
2205
2206         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2207                 /* Turn on the copper */
2208                 ixgbe_set_phy_power(hw, true);
2209         } else {
2210                 /* Turn on the laser */
2211                 ixgbe_enable_tx_laser(hw);
2212         }
2213
2214         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2215         if (err)
2216                 goto error;
2217         dev->data->dev_link.link_status = link_up;
2218
2219         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2220         if (err)
2221                 goto error;
2222
2223         link_speeds = &dev->data->dev_conf.link_speeds;
2224         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2225                         ETH_LINK_SPEED_10G)) {
2226                 PMD_INIT_LOG(ERR, "Invalid link setting");
2227                 goto error;
2228         }
2229
2230         speed = 0x0;
2231         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2232                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2233                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2234                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2235         } else {
2236                 if (*link_speeds & ETH_LINK_SPEED_10G)
2237                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2238                 if (*link_speeds & ETH_LINK_SPEED_1G)
2239                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2240                 if (*link_speeds & ETH_LINK_SPEED_100M)
2241                         speed |= IXGBE_LINK_SPEED_100_FULL;
2242         }
2243
2244         err = ixgbe_setup_link(hw, speed, link_up);
2245         if (err)
2246                 goto error;
2247
2248 skip_link_setup:
2249
2250         if (rte_intr_allow_others(intr_handle)) {
2251                 /* check if lsc interrupt is enabled */
2252                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2253                         ixgbe_dev_lsc_interrupt_setup(dev);
2254         } else {
2255                 rte_intr_callback_unregister(intr_handle,
2256                                              ixgbe_dev_interrupt_handler,
2257                                              (void *)dev);
2258                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2259                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2260                                      " no intr multiplex\n");
2261         }
2262
2263         /* check if rxq interrupt is enabled */
2264         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2265             rte_intr_dp_is_en(intr_handle))
2266                 ixgbe_dev_rxq_interrupt_setup(dev);
2267
2268         /* enable uio/vfio intr/eventfd mapping */
2269         rte_intr_enable(intr_handle);
2270
2271         /* resume enabled intr since hw reset */
2272         ixgbe_enable_intr(dev);
2273
2274         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2275                 ETH_VLAN_EXTEND_MASK;
2276         ixgbe_vlan_offload_set(dev, mask);
2277
2278         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2279                 /* Enable vlan filtering for VMDq */
2280                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2281         }
2282
2283         /* Configure DCB hw */
2284         ixgbe_configure_dcb(dev);
2285
2286         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2287                 err = ixgbe_fdir_configure(dev);
2288                 if (err)
2289                         goto error;
2290         }
2291
2292         /* Restore vf rate limit */
2293         if (vfinfo != NULL) {
2294                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2295                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2296                                 if (vfinfo[vf].tx_rate[idx] != 0)
2297                                         ixgbe_set_vf_rate_limit(dev, vf,
2298                                                 vfinfo[vf].tx_rate[idx],
2299                                                 1 << idx);
2300         }
2301
2302         ixgbe_restore_statistics_mapping(dev);
2303
2304         return 0;
2305
2306 error:
2307         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2308         ixgbe_dev_clear_queues(dev);
2309         return -EIO;
2310 }
2311
2312 /*
2313  * Stop device: disable rx and tx functions to allow for reconfiguring.
2314  */
2315 static void
2316 ixgbe_dev_stop(struct rte_eth_dev *dev)
2317 {
2318         struct rte_eth_link link;
2319         struct ixgbe_hw *hw =
2320                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2321         struct ixgbe_vf_info *vfinfo =
2322                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2323         struct ixgbe_filter_info *filter_info =
2324                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2325         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2326         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2327         int vf;
2328
2329         PMD_INIT_FUNC_TRACE();
2330
2331         /* disable interrupts */
2332         ixgbe_disable_intr(hw);
2333
2334         /* reset the NIC */
2335         ixgbe_pf_reset_hw(hw);
2336         hw->adapter_stopped = 0;
2337
2338         /* stop adapter */
2339         ixgbe_stop_adapter(hw);
2340
2341         for (vf = 0; vfinfo != NULL &&
2342                      vf < dev->pci_dev->max_vfs; vf++)
2343                 vfinfo[vf].clear_to_send = false;
2344
2345         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2346                 /* Turn off the copper */
2347                 ixgbe_set_phy_power(hw, false);
2348         } else {
2349                 /* Turn off the laser */
2350                 ixgbe_disable_tx_laser(hw);
2351         }
2352
2353         ixgbe_dev_clear_queues(dev);
2354
2355         /* Clear stored conf */
2356         dev->data->scattered_rx = 0;
2357         dev->data->lro = 0;
2358
2359         /* Clear recorded link status */
2360         memset(&link, 0, sizeof(link));
2361         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2362
2363         /* Remove all ntuple filters of the device */
2364         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2365              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2366                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2367                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2368                              p_5tuple, entries);
2369                 rte_free(p_5tuple);
2370         }
2371         memset(filter_info->fivetuple_mask, 0,
2372                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2373
2374         if (!rte_intr_allow_others(intr_handle))
2375                 /* resume to the default handler */
2376                 rte_intr_callback_register(intr_handle,
2377                                            ixgbe_dev_interrupt_handler,
2378                                            (void *)dev);
2379
2380         /* Clean datapath event and queue/vec mapping */
2381         rte_intr_efd_disable(intr_handle);
2382         if (intr_handle->intr_vec != NULL) {
2383                 rte_free(intr_handle->intr_vec);
2384                 intr_handle->intr_vec = NULL;
2385         }
2386 }
2387
2388 /*
2389  * Set device link up: enable tx.
2390  */
2391 static int
2392 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2393 {
2394         struct ixgbe_hw *hw =
2395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396         if (hw->mac.type == ixgbe_mac_82599EB) {
2397 #ifdef RTE_NIC_BYPASS
2398                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2399                         /* Not suported in bypass mode */
2400                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2401                                      "by device id 0x%x", hw->device_id);
2402                         return -ENOTSUP;
2403                 }
2404 #endif
2405         }
2406
2407         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2408                 /* Turn on the copper */
2409                 ixgbe_set_phy_power(hw, true);
2410         } else {
2411                 /* Turn on the laser */
2412                 ixgbe_enable_tx_laser(hw);
2413         }
2414
2415         return 0;
2416 }
2417
2418 /*
2419  * Set device link down: disable tx.
2420  */
2421 static int
2422 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2423 {
2424         struct ixgbe_hw *hw =
2425                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2426         if (hw->mac.type == ixgbe_mac_82599EB) {
2427 #ifdef RTE_NIC_BYPASS
2428                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2429                         /* Not suported in bypass mode */
2430                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2431                                      "by device id 0x%x", hw->device_id);
2432                         return -ENOTSUP;
2433                 }
2434 #endif
2435         }
2436
2437         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2438                 /* Turn off the copper */
2439                 ixgbe_set_phy_power(hw, false);
2440         } else {
2441                 /* Turn off the laser */
2442                 ixgbe_disable_tx_laser(hw);
2443         }
2444
2445         return 0;
2446 }
2447
2448 /*
2449  * Reest and stop device.
2450  */
2451 static void
2452 ixgbe_dev_close(struct rte_eth_dev *dev)
2453 {
2454         struct ixgbe_hw *hw =
2455                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456
2457         PMD_INIT_FUNC_TRACE();
2458
2459         ixgbe_pf_reset_hw(hw);
2460
2461         ixgbe_dev_stop(dev);
2462         hw->adapter_stopped = 1;
2463
2464         ixgbe_dev_free_queues(dev);
2465
2466         ixgbe_disable_pcie_master(hw);
2467
2468         /* reprogram the RAR[0] in case user changed it. */
2469         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2470 }
2471
2472 static void
2473 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2474                            struct ixgbe_hw_stats *hw_stats,
2475                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2476                            uint64_t *total_qprc, uint64_t *total_qprdc)
2477 {
2478         uint32_t bprc, lxon, lxoff, total;
2479         uint32_t delta_gprc = 0;
2480         unsigned i;
2481         /* Workaround for RX byte count not including CRC bytes when CRC
2482 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2483          * is disabled.
2484 +        */
2485         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2486                         IXGBE_HLREG0_RXCRCSTRP);
2487
2488         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2489         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2490         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2491         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2492
2493         for (i = 0; i < 8; i++) {
2494                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2495
2496                 /* global total per queue */
2497                 hw_stats->mpc[i] += mp;
2498                 /* Running comprehensive total for stats display */
2499                 *total_missed_rx += hw_stats->mpc[i];
2500                 if (hw->mac.type == ixgbe_mac_82598EB) {
2501                         hw_stats->rnbc[i] +=
2502                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2503                         hw_stats->pxonrxc[i] +=
2504                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2505                         hw_stats->pxoffrxc[i] +=
2506                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2507                 } else {
2508                         hw_stats->pxonrxc[i] +=
2509                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2510                         hw_stats->pxoffrxc[i] +=
2511                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2512                         hw_stats->pxon2offc[i] +=
2513                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2514                 }
2515                 hw_stats->pxontxc[i] +=
2516                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2517                 hw_stats->pxofftxc[i] +=
2518                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2519         }
2520         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2521                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2522                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2523                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2524
2525                 delta_gprc += delta_qprc;
2526
2527                 hw_stats->qprc[i] += delta_qprc;
2528                 hw_stats->qptc[i] += delta_qptc;
2529
2530                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2531                 hw_stats->qbrc[i] +=
2532                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2533                 if (crc_strip == 0)
2534                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2535
2536                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2537                 hw_stats->qbtc[i] +=
2538                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2539
2540                 hw_stats->qprdc[i] += delta_qprdc;
2541                 *total_qprdc += hw_stats->qprdc[i];
2542
2543                 *total_qprc += hw_stats->qprc[i];
2544                 *total_qbrc += hw_stats->qbrc[i];
2545         }
2546         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2547         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2548         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2549
2550         /*
2551          * An errata states that gprc actually counts good + missed packets:
2552          * Workaround to set gprc to summated queue packet receives
2553          */
2554         hw_stats->gprc = *total_qprc;
2555
2556         if (hw->mac.type != ixgbe_mac_82598EB) {
2557                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2558                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2559                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2560                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2561                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2562                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2563                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2564                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2565         } else {
2566                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2567                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2568                 /* 82598 only has a counter in the high register */
2569                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2570                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2571                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2572         }
2573         uint64_t old_tpr = hw_stats->tpr;
2574
2575         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2576         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2577
2578         if (crc_strip == 0)
2579                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2580
2581         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2582         hw_stats->gptc += delta_gptc;
2583         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2584         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2585
2586         /*
2587          * Workaround: mprc hardware is incorrectly counting
2588          * broadcasts, so for now we subtract those.
2589          */
2590         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2591         hw_stats->bprc += bprc;
2592         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2593         if (hw->mac.type == ixgbe_mac_82598EB)
2594                 hw_stats->mprc -= bprc;
2595
2596         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2597         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2598         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2599         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2600         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2601         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2602
2603         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2604         hw_stats->lxontxc += lxon;
2605         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2606         hw_stats->lxofftxc += lxoff;
2607         total = lxon + lxoff;
2608
2609         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2610         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2611         hw_stats->gptc -= total;
2612         hw_stats->mptc -= total;
2613         hw_stats->ptc64 -= total;
2614         hw_stats->gotc -= total * ETHER_MIN_LEN;
2615
2616         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2617         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2618         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2619         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2620         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2621         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2622         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2623         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2624         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2625         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2626         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2627         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2628         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2629         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2630         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2631         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2632         /* Only read FCOE on 82599 */
2633         if (hw->mac.type != ixgbe_mac_82598EB) {
2634                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2635                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2636                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2637                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2638                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2639         }
2640
2641         /* Flow Director Stats registers */
2642         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2643         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2644 }
2645
2646 /*
2647  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2648  */
2649 static void
2650 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2651 {
2652         struct ixgbe_hw *hw =
2653                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654         struct ixgbe_hw_stats *hw_stats =
2655                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2656         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2657         unsigned i;
2658
2659         total_missed_rx = 0;
2660         total_qbrc = 0;
2661         total_qprc = 0;
2662         total_qprdc = 0;
2663
2664         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2665                         &total_qprc, &total_qprdc);
2666
2667         if (stats == NULL)
2668                 return;
2669
2670         /* Fill out the rte_eth_stats statistics structure */
2671         stats->ipackets = total_qprc;
2672         stats->ibytes = total_qbrc;
2673         stats->opackets = hw_stats->gptc;
2674         stats->obytes = hw_stats->gotc;
2675
2676         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2677                 stats->q_ipackets[i] = hw_stats->qprc[i];
2678                 stats->q_opackets[i] = hw_stats->qptc[i];
2679                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2680                 stats->q_obytes[i] = hw_stats->qbtc[i];
2681                 stats->q_errors[i] = hw_stats->qprdc[i];
2682         }
2683
2684         /* Rx Errors */
2685         stats->imissed  = total_missed_rx;
2686         stats->ierrors  = hw_stats->crcerrs +
2687                           hw_stats->mspdc +
2688                           hw_stats->rlec +
2689                           hw_stats->ruc +
2690                           hw_stats->roc +
2691                           hw_stats->illerrc +
2692                           hw_stats->errbc +
2693                           hw_stats->rfc +
2694                           hw_stats->fccrc +
2695                           hw_stats->fclast;
2696
2697         /* Tx Errors */
2698         stats->oerrors  = 0;
2699 }
2700
2701 static void
2702 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2703 {
2704         struct ixgbe_hw_stats *stats =
2705                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2706
2707         /* HW registers are cleared on read */
2708         ixgbe_dev_stats_get(dev, NULL);
2709
2710         /* Reset software totals */
2711         memset(stats, 0, sizeof(*stats));
2712 }
2713
2714 /* This function calculates the number of xstats based on the current config */
2715 static unsigned
2716 ixgbe_xstats_calc_num(void) {
2717         return IXGBE_NB_HW_STATS +
2718                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2719                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2720 }
2721
2722 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2723         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2724 {
2725         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2726         unsigned stat, i, count;
2727
2728         if (xstats_names != NULL) {
2729                 count = 0;
2730
2731                 /* Note: limit >= cnt_stats checked upstream
2732                  * in rte_eth_xstats_names()
2733                  */
2734
2735                 /* Extended stats from ixgbe_hw_stats */
2736                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2737                         xstats_names[count].id = count;
2738                         snprintf(xstats_names[count].name,
2739                                 sizeof(xstats_names[count].name),
2740                                 "%s",
2741                                 rte_ixgbe_stats_strings[i].name);
2742                         count++;
2743                 }
2744
2745                 /* RX Priority Stats */
2746                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2747                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2748                                 xstats_names[count].id = count;
2749                                 snprintf(xstats_names[count].name,
2750                                         sizeof(xstats_names[count].name),
2751                                         "rx_priority%u_%s", i,
2752                                         rte_ixgbe_rxq_strings[stat].name);
2753                                 count++;
2754                         }
2755                 }
2756
2757                 /* TX Priority Stats */
2758                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2759                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2760                                 xstats_names[count].id = count;
2761                                 snprintf(xstats_names[count].name,
2762                                         sizeof(xstats_names[count].name),
2763                                         "tx_priority%u_%s", i,
2764                                         rte_ixgbe_txq_strings[stat].name);
2765                                 count++;
2766                         }
2767                 }
2768         }
2769         return cnt_stats;
2770 }
2771
2772 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2773         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2774 {
2775         unsigned i;
2776
2777         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2778                 return -ENOMEM;
2779
2780         if (xstats_names != NULL)
2781                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2782                         snprintf(xstats_names[i].name,
2783                                 sizeof(xstats_names[i].name),
2784                                 "%s", rte_ixgbevf_stats_strings[i].name);
2785         return IXGBEVF_NB_XSTATS;
2786 }
2787
2788 static int
2789 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2790                                          unsigned n)
2791 {
2792         struct ixgbe_hw *hw =
2793                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794         struct ixgbe_hw_stats *hw_stats =
2795                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2796         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2797         unsigned i, stat, count = 0;
2798
2799         count = ixgbe_xstats_calc_num();
2800
2801         if (n < count)
2802                 return count;
2803
2804         total_missed_rx = 0;
2805         total_qbrc = 0;
2806         total_qprc = 0;
2807         total_qprdc = 0;
2808
2809         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2810                                    &total_qprc, &total_qprdc);
2811
2812         /* If this is a reset xstats is NULL, and we have cleared the
2813          * registers by reading them.
2814          */
2815         if (!xstats)
2816                 return 0;
2817
2818         /* Extended stats from ixgbe_hw_stats */
2819         count = 0;
2820         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2821                 xstats[count].id = count;
2822                 xstats[count].name[0] = '\0';
2823                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2824                                 rte_ixgbe_stats_strings[i].offset);
2825                 count++;
2826         }
2827
2828         /* RX Priority Stats */
2829         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2830                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2831                         xstats[count].id = count;
2832                         xstats[count].name[0] = '\0';
2833                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2834                                         rte_ixgbe_rxq_strings[stat].offset +
2835                                         (sizeof(uint64_t) * i));
2836                         count++;
2837                 }
2838         }
2839
2840         /* TX Priority Stats */
2841         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2842                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2843                         xstats[count].id = count;
2844                         xstats[count].name[0] = '\0';
2845                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2846                                         rte_ixgbe_txq_strings[stat].offset +
2847                                         (sizeof(uint64_t) * i));
2848                         count++;
2849                 }
2850         }
2851         return count;
2852 }
2853
2854 static void
2855 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2856 {
2857         struct ixgbe_hw_stats *stats =
2858                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2859
2860         unsigned count = ixgbe_xstats_calc_num();
2861
2862         /* HW registers are cleared on read */
2863         ixgbe_dev_xstats_get(dev, NULL, count);
2864
2865         /* Reset software totals */
2866         memset(stats, 0, sizeof(*stats));
2867 }
2868
2869 static void
2870 ixgbevf_update_stats(struct rte_eth_dev *dev)
2871 {
2872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2874                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2875
2876         /* Good Rx packet, include VF loopback */
2877         UPDATE_VF_STAT(IXGBE_VFGPRC,
2878             hw_stats->last_vfgprc, hw_stats->vfgprc);
2879
2880         /* Good Rx octets, include VF loopback */
2881         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2882             hw_stats->last_vfgorc, hw_stats->vfgorc);
2883
2884         /* Good Tx packet, include VF loopback */
2885         UPDATE_VF_STAT(IXGBE_VFGPTC,
2886             hw_stats->last_vfgptc, hw_stats->vfgptc);
2887
2888         /* Good Tx octets, include VF loopback */
2889         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2890             hw_stats->last_vfgotc, hw_stats->vfgotc);
2891
2892         /* Rx Multicst Packet */
2893         UPDATE_VF_STAT(IXGBE_VFMPRC,
2894             hw_stats->last_vfmprc, hw_stats->vfmprc);
2895 }
2896
2897 static int
2898 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2899                        unsigned n)
2900 {
2901         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2902                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2903         unsigned i;
2904
2905         if (n < IXGBEVF_NB_XSTATS)
2906                 return IXGBEVF_NB_XSTATS;
2907
2908         ixgbevf_update_stats(dev);
2909
2910         if (!xstats)
2911                 return 0;
2912
2913         /* Extended stats */
2914         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2915                 xstats[i].id = i;
2916                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2917                         rte_ixgbevf_stats_strings[i].offset);
2918         }
2919
2920         return IXGBEVF_NB_XSTATS;
2921 }
2922
2923 static void
2924 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2925 {
2926         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2927                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2928
2929         ixgbevf_update_stats(dev);
2930
2931         if (stats == NULL)
2932                 return;
2933
2934         stats->ipackets = hw_stats->vfgprc;
2935         stats->ibytes = hw_stats->vfgorc;
2936         stats->opackets = hw_stats->vfgptc;
2937         stats->obytes = hw_stats->vfgotc;
2938 }
2939
2940 static void
2941 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2942 {
2943         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2944                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2945
2946         /* Sync HW register to the last stats */
2947         ixgbevf_dev_stats_get(dev, NULL);
2948
2949         /* reset HW current stats*/
2950         hw_stats->vfgprc = 0;
2951         hw_stats->vfgorc = 0;
2952         hw_stats->vfgptc = 0;
2953         hw_stats->vfgotc = 0;
2954 }
2955
2956 static void
2957 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2958 {
2959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2961
2962         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2963         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2964         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
2965                 /*
2966                  * When DCB/VT is off, maximum number of queues changes,
2967                  * except for 82598EB, which remains constant.
2968                  */
2969                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2970                                 hw->mac.type != ixgbe_mac_82598EB)
2971                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
2972         }
2973         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2974         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2975         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2976         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2977         dev_info->max_vfs = dev->pci_dev->max_vfs;
2978         if (hw->mac.type == ixgbe_mac_82598EB)
2979                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2980         else
2981                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2982         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2983         dev_info->rx_offload_capa =
2984                 DEV_RX_OFFLOAD_VLAN_STRIP |
2985                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2986                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2987                 DEV_RX_OFFLOAD_TCP_CKSUM;
2988
2989         /*
2990          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2991          * mode.
2992          */
2993         if ((hw->mac.type == ixgbe_mac_82599EB ||
2994              hw->mac.type == ixgbe_mac_X540) &&
2995             !RTE_ETH_DEV_SRIOV(dev).active)
2996                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2997
2998         if (hw->mac.type == ixgbe_mac_X550 ||
2999             hw->mac.type == ixgbe_mac_X550EM_x ||
3000             hw->mac.type == ixgbe_mac_X550EM_a)
3001                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3002
3003         dev_info->tx_offload_capa =
3004                 DEV_TX_OFFLOAD_VLAN_INSERT |
3005                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3006                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3007                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3008                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3009                 DEV_TX_OFFLOAD_TCP_TSO;
3010
3011         if (hw->mac.type == ixgbe_mac_X550 ||
3012             hw->mac.type == ixgbe_mac_X550EM_x ||
3013             hw->mac.type == ixgbe_mac_X550EM_a)
3014                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3015
3016         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3017                 .rx_thresh = {
3018                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3019                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3020                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3021                 },
3022                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3023                 .rx_drop_en = 0,
3024         };
3025
3026         dev_info->default_txconf = (struct rte_eth_txconf) {
3027                 .tx_thresh = {
3028                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3029                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3030                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3031                 },
3032                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3033                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3034                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3035                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3036         };
3037
3038         dev_info->rx_desc_lim = rx_desc_lim;
3039         dev_info->tx_desc_lim = tx_desc_lim;
3040
3041         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3042         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3043         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3044
3045         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3046         if (hw->mac.type == ixgbe_mac_X540 ||
3047             hw->mac.type == ixgbe_mac_X540_vf ||
3048             hw->mac.type == ixgbe_mac_X550 ||
3049             hw->mac.type == ixgbe_mac_X550_vf) {
3050                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3051         }
3052 }
3053
3054 static const uint32_t *
3055 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3056 {
3057         static const uint32_t ptypes[] = {
3058                 /* For non-vec functions,
3059                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3060                  * for vec functions,
3061                  * refers to _recv_raw_pkts_vec().
3062                  */
3063                 RTE_PTYPE_L2_ETHER,
3064                 RTE_PTYPE_L3_IPV4,
3065                 RTE_PTYPE_L3_IPV4_EXT,
3066                 RTE_PTYPE_L3_IPV6,
3067                 RTE_PTYPE_L3_IPV6_EXT,
3068                 RTE_PTYPE_L4_SCTP,
3069                 RTE_PTYPE_L4_TCP,
3070                 RTE_PTYPE_L4_UDP,
3071                 RTE_PTYPE_TUNNEL_IP,
3072                 RTE_PTYPE_INNER_L3_IPV6,
3073                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3074                 RTE_PTYPE_INNER_L4_TCP,
3075                 RTE_PTYPE_INNER_L4_UDP,
3076                 RTE_PTYPE_UNKNOWN
3077         };
3078
3079         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3080             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3081             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3082             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3083                 return ptypes;
3084         return NULL;
3085 }
3086
3087 static void
3088 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3089                      struct rte_eth_dev_info *dev_info)
3090 {
3091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3092
3093         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3094         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3095         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3096         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3097         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3098         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3099         dev_info->max_vfs = dev->pci_dev->max_vfs;
3100         if (hw->mac.type == ixgbe_mac_82598EB)
3101                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3102         else
3103                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3104         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3105                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3106                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3107                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3108         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3109                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3110                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3111                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3112                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3113                                 DEV_TX_OFFLOAD_TCP_TSO;
3114
3115         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3116                 .rx_thresh = {
3117                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3118                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3119                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3120                 },
3121                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3122                 .rx_drop_en = 0,
3123         };
3124
3125         dev_info->default_txconf = (struct rte_eth_txconf) {
3126                 .tx_thresh = {
3127                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3128                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3129                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3130                 },
3131                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3132                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3133                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3134                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3135         };
3136
3137         dev_info->rx_desc_lim = rx_desc_lim;
3138         dev_info->tx_desc_lim = tx_desc_lim;
3139 }
3140
3141 /* return 0 means link status changed, -1 means not changed */
3142 static int
3143 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3144 {
3145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3146         struct rte_eth_link link, old;
3147         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3148         int link_up;
3149         int diag;
3150
3151         link.link_status = ETH_LINK_DOWN;
3152         link.link_speed = 0;
3153         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3154         memset(&old, 0, sizeof(old));
3155         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3156
3157         hw->mac.get_link_status = true;
3158
3159         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3160         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3161                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3162         else
3163                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3164
3165         if (diag != 0) {
3166                 link.link_speed = ETH_SPEED_NUM_100M;
3167                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3168                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3169                 if (link.link_status == old.link_status)
3170                         return -1;
3171                 return 0;
3172         }
3173
3174         if (link_up == 0) {
3175                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3176                 if (link.link_status == old.link_status)
3177                         return -1;
3178                 return 0;
3179         }
3180         link.link_status = ETH_LINK_UP;
3181         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3182
3183         switch (link_speed) {
3184         default:
3185         case IXGBE_LINK_SPEED_UNKNOWN:
3186                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3187                 link.link_speed = ETH_SPEED_NUM_100M;
3188                 break;
3189
3190         case IXGBE_LINK_SPEED_100_FULL:
3191                 link.link_speed = ETH_SPEED_NUM_100M;
3192                 break;
3193
3194         case IXGBE_LINK_SPEED_1GB_FULL:
3195                 link.link_speed = ETH_SPEED_NUM_1G;
3196                 break;
3197
3198         case IXGBE_LINK_SPEED_10GB_FULL:
3199                 link.link_speed = ETH_SPEED_NUM_10G;
3200                 break;
3201         }
3202         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3203
3204         if (link.link_status == old.link_status)
3205                 return -1;
3206
3207         return 0;
3208 }
3209
3210 static void
3211 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3212 {
3213         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214         uint32_t fctrl;
3215
3216         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3217         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3218         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3219 }
3220
3221 static void
3222 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3223 {
3224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3225         uint32_t fctrl;
3226
3227         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3228         fctrl &= (~IXGBE_FCTRL_UPE);
3229         if (dev->data->all_multicast == 1)
3230                 fctrl |= IXGBE_FCTRL_MPE;
3231         else
3232                 fctrl &= (~IXGBE_FCTRL_MPE);
3233         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3234 }
3235
3236 static void
3237 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3238 {
3239         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3240         uint32_t fctrl;
3241
3242         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3243         fctrl |= IXGBE_FCTRL_MPE;
3244         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3245 }
3246
3247 static void
3248 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3249 {
3250         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3251         uint32_t fctrl;
3252
3253         if (dev->data->promiscuous == 1)
3254                 return; /* must remain in all_multicast mode */
3255
3256         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3257         fctrl &= (~IXGBE_FCTRL_MPE);
3258         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3259 }
3260
3261 /**
3262  * It clears the interrupt causes and enables the interrupt.
3263  * It will be called once only during nic initialized.
3264  *
3265  * @param dev
3266  *  Pointer to struct rte_eth_dev.
3267  *
3268  * @return
3269  *  - On success, zero.
3270  *  - On failure, a negative value.
3271  */
3272 static int
3273 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3274 {
3275         struct ixgbe_interrupt *intr =
3276                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3277
3278         ixgbe_dev_link_status_print(dev);
3279         intr->mask |= IXGBE_EICR_LSC;
3280
3281         return 0;
3282 }
3283
3284 /**
3285  * It clears the interrupt causes and enables the interrupt.
3286  * It will be called once only during nic initialized.
3287  *
3288  * @param dev
3289  *  Pointer to struct rte_eth_dev.
3290  *
3291  * @return
3292  *  - On success, zero.
3293  *  - On failure, a negative value.
3294  */
3295 static int
3296 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3297 {
3298         struct ixgbe_interrupt *intr =
3299                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3300
3301         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3302
3303         return 0;
3304 }
3305
3306 /*
3307  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3308  *
3309  * @param dev
3310  *  Pointer to struct rte_eth_dev.
3311  *
3312  * @return
3313  *  - On success, zero.
3314  *  - On failure, a negative value.
3315  */
3316 static int
3317 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3318 {
3319         uint32_t eicr;
3320         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3321         struct ixgbe_interrupt *intr =
3322                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3323
3324         /* clear all cause mask */
3325         ixgbe_disable_intr(hw);
3326
3327         /* read-on-clear nic registers here */
3328         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3329         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3330
3331         intr->flags = 0;
3332
3333         /* set flag for async link update */
3334         if (eicr & IXGBE_EICR_LSC)
3335                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3336
3337         if (eicr & IXGBE_EICR_MAILBOX)
3338                 intr->flags |= IXGBE_FLAG_MAILBOX;
3339
3340         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3341             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3342             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3343                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3344
3345         return 0;
3346 }
3347
3348 /**
3349  * It gets and then prints the link status.
3350  *
3351  * @param dev
3352  *  Pointer to struct rte_eth_dev.
3353  *
3354  * @return
3355  *  - On success, zero.
3356  *  - On failure, a negative value.
3357  */
3358 static void
3359 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3360 {
3361         struct rte_eth_link link;
3362
3363         memset(&link, 0, sizeof(link));
3364         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3365         if (link.link_status) {
3366                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3367                                         (int)(dev->data->port_id),
3368                                         (unsigned)link.link_speed,
3369                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3370                                         "full-duplex" : "half-duplex");
3371         } else {
3372                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3373                                 (int)(dev->data->port_id));
3374         }
3375         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3376                                 dev->pci_dev->addr.domain,
3377                                 dev->pci_dev->addr.bus,
3378                                 dev->pci_dev->addr.devid,
3379                                 dev->pci_dev->addr.function);
3380 }
3381
3382 /*
3383  * It executes link_update after knowing an interrupt occurred.
3384  *
3385  * @param dev
3386  *  Pointer to struct rte_eth_dev.
3387  *
3388  * @return
3389  *  - On success, zero.
3390  *  - On failure, a negative value.
3391  */
3392 static int
3393 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3394 {
3395         struct ixgbe_interrupt *intr =
3396                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3397         int64_t timeout;
3398         struct rte_eth_link link;
3399         int intr_enable_delay = false;
3400         struct ixgbe_hw *hw =
3401                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3402
3403         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3404
3405         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3406                 ixgbe_pf_mbx_process(dev);
3407                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3408         }
3409
3410         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3411                 ixgbe_handle_lasi(hw);
3412                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3413         }
3414
3415         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3416                 /* get the link status before link update, for predicting later */
3417                 memset(&link, 0, sizeof(link));
3418                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3419
3420                 ixgbe_dev_link_update(dev, 0);
3421
3422                 /* likely to up */
3423                 if (!link.link_status)
3424                         /* handle it 1 sec later, wait it being stable */
3425                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3426                 /* likely to down */
3427                 else
3428                         /* handle it 4 sec later, wait it being stable */
3429                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3430
3431                 ixgbe_dev_link_status_print(dev);
3432
3433                 intr_enable_delay = true;
3434         }
3435
3436         if (intr_enable_delay) {
3437                 if (rte_eal_alarm_set(timeout * 1000,
3438                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3439                         PMD_DRV_LOG(ERR, "Error setting alarm");
3440         } else {
3441                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3442                 ixgbe_enable_intr(dev);
3443                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3444         }
3445
3446
3447         return 0;
3448 }
3449
3450 /**
3451  * Interrupt handler which shall be registered for alarm callback for delayed
3452  * handling specific interrupt to wait for the stable nic state. As the
3453  * NIC interrupt state is not stable for ixgbe after link is just down,
3454  * it needs to wait 4 seconds to get the stable status.
3455  *
3456  * @param handle
3457  *  Pointer to interrupt handle.
3458  * @param param
3459  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3460  *
3461  * @return
3462  *  void
3463  */
3464 static void
3465 ixgbe_dev_interrupt_delayed_handler(void *param)
3466 {
3467         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3468         struct ixgbe_interrupt *intr =
3469                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3470         struct ixgbe_hw *hw =
3471                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3472         uint32_t eicr;
3473
3474         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3475         if (eicr & IXGBE_EICR_MAILBOX)
3476                 ixgbe_pf_mbx_process(dev);
3477
3478         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3479                 ixgbe_handle_lasi(hw);
3480                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3481         }
3482
3483         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3484                 ixgbe_dev_link_update(dev, 0);
3485                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3486                 ixgbe_dev_link_status_print(dev);
3487                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3488         }
3489
3490         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3491         ixgbe_enable_intr(dev);
3492         rte_intr_enable(&(dev->pci_dev->intr_handle));
3493 }
3494
3495 /**
3496  * Interrupt handler triggered by NIC  for handling
3497  * specific interrupt.
3498  *
3499  * @param handle
3500  *  Pointer to interrupt handle.
3501  * @param param
3502  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3503  *
3504  * @return
3505  *  void
3506  */
3507 static void
3508 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3509                             void *param)
3510 {
3511         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3512
3513         ixgbe_dev_interrupt_get_status(dev);
3514         ixgbe_dev_interrupt_action(dev);
3515 }
3516
3517 static int
3518 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3519 {
3520         struct ixgbe_hw *hw;
3521
3522         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3523         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3524 }
3525
3526 static int
3527 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3528 {
3529         struct ixgbe_hw *hw;
3530
3531         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3532         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3533 }
3534
3535 static int
3536 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3537 {
3538         struct ixgbe_hw *hw;
3539         uint32_t mflcn_reg;
3540         uint32_t fccfg_reg;
3541         int rx_pause;
3542         int tx_pause;
3543
3544         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3545
3546         fc_conf->pause_time = hw->fc.pause_time;
3547         fc_conf->high_water = hw->fc.high_water[0];
3548         fc_conf->low_water = hw->fc.low_water[0];
3549         fc_conf->send_xon = hw->fc.send_xon;
3550         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3551
3552         /*
3553          * Return rx_pause status according to actual setting of
3554          * MFLCN register.
3555          */
3556         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3557         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3558                 rx_pause = 1;
3559         else
3560                 rx_pause = 0;
3561
3562         /*
3563          * Return tx_pause status according to actual setting of
3564          * FCCFG register.
3565          */
3566         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3567         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3568                 tx_pause = 1;
3569         else
3570                 tx_pause = 0;
3571
3572         if (rx_pause && tx_pause)
3573                 fc_conf->mode = RTE_FC_FULL;
3574         else if (rx_pause)
3575                 fc_conf->mode = RTE_FC_RX_PAUSE;
3576         else if (tx_pause)
3577                 fc_conf->mode = RTE_FC_TX_PAUSE;
3578         else
3579                 fc_conf->mode = RTE_FC_NONE;
3580
3581         return 0;
3582 }
3583
3584 static int
3585 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3586 {
3587         struct ixgbe_hw *hw;
3588         int err;
3589         uint32_t rx_buf_size;
3590         uint32_t max_high_water;
3591         uint32_t mflcn;
3592         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3593                 ixgbe_fc_none,
3594                 ixgbe_fc_rx_pause,
3595                 ixgbe_fc_tx_pause,
3596                 ixgbe_fc_full
3597         };
3598
3599         PMD_INIT_FUNC_TRACE();
3600
3601         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3602         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3603         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3604
3605         /*
3606          * At least reserve one Ethernet frame for watermark
3607          * high_water/low_water in kilo bytes for ixgbe
3608          */
3609         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3610         if ((fc_conf->high_water > max_high_water) ||
3611                 (fc_conf->high_water < fc_conf->low_water)) {
3612                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3613                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3614                 return -EINVAL;
3615         }
3616
3617         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3618         hw->fc.pause_time     = fc_conf->pause_time;
3619         hw->fc.high_water[0]  = fc_conf->high_water;
3620         hw->fc.low_water[0]   = fc_conf->low_water;
3621         hw->fc.send_xon       = fc_conf->send_xon;
3622         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3623
3624         err = ixgbe_fc_enable(hw);
3625
3626         /* Not negotiated is not an error case */
3627         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3628
3629                 /* check if we want to forward MAC frames - driver doesn't have native
3630                  * capability to do that, so we'll write the registers ourselves */
3631
3632                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3633
3634                 /* set or clear MFLCN.PMCF bit depending on configuration */
3635                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3636                         mflcn |= IXGBE_MFLCN_PMCF;
3637                 else
3638                         mflcn &= ~IXGBE_MFLCN_PMCF;
3639
3640                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3641                 IXGBE_WRITE_FLUSH(hw);
3642
3643                 return 0;
3644         }
3645
3646         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3647         return -EIO;
3648 }
3649
3650 /**
3651  *  ixgbe_pfc_enable_generic - Enable flow control
3652  *  @hw: pointer to hardware structure
3653  *  @tc_num: traffic class number
3654  *  Enable flow control according to the current settings.
3655  */
3656 static int
3657 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3658 {
3659         int ret_val = 0;
3660         uint32_t mflcn_reg, fccfg_reg;
3661         uint32_t reg;
3662         uint32_t fcrtl, fcrth;
3663         uint8_t i;
3664         uint8_t nb_rx_en;
3665
3666         /* Validate the water mark configuration */
3667         if (!hw->fc.pause_time) {
3668                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3669                 goto out;
3670         }
3671
3672         /* Low water mark of zero causes XOFF floods */
3673         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3674                  /* High/Low water can not be 0 */
3675                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3676                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3677                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3678                         goto out;
3679                 }
3680
3681                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3682                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3683                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3684                         goto out;
3685                 }
3686         }
3687         /* Negotiate the fc mode to use */
3688         ixgbe_fc_autoneg(hw);
3689
3690         /* Disable any previous flow control settings */
3691         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3692         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3693
3694         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3695         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3696
3697         switch (hw->fc.current_mode) {
3698         case ixgbe_fc_none:
3699                 /*
3700                  * If the count of enabled RX Priority Flow control >1,
3701                  * and the TX pause can not be disabled
3702                  */
3703                 nb_rx_en = 0;
3704                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3705                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3706                         if (reg & IXGBE_FCRTH_FCEN)
3707                                 nb_rx_en++;
3708                 }
3709                 if (nb_rx_en > 1)
3710                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3711                 break;
3712         case ixgbe_fc_rx_pause:
3713                 /*
3714                  * Rx Flow control is enabled and Tx Flow control is
3715                  * disabled by software override. Since there really
3716                  * isn't a way to advertise that we are capable of RX
3717                  * Pause ONLY, we will advertise that we support both
3718                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3719                  * disable the adapter's ability to send PAUSE frames.
3720                  */
3721                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3722                 /*
3723                  * If the count of enabled RX Priority Flow control >1,
3724                  * and the TX pause can not be disabled
3725                  */
3726                 nb_rx_en = 0;
3727                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3728                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3729                         if (reg & IXGBE_FCRTH_FCEN)
3730                                 nb_rx_en++;
3731                 }
3732                 if (nb_rx_en > 1)
3733                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3734                 break;
3735         case ixgbe_fc_tx_pause:
3736                 /*
3737                  * Tx Flow control is enabled, and Rx Flow control is
3738                  * disabled by software override.
3739                  */
3740                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3741                 break;
3742         case ixgbe_fc_full:
3743                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3744                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3745                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3746                 break;
3747         default:
3748                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3749                 ret_val = IXGBE_ERR_CONFIG;
3750                 goto out;
3751         }
3752
3753         /* Set 802.3x based flow control settings. */
3754         mflcn_reg |= IXGBE_MFLCN_DPF;
3755         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3756         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3757
3758         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3759         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3760                 hw->fc.high_water[tc_num]) {
3761                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3762                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3763                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3764         } else {
3765                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3766                 /*
3767                  * In order to prevent Tx hangs when the internal Tx
3768                  * switch is enabled we must set the high water mark
3769                  * to the maximum FCRTH value.  This allows the Tx
3770                  * switch to function even under heavy Rx workloads.
3771                  */
3772                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3773         }
3774         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3775
3776         /* Configure pause time (2 TCs per register) */
3777         reg = hw->fc.pause_time * 0x00010001;
3778         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3779                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3780
3781         /* Configure flow control refresh threshold value */
3782         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3783
3784 out:
3785         return ret_val;
3786 }
3787
3788 static int
3789 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3790 {
3791         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3792         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3793
3794         if (hw->mac.type != ixgbe_mac_82598EB) {
3795                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3796         }
3797         return ret_val;
3798 }
3799
3800 static int
3801 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3802 {
3803         int err;
3804         uint32_t rx_buf_size;
3805         uint32_t max_high_water;
3806         uint8_t tc_num;
3807         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3808         struct ixgbe_hw *hw =
3809                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3810         struct ixgbe_dcb_config *dcb_config =
3811                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3812
3813         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3814                 ixgbe_fc_none,
3815                 ixgbe_fc_rx_pause,
3816                 ixgbe_fc_tx_pause,
3817                 ixgbe_fc_full
3818         };
3819
3820         PMD_INIT_FUNC_TRACE();
3821
3822         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3823         tc_num = map[pfc_conf->priority];
3824         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3825         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3826         /*
3827          * At least reserve one Ethernet frame for watermark
3828          * high_water/low_water in kilo bytes for ixgbe
3829          */
3830         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3831         if ((pfc_conf->fc.high_water > max_high_water) ||
3832             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3833                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3834                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3835                 return -EINVAL;
3836         }
3837
3838         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3839         hw->fc.pause_time = pfc_conf->fc.pause_time;
3840         hw->fc.send_xon = pfc_conf->fc.send_xon;
3841         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3842         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3843
3844         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3845
3846         /* Not negotiated is not an error case */
3847         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3848                 return 0;
3849
3850         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3851         return -EIO;
3852 }
3853
3854 static int
3855 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3856                           struct rte_eth_rss_reta_entry64 *reta_conf,
3857                           uint16_t reta_size)
3858 {
3859         uint16_t i, sp_reta_size;
3860         uint8_t j, mask;
3861         uint32_t reta, r;
3862         uint16_t idx, shift;
3863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3864         uint32_t reta_reg;
3865
3866         PMD_INIT_FUNC_TRACE();
3867
3868         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3869                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3870                         "NIC.");
3871                 return -ENOTSUP;
3872         }
3873
3874         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3875         if (reta_size != sp_reta_size) {
3876                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3877                         "(%d) doesn't match the number hardware can supported "
3878                         "(%d)\n", reta_size, sp_reta_size);
3879                 return -EINVAL;
3880         }
3881
3882         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3883                 idx = i / RTE_RETA_GROUP_SIZE;
3884                 shift = i % RTE_RETA_GROUP_SIZE;
3885                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3886                                                 IXGBE_4_BIT_MASK);
3887                 if (!mask)
3888                         continue;
3889                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3890                 if (mask == IXGBE_4_BIT_MASK)
3891                         r = 0;
3892                 else
3893                         r = IXGBE_READ_REG(hw, reta_reg);
3894                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3895                         if (mask & (0x1 << j))
3896                                 reta |= reta_conf[idx].reta[shift + j] <<
3897                                                         (CHAR_BIT * j);
3898                         else
3899                                 reta |= r & (IXGBE_8_BIT_MASK <<
3900                                                 (CHAR_BIT * j));
3901                 }
3902                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3903         }
3904
3905         return 0;
3906 }
3907
3908 static int
3909 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3910                          struct rte_eth_rss_reta_entry64 *reta_conf,
3911                          uint16_t reta_size)
3912 {
3913         uint16_t i, sp_reta_size;
3914         uint8_t j, mask;
3915         uint32_t reta;
3916         uint16_t idx, shift;
3917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3918         uint32_t reta_reg;
3919
3920         PMD_INIT_FUNC_TRACE();
3921         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3922         if (reta_size != sp_reta_size) {
3923                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3924                         "(%d) doesn't match the number hardware can supported "
3925                         "(%d)\n", reta_size, sp_reta_size);
3926                 return -EINVAL;
3927         }
3928
3929         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3930                 idx = i / RTE_RETA_GROUP_SIZE;
3931                 shift = i % RTE_RETA_GROUP_SIZE;
3932                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3933                                                 IXGBE_4_BIT_MASK);
3934                 if (!mask)
3935                         continue;
3936
3937                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3938                 reta = IXGBE_READ_REG(hw, reta_reg);
3939                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3940                         if (mask & (0x1 << j))
3941                                 reta_conf[idx].reta[shift + j] =
3942                                         ((reta >> (CHAR_BIT * j)) &
3943                                                 IXGBE_8_BIT_MASK);
3944                 }
3945         }
3946
3947         return 0;
3948 }
3949
3950 static void
3951 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3952                                 uint32_t index, uint32_t pool)
3953 {
3954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3955         uint32_t enable_addr = 1;
3956
3957         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3958 }
3959
3960 static void
3961 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3962 {
3963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3964
3965         ixgbe_clear_rar(hw, index);
3966 }
3967
3968 static void
3969 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3970 {
3971         ixgbe_remove_rar(dev, 0);
3972
3973         ixgbe_add_rar(dev, addr, 0, 0);
3974 }
3975
3976 static int
3977 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3978 {
3979         uint32_t hlreg0;
3980         uint32_t maxfrs;
3981         struct ixgbe_hw *hw;
3982         struct rte_eth_dev_info dev_info;
3983         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3984
3985         ixgbe_dev_info_get(dev, &dev_info);
3986
3987         /* check that mtu is within the allowed range */
3988         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3989                 return -EINVAL;
3990
3991         /* refuse mtu that requires the support of scattered packets when this
3992          * feature has not been enabled before.
3993          */
3994         if (!dev->data->scattered_rx &&
3995             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3996              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3997                 return -EINVAL;
3998
3999         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4000         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4001
4002         /* switch to jumbo mode if needed */
4003         if (frame_size > ETHER_MAX_LEN) {
4004                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4005                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4006         } else {
4007                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4008                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4009         }
4010         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4011
4012         /* update max frame size */
4013         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4014
4015         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4016         maxfrs &= 0x0000FFFF;
4017         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4018         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4019
4020         return 0;
4021 }
4022
4023 /*
4024  * Virtual Function operations
4025  */
4026 static void
4027 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4028 {
4029         PMD_INIT_FUNC_TRACE();
4030
4031         /* Clear interrupt mask to stop from interrupts being generated */
4032         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4033
4034         IXGBE_WRITE_FLUSH(hw);
4035 }
4036
4037 static void
4038 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4039 {
4040         PMD_INIT_FUNC_TRACE();
4041
4042         /* VF enable interrupt autoclean */
4043         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4044         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4045         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4046
4047         IXGBE_WRITE_FLUSH(hw);
4048 }
4049
4050 static int
4051 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4052 {
4053         struct rte_eth_conf *conf = &dev->data->dev_conf;
4054         struct ixgbe_adapter *adapter =
4055                         (struct ixgbe_adapter *)dev->data->dev_private;
4056
4057         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4058                      dev->data->port_id);
4059
4060         /*
4061          * VF has no ability to enable/disable HW CRC
4062          * Keep the persistent behavior the same as Host PF
4063          */
4064 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4065         if (!conf->rxmode.hw_strip_crc) {
4066                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4067                 conf->rxmode.hw_strip_crc = 1;
4068         }
4069 #else
4070         if (conf->rxmode.hw_strip_crc) {
4071                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4072                 conf->rxmode.hw_strip_crc = 0;
4073         }
4074 #endif
4075
4076         /*
4077          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4078          * allocation or vector Rx preconditions we will reset it.
4079          */
4080         adapter->rx_bulk_alloc_allowed = true;
4081         adapter->rx_vec_allowed = true;
4082
4083         return 0;
4084 }
4085
4086 static int
4087 ixgbevf_dev_start(struct rte_eth_dev *dev)
4088 {
4089         struct ixgbe_hw *hw =
4090                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4091         uint32_t intr_vector = 0;
4092         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4093
4094         int err, mask = 0;
4095
4096         PMD_INIT_FUNC_TRACE();
4097
4098         hw->mac.ops.reset_hw(hw);
4099         hw->mac.get_link_status = true;
4100
4101         /* negotiate mailbox API version to use with the PF. */
4102         ixgbevf_negotiate_api(hw);
4103
4104         ixgbevf_dev_tx_init(dev);
4105
4106         /* This can fail when allocating mbufs for descriptor rings */
4107         err = ixgbevf_dev_rx_init(dev);
4108         if (err) {
4109                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4110                 ixgbe_dev_clear_queues(dev);
4111                 return err;
4112         }
4113
4114         /* Set vfta */
4115         ixgbevf_set_vfta_all(dev, 1);
4116
4117         /* Set HW strip */
4118         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4119                 ETH_VLAN_EXTEND_MASK;
4120         ixgbevf_vlan_offload_set(dev, mask);
4121
4122         ixgbevf_dev_rxtx_start(dev);
4123
4124         /* check and configure queue intr-vector mapping */
4125         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4126                 intr_vector = dev->data->nb_rx_queues;
4127                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4128                         return -1;
4129         }
4130
4131         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4132                 intr_handle->intr_vec =
4133                         rte_zmalloc("intr_vec",
4134                                     dev->data->nb_rx_queues * sizeof(int), 0);
4135                 if (intr_handle->intr_vec == NULL) {
4136                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4137                                      " intr_vec\n", dev->data->nb_rx_queues);
4138                         return -ENOMEM;
4139                 }
4140         }
4141         ixgbevf_configure_msix(dev);
4142
4143         rte_intr_enable(intr_handle);
4144
4145         /* Re-enable interrupt for VF */
4146         ixgbevf_intr_enable(hw);
4147
4148         return 0;
4149 }
4150
4151 static void
4152 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4153 {
4154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4155         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4156
4157         PMD_INIT_FUNC_TRACE();
4158
4159         hw->adapter_stopped = 1;
4160         ixgbe_stop_adapter(hw);
4161
4162         /*
4163           * Clear what we set, but we still keep shadow_vfta to
4164           * restore after device starts
4165           */
4166         ixgbevf_set_vfta_all(dev, 0);
4167
4168         /* Clear stored conf */
4169         dev->data->scattered_rx = 0;
4170
4171         ixgbe_dev_clear_queues(dev);
4172
4173         /* Clean datapath event and queue/vec mapping */
4174         rte_intr_efd_disable(intr_handle);
4175         if (intr_handle->intr_vec != NULL) {
4176                 rte_free(intr_handle->intr_vec);
4177                 intr_handle->intr_vec = NULL;
4178         }
4179 }
4180
4181 static void
4182 ixgbevf_dev_close(struct rte_eth_dev *dev)
4183 {
4184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4185
4186         PMD_INIT_FUNC_TRACE();
4187
4188         ixgbe_reset_hw(hw);
4189
4190         ixgbevf_dev_stop(dev);
4191
4192         ixgbe_dev_free_queues(dev);
4193
4194         /**
4195          * Remove the VF MAC address ro ensure
4196          * that the VF traffic goes to the PF
4197          * after stop, close and detach of the VF
4198          **/
4199         ixgbevf_remove_mac_addr(dev, 0);
4200 }
4201
4202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4203 {
4204         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4205         struct ixgbe_vfta *shadow_vfta =
4206                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4207         int i = 0, j = 0, vfta = 0, mask = 1;
4208
4209         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4210                 vfta = shadow_vfta->vfta[i];
4211                 if (vfta) {
4212                         mask = 1;
4213                         for (j = 0; j < 32; j++) {
4214                                 if (vfta & mask)
4215                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4216                                 mask <<= 1;
4217                         }
4218                 }
4219         }
4220
4221 }
4222
4223 static int
4224 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4225 {
4226         struct ixgbe_hw *hw =
4227                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4228         struct ixgbe_vfta *shadow_vfta =
4229                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4230         uint32_t vid_idx = 0;
4231         uint32_t vid_bit = 0;
4232         int ret = 0;
4233
4234         PMD_INIT_FUNC_TRACE();
4235
4236         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4237         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4238         if (ret) {
4239                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4240                 return ret;
4241         }
4242         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4243         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4244
4245         /* Save what we set and retore it after device reset */
4246         if (on)
4247                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4248         else
4249                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4250
4251         return 0;
4252 }
4253
4254 static void
4255 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4256 {
4257         struct ixgbe_hw *hw =
4258                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4259         uint32_t ctrl;
4260
4261         PMD_INIT_FUNC_TRACE();
4262
4263         if (queue >= hw->mac.max_rx_queues)
4264                 return;
4265
4266         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4267         if (on)
4268                 ctrl |= IXGBE_RXDCTL_VME;
4269         else
4270                 ctrl &= ~IXGBE_RXDCTL_VME;
4271         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4272
4273         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4274 }
4275
4276 static void
4277 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4278 {
4279         struct ixgbe_hw *hw =
4280                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4281         uint16_t i;
4282         int on = 0;
4283
4284         /* VF function only support hw strip feature, others are not support */
4285         if (mask & ETH_VLAN_STRIP_MASK) {
4286                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4287
4288                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4289                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4290         }
4291 }
4292
4293 static int
4294 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4295 {
4296         uint32_t reg_val;
4297
4298         /* we only need to do this if VMDq is enabled */
4299         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4300         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4301                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4302                 return -1;
4303         }
4304
4305         return 0;
4306 }
4307
4308 static uint32_t
4309 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4310 {
4311         uint32_t vector = 0;
4312
4313         switch (hw->mac.mc_filter_type) {
4314         case 0:   /* use bits [47:36] of the address */
4315                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4316                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4317                 break;
4318         case 1:   /* use bits [46:35] of the address */
4319                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4320                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4321                 break;
4322         case 2:   /* use bits [45:34] of the address */
4323                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4324                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4325                 break;
4326         case 3:   /* use bits [43:32] of the address */
4327                 vector = ((uc_addr->addr_bytes[4]) |
4328                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4329                 break;
4330         default:  /* Invalid mc_filter_type */
4331                 break;
4332         }
4333
4334         /* vector can only be 12-bits or boundary will be exceeded */
4335         vector &= 0xFFF;
4336         return vector;
4337 }
4338
4339 static int
4340 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4341                         uint8_t on)
4342 {
4343         uint32_t vector;
4344         uint32_t uta_idx;
4345         uint32_t reg_val;
4346         uint32_t uta_shift;
4347         uint32_t rc;
4348         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4349         const uint32_t ixgbe_uta_bit_shift = 5;
4350         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4351         const uint32_t bit1 = 0x1;
4352
4353         struct ixgbe_hw *hw =
4354                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4355         struct ixgbe_uta_info *uta_info =
4356                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4357
4358         /* The UTA table only exists on 82599 hardware and newer */
4359         if (hw->mac.type < ixgbe_mac_82599EB)
4360                 return -ENOTSUP;
4361
4362         vector = ixgbe_uta_vector(hw, mac_addr);
4363         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4364         uta_shift = vector & ixgbe_uta_bit_mask;
4365
4366         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4367         if (rc == on)
4368                 return 0;
4369
4370         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4371         if (on) {
4372                 uta_info->uta_in_use++;
4373                 reg_val |= (bit1 << uta_shift);
4374                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4375         } else {
4376                 uta_info->uta_in_use--;
4377                 reg_val &= ~(bit1 << uta_shift);
4378                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4379         }
4380
4381         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4382
4383         if (uta_info->uta_in_use > 0)
4384                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4385                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4386         else
4387                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4388
4389         return 0;
4390 }
4391
4392 static int
4393 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4394 {
4395         int i;
4396         struct ixgbe_hw *hw =
4397                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4398         struct ixgbe_uta_info *uta_info =
4399                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4400
4401         /* The UTA table only exists on 82599 hardware and newer */
4402         if (hw->mac.type < ixgbe_mac_82599EB)
4403                 return -ENOTSUP;
4404
4405         if (on) {
4406                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4407                         uta_info->uta_shadow[i] = ~0;
4408                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4409                 }
4410         } else {
4411                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4412                         uta_info->uta_shadow[i] = 0;
4413                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4414                 }
4415         }
4416         return 0;
4417
4418 }
4419
4420 uint32_t
4421 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4422 {
4423         uint32_t new_val = orig_val;
4424
4425         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4426                 new_val |= IXGBE_VMOLR_AUPE;
4427         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4428                 new_val |= IXGBE_VMOLR_ROMPE;
4429         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4430                 new_val |= IXGBE_VMOLR_ROPE;
4431         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4432                 new_val |= IXGBE_VMOLR_BAM;
4433         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4434                 new_val |= IXGBE_VMOLR_MPE;
4435
4436         return new_val;
4437 }
4438
4439 static int
4440 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4441                                uint16_t rx_mask, uint8_t on)
4442 {
4443         int val = 0;
4444
4445         struct ixgbe_hw *hw =
4446                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4448
4449         if (hw->mac.type == ixgbe_mac_82598EB) {
4450                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4451                              " on 82599 hardware and newer");
4452                 return -ENOTSUP;
4453         }
4454         if (ixgbe_vmdq_mode_check(hw) < 0)
4455                 return -ENOTSUP;
4456
4457         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4458
4459         if (on)
4460                 vmolr |= val;
4461         else
4462                 vmolr &= ~val;
4463
4464         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4465
4466         return 0;
4467 }
4468
4469 static int
4470 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4471 {
4472         uint32_t reg, addr;
4473         uint32_t val;
4474         const uint8_t bit1 = 0x1;
4475
4476         struct ixgbe_hw *hw =
4477                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4478
4479         if (ixgbe_vmdq_mode_check(hw) < 0)
4480                 return -ENOTSUP;
4481
4482         if (pool >= ETH_64_POOLS)
4483                 return -EINVAL;
4484
4485         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4486         if (pool >= 32) {
4487                 addr = IXGBE_VFRE(1);
4488                 val = bit1 << (pool - 32);
4489         } else {
4490                 addr = IXGBE_VFRE(0);
4491                 val = bit1 << pool;
4492         }
4493
4494         reg = IXGBE_READ_REG(hw, addr);
4495
4496         if (on)
4497                 reg |= val;
4498         else
4499                 reg &= ~val;
4500
4501         IXGBE_WRITE_REG(hw, addr, reg);
4502
4503         return 0;
4504 }
4505
4506 static int
4507 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4508 {
4509         uint32_t reg, addr;
4510         uint32_t val;
4511         const uint8_t bit1 = 0x1;
4512
4513         struct ixgbe_hw *hw =
4514                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4515
4516         if (ixgbe_vmdq_mode_check(hw) < 0)
4517                 return -ENOTSUP;
4518
4519         if (pool >= ETH_64_POOLS)
4520                 return -EINVAL;
4521
4522         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4523         if (pool >= 32) {
4524                 addr = IXGBE_VFTE(1);
4525                 val = bit1 << (pool - 32);
4526         } else {
4527                 addr = IXGBE_VFTE(0);
4528                 val = bit1 << pool;
4529         }
4530
4531         reg = IXGBE_READ_REG(hw, addr);
4532
4533         if (on)
4534                 reg |= val;
4535         else
4536                 reg &= ~val;
4537
4538         IXGBE_WRITE_REG(hw, addr, reg);
4539
4540         return 0;
4541 }
4542
4543 static int
4544 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4545                         uint64_t pool_mask, uint8_t vlan_on)
4546 {
4547         int ret = 0;
4548         uint16_t pool_idx;
4549         struct ixgbe_hw *hw =
4550                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4551
4552         if (ixgbe_vmdq_mode_check(hw) < 0)
4553                 return -ENOTSUP;
4554         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4555                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4556                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx, vlan_on);
4557                         if (ret < 0)
4558                                 return ret;
4559                 }
4560         }
4561
4562         return ret;
4563 }
4564
4565 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4566 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4567 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4568 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4569 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4570         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4571         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4572
4573 static int
4574 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4575                         struct rte_eth_mirror_conf *mirror_conf,
4576                         uint8_t rule_id, uint8_t on)
4577 {
4578         uint32_t mr_ctl, vlvf;
4579         uint32_t mp_lsb = 0;
4580         uint32_t mv_msb = 0;
4581         uint32_t mv_lsb = 0;
4582         uint32_t mp_msb = 0;
4583         uint8_t i = 0;
4584         int reg_index = 0;
4585         uint64_t vlan_mask = 0;
4586
4587         const uint8_t pool_mask_offset = 32;
4588         const uint8_t vlan_mask_offset = 32;
4589         const uint8_t dst_pool_offset = 8;
4590         const uint8_t rule_mr_offset  = 4;
4591         const uint8_t mirror_rule_mask = 0x0F;
4592
4593         struct ixgbe_mirror_info *mr_info =
4594                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4595         struct ixgbe_hw *hw =
4596                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4597         uint8_t mirror_type = 0;
4598
4599         if (ixgbe_vmdq_mode_check(hw) < 0)
4600                 return -ENOTSUP;
4601
4602         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4603                 return -EINVAL;
4604
4605         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4606                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4607                         mirror_conf->rule_type);
4608                 return -EINVAL;
4609         }
4610
4611         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4612                 mirror_type |= IXGBE_MRCTL_VLME;
4613                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4614                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4615                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4616                                 /* search vlan id related pool vlan filter index */
4617                                 reg_index = ixgbe_find_vlvf_slot(hw,
4618                                                 mirror_conf->vlan.vlan_id[i]);
4619                                 if (reg_index < 0)
4620                                         return -EINVAL;
4621                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4622                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4623                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4624                                       mirror_conf->vlan.vlan_id[i]))
4625                                         vlan_mask |= (1ULL << reg_index);
4626                                 else
4627                                         return -EINVAL;
4628                         }
4629                 }
4630
4631                 if (on) {
4632                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4633                         mv_msb = vlan_mask >> vlan_mask_offset;
4634
4635                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4636                                                 mirror_conf->vlan.vlan_mask;
4637                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4638                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4639                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4640                                                 mirror_conf->vlan.vlan_id[i];
4641                         }
4642                 } else {
4643                         mv_lsb = 0;
4644                         mv_msb = 0;
4645                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4646                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4647                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4648                 }
4649         }
4650
4651         /*
4652          * if enable pool mirror, write related pool mask register,if disable
4653          * pool mirror, clear PFMRVM register
4654          */
4655         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4656                 mirror_type |= IXGBE_MRCTL_VPME;
4657                 if (on) {
4658                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4659                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4660                         mr_info->mr_conf[rule_id].pool_mask =
4661                                         mirror_conf->pool_mask;
4662
4663                 } else {
4664                         mp_lsb = 0;
4665                         mp_msb = 0;
4666                         mr_info->mr_conf[rule_id].pool_mask = 0;
4667                 }
4668         }
4669         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4670                 mirror_type |= IXGBE_MRCTL_UPME;
4671         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4672                 mirror_type |= IXGBE_MRCTL_DPME;
4673
4674         /* read  mirror control register and recalculate it */
4675         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4676
4677         if (on) {
4678                 mr_ctl |= mirror_type;
4679                 mr_ctl &= mirror_rule_mask;
4680                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4681         } else
4682                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4683
4684         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4685         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4686
4687         /* write mirrror control  register */
4688         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4689
4690         /* write pool mirrror control  register */
4691         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4692                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4693                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4694                                 mp_msb);
4695         }
4696         /* write VLAN mirrror control  register */
4697         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4698                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4699                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4700                                 mv_msb);
4701         }
4702
4703         return 0;
4704 }
4705
4706 static int
4707 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4708 {
4709         int mr_ctl = 0;
4710         uint32_t lsb_val = 0;
4711         uint32_t msb_val = 0;
4712         const uint8_t rule_mr_offset = 4;
4713
4714         struct ixgbe_hw *hw =
4715                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4716         struct ixgbe_mirror_info *mr_info =
4717                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4718
4719         if (ixgbe_vmdq_mode_check(hw) < 0)
4720                 return -ENOTSUP;
4721
4722         memset(&mr_info->mr_conf[rule_id], 0,
4723                 sizeof(struct rte_eth_mirror_conf));
4724
4725         /* clear PFVMCTL register */
4726         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4727
4728         /* clear pool mask register */
4729         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4730         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4731
4732         /* clear vlan mask register */
4733         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4734         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4735
4736         return 0;
4737 }
4738
4739 static int
4740 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4741 {
4742         uint32_t mask;
4743         struct ixgbe_hw *hw =
4744                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4745
4746         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4747         mask |= (1 << IXGBE_MISC_VEC_ID);
4748         RTE_SET_USED(queue_id);
4749         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4750
4751         rte_intr_enable(&dev->pci_dev->intr_handle);
4752
4753         return 0;
4754 }
4755
4756 static int
4757 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4758 {
4759         uint32_t mask;
4760         struct ixgbe_hw *hw =
4761                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4762
4763         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4764         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4765         RTE_SET_USED(queue_id);
4766         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4767
4768         return 0;
4769 }
4770
4771 static int
4772 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4773 {
4774         uint32_t mask;
4775         struct ixgbe_hw *hw =
4776                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4777         struct ixgbe_interrupt *intr =
4778                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4779
4780         if (queue_id < 16) {
4781                 ixgbe_disable_intr(hw);
4782                 intr->mask |= (1 << queue_id);
4783                 ixgbe_enable_intr(dev);
4784         } else if (queue_id < 32) {
4785                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4786                 mask &= (1 << queue_id);
4787                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4788         } else if (queue_id < 64) {
4789                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4790                 mask &= (1 << (queue_id - 32));
4791                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4792         }
4793         rte_intr_enable(&dev->pci_dev->intr_handle);
4794
4795         return 0;
4796 }
4797
4798 static int
4799 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4800 {
4801         uint32_t mask;
4802         struct ixgbe_hw *hw =
4803                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804         struct ixgbe_interrupt *intr =
4805                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4806
4807         if (queue_id < 16) {
4808                 ixgbe_disable_intr(hw);
4809                 intr->mask &= ~(1 << queue_id);
4810                 ixgbe_enable_intr(dev);
4811         } else if (queue_id < 32) {
4812                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4813                 mask &= ~(1 << queue_id);
4814                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4815         } else if (queue_id < 64) {
4816                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4817                 mask &= ~(1 << (queue_id - 32));
4818                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4819         }
4820
4821         return 0;
4822 }
4823
4824 static void
4825 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4826                      uint8_t queue, uint8_t msix_vector)
4827 {
4828         uint32_t tmp, idx;
4829
4830         if (direction == -1) {
4831                 /* other causes */
4832                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4833                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4834                 tmp &= ~0xFF;
4835                 tmp |= msix_vector;
4836                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4837         } else {
4838                 /* rx or tx cause */
4839                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4840                 idx = ((16 * (queue & 1)) + (8 * direction));
4841                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4842                 tmp &= ~(0xFF << idx);
4843                 tmp |= (msix_vector << idx);
4844                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4845         }
4846 }
4847
4848 /**
4849  * set the IVAR registers, mapping interrupt causes to vectors
4850  * @param hw
4851  *  pointer to ixgbe_hw struct
4852  * @direction
4853  *  0 for Rx, 1 for Tx, -1 for other causes
4854  * @queue
4855  *  queue to map the corresponding interrupt to
4856  * @msix_vector
4857  *  the vector to map to the corresponding queue
4858  */
4859 static void
4860 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4861                    uint8_t queue, uint8_t msix_vector)
4862 {
4863         uint32_t tmp, idx;
4864
4865         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4866         if (hw->mac.type == ixgbe_mac_82598EB) {
4867                 if (direction == -1)
4868                         direction = 0;
4869                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4870                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4871                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4872                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4873                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4874         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4875                         (hw->mac.type == ixgbe_mac_X540)) {
4876                 if (direction == -1) {
4877                         /* other causes */
4878                         idx = ((queue & 1) * 8);
4879                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4880                         tmp &= ~(0xFF << idx);
4881                         tmp |= (msix_vector << idx);
4882                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4883                 } else {
4884                         /* rx or tx causes */
4885                         idx = ((16 * (queue & 1)) + (8 * direction));
4886                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4887                         tmp &= ~(0xFF << idx);
4888                         tmp |= (msix_vector << idx);
4889                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4890                 }
4891         }
4892 }
4893
4894 static void
4895 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4896 {
4897         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4898         struct ixgbe_hw *hw =
4899                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4900         uint32_t q_idx;
4901         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4902
4903         /* won't configure msix register if no mapping is done
4904          * between intr vector and event fd.
4905          */
4906         if (!rte_intr_dp_is_en(intr_handle))
4907                 return;
4908
4909         /* Configure all RX queues of VF */
4910         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4911                 /* Force all queue use vector 0,
4912                  * as IXGBE_VF_MAXMSIVECOTR = 1
4913                  */
4914                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4915                 intr_handle->intr_vec[q_idx] = vector_idx;
4916         }
4917
4918         /* Configure VF other cause ivar */
4919         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4920 }
4921
4922 /**
4923  * Sets up the hardware to properly generate MSI-X interrupts
4924  * @hw
4925  *  board private structure
4926  */
4927 static void
4928 ixgbe_configure_msix(struct rte_eth_dev *dev)
4929 {
4930         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4931         struct ixgbe_hw *hw =
4932                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4933         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4934         uint32_t vec = IXGBE_MISC_VEC_ID;
4935         uint32_t mask;
4936         uint32_t gpie;
4937
4938         /* won't configure msix register if no mapping is done
4939          * between intr vector and event fd
4940          */
4941         if (!rte_intr_dp_is_en(intr_handle))
4942                 return;
4943
4944         if (rte_intr_allow_others(intr_handle))
4945                 vec = base = IXGBE_RX_VEC_START;
4946
4947         /* setup GPIE for MSI-x mode */
4948         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4949         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4950                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4951         /* auto clearing and auto setting corresponding bits in EIMS
4952          * when MSI-X interrupt is triggered
4953          */
4954         if (hw->mac.type == ixgbe_mac_82598EB) {
4955                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4956         } else {
4957                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4958                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4959         }
4960         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4961
4962         /* Populate the IVAR table and set the ITR values to the
4963          * corresponding register.
4964          */
4965         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4966              queue_id++) {
4967                 /* by default, 1:1 mapping */
4968                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4969                 intr_handle->intr_vec[queue_id] = vec;
4970                 if (vec < base + intr_handle->nb_efd - 1)
4971                         vec++;
4972         }
4973
4974         switch (hw->mac.type) {
4975         case ixgbe_mac_82598EB:
4976                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4977                                    IXGBE_MISC_VEC_ID);
4978                 break;
4979         case ixgbe_mac_82599EB:
4980         case ixgbe_mac_X540:
4981                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4982                 break;
4983         default:
4984                 break;
4985         }
4986         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4987                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4988
4989         /* set up to autoclear timer, and the vectors */
4990         mask = IXGBE_EIMS_ENABLE_MASK;
4991         mask &= ~(IXGBE_EIMS_OTHER |
4992                   IXGBE_EIMS_MAILBOX |
4993                   IXGBE_EIMS_LSC);
4994
4995         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4996 }
4997
4998 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4999         uint16_t queue_idx, uint16_t tx_rate)
5000 {
5001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5002         uint32_t rf_dec, rf_int;
5003         uint32_t bcnrc_val;
5004         uint16_t link_speed = dev->data->dev_link.link_speed;
5005
5006         if (queue_idx >= hw->mac.max_tx_queues)
5007                 return -EINVAL;
5008
5009         if (tx_rate != 0) {
5010                 /* Calculate the rate factor values to set */
5011                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5012                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5013                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5014
5015                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5016                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5017                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5018                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5019         } else {
5020                 bcnrc_val = 0;
5021         }
5022
5023         /*
5024          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5025          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5026          * set as 0x4.
5027          */
5028         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5029                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5030                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5031                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5032                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5033         else
5034                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5035                         IXGBE_MMW_SIZE_DEFAULT);
5036
5037         /* Set RTTBCNRC of queue X */
5038         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5039         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5040         IXGBE_WRITE_FLUSH(hw);
5041
5042         return 0;
5043 }
5044
5045 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5046         uint16_t tx_rate, uint64_t q_msk)
5047 {
5048         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5049         struct ixgbe_vf_info *vfinfo =
5050                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5051         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5052         uint32_t queue_stride =
5053                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5054         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5055         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5056         uint16_t total_rate = 0;
5057
5058         if (queue_end >= hw->mac.max_tx_queues)
5059                 return -EINVAL;
5060
5061         if (vfinfo != NULL) {
5062                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5063                         if (vf_idx == vf)
5064                                 continue;
5065                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5066                                 idx++)
5067                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5068                 }
5069         } else
5070                 return -EINVAL;
5071
5072         /* Store tx_rate for this vf. */
5073         for (idx = 0; idx < nb_q_per_pool; idx++) {
5074                 if (((uint64_t)0x1 << idx) & q_msk) {
5075                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5076                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5077                         total_rate += tx_rate;
5078                 }
5079         }
5080
5081         if (total_rate > dev->data->dev_link.link_speed) {
5082                 /*
5083                  * Reset stored TX rate of the VF if it causes exceed
5084                  * link speed.
5085                  */
5086                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5087                 return -EINVAL;
5088         }
5089
5090         /* Set RTTBCNRC of each queue/pool for vf X  */
5091         for (; queue_idx <= queue_end; queue_idx++) {
5092                 if (0x1 & q_msk)
5093                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5094                 q_msk = q_msk >> 1;
5095         }
5096
5097         return 0;
5098 }
5099
5100 static void
5101 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5102                      __attribute__((unused)) uint32_t index,
5103                      __attribute__((unused)) uint32_t pool)
5104 {
5105         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5106         int diag;
5107
5108         /*
5109          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5110          * operation. Trap this case to avoid exhausting the [very limited]
5111          * set of PF resources used to store VF MAC addresses.
5112          */
5113         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5114                 return;
5115         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5116         if (diag == 0)
5117                 return;
5118         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5119 }
5120
5121 static void
5122 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5123 {
5124         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5125         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5126         struct ether_addr *mac_addr;
5127         uint32_t i;
5128         int diag;
5129
5130         /*
5131          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5132          * not support the deletion of a given MAC address.
5133          * Instead, it imposes to delete all MAC addresses, then to add again
5134          * all MAC addresses with the exception of the one to be deleted.
5135          */
5136         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5137
5138         /*
5139          * Add again all MAC addresses, with the exception of the deleted one
5140          * and of the permanent MAC address.
5141          */
5142         for (i = 0, mac_addr = dev->data->mac_addrs;
5143              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5144                 /* Skip the deleted MAC address */
5145                 if (i == index)
5146                         continue;
5147                 /* Skip NULL MAC addresses */
5148                 if (is_zero_ether_addr(mac_addr))
5149                         continue;
5150                 /* Skip the permanent MAC address */
5151                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5152                         continue;
5153                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5154                 if (diag != 0)
5155                         PMD_DRV_LOG(ERR,
5156                                     "Adding again MAC address "
5157                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5158                                     "diag=%d",
5159                                     mac_addr->addr_bytes[0],
5160                                     mac_addr->addr_bytes[1],
5161                                     mac_addr->addr_bytes[2],
5162                                     mac_addr->addr_bytes[3],
5163                                     mac_addr->addr_bytes[4],
5164                                     mac_addr->addr_bytes[5],
5165                                     diag);
5166         }
5167 }
5168
5169 static void
5170 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5171 {
5172         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5173
5174         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5175 }
5176
5177 #define MAC_TYPE_FILTER_SUP(type)    do {\
5178         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5179                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5180                 (type) != ixgbe_mac_X550EM_a)\
5181                 return -ENOTSUP;\
5182 } while (0)
5183
5184 static int
5185 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5186                         struct rte_eth_syn_filter *filter,
5187                         bool add)
5188 {
5189         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5190         uint32_t synqf;
5191
5192         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5193                 return -EINVAL;
5194
5195         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5196
5197         if (add) {
5198                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5199                         return -EINVAL;
5200                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5201                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5202
5203                 if (filter->hig_pri)
5204                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5205                 else
5206                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5207         } else {
5208                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5209                         return -ENOENT;
5210                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5211         }
5212         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5213         IXGBE_WRITE_FLUSH(hw);
5214         return 0;
5215 }
5216
5217 static int
5218 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5219                         struct rte_eth_syn_filter *filter)
5220 {
5221         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5222         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5223
5224         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5225                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5226                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5227                 return 0;
5228         }
5229         return -ENOENT;
5230 }
5231
5232 static int
5233 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5234                         enum rte_filter_op filter_op,
5235                         void *arg)
5236 {
5237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5238         int ret;
5239
5240         MAC_TYPE_FILTER_SUP(hw->mac.type);
5241
5242         if (filter_op == RTE_ETH_FILTER_NOP)
5243                 return 0;
5244
5245         if (arg == NULL) {
5246                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5247                             filter_op);
5248                 return -EINVAL;
5249         }
5250
5251         switch (filter_op) {
5252         case RTE_ETH_FILTER_ADD:
5253                 ret = ixgbe_syn_filter_set(dev,
5254                                 (struct rte_eth_syn_filter *)arg,
5255                                 TRUE);
5256                 break;
5257         case RTE_ETH_FILTER_DELETE:
5258                 ret = ixgbe_syn_filter_set(dev,
5259                                 (struct rte_eth_syn_filter *)arg,
5260                                 FALSE);
5261                 break;
5262         case RTE_ETH_FILTER_GET:
5263                 ret = ixgbe_syn_filter_get(dev,
5264                                 (struct rte_eth_syn_filter *)arg);
5265                 break;
5266         default:
5267                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5268                 ret = -EINVAL;
5269                 break;
5270         }
5271
5272         return ret;
5273 }
5274
5275
5276 static inline enum ixgbe_5tuple_protocol
5277 convert_protocol_type(uint8_t protocol_value)
5278 {
5279         if (protocol_value == IPPROTO_TCP)
5280                 return IXGBE_FILTER_PROTOCOL_TCP;
5281         else if (protocol_value == IPPROTO_UDP)
5282                 return IXGBE_FILTER_PROTOCOL_UDP;
5283         else if (protocol_value == IPPROTO_SCTP)
5284                 return IXGBE_FILTER_PROTOCOL_SCTP;
5285         else
5286                 return IXGBE_FILTER_PROTOCOL_NONE;
5287 }
5288
5289 /*
5290  * add a 5tuple filter
5291  *
5292  * @param
5293  * dev: Pointer to struct rte_eth_dev.
5294  * index: the index the filter allocates.
5295  * filter: ponter to the filter that will be added.
5296  * rx_queue: the queue id the filter assigned to.
5297  *
5298  * @return
5299  *    - On success, zero.
5300  *    - On failure, a negative value.
5301  */
5302 static int
5303 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5304                         struct ixgbe_5tuple_filter *filter)
5305 {
5306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5307         struct ixgbe_filter_info *filter_info =
5308                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5309         int i, idx, shift;
5310         uint32_t ftqf, sdpqf;
5311         uint32_t l34timir = 0;
5312         uint8_t mask = 0xff;
5313
5314         /*
5315          * look for an unused 5tuple filter index,
5316          * and insert the filter to list.
5317          */
5318         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5319                 idx = i / (sizeof(uint32_t) * NBBY);
5320                 shift = i % (sizeof(uint32_t) * NBBY);
5321                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5322                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5323                         filter->index = i;
5324                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5325                                           filter,
5326                                           entries);
5327                         break;
5328                 }
5329         }
5330         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5331                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5332                 return -ENOSYS;
5333         }
5334
5335         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5336                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5337         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5338
5339         ftqf = (uint32_t)(filter->filter_info.proto &
5340                 IXGBE_FTQF_PROTOCOL_MASK);
5341         ftqf |= (uint32_t)((filter->filter_info.priority &
5342                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5343         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5344                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5345         if (filter->filter_info.dst_ip_mask == 0)
5346                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5347         if (filter->filter_info.src_port_mask == 0)
5348                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5349         if (filter->filter_info.dst_port_mask == 0)
5350                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5351         if (filter->filter_info.proto_mask == 0)
5352                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5353         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5354         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5355         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5356
5357         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5358         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5359         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5360         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5361
5362         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5363         l34timir |= (uint32_t)(filter->queue <<
5364                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5365         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5366         return 0;
5367 }
5368
5369 /*
5370  * remove a 5tuple filter
5371  *
5372  * @param
5373  * dev: Pointer to struct rte_eth_dev.
5374  * filter: the pointer of the filter will be removed.
5375  */
5376 static void
5377 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5378                         struct ixgbe_5tuple_filter *filter)
5379 {
5380         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5381         struct ixgbe_filter_info *filter_info =
5382                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5383         uint16_t index = filter->index;
5384
5385         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5386                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5387         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5388         rte_free(filter);
5389
5390         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5391         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5392         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5393         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5394         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5395 }
5396
5397 static int
5398 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5399 {
5400         struct ixgbe_hw *hw;
5401         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5402
5403         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5404
5405         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5406                 return -EINVAL;
5407
5408         /* refuse mtu that requires the support of scattered packets when this
5409          * feature has not been enabled before.
5410          */
5411         if (!dev->data->scattered_rx &&
5412             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5413              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5414                 return -EINVAL;
5415
5416         /*
5417          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5418          * request of the version 2.0 of the mailbox API.
5419          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5420          * of the mailbox API.
5421          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5422          * prior to 3.11.33 which contains the following change:
5423          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5424          */
5425         ixgbevf_rlpml_set_vf(hw, max_frame);
5426
5427         /* update max frame size */
5428         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5429         return 0;
5430 }
5431
5432 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5433         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5434                 return -ENOTSUP;\
5435 } while (0)
5436
5437 static inline struct ixgbe_5tuple_filter *
5438 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5439                         struct ixgbe_5tuple_filter_info *key)
5440 {
5441         struct ixgbe_5tuple_filter *it;
5442
5443         TAILQ_FOREACH(it, filter_list, entries) {
5444                 if (memcmp(key, &it->filter_info,
5445                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5446                         return it;
5447                 }
5448         }
5449         return NULL;
5450 }
5451
5452 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5453 static inline int
5454 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5455                         struct ixgbe_5tuple_filter_info *filter_info)
5456 {
5457         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5458                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5459                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5460                 return -EINVAL;
5461
5462         switch (filter->dst_ip_mask) {
5463         case UINT32_MAX:
5464                 filter_info->dst_ip_mask = 0;
5465                 filter_info->dst_ip = filter->dst_ip;
5466                 break;
5467         case 0:
5468                 filter_info->dst_ip_mask = 1;
5469                 break;
5470         default:
5471                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5472                 return -EINVAL;
5473         }
5474
5475         switch (filter->src_ip_mask) {
5476         case UINT32_MAX:
5477                 filter_info->src_ip_mask = 0;
5478                 filter_info->src_ip = filter->src_ip;
5479                 break;
5480         case 0:
5481                 filter_info->src_ip_mask = 1;
5482                 break;
5483         default:
5484                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5485                 return -EINVAL;
5486         }
5487
5488         switch (filter->dst_port_mask) {
5489         case UINT16_MAX:
5490                 filter_info->dst_port_mask = 0;
5491                 filter_info->dst_port = filter->dst_port;
5492                 break;
5493         case 0:
5494                 filter_info->dst_port_mask = 1;
5495                 break;
5496         default:
5497                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5498                 return -EINVAL;
5499         }
5500
5501         switch (filter->src_port_mask) {
5502         case UINT16_MAX:
5503                 filter_info->src_port_mask = 0;
5504                 filter_info->src_port = filter->src_port;
5505                 break;
5506         case 0:
5507                 filter_info->src_port_mask = 1;
5508                 break;
5509         default:
5510                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5511                 return -EINVAL;
5512         }
5513
5514         switch (filter->proto_mask) {
5515         case UINT8_MAX:
5516                 filter_info->proto_mask = 0;
5517                 filter_info->proto =
5518                         convert_protocol_type(filter->proto);
5519                 break;
5520         case 0:
5521                 filter_info->proto_mask = 1;
5522                 break;
5523         default:
5524                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5525                 return -EINVAL;
5526         }
5527
5528         filter_info->priority = (uint8_t)filter->priority;
5529         return 0;
5530 }
5531
5532 /*
5533  * add or delete a ntuple filter
5534  *
5535  * @param
5536  * dev: Pointer to struct rte_eth_dev.
5537  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5538  * add: if true, add filter, if false, remove filter
5539  *
5540  * @return
5541  *    - On success, zero.
5542  *    - On failure, a negative value.
5543  */
5544 static int
5545 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5546                         struct rte_eth_ntuple_filter *ntuple_filter,
5547                         bool add)
5548 {
5549         struct ixgbe_filter_info *filter_info =
5550                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5551         struct ixgbe_5tuple_filter_info filter_5tuple;
5552         struct ixgbe_5tuple_filter *filter;
5553         int ret;
5554
5555         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5556                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5557                 return -EINVAL;
5558         }
5559
5560         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5561         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5562         if (ret < 0)
5563                 return ret;
5564
5565         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5566                                          &filter_5tuple);
5567         if (filter != NULL && add) {
5568                 PMD_DRV_LOG(ERR, "filter exists.");
5569                 return -EEXIST;
5570         }
5571         if (filter == NULL && !add) {
5572                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5573                 return -ENOENT;
5574         }
5575
5576         if (add) {
5577                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5578                                 sizeof(struct ixgbe_5tuple_filter), 0);
5579                 if (filter == NULL)
5580                         return -ENOMEM;
5581                 (void)rte_memcpy(&filter->filter_info,
5582                                  &filter_5tuple,
5583                                  sizeof(struct ixgbe_5tuple_filter_info));
5584                 filter->queue = ntuple_filter->queue;
5585                 ret = ixgbe_add_5tuple_filter(dev, filter);
5586                 if (ret < 0) {
5587                         rte_free(filter);
5588                         return ret;
5589                 }
5590         } else
5591                 ixgbe_remove_5tuple_filter(dev, filter);
5592
5593         return 0;
5594 }
5595
5596 /*
5597  * get a ntuple filter
5598  *
5599  * @param
5600  * dev: Pointer to struct rte_eth_dev.
5601  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5602  *
5603  * @return
5604  *    - On success, zero.
5605  *    - On failure, a negative value.
5606  */
5607 static int
5608 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5609                         struct rte_eth_ntuple_filter *ntuple_filter)
5610 {
5611         struct ixgbe_filter_info *filter_info =
5612                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5613         struct ixgbe_5tuple_filter_info filter_5tuple;
5614         struct ixgbe_5tuple_filter *filter;
5615         int ret;
5616
5617         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5618                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5619                 return -EINVAL;
5620         }
5621
5622         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5623         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5624         if (ret < 0)
5625                 return ret;
5626
5627         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5628                                          &filter_5tuple);
5629         if (filter == NULL) {
5630                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5631                 return -ENOENT;
5632         }
5633         ntuple_filter->queue = filter->queue;
5634         return 0;
5635 }
5636
5637 /*
5638  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5639  * @dev: pointer to rte_eth_dev structure
5640  * @filter_op:operation will be taken.
5641  * @arg: a pointer to specific structure corresponding to the filter_op
5642  *
5643  * @return
5644  *    - On success, zero.
5645  *    - On failure, a negative value.
5646  */
5647 static int
5648 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5649                                 enum rte_filter_op filter_op,
5650                                 void *arg)
5651 {
5652         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5653         int ret;
5654
5655         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5656
5657         if (filter_op == RTE_ETH_FILTER_NOP)
5658                 return 0;
5659
5660         if (arg == NULL) {
5661                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5662                             filter_op);
5663                 return -EINVAL;
5664         }
5665
5666         switch (filter_op) {
5667         case RTE_ETH_FILTER_ADD:
5668                 ret = ixgbe_add_del_ntuple_filter(dev,
5669                         (struct rte_eth_ntuple_filter *)arg,
5670                         TRUE);
5671                 break;
5672         case RTE_ETH_FILTER_DELETE:
5673                 ret = ixgbe_add_del_ntuple_filter(dev,
5674                         (struct rte_eth_ntuple_filter *)arg,
5675                         FALSE);
5676                 break;
5677         case RTE_ETH_FILTER_GET:
5678                 ret = ixgbe_get_ntuple_filter(dev,
5679                         (struct rte_eth_ntuple_filter *)arg);
5680                 break;
5681         default:
5682                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5683                 ret = -EINVAL;
5684                 break;
5685         }
5686         return ret;
5687 }
5688
5689 static inline int
5690 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5691                         uint16_t ethertype)
5692 {
5693         int i;
5694
5695         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5696                 if (filter_info->ethertype_filters[i] == ethertype &&
5697                     (filter_info->ethertype_mask & (1 << i)))
5698                         return i;
5699         }
5700         return -1;
5701 }
5702
5703 static inline int
5704 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5705                         uint16_t ethertype)
5706 {
5707         int i;
5708
5709         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5710                 if (!(filter_info->ethertype_mask & (1 << i))) {
5711                         filter_info->ethertype_mask |= 1 << i;
5712                         filter_info->ethertype_filters[i] = ethertype;
5713                         return i;
5714                 }
5715         }
5716         return -1;
5717 }
5718
5719 static inline int
5720 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5721                         uint8_t idx)
5722 {
5723         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5724                 return -1;
5725         filter_info->ethertype_mask &= ~(1 << idx);
5726         filter_info->ethertype_filters[idx] = 0;
5727         return idx;
5728 }
5729
5730 static int
5731 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5732                         struct rte_eth_ethertype_filter *filter,
5733                         bool add)
5734 {
5735         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5736         struct ixgbe_filter_info *filter_info =
5737                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5738         uint32_t etqf = 0;
5739         uint32_t etqs = 0;
5740         int ret;
5741
5742         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5743                 return -EINVAL;
5744
5745         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5746                 filter->ether_type == ETHER_TYPE_IPv6) {
5747                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5748                         " ethertype filter.", filter->ether_type);
5749                 return -EINVAL;
5750         }
5751
5752         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5753                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5754                 return -EINVAL;
5755         }
5756         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5757                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5758                 return -EINVAL;
5759         }
5760
5761         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5762         if (ret >= 0 && add) {
5763                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5764                             filter->ether_type);
5765                 return -EEXIST;
5766         }
5767         if (ret < 0 && !add) {
5768                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5769                             filter->ether_type);
5770                 return -ENOENT;
5771         }
5772
5773         if (add) {
5774                 ret = ixgbe_ethertype_filter_insert(filter_info,
5775                         filter->ether_type);
5776                 if (ret < 0) {
5777                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5778                         return -ENOSYS;
5779                 }
5780                 etqf = IXGBE_ETQF_FILTER_EN;
5781                 etqf |= (uint32_t)filter->ether_type;
5782                 etqs |= (uint32_t)((filter->queue <<
5783                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5784                                     IXGBE_ETQS_RX_QUEUE);
5785                 etqs |= IXGBE_ETQS_QUEUE_EN;
5786         } else {
5787                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5788                 if (ret < 0)
5789                         return -ENOSYS;
5790         }
5791         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5792         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5793         IXGBE_WRITE_FLUSH(hw);
5794
5795         return 0;
5796 }
5797
5798 static int
5799 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5800                         struct rte_eth_ethertype_filter *filter)
5801 {
5802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5803         struct ixgbe_filter_info *filter_info =
5804                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5805         uint32_t etqf, etqs;
5806         int ret;
5807
5808         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5809         if (ret < 0) {
5810                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5811                             filter->ether_type);
5812                 return -ENOENT;
5813         }
5814
5815         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5816         if (etqf & IXGBE_ETQF_FILTER_EN) {
5817                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5818                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5819                 filter->flags = 0;
5820                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5821                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5822                 return 0;
5823         }
5824         return -ENOENT;
5825 }
5826
5827 /*
5828  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5829  * @dev: pointer to rte_eth_dev structure
5830  * @filter_op:operation will be taken.
5831  * @arg: a pointer to specific structure corresponding to the filter_op
5832  */
5833 static int
5834 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5835                                 enum rte_filter_op filter_op,
5836                                 void *arg)
5837 {
5838         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5839         int ret;
5840
5841         MAC_TYPE_FILTER_SUP(hw->mac.type);
5842
5843         if (filter_op == RTE_ETH_FILTER_NOP)
5844                 return 0;
5845
5846         if (arg == NULL) {
5847                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5848                             filter_op);
5849                 return -EINVAL;
5850         }
5851
5852         switch (filter_op) {
5853         case RTE_ETH_FILTER_ADD:
5854                 ret = ixgbe_add_del_ethertype_filter(dev,
5855                         (struct rte_eth_ethertype_filter *)arg,
5856                         TRUE);
5857                 break;
5858         case RTE_ETH_FILTER_DELETE:
5859                 ret = ixgbe_add_del_ethertype_filter(dev,
5860                         (struct rte_eth_ethertype_filter *)arg,
5861                         FALSE);
5862                 break;
5863         case RTE_ETH_FILTER_GET:
5864                 ret = ixgbe_get_ethertype_filter(dev,
5865                         (struct rte_eth_ethertype_filter *)arg);
5866                 break;
5867         default:
5868                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5869                 ret = -EINVAL;
5870                 break;
5871         }
5872         return ret;
5873 }
5874
5875 static int
5876 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5877                      enum rte_filter_type filter_type,
5878                      enum rte_filter_op filter_op,
5879                      void *arg)
5880 {
5881         int ret = -EINVAL;
5882
5883         switch (filter_type) {
5884         case RTE_ETH_FILTER_NTUPLE:
5885                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5886                 break;
5887         case RTE_ETH_FILTER_ETHERTYPE:
5888                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5889                 break;
5890         case RTE_ETH_FILTER_SYN:
5891                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5892                 break;
5893         case RTE_ETH_FILTER_FDIR:
5894                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5895                 break;
5896         case RTE_ETH_FILTER_L2_TUNNEL:
5897                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5898                 break;
5899         default:
5900                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5901                                                         filter_type);
5902                 break;
5903         }
5904
5905         return ret;
5906 }
5907
5908 static u8 *
5909 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5910                         u8 **mc_addr_ptr, u32 *vmdq)
5911 {
5912         u8 *mc_addr;
5913
5914         *vmdq = 0;
5915         mc_addr = *mc_addr_ptr;
5916         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5917         return mc_addr;
5918 }
5919
5920 static int
5921 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5922                           struct ether_addr *mc_addr_set,
5923                           uint32_t nb_mc_addr)
5924 {
5925         struct ixgbe_hw *hw;
5926         u8 *mc_addr_list;
5927
5928         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5929         mc_addr_list = (u8 *)mc_addr_set;
5930         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5931                                          ixgbe_dev_addr_list_itr, TRUE);
5932 }
5933
5934 static uint64_t
5935 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5936 {
5937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5938         uint64_t systime_cycles;
5939
5940         switch (hw->mac.type) {
5941         case ixgbe_mac_X550:
5942         case ixgbe_mac_X550EM_x:
5943         case ixgbe_mac_X550EM_a:
5944                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5945                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5946                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5947                                 * NSEC_PER_SEC;
5948                 break;
5949         default:
5950                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5951                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5952                                 << 32;
5953         }
5954
5955         return systime_cycles;
5956 }
5957
5958 static uint64_t
5959 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5960 {
5961         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5962         uint64_t rx_tstamp_cycles;
5963
5964         switch (hw->mac.type) {
5965         case ixgbe_mac_X550:
5966         case ixgbe_mac_X550EM_x:
5967         case ixgbe_mac_X550EM_a:
5968                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5969                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5970                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5971                                 * NSEC_PER_SEC;
5972                 break;
5973         default:
5974                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5975                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5976                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5977                                 << 32;
5978         }
5979
5980         return rx_tstamp_cycles;
5981 }
5982
5983 static uint64_t
5984 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5985 {
5986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5987         uint64_t tx_tstamp_cycles;
5988
5989         switch (hw->mac.type) {
5990         case ixgbe_mac_X550:
5991         case ixgbe_mac_X550EM_x:
5992         case ixgbe_mac_X550EM_a:
5993                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5994                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5995                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5996                                 * NSEC_PER_SEC;
5997                 break;
5998         default:
5999                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6000                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6001                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6002                                 << 32;
6003         }
6004
6005         return tx_tstamp_cycles;
6006 }
6007
6008 static void
6009 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6010 {
6011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6012         struct ixgbe_adapter *adapter =
6013                 (struct ixgbe_adapter *)dev->data->dev_private;
6014         struct rte_eth_link link;
6015         uint32_t incval = 0;
6016         uint32_t shift = 0;
6017
6018         /* Get current link speed. */
6019         memset(&link, 0, sizeof(link));
6020         ixgbe_dev_link_update(dev, 1);
6021         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6022
6023         switch (link.link_speed) {
6024         case ETH_SPEED_NUM_100M:
6025                 incval = IXGBE_INCVAL_100;
6026                 shift = IXGBE_INCVAL_SHIFT_100;
6027                 break;
6028         case ETH_SPEED_NUM_1G:
6029                 incval = IXGBE_INCVAL_1GB;
6030                 shift = IXGBE_INCVAL_SHIFT_1GB;
6031                 break;
6032         case ETH_SPEED_NUM_10G:
6033         default:
6034                 incval = IXGBE_INCVAL_10GB;
6035                 shift = IXGBE_INCVAL_SHIFT_10GB;
6036                 break;
6037         }
6038
6039         switch (hw->mac.type) {
6040         case ixgbe_mac_X550:
6041         case ixgbe_mac_X550EM_x:
6042         case ixgbe_mac_X550EM_a:
6043                 /* Independent of link speed. */
6044                 incval = 1;
6045                 /* Cycles read will be interpreted as ns. */
6046                 shift = 0;
6047                 /* Fall-through */
6048         case ixgbe_mac_X540:
6049                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6050                 break;
6051         case ixgbe_mac_82599EB:
6052                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6053                 shift -= IXGBE_INCVAL_SHIFT_82599;
6054                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6055                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6056                 break;
6057         default:
6058                 /* Not supported. */
6059                 return;
6060         }
6061
6062         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6063         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6064         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6065
6066         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6067         adapter->systime_tc.cc_shift = shift;
6068         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6069
6070         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6071         adapter->rx_tstamp_tc.cc_shift = shift;
6072         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6073
6074         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6075         adapter->tx_tstamp_tc.cc_shift = shift;
6076         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6077 }
6078
6079 static int
6080 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6081 {
6082         struct ixgbe_adapter *adapter =
6083                         (struct ixgbe_adapter *)dev->data->dev_private;
6084
6085         adapter->systime_tc.nsec += delta;
6086         adapter->rx_tstamp_tc.nsec += delta;
6087         adapter->tx_tstamp_tc.nsec += delta;
6088
6089         return 0;
6090 }
6091
6092 static int
6093 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6094 {
6095         uint64_t ns;
6096         struct ixgbe_adapter *adapter =
6097                         (struct ixgbe_adapter *)dev->data->dev_private;
6098
6099         ns = rte_timespec_to_ns(ts);
6100         /* Set the timecounters to a new value. */
6101         adapter->systime_tc.nsec = ns;
6102         adapter->rx_tstamp_tc.nsec = ns;
6103         adapter->tx_tstamp_tc.nsec = ns;
6104
6105         return 0;
6106 }
6107
6108 static int
6109 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6110 {
6111         uint64_t ns, systime_cycles;
6112         struct ixgbe_adapter *adapter =
6113                         (struct ixgbe_adapter *)dev->data->dev_private;
6114
6115         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6116         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6117         *ts = rte_ns_to_timespec(ns);
6118
6119         return 0;
6120 }
6121
6122 static int
6123 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6124 {
6125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6126         uint32_t tsync_ctl;
6127         uint32_t tsauxc;
6128
6129         /* Stop the timesync system time. */
6130         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6131         /* Reset the timesync system time value. */
6132         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6133         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6134
6135         /* Enable system time for platforms where it isn't on by default. */
6136         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6137         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6138         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6139
6140         ixgbe_start_timecounters(dev);
6141
6142         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6143         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6144                         (ETHER_TYPE_1588 |
6145                          IXGBE_ETQF_FILTER_EN |
6146                          IXGBE_ETQF_1588));
6147
6148         /* Enable timestamping of received PTP packets. */
6149         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6150         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6151         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6152
6153         /* Enable timestamping of transmitted PTP packets. */
6154         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6155         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6156         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6157
6158         IXGBE_WRITE_FLUSH(hw);
6159
6160         return 0;
6161 }
6162
6163 static int
6164 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6165 {
6166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6167         uint32_t tsync_ctl;
6168
6169         /* Disable timestamping of transmitted PTP packets. */
6170         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6171         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6172         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6173
6174         /* Disable timestamping of received PTP packets. */
6175         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6176         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6177         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6178
6179         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6180         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6181
6182         /* Stop incrementating the System Time registers. */
6183         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6184
6185         return 0;
6186 }
6187
6188 static int
6189 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6190                                  struct timespec *timestamp,
6191                                  uint32_t flags __rte_unused)
6192 {
6193         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6194         struct ixgbe_adapter *adapter =
6195                 (struct ixgbe_adapter *)dev->data->dev_private;
6196         uint32_t tsync_rxctl;
6197         uint64_t rx_tstamp_cycles;
6198         uint64_t ns;
6199
6200         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6201         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6202                 return -EINVAL;
6203
6204         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6205         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6206         *timestamp = rte_ns_to_timespec(ns);
6207
6208         return  0;
6209 }
6210
6211 static int
6212 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6213                                  struct timespec *timestamp)
6214 {
6215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6216         struct ixgbe_adapter *adapter =
6217                 (struct ixgbe_adapter *)dev->data->dev_private;
6218         uint32_t tsync_txctl;
6219         uint64_t tx_tstamp_cycles;
6220         uint64_t ns;
6221
6222         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6223         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6224                 return -EINVAL;
6225
6226         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6227         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6228         *timestamp = rte_ns_to_timespec(ns);
6229
6230         return 0;
6231 }
6232
6233 static int
6234 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6235 {
6236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6237         int count = 0;
6238         int g_ind = 0;
6239         const struct reg_info *reg_group;
6240         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6241                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6242
6243         while ((reg_group = reg_set[g_ind++]))
6244                 count += ixgbe_regs_group_count(reg_group);
6245
6246         return count;
6247 }
6248
6249 static int
6250 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6251 {
6252         int count = 0;
6253         int g_ind = 0;
6254         const struct reg_info *reg_group;
6255
6256         while ((reg_group = ixgbevf_regs[g_ind++]))
6257                 count += ixgbe_regs_group_count(reg_group);
6258
6259         return count;
6260 }
6261
6262 static int
6263 ixgbe_get_regs(struct rte_eth_dev *dev,
6264               struct rte_dev_reg_info *regs)
6265 {
6266         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6267         uint32_t *data = regs->data;
6268         int g_ind = 0;
6269         int count = 0;
6270         const struct reg_info *reg_group;
6271         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6272                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6273
6274         /* Support only full register dump */
6275         if ((regs->length == 0) ||
6276             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6277                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6278                         hw->device_id;
6279                 while ((reg_group = reg_set[g_ind++]))
6280                         count += ixgbe_read_regs_group(dev, &data[count],
6281                                 reg_group);
6282                 return 0;
6283         }
6284
6285         return -ENOTSUP;
6286 }
6287
6288 static int
6289 ixgbevf_get_regs(struct rte_eth_dev *dev,
6290                 struct rte_dev_reg_info *regs)
6291 {
6292         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6293         uint32_t *data = regs->data;
6294         int g_ind = 0;
6295         int count = 0;
6296         const struct reg_info *reg_group;
6297
6298         /* Support only full register dump */
6299         if ((regs->length == 0) ||
6300             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6301                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6302                         hw->device_id;
6303                 while ((reg_group = ixgbevf_regs[g_ind++]))
6304                         count += ixgbe_read_regs_group(dev, &data[count],
6305                                                       reg_group);
6306                 return 0;
6307         }
6308
6309         return -ENOTSUP;
6310 }
6311
6312 static int
6313 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6314 {
6315         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6316
6317         /* Return unit is byte count */
6318         return hw->eeprom.word_size * 2;
6319 }
6320
6321 static int
6322 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6323                 struct rte_dev_eeprom_info *in_eeprom)
6324 {
6325         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6326         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6327         uint16_t *data = in_eeprom->data;
6328         int first, length;
6329
6330         first = in_eeprom->offset >> 1;
6331         length = in_eeprom->length >> 1;
6332         if ((first > hw->eeprom.word_size) ||
6333             ((first + length) > hw->eeprom.word_size))
6334                 return -EINVAL;
6335
6336         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6337
6338         return eeprom->ops.read_buffer(hw, first, length, data);
6339 }
6340
6341 static int
6342 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6343                 struct rte_dev_eeprom_info *in_eeprom)
6344 {
6345         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6346         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6347         uint16_t *data = in_eeprom->data;
6348         int first, length;
6349
6350         first = in_eeprom->offset >> 1;
6351         length = in_eeprom->length >> 1;
6352         if ((first > hw->eeprom.word_size) ||
6353             ((first + length) > hw->eeprom.word_size))
6354                 return -EINVAL;
6355
6356         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6357
6358         return eeprom->ops.write_buffer(hw,  first, length, data);
6359 }
6360
6361 uint16_t
6362 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6363         switch (mac_type) {
6364         case ixgbe_mac_X550:
6365         case ixgbe_mac_X550EM_x:
6366         case ixgbe_mac_X550EM_a:
6367                 return ETH_RSS_RETA_SIZE_512;
6368         case ixgbe_mac_X550_vf:
6369         case ixgbe_mac_X550EM_x_vf:
6370         case ixgbe_mac_X550EM_a_vf:
6371                 return ETH_RSS_RETA_SIZE_64;
6372         default:
6373                 return ETH_RSS_RETA_SIZE_128;
6374         }
6375 }
6376
6377 uint32_t
6378 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6379         switch (mac_type) {
6380         case ixgbe_mac_X550:
6381         case ixgbe_mac_X550EM_x:
6382         case ixgbe_mac_X550EM_a:
6383                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6384                         return IXGBE_RETA(reta_idx >> 2);
6385                 else
6386                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6387         case ixgbe_mac_X550_vf:
6388         case ixgbe_mac_X550EM_x_vf:
6389         case ixgbe_mac_X550EM_a_vf:
6390                 return IXGBE_VFRETA(reta_idx >> 2);
6391         default:
6392                 return IXGBE_RETA(reta_idx >> 2);
6393         }
6394 }
6395
6396 uint32_t
6397 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6398         switch (mac_type) {
6399         case ixgbe_mac_X550_vf:
6400         case ixgbe_mac_X550EM_x_vf:
6401         case ixgbe_mac_X550EM_a_vf:
6402                 return IXGBE_VFMRQC;
6403         default:
6404                 return IXGBE_MRQC;
6405         }
6406 }
6407
6408 uint32_t
6409 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6410         switch (mac_type) {
6411         case ixgbe_mac_X550_vf:
6412         case ixgbe_mac_X550EM_x_vf:
6413         case ixgbe_mac_X550EM_a_vf:
6414                 return IXGBE_VFRSSRK(i);
6415         default:
6416                 return IXGBE_RSSRK(i);
6417         }
6418 }
6419
6420 bool
6421 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6422         switch (mac_type) {
6423         case ixgbe_mac_82599_vf:
6424         case ixgbe_mac_X540_vf:
6425                 return 0;
6426         default:
6427                 return 1;
6428         }
6429 }
6430
6431 static int
6432 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6433                         struct rte_eth_dcb_info *dcb_info)
6434 {
6435         struct ixgbe_dcb_config *dcb_config =
6436                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6437         struct ixgbe_dcb_tc_config *tc;
6438         uint8_t i, j;
6439
6440         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6441                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6442         else
6443                 dcb_info->nb_tcs = 1;
6444
6445         if (dcb_config->vt_mode) { /* vt is enabled*/
6446                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6447                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6448                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6449                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6450                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6451                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6452                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6453                                                 i * dcb_info->nb_tcs + j;
6454                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6455                                 dcb_info->tc_queue.tc_txq[i][j].base =
6456                                                 i * dcb_info->nb_tcs + j;
6457                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6458                         }
6459                 }
6460         } else { /* vt is disabled*/
6461                 struct rte_eth_dcb_rx_conf *rx_conf =
6462                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6463                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6464                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6465                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6466                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6467                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6468                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6469                         }
6470                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6471                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6472                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6473                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6474                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6475                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6476                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6477                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6478                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6479                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6480                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6481                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6482                         }
6483                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6484                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6485                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6486                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6487                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6488                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6489                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6490                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6491                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6492                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6493                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6494                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6495                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6496                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6497                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6498                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6499                 }
6500         }
6501         for (i = 0; i < dcb_info->nb_tcs; i++) {
6502                 tc = &dcb_config->tc_config[i];
6503                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6504         }
6505         return 0;
6506 }
6507
6508 /* Update e-tag ether type */
6509 static int
6510 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6511                             uint16_t ether_type)
6512 {
6513         uint32_t etag_etype;
6514
6515         if (hw->mac.type != ixgbe_mac_X550 &&
6516             hw->mac.type != ixgbe_mac_X550EM_x &&
6517             hw->mac.type != ixgbe_mac_X550EM_a) {
6518                 return -ENOTSUP;
6519         }
6520
6521         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6522         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6523         etag_etype |= ether_type;
6524         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6525         IXGBE_WRITE_FLUSH(hw);
6526
6527         return 0;
6528 }
6529
6530 /* Config l2 tunnel ether type */
6531 static int
6532 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6533                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6534 {
6535         int ret = 0;
6536         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6537
6538         if (l2_tunnel == NULL)
6539                 return -EINVAL;
6540
6541         switch (l2_tunnel->l2_tunnel_type) {
6542         case RTE_L2_TUNNEL_TYPE_E_TAG:
6543                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6544                 break;
6545         default:
6546                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6547                 ret = -EINVAL;
6548                 break;
6549         }
6550
6551         return ret;
6552 }
6553
6554 /* Enable e-tag tunnel */
6555 static int
6556 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6557 {
6558         uint32_t etag_etype;
6559
6560         if (hw->mac.type != ixgbe_mac_X550 &&
6561             hw->mac.type != ixgbe_mac_X550EM_x &&
6562             hw->mac.type != ixgbe_mac_X550EM_a) {
6563                 return -ENOTSUP;
6564         }
6565
6566         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6567         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6568         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6569         IXGBE_WRITE_FLUSH(hw);
6570
6571         return 0;
6572 }
6573
6574 /* Enable l2 tunnel */
6575 static int
6576 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6577                            enum rte_eth_tunnel_type l2_tunnel_type)
6578 {
6579         int ret = 0;
6580         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6581
6582         switch (l2_tunnel_type) {
6583         case RTE_L2_TUNNEL_TYPE_E_TAG:
6584                 ret = ixgbe_e_tag_enable(hw);
6585                 break;
6586         default:
6587                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6588                 ret = -EINVAL;
6589                 break;
6590         }
6591
6592         return ret;
6593 }
6594
6595 /* Disable e-tag tunnel */
6596 static int
6597 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6598 {
6599         uint32_t etag_etype;
6600
6601         if (hw->mac.type != ixgbe_mac_X550 &&
6602             hw->mac.type != ixgbe_mac_X550EM_x &&
6603             hw->mac.type != ixgbe_mac_X550EM_a) {
6604                 return -ENOTSUP;
6605         }
6606
6607         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6608         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6609         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6610         IXGBE_WRITE_FLUSH(hw);
6611
6612         return 0;
6613 }
6614
6615 /* Disable l2 tunnel */
6616 static int
6617 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6618                             enum rte_eth_tunnel_type l2_tunnel_type)
6619 {
6620         int ret = 0;
6621         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6622
6623         switch (l2_tunnel_type) {
6624         case RTE_L2_TUNNEL_TYPE_E_TAG:
6625                 ret = ixgbe_e_tag_disable(hw);
6626                 break;
6627         default:
6628                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6629                 ret = -EINVAL;
6630                 break;
6631         }
6632
6633         return ret;
6634 }
6635
6636 static int
6637 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6638                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6639 {
6640         int ret = 0;
6641         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6642         uint32_t i, rar_entries;
6643         uint32_t rar_low, rar_high;
6644
6645         if (hw->mac.type != ixgbe_mac_X550 &&
6646             hw->mac.type != ixgbe_mac_X550EM_x &&
6647             hw->mac.type != ixgbe_mac_X550EM_a) {
6648                 return -ENOTSUP;
6649         }
6650
6651         rar_entries = ixgbe_get_num_rx_addrs(hw);
6652
6653         for (i = 1; i < rar_entries; i++) {
6654                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6655                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6656                 if ((rar_high & IXGBE_RAH_AV) &&
6657                     (rar_high & IXGBE_RAH_ADTYPE) &&
6658                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6659                      l2_tunnel->tunnel_id)) {
6660                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6661                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6662
6663                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6664
6665                         return ret;
6666                 }
6667         }
6668
6669         return ret;
6670 }
6671
6672 static int
6673 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6674                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6675 {
6676         int ret = 0;
6677         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6678         uint32_t i, rar_entries;
6679         uint32_t rar_low, rar_high;
6680
6681         if (hw->mac.type != ixgbe_mac_X550 &&
6682             hw->mac.type != ixgbe_mac_X550EM_x &&
6683             hw->mac.type != ixgbe_mac_X550EM_a) {
6684                 return -ENOTSUP;
6685         }
6686
6687         /* One entry for one tunnel. Try to remove potential existing entry. */
6688         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6689
6690         rar_entries = ixgbe_get_num_rx_addrs(hw);
6691
6692         for (i = 1; i < rar_entries; i++) {
6693                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6694                 if (rar_high & IXGBE_RAH_AV) {
6695                         continue;
6696                 } else {
6697                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6698                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6699                         rar_low = l2_tunnel->tunnel_id;
6700
6701                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6702                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6703
6704                         return ret;
6705                 }
6706         }
6707
6708         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6709                      " Please remove a rule before adding a new one.");
6710         return -EINVAL;
6711 }
6712
6713 /* Add l2 tunnel filter */
6714 static int
6715 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6716                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6717 {
6718         int ret = 0;
6719
6720         switch (l2_tunnel->l2_tunnel_type) {
6721         case RTE_L2_TUNNEL_TYPE_E_TAG:
6722                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6723                 break;
6724         default:
6725                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6726                 ret = -EINVAL;
6727                 break;
6728         }
6729
6730         return ret;
6731 }
6732
6733 /* Delete l2 tunnel filter */
6734 static int
6735 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6736                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6737 {
6738         int ret = 0;
6739
6740         switch (l2_tunnel->l2_tunnel_type) {
6741         case RTE_L2_TUNNEL_TYPE_E_TAG:
6742                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6743                 break;
6744         default:
6745                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6746                 ret = -EINVAL;
6747                 break;
6748         }
6749
6750         return ret;
6751 }
6752
6753 /**
6754  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6755  * @dev: pointer to rte_eth_dev structure
6756  * @filter_op:operation will be taken.
6757  * @arg: a pointer to specific structure corresponding to the filter_op
6758  */
6759 static int
6760 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6761                                   enum rte_filter_op filter_op,
6762                                   void *arg)
6763 {
6764         int ret = 0;
6765
6766         if (filter_op == RTE_ETH_FILTER_NOP)
6767                 return 0;
6768
6769         if (arg == NULL) {
6770                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6771                             filter_op);
6772                 return -EINVAL;
6773         }
6774
6775         switch (filter_op) {
6776         case RTE_ETH_FILTER_ADD:
6777                 ret = ixgbe_dev_l2_tunnel_filter_add
6778                         (dev,
6779                          (struct rte_eth_l2_tunnel_conf *)arg);
6780                 break;
6781         case RTE_ETH_FILTER_DELETE:
6782                 ret = ixgbe_dev_l2_tunnel_filter_del
6783                         (dev,
6784                          (struct rte_eth_l2_tunnel_conf *)arg);
6785                 break;
6786         default:
6787                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6788                 ret = -EINVAL;
6789                 break;
6790         }
6791         return ret;
6792 }
6793
6794 static int
6795 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6796 {
6797         int ret = 0;
6798         uint32_t ctrl;
6799         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6800
6801         if (hw->mac.type != ixgbe_mac_X550 &&
6802             hw->mac.type != ixgbe_mac_X550EM_x &&
6803             hw->mac.type != ixgbe_mac_X550EM_a) {
6804                 return -ENOTSUP;
6805         }
6806
6807         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6808         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6809         if (en)
6810                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6811         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6812
6813         return ret;
6814 }
6815
6816 /* Enable l2 tunnel forwarding */
6817 static int
6818 ixgbe_dev_l2_tunnel_forwarding_enable
6819         (struct rte_eth_dev *dev,
6820          enum rte_eth_tunnel_type l2_tunnel_type)
6821 {
6822         int ret = 0;
6823
6824         switch (l2_tunnel_type) {
6825         case RTE_L2_TUNNEL_TYPE_E_TAG:
6826                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6827                 break;
6828         default:
6829                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6830                 ret = -EINVAL;
6831                 break;
6832         }
6833
6834         return ret;
6835 }
6836
6837 /* Disable l2 tunnel forwarding */
6838 static int
6839 ixgbe_dev_l2_tunnel_forwarding_disable
6840         (struct rte_eth_dev *dev,
6841          enum rte_eth_tunnel_type l2_tunnel_type)
6842 {
6843         int ret = 0;
6844
6845         switch (l2_tunnel_type) {
6846         case RTE_L2_TUNNEL_TYPE_E_TAG:
6847                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6848                 break;
6849         default:
6850                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6851                 ret = -EINVAL;
6852                 break;
6853         }
6854
6855         return ret;
6856 }
6857
6858 static int
6859 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6860                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6861                              bool en)
6862 {
6863         int ret = 0;
6864         uint32_t vmtir, vmvir;
6865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6866
6867         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6868                 PMD_DRV_LOG(ERR,
6869                             "VF id %u should be less than %u",
6870                             l2_tunnel->vf_id,
6871                             dev->pci_dev->max_vfs);
6872                 return -EINVAL;
6873         }
6874
6875         if (hw->mac.type != ixgbe_mac_X550 &&
6876             hw->mac.type != ixgbe_mac_X550EM_x &&
6877             hw->mac.type != ixgbe_mac_X550EM_a) {
6878                 return -ENOTSUP;
6879         }
6880
6881         if (en)
6882                 vmtir = l2_tunnel->tunnel_id;
6883         else
6884                 vmtir = 0;
6885
6886         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6887
6888         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6889         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6890         if (en)
6891                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6892         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6893
6894         return ret;
6895 }
6896
6897 /* Enable l2 tunnel tag insertion */
6898 static int
6899 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6900                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6901 {
6902         int ret = 0;
6903
6904         switch (l2_tunnel->l2_tunnel_type) {
6905         case RTE_L2_TUNNEL_TYPE_E_TAG:
6906                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6907                 break;
6908         default:
6909                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6910                 ret = -EINVAL;
6911                 break;
6912         }
6913
6914         return ret;
6915 }
6916
6917 /* Disable l2 tunnel tag insertion */
6918 static int
6919 ixgbe_dev_l2_tunnel_insertion_disable
6920         (struct rte_eth_dev *dev,
6921          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6922 {
6923         int ret = 0;
6924
6925         switch (l2_tunnel->l2_tunnel_type) {
6926         case RTE_L2_TUNNEL_TYPE_E_TAG:
6927                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6928                 break;
6929         default:
6930                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6931                 ret = -EINVAL;
6932                 break;
6933         }
6934
6935         return ret;
6936 }
6937
6938 static int
6939 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6940                              bool en)
6941 {
6942         int ret = 0;
6943         uint32_t qde;
6944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6945
6946         if (hw->mac.type != ixgbe_mac_X550 &&
6947             hw->mac.type != ixgbe_mac_X550EM_x &&
6948             hw->mac.type != ixgbe_mac_X550EM_a) {
6949                 return -ENOTSUP;
6950         }
6951
6952         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6953         if (en)
6954                 qde |= IXGBE_QDE_STRIP_TAG;
6955         else
6956                 qde &= ~IXGBE_QDE_STRIP_TAG;
6957         qde &= ~IXGBE_QDE_READ;
6958         qde |= IXGBE_QDE_WRITE;
6959         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6960
6961         return ret;
6962 }
6963
6964 /* Enable l2 tunnel tag stripping */
6965 static int
6966 ixgbe_dev_l2_tunnel_stripping_enable
6967         (struct rte_eth_dev *dev,
6968          enum rte_eth_tunnel_type l2_tunnel_type)
6969 {
6970         int ret = 0;
6971
6972         switch (l2_tunnel_type) {
6973         case RTE_L2_TUNNEL_TYPE_E_TAG:
6974                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6975                 break;
6976         default:
6977                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6978                 ret = -EINVAL;
6979                 break;
6980         }
6981
6982         return ret;
6983 }
6984
6985 /* Disable l2 tunnel tag stripping */
6986 static int
6987 ixgbe_dev_l2_tunnel_stripping_disable
6988         (struct rte_eth_dev *dev,
6989          enum rte_eth_tunnel_type l2_tunnel_type)
6990 {
6991         int ret = 0;
6992
6993         switch (l2_tunnel_type) {
6994         case RTE_L2_TUNNEL_TYPE_E_TAG:
6995                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6996                 break;
6997         default:
6998                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6999                 ret = -EINVAL;
7000                 break;
7001         }
7002
7003         return ret;
7004 }
7005
7006 /* Enable/disable l2 tunnel offload functions */
7007 static int
7008 ixgbe_dev_l2_tunnel_offload_set
7009         (struct rte_eth_dev *dev,
7010          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7011          uint32_t mask,
7012          uint8_t en)
7013 {
7014         int ret = 0;
7015
7016         if (l2_tunnel == NULL)
7017                 return -EINVAL;
7018
7019         ret = -EINVAL;
7020         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7021                 if (en)
7022                         ret = ixgbe_dev_l2_tunnel_enable(
7023                                 dev,
7024                                 l2_tunnel->l2_tunnel_type);
7025                 else
7026                         ret = ixgbe_dev_l2_tunnel_disable(
7027                                 dev,
7028                                 l2_tunnel->l2_tunnel_type);
7029         }
7030
7031         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7032                 if (en)
7033                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7034                                 dev,
7035                                 l2_tunnel);
7036                 else
7037                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7038                                 dev,
7039                                 l2_tunnel);
7040         }
7041
7042         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7043                 if (en)
7044                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7045                                 dev,
7046                                 l2_tunnel->l2_tunnel_type);
7047                 else
7048                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7049                                 dev,
7050                                 l2_tunnel->l2_tunnel_type);
7051         }
7052
7053         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7054                 if (en)
7055                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7056                                 dev,
7057                                 l2_tunnel->l2_tunnel_type);
7058                 else
7059                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7060                                 dev,
7061                                 l2_tunnel->l2_tunnel_type);
7062         }
7063
7064         return ret;
7065 }
7066
7067 static int
7068 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7069                         uint16_t port)
7070 {
7071         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7072         IXGBE_WRITE_FLUSH(hw);
7073
7074         return 0;
7075 }
7076
7077 /* There's only one register for VxLAN UDP port.
7078  * So, we cannot add several ports. Will update it.
7079  */
7080 static int
7081 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7082                      uint16_t port)
7083 {
7084         if (port == 0) {
7085                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7086                 return -EINVAL;
7087         }
7088
7089         return ixgbe_update_vxlan_port(hw, port);
7090 }
7091
7092 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7093  * UDP port, it must have a value.
7094  * So, will reset it to the original value 0.
7095  */
7096 static int
7097 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7098                      uint16_t port)
7099 {
7100         uint16_t cur_port;
7101
7102         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7103
7104         if (cur_port != port) {
7105                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7106                 return -EINVAL;
7107         }
7108
7109         return ixgbe_update_vxlan_port(hw, 0);
7110 }
7111
7112 /* Add UDP tunneling port */
7113 static int
7114 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7115                               struct rte_eth_udp_tunnel *udp_tunnel)
7116 {
7117         int ret = 0;
7118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7119
7120         if (hw->mac.type != ixgbe_mac_X550 &&
7121             hw->mac.type != ixgbe_mac_X550EM_x &&
7122             hw->mac.type != ixgbe_mac_X550EM_a) {
7123                 return -ENOTSUP;
7124         }
7125
7126         if (udp_tunnel == NULL)
7127                 return -EINVAL;
7128
7129         switch (udp_tunnel->prot_type) {
7130         case RTE_TUNNEL_TYPE_VXLAN:
7131                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7132                 break;
7133
7134         case RTE_TUNNEL_TYPE_GENEVE:
7135         case RTE_TUNNEL_TYPE_TEREDO:
7136                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7137                 ret = -EINVAL;
7138                 break;
7139
7140         default:
7141                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7142                 ret = -EINVAL;
7143                 break;
7144         }
7145
7146         return ret;
7147 }
7148
7149 /* Remove UDP tunneling port */
7150 static int
7151 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7152                               struct rte_eth_udp_tunnel *udp_tunnel)
7153 {
7154         int ret = 0;
7155         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7156
7157         if (hw->mac.type != ixgbe_mac_X550 &&
7158             hw->mac.type != ixgbe_mac_X550EM_x &&
7159             hw->mac.type != ixgbe_mac_X550EM_a) {
7160                 return -ENOTSUP;
7161         }
7162
7163         if (udp_tunnel == NULL)
7164                 return -EINVAL;
7165
7166         switch (udp_tunnel->prot_type) {
7167         case RTE_TUNNEL_TYPE_VXLAN:
7168                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7169                 break;
7170         case RTE_TUNNEL_TYPE_GENEVE:
7171         case RTE_TUNNEL_TYPE_TEREDO:
7172                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7173                 ret = -EINVAL;
7174                 break;
7175         default:
7176                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7177                 ret = -EINVAL;
7178                 break;
7179         }
7180
7181         return ret;
7182 }
7183
7184 /* ixgbevf_update_xcast_mode - Update Multicast mode
7185  * @hw: pointer to the HW structure
7186  * @netdev: pointer to net device structure
7187  * @xcast_mode: new multicast mode
7188  *
7189  * Updates the Multicast Mode of VF.
7190  */
7191 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7192                                      int xcast_mode)
7193 {
7194         struct ixgbe_mbx_info *mbx = &hw->mbx;
7195         u32 msgbuf[2];
7196         s32 err;
7197
7198         switch (hw->api_version) {
7199         case ixgbe_mbox_api_12:
7200                 break;
7201         default:
7202                 return -EOPNOTSUPP;
7203         }
7204
7205         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7206         msgbuf[1] = xcast_mode;
7207
7208         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7209         if (err)
7210                 return err;
7211
7212         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7213         if (err)
7214                 return err;
7215
7216         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7217         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7218                 return -EPERM;
7219
7220         return 0;
7221 }
7222
7223 static void
7224 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7225 {
7226         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7227
7228         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7229 }
7230
7231 static void
7232 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7233 {
7234         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7235
7236         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7237 }
7238
7239 static struct rte_driver rte_ixgbe_driver = {
7240         .type = PMD_PDEV,
7241         .init = rte_ixgbe_pmd_init,
7242 };
7243
7244 static struct rte_driver rte_ixgbevf_driver = {
7245         .type = PMD_PDEV,
7246         .init = rte_ixgbevf_pmd_init,
7247 };
7248
7249 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7250 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);