drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 183                                              uint16_t queue_id,
 184                                              uint8_t stat_idx,
 185                                              uint8_t is_rx);
 186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 187                                struct rte_eth_dev_info *dev_info);
 188 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                  struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 202 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 203 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 204 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 205 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 206
 207 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 208 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 209 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 210                                struct rte_eth_fc_conf *fc_conf);
 211 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 212                                struct rte_eth_fc_conf *fc_conf);
 213 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 214                 struct rte_eth_pfc_conf *pfc_conf);
 215 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 226 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 227                 void *param);
 228 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 229 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 230                 uint32_t index, uint32_t pool);
 231 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 232 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 233                                            struct ether_addr *mac_addr);
 234 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 244 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 245 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 255                                             uint16_t queue_id);
 256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 257                                              uint16_t queue_id);
 258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 259                                  uint8_t queue, uint8_t msix_vector);
 260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 263
 264 /* For Eth VMDQ APIs support */
 265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 266                 ether_addr* mac_addr,uint8_t on);
 267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 268 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 269                 uint16_t rx_mask, uint8_t on);
 270 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 271 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 272 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 273                 uint64_t pool_mask,uint8_t vlan_on);
 274 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 275                 struct rte_eth_mirror_conf *mirror_conf,
 276                 uint8_t rule_id, uint8_t on);
 277 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 278                 uint8_t rule_id);
 279 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 280                                           uint16_t queue_id);
 281 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 282                                            uint16_t queue_id);
 283 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 284                                uint8_t queue, uint8_t msix_vector);
 285 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 286
 287 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 288                 uint16_t queue_idx, uint16_t tx_rate);
 289 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 290                 uint16_t tx_rate, uint64_t q_msk);
 291
 292 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 293                                  struct ether_addr *mac_addr,
 294                                  uint32_t index, uint32_t pool);
 295 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 296 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 297                                              struct ether_addr *mac_addr);
 298 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 299                         struct rte_eth_syn_filter *filter,
 300                         bool add);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 311                         struct rte_eth_ntuple_filter *filter,
 312                         bool add);
 313 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 314                                 enum rte_filter_op filter_op,
 315                                 void *arg);
 316 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 317                         struct rte_eth_ntuple_filter *filter);
 318 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter,
 320                         bool add);
 321 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ethertype_filter *filter);
 326 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                      enum rte_filter_type filter_type,
 328                      enum rte_filter_op filter_op,
 329                      void *arg);
 330 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 331
 332 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 333                                       struct ether_addr *mc_addr_set,
 334                                       uint32_t nb_mc_addr);
 335 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 336                                    struct rte_eth_dcb_info *dcb_info);
 337
 338 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 339 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 340                             struct rte_dev_reg_info *regs);
 341 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 342 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 343                                 struct rte_dev_eeprom_info *eeprom);
 344 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 345                                 struct rte_dev_eeprom_info *eeprom);
 346
 347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 349                                 struct rte_dev_reg_info *regs);
 350
 351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                             struct timespec *timestamp,
 355                                             uint32_t flags);
 356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                             struct timespec *timestamp);
 358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 362                                    const struct timespec *timestamp);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379
 380 /*
 381  * Define VF Stats MACRO for Non "cleared on read" register
 382  */
 383 #define UPDATE_VF_STAT(reg, last, cur)                          \
 384 {                                                               \
 385         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 386         cur += (latest - last) & UINT_MAX;                      \
 387         last = latest;                                          \
 388 }
 389
 390 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 391 {                                                                \
 392         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 393         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 394         u64 latest = ((new_msb << 32) | new_lsb);                \
 395         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 396         last = latest;                                           \
 397 }
 398
 399 #define IXGBE_SET_HWSTRIP(h, q) do{\
 400                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 402                 (h)->bitmap[idx] |= 1 << bit;\
 403         } while (0)
 404
 405 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 406                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 407                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 408                 (h)->bitmap[idx] &= ~(1 << bit);\
 409         } while (0)
 410
 411 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 412                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 413                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 414                 (r) = (h)->bitmap[idx] >> bit & 1;\
 415         } while (0)
 416
 417 /*
 418  * The set of PCI devices this driver supports
 419  */
 420 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 421
 422 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 423 #include "rte_pci_dev_ids.h"
 424
 425 { .vendor_id = 0, /* sentinel */ },
 426 };
 427
 428
 429 /*
 430  * The set of PCI devices this driver supports (for 82599 VF)
 431  */
 432 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 433
 434 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 435 #include "rte_pci_dev_ids.h"
 436 { .vendor_id = 0, /* sentinel */ },
 437
 438 };
 439
 440 static const struct rte_eth_desc_lim rx_desc_lim = {
 441         .nb_max = IXGBE_MAX_RING_DESC,
 442         .nb_min = IXGBE_MIN_RING_DESC,
 443         .nb_align = IXGBE_RXD_ALIGN,
 444 };
 445
 446 static const struct rte_eth_desc_lim tx_desc_lim = {
 447         .nb_max = IXGBE_MAX_RING_DESC,
 448         .nb_min = IXGBE_MIN_RING_DESC,
 449         .nb_align = IXGBE_TXD_ALIGN,
 450 };
 451
 452 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 453         .dev_configure        = ixgbe_dev_configure,
 454         .dev_start            = ixgbe_dev_start,
 455         .dev_stop             = ixgbe_dev_stop,
 456         .dev_set_link_up    = ixgbe_dev_set_link_up,
 457         .dev_set_link_down  = ixgbe_dev_set_link_down,
 458         .dev_close            = ixgbe_dev_close,
 459         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 460         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 461         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 462         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 463         .link_update          = ixgbe_dev_link_update,
 464         .stats_get            = ixgbe_dev_stats_get,
 465         .xstats_get           = ixgbe_dev_xstats_get,
 466         .stats_reset          = ixgbe_dev_stats_reset,
 467         .xstats_reset         = ixgbe_dev_xstats_reset,
 468         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 469         .dev_infos_get        = ixgbe_dev_info_get,
 470         .mtu_set              = ixgbe_dev_mtu_set,
 471         .vlan_filter_set      = ixgbe_vlan_filter_set,
 472         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 473         .vlan_offload_set     = ixgbe_vlan_offload_set,
 474         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 475         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 476         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 477         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 478         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 479         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 480         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 481         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 482         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 483         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 484         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 485         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 486         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 487         .dev_led_on           = ixgbe_dev_led_on,
 488         .dev_led_off          = ixgbe_dev_led_off,
 489         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 490         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 491         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 492         .mac_addr_add         = ixgbe_add_rar,
 493         .mac_addr_remove      = ixgbe_remove_rar,
 494         .mac_addr_set         = ixgbe_set_default_mac_addr,
 495         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 496         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 497         .mirror_rule_set      = ixgbe_mirror_rule_set,
 498         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 499         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 500         .set_vf_rx            = ixgbe_set_pool_rx,
 501         .set_vf_tx            = ixgbe_set_pool_tx,
 502         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 503         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 504         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 505         .reta_update          = ixgbe_dev_rss_reta_update,
 506         .reta_query           = ixgbe_dev_rss_reta_query,
 507 #ifdef RTE_NIC_BYPASS
 508         .bypass_init          = ixgbe_bypass_init,
 509         .bypass_state_set     = ixgbe_bypass_state_store,
 510         .bypass_state_show    = ixgbe_bypass_state_show,
 511         .bypass_event_set     = ixgbe_bypass_event_store,
 512         .bypass_event_show    = ixgbe_bypass_event_show,
 513         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 514         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 515         .bypass_ver_show      = ixgbe_bypass_ver_show,
 516         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 517 #endif /* RTE_NIC_BYPASS */
 518         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 519         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 520         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 521         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 522         .rxq_info_get         = ixgbe_rxq_info_get,
 523         .txq_info_get         = ixgbe_txq_info_get,
 524         .timesync_enable      = ixgbe_timesync_enable,
 525         .timesync_disable     = ixgbe_timesync_disable,
 526         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 527         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 528         .get_reg_length       = ixgbe_get_reg_length,
 529         .get_reg              = ixgbe_get_regs,
 530         .get_eeprom_length    = ixgbe_get_eeprom_length,
 531         .get_eeprom           = ixgbe_get_eeprom,
 532         .set_eeprom           = ixgbe_set_eeprom,
 533         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 534         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 535         .timesync_read_time   = ixgbe_timesync_read_time,
 536         .timesync_write_time  = ixgbe_timesync_write_time,
 537         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 538         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 539         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 540         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 541 };
 542
 543 /*
 544  * dev_ops for virtual function, bare necessities for basic vf
 545  * operation have been implemented
 546  */
 547 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 548         .dev_configure        = ixgbevf_dev_configure,
 549         .dev_start            = ixgbevf_dev_start,
 550         .dev_stop             = ixgbevf_dev_stop,
 551         .link_update          = ixgbe_dev_link_update,
 552         .stats_get            = ixgbevf_dev_stats_get,
 553         .xstats_get           = ixgbevf_dev_xstats_get,
 554         .stats_reset          = ixgbevf_dev_stats_reset,
 555         .xstats_reset         = ixgbevf_dev_stats_reset,
 556         .dev_close            = ixgbevf_dev_close,
 557         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 558         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 559         .dev_infos_get        = ixgbevf_dev_info_get,
 560         .mtu_set              = ixgbevf_dev_set_mtu,
 561         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 562         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 563         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 564         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 565         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 566         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 567         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 568         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 569         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 570         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 571         .mac_addr_add         = ixgbevf_add_mac_addr,
 572         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 573         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 574         .rxq_info_get         = ixgbe_rxq_info_get,
 575         .txq_info_get         = ixgbe_txq_info_get,
 576         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 577         .get_reg_length       = ixgbevf_get_reg_length,
 578         .get_reg              = ixgbevf_get_regs,
 579         .reta_update          = ixgbe_dev_rss_reta_update,
 580         .reta_query           = ixgbe_dev_rss_reta_query,
 581         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 582         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 583 };
 584
 585 /* store statistics names and its offset in stats structure */
 586 struct rte_ixgbe_xstats_name_off {
 587         char name[RTE_ETH_XSTATS_NAME_SIZE];
 588         unsigned offset;
 589 };
 590
 591 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 592         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 593         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 594         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 595         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 596         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 597         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 598         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 599         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 600         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 601         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 602         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 603         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 604         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 605         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 606         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 607                 prc1023)},
 608         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 609                 prc1522)},
 610         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 611         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 612         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 613         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 614         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 615         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 616         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 617         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 618         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 619         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 620         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 621         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 622         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 623         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 624         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 625         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 627                 ptc1023)},
 628         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 629                 ptc1522)},
 630         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 631         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 632         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 633         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 634
 635         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 636                 fdirustat_add)},
 637         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 638                 fdirustat_remove)},
 639         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 640                 fdirfstat_fadd)},
 641         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 642                 fdirfstat_fremove)},
 643         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 644                 fdirmatch)},
 645         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 646                 fdirmiss)},
 647
 648         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 649         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 650         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 651                 fclast)},
 652         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 653         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 654         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 655         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 656         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 657                 fcoe_noddp)},
 658         {"rx_fcoe_no_direct_data_placement_ext_buff",
 659                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 660
 661         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 662                 lxontxc)},
 663         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 664                 lxonrxc)},
 665         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 666                 lxofftxc)},
 667         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 668                 lxoffrxc)},
 669         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 670 };
 671
 672 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 673                            sizeof(rte_ixgbe_stats_strings[0]))
 674
 675 /* Per-queue statistics */
 676 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 677         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 678         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 679         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 680         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 681 };
 682
 683 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 684                            sizeof(rte_ixgbe_rxq_strings[0]))
 685
 686 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 687         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 688         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 689         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 690                 pxon2offc)},
 691 };
 692
 693 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 694                            sizeof(rte_ixgbe_txq_strings[0]))
 695
 696 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 697         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 698 };
 699
 700 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 701                 sizeof(rte_ixgbevf_stats_strings[0]))
 702
 703 /**
 704  * Atomically reads the link status information from global
 705  * structure rte_eth_dev.
 706  *
 707  * @param dev
 708  *   - Pointer to the structure rte_eth_dev to read from.
 709  *   - Pointer to the buffer to be saved with the link status.
 710  *
 711  * @return
 712  *   - On success, zero.
 713  *   - On failure, negative value.
 714  */
 715 static inline int
 716 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 717                                 struct rte_eth_link *link)
 718 {
 719         struct rte_eth_link *dst = link;
 720         struct rte_eth_link *src = &(dev->data->dev_link);
 721
 722         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 723                                         *(uint64_t *)src) == 0)
 724                 return -1;
 725
 726         return 0;
 727 }
 728
 729 /**
 730  * Atomically writes the link status information into global
 731  * structure rte_eth_dev.
 732  *
 733  * @param dev
 734  *   - Pointer to the structure rte_eth_dev to read from.
 735  *   - Pointer to the buffer to be saved with the link status.
 736  *
 737  * @return
 738  *   - On success, zero.
 739  *   - On failure, negative value.
 740  */
 741 static inline int
 742 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 743                                 struct rte_eth_link *link)
 744 {
 745         struct rte_eth_link *dst = &(dev->data->dev_link);
 746         struct rte_eth_link *src = link;
 747
 748         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 749                                         *(uint64_t *)src) == 0)
 750                 return -1;
 751
 752         return 0;
 753 }
 754
 755 /*
 756  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 757  */
 758 static inline int
 759 ixgbe_is_sfp(struct ixgbe_hw *hw)
 760 {
 761         switch (hw->phy.type) {
 762         case ixgbe_phy_sfp_avago:
 763         case ixgbe_phy_sfp_ftl:
 764         case ixgbe_phy_sfp_intel:
 765         case ixgbe_phy_sfp_unknown:
 766         case ixgbe_phy_sfp_passive_tyco:
 767         case ixgbe_phy_sfp_passive_unknown:
 768                 return 1;
 769         default:
 770                 return 0;
 771         }
 772 }
 773
 774 static inline int32_t
 775 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 776 {
 777         uint32_t ctrl_ext;
 778         int32_t status;
 779
 780         status = ixgbe_reset_hw(hw);
 781
 782         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 783         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 784         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 785         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 786         IXGBE_WRITE_FLUSH(hw);
 787
 788         return status;
 789 }
 790
 791 static inline void
 792 ixgbe_enable_intr(struct rte_eth_dev *dev)
 793 {
 794         struct ixgbe_interrupt *intr =
 795                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 796         struct ixgbe_hw *hw =
 797                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 798
 799         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 800         IXGBE_WRITE_FLUSH(hw);
 801 }
 802
 803 /*
 804  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 805  */
 806 static void
 807 ixgbe_disable_intr(struct ixgbe_hw *hw)
 808 {
 809         PMD_INIT_FUNC_TRACE();
 810
 811         if (hw->mac.type == ixgbe_mac_82598EB) {
 812                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 813         } else {
 814                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 815                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 816                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 817         }
 818         IXGBE_WRITE_FLUSH(hw);
 819 }
 820
 821 /*
 822  * This function resets queue statistics mapping registers.
 823  * From Niantic datasheet, Initialization of Statistics section:
 824  * "...if software requires the queue counters, the RQSMR and TQSM registers
 825  * must be re-programmed following a device reset.
 826  */
 827 static void
 828 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 829 {
 830         uint32_t i;
 831
 832         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 833                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 834                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 835         }
 836 }
 837
 838
 839 static int
 840 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 841                                   uint16_t queue_id,
 842                                   uint8_t stat_idx,
 843                                   uint8_t is_rx)
 844 {
 845 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 846 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 847 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 848
 849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 850         struct ixgbe_stat_mapping_registers *stat_mappings =
 851                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 852         uint32_t qsmr_mask = 0;
 853         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 854         uint32_t q_map;
 855         uint8_t n, offset;
 856
 857         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 858                 (hw->mac.type != ixgbe_mac_X540) &&
 859                 (hw->mac.type != ixgbe_mac_X550) &&
 860                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 861                 (hw->mac.type != ixgbe_mac_X550EM_a))
 862                 return -ENOSYS;
 863
 864         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 865                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 866                      queue_id, stat_idx);
 867
 868         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 869         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 870                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 871                 return -EIO;
 872         }
 873         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 874
 875         /* Now clear any previous stat_idx set */
 876         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 877         if (!is_rx)
 878                 stat_mappings->tqsm[n] &= ~clearing_mask;
 879         else
 880                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 881
 882         q_map = (uint32_t)stat_idx;
 883         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 884         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 885         if (!is_rx)
 886                 stat_mappings->tqsm[n] |= qsmr_mask;
 887         else
 888                 stat_mappings->rqsmr[n] |= qsmr_mask;
 889
 890         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 891                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 892                      queue_id, stat_idx);
 893         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 894                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 895
 896         /* Now write the mapping in the appropriate register */
 897         if (is_rx) {
 898                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 899                              stat_mappings->rqsmr[n], n);
 900                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 901         }
 902         else {
 903                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 904                              stat_mappings->tqsm[n], n);
 905                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 906         }
 907         return 0;
 908 }
 909
 910 static void
 911 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 912 {
 913         struct ixgbe_stat_mapping_registers *stat_mappings =
 914                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 916         int i;
 917
 918         /* write whatever was in stat mapping table to the NIC */
 919         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 920                 /* rx */
 921                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 922
 923                 /* tx */
 924                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 925         }
 926 }
 927
 928 static void
 929 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 930 {
 931         uint8_t i;
 932         struct ixgbe_dcb_tc_config *tc;
 933         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 934
 935         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 936         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 937         for (i = 0; i < dcb_max_tc; i++) {
 938                 tc = &dcb_config->tc_config[i];
 939                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 940                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 941                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 942                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 943                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 944                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 945                 tc->pfc = ixgbe_dcb_pfc_disabled;
 946         }
 947
 948         /* Initialize default user to priority mapping, UPx->TC0 */
 949         tc = &dcb_config->tc_config[0];
 950         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 951         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 952         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 953                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 954                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 955         }
 956         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 957         dcb_config->pfc_mode_enable = false;
 958         dcb_config->vt_mode = true;
 959         dcb_config->round_robin_enable = false;
 960         /* support all DCB capabilities in 82599 */
 961         dcb_config->support.capabilities = 0xFF;
 962
 963         /*we only support 4 Tcs for X540, X550 */
 964         if (hw->mac.type == ixgbe_mac_X540 ||
 965                 hw->mac.type == ixgbe_mac_X550 ||
 966                 hw->mac.type == ixgbe_mac_X550EM_x ||
 967                 hw->mac.type == ixgbe_mac_X550EM_a) {
 968                 dcb_config->num_tcs.pg_tcs = 4;
 969                 dcb_config->num_tcs.pfc_tcs = 4;
 970         }
 971 }
 972
 973 /*
 974  * Ensure that all locks are released before first NVM or PHY access
 975  */
 976 static void
 977 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 978 {
 979         uint16_t mask;
 980
 981         /*
 982          * Phy lock should not fail in this early stage. If this is the case,
 983          * it is due to an improper exit of the application.
 984          * So force the release of the faulty lock. Release of common lock
 985          * is done automatically by swfw_sync function.
 986          */
 987         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 988         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 989                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 990         }
 991         ixgbe_release_swfw_semaphore(hw, mask);
 992
 993         /*
 994          * These ones are more tricky since they are common to all ports; but
 995          * swfw_sync retries last long enough (1s) to be almost sure that if
 996          * lock can not be taken it is due to an improper lock of the
 997          * semaphore.
 998          */
 999         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1000         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1001                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1002         }
1003         ixgbe_release_swfw_semaphore(hw, mask);
1004 }
1005
1006 /*
1007  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1008  * It returns 0 on success.
1009  */
1010 static int
1011 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1012 {
1013         struct rte_pci_device *pci_dev;
1014         struct ixgbe_hw *hw =
1015                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1016         struct ixgbe_vfta * shadow_vfta =
1017                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1018         struct ixgbe_hwstrip *hwstrip =
1019                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1020         struct ixgbe_dcb_config *dcb_config =
1021                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1022         struct ixgbe_filter_info *filter_info =
1023                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1024         uint32_t ctrl_ext;
1025         uint16_t csum;
1026         int diag, i;
1027
1028         PMD_INIT_FUNC_TRACE();
1029
1030         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1031         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1032         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1033
1034         /*
1035          * For secondary processes, we don't initialise any further as primary
1036          * has already done this work. Only check we don't need a different
1037          * RX and TX function.
1038          */
1039         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1040                 struct ixgbe_tx_queue *txq;
1041                 /* TX queue function in primary, set by last queue initialized
1042                  * Tx queue may not initialized by primary process */
1043                 if (eth_dev->data->tx_queues) {
1044                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1045                         ixgbe_set_tx_function(eth_dev, txq);
1046                 } else {
1047                         /* Use default TX function if we get here */
1048                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1049                                              "Using default TX function.");
1050                 }
1051
1052                 ixgbe_set_rx_function(eth_dev);
1053
1054                 return 0;
1055         }
1056         pci_dev = eth_dev->pci_dev;
1057
1058         rte_eth_copy_pci_info(eth_dev, pci_dev);
1059
1060         /* Vendor and Device ID need to be set before init of shared code */
1061         hw->device_id = pci_dev->id.device_id;
1062         hw->vendor_id = pci_dev->id.vendor_id;
1063         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1064         hw->allow_unsupported_sfp = 1;
1065
1066         /* Initialize the shared code (base driver) */
1067 #ifdef RTE_NIC_BYPASS
1068         diag = ixgbe_bypass_init_shared_code(hw);
1069 #else
1070         diag = ixgbe_init_shared_code(hw);
1071 #endif /* RTE_NIC_BYPASS */
1072
1073         if (diag != IXGBE_SUCCESS) {
1074                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1075                 return -EIO;
1076         }
1077
1078         /* pick up the PCI bus settings for reporting later */
1079         ixgbe_get_bus_info(hw);
1080
1081         /* Unlock any pending hardware semaphore */
1082         ixgbe_swfw_lock_reset(hw);
1083
1084         /* Initialize DCB configuration*/
1085         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1086         ixgbe_dcb_init(hw,dcb_config);
1087         /* Get Hardware Flow Control setting */
1088         hw->fc.requested_mode = ixgbe_fc_full;
1089         hw->fc.current_mode = ixgbe_fc_full;
1090         hw->fc.pause_time = IXGBE_FC_PAUSE;
1091         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1092                 hw->fc.low_water[i] = IXGBE_FC_LO;
1093                 hw->fc.high_water[i] = IXGBE_FC_HI;
1094         }
1095         hw->fc.send_xon = 1;
1096
1097         /* Make sure we have a good EEPROM before we read from it */
1098         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1099         if (diag != IXGBE_SUCCESS) {
1100                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1101                 return -EIO;
1102         }
1103
1104 #ifdef RTE_NIC_BYPASS
1105         diag = ixgbe_bypass_init_hw(hw);
1106 #else
1107         diag = ixgbe_init_hw(hw);
1108 #endif /* RTE_NIC_BYPASS */
1109
1110         /*
1111          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1112          * is called too soon after the kernel driver unbinding/binding occurs.
1113          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1114          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1115          * also called. See ixgbe_identify_phy_82599(). The reason for the
1116          * failure is not known, and only occuts when virtualisation features
1117          * are disabled in the bios. A delay of 100ms  was found to be enough by
1118          * trial-and-error, and is doubled to be safe.
1119          */
1120         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1121                 rte_delay_ms(200);
1122                 diag = ixgbe_init_hw(hw);
1123         }
1124
1125         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1126                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1127                     "LOM.  Please be aware there may be issues associated "
1128                     "with your hardware.");
1129                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1130                     "please contact your Intel or hardware representative "
1131                     "who provided you with this hardware.");
1132         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1133                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1134         if (diag) {
1135                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1136                 return -EIO;
1137         }
1138
1139         /* Reset the hw statistics */
1140         ixgbe_dev_stats_reset(eth_dev);
1141
1142         /* disable interrupt */
1143         ixgbe_disable_intr(hw);
1144
1145         /* reset mappings for queue statistics hw counters*/
1146         ixgbe_reset_qstat_mappings(hw);
1147
1148         /* Allocate memory for storing MAC addresses */
1149         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1150                         hw->mac.num_rar_entries, 0);
1151         if (eth_dev->data->mac_addrs == NULL) {
1152                 PMD_INIT_LOG(ERR,
1153                         "Failed to allocate %u bytes needed to store "
1154                         "MAC addresses",
1155                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1156                 return -ENOMEM;
1157         }
1158         /* Copy the permanent MAC address */
1159         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1160                         &eth_dev->data->mac_addrs[0]);
1161
1162         /* Allocate memory for storing hash filter MAC addresses */
1163         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1164                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1165         if (eth_dev->data->hash_mac_addrs == NULL) {
1166                 PMD_INIT_LOG(ERR,
1167                         "Failed to allocate %d bytes needed to store MAC addresses",
1168                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1169                 return -ENOMEM;
1170         }
1171
1172         /* initialize the vfta */
1173         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1174
1175         /* initialize the hw strip bitmap*/
1176         memset(hwstrip, 0, sizeof(*hwstrip));
1177
1178         /* initialize PF if max_vfs not zero */
1179         ixgbe_pf_host_init(eth_dev);
1180
1181         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1182         /* let hardware know driver is loaded */
1183         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1184         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1185         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1186         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1187         IXGBE_WRITE_FLUSH(hw);
1188
1189         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1190                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1191                              (int) hw->mac.type, (int) hw->phy.type,
1192                              (int) hw->phy.sfp_type);
1193         else
1194                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1195                              (int) hw->mac.type, (int) hw->phy.type);
1196
1197         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1198                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1199                         pci_dev->id.device_id);
1200
1201         rte_intr_callback_register(&pci_dev->intr_handle,
1202                                    ixgbe_dev_interrupt_handler,
1203                                    (void *)eth_dev);
1204
1205         /* enable uio/vfio intr/eventfd mapping */
1206         rte_intr_enable(&pci_dev->intr_handle);
1207
1208         /* enable support intr */
1209         ixgbe_enable_intr(eth_dev);
1210
1211         /* initialize 5tuple filter list */
1212         TAILQ_INIT(&filter_info->fivetuple_list);
1213         memset(filter_info->fivetuple_mask, 0,
1214                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1215
1216         return 0;
1217 }
1218
1219 static int
1220 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1221 {
1222         struct rte_pci_device *pci_dev;
1223         struct ixgbe_hw *hw;
1224
1225         PMD_INIT_FUNC_TRACE();
1226
1227         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1228                 return -EPERM;
1229
1230         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1231         pci_dev = eth_dev->pci_dev;
1232
1233         if (hw->adapter_stopped == 0)
1234                 ixgbe_dev_close(eth_dev);
1235
1236         eth_dev->dev_ops = NULL;
1237         eth_dev->rx_pkt_burst = NULL;
1238         eth_dev->tx_pkt_burst = NULL;
1239
1240         /* Unlock any pending hardware semaphore */
1241         ixgbe_swfw_lock_reset(hw);
1242
1243         /* disable uio intr before callback unregister */
1244         rte_intr_disable(&(pci_dev->intr_handle));
1245         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1246                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1247
1248         /* uninitialize PF if max_vfs not zero */
1249         ixgbe_pf_host_uninit(eth_dev);
1250
1251         rte_free(eth_dev->data->mac_addrs);
1252         eth_dev->data->mac_addrs = NULL;
1253
1254         rte_free(eth_dev->data->hash_mac_addrs);
1255         eth_dev->data->hash_mac_addrs = NULL;
1256
1257         return 0;
1258 }
1259
1260 /*
1261  * Negotiate mailbox API version with the PF.
1262  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1263  * Then we try to negotiate starting with the most recent one.
1264  * If all negotiation attempts fail, then we will proceed with
1265  * the default one (ixgbe_mbox_api_10).
1266  */
1267 static void
1268 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1269 {
1270         int32_t i;
1271
1272         /* start with highest supported, proceed down */
1273         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1274                 ixgbe_mbox_api_12,
1275                 ixgbe_mbox_api_11,
1276                 ixgbe_mbox_api_10,
1277         };
1278
1279         for (i = 0;
1280                         i != RTE_DIM(sup_ver) &&
1281                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1282                         i++)
1283                 ;
1284 }
1285
1286 static void
1287 generate_random_mac_addr(struct ether_addr *mac_addr)
1288 {
1289         uint64_t random;
1290
1291         /* Set Organizationally Unique Identifier (OUI) prefix. */
1292         mac_addr->addr_bytes[0] = 0x00;
1293         mac_addr->addr_bytes[1] = 0x09;
1294         mac_addr->addr_bytes[2] = 0xC0;
1295         /* Force indication of locally assigned MAC address. */
1296         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1297         /* Generate the last 3 bytes of the MAC address with a random number. */
1298         random = rte_rand();
1299         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1300 }
1301
1302 /*
1303  * Virtual Function device init
1304  */
1305 static int
1306 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1307 {
1308         int diag;
1309         uint32_t tc, tcs;
1310         struct rte_pci_device *pci_dev;
1311         struct ixgbe_hw *hw =
1312                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1313         struct ixgbe_vfta * shadow_vfta =
1314                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1315         struct ixgbe_hwstrip *hwstrip =
1316                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1317         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1318
1319         PMD_INIT_FUNC_TRACE();
1320
1321         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1322         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1323         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1324
1325         /* for secondary processes, we don't initialise any further as primary
1326          * has already done this work. Only check we don't need a different
1327          * RX function */
1328         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1329                 struct ixgbe_tx_queue *txq;
1330                 /* TX queue function in primary, set by last queue initialized
1331                  * Tx queue may not initialized by primary process
1332                  */
1333                 if (eth_dev->data->tx_queues) {
1334                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1335                         ixgbe_set_tx_function(eth_dev, txq);
1336                 } else {
1337                         /* Use default TX function if we get here */
1338                         PMD_INIT_LOG(NOTICE,
1339                                 "No TX queues configured yet. Using default TX function.");
1340                 }
1341
1342                 ixgbe_set_rx_function(eth_dev);
1343
1344                 return 0;
1345         }
1346
1347         pci_dev = eth_dev->pci_dev;
1348
1349         rte_eth_copy_pci_info(eth_dev, pci_dev);
1350
1351         hw->device_id = pci_dev->id.device_id;
1352         hw->vendor_id = pci_dev->id.vendor_id;
1353         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1354
1355         /* initialize the vfta */
1356         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1357
1358         /* initialize the hw strip bitmap*/
1359         memset(hwstrip, 0, sizeof(*hwstrip));
1360
1361         /* Initialize the shared code (base driver) */
1362         diag = ixgbe_init_shared_code(hw);
1363         if (diag != IXGBE_SUCCESS) {
1364                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1365                 return -EIO;
1366         }
1367
1368         /* init_mailbox_params */
1369         hw->mbx.ops.init_params(hw);
1370
1371         /* Reset the hw statistics */
1372         ixgbevf_dev_stats_reset(eth_dev);
1373
1374         /* Disable the interrupts for VF */
1375         ixgbevf_intr_disable(hw);
1376
1377         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1378         diag = hw->mac.ops.reset_hw(hw);
1379
1380         /*
1381          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1382          * the underlying PF driver has not assigned a MAC address to the VF.
1383          * In this case, assign a random MAC address.
1384          */
1385         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1386                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1387                 return diag;
1388         }
1389
1390         /* negotiate mailbox API version to use with the PF. */
1391         ixgbevf_negotiate_api(hw);
1392
1393         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1394         ixgbevf_get_queues(hw, &tcs, &tc);
1395
1396         /* Allocate memory for storing MAC addresses */
1397         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1398                         hw->mac.num_rar_entries, 0);
1399         if (eth_dev->data->mac_addrs == NULL) {
1400                 PMD_INIT_LOG(ERR,
1401                         "Failed to allocate %u bytes needed to store "
1402                         "MAC addresses",
1403                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1404                 return -ENOMEM;
1405         }
1406
1407         /* Generate a random MAC address, if none was assigned by PF. */
1408         if (is_zero_ether_addr(perm_addr)) {
1409                 generate_random_mac_addr(perm_addr);
1410                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1411                 if (diag) {
1412                         rte_free(eth_dev->data->mac_addrs);
1413                         eth_dev->data->mac_addrs = NULL;
1414                         return diag;
1415                 }
1416                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1417                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1418                              "%02x:%02x:%02x:%02x:%02x:%02x",
1419                              perm_addr->addr_bytes[0],
1420                              perm_addr->addr_bytes[1],
1421                              perm_addr->addr_bytes[2],
1422                              perm_addr->addr_bytes[3],
1423                              perm_addr->addr_bytes[4],
1424                              perm_addr->addr_bytes[5]);
1425         }
1426
1427         /* Copy the permanent MAC address */
1428         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1429
1430         /* reset the hardware with the new settings */
1431         diag = hw->mac.ops.start_hw(hw);
1432         switch (diag) {
1433                 case  0:
1434                         break;
1435
1436                 default:
1437                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1438                         return -EIO;
1439         }
1440
1441         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1442                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1443                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1444
1445         return 0;
1446 }
1447
1448 /* Virtual Function device uninit */
1449
1450 static int
1451 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1452 {
1453         struct ixgbe_hw *hw;
1454
1455         PMD_INIT_FUNC_TRACE();
1456
1457         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1458                 return -EPERM;
1459
1460         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1461
1462         if (hw->adapter_stopped == 0)
1463                 ixgbevf_dev_close(eth_dev);
1464
1465         eth_dev->dev_ops = NULL;
1466         eth_dev->rx_pkt_burst = NULL;
1467         eth_dev->tx_pkt_burst = NULL;
1468
1469         /* Disable the interrupts for VF */
1470         ixgbevf_intr_disable(hw);
1471
1472         rte_free(eth_dev->data->mac_addrs);
1473         eth_dev->data->mac_addrs = NULL;
1474
1475         return 0;
1476 }
1477
1478 static struct eth_driver rte_ixgbe_pmd = {
1479         .pci_drv = {
1480                 .name = "rte_ixgbe_pmd",
1481                 .id_table = pci_id_ixgbe_map,
1482                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1483                         RTE_PCI_DRV_DETACHABLE,
1484         },
1485         .eth_dev_init = eth_ixgbe_dev_init,
1486         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1487         .dev_private_size = sizeof(struct ixgbe_adapter),
1488 };
1489
1490 /*
1491  * virtual function driver struct
1492  */
1493 static struct eth_driver rte_ixgbevf_pmd = {
1494         .pci_drv = {
1495                 .name = "rte_ixgbevf_pmd",
1496                 .id_table = pci_id_ixgbevf_map,
1497                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1498         },
1499         .eth_dev_init = eth_ixgbevf_dev_init,
1500         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1501         .dev_private_size = sizeof(struct ixgbe_adapter),
1502 };
1503
1504 /*
1505  * Driver initialization routine.
1506  * Invoked once at EAL init time.
1507  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1508  */
1509 static int
1510 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1511 {
1512         PMD_INIT_FUNC_TRACE();
1513
1514         rte_eth_driver_register(&rte_ixgbe_pmd);
1515         return 0;
1516 }
1517
1518 /*
1519  * VF Driver initialization routine.
1520  * Invoked one at EAL init time.
1521  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1522  */
1523 static int
1524 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1525 {
1526         PMD_INIT_FUNC_TRACE();
1527
1528         rte_eth_driver_register(&rte_ixgbevf_pmd);
1529         return 0;
1530 }
1531
1532 static int
1533 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1534 {
1535         struct ixgbe_hw *hw =
1536                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537         struct ixgbe_vfta * shadow_vfta =
1538                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1539         uint32_t vfta;
1540         uint32_t vid_idx;
1541         uint32_t vid_bit;
1542
1543         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1544         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1545         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1546         if (on)
1547                 vfta |= vid_bit;
1548         else
1549                 vfta &= ~vid_bit;
1550         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1551
1552         /* update local VFTA copy */
1553         shadow_vfta->vfta[vid_idx] = vfta;
1554
1555         return 0;
1556 }
1557
1558 static void
1559 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1560 {
1561         if (on)
1562                 ixgbe_vlan_hw_strip_enable(dev, queue);
1563         else
1564                 ixgbe_vlan_hw_strip_disable(dev, queue);
1565 }
1566
1567 static int
1568 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1569                     enum rte_vlan_type vlan_type,
1570                     uint16_t tpid)
1571 {
1572         struct ixgbe_hw *hw =
1573                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1574         int ret = 0;
1575
1576         switch (vlan_type) {
1577         case ETH_VLAN_TYPE_INNER:
1578                 /* Only the high 16-bits is valid */
1579                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1580                 break;
1581         default:
1582                 ret = -EINVAL;
1583                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1584                 break;
1585         }
1586
1587         return ret;
1588 }
1589
1590 void
1591 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1592 {
1593         struct ixgbe_hw *hw =
1594                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595         uint32_t vlnctrl;
1596
1597         PMD_INIT_FUNC_TRACE();
1598
1599         /* Filter Table Disable */
1600         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1601         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1602
1603         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1604 }
1605
1606 void
1607 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1608 {
1609         struct ixgbe_hw *hw =
1610                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611         struct ixgbe_vfta * shadow_vfta =
1612                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1613         uint32_t vlnctrl;
1614         uint16_t i;
1615
1616         PMD_INIT_FUNC_TRACE();
1617
1618         /* Filter Table Enable */
1619         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1620         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1621         vlnctrl |= IXGBE_VLNCTRL_VFE;
1622
1623         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1624
1625         /* write whatever is in local vfta copy */
1626         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1627                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1628 }
1629
1630 static void
1631 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1632 {
1633         struct ixgbe_hwstrip *hwstrip =
1634                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1635
1636         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1637                 return;
1638
1639         if (on)
1640                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1641         else
1642                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1643 }
1644
1645 static void
1646 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1647 {
1648         struct ixgbe_hw *hw =
1649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650         uint32_t ctrl;
1651
1652         PMD_INIT_FUNC_TRACE();
1653
1654         if (hw->mac.type == ixgbe_mac_82598EB) {
1655                 /* No queue level support */
1656                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1657                 return;
1658         }
1659         else {
1660                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1661                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1662                 ctrl &= ~IXGBE_RXDCTL_VME;
1663                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1664         }
1665         /* record those setting for HW strip per queue */
1666         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1667 }
1668
1669 static void
1670 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1671 {
1672         struct ixgbe_hw *hw =
1673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         uint32_t ctrl;
1675
1676         PMD_INIT_FUNC_TRACE();
1677
1678         if (hw->mac.type == ixgbe_mac_82598EB) {
1679                 /* No queue level supported */
1680                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1681                 return;
1682         }
1683         else {
1684                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1685                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1686                 ctrl |= IXGBE_RXDCTL_VME;
1687                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1688         }
1689         /* record those setting for HW strip per queue */
1690         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1691 }
1692
1693 void
1694 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1695 {
1696         struct ixgbe_hw *hw =
1697                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698         uint32_t ctrl;
1699         uint16_t i;
1700
1701         PMD_INIT_FUNC_TRACE();
1702
1703         if (hw->mac.type == ixgbe_mac_82598EB) {
1704                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1705                 ctrl &= ~IXGBE_VLNCTRL_VME;
1706                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1707         }
1708         else {
1709                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1710                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1711                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1712                         ctrl &= ~IXGBE_RXDCTL_VME;
1713                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1714
1715                         /* record those setting for HW strip per queue */
1716                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1717                 }
1718         }
1719 }
1720
1721 void
1722 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1723 {
1724         struct ixgbe_hw *hw =
1725                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         uint32_t ctrl;
1727         uint16_t i;
1728
1729         PMD_INIT_FUNC_TRACE();
1730
1731         if (hw->mac.type == ixgbe_mac_82598EB) {
1732                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1733                 ctrl |= IXGBE_VLNCTRL_VME;
1734                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1735         }
1736         else {
1737                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1738                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1739                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1740                         ctrl |= IXGBE_RXDCTL_VME;
1741                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1742
1743                         /* record those setting for HW strip per queue */
1744                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1745                 }
1746         }
1747 }
1748
1749 static void
1750 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1751 {
1752         struct ixgbe_hw *hw =
1753                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754         uint32_t ctrl;
1755
1756         PMD_INIT_FUNC_TRACE();
1757
1758         /* DMATXCTRL: Geric Double VLAN Disable */
1759         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1760         ctrl &= ~IXGBE_DMATXCTL_GDV;
1761         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1762
1763         /* CTRL_EXT: Global Double VLAN Disable */
1764         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1765         ctrl &= ~IXGBE_EXTENDED_VLAN;
1766         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1767
1768 }
1769
1770 static void
1771 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1772 {
1773         struct ixgbe_hw *hw =
1774                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775         uint32_t ctrl;
1776
1777         PMD_INIT_FUNC_TRACE();
1778
1779         /* DMATXCTRL: Geric Double VLAN Enable */
1780         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1781         ctrl |= IXGBE_DMATXCTL_GDV;
1782         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1783
1784         /* CTRL_EXT: Global Double VLAN Enable */
1785         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1786         ctrl |= IXGBE_EXTENDED_VLAN;
1787         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1788
1789         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1790         if (hw->mac.type == ixgbe_mac_X550 ||
1791             hw->mac.type == ixgbe_mac_X550EM_x) {
1792                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1793                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1794                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1795         }
1796
1797         /*
1798          * VET EXT field in the EXVET register = 0x8100 by default
1799          * So no need to change. Same to VT field of DMATXCTL register
1800          */
1801 }
1802
1803 static void
1804 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1805 {
1806         if (mask & ETH_VLAN_STRIP_MASK) {
1807                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1808                         ixgbe_vlan_hw_strip_enable_all(dev);
1809                 else
1810                         ixgbe_vlan_hw_strip_disable_all(dev);
1811         }
1812
1813         if (mask & ETH_VLAN_FILTER_MASK) {
1814                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1815                         ixgbe_vlan_hw_filter_enable(dev);
1816                 else
1817                         ixgbe_vlan_hw_filter_disable(dev);
1818         }
1819
1820         if (mask & ETH_VLAN_EXTEND_MASK) {
1821                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1822                         ixgbe_vlan_hw_extend_enable(dev);
1823                 else
1824                         ixgbe_vlan_hw_extend_disable(dev);
1825         }
1826 }
1827
1828 static void
1829 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1830 {
1831         struct ixgbe_hw *hw =
1832                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1834         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1835         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1836         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1837 }
1838
1839 static int
1840 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1841 {
1842         switch (nb_rx_q) {
1843         case 1:
1844         case 2:
1845                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1846                 break;
1847         case 4:
1848                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1849                 break;
1850         default:
1851                 return -EINVAL;
1852         }
1853
1854         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1855         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1856
1857         return 0;
1858 }
1859
1860 static int
1861 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1862 {
1863         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1864         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1865         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1866
1867         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1868                 /* check multi-queue mode */
1869                 switch (dev_conf->rxmode.mq_mode) {
1870                 case ETH_MQ_RX_VMDQ_DCB:
1871                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1872                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1873                         PMD_INIT_LOG(ERR, "SRIOV active,"
1874                                         " unsupported mq_mode rx %d.",
1875                                         dev_conf->rxmode.mq_mode);
1876                         return -EINVAL;
1877                 case ETH_MQ_RX_RSS:
1878                 case ETH_MQ_RX_VMDQ_RSS:
1879                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1880                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1881                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1882                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1883                                                 " invalid queue number"
1884                                                 " for VMDQ RSS, allowed"
1885                                                 " value are 1, 2 or 4.");
1886                                         return -EINVAL;
1887                                 }
1888                         break;
1889                 case ETH_MQ_RX_VMDQ_ONLY:
1890                 case ETH_MQ_RX_NONE:
1891                         /* if nothing mq mode configure, use default scheme */
1892                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1893                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1894                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1895                         break;
1896                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1897                         /* SRIOV only works in VMDq enable mode */
1898                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1899                                         " wrong mq_mode rx %d.",
1900                                         dev_conf->rxmode.mq_mode);
1901                         return -EINVAL;
1902                 }
1903
1904                 switch (dev_conf->txmode.mq_mode) {
1905                 case ETH_MQ_TX_VMDQ_DCB:
1906                         /* DCB VMDQ in SRIOV mode, not implement yet */
1907                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1908                                         " unsupported VMDQ mq_mode tx %d.",
1909                                         dev_conf->txmode.mq_mode);
1910                         return -EINVAL;
1911                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1912                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1913                         break;
1914                 }
1915
1916                 /* check valid queue number */
1917                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1918                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1919                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1920                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1921                                         " must be less than or equal to %d.",
1922                                         nb_rx_q, nb_tx_q,
1923                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1924                         return -EINVAL;
1925                 }
1926         } else {
1927                 /* check configuration for vmdb+dcb mode */
1928                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1929                         const struct rte_eth_vmdq_dcb_conf *conf;
1930
1931                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1932                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1933                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1934                                 return -EINVAL;
1935                         }
1936                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1937                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1938                                conf->nb_queue_pools == ETH_32_POOLS)) {
1939                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1940                                                 " nb_queue_pools must be %d or %d.",
1941                                                 ETH_16_POOLS, ETH_32_POOLS);
1942                                 return -EINVAL;
1943                         }
1944                 }
1945                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1946                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1947
1948                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1949                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1950                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1951                                 return -EINVAL;
1952                         }
1953                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1954                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1955                                conf->nb_queue_pools == ETH_32_POOLS)) {
1956                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1957                                                 " nb_queue_pools != %d and"
1958                                                 " nb_queue_pools != %d.",
1959                                                 ETH_16_POOLS, ETH_32_POOLS);
1960                                 return -EINVAL;
1961                         }
1962                 }
1963
1964                 /* For DCB mode check our configuration before we go further */
1965                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1966                         const struct rte_eth_dcb_rx_conf *conf;
1967
1968                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1969                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1970                                                  IXGBE_DCB_NB_QUEUES);
1971                                 return -EINVAL;
1972                         }
1973                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1974                         if (!(conf->nb_tcs == ETH_4_TCS ||
1975                                conf->nb_tcs == ETH_8_TCS)) {
1976                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1977                                                 " and nb_tcs != %d.",
1978                                                 ETH_4_TCS, ETH_8_TCS);
1979                                 return -EINVAL;
1980                         }
1981                 }
1982
1983                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1984                         const struct rte_eth_dcb_tx_conf *conf;
1985
1986                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1987                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1988                                                  IXGBE_DCB_NB_QUEUES);
1989                                 return -EINVAL;
1990                         }
1991                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1992                         if (!(conf->nb_tcs == ETH_4_TCS ||
1993                                conf->nb_tcs == ETH_8_TCS)) {
1994                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1995                                                 " and nb_tcs != %d.",
1996                                                 ETH_4_TCS, ETH_8_TCS);
1997                                 return -EINVAL;
1998                         }
1999                 }
2000         }
2001         return 0;
2002 }
2003
2004 static int
2005 ixgbe_dev_configure(struct rte_eth_dev *dev)
2006 {
2007         struct ixgbe_interrupt *intr =
2008                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2009         struct ixgbe_adapter *adapter =
2010                 (struct ixgbe_adapter *)dev->data->dev_private;
2011         int ret;
2012
2013         PMD_INIT_FUNC_TRACE();
2014         /* multipe queue mode checking */
2015         ret  = ixgbe_check_mq_mode(dev);
2016         if (ret != 0) {
2017                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2018                             ret);
2019                 return ret;
2020         }
2021
2022         /* set flag to update link status after init */
2023         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2024
2025         /*
2026          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2027          * allocation or vector Rx preconditions we will reset it.
2028          */
2029         adapter->rx_bulk_alloc_allowed = true;
2030         adapter->rx_vec_allowed = true;
2031
2032         return 0;
2033 }
2034
2035 static void
2036 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2037 {
2038         struct ixgbe_hw *hw =
2039                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2040         struct ixgbe_interrupt *intr =
2041                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2042         uint32_t gpie;
2043
2044         /* only set up it on X550EM_X */
2045         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2046                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2047                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2048                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2049                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2050                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2051         }
2052 }
2053
2054 /*
2055  * Configure device link speed and setup link.
2056  * It returns 0 on success.
2057  */
2058 static int
2059 ixgbe_dev_start(struct rte_eth_dev *dev)
2060 {
2061         struct ixgbe_hw *hw =
2062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063         struct ixgbe_vf_info *vfinfo =
2064                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2065         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2066         uint32_t intr_vector = 0;
2067         int err, link_up = 0, negotiate = 0;
2068         uint32_t speed = 0;
2069         int mask = 0;
2070         int status;
2071         uint16_t vf, idx;
2072
2073         PMD_INIT_FUNC_TRACE();
2074
2075         /* IXGBE devices don't support half duplex */
2076         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2077                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2078                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2079                              dev->data->dev_conf.link_duplex,
2080                              dev->data->port_id);
2081                 return -EINVAL;
2082         }
2083
2084         /* disable uio/vfio intr/eventfd mapping */
2085         rte_intr_disable(intr_handle);
2086
2087         /* stop adapter */
2088         hw->adapter_stopped = 0;
2089         ixgbe_stop_adapter(hw);
2090
2091         /* reinitialize adapter
2092          * this calls reset and start */
2093         status = ixgbe_pf_reset_hw(hw);
2094         if (status != 0)
2095                 return -1;
2096         hw->mac.ops.start_hw(hw);
2097         hw->mac.get_link_status = true;
2098
2099         /* configure PF module if SRIOV enabled */
2100         ixgbe_pf_host_configure(dev);
2101
2102         ixgbe_dev_phy_intr_setup(dev);
2103
2104         /* check and configure queue intr-vector mapping */
2105         if ((rte_intr_cap_multiple(intr_handle) ||
2106              !RTE_ETH_DEV_SRIOV(dev).active) &&
2107             dev->data->dev_conf.intr_conf.rxq != 0) {
2108                 intr_vector = dev->data->nb_rx_queues;
2109                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2110                         return -1;
2111         }
2112
2113         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2114                 intr_handle->intr_vec =
2115                         rte_zmalloc("intr_vec",
2116                                     dev->data->nb_rx_queues * sizeof(int), 0);
2117                 if (intr_handle->intr_vec == NULL) {
2118                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2119                                      " intr_vec\n", dev->data->nb_rx_queues);
2120                         return -ENOMEM;
2121                 }
2122         }
2123
2124         /* confiugre msix for sleep until rx interrupt */
2125         ixgbe_configure_msix(dev);
2126
2127         /* initialize transmission unit */
2128         ixgbe_dev_tx_init(dev);
2129
2130         /* This can fail when allocating mbufs for descriptor rings */
2131         err = ixgbe_dev_rx_init(dev);
2132         if (err) {
2133                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2134                 goto error;
2135         }
2136
2137         err = ixgbe_dev_rxtx_start(dev);
2138         if (err < 0) {
2139                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2140                 goto error;
2141         }
2142
2143         /* Skip link setup if loopback mode is enabled for 82599. */
2144         if (hw->mac.type == ixgbe_mac_82599EB &&
2145                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2146                 goto skip_link_setup;
2147
2148         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2149                 err = hw->mac.ops.setup_sfp(hw);
2150                 if (err)
2151                         goto error;
2152         }
2153
2154         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2155                 /* Turn on the copper */
2156                 ixgbe_set_phy_power(hw, true);
2157         } else {
2158                 /* Turn on the laser */
2159                 ixgbe_enable_tx_laser(hw);
2160         }
2161
2162         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2163         if (err)
2164                 goto error;
2165         dev->data->dev_link.link_status = link_up;
2166
2167         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2168         if (err)
2169                 goto error;
2170
2171         switch(dev->data->dev_conf.link_speed) {
2172         case ETH_LINK_SPEED_AUTONEG:
2173                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2174                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2175                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2176                 break;
2177         case ETH_LINK_SPEED_100:
2178                 /*
2179                  * Invalid for 82598 but error will be detected by
2180                  * ixgbe_setup_link()
2181                  */
2182                 speed = IXGBE_LINK_SPEED_100_FULL;
2183                 break;
2184         case ETH_LINK_SPEED_1000:
2185                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2186                 break;
2187         case ETH_LINK_SPEED_10000:
2188                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2189                 break;
2190         default:
2191                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2192                              dev->data->dev_conf.link_speed,
2193                              dev->data->port_id);
2194                 goto error;
2195         }
2196
2197         err = ixgbe_setup_link(hw, speed, link_up);
2198         if (err)
2199                 goto error;
2200
2201 skip_link_setup:
2202
2203         if (rte_intr_allow_others(intr_handle)) {
2204                 /* check if lsc interrupt is enabled */
2205                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2206                         ixgbe_dev_lsc_interrupt_setup(dev);
2207         } else {
2208                 rte_intr_callback_unregister(intr_handle,
2209                                              ixgbe_dev_interrupt_handler,
2210                                              (void *)dev);
2211                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2212                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2213                                      " no intr multiplex\n");
2214         }
2215
2216         /* check if rxq interrupt is enabled */
2217         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2218             rte_intr_dp_is_en(intr_handle))
2219                 ixgbe_dev_rxq_interrupt_setup(dev);
2220
2221         /* enable uio/vfio intr/eventfd mapping */
2222         rte_intr_enable(intr_handle);
2223
2224         /* resume enabled intr since hw reset */
2225         ixgbe_enable_intr(dev);
2226
2227         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2228                 ETH_VLAN_EXTEND_MASK;
2229         ixgbe_vlan_offload_set(dev, mask);
2230
2231         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2232                 /* Enable vlan filtering for VMDq */
2233                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2234         }
2235
2236         /* Configure DCB hw */
2237         ixgbe_configure_dcb(dev);
2238
2239         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2240                 err = ixgbe_fdir_configure(dev);
2241                 if (err)
2242                         goto error;
2243         }
2244
2245         /* Restore vf rate limit */
2246         if (vfinfo != NULL) {
2247                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2248                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2249                                 if (vfinfo[vf].tx_rate[idx] != 0)
2250                                         ixgbe_set_vf_rate_limit(dev, vf,
2251                                                 vfinfo[vf].tx_rate[idx],
2252                                                 1 << idx);
2253         }
2254
2255         ixgbe_restore_statistics_mapping(dev);
2256
2257         return 0;
2258
2259 error:
2260         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2261         ixgbe_dev_clear_queues(dev);
2262         return -EIO;
2263 }
2264
2265 /*
2266  * Stop device: disable rx and tx functions to allow for reconfiguring.
2267  */
2268 static void
2269 ixgbe_dev_stop(struct rte_eth_dev *dev)
2270 {
2271         struct rte_eth_link link;
2272         struct ixgbe_hw *hw =
2273                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2274         struct ixgbe_vf_info *vfinfo =
2275                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2276         struct ixgbe_filter_info *filter_info =
2277                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2278         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2279         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2280         int vf;
2281
2282         PMD_INIT_FUNC_TRACE();
2283
2284         /* disable interrupts */
2285         ixgbe_disable_intr(hw);
2286
2287         /* reset the NIC */
2288         ixgbe_pf_reset_hw(hw);
2289         hw->adapter_stopped = 0;
2290
2291         /* stop adapter */
2292         ixgbe_stop_adapter(hw);
2293
2294         for (vf = 0; vfinfo != NULL &&
2295                      vf < dev->pci_dev->max_vfs; vf++)
2296                 vfinfo[vf].clear_to_send = false;
2297
2298         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2299                 /* Turn off the copper */
2300                 ixgbe_set_phy_power(hw, false);
2301         } else {
2302                 /* Turn off the laser */
2303                 ixgbe_disable_tx_laser(hw);
2304         }
2305
2306         ixgbe_dev_clear_queues(dev);
2307
2308         /* Clear stored conf */
2309         dev->data->scattered_rx = 0;
2310         dev->data->lro = 0;
2311
2312         /* Clear recorded link status */
2313         memset(&link, 0, sizeof(link));
2314         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2315
2316         /* Remove all ntuple filters of the device */
2317         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2318              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2319                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2320                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2321                              p_5tuple, entries);
2322                 rte_free(p_5tuple);
2323         }
2324         memset(filter_info->fivetuple_mask, 0,
2325                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2326
2327         if (!rte_intr_allow_others(intr_handle))
2328                 /* resume to the default handler */
2329                 rte_intr_callback_register(intr_handle,
2330                                            ixgbe_dev_interrupt_handler,
2331                                            (void *)dev);
2332
2333         /* Clean datapath event and queue/vec mapping */
2334         rte_intr_efd_disable(intr_handle);
2335         if (intr_handle->intr_vec != NULL) {
2336                 rte_free(intr_handle->intr_vec);
2337                 intr_handle->intr_vec = NULL;
2338         }
2339 }
2340
2341 /*
2342  * Set device link up: enable tx.
2343  */
2344 static int
2345 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2346 {
2347         struct ixgbe_hw *hw =
2348                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2349         if (hw->mac.type == ixgbe_mac_82599EB) {
2350 #ifdef RTE_NIC_BYPASS
2351                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2352                         /* Not suported in bypass mode */
2353                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2354                                      "by device id 0x%x", hw->device_id);
2355                         return -ENOTSUP;
2356                 }
2357 #endif
2358         }
2359
2360         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2361                 /* Turn on the copper */
2362                 ixgbe_set_phy_power(hw, true);
2363         } else {
2364                 /* Turn on the laser */
2365                 ixgbe_enable_tx_laser(hw);
2366         }
2367
2368         return 0;
2369 }
2370
2371 /*
2372  * Set device link down: disable tx.
2373  */
2374 static int
2375 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2376 {
2377         struct ixgbe_hw *hw =
2378                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379         if (hw->mac.type == ixgbe_mac_82599EB) {
2380 #ifdef RTE_NIC_BYPASS
2381                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2382                         /* Not suported in bypass mode */
2383                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2384                                      "by device id 0x%x", hw->device_id);
2385                         return -ENOTSUP;
2386                 }
2387 #endif
2388         }
2389
2390         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2391                 /* Turn off the copper */
2392                 ixgbe_set_phy_power(hw, false);
2393         } else {
2394                 /* Turn off the laser */
2395                 ixgbe_disable_tx_laser(hw);
2396         }
2397
2398         return 0;
2399 }
2400
2401 /*
2402  * Reest and stop device.
2403  */
2404 static void
2405 ixgbe_dev_close(struct rte_eth_dev *dev)
2406 {
2407         struct ixgbe_hw *hw =
2408                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409
2410         PMD_INIT_FUNC_TRACE();
2411
2412         ixgbe_pf_reset_hw(hw);
2413
2414         ixgbe_dev_stop(dev);
2415         hw->adapter_stopped = 1;
2416
2417         ixgbe_dev_free_queues(dev);
2418
2419         ixgbe_disable_pcie_master(hw);
2420
2421         /* reprogram the RAR[0] in case user changed it. */
2422         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2423 }
2424
2425 static void
2426 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2427                            struct ixgbe_hw_stats *hw_stats,
2428                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2429                            uint64_t *total_qprc, uint64_t *total_qprdc)
2430 {
2431         uint32_t bprc, lxon, lxoff, total;
2432         uint32_t delta_gprc = 0;
2433         unsigned i;
2434         /* Workaround for RX byte count not including CRC bytes when CRC
2435 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2436          * is disabled.
2437 +        */
2438         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2439                         IXGBE_HLREG0_RXCRCSTRP);
2440
2441         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2442         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2443         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2444         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2445
2446         for (i = 0; i < 8; i++) {
2447                 uint32_t mp;
2448                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2449                 /* global total per queue */
2450                 hw_stats->mpc[i] += mp;
2451                 /* Running comprehensive total for stats display */
2452                 *total_missed_rx += hw_stats->mpc[i];
2453                 if (hw->mac.type == ixgbe_mac_82598EB) {
2454                         hw_stats->rnbc[i] +=
2455                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2456                         hw_stats->pxonrxc[i] +=
2457                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2458                         hw_stats->pxoffrxc[i] +=
2459                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2460                 } else {
2461                         hw_stats->pxonrxc[i] +=
2462                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2463                         hw_stats->pxoffrxc[i] +=
2464                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2465                         hw_stats->pxon2offc[i] +=
2466                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2467                 }
2468                 hw_stats->pxontxc[i] +=
2469                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2470                 hw_stats->pxofftxc[i] +=
2471                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2472         }
2473         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2474                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2475                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2476                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2477
2478                 delta_gprc += delta_qprc;
2479
2480                 hw_stats->qprc[i] += delta_qprc;
2481                 hw_stats->qptc[i] += delta_qptc;
2482
2483                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2484                 hw_stats->qbrc[i] +=
2485                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2486                 if (crc_strip == 0)
2487                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2488
2489                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2490                 hw_stats->qbtc[i] +=
2491                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2492
2493                 hw_stats->qprdc[i] += delta_qprdc;
2494                 *total_qprdc += hw_stats->qprdc[i];
2495
2496                 *total_qprc += hw_stats->qprc[i];
2497                 *total_qbrc += hw_stats->qbrc[i];
2498         }
2499         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2500         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2501         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2502
2503         /*
2504          * An errata states that gprc actually counts good + missed packets:
2505          * Workaround to set gprc to summated queue packet receives
2506          */
2507         hw_stats->gprc = *total_qprc;
2508
2509         if (hw->mac.type != ixgbe_mac_82598EB) {
2510                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2511                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2512                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2513                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2514                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2515                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2516                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2517                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2518         } else {
2519                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2520                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2521                 /* 82598 only has a counter in the high register */
2522                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2523                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2524                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2525         }
2526         uint64_t old_tpr = hw_stats->tpr;
2527
2528         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2529         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2530
2531         if (crc_strip == 0)
2532                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2533
2534         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2535         hw_stats->gptc += delta_gptc;
2536         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2537         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2538
2539         /*
2540          * Workaround: mprc hardware is incorrectly counting
2541          * broadcasts, so for now we subtract those.
2542          */
2543         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2544         hw_stats->bprc += bprc;
2545         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2546         if (hw->mac.type == ixgbe_mac_82598EB)
2547                 hw_stats->mprc -= bprc;
2548
2549         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2550         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2551         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2552         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2553         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2554         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2555
2556         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2557         hw_stats->lxontxc += lxon;
2558         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2559         hw_stats->lxofftxc += lxoff;
2560         total = lxon + lxoff;
2561
2562         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2563         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2564         hw_stats->gptc -= total;
2565         hw_stats->mptc -= total;
2566         hw_stats->ptc64 -= total;
2567         hw_stats->gotc -= total * ETHER_MIN_LEN;
2568
2569         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2570         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2571         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2572         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2573         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2574         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2575         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2576         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2577         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2578         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2579         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2580         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2581         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2582         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2583         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2584         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2585         /* Only read FCOE on 82599 */
2586         if (hw->mac.type != ixgbe_mac_82598EB) {
2587                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2588                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2589                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2590                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2591                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2592         }
2593
2594         /* Flow Director Stats registers */
2595         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2596         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2597 }
2598
2599 /*
2600  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2601  */
2602 static void
2603 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2604 {
2605         struct ixgbe_hw *hw =
2606                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2607         struct ixgbe_hw_stats *hw_stats =
2608                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2609         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2610         unsigned i;
2611
2612         total_missed_rx = 0;
2613         total_qbrc = 0;
2614         total_qprc = 0;
2615         total_qprdc = 0;
2616
2617         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2618                         &total_qprc, &total_qprdc);
2619
2620         if (stats == NULL)
2621                 return;
2622
2623         /* Fill out the rte_eth_stats statistics structure */
2624         stats->ipackets = total_qprc;
2625         stats->ibytes = total_qbrc;
2626         stats->opackets = hw_stats->gptc;
2627         stats->obytes = hw_stats->gotc;
2628
2629         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2630                 stats->q_ipackets[i] = hw_stats->qprc[i];
2631                 stats->q_opackets[i] = hw_stats->qptc[i];
2632                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2633                 stats->q_obytes[i] = hw_stats->qbtc[i];
2634                 stats->q_errors[i] = hw_stats->qprdc[i];
2635         }
2636
2637         /* Rx Errors */
2638         stats->imissed  = total_missed_rx;
2639         stats->ierrors  = hw_stats->crcerrs +
2640                           hw_stats->mspdc +
2641                           hw_stats->rlec +
2642                           hw_stats->ruc +
2643                           hw_stats->roc +
2644                           total_missed_rx +
2645                           hw_stats->illerrc +
2646                           hw_stats->errbc +
2647                           hw_stats->rfc +
2648                           hw_stats->fccrc +
2649                           hw_stats->fclast;
2650
2651         /* Tx Errors */
2652         stats->oerrors  = 0;
2653 }
2654
2655 static void
2656 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2657 {
2658         struct ixgbe_hw_stats *stats =
2659                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2660
2661         /* HW registers are cleared on read */
2662         ixgbe_dev_stats_get(dev, NULL);
2663
2664         /* Reset software totals */
2665         memset(stats, 0, sizeof(*stats));
2666 }
2667
2668 /* This function calculates the number of xstats based on the current config */
2669 static unsigned
2670 ixgbe_xstats_calc_num(void) {
2671         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2672                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2673 }
2674
2675 static int
2676 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2677                                          unsigned n)
2678 {
2679         struct ixgbe_hw *hw =
2680                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681         struct ixgbe_hw_stats *hw_stats =
2682                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2683         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2684         unsigned i, stat, count = 0;
2685
2686         count = ixgbe_xstats_calc_num();
2687
2688         if (n < count)
2689                 return count;
2690
2691         total_missed_rx = 0;
2692         total_qbrc = 0;
2693         total_qprc = 0;
2694         total_qprdc = 0;
2695
2696         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2697                                    &total_qprc, &total_qprdc);
2698
2699         /* If this is a reset xstats is NULL, and we have cleared the
2700          * registers by reading them.
2701          */
2702         if (!xstats)
2703                 return 0;
2704
2705         /* Extended stats from ixgbe_hw_stats */
2706         count = 0;
2707         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2708                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2709                          rte_ixgbe_stats_strings[i].name);
2710                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2711                                 rte_ixgbe_stats_strings[i].offset);
2712                 count++;
2713         }
2714
2715         /* RX Priority Stats */
2716         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2717                 for (i = 0; i < 8; i++) {
2718                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2719                                  "rx_priority%u_%s", i,
2720                                  rte_ixgbe_rxq_strings[stat].name);
2721                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2722                                         rte_ixgbe_rxq_strings[stat].offset +
2723                                         (sizeof(uint64_t) * i));
2724                         count++;
2725                 }
2726         }
2727
2728         /* TX Priority Stats */
2729         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2730                 for (i = 0; i < 8; i++) {
2731                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2732                                  "tx_priority%u_%s", i,
2733                                  rte_ixgbe_txq_strings[stat].name);
2734                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2735                                         rte_ixgbe_txq_strings[stat].offset +
2736                                         (sizeof(uint64_t) * i));
2737                         count++;
2738                 }
2739         }
2740
2741         return count;
2742 }
2743
2744 static void
2745 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2746 {
2747         struct ixgbe_hw_stats *stats =
2748                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2749
2750         unsigned count = ixgbe_xstats_calc_num();
2751
2752         /* HW registers are cleared on read */
2753         ixgbe_dev_xstats_get(dev, NULL, count);
2754
2755         /* Reset software totals */
2756         memset(stats, 0, sizeof(*stats));
2757 }
2758
2759 static void
2760 ixgbevf_update_stats(struct rte_eth_dev *dev)
2761 {
2762         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2763         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2764                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2765
2766         /* Good Rx packet, include VF loopback */
2767         UPDATE_VF_STAT(IXGBE_VFGPRC,
2768             hw_stats->last_vfgprc, hw_stats->vfgprc);
2769
2770         /* Good Rx octets, include VF loopback */
2771         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2772             hw_stats->last_vfgorc, hw_stats->vfgorc);
2773
2774         /* Good Tx packet, include VF loopback */
2775         UPDATE_VF_STAT(IXGBE_VFGPTC,
2776             hw_stats->last_vfgptc, hw_stats->vfgptc);
2777
2778         /* Good Tx octets, include VF loopback */
2779         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2780             hw_stats->last_vfgotc, hw_stats->vfgotc);
2781
2782         /* Rx Multicst Packet */
2783         UPDATE_VF_STAT(IXGBE_VFMPRC,
2784             hw_stats->last_vfmprc, hw_stats->vfmprc);
2785 }
2786
2787 static int
2788 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2789                        unsigned n)
2790 {
2791         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2792                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2793         unsigned i;
2794
2795         if (n < IXGBEVF_NB_XSTATS)
2796                 return IXGBEVF_NB_XSTATS;
2797
2798         ixgbevf_update_stats(dev);
2799
2800         if (!xstats)
2801                 return 0;
2802
2803         /* Extended stats */
2804         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2805                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2806                          "%s", rte_ixgbevf_stats_strings[i].name);
2807                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2808                         rte_ixgbevf_stats_strings[i].offset);
2809         }
2810
2811         return IXGBEVF_NB_XSTATS;
2812 }
2813
2814 static void
2815 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2816 {
2817         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2818                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2819
2820         ixgbevf_update_stats(dev);
2821
2822         if (stats == NULL)
2823                 return;
2824
2825         stats->ipackets = hw_stats->vfgprc;
2826         stats->ibytes = hw_stats->vfgorc;
2827         stats->opackets = hw_stats->vfgptc;
2828         stats->obytes = hw_stats->vfgotc;
2829         stats->imcasts = hw_stats->vfmprc;
2830         /* stats->imcasts should be removed as imcasts is deprecated */
2831 }
2832
2833 static void
2834 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2835 {
2836         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2837                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2838
2839         /* Sync HW register to the last stats */
2840         ixgbevf_dev_stats_get(dev, NULL);
2841
2842         /* reset HW current stats*/
2843         hw_stats->vfgprc = 0;
2844         hw_stats->vfgorc = 0;
2845         hw_stats->vfgptc = 0;
2846         hw_stats->vfgotc = 0;
2847         hw_stats->vfmprc = 0;
2848
2849 }
2850
2851 static void
2852 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2853 {
2854         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855
2856         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2857         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2858         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2859         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2860         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2861         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2862         dev_info->max_vfs = dev->pci_dev->max_vfs;
2863         if (hw->mac.type == ixgbe_mac_82598EB)
2864                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2865         else
2866                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2867         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2868         dev_info->rx_offload_capa =
2869                 DEV_RX_OFFLOAD_VLAN_STRIP |
2870                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2871                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2872                 DEV_RX_OFFLOAD_TCP_CKSUM;
2873
2874         /*
2875          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2876          * mode.
2877          */
2878         if ((hw->mac.type == ixgbe_mac_82599EB ||
2879              hw->mac.type == ixgbe_mac_X540) &&
2880             !RTE_ETH_DEV_SRIOV(dev).active)
2881                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2882
2883         if (hw->mac.type == ixgbe_mac_X550 ||
2884             hw->mac.type == ixgbe_mac_X550EM_x)
2885                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2886
2887         dev_info->tx_offload_capa =
2888                 DEV_TX_OFFLOAD_VLAN_INSERT |
2889                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2890                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2891                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2892                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2893                 DEV_TX_OFFLOAD_TCP_TSO;
2894
2895         if (hw->mac.type == ixgbe_mac_X550 ||
2896             hw->mac.type == ixgbe_mac_X550EM_x)
2897                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2898
2899         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2900                 .rx_thresh = {
2901                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2902                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2903                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2904                 },
2905                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2906                 .rx_drop_en = 0,
2907         };
2908
2909         dev_info->default_txconf = (struct rte_eth_txconf) {
2910                 .tx_thresh = {
2911                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2912                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2913                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2914                 },
2915                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2916                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2917                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2918                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2919         };
2920
2921         dev_info->rx_desc_lim = rx_desc_lim;
2922         dev_info->tx_desc_lim = tx_desc_lim;
2923
2924         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2925         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2926         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2927 }
2928
2929 static void
2930 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2931                      struct rte_eth_dev_info *dev_info)
2932 {
2933         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2934
2935         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2936         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2937         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2938         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2939         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2940         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2941         dev_info->max_vfs = dev->pci_dev->max_vfs;
2942         if (hw->mac.type == ixgbe_mac_82598EB)
2943                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2944         else
2945                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2946         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2947                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2948                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2949                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2950         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2951                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2952                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2953                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2954                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2955                                 DEV_TX_OFFLOAD_TCP_TSO;
2956
2957         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2958                 .rx_thresh = {
2959                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2960                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2961                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2962                 },
2963                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2964                 .rx_drop_en = 0,
2965         };
2966
2967         dev_info->default_txconf = (struct rte_eth_txconf) {
2968                 .tx_thresh = {
2969                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2970                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2971                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2972                 },
2973                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2974                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2975                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2976                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2977         };
2978
2979         dev_info->rx_desc_lim = rx_desc_lim;
2980         dev_info->tx_desc_lim = tx_desc_lim;
2981 }
2982
2983 /* return 0 means link status changed, -1 means not changed */
2984 static int
2985 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2986 {
2987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2988         struct rte_eth_link link, old;
2989         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2990         int link_up;
2991         int diag;
2992
2993         link.link_status = 0;
2994         link.link_speed = 0;
2995         link.link_duplex = 0;
2996         memset(&old, 0, sizeof(old));
2997         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2998
2999         hw->mac.get_link_status = true;
3000
3001         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3002         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3003                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3004         else
3005                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3006
3007         if (diag != 0) {
3008                 link.link_speed = ETH_LINK_SPEED_100;
3009                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3010                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3011                 if (link.link_status == old.link_status)
3012                         return -1;
3013                 return 0;
3014         }
3015
3016         if (link_up == 0) {
3017                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3018                 if (link.link_status == old.link_status)
3019                         return -1;
3020                 return 0;
3021         }
3022         link.link_status = 1;
3023         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3024
3025         switch (link_speed) {
3026         default:
3027         case IXGBE_LINK_SPEED_UNKNOWN:
3028                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3029                 link.link_speed = ETH_LINK_SPEED_100;
3030                 break;
3031
3032         case IXGBE_LINK_SPEED_100_FULL:
3033                 link.link_speed = ETH_LINK_SPEED_100;
3034                 break;
3035
3036         case IXGBE_LINK_SPEED_1GB_FULL:
3037                 link.link_speed = ETH_LINK_SPEED_1000;
3038                 break;
3039
3040         case IXGBE_LINK_SPEED_10GB_FULL:
3041                 link.link_speed = ETH_LINK_SPEED_10000;
3042                 break;
3043         }
3044         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3045
3046         if (link.link_status == old.link_status)
3047                 return -1;
3048
3049         return 0;
3050 }
3051
3052 static void
3053 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3054 {
3055         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3056         uint32_t fctrl;
3057
3058         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3059         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3060         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3061 }
3062
3063 static void
3064 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3065 {
3066         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067         uint32_t fctrl;
3068
3069         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3070         fctrl &= (~IXGBE_FCTRL_UPE);
3071         if (dev->data->all_multicast == 1)
3072                 fctrl |= IXGBE_FCTRL_MPE;
3073         else
3074                 fctrl &= (~IXGBE_FCTRL_MPE);
3075         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3076 }
3077
3078 static void
3079 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3080 {
3081         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3082         uint32_t fctrl;
3083
3084         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3085         fctrl |= IXGBE_FCTRL_MPE;
3086         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3087 }
3088
3089 static void
3090 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3091 {
3092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3093         uint32_t fctrl;
3094
3095         if (dev->data->promiscuous == 1)
3096                 return; /* must remain in all_multicast mode */
3097
3098         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3099         fctrl &= (~IXGBE_FCTRL_MPE);
3100         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3101 }
3102
3103 /**
3104  * It clears the interrupt causes and enables the interrupt.
3105  * It will be called once only during nic initialized.
3106  *
3107  * @param dev
3108  *  Pointer to struct rte_eth_dev.
3109  *
3110  * @return
3111  *  - On success, zero.
3112  *  - On failure, a negative value.
3113  */
3114 static int
3115 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3116 {
3117         struct ixgbe_interrupt *intr =
3118                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3119
3120         ixgbe_dev_link_status_print(dev);
3121         intr->mask |= IXGBE_EICR_LSC;
3122
3123         return 0;
3124 }
3125
3126 /**
3127  * It clears the interrupt causes and enables the interrupt.
3128  * It will be called once only during nic initialized.
3129  *
3130  * @param dev
3131  *  Pointer to struct rte_eth_dev.
3132  *
3133  * @return
3134  *  - On success, zero.
3135  *  - On failure, a negative value.
3136  */
3137 static int
3138 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3139 {
3140         struct ixgbe_interrupt *intr =
3141                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3142
3143         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3144
3145         return 0;
3146 }
3147
3148 /*
3149  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3150  *
3151  * @param dev
3152  *  Pointer to struct rte_eth_dev.
3153  *
3154  * @return
3155  *  - On success, zero.
3156  *  - On failure, a negative value.
3157  */
3158 static int
3159 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3160 {
3161         uint32_t eicr;
3162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3163         struct ixgbe_interrupt *intr =
3164                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3165
3166         /* clear all cause mask */
3167         ixgbe_disable_intr(hw);
3168
3169         /* read-on-clear nic registers here */
3170         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3171         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3172
3173         intr->flags = 0;
3174
3175         /* set flag for async link update */
3176         if (eicr & IXGBE_EICR_LSC)
3177                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3178
3179         if (eicr & IXGBE_EICR_MAILBOX)
3180                 intr->flags |= IXGBE_FLAG_MAILBOX;
3181
3182         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3183             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3184             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3185                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3186
3187         return 0;
3188 }
3189
3190 /**
3191  * It gets and then prints the link status.
3192  *
3193  * @param dev
3194  *  Pointer to struct rte_eth_dev.
3195  *
3196  * @return
3197  *  - On success, zero.
3198  *  - On failure, a negative value.
3199  */
3200 static void
3201 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3202 {
3203         struct rte_eth_link link;
3204
3205         memset(&link, 0, sizeof(link));
3206         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3207         if (link.link_status) {
3208                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3209                                         (int)(dev->data->port_id),
3210                                         (unsigned)link.link_speed,
3211                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3212                                         "full-duplex" : "half-duplex");
3213         } else {
3214                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3215                                 (int)(dev->data->port_id));
3216         }
3217         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3218                                 dev->pci_dev->addr.domain,
3219                                 dev->pci_dev->addr.bus,
3220                                 dev->pci_dev->addr.devid,
3221                                 dev->pci_dev->addr.function);
3222 }
3223
3224 /*
3225  * It executes link_update after knowing an interrupt occurred.
3226  *
3227  * @param dev
3228  *  Pointer to struct rte_eth_dev.
3229  *
3230  * @return
3231  *  - On success, zero.
3232  *  - On failure, a negative value.
3233  */
3234 static int
3235 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3236 {
3237         struct ixgbe_interrupt *intr =
3238                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3239         int64_t timeout;
3240         struct rte_eth_link link;
3241         int intr_enable_delay = false;
3242         struct ixgbe_hw *hw =
3243                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3244
3245         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3246
3247         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3248                 ixgbe_pf_mbx_process(dev);
3249                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3250         }
3251
3252         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3253                 ixgbe_handle_lasi(hw);
3254                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3255         }
3256
3257         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3258                 /* get the link status before link update, for predicting later */
3259                 memset(&link, 0, sizeof(link));
3260                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3261
3262                 ixgbe_dev_link_update(dev, 0);
3263
3264                 /* likely to up */
3265                 if (!link.link_status)
3266                         /* handle it 1 sec later, wait it being stable */
3267                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3268                 /* likely to down */
3269                 else
3270                         /* handle it 4 sec later, wait it being stable */
3271                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3272
3273                 ixgbe_dev_link_status_print(dev);
3274
3275                 intr_enable_delay = true;
3276         }
3277
3278         if (intr_enable_delay) {
3279                 if (rte_eal_alarm_set(timeout * 1000,
3280                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3281                         PMD_DRV_LOG(ERR, "Error setting alarm");
3282         } else {
3283                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3284                 ixgbe_enable_intr(dev);
3285                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3286         }
3287
3288
3289         return 0;
3290 }
3291
3292 /**
3293  * Interrupt handler which shall be registered for alarm callback for delayed
3294  * handling specific interrupt to wait for the stable nic state. As the
3295  * NIC interrupt state is not stable for ixgbe after link is just down,
3296  * it needs to wait 4 seconds to get the stable status.
3297  *
3298  * @param handle
3299  *  Pointer to interrupt handle.
3300  * @param param
3301  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3302  *
3303  * @return
3304  *  void
3305  */
3306 static void
3307 ixgbe_dev_interrupt_delayed_handler(void *param)
3308 {
3309         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3310         struct ixgbe_interrupt *intr =
3311                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3312         struct ixgbe_hw *hw =
3313                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3314         uint32_t eicr;
3315
3316         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3317         if (eicr & IXGBE_EICR_MAILBOX)
3318                 ixgbe_pf_mbx_process(dev);
3319
3320         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3321                 ixgbe_handle_lasi(hw);
3322                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3323         }
3324
3325         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3326                 ixgbe_dev_link_update(dev, 0);
3327                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3328                 ixgbe_dev_link_status_print(dev);
3329                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3330         }
3331
3332         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3333         ixgbe_enable_intr(dev);
3334         rte_intr_enable(&(dev->pci_dev->intr_handle));
3335 }
3336
3337 /**
3338  * Interrupt handler triggered by NIC  for handling
3339  * specific interrupt.
3340  *
3341  * @param handle
3342  *  Pointer to interrupt handle.
3343  * @param param
3344  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3345  *
3346  * @return
3347  *  void
3348  */
3349 static void
3350 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3351                             void *param)
3352 {
3353         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3354
3355         ixgbe_dev_interrupt_get_status(dev);
3356         ixgbe_dev_interrupt_action(dev);
3357 }
3358
3359 static int
3360 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3361 {
3362         struct ixgbe_hw *hw;
3363
3364         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3365         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3366 }
3367
3368 static int
3369 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3370 {
3371         struct ixgbe_hw *hw;
3372
3373         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3375 }
3376
3377 static int
3378 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3379 {
3380         struct ixgbe_hw *hw;
3381         uint32_t mflcn_reg;
3382         uint32_t fccfg_reg;
3383         int rx_pause;
3384         int tx_pause;
3385
3386         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3387
3388         fc_conf->pause_time = hw->fc.pause_time;
3389         fc_conf->high_water = hw->fc.high_water[0];
3390         fc_conf->low_water = hw->fc.low_water[0];
3391         fc_conf->send_xon = hw->fc.send_xon;
3392         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3393
3394         /*
3395          * Return rx_pause status according to actual setting of
3396          * MFLCN register.
3397          */
3398         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3399         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3400                 rx_pause = 1;
3401         else
3402                 rx_pause = 0;
3403
3404         /*
3405          * Return tx_pause status according to actual setting of
3406          * FCCFG register.
3407          */
3408         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3409         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3410                 tx_pause = 1;
3411         else
3412                 tx_pause = 0;
3413
3414         if (rx_pause && tx_pause)
3415                 fc_conf->mode = RTE_FC_FULL;
3416         else if (rx_pause)
3417                 fc_conf->mode = RTE_FC_RX_PAUSE;
3418         else if (tx_pause)
3419                 fc_conf->mode = RTE_FC_TX_PAUSE;
3420         else
3421                 fc_conf->mode = RTE_FC_NONE;
3422
3423         return 0;
3424 }
3425
3426 static int
3427 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3428 {
3429         struct ixgbe_hw *hw;
3430         int err;
3431         uint32_t rx_buf_size;
3432         uint32_t max_high_water;
3433         uint32_t mflcn;
3434         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3435                 ixgbe_fc_none,
3436                 ixgbe_fc_rx_pause,
3437                 ixgbe_fc_tx_pause,
3438                 ixgbe_fc_full
3439         };
3440
3441         PMD_INIT_FUNC_TRACE();
3442
3443         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3445         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3446
3447         /*
3448          * At least reserve one Ethernet frame for watermark
3449          * high_water/low_water in kilo bytes for ixgbe
3450          */
3451         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3452         if ((fc_conf->high_water > max_high_water) ||
3453                 (fc_conf->high_water < fc_conf->low_water)) {
3454                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3455                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3456                 return -EINVAL;
3457         }
3458
3459         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3460         hw->fc.pause_time     = fc_conf->pause_time;
3461         hw->fc.high_water[0]  = fc_conf->high_water;
3462         hw->fc.low_water[0]   = fc_conf->low_water;
3463         hw->fc.send_xon       = fc_conf->send_xon;
3464         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3465
3466         err = ixgbe_fc_enable(hw);
3467
3468         /* Not negotiated is not an error case */
3469         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3470
3471                 /* check if we want to forward MAC frames - driver doesn't have native
3472                  * capability to do that, so we'll write the registers ourselves */
3473
3474                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3475
3476                 /* set or clear MFLCN.PMCF bit depending on configuration */
3477                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3478                         mflcn |= IXGBE_MFLCN_PMCF;
3479                 else
3480                         mflcn &= ~IXGBE_MFLCN_PMCF;
3481
3482                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3483                 IXGBE_WRITE_FLUSH(hw);
3484
3485                 return 0;
3486         }
3487
3488         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3489         return -EIO;
3490 }
3491
3492 /**
3493  *  ixgbe_pfc_enable_generic - Enable flow control
3494  *  @hw: pointer to hardware structure
3495  *  @tc_num: traffic class number
3496  *  Enable flow control according to the current settings.
3497  */
3498 static int
3499 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3500 {
3501         int ret_val = 0;
3502         uint32_t mflcn_reg, fccfg_reg;
3503         uint32_t reg;
3504         uint32_t fcrtl, fcrth;
3505         uint8_t i;
3506         uint8_t nb_rx_en;
3507
3508         /* Validate the water mark configuration */
3509         if (!hw->fc.pause_time) {
3510                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3511                 goto out;
3512         }
3513
3514         /* Low water mark of zero causes XOFF floods */
3515         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3516                  /* High/Low water can not be 0 */
3517                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3518                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3519                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3520                         goto out;
3521                 }
3522
3523                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3524                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3525                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3526                         goto out;
3527                 }
3528         }
3529         /* Negotiate the fc mode to use */
3530         ixgbe_fc_autoneg(hw);
3531
3532         /* Disable any previous flow control settings */
3533         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3534         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3535
3536         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3537         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3538
3539         switch (hw->fc.current_mode) {
3540         case ixgbe_fc_none:
3541                 /*
3542                  * If the count of enabled RX Priority Flow control >1,
3543                  * and the TX pause can not be disabled
3544                  */
3545                 nb_rx_en = 0;
3546                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3547                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3548                         if (reg & IXGBE_FCRTH_FCEN)
3549                                 nb_rx_en++;
3550                 }
3551                 if (nb_rx_en > 1)
3552                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3553                 break;
3554         case ixgbe_fc_rx_pause:
3555                 /*
3556                  * Rx Flow control is enabled and Tx Flow control is
3557                  * disabled by software override. Since there really
3558                  * isn't a way to advertise that we are capable of RX
3559                  * Pause ONLY, we will advertise that we support both
3560                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3561                  * disable the adapter's ability to send PAUSE frames.
3562                  */
3563                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3564                 /*
3565                  * If the count of enabled RX Priority Flow control >1,
3566                  * and the TX pause can not be disabled
3567                  */
3568                 nb_rx_en = 0;
3569                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3570                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3571                         if (reg & IXGBE_FCRTH_FCEN)
3572                                 nb_rx_en++;
3573                 }
3574                 if (nb_rx_en > 1)
3575                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3576                 break;
3577         case ixgbe_fc_tx_pause:
3578                 /*
3579                  * Tx Flow control is enabled, and Rx Flow control is
3580                  * disabled by software override.
3581                  */
3582                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3583                 break;
3584         case ixgbe_fc_full:
3585                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3586                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3587                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3588                 break;
3589         default:
3590                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3591                 ret_val = IXGBE_ERR_CONFIG;
3592                 goto out;
3593                 break;
3594         }
3595
3596         /* Set 802.3x based flow control settings. */
3597         mflcn_reg |= IXGBE_MFLCN_DPF;
3598         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3599         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3600
3601         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3602         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3603                 hw->fc.high_water[tc_num]) {
3604                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3605                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3606                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3607         } else {
3608                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3609                 /*
3610                  * In order to prevent Tx hangs when the internal Tx
3611                  * switch is enabled we must set the high water mark
3612                  * to the maximum FCRTH value.  This allows the Tx
3613                  * switch to function even under heavy Rx workloads.
3614                  */
3615                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3616         }
3617         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3618
3619         /* Configure pause time (2 TCs per register) */
3620         reg = hw->fc.pause_time * 0x00010001;
3621         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3622                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3623
3624         /* Configure flow control refresh threshold value */
3625         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3626
3627 out:
3628         return ret_val;
3629 }
3630
3631 static int
3632 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3633 {
3634         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3636
3637         if (hw->mac.type != ixgbe_mac_82598EB) {
3638                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3639         }
3640         return ret_val;
3641 }
3642
3643 static int
3644 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3645 {
3646         int err;
3647         uint32_t rx_buf_size;
3648         uint32_t max_high_water;
3649         uint8_t tc_num;
3650         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3651         struct ixgbe_hw *hw =
3652                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3653         struct ixgbe_dcb_config *dcb_config =
3654                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3655
3656         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3657                 ixgbe_fc_none,
3658                 ixgbe_fc_rx_pause,
3659                 ixgbe_fc_tx_pause,
3660                 ixgbe_fc_full
3661         };
3662
3663         PMD_INIT_FUNC_TRACE();
3664
3665         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3666         tc_num = map[pfc_conf->priority];
3667         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3668         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3669         /*
3670          * At least reserve one Ethernet frame for watermark
3671          * high_water/low_water in kilo bytes for ixgbe
3672          */
3673         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3674         if ((pfc_conf->fc.high_water > max_high_water) ||
3675             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3676                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3677                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3678                 return -EINVAL;
3679         }
3680
3681         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3682         hw->fc.pause_time = pfc_conf->fc.pause_time;
3683         hw->fc.send_xon = pfc_conf->fc.send_xon;
3684         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3685         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3686
3687         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3688
3689         /* Not negotiated is not an error case */
3690         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3691                 return 0;
3692
3693         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3694         return -EIO;
3695 }
3696
3697 static int
3698 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3699                           struct rte_eth_rss_reta_entry64 *reta_conf,
3700                           uint16_t reta_size)
3701 {
3702         uint8_t i, j, mask;
3703         uint32_t reta, r;
3704         uint16_t idx, shift;
3705         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3706         uint16_t sp_reta_size;
3707         uint32_t reta_reg;
3708
3709         PMD_INIT_FUNC_TRACE();
3710
3711         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3712                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3713                         "NIC.");
3714                 return -ENOTSUP;
3715         }
3716
3717         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3718         if (reta_size != sp_reta_size) {
3719                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3720                         "(%d) doesn't match the number hardware can supported "
3721                         "(%d)\n", reta_size, sp_reta_size);
3722                 return -EINVAL;
3723         }
3724
3725         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3726                 idx = i / RTE_RETA_GROUP_SIZE;
3727                 shift = i % RTE_RETA_GROUP_SIZE;
3728                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3729                                                 IXGBE_4_BIT_MASK);
3730                 if (!mask)
3731                         continue;
3732                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3733                 if (mask == IXGBE_4_BIT_MASK)
3734                         r = 0;
3735                 else
3736                         r = IXGBE_READ_REG(hw, reta_reg);
3737                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3738                         if (mask & (0x1 << j))
3739                                 reta |= reta_conf[idx].reta[shift + j] <<
3740                                                         (CHAR_BIT * j);
3741                         else
3742                                 reta |= r & (IXGBE_8_BIT_MASK <<
3743                                                 (CHAR_BIT * j));
3744                 }
3745                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3746         }
3747
3748         return 0;
3749 }
3750
3751 static int
3752 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3753                          struct rte_eth_rss_reta_entry64 *reta_conf,
3754                          uint16_t reta_size)
3755 {
3756         uint8_t i, j, mask;
3757         uint32_t reta;
3758         uint16_t idx, shift;
3759         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3760         uint16_t sp_reta_size;
3761         uint32_t reta_reg;
3762
3763         PMD_INIT_FUNC_TRACE();
3764         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3765         if (reta_size != sp_reta_size) {
3766                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3767                         "(%d) doesn't match the number hardware can supported "
3768                         "(%d)\n", reta_size, sp_reta_size);
3769                 return -EINVAL;
3770         }
3771
3772         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3773                 idx = i / RTE_RETA_GROUP_SIZE;
3774                 shift = i % RTE_RETA_GROUP_SIZE;
3775                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3776                                                 IXGBE_4_BIT_MASK);
3777                 if (!mask)
3778                         continue;
3779
3780                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3781                 reta = IXGBE_READ_REG(hw, reta_reg);
3782                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3783                         if (mask & (0x1 << j))
3784                                 reta_conf[idx].reta[shift + j] =
3785                                         ((reta >> (CHAR_BIT * j)) &
3786                                                 IXGBE_8_BIT_MASK);
3787                 }
3788         }
3789
3790         return 0;
3791 }
3792
3793 static void
3794 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3795                                 uint32_t index, uint32_t pool)
3796 {
3797         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3798         uint32_t enable_addr = 1;
3799
3800         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3801 }
3802
3803 static void
3804 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3805 {
3806         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807
3808         ixgbe_clear_rar(hw, index);
3809 }
3810
3811 static void
3812 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3813 {
3814         ixgbe_remove_rar(dev, 0);
3815
3816         ixgbe_add_rar(dev, addr, 0, 0);
3817 }
3818
3819 static int
3820 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3821 {
3822         uint32_t hlreg0;
3823         uint32_t maxfrs;
3824         struct ixgbe_hw *hw;
3825         struct rte_eth_dev_info dev_info;
3826         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3827
3828         ixgbe_dev_info_get(dev, &dev_info);
3829
3830         /* check that mtu is within the allowed range */
3831         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3832                 return -EINVAL;
3833
3834         /* refuse mtu that requires the support of scattered packets when this
3835          * feature has not been enabled before. */
3836         if (!dev->data->scattered_rx &&
3837             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3838              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3839                 return -EINVAL;
3840
3841         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3842         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3843
3844         /* switch to jumbo mode if needed */
3845         if (frame_size > ETHER_MAX_LEN) {
3846                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3847                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3848         } else {
3849                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3850                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3851         }
3852         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3853
3854         /* update max frame size */
3855         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3856
3857         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3858         maxfrs &= 0x0000FFFF;
3859         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3860         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3861
3862         return 0;
3863 }
3864
3865 /*
3866  * Virtual Function operations
3867  */
3868 static void
3869 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3870 {
3871         PMD_INIT_FUNC_TRACE();
3872
3873         /* Clear interrupt mask to stop from interrupts being generated */
3874         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3875
3876         IXGBE_WRITE_FLUSH(hw);
3877 }
3878
3879 static void
3880 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3881 {
3882         PMD_INIT_FUNC_TRACE();
3883
3884         /* VF enable interrupt autoclean */
3885         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3886         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3887         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3888
3889         IXGBE_WRITE_FLUSH(hw);
3890 }
3891
3892 static int
3893 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3894 {
3895         struct rte_eth_conf* conf = &dev->data->dev_conf;
3896         struct ixgbe_adapter *adapter =
3897                         (struct ixgbe_adapter *)dev->data->dev_private;
3898
3899         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3900                      dev->data->port_id);
3901
3902         /*
3903          * VF has no ability to enable/disable HW CRC
3904          * Keep the persistent behavior the same as Host PF
3905          */
3906 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3907         if (!conf->rxmode.hw_strip_crc) {
3908                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3909                 conf->rxmode.hw_strip_crc = 1;
3910         }
3911 #else
3912         if (conf->rxmode.hw_strip_crc) {
3913                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3914                 conf->rxmode.hw_strip_crc = 0;
3915         }
3916 #endif
3917
3918         /*
3919          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3920          * allocation or vector Rx preconditions we will reset it.
3921          */
3922         adapter->rx_bulk_alloc_allowed = true;
3923         adapter->rx_vec_allowed = true;
3924
3925         return 0;
3926 }
3927
3928 static int
3929 ixgbevf_dev_start(struct rte_eth_dev *dev)
3930 {
3931         struct ixgbe_hw *hw =
3932                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3933         uint32_t intr_vector = 0;
3934         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3935
3936         int err, mask = 0;
3937
3938         PMD_INIT_FUNC_TRACE();
3939
3940         hw->mac.ops.reset_hw(hw);
3941         hw->mac.get_link_status = true;
3942
3943         /* negotiate mailbox API version to use with the PF. */
3944         ixgbevf_negotiate_api(hw);
3945
3946         ixgbevf_dev_tx_init(dev);
3947
3948         /* This can fail when allocating mbufs for descriptor rings */
3949         err = ixgbevf_dev_rx_init(dev);
3950         if (err) {
3951                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3952                 ixgbe_dev_clear_queues(dev);
3953                 return err;
3954         }
3955
3956         /* Set vfta */
3957         ixgbevf_set_vfta_all(dev,1);
3958
3959         /* Set HW strip */
3960         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3961                 ETH_VLAN_EXTEND_MASK;
3962         ixgbevf_vlan_offload_set(dev, mask);
3963
3964         ixgbevf_dev_rxtx_start(dev);
3965
3966         /* check and configure queue intr-vector mapping */
3967         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3968                 intr_vector = dev->data->nb_rx_queues;
3969                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3970                         return -1;
3971         }
3972
3973         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3974                 intr_handle->intr_vec =
3975                         rte_zmalloc("intr_vec",
3976                                     dev->data->nb_rx_queues * sizeof(int), 0);
3977                 if (intr_handle->intr_vec == NULL) {
3978                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3979                                      " intr_vec\n", dev->data->nb_rx_queues);
3980                         return -ENOMEM;
3981                 }
3982         }
3983         ixgbevf_configure_msix(dev);
3984
3985         rte_intr_enable(intr_handle);
3986
3987         /* Re-enable interrupt for VF */
3988         ixgbevf_intr_enable(hw);
3989
3990         return 0;
3991 }
3992
3993 static void
3994 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3995 {
3996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3997         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3998
3999         PMD_INIT_FUNC_TRACE();
4000
4001         hw->adapter_stopped = 1;
4002         ixgbe_stop_adapter(hw);
4003
4004         /*
4005           * Clear what we set, but we still keep shadow_vfta to
4006           * restore after device starts
4007           */
4008         ixgbevf_set_vfta_all(dev,0);
4009
4010         /* Clear stored conf */
4011         dev->data->scattered_rx = 0;
4012
4013         ixgbe_dev_clear_queues(dev);
4014
4015         /* Clean datapath event and queue/vec mapping */
4016         rte_intr_efd_disable(intr_handle);
4017         if (intr_handle->intr_vec != NULL) {
4018                 rte_free(intr_handle->intr_vec);
4019                 intr_handle->intr_vec = NULL;
4020         }
4021 }
4022
4023 static void
4024 ixgbevf_dev_close(struct rte_eth_dev *dev)
4025 {
4026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4027
4028         PMD_INIT_FUNC_TRACE();
4029
4030         ixgbe_reset_hw(hw);
4031
4032         ixgbevf_dev_stop(dev);
4033
4034         ixgbe_dev_free_queues(dev);
4035
4036         /**
4037          * Remove the VF MAC address ro ensure
4038          * that the VF traffic goes to the PF
4039          * after stop, close and detach of the VF
4040          **/
4041         ixgbevf_remove_mac_addr(dev, 0);
4042 }
4043
4044 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4045 {
4046         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4047         struct ixgbe_vfta * shadow_vfta =
4048                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4049         int i = 0, j = 0, vfta = 0, mask = 1;
4050
4051         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4052                 vfta = shadow_vfta->vfta[i];
4053                 if (vfta) {
4054                         mask = 1;
4055                         for (j = 0; j < 32; j++){
4056                                 if (vfta & mask)
4057                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4058                                 mask<<=1;
4059                         }
4060                 }
4061         }
4062
4063 }
4064
4065 static int
4066 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4067 {
4068         struct ixgbe_hw *hw =
4069                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4070         struct ixgbe_vfta * shadow_vfta =
4071                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4072         uint32_t vid_idx = 0;
4073         uint32_t vid_bit = 0;
4074         int ret = 0;
4075
4076         PMD_INIT_FUNC_TRACE();
4077
4078         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4079         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4080         if (ret) {
4081                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4082                 return ret;
4083         }
4084         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4085         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4086
4087         /* Save what we set and retore it after device reset */
4088         if (on)
4089                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4090         else
4091                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4092
4093         return 0;
4094 }
4095
4096 static void
4097 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4098 {
4099         struct ixgbe_hw *hw =
4100                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4101         uint32_t ctrl;
4102
4103         PMD_INIT_FUNC_TRACE();
4104
4105         if (queue >= hw->mac.max_rx_queues)
4106                 return;
4107
4108         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4109         if (on)
4110                 ctrl |= IXGBE_RXDCTL_VME;
4111         else
4112                 ctrl &= ~IXGBE_RXDCTL_VME;
4113         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4114
4115         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4116 }
4117
4118 static void
4119 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4120 {
4121         struct ixgbe_hw *hw =
4122                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4123         uint16_t i;
4124         int on = 0;
4125
4126         /* VF function only support hw strip feature, others are not support */
4127         if (mask & ETH_VLAN_STRIP_MASK) {
4128                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4129
4130                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4131                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4132         }
4133 }
4134
4135 static int
4136 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4137 {
4138         uint32_t reg_val;
4139
4140         /* we only need to do this if VMDq is enabled */
4141         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4142         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4143                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4144                 return -1;
4145         }
4146
4147         return 0;
4148 }
4149
4150 static uint32_t
4151 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4152 {
4153         uint32_t vector = 0;
4154         switch (hw->mac.mc_filter_type) {
4155         case 0:   /* use bits [47:36] of the address */
4156                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4157                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4158                 break;
4159         case 1:   /* use bits [46:35] of the address */
4160                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4161                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4162                 break;
4163         case 2:   /* use bits [45:34] of the address */
4164                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4165                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4166                 break;
4167         case 3:   /* use bits [43:32] of the address */
4168                 vector = ((uc_addr->addr_bytes[4]) |
4169                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4170                 break;
4171         default:  /* Invalid mc_filter_type */
4172                 break;
4173         }
4174
4175         /* vector can only be 12-bits or boundary will be exceeded */
4176         vector &= 0xFFF;
4177         return vector;
4178 }
4179
4180 static int
4181 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4182                                uint8_t on)
4183 {
4184         uint32_t vector;
4185         uint32_t uta_idx;
4186         uint32_t reg_val;
4187         uint32_t uta_shift;
4188         uint32_t rc;
4189         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4190         const uint32_t ixgbe_uta_bit_shift = 5;
4191         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4192         const uint32_t bit1 = 0x1;
4193
4194         struct ixgbe_hw *hw =
4195                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4196         struct ixgbe_uta_info *uta_info =
4197                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4198
4199         /* The UTA table only exists on 82599 hardware and newer */
4200         if (hw->mac.type < ixgbe_mac_82599EB)
4201                 return -ENOTSUP;
4202
4203         vector = ixgbe_uta_vector(hw,mac_addr);
4204         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4205         uta_shift = vector & ixgbe_uta_bit_mask;
4206
4207         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4208         if (rc == on)
4209                 return 0;
4210
4211         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4212         if (on) {
4213                 uta_info->uta_in_use++;
4214                 reg_val |= (bit1 << uta_shift);
4215                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4216         } else {
4217                 uta_info->uta_in_use--;
4218                 reg_val &= ~(bit1 << uta_shift);
4219                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4220         }
4221
4222         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4223
4224         if (uta_info->uta_in_use > 0)
4225                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4226                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4227         else
4228                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4229
4230         return 0;
4231 }
4232
4233 static int
4234 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4235 {
4236         int i;
4237         struct ixgbe_hw *hw =
4238                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4239         struct ixgbe_uta_info *uta_info =
4240                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4241
4242         /* The UTA table only exists on 82599 hardware and newer */
4243         if (hw->mac.type < ixgbe_mac_82599EB)
4244                 return -ENOTSUP;
4245
4246         if (on) {
4247                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4248                         uta_info->uta_shadow[i] = ~0;
4249                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4250                 }
4251         } else {
4252                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4253                         uta_info->uta_shadow[i] = 0;
4254                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4255                 }
4256         }
4257         return 0;
4258
4259 }
4260
4261 uint32_t
4262 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4263 {
4264         uint32_t new_val = orig_val;
4265
4266         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4267                 new_val |= IXGBE_VMOLR_AUPE;
4268         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4269                 new_val |= IXGBE_VMOLR_ROMPE;
4270         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4271                 new_val |= IXGBE_VMOLR_ROPE;
4272         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4273                 new_val |= IXGBE_VMOLR_BAM;
4274         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4275                 new_val |= IXGBE_VMOLR_MPE;
4276
4277         return new_val;
4278 }
4279
4280 static int
4281 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4282                                uint16_t rx_mask, uint8_t on)
4283 {
4284         int val = 0;
4285
4286         struct ixgbe_hw *hw =
4287                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4288         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4289
4290         if (hw->mac.type == ixgbe_mac_82598EB) {
4291                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4292                              " on 82599 hardware and newer");
4293                 return -ENOTSUP;
4294         }
4295         if (ixgbe_vmdq_mode_check(hw) < 0)
4296                 return -ENOTSUP;
4297
4298         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4299
4300         if (on)
4301                 vmolr |= val;
4302         else
4303                 vmolr &= ~val;
4304
4305         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4306
4307         return 0;
4308 }
4309
4310 static int
4311 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4312 {
4313         uint32_t reg,addr;
4314         uint32_t val;
4315         const uint8_t bit1 = 0x1;
4316
4317         struct ixgbe_hw *hw =
4318                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4319
4320         if (ixgbe_vmdq_mode_check(hw) < 0)
4321                 return -ENOTSUP;
4322
4323         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4324         reg = IXGBE_READ_REG(hw, addr);
4325         val = bit1 << pool;
4326
4327         if (on)
4328                 reg |= val;
4329         else
4330                 reg &= ~val;
4331
4332         IXGBE_WRITE_REG(hw, addr,reg);
4333
4334         return 0;
4335 }
4336
4337 static int
4338 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4339 {
4340         uint32_t reg,addr;
4341         uint32_t val;
4342         const uint8_t bit1 = 0x1;
4343
4344         struct ixgbe_hw *hw =
4345                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4346
4347         if (ixgbe_vmdq_mode_check(hw) < 0)
4348                 return -ENOTSUP;
4349
4350         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4351         reg = IXGBE_READ_REG(hw, addr);
4352         val = bit1 << pool;
4353
4354         if (on)
4355                 reg |= val;
4356         else
4357                 reg &= ~val;
4358
4359         IXGBE_WRITE_REG(hw, addr,reg);
4360
4361         return 0;
4362 }
4363
4364 static int
4365 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4366                         uint64_t pool_mask, uint8_t vlan_on)
4367 {
4368         int ret = 0;
4369         uint16_t pool_idx;
4370         struct ixgbe_hw *hw =
4371                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4372
4373         if (ixgbe_vmdq_mode_check(hw) < 0)
4374                 return -ENOTSUP;
4375         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4376                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4377                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4378                         if (ret < 0)
4379                                 return ret;
4380         }
4381
4382         return ret;
4383 }
4384
4385 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4386 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4387 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4388 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4389 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4390         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4391         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4392
4393 static int
4394 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4395                         struct rte_eth_mirror_conf *mirror_conf,
4396                         uint8_t rule_id, uint8_t on)
4397 {
4398         uint32_t mr_ctl,vlvf;
4399         uint32_t mp_lsb = 0;
4400         uint32_t mv_msb = 0;
4401         uint32_t mv_lsb = 0;
4402         uint32_t mp_msb = 0;
4403         uint8_t i = 0;
4404         int reg_index = 0;
4405         uint64_t vlan_mask = 0;
4406
4407         const uint8_t pool_mask_offset = 32;
4408         const uint8_t vlan_mask_offset = 32;
4409         const uint8_t dst_pool_offset = 8;
4410         const uint8_t rule_mr_offset  = 4;
4411         const uint8_t mirror_rule_mask= 0x0F;
4412
4413         struct ixgbe_mirror_info *mr_info =
4414                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4415         struct ixgbe_hw *hw =
4416                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4417         uint8_t mirror_type = 0;
4418
4419         if (ixgbe_vmdq_mode_check(hw) < 0)
4420                 return -ENOTSUP;
4421
4422         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4423                 return -EINVAL;
4424
4425         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4426                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4427                         mirror_conf->rule_type);
4428                 return -EINVAL;
4429         }
4430
4431         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4432                 mirror_type |= IXGBE_MRCTL_VLME;
4433                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4434                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4435                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4436                                 /* search vlan id related pool vlan filter index */
4437                                 reg_index = ixgbe_find_vlvf_slot(hw,
4438                                                 mirror_conf->vlan.vlan_id[i]);
4439                                 if (reg_index < 0)
4440                                         return -EINVAL;
4441                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4442                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4443                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4444                                       mirror_conf->vlan.vlan_id[i]))
4445                                         vlan_mask |= (1ULL << reg_index);
4446                                 else
4447                                         return -EINVAL;
4448                         }
4449                 }
4450
4451                 if (on) {
4452                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4453                         mv_msb = vlan_mask >> vlan_mask_offset;
4454
4455                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4456                                                 mirror_conf->vlan.vlan_mask;
4457                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4458                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4459                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4460                                                 mirror_conf->vlan.vlan_id[i];
4461                         }
4462                 } else {
4463                         mv_lsb = 0;
4464                         mv_msb = 0;
4465                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4466                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4467                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4468                 }
4469         }
4470
4471         /*
4472          * if enable pool mirror, write related pool mask register,if disable
4473          * pool mirror, clear PFMRVM register
4474          */
4475         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4476                 mirror_type |= IXGBE_MRCTL_VPME;
4477                 if (on) {
4478                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4479                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4480                         mr_info->mr_conf[rule_id].pool_mask =
4481                                         mirror_conf->pool_mask;
4482
4483                 } else {
4484                         mp_lsb = 0;
4485                         mp_msb = 0;
4486                         mr_info->mr_conf[rule_id].pool_mask = 0;
4487                 }
4488         }
4489         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4490                 mirror_type |= IXGBE_MRCTL_UPME;
4491         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4492                 mirror_type |= IXGBE_MRCTL_DPME;
4493
4494         /* read  mirror control register and recalculate it */
4495         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4496
4497         if (on) {
4498                 mr_ctl |= mirror_type;
4499                 mr_ctl &= mirror_rule_mask;
4500                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4501         } else
4502                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4503
4504         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4505         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4506
4507         /* write mirrror control  register */
4508         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4509
4510         /* write pool mirrror control  register */
4511         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4512                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4513                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4514                                 mp_msb);
4515         }
4516         /* write VLAN mirrror control  register */
4517         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4518                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4519                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4520                                 mv_msb);
4521         }
4522
4523         return 0;
4524 }
4525
4526 static int
4527 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4528 {
4529         int mr_ctl = 0;
4530         uint32_t lsb_val = 0;
4531         uint32_t msb_val = 0;
4532         const uint8_t rule_mr_offset = 4;
4533
4534         struct ixgbe_hw *hw =
4535                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4536         struct ixgbe_mirror_info *mr_info =
4537                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4538
4539         if (ixgbe_vmdq_mode_check(hw) < 0)
4540                 return -ENOTSUP;
4541
4542         memset(&mr_info->mr_conf[rule_id], 0,
4543                 sizeof(struct rte_eth_mirror_conf));
4544
4545         /* clear PFVMCTL register */
4546         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4547
4548         /* clear pool mask register */
4549         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4550         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4551
4552         /* clear vlan mask register */
4553         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4554         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4555
4556         return 0;
4557 }
4558
4559 static int
4560 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4561 {
4562         uint32_t mask;
4563         struct ixgbe_hw *hw =
4564                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4565
4566         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4567         mask |= (1 << IXGBE_MISC_VEC_ID);
4568         RTE_SET_USED(queue_id);
4569         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4570
4571         rte_intr_enable(&dev->pci_dev->intr_handle);
4572
4573         return 0;
4574 }
4575
4576 static int
4577 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4578 {
4579         uint32_t mask;
4580         struct ixgbe_hw *hw =
4581                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4582
4583         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4584         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4585         RTE_SET_USED(queue_id);
4586         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4587
4588         return 0;
4589 }
4590
4591 static int
4592 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4593 {
4594         uint32_t mask;
4595         struct ixgbe_hw *hw =
4596                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4597         struct ixgbe_interrupt *intr =
4598                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4599
4600         if (queue_id < 16) {
4601                 ixgbe_disable_intr(hw);
4602                 intr->mask |= (1 << queue_id);
4603                 ixgbe_enable_intr(dev);
4604         } else if (queue_id < 32) {
4605                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4606                 mask &= (1 << queue_id);
4607                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4608         } else if (queue_id < 64) {
4609                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4610                 mask &= (1 << (queue_id - 32));
4611                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4612         }
4613         rte_intr_enable(&dev->pci_dev->intr_handle);
4614
4615         return 0;
4616 }
4617
4618 static int
4619 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4620 {
4621         uint32_t mask;
4622         struct ixgbe_hw *hw =
4623                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4624         struct ixgbe_interrupt *intr =
4625                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4626
4627         if (queue_id < 16) {
4628                 ixgbe_disable_intr(hw);
4629                 intr->mask &= ~(1 << queue_id);
4630                 ixgbe_enable_intr(dev);
4631         } else if (queue_id < 32) {
4632                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4633                 mask &= ~(1 << queue_id);
4634                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4635         } else if (queue_id < 64) {
4636                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4637                 mask &= ~(1 << (queue_id - 32));
4638                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4639         }
4640
4641         return 0;
4642 }
4643
4644 static void
4645 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4646                      uint8_t queue, uint8_t msix_vector)
4647 {
4648         uint32_t tmp, idx;
4649
4650         if (direction == -1) {
4651                 /* other causes */
4652                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4653                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4654                 tmp &= ~0xFF;
4655                 tmp |= msix_vector;
4656                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4657         } else {
4658                 /* rx or tx cause */
4659                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4660                 idx = ((16 * (queue & 1)) + (8 * direction));
4661                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4662                 tmp &= ~(0xFF << idx);
4663                 tmp |= (msix_vector << idx);
4664                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4665         }
4666 }
4667
4668 /**
4669  * set the IVAR registers, mapping interrupt causes to vectors
4670  * @param hw
4671  *  pointer to ixgbe_hw struct
4672  * @direction
4673  *  0 for Rx, 1 for Tx, -1 for other causes
4674  * @queue
4675  *  queue to map the corresponding interrupt to
4676  * @msix_vector
4677  *  the vector to map to the corresponding queue
4678  */
4679 static void
4680 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4681                    uint8_t queue, uint8_t msix_vector)
4682 {
4683         uint32_t tmp, idx;
4684
4685         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4686         if (hw->mac.type == ixgbe_mac_82598EB) {
4687                 if (direction == -1)
4688                         direction = 0;
4689                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4690                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4691                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4692                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4693                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4694         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4695                         (hw->mac.type == ixgbe_mac_X540)) {
4696                 if (direction == -1) {
4697                         /* other causes */
4698                         idx = ((queue & 1) * 8);
4699                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4700                         tmp &= ~(0xFF << idx);
4701                         tmp |= (msix_vector << idx);
4702                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4703                 } else {
4704                         /* rx or tx causes */
4705                         idx = ((16 * (queue & 1)) + (8 * direction));
4706                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4707                         tmp &= ~(0xFF << idx);
4708                         tmp |= (msix_vector << idx);
4709                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4710                 }
4711         }
4712 }
4713
4714 static void
4715 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4716 {
4717         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4718         struct ixgbe_hw *hw =
4719                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4720         uint32_t q_idx;
4721         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4722
4723         /* won't configure msix register if no mapping is done
4724          * between intr vector and event fd.
4725          */
4726         if (!rte_intr_dp_is_en(intr_handle))
4727                 return;
4728
4729         /* Configure all RX queues of VF */
4730         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4731                 /* Force all queue use vector 0,
4732                  * as IXGBE_VF_MAXMSIVECOTR = 1
4733                  */
4734                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4735                 intr_handle->intr_vec[q_idx] = vector_idx;
4736         }
4737
4738         /* Configure VF other cause ivar */
4739         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4740 }
4741
4742 /**
4743  * Sets up the hardware to properly generate MSI-X interrupts
4744  * @hw
4745  *  board private structure
4746  */
4747 static void
4748 ixgbe_configure_msix(struct rte_eth_dev *dev)
4749 {
4750         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4751         struct ixgbe_hw *hw =
4752                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4753         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4754         uint32_t vec = IXGBE_MISC_VEC_ID;
4755         uint32_t mask;
4756         uint32_t gpie;
4757
4758         /* won't configure msix register if no mapping is done
4759          * between intr vector and event fd
4760          */
4761         if (!rte_intr_dp_is_en(intr_handle))
4762                 return;
4763
4764         if (rte_intr_allow_others(intr_handle))
4765                 vec = base = IXGBE_RX_VEC_START;
4766
4767         /* setup GPIE for MSI-x mode */
4768         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4769         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4770                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4771         /* auto clearing and auto setting corresponding bits in EIMS
4772          * when MSI-X interrupt is triggered
4773          */
4774         if (hw->mac.type == ixgbe_mac_82598EB) {
4775                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4776         } else {
4777                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4778                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4779         }
4780         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4781
4782         /* Populate the IVAR table and set the ITR values to the
4783          * corresponding register.
4784          */
4785         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4786              queue_id++) {
4787                 /* by default, 1:1 mapping */
4788                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4789                 intr_handle->intr_vec[queue_id] = vec;
4790                 if (vec < base + intr_handle->nb_efd - 1)
4791                         vec++;
4792         }
4793
4794         switch (hw->mac.type) {
4795         case ixgbe_mac_82598EB:
4796                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4797                                    IXGBE_MISC_VEC_ID);
4798                 break;
4799         case ixgbe_mac_82599EB:
4800         case ixgbe_mac_X540:
4801                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4802                 break;
4803         default:
4804                 break;
4805         }
4806         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4807                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4808
4809         /* set up to autoclear timer, and the vectors */
4810         mask = IXGBE_EIMS_ENABLE_MASK;
4811         mask &= ~(IXGBE_EIMS_OTHER |
4812                   IXGBE_EIMS_MAILBOX |
4813                   IXGBE_EIMS_LSC);
4814
4815         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4816 }
4817
4818 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4819         uint16_t queue_idx, uint16_t tx_rate)
4820 {
4821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4822         uint32_t rf_dec, rf_int;
4823         uint32_t bcnrc_val;
4824         uint16_t link_speed = dev->data->dev_link.link_speed;
4825
4826         if (queue_idx >= hw->mac.max_tx_queues)
4827                 return -EINVAL;
4828
4829         if (tx_rate != 0) {
4830                 /* Calculate the rate factor values to set */
4831                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4832                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4833                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4834
4835                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4836                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4837                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4838                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4839         } else {
4840                 bcnrc_val = 0;
4841         }
4842
4843         /*
4844          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4845          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4846          * set as 0x4.
4847          */
4848         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4849                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4850                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4851                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4852                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4853         else
4854                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4855                         IXGBE_MMW_SIZE_DEFAULT);
4856
4857         /* Set RTTBCNRC of queue X */
4858         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4859         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4860         IXGBE_WRITE_FLUSH(hw);
4861
4862         return 0;
4863 }
4864
4865 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4866         uint16_t tx_rate, uint64_t q_msk)
4867 {
4868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4869         struct ixgbe_vf_info *vfinfo =
4870                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4871         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4872         uint32_t queue_stride =
4873                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4874         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4875         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4876         uint16_t total_rate = 0;
4877
4878         if (queue_end >= hw->mac.max_tx_queues)
4879                 return -EINVAL;
4880
4881         if (vfinfo != NULL) {
4882                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4883                         if (vf_idx == vf)
4884                                 continue;
4885                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4886                                 idx++)
4887                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4888                 }
4889         } else
4890                 return -EINVAL;
4891
4892         /* Store tx_rate for this vf. */
4893         for (idx = 0; idx < nb_q_per_pool; idx++) {
4894                 if (((uint64_t)0x1 << idx) & q_msk) {
4895                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4896                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4897                         total_rate += tx_rate;
4898                 }
4899         }
4900
4901         if (total_rate > dev->data->dev_link.link_speed) {
4902                 /*
4903                  * Reset stored TX rate of the VF if it causes exceed
4904                  * link speed.
4905                  */
4906                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4907                 return -EINVAL;
4908         }
4909
4910         /* Set RTTBCNRC of each queue/pool for vf X  */
4911         for (; queue_idx <= queue_end; queue_idx++) {
4912                 if (0x1 & q_msk)
4913                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4914                 q_msk = q_msk >> 1;
4915         }
4916
4917         return 0;
4918 }
4919
4920 static void
4921 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4922                      __attribute__((unused)) uint32_t index,
4923                      __attribute__((unused)) uint32_t pool)
4924 {
4925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4926         int diag;
4927
4928         /*
4929          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4930          * operation. Trap this case to avoid exhausting the [very limited]
4931          * set of PF resources used to store VF MAC addresses.
4932          */
4933         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4934                 return;
4935         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4936         if (diag == 0)
4937                 return;
4938         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4939 }
4940
4941 static void
4942 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4943 {
4944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4945         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4946         struct ether_addr *mac_addr;
4947         uint32_t i;
4948         int diag;
4949
4950         /*
4951          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4952          * not support the deletion of a given MAC address.
4953          * Instead, it imposes to delete all MAC addresses, then to add again
4954          * all MAC addresses with the exception of the one to be deleted.
4955          */
4956         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4957
4958         /*
4959          * Add again all MAC addresses, with the exception of the deleted one
4960          * and of the permanent MAC address.
4961          */
4962         for (i = 0, mac_addr = dev->data->mac_addrs;
4963              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4964                 /* Skip the deleted MAC address */
4965                 if (i == index)
4966                         continue;
4967                 /* Skip NULL MAC addresses */
4968                 if (is_zero_ether_addr(mac_addr))
4969                         continue;
4970                 /* Skip the permanent MAC address */
4971                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4972                         continue;
4973                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4974                 if (diag != 0)
4975                         PMD_DRV_LOG(ERR,
4976                                     "Adding again MAC address "
4977                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4978                                     "diag=%d",
4979                                     mac_addr->addr_bytes[0],
4980                                     mac_addr->addr_bytes[1],
4981                                     mac_addr->addr_bytes[2],
4982                                     mac_addr->addr_bytes[3],
4983                                     mac_addr->addr_bytes[4],
4984                                     mac_addr->addr_bytes[5],
4985                                     diag);
4986         }
4987 }
4988
4989 static void
4990 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4991 {
4992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4993
4994         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4995 }
4996
4997 #define MAC_TYPE_FILTER_SUP(type)    do {\
4998         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4999                 (type) != ixgbe_mac_X550)\
5000                 return -ENOTSUP;\
5001 } while (0)
5002
5003 static int
5004 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5005                         struct rte_eth_syn_filter *filter,
5006                         bool add)
5007 {
5008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5009         uint32_t synqf;
5010
5011         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5012                 return -EINVAL;
5013
5014         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5015
5016         if (add) {
5017                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5018                         return -EINVAL;
5019                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5020                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5021
5022                 if (filter->hig_pri)
5023                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5024                 else
5025                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5026         } else {
5027                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5028                         return -ENOENT;
5029                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5030         }
5031         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5032         IXGBE_WRITE_FLUSH(hw);
5033         return 0;
5034 }
5035
5036 static int
5037 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5038                         struct rte_eth_syn_filter *filter)
5039 {
5040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5041         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5042
5043         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5044                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5045                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5046                 return 0;
5047         }
5048         return -ENOENT;
5049 }
5050
5051 static int
5052 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5053                         enum rte_filter_op filter_op,
5054                         void *arg)
5055 {
5056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057         int ret;
5058
5059         MAC_TYPE_FILTER_SUP(hw->mac.type);
5060
5061         if (filter_op == RTE_ETH_FILTER_NOP)
5062                 return 0;
5063
5064         if (arg == NULL) {
5065                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5066                             filter_op);
5067                 return -EINVAL;
5068         }
5069
5070         switch (filter_op) {
5071         case RTE_ETH_FILTER_ADD:
5072                 ret = ixgbe_syn_filter_set(dev,
5073                                 (struct rte_eth_syn_filter *)arg,
5074                                 TRUE);
5075                 break;
5076         case RTE_ETH_FILTER_DELETE:
5077                 ret = ixgbe_syn_filter_set(dev,
5078                                 (struct rte_eth_syn_filter *)arg,
5079                                 FALSE);
5080                 break;
5081         case RTE_ETH_FILTER_GET:
5082                 ret = ixgbe_syn_filter_get(dev,
5083                                 (struct rte_eth_syn_filter *)arg);
5084                 break;
5085         default:
5086                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5087                 ret = -EINVAL;
5088                 break;
5089         }
5090
5091         return ret;
5092 }
5093
5094
5095 static inline enum ixgbe_5tuple_protocol
5096 convert_protocol_type(uint8_t protocol_value)
5097 {
5098         if (protocol_value == IPPROTO_TCP)
5099                 return IXGBE_FILTER_PROTOCOL_TCP;
5100         else if (protocol_value == IPPROTO_UDP)
5101                 return IXGBE_FILTER_PROTOCOL_UDP;
5102         else if (protocol_value == IPPROTO_SCTP)
5103                 return IXGBE_FILTER_PROTOCOL_SCTP;
5104         else
5105                 return IXGBE_FILTER_PROTOCOL_NONE;
5106 }
5107
5108 /*
5109  * add a 5tuple filter
5110  *
5111  * @param
5112  * dev: Pointer to struct rte_eth_dev.
5113  * index: the index the filter allocates.
5114  * filter: ponter to the filter that will be added.
5115  * rx_queue: the queue id the filter assigned to.
5116  *
5117  * @return
5118  *    - On success, zero.
5119  *    - On failure, a negative value.
5120  */
5121 static int
5122 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5123                         struct ixgbe_5tuple_filter *filter)
5124 {
5125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5126         struct ixgbe_filter_info *filter_info =
5127                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5128         int i, idx, shift;
5129         uint32_t ftqf, sdpqf;
5130         uint32_t l34timir = 0;
5131         uint8_t mask = 0xff;
5132
5133         /*
5134          * look for an unused 5tuple filter index,
5135          * and insert the filter to list.
5136          */
5137         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5138                 idx = i / (sizeof(uint32_t) * NBBY);
5139                 shift = i % (sizeof(uint32_t) * NBBY);
5140                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5141                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5142                         filter->index = i;
5143                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5144                                           filter,
5145                                           entries);
5146                         break;
5147                 }
5148         }
5149         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5150                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5151                 return -ENOSYS;
5152         }
5153
5154         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5155                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5156         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5157
5158         ftqf = (uint32_t)(filter->filter_info.proto &
5159                 IXGBE_FTQF_PROTOCOL_MASK);
5160         ftqf |= (uint32_t)((filter->filter_info.priority &
5161                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5162         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5163                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5164         if (filter->filter_info.dst_ip_mask == 0)
5165                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5166         if (filter->filter_info.src_port_mask == 0)
5167                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5168         if (filter->filter_info.dst_port_mask == 0)
5169                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5170         if (filter->filter_info.proto_mask == 0)
5171                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5172         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5173         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5174         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5175
5176         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5177         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5178         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5179         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5180
5181         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5182         l34timir |= (uint32_t)(filter->queue <<
5183                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5184         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5185         return 0;
5186 }
5187
5188 /*
5189  * remove a 5tuple filter
5190  *
5191  * @param
5192  * dev: Pointer to struct rte_eth_dev.
5193  * filter: the pointer of the filter will be removed.
5194  */
5195 static void
5196 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5197                         struct ixgbe_5tuple_filter *filter)
5198 {
5199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5200         struct ixgbe_filter_info *filter_info =
5201                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5202         uint16_t index = filter->index;
5203
5204         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5205                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5206         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5207         rte_free(filter);
5208
5209         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5210         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5211         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5212         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5213         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5214 }
5215
5216 static int
5217 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5218 {
5219         struct ixgbe_hw *hw;
5220         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5221
5222         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5223
5224         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5225                 return -EINVAL;
5226
5227         /* refuse mtu that requires the support of scattered packets when this
5228          * feature has not been enabled before. */
5229         if (!dev->data->scattered_rx &&
5230             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5231              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5232                 return -EINVAL;
5233
5234         /*
5235          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5236          * request of the version 2.0 of the mailbox API.
5237          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5238          * of the mailbox API.
5239          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5240          * prior to 3.11.33 which contains the following change:
5241          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5242          */
5243         ixgbevf_rlpml_set_vf(hw, max_frame);
5244
5245         /* update max frame size */
5246         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5247         return 0;
5248 }
5249
5250 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5251         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5252                 return -ENOTSUP;\
5253 } while (0)
5254
5255 static inline struct ixgbe_5tuple_filter *
5256 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5257                         struct ixgbe_5tuple_filter_info *key)
5258 {
5259         struct ixgbe_5tuple_filter *it;
5260
5261         TAILQ_FOREACH(it, filter_list, entries) {
5262                 if (memcmp(key, &it->filter_info,
5263                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5264                         return it;
5265                 }
5266         }
5267         return NULL;
5268 }
5269
5270 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5271 static inline int
5272 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5273                         struct ixgbe_5tuple_filter_info *filter_info)
5274 {
5275         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5276                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5277                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5278                 return -EINVAL;
5279
5280         switch (filter->dst_ip_mask) {
5281         case UINT32_MAX:
5282                 filter_info->dst_ip_mask = 0;
5283                 filter_info->dst_ip = filter->dst_ip;
5284                 break;
5285         case 0:
5286                 filter_info->dst_ip_mask = 1;
5287                 break;
5288         default:
5289                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5290                 return -EINVAL;
5291         }
5292
5293         switch (filter->src_ip_mask) {
5294         case UINT32_MAX:
5295                 filter_info->src_ip_mask = 0;
5296                 filter_info->src_ip = filter->src_ip;
5297                 break;
5298         case 0:
5299                 filter_info->src_ip_mask = 1;
5300                 break;
5301         default:
5302                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5303                 return -EINVAL;
5304         }
5305
5306         switch (filter->dst_port_mask) {
5307         case UINT16_MAX:
5308                 filter_info->dst_port_mask = 0;
5309                 filter_info->dst_port = filter->dst_port;
5310                 break;
5311         case 0:
5312                 filter_info->dst_port_mask = 1;
5313                 break;
5314         default:
5315                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5316                 return -EINVAL;
5317         }
5318
5319         switch (filter->src_port_mask) {
5320         case UINT16_MAX:
5321                 filter_info->src_port_mask = 0;
5322                 filter_info->src_port = filter->src_port;
5323                 break;
5324         case 0:
5325                 filter_info->src_port_mask = 1;
5326                 break;
5327         default:
5328                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5329                 return -EINVAL;
5330         }
5331
5332         switch (filter->proto_mask) {
5333         case UINT8_MAX:
5334                 filter_info->proto_mask = 0;
5335                 filter_info->proto =
5336                         convert_protocol_type(filter->proto);
5337                 break;
5338         case 0:
5339                 filter_info->proto_mask = 1;
5340                 break;
5341         default:
5342                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5343                 return -EINVAL;
5344         }
5345
5346         filter_info->priority = (uint8_t)filter->priority;
5347         return 0;
5348 }
5349
5350 /*
5351  * add or delete a ntuple filter
5352  *
5353  * @param
5354  * dev: Pointer to struct rte_eth_dev.
5355  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5356  * add: if true, add filter, if false, remove filter
5357  *
5358  * @return
5359  *    - On success, zero.
5360  *    - On failure, a negative value.
5361  */
5362 static int
5363 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5364                         struct rte_eth_ntuple_filter *ntuple_filter,
5365                         bool add)
5366 {
5367         struct ixgbe_filter_info *filter_info =
5368                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5369         struct ixgbe_5tuple_filter_info filter_5tuple;
5370         struct ixgbe_5tuple_filter *filter;
5371         int ret;
5372
5373         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5374                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5375                 return -EINVAL;
5376         }
5377
5378         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5379         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5380         if (ret < 0)
5381                 return ret;
5382
5383         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5384                                          &filter_5tuple);
5385         if (filter != NULL && add) {
5386                 PMD_DRV_LOG(ERR, "filter exists.");
5387                 return -EEXIST;
5388         }
5389         if (filter == NULL && !add) {
5390                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5391                 return -ENOENT;
5392         }
5393
5394         if (add) {
5395                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5396                                 sizeof(struct ixgbe_5tuple_filter), 0);
5397                 if (filter == NULL)
5398                         return -ENOMEM;
5399                 (void)rte_memcpy(&filter->filter_info,
5400                                  &filter_5tuple,
5401                                  sizeof(struct ixgbe_5tuple_filter_info));
5402                 filter->queue = ntuple_filter->queue;
5403                 ret = ixgbe_add_5tuple_filter(dev, filter);
5404                 if (ret < 0) {
5405                         rte_free(filter);
5406                         return ret;
5407                 }
5408         } else
5409                 ixgbe_remove_5tuple_filter(dev, filter);
5410
5411         return 0;
5412 }
5413
5414 /*
5415  * get a ntuple filter
5416  *
5417  * @param
5418  * dev: Pointer to struct rte_eth_dev.
5419  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5420  *
5421  * @return
5422  *    - On success, zero.
5423  *    - On failure, a negative value.
5424  */
5425 static int
5426 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5427                         struct rte_eth_ntuple_filter *ntuple_filter)
5428 {
5429         struct ixgbe_filter_info *filter_info =
5430                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5431         struct ixgbe_5tuple_filter_info filter_5tuple;
5432         struct ixgbe_5tuple_filter *filter;
5433         int ret;
5434
5435         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5436                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5437                 return -EINVAL;
5438         }
5439
5440         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5441         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5442         if (ret < 0)
5443                 return ret;
5444
5445         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5446                                          &filter_5tuple);
5447         if (filter == NULL) {
5448                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5449                 return -ENOENT;
5450         }
5451         ntuple_filter->queue = filter->queue;
5452         return 0;
5453 }
5454
5455 /*
5456  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5457  * @dev: pointer to rte_eth_dev structure
5458  * @filter_op:operation will be taken.
5459  * @arg: a pointer to specific structure corresponding to the filter_op
5460  *
5461  * @return
5462  *    - On success, zero.
5463  *    - On failure, a negative value.
5464  */
5465 static int
5466 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5467                                 enum rte_filter_op filter_op,
5468                                 void *arg)
5469 {
5470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5471         int ret;
5472
5473         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5474
5475         if (filter_op == RTE_ETH_FILTER_NOP)
5476                 return 0;
5477
5478         if (arg == NULL) {
5479                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5480                             filter_op);
5481                 return -EINVAL;
5482         }
5483
5484         switch (filter_op) {
5485         case RTE_ETH_FILTER_ADD:
5486                 ret = ixgbe_add_del_ntuple_filter(dev,
5487                         (struct rte_eth_ntuple_filter *)arg,
5488                         TRUE);
5489                 break;
5490         case RTE_ETH_FILTER_DELETE:
5491                 ret = ixgbe_add_del_ntuple_filter(dev,
5492                         (struct rte_eth_ntuple_filter *)arg,
5493                         FALSE);
5494                 break;
5495         case RTE_ETH_FILTER_GET:
5496                 ret = ixgbe_get_ntuple_filter(dev,
5497                         (struct rte_eth_ntuple_filter *)arg);
5498                 break;
5499         default:
5500                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5501                 ret = -EINVAL;
5502                 break;
5503         }
5504         return ret;
5505 }
5506
5507 static inline int
5508 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5509                         uint16_t ethertype)
5510 {
5511         int i;
5512
5513         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5514                 if (filter_info->ethertype_filters[i] == ethertype &&
5515                     (filter_info->ethertype_mask & (1 << i)))
5516                         return i;
5517         }
5518         return -1;
5519 }
5520
5521 static inline int
5522 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5523                         uint16_t ethertype)
5524 {
5525         int i;
5526
5527         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5528                 if (!(filter_info->ethertype_mask & (1 << i))) {
5529                         filter_info->ethertype_mask |= 1 << i;
5530                         filter_info->ethertype_filters[i] = ethertype;
5531                         return i;
5532                 }
5533         }
5534         return -1;
5535 }
5536
5537 static inline int
5538 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5539                         uint8_t idx)
5540 {
5541         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5542                 return -1;
5543         filter_info->ethertype_mask &= ~(1 << idx);
5544         filter_info->ethertype_filters[idx] = 0;
5545         return idx;
5546 }
5547
5548 static int
5549 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5550                         struct rte_eth_ethertype_filter *filter,
5551                         bool add)
5552 {
5553         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5554         struct ixgbe_filter_info *filter_info =
5555                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5556         uint32_t etqf = 0;
5557         uint32_t etqs = 0;
5558         int ret;
5559
5560         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5561                 return -EINVAL;
5562
5563         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5564                 filter->ether_type == ETHER_TYPE_IPv6) {
5565                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5566                         " ethertype filter.", filter->ether_type);
5567                 return -EINVAL;
5568         }
5569
5570         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5571                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5572                 return -EINVAL;
5573         }
5574         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5575                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5576                 return -EINVAL;
5577         }
5578
5579         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5580         if (ret >= 0 && add) {
5581                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5582                             filter->ether_type);
5583                 return -EEXIST;
5584         }
5585         if (ret < 0 && !add) {
5586                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5587                             filter->ether_type);
5588                 return -ENOENT;
5589         }
5590
5591         if (add) {
5592                 ret = ixgbe_ethertype_filter_insert(filter_info,
5593                         filter->ether_type);
5594                 if (ret < 0) {
5595                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5596                         return -ENOSYS;
5597                 }
5598                 etqf = IXGBE_ETQF_FILTER_EN;
5599                 etqf |= (uint32_t)filter->ether_type;
5600                 etqs |= (uint32_t)((filter->queue <<
5601                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5602                                     IXGBE_ETQS_RX_QUEUE);
5603                 etqs |= IXGBE_ETQS_QUEUE_EN;
5604         } else {
5605                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5606                 if (ret < 0)
5607                         return -ENOSYS;
5608         }
5609         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5610         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5611         IXGBE_WRITE_FLUSH(hw);
5612
5613         return 0;
5614 }
5615
5616 static int
5617 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5618                         struct rte_eth_ethertype_filter *filter)
5619 {
5620         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5621         struct ixgbe_filter_info *filter_info =
5622                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5623         uint32_t etqf, etqs;
5624         int ret;
5625
5626         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5627         if (ret < 0) {
5628                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5629                             filter->ether_type);
5630                 return -ENOENT;
5631         }
5632
5633         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5634         if (etqf & IXGBE_ETQF_FILTER_EN) {
5635                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5636                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5637                 filter->flags = 0;
5638                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5639                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5640                 return 0;
5641         }
5642         return -ENOENT;
5643 }
5644
5645 /*
5646  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5647  * @dev: pointer to rte_eth_dev structure
5648  * @filter_op:operation will be taken.
5649  * @arg: a pointer to specific structure corresponding to the filter_op
5650  */
5651 static int
5652 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5653                                 enum rte_filter_op filter_op,
5654                                 void *arg)
5655 {
5656         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5657         int ret;
5658
5659         MAC_TYPE_FILTER_SUP(hw->mac.type);
5660
5661         if (filter_op == RTE_ETH_FILTER_NOP)
5662                 return 0;
5663
5664         if (arg == NULL) {
5665                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5666                             filter_op);
5667                 return -EINVAL;
5668         }
5669
5670         switch (filter_op) {
5671         case RTE_ETH_FILTER_ADD:
5672                 ret = ixgbe_add_del_ethertype_filter(dev,
5673                         (struct rte_eth_ethertype_filter *)arg,
5674                         TRUE);
5675                 break;
5676         case RTE_ETH_FILTER_DELETE:
5677                 ret = ixgbe_add_del_ethertype_filter(dev,
5678                         (struct rte_eth_ethertype_filter *)arg,
5679                         FALSE);
5680                 break;
5681         case RTE_ETH_FILTER_GET:
5682                 ret = ixgbe_get_ethertype_filter(dev,
5683                         (struct rte_eth_ethertype_filter *)arg);
5684                 break;
5685         default:
5686                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5687                 ret = -EINVAL;
5688                 break;
5689         }
5690         return ret;
5691 }
5692
5693 static int
5694 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5695                      enum rte_filter_type filter_type,
5696                      enum rte_filter_op filter_op,
5697                      void *arg)
5698 {
5699         int ret = -EINVAL;
5700
5701         switch (filter_type) {
5702         case RTE_ETH_FILTER_NTUPLE:
5703                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5704                 break;
5705         case RTE_ETH_FILTER_ETHERTYPE:
5706                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5707                 break;
5708         case RTE_ETH_FILTER_SYN:
5709                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5710                 break;
5711         case RTE_ETH_FILTER_FDIR:
5712                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5713                 break;
5714         case RTE_ETH_FILTER_L2_TUNNEL:
5715                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5716                 break;
5717         default:
5718                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5719                                                         filter_type);
5720                 break;
5721         }
5722
5723         return ret;
5724 }
5725
5726 static u8 *
5727 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5728                         u8 **mc_addr_ptr, u32 *vmdq)
5729 {
5730         u8 *mc_addr;
5731
5732         *vmdq = 0;
5733         mc_addr = *mc_addr_ptr;
5734         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5735         return mc_addr;
5736 }
5737
5738 static int
5739 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5740                           struct ether_addr *mc_addr_set,
5741                           uint32_t nb_mc_addr)
5742 {
5743         struct ixgbe_hw *hw;
5744         u8 *mc_addr_list;
5745
5746         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5747         mc_addr_list = (u8 *)mc_addr_set;
5748         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5749                                          ixgbe_dev_addr_list_itr, TRUE);
5750 }
5751
5752 static uint64_t
5753 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5754 {
5755         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5756         uint64_t systime_cycles;
5757
5758         switch (hw->mac.type) {
5759         case ixgbe_mac_X550:
5760                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5761                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5762                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5763                                 * NSEC_PER_SEC;
5764                 break;
5765         default:
5766                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5767                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5768                                 << 32;
5769         }
5770
5771         return systime_cycles;
5772 }
5773
5774 static uint64_t
5775 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5776 {
5777         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5778         uint64_t rx_tstamp_cycles;
5779
5780         switch (hw->mac.type) {
5781         case ixgbe_mac_X550:
5782                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5783                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5784                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5785                                 * NSEC_PER_SEC;
5786                 break;
5787         default:
5788                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5789                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5790                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5791                                 << 32;
5792         }
5793
5794         return rx_tstamp_cycles;
5795 }
5796
5797 static uint64_t
5798 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5799 {
5800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5801         uint64_t tx_tstamp_cycles;
5802
5803         switch (hw->mac.type) {
5804         case ixgbe_mac_X550:
5805                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5806                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5807                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5808                                 * NSEC_PER_SEC;
5809                 break;
5810         default:
5811                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5812                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5813                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5814                                 << 32;
5815         }
5816
5817         return tx_tstamp_cycles;
5818 }
5819
5820 static void
5821 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5822 {
5823         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5824         struct ixgbe_adapter *adapter =
5825                 (struct ixgbe_adapter *)dev->data->dev_private;
5826         struct rte_eth_link link;
5827         uint32_t incval = 0;
5828         uint32_t shift = 0;
5829
5830         /* Get current link speed. */
5831         memset(&link, 0, sizeof(link));
5832         ixgbe_dev_link_update(dev, 1);
5833         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5834
5835         switch (link.link_speed) {
5836         case ETH_LINK_SPEED_100:
5837                 incval = IXGBE_INCVAL_100;
5838                 shift = IXGBE_INCVAL_SHIFT_100;
5839                 break;
5840         case ETH_LINK_SPEED_1000:
5841                 incval = IXGBE_INCVAL_1GB;
5842                 shift = IXGBE_INCVAL_SHIFT_1GB;
5843                 break;
5844         case ETH_LINK_SPEED_10000:
5845         default:
5846                 incval = IXGBE_INCVAL_10GB;
5847                 shift = IXGBE_INCVAL_SHIFT_10GB;
5848                 break;
5849         }
5850
5851         switch (hw->mac.type) {
5852         case ixgbe_mac_X550:
5853                 /* Independent of link speed. */
5854                 incval = 1;
5855                 /* Cycles read will be interpreted as ns. */
5856                 shift = 0;
5857                 /* Fall-through */
5858         case ixgbe_mac_X540:
5859                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5860                 break;
5861         case ixgbe_mac_82599EB:
5862                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5863                 shift -= IXGBE_INCVAL_SHIFT_82599;
5864                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5865                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5866                 break;
5867         default:
5868                 /* Not supported. */
5869                 return;
5870         }
5871
5872         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5873         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5874         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5875
5876         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5877         adapter->systime_tc.cc_shift = shift;
5878         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5879
5880         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5881         adapter->rx_tstamp_tc.cc_shift = shift;
5882         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5883
5884         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5885         adapter->tx_tstamp_tc.cc_shift = shift;
5886         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5887 }
5888
5889 static int
5890 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5891 {
5892         struct ixgbe_adapter *adapter =
5893                         (struct ixgbe_adapter *)dev->data->dev_private;
5894
5895         adapter->systime_tc.nsec += delta;
5896         adapter->rx_tstamp_tc.nsec += delta;
5897         adapter->tx_tstamp_tc.nsec += delta;
5898
5899         return 0;
5900 }
5901
5902 static int
5903 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5904 {
5905         uint64_t ns;
5906         struct ixgbe_adapter *adapter =
5907                         (struct ixgbe_adapter *)dev->data->dev_private;
5908
5909         ns = rte_timespec_to_ns(ts);
5910         /* Set the timecounters to a new value. */
5911         adapter->systime_tc.nsec = ns;
5912         adapter->rx_tstamp_tc.nsec = ns;
5913         adapter->tx_tstamp_tc.nsec = ns;
5914
5915         return 0;
5916 }
5917
5918 static int
5919 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5920 {
5921         uint64_t ns, systime_cycles;
5922         struct ixgbe_adapter *adapter =
5923                         (struct ixgbe_adapter *)dev->data->dev_private;
5924
5925         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5926         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5927         *ts = rte_ns_to_timespec(ns);
5928
5929         return 0;
5930 }
5931
5932 static int
5933 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5934 {
5935         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5936         uint32_t tsync_ctl;
5937         uint32_t tsauxc;
5938
5939         /* Stop the timesync system time. */
5940         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5941         /* Reset the timesync system time value. */
5942         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5943         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5944
5945         /* Enable system time for platforms where it isn't on by default. */
5946         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5947         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5948         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5949
5950         ixgbe_start_timecounters(dev);
5951
5952         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5953         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5954                         (ETHER_TYPE_1588 |
5955                          IXGBE_ETQF_FILTER_EN |
5956                          IXGBE_ETQF_1588));
5957
5958         /* Enable timestamping of received PTP packets. */
5959         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5960         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5961         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5962
5963         /* Enable timestamping of transmitted PTP packets. */
5964         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5965         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5966         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5967
5968         IXGBE_WRITE_FLUSH(hw);
5969
5970         return 0;
5971 }
5972
5973 static int
5974 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5975 {
5976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5977         uint32_t tsync_ctl;
5978
5979         /* Disable timestamping of transmitted PTP packets. */
5980         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5981         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5982         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5983
5984         /* Disable timestamping of received PTP packets. */
5985         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5986         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5987         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5988
5989         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5990         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5991
5992         /* Stop incrementating the System Time registers. */
5993         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5994
5995         return 0;
5996 }
5997
5998 static int
5999 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6000                                  struct timespec *timestamp,
6001                                  uint32_t flags __rte_unused)
6002 {
6003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6004         struct ixgbe_adapter *adapter =
6005                 (struct ixgbe_adapter *)dev->data->dev_private;
6006         uint32_t tsync_rxctl;
6007         uint64_t rx_tstamp_cycles;
6008         uint64_t ns;
6009
6010         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6011         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6012                 return -EINVAL;
6013
6014         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6015         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6016         *timestamp = rte_ns_to_timespec(ns);
6017
6018         return  0;
6019 }
6020
6021 static int
6022 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6023                                  struct timespec *timestamp)
6024 {
6025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6026         struct ixgbe_adapter *adapter =
6027                 (struct ixgbe_adapter *)dev->data->dev_private;
6028         uint32_t tsync_txctl;
6029         uint64_t tx_tstamp_cycles;
6030         uint64_t ns;
6031
6032         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6033         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6034                 return -EINVAL;
6035
6036         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6037         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6038         *timestamp = rte_ns_to_timespec(ns);
6039
6040         return 0;
6041 }
6042
6043 static int
6044 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6045 {
6046         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6047         int count = 0;
6048         int g_ind = 0;
6049         const struct reg_info *reg_group;
6050         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6051                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6052
6053         while ((reg_group = reg_set[g_ind++]))
6054                 count += ixgbe_regs_group_count(reg_group);
6055
6056         return count;
6057 }
6058
6059 static int
6060 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6061 {
6062         int count = 0;
6063         int g_ind = 0;
6064         const struct reg_info *reg_group;
6065
6066         while ((reg_group = ixgbevf_regs[g_ind++]))
6067                 count += ixgbe_regs_group_count(reg_group);
6068
6069         return count;
6070 }
6071
6072 static int
6073 ixgbe_get_regs(struct rte_eth_dev *dev,
6074               struct rte_dev_reg_info *regs)
6075 {
6076         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6077         uint32_t *data = regs->data;
6078         int g_ind = 0;
6079         int count = 0;
6080         const struct reg_info *reg_group;
6081         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6082                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6083
6084         /* Support only full register dump */
6085         if ((regs->length == 0) ||
6086             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6087                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6088                         hw->device_id;
6089                 while ((reg_group = reg_set[g_ind++]))
6090                         count += ixgbe_read_regs_group(dev, &data[count],
6091                                 reg_group);
6092                 return 0;
6093         }
6094
6095         return -ENOTSUP;
6096 }
6097
6098 static int
6099 ixgbevf_get_regs(struct rte_eth_dev *dev,
6100                 struct rte_dev_reg_info *regs)
6101 {
6102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6103         uint32_t *data = regs->data;
6104         int g_ind = 0;
6105         int count = 0;
6106         const struct reg_info *reg_group;
6107
6108         /* Support only full register dump */
6109         if ((regs->length == 0) ||
6110             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6111                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6112                         hw->device_id;
6113                 while ((reg_group = ixgbevf_regs[g_ind++]))
6114                         count += ixgbe_read_regs_group(dev, &data[count],
6115                                                       reg_group);
6116                 return 0;
6117         }
6118
6119         return -ENOTSUP;
6120 }
6121
6122 static int
6123 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6124 {
6125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6126
6127         /* Return unit is byte count */
6128         return hw->eeprom.word_size * 2;
6129 }
6130
6131 static int
6132 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6133                 struct rte_dev_eeprom_info *in_eeprom)
6134 {
6135         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6136         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6137         uint16_t *data = in_eeprom->data;
6138         int first, length;
6139
6140         first = in_eeprom->offset >> 1;
6141         length = in_eeprom->length >> 1;
6142         if ((first > hw->eeprom.word_size) ||
6143             ((first + length) > hw->eeprom.word_size))
6144                 return -EINVAL;
6145
6146         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6147
6148         return eeprom->ops.read_buffer(hw, first, length, data);
6149 }
6150
6151 static int
6152 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6153                 struct rte_dev_eeprom_info *in_eeprom)
6154 {
6155         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6156         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6157         uint16_t *data = in_eeprom->data;
6158         int first, length;
6159
6160         first = in_eeprom->offset >> 1;
6161         length = in_eeprom->length >> 1;
6162         if ((first > hw->eeprom.word_size) ||
6163             ((first + length) > hw->eeprom.word_size))
6164                 return -EINVAL;
6165
6166         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6167
6168         return eeprom->ops.write_buffer(hw,  first, length, data);
6169 }
6170
6171 uint16_t
6172 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6173         switch (mac_type) {
6174         case ixgbe_mac_X550:
6175         case ixgbe_mac_X550EM_x:
6176         case ixgbe_mac_X550EM_a:
6177                 return ETH_RSS_RETA_SIZE_512;
6178         case ixgbe_mac_X550_vf:
6179         case ixgbe_mac_X550EM_x_vf:
6180         case ixgbe_mac_X550EM_a_vf:
6181                 return ETH_RSS_RETA_SIZE_64;
6182         default:
6183                 return ETH_RSS_RETA_SIZE_128;
6184         }
6185 }
6186
6187 uint32_t
6188 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6189         switch (mac_type) {
6190         case ixgbe_mac_X550:
6191         case ixgbe_mac_X550EM_x:
6192         case ixgbe_mac_X550EM_a:
6193                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6194                         return IXGBE_RETA(reta_idx >> 2);
6195                 else
6196                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6197         case ixgbe_mac_X550_vf:
6198         case ixgbe_mac_X550EM_x_vf:
6199         case ixgbe_mac_X550EM_a_vf:
6200                 return IXGBE_VFRETA(reta_idx >> 2);
6201         default:
6202                 return IXGBE_RETA(reta_idx >> 2);
6203         }
6204 }
6205
6206 uint32_t
6207 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6208         switch (mac_type) {
6209         case ixgbe_mac_X550_vf:
6210         case ixgbe_mac_X550EM_x_vf:
6211         case ixgbe_mac_X550EM_a_vf:
6212                 return IXGBE_VFMRQC;
6213         default:
6214                 return IXGBE_MRQC;
6215         }
6216 }
6217
6218 uint32_t
6219 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6220         switch (mac_type) {
6221         case ixgbe_mac_X550_vf:
6222         case ixgbe_mac_X550EM_x_vf:
6223         case ixgbe_mac_X550EM_a_vf:
6224                 return IXGBE_VFRSSRK(i);
6225         default:
6226                 return IXGBE_RSSRK(i);
6227         }
6228 }
6229
6230 bool
6231 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6232         switch (mac_type) {
6233         case ixgbe_mac_82599_vf:
6234         case ixgbe_mac_X540_vf:
6235                 return 0;
6236         default:
6237                 return 1;
6238         }
6239 }
6240
6241 static int
6242 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6243                         struct rte_eth_dcb_info *dcb_info)
6244 {
6245         struct ixgbe_dcb_config *dcb_config =
6246                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6247         struct ixgbe_dcb_tc_config *tc;
6248         uint8_t i, j;
6249
6250         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6251                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6252         else
6253                 dcb_info->nb_tcs = 1;
6254
6255         if (dcb_config->vt_mode) { /* vt is enabled*/
6256                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6257                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6258                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6259                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6260                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6261                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6262                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6263                                                 i * dcb_info->nb_tcs + j;
6264                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6265                                 dcb_info->tc_queue.tc_txq[i][j].base =
6266                                                 i * dcb_info->nb_tcs + j;
6267                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6268                         }
6269                 }
6270         } else { /* vt is disabled*/
6271                 struct rte_eth_dcb_rx_conf *rx_conf =
6272                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6273                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6274                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6275                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6276                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6277                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6278                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6279                         }
6280                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6281                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6282                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6283                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6284                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6285                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6286                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6287                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6288                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6289                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6290                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6291                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6292                         }
6293                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6294                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6295                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6296                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6297                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6298                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6299                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6300                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6301                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6302                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6303                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6304                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6305                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6306                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6307                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6308                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6309                 }
6310         }
6311         for (i = 0; i < dcb_info->nb_tcs; i++) {
6312                 tc = &dcb_config->tc_config[i];
6313                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6314         }
6315         return 0;
6316 }
6317
6318 /* Update e-tag ether type */
6319 static int
6320 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6321                             uint16_t ether_type)
6322 {
6323         uint32_t etag_etype;
6324
6325         if (hw->mac.type != ixgbe_mac_X550 &&
6326             hw->mac.type != ixgbe_mac_X550EM_x) {
6327                 return -ENOTSUP;
6328         }
6329
6330         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6331         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6332         etag_etype |= ether_type;
6333         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6334         IXGBE_WRITE_FLUSH(hw);
6335
6336         return 0;
6337 }
6338
6339 /* Config l2 tunnel ether type */
6340 static int
6341 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6342                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6343 {
6344         int ret = 0;
6345         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6346
6347         if (l2_tunnel == NULL)
6348                 return -EINVAL;
6349
6350         switch (l2_tunnel->l2_tunnel_type) {
6351         case RTE_L2_TUNNEL_TYPE_E_TAG:
6352                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6353                 break;
6354         default:
6355                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6356                 ret = -EINVAL;
6357                 break;
6358         }
6359
6360         return ret;
6361 }
6362
6363 /* Enable e-tag tunnel */
6364 static int
6365 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6366 {
6367         uint32_t etag_etype;
6368
6369         if (hw->mac.type != ixgbe_mac_X550 &&
6370             hw->mac.type != ixgbe_mac_X550EM_x) {
6371                 return -ENOTSUP;
6372         }
6373
6374         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6375         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6376         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6377         IXGBE_WRITE_FLUSH(hw);
6378
6379         return 0;
6380 }
6381
6382 /* Enable l2 tunnel */
6383 static int
6384 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6385                            enum rte_eth_tunnel_type l2_tunnel_type)
6386 {
6387         int ret = 0;
6388         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6389
6390         switch (l2_tunnel_type) {
6391         case RTE_L2_TUNNEL_TYPE_E_TAG:
6392                 ret = ixgbe_e_tag_enable(hw);
6393                 break;
6394         default:
6395                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6396                 ret = -EINVAL;
6397                 break;
6398         }
6399
6400         return ret;
6401 }
6402
6403 /* Disable e-tag tunnel */
6404 static int
6405 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6406 {
6407         uint32_t etag_etype;
6408
6409         if (hw->mac.type != ixgbe_mac_X550 &&
6410             hw->mac.type != ixgbe_mac_X550EM_x) {
6411                 return -ENOTSUP;
6412         }
6413
6414         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6415         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6416         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6417         IXGBE_WRITE_FLUSH(hw);
6418
6419         return 0;
6420 }
6421
6422 /* Disable l2 tunnel */
6423 static int
6424 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6425                             enum rte_eth_tunnel_type l2_tunnel_type)
6426 {
6427         int ret = 0;
6428         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6429
6430         switch (l2_tunnel_type) {
6431         case RTE_L2_TUNNEL_TYPE_E_TAG:
6432                 ret = ixgbe_e_tag_disable(hw);
6433                 break;
6434         default:
6435                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6436                 ret = -EINVAL;
6437                 break;
6438         }
6439
6440         return ret;
6441 }
6442
6443 static int
6444 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6445                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6446 {
6447         int ret = 0;
6448         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6449         uint32_t i, rar_entries;
6450         uint32_t rar_low, rar_high;
6451
6452         if (hw->mac.type != ixgbe_mac_X550 &&
6453             hw->mac.type != ixgbe_mac_X550EM_x) {
6454                 return -ENOTSUP;
6455         }
6456
6457         rar_entries = ixgbe_get_num_rx_addrs(hw);
6458
6459         for (i = 1; i < rar_entries; i++) {
6460                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6461                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6462                 if ((rar_high & IXGBE_RAH_AV) &&
6463                     (rar_high & IXGBE_RAH_ADTYPE) &&
6464                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6465                      l2_tunnel->tunnel_id)) {
6466                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6467                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6468
6469                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6470
6471                         return ret;
6472                 }
6473         }
6474
6475         return ret;
6476 }
6477
6478 static int
6479 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6480                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6481 {
6482         int ret = 0;
6483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6484         uint32_t i, rar_entries;
6485         uint32_t rar_low, rar_high;
6486
6487         if (hw->mac.type != ixgbe_mac_X550 &&
6488             hw->mac.type != ixgbe_mac_X550EM_x) {
6489                 return -ENOTSUP;
6490         }
6491
6492         /* One entry for one tunnel. Try to remove potential existing entry. */
6493         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6494
6495         rar_entries = ixgbe_get_num_rx_addrs(hw);
6496
6497         for (i = 1; i < rar_entries; i++) {
6498                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6499                 if (rar_high & IXGBE_RAH_AV) {
6500                         continue;
6501                 } else {
6502                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6503                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6504                         rar_low = l2_tunnel->tunnel_id;
6505
6506                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6507                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6508
6509                         return ret;
6510                 }
6511         }
6512
6513         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6514                      " Please remove a rule before adding a new one.");
6515         return -EINVAL;
6516 }
6517
6518 /* Add l2 tunnel filter */
6519 static int
6520 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6521                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6522 {
6523         int ret = 0;
6524
6525         switch (l2_tunnel->l2_tunnel_type) {
6526         case RTE_L2_TUNNEL_TYPE_E_TAG:
6527                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6528                 break;
6529         default:
6530                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6531                 ret = -EINVAL;
6532                 break;
6533         }
6534
6535         return ret;
6536 }
6537
6538 /* Delete l2 tunnel filter */
6539 static int
6540 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6541                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6542 {
6543         int ret = 0;
6544
6545         switch (l2_tunnel->l2_tunnel_type) {
6546         case RTE_L2_TUNNEL_TYPE_E_TAG:
6547                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6548                 break;
6549         default:
6550                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6551                 ret = -EINVAL;
6552                 break;
6553         }
6554
6555         return ret;
6556 }
6557
6558 /**
6559  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6560  * @dev: pointer to rte_eth_dev structure
6561  * @filter_op:operation will be taken.
6562  * @arg: a pointer to specific structure corresponding to the filter_op
6563  */
6564 static int
6565 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6566                                   enum rte_filter_op filter_op,
6567                                   void *arg)
6568 {
6569         int ret = 0;
6570
6571         if (filter_op == RTE_ETH_FILTER_NOP)
6572                 return 0;
6573
6574         if (arg == NULL) {
6575                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6576                             filter_op);
6577                 return -EINVAL;
6578         }
6579
6580         switch (filter_op) {
6581         case RTE_ETH_FILTER_ADD:
6582                 ret = ixgbe_dev_l2_tunnel_filter_add
6583                         (dev,
6584                          (struct rte_eth_l2_tunnel_conf *)arg);
6585                 break;
6586         case RTE_ETH_FILTER_DELETE:
6587                 ret = ixgbe_dev_l2_tunnel_filter_del
6588                         (dev,
6589                          (struct rte_eth_l2_tunnel_conf *)arg);
6590                 break;
6591         default:
6592                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6593                 ret = -EINVAL;
6594                 break;
6595         }
6596         return ret;
6597 }
6598
6599 static int
6600 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6601 {
6602         int ret = 0;
6603         uint32_t ctrl;
6604         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6605
6606         if (hw->mac.type != ixgbe_mac_X550 &&
6607             hw->mac.type != ixgbe_mac_X550EM_x) {
6608                 return -ENOTSUP;
6609         }
6610
6611         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6612         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6613         if (en)
6614                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6615         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6616
6617         return ret;
6618 }
6619
6620 /* Enable l2 tunnel forwarding */
6621 static int
6622 ixgbe_dev_l2_tunnel_forwarding_enable
6623         (struct rte_eth_dev *dev,
6624          enum rte_eth_tunnel_type l2_tunnel_type)
6625 {
6626         int ret = 0;
6627
6628         switch (l2_tunnel_type) {
6629         case RTE_L2_TUNNEL_TYPE_E_TAG:
6630                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6631                 break;
6632         default:
6633                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6634                 ret = -EINVAL;
6635                 break;
6636         }
6637
6638         return ret;
6639 }
6640
6641 /* Disable l2 tunnel forwarding */
6642 static int
6643 ixgbe_dev_l2_tunnel_forwarding_disable
6644         (struct rte_eth_dev *dev,
6645          enum rte_eth_tunnel_type l2_tunnel_type)
6646 {
6647         int ret = 0;
6648
6649         switch (l2_tunnel_type) {
6650         case RTE_L2_TUNNEL_TYPE_E_TAG:
6651                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6652                 break;
6653         default:
6654                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6655                 ret = -EINVAL;
6656                 break;
6657         }
6658
6659         return ret;
6660 }
6661
6662 static int
6663 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6664                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6665                              bool en)
6666 {
6667         int ret = 0;
6668         uint32_t vmtir, vmvir;
6669         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6670
6671         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6672                 PMD_DRV_LOG(ERR,
6673                             "VF id %u should be less than %u",
6674                             l2_tunnel->vf_id,
6675                             dev->pci_dev->max_vfs);
6676                 return -EINVAL;
6677         }
6678
6679         if (hw->mac.type != ixgbe_mac_X550 &&
6680             hw->mac.type != ixgbe_mac_X550EM_x) {
6681                 return -ENOTSUP;
6682         }
6683
6684         if (en)
6685                 vmtir = l2_tunnel->tunnel_id;
6686         else
6687                 vmtir = 0;
6688
6689         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6690
6691         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6692         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6693         if (en)
6694                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6695         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6696
6697         return ret;
6698 }
6699
6700 /* Enable l2 tunnel tag insertion */
6701 static int
6702 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6703                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6704 {
6705         int ret = 0;
6706
6707         switch (l2_tunnel->l2_tunnel_type) {
6708         case RTE_L2_TUNNEL_TYPE_E_TAG:
6709                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6710                 break;
6711         default:
6712                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6713                 ret = -EINVAL;
6714                 break;
6715         }
6716
6717         return ret;
6718 }
6719
6720 /* Disable l2 tunnel tag insertion */
6721 static int
6722 ixgbe_dev_l2_tunnel_insertion_disable
6723         (struct rte_eth_dev *dev,
6724          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6725 {
6726         int ret = 0;
6727
6728         switch (l2_tunnel->l2_tunnel_type) {
6729         case RTE_L2_TUNNEL_TYPE_E_TAG:
6730                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6731                 break;
6732         default:
6733                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6734                 ret = -EINVAL;
6735                 break;
6736         }
6737
6738         return ret;
6739 }
6740
6741 static int
6742 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6743                              bool en)
6744 {
6745         int ret = 0;
6746         uint32_t qde;
6747         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6748
6749         if (hw->mac.type != ixgbe_mac_X550 &&
6750             hw->mac.type != ixgbe_mac_X550EM_x) {
6751                 return -ENOTSUP;
6752         }
6753
6754         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6755         if (en)
6756                 qde |= IXGBE_QDE_STRIP_TAG;
6757         else
6758                 qde &= ~IXGBE_QDE_STRIP_TAG;
6759         qde &= ~IXGBE_QDE_READ;
6760         qde |= IXGBE_QDE_WRITE;
6761         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6762
6763         return ret;
6764 }
6765
6766 /* Enable l2 tunnel tag stripping */
6767 static int
6768 ixgbe_dev_l2_tunnel_stripping_enable
6769         (struct rte_eth_dev *dev,
6770          enum rte_eth_tunnel_type l2_tunnel_type)
6771 {
6772         int ret = 0;
6773
6774         switch (l2_tunnel_type) {
6775         case RTE_L2_TUNNEL_TYPE_E_TAG:
6776                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6777                 break;
6778         default:
6779                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6780                 ret = -EINVAL;
6781                 break;
6782         }
6783
6784         return ret;
6785 }
6786
6787 /* Disable l2 tunnel tag stripping */
6788 static int
6789 ixgbe_dev_l2_tunnel_stripping_disable
6790         (struct rte_eth_dev *dev,
6791          enum rte_eth_tunnel_type l2_tunnel_type)
6792 {
6793         int ret = 0;
6794
6795         switch (l2_tunnel_type) {
6796         case RTE_L2_TUNNEL_TYPE_E_TAG:
6797                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6798                 break;
6799         default:
6800                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6801                 ret = -EINVAL;
6802                 break;
6803         }
6804
6805         return ret;
6806 }
6807
6808 /* Enable/disable l2 tunnel offload functions */
6809 static int
6810 ixgbe_dev_l2_tunnel_offload_set
6811         (struct rte_eth_dev *dev,
6812          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6813          uint32_t mask,
6814          uint8_t en)
6815 {
6816         int ret = 0;
6817
6818         if (l2_tunnel == NULL)
6819                 return -EINVAL;
6820
6821         ret = -EINVAL;
6822         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6823                 if (en)
6824                         ret = ixgbe_dev_l2_tunnel_enable(
6825                                 dev,
6826                                 l2_tunnel->l2_tunnel_type);
6827                 else
6828                         ret = ixgbe_dev_l2_tunnel_disable(
6829                                 dev,
6830                                 l2_tunnel->l2_tunnel_type);
6831         }
6832
6833         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6834                 if (en)
6835                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6836                                 dev,
6837                                 l2_tunnel);
6838                 else
6839                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6840                                 dev,
6841                                 l2_tunnel);
6842         }
6843
6844         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6845                 if (en)
6846                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6847                                 dev,
6848                                 l2_tunnel->l2_tunnel_type);
6849                 else
6850                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6851                                 dev,
6852                                 l2_tunnel->l2_tunnel_type);
6853         }
6854
6855         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6856                 if (en)
6857                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6858                                 dev,
6859                                 l2_tunnel->l2_tunnel_type);
6860                 else
6861                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6862                                 dev,
6863                                 l2_tunnel->l2_tunnel_type);
6864         }
6865
6866         return ret;
6867 }
6868
6869 static int
6870 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6871                         uint16_t port)
6872 {
6873         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6874         IXGBE_WRITE_FLUSH(hw);
6875
6876         return 0;
6877 }
6878
6879 /* There's only one register for VxLAN UDP port.
6880  * So, we cannot add several ports. Will update it.
6881  */
6882 static int
6883 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6884                      uint16_t port)
6885 {
6886         if (port == 0) {
6887                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6888                 return -EINVAL;
6889         }
6890
6891         return ixgbe_update_vxlan_port(hw, port);
6892 }
6893
6894 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6895  * UDP port, it must have a value.
6896  * So, will reset it to the original value 0.
6897  */
6898 static int
6899 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6900                      uint16_t port)
6901 {
6902         uint16_t cur_port;
6903
6904         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6905
6906         if (cur_port != port) {
6907                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6908                 return -EINVAL;
6909         }
6910
6911         return ixgbe_update_vxlan_port(hw, 0);
6912 }
6913
6914 /* Add UDP tunneling port */
6915 static int
6916 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6917                               struct rte_eth_udp_tunnel *udp_tunnel)
6918 {
6919         int ret = 0;
6920         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6921
6922         if (hw->mac.type != ixgbe_mac_X550 &&
6923             hw->mac.type != ixgbe_mac_X550EM_x) {
6924                 return -ENOTSUP;
6925         }
6926
6927         if (udp_tunnel == NULL)
6928                 return -EINVAL;
6929
6930         switch (udp_tunnel->prot_type) {
6931         case RTE_TUNNEL_TYPE_VXLAN:
6932                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6933                 break;
6934
6935         case RTE_TUNNEL_TYPE_GENEVE:
6936         case RTE_TUNNEL_TYPE_TEREDO:
6937                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6938                 ret = -EINVAL;
6939                 break;
6940
6941         default:
6942                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6943                 ret = -EINVAL;
6944                 break;
6945         }
6946
6947         return ret;
6948 }
6949
6950 /* Remove UDP tunneling port */
6951 static int
6952 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6953                               struct rte_eth_udp_tunnel *udp_tunnel)
6954 {
6955         int ret = 0;
6956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6957
6958         if (hw->mac.type != ixgbe_mac_X550 &&
6959             hw->mac.type != ixgbe_mac_X550EM_x) {
6960                 return -ENOTSUP;
6961         }
6962
6963         if (udp_tunnel == NULL)
6964                 return -EINVAL;
6965
6966         switch (udp_tunnel->prot_type) {
6967         case RTE_TUNNEL_TYPE_VXLAN:
6968                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
6969                 break;
6970         case RTE_TUNNEL_TYPE_GENEVE:
6971         case RTE_TUNNEL_TYPE_TEREDO:
6972                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6973                 ret = -EINVAL;
6974                 break;
6975         default:
6976                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6977                 ret = -EINVAL;
6978                 break;
6979         }
6980
6981         return ret;
6982 }
6983
6984 /* ixgbevf_update_xcast_mode - Update Multicast mode
6985  * @hw: pointer to the HW structure
6986  * @netdev: pointer to net device structure
6987  * @xcast_mode: new multicast mode
6988  *
6989  * Updates the Multicast Mode of VF.
6990  */
6991 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
6992                                      int xcast_mode)
6993 {
6994         struct ixgbe_mbx_info *mbx = &hw->mbx;
6995         u32 msgbuf[2];
6996         s32 err;
6997
6998         switch (hw->api_version) {
6999         case ixgbe_mbox_api_12:
7000                 break;
7001         default:
7002                 return -EOPNOTSUPP;
7003         }
7004
7005         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7006         msgbuf[1] = xcast_mode;
7007
7008         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7009         if (err)
7010                 return err;
7011
7012         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7013         if (err)
7014                 return err;
7015
7016         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7017         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7018                 return -EPERM;
7019
7020         return 0;
7021 }
7022
7023 static void
7024 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7025 {
7026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7027
7028         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7029 }
7030
7031 static void
7032 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7033 {
7034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7035
7036         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7037 }
7038
7039 static struct rte_driver rte_ixgbe_driver = {
7040         .type = PMD_PDEV,
7041         .init = rte_ixgbe_pmd_init,
7042 };
7043
7044 static struct rte_driver rte_ixgbevf_driver = {
7045         .type = PMD_PDEV,
7046         .init = rte_ixgbevf_pmd_init,
7047 };
7048
7049 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7050 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);