drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 enum ixgbevf_xcast_modes {
 158         IXGBEVF_XCAST_MODE_NONE = 0,
 159         IXGBEVF_XCAST_MODE_MULTI,
 160         IXGBEVF_XCAST_MODE_ALLMULTI,
 161 };
 162
 163 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 164 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 165
 166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 197                                  size_t fw_size);
 198 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 199                                struct rte_eth_dev_info *dev_info);
 200 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 201 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 202                                  struct rte_eth_dev_info *dev_info);
 203 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 204
 205 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 206                 uint16_t vlan_id, int on);
 207 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 208                                enum rte_vlan_type vlan_type,
 209                                uint16_t tpid_id);
 210 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 211                 uint16_t queue, bool on);
 212 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 213                 int on);
 214 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 215 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 216 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 217 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 218 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 219
 220 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 222 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 225                                struct rte_eth_fc_conf *fc_conf);
 226 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 227                 struct rte_eth_pfc_conf *pfc_conf);
 228 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 229                         struct rte_eth_rss_reta_entry64 *reta_conf,
 230                         uint16_t reta_size);
 231 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 232                         struct rte_eth_rss_reta_entry64 *reta_conf,
 233                         uint16_t reta_size);
 234 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 240                                       struct rte_intr_handle *handle);
 241 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 242                 void *param);
 243 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 244 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 245                 uint32_t index, uint32_t pool);
 246 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 247 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 248                                            struct ether_addr *mac_addr);
 249 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 250 static int is_ixgbe_pmd(const char *driver_name);
 251
 252 /* For Virtual Function support */
 253 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 254 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 255 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 256 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 257 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 258 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 259 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 260 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 261 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 262                 struct rte_eth_stats *stats);
 263 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 264 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 265                 uint16_t vlan_id, int on);
 266 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 267                 uint16_t queue, int on);
 268 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 269 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 270 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 271                                             uint16_t queue_id);
 272 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 273                                              uint16_t queue_id);
 274 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 275                                  uint8_t queue, uint8_t msix_vector);
 276 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 277 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 298                 uint16_t queue_idx, uint16_t tx_rate);
 299
 300 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 301                                  struct ether_addr *mac_addr,
 302                                  uint32_t index, uint32_t pool);
 303 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 304 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 305                                              struct ether_addr *mac_addr);
 306 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 307                         struct rte_eth_syn_filter *filter,
 308                         bool add);
 309 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 310                         struct rte_eth_syn_filter *filter);
 311 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 312                         enum rte_filter_op filter_op,
 313                         void *arg);
 314 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 315                         struct ixgbe_5tuple_filter *filter);
 316 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 317                         struct ixgbe_5tuple_filter *filter);
 318 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ntuple_filter *filter,
 320                         bool add);
 321 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ntuple_filter *filter);
 326 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ethertype_filter *filter,
 328                         bool add);
 329 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 330                                 enum rte_filter_op filter_op,
 331                                 void *arg);
 332 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 333                         struct rte_eth_ethertype_filter *filter);
 334 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 335                      enum rte_filter_type filter_type,
 336                      enum rte_filter_op filter_op,
 337                      void *arg);
 338 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 339
 340 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 341                                       struct ether_addr *mc_addr_set,
 342                                       uint32_t nb_mc_addr);
 343 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 344                                    struct rte_eth_dcb_info *dcb_info);
 345
 346 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 348                             struct rte_dev_reg_info *regs);
 349 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 350 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 351                                 struct rte_dev_eeprom_info *eeprom);
 352 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 353                                 struct rte_dev_eeprom_info *eeprom);
 354
 355 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 356 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 357                                 struct rte_dev_reg_info *regs);
 358
 359 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 361 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 362                                             struct timespec *timestamp,
 363                                             uint32_t flags);
 364 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 365                                             struct timespec *timestamp);
 366 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 367 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 368                                    struct timespec *timestamp);
 369 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 370                                    const struct timespec *timestamp);
 371 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 372                                           void *param);
 373
 374 static int ixgbe_dev_l2_tunnel_eth_type_conf
 375         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 376 static int ixgbe_dev_l2_tunnel_offload_set
 377         (struct rte_eth_dev *dev,
 378          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 379          uint32_t mask,
 380          uint8_t en);
 381 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 382                                              enum rte_filter_op filter_op,
 383                                              void *arg);
 384
 385 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 386                                          struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 388                                          struct rte_eth_udp_tunnel *udp_tunnel);
 389
 390 /*
 391  * Define VF Stats MACRO for Non "cleared on read" register
 392  */
 393 #define UPDATE_VF_STAT(reg, last, cur)                          \
 394 {                                                               \
 395         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 396         cur += (latest - last) & UINT_MAX;                      \
 397         last = latest;                                          \
 398 }
 399
 400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 401 {                                                                \
 402         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 403         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 404         u64 latest = ((new_msb << 32) | new_lsb);                \
 405         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 406         last = latest;                                           \
 407 }
 408
 409 #define IXGBE_SET_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] |= 1 << bit;\
 413         } while (0)
 414
 415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (h)->bitmap[idx] &= ~(1 << bit);\
 419         } while (0)
 420
 421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 422                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 423                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 424                 (r) = (h)->bitmap[idx] >> bit & 1;\
 425         } while (0)
 426
 427 /*
 428  * The set of PCI devices this driver supports
 429  */
 430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 484 #ifdef RTE_NIC_BYPASS
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 486 #endif
 487         { .vendor_id = 0, /* sentinel */ },
 488 };
 489
 490 /*
 491  * The set of PCI devices this driver supports (for 82599 VF)
 492  */
 493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 504         { .vendor_id = 0, /* sentinel */ },
 505 };
 506
 507 static const struct rte_eth_desc_lim rx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_RXD_ALIGN,
 511 };
 512
 513 static const struct rte_eth_desc_lim tx_desc_lim = {
 514         .nb_max = IXGBE_MAX_RING_DESC,
 515         .nb_min = IXGBE_MIN_RING_DESC,
 516         .nb_align = IXGBE_TXD_ALIGN,
 517         .nb_seg_max = IXGBE_TX_MAX_SEG,
 518         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 519 };
 520
 521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 522         .dev_configure        = ixgbe_dev_configure,
 523         .dev_start            = ixgbe_dev_start,
 524         .dev_stop             = ixgbe_dev_stop,
 525         .dev_set_link_up    = ixgbe_dev_set_link_up,
 526         .dev_set_link_down  = ixgbe_dev_set_link_down,
 527         .dev_close            = ixgbe_dev_close,
 528         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 529         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 530         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 531         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 532         .link_update          = ixgbe_dev_link_update,
 533         .stats_get            = ixgbe_dev_stats_get,
 534         .xstats_get           = ixgbe_dev_xstats_get,
 535         .stats_reset          = ixgbe_dev_stats_reset,
 536         .xstats_reset         = ixgbe_dev_xstats_reset,
 537         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 538         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 539         .fw_version_get       = ixgbe_fw_version_get,
 540         .dev_infos_get        = ixgbe_dev_info_get,
 541         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 542         .mtu_set              = ixgbe_dev_mtu_set,
 543         .vlan_filter_set      = ixgbe_vlan_filter_set,
 544         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 545         .vlan_offload_set     = ixgbe_vlan_offload_set,
 546         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 547         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 548         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 549         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 550         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 551         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 552         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 553         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 554         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 555         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 556         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 557         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 558         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 559         .dev_led_on           = ixgbe_dev_led_on,
 560         .dev_led_off          = ixgbe_dev_led_off,
 561         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 562         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 563         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 564         .mac_addr_add         = ixgbe_add_rar,
 565         .mac_addr_remove      = ixgbe_remove_rar,
 566         .mac_addr_set         = ixgbe_set_default_mac_addr,
 567         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 568         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 569         .mirror_rule_set      = ixgbe_mirror_rule_set,
 570         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 571         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 572         .reta_update          = ixgbe_dev_rss_reta_update,
 573         .reta_query           = ixgbe_dev_rss_reta_query,
 574 #ifdef RTE_NIC_BYPASS
 575         .bypass_init          = ixgbe_bypass_init,
 576         .bypass_state_set     = ixgbe_bypass_state_store,
 577         .bypass_state_show    = ixgbe_bypass_state_show,
 578         .bypass_event_set     = ixgbe_bypass_event_store,
 579         .bypass_event_show    = ixgbe_bypass_event_show,
 580         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 581         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 582         .bypass_ver_show      = ixgbe_bypass_ver_show,
 583         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 584 #endif /* RTE_NIC_BYPASS */
 585         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 586         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 587         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 588         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 589         .rxq_info_get         = ixgbe_rxq_info_get,
 590         .txq_info_get         = ixgbe_txq_info_get,
 591         .timesync_enable      = ixgbe_timesync_enable,
 592         .timesync_disable     = ixgbe_timesync_disable,
 593         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 594         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 595         .get_reg              = ixgbe_get_regs,
 596         .get_eeprom_length    = ixgbe_get_eeprom_length,
 597         .get_eeprom           = ixgbe_get_eeprom,
 598         .set_eeprom           = ixgbe_set_eeprom,
 599         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 600         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 601         .timesync_read_time   = ixgbe_timesync_read_time,
 602         .timesync_write_time  = ixgbe_timesync_write_time,
 603         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 604         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 605         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 606         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 607 };
 608
 609 /*
 610  * dev_ops for virtual function, bare necessities for basic vf
 611  * operation have been implemented
 612  */
 613 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 614         .dev_configure        = ixgbevf_dev_configure,
 615         .dev_start            = ixgbevf_dev_start,
 616         .dev_stop             = ixgbevf_dev_stop,
 617         .link_update          = ixgbe_dev_link_update,
 618         .stats_get            = ixgbevf_dev_stats_get,
 619         .xstats_get           = ixgbevf_dev_xstats_get,
 620         .stats_reset          = ixgbevf_dev_stats_reset,
 621         .xstats_reset         = ixgbevf_dev_stats_reset,
 622         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 623         .dev_close            = ixgbevf_dev_close,
 624         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 625         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 626         .dev_infos_get        = ixgbevf_dev_info_get,
 627         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 628         .mtu_set              = ixgbevf_dev_set_mtu,
 629         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 630         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 631         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 632         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 633         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 634         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 635         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 636         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 637         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 638         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 639         .mac_addr_add         = ixgbevf_add_mac_addr,
 640         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 641         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 642         .rxq_info_get         = ixgbe_rxq_info_get,
 643         .txq_info_get         = ixgbe_txq_info_get,
 644         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 645         .get_reg              = ixgbevf_get_regs,
 646         .reta_update          = ixgbe_dev_rss_reta_update,
 647         .reta_query           = ixgbe_dev_rss_reta_query,
 648         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 649         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 650 };
 651
 652 /* store statistics names and its offset in stats structure */
 653 struct rte_ixgbe_xstats_name_off {
 654         char name[RTE_ETH_XSTATS_NAME_SIZE];
 655         unsigned offset;
 656 };
 657
 658 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 659         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 660         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 661         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 662         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 663         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 664         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 665         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 666         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 667         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 668         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 669         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 670         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 671         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 672         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 673         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 674                 prc1023)},
 675         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 676                 prc1522)},
 677         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 678         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 679         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 680         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 681         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 682         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 683         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 684         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 685         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 686         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 687         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 688         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 689         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 690         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 691         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 692         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 693         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 694                 ptc1023)},
 695         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 696                 ptc1522)},
 697         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 698         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 699         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 700         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 701
 702         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 703                 fdirustat_add)},
 704         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirustat_remove)},
 706         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 707                 fdirfstat_fadd)},
 708         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 709                 fdirfstat_fremove)},
 710         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirmatch)},
 712         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 713                 fdirmiss)},
 714
 715         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 716         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 717         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 718                 fclast)},
 719         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 720         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 721         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 722         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 723         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 724                 fcoe_noddp)},
 725         {"rx_fcoe_no_direct_data_placement_ext_buff",
 726                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 727
 728         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 729                 lxontxc)},
 730         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 731                 lxonrxc)},
 732         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 733                 lxofftxc)},
 734         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 735                 lxoffrxc)},
 736         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 737 };
 738
 739 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 740                            sizeof(rte_ixgbe_stats_strings[0]))
 741
 742 /* MACsec statistics */
 743 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 744         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 745                 out_pkts_untagged)},
 746         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 747                 out_pkts_encrypted)},
 748         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 749                 out_pkts_protected)},
 750         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 751                 out_octets_encrypted)},
 752         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 753                 out_octets_protected)},
 754         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_untagged)},
 756         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_badtag)},
 758         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_nosci)},
 760         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_unknownsci)},
 762         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 763                 in_octets_decrypted)},
 764         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 765                 in_octets_validated)},
 766         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_unchecked)},
 768         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_delayed)},
 770         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_late)},
 772         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_ok)},
 774         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_invalid)},
 776         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_notvalid)},
 778         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_unusedsa)},
 780         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 781                 in_pkts_notusingsa)},
 782 };
 783
 784 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 785                            sizeof(rte_ixgbe_macsec_strings[0]))
 786
 787 /* Per-queue statistics */
 788 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 789         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 790         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 791         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 792         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 793 };
 794
 795 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 796                            sizeof(rte_ixgbe_rxq_strings[0]))
 797 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 798
 799 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 800         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 801         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 802         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 803                 pxon2offc)},
 804 };
 805
 806 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 807                            sizeof(rte_ixgbe_txq_strings[0]))
 808 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 809
 810 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 811         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 812 };
 813
 814 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 815                 sizeof(rte_ixgbevf_stats_strings[0]))
 816
 817 /**
 818  * Atomically reads the link status information from global
 819  * structure rte_eth_dev.
 820  *
 821  * @param dev
 822  *   - Pointer to the structure rte_eth_dev to read from.
 823  *   - Pointer to the buffer to be saved with the link status.
 824  *
 825  * @return
 826  *   - On success, zero.
 827  *   - On failure, negative value.
 828  */
 829 static inline int
 830 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 831                                 struct rte_eth_link *link)
 832 {
 833         struct rte_eth_link *dst = link;
 834         struct rte_eth_link *src = &(dev->data->dev_link);
 835
 836         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 837                                         *(uint64_t *)src) == 0)
 838                 return -1;
 839
 840         return 0;
 841 }
 842
 843 /**
 844  * Atomically writes the link status information into global
 845  * structure rte_eth_dev.
 846  *
 847  * @param dev
 848  *   - Pointer to the structure rte_eth_dev to read from.
 849  *   - Pointer to the buffer to be saved with the link status.
 850  *
 851  * @return
 852  *   - On success, zero.
 853  *   - On failure, negative value.
 854  */
 855 static inline int
 856 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 857                                 struct rte_eth_link *link)
 858 {
 859         struct rte_eth_link *dst = &(dev->data->dev_link);
 860         struct rte_eth_link *src = link;
 861
 862         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 863                                         *(uint64_t *)src) == 0)
 864                 return -1;
 865
 866         return 0;
 867 }
 868
 869 /*
 870  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 871  */
 872 static inline int
 873 ixgbe_is_sfp(struct ixgbe_hw *hw)
 874 {
 875         switch (hw->phy.type) {
 876         case ixgbe_phy_sfp_avago:
 877         case ixgbe_phy_sfp_ftl:
 878         case ixgbe_phy_sfp_intel:
 879         case ixgbe_phy_sfp_unknown:
 880         case ixgbe_phy_sfp_passive_tyco:
 881         case ixgbe_phy_sfp_passive_unknown:
 882                 return 1;
 883         default:
 884                 return 0;
 885         }
 886 }
 887
 888 static inline int32_t
 889 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 890 {
 891         uint32_t ctrl_ext;
 892         int32_t status;
 893
 894         status = ixgbe_reset_hw(hw);
 895
 896         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 897         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 898         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 899         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 900         IXGBE_WRITE_FLUSH(hw);
 901
 902         return status;
 903 }
 904
 905 static inline void
 906 ixgbe_enable_intr(struct rte_eth_dev *dev)
 907 {
 908         struct ixgbe_interrupt *intr =
 909                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 910         struct ixgbe_hw *hw =
 911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 912
 913         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 914         IXGBE_WRITE_FLUSH(hw);
 915 }
 916
 917 /*
 918  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 919  */
 920 static void
 921 ixgbe_disable_intr(struct ixgbe_hw *hw)
 922 {
 923         PMD_INIT_FUNC_TRACE();
 924
 925         if (hw->mac.type == ixgbe_mac_82598EB) {
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 927         } else {
 928                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 930                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 931         }
 932         IXGBE_WRITE_FLUSH(hw);
 933 }
 934
 935 /*
 936  * This function resets queue statistics mapping registers.
 937  * From Niantic datasheet, Initialization of Statistics section:
 938  * "...if software requires the queue counters, the RQSMR and TQSM registers
 939  * must be re-programmed following a device reset.
 940  */
 941 static void
 942 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 943 {
 944         uint32_t i;
 945
 946         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 947                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 948                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 949         }
 950 }
 951
 952
 953 static int
 954 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 955                                   uint16_t queue_id,
 956                                   uint8_t stat_idx,
 957                                   uint8_t is_rx)
 958 {
 959 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 960 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 961 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 962
 963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 964         struct ixgbe_stat_mapping_registers *stat_mappings =
 965                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 966         uint32_t qsmr_mask = 0;
 967         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 968         uint32_t q_map;
 969         uint8_t n, offset;
 970
 971         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 972                 (hw->mac.type != ixgbe_mac_X540) &&
 973                 (hw->mac.type != ixgbe_mac_X550) &&
 974                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 975                 (hw->mac.type != ixgbe_mac_X550EM_a))
 976                 return -ENOSYS;
 977
 978         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 979                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 980                      queue_id, stat_idx);
 981
 982         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 983         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 984                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 985                 return -EIO;
 986         }
 987         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 988
 989         /* Now clear any previous stat_idx set */
 990         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 991         if (!is_rx)
 992                 stat_mappings->tqsm[n] &= ~clearing_mask;
 993         else
 994                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 995
 996         q_map = (uint32_t)stat_idx;
 997         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 998         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 999         if (!is_rx)
1000                 stat_mappings->tqsm[n] |= qsmr_mask;
1001         else
1002                 stat_mappings->rqsmr[n] |= qsmr_mask;
1003
1004         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1005                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1006                      queue_id, stat_idx);
1007         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1008                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1009
1010         /* Now write the mapping in the appropriate register */
1011         if (is_rx) {
1012                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1013                              stat_mappings->rqsmr[n], n);
1014                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1015         } else {
1016                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1017                              stat_mappings->tqsm[n], n);
1018                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1019         }
1020         return 0;
1021 }
1022
1023 static void
1024 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1025 {
1026         struct ixgbe_stat_mapping_registers *stat_mappings =
1027                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1029         int i;
1030
1031         /* write whatever was in stat mapping table to the NIC */
1032         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1033                 /* rx */
1034                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1035
1036                 /* tx */
1037                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1038         }
1039 }
1040
1041 static void
1042 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1043 {
1044         uint8_t i;
1045         struct ixgbe_dcb_tc_config *tc;
1046         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1047
1048         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1049         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1050         for (i = 0; i < dcb_max_tc; i++) {
1051                 tc = &dcb_config->tc_config[i];
1052                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1053                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1054                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1055                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1056                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1057                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1058                 tc->pfc = ixgbe_dcb_pfc_disabled;
1059         }
1060
1061         /* Initialize default user to priority mapping, UPx->TC0 */
1062         tc = &dcb_config->tc_config[0];
1063         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1064         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1065         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1066                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1067                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1068         }
1069         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1070         dcb_config->pfc_mode_enable = false;
1071         dcb_config->vt_mode = true;
1072         dcb_config->round_robin_enable = false;
1073         /* support all DCB capabilities in 82599 */
1074         dcb_config->support.capabilities = 0xFF;
1075
1076         /*we only support 4 Tcs for X540, X550 */
1077         if (hw->mac.type == ixgbe_mac_X540 ||
1078                 hw->mac.type == ixgbe_mac_X550 ||
1079                 hw->mac.type == ixgbe_mac_X550EM_x ||
1080                 hw->mac.type == ixgbe_mac_X550EM_a) {
1081                 dcb_config->num_tcs.pg_tcs = 4;
1082                 dcb_config->num_tcs.pfc_tcs = 4;
1083         }
1084 }
1085
1086 /*
1087  * Ensure that all locks are released before first NVM or PHY access
1088  */
1089 static void
1090 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1091 {
1092         uint16_t mask;
1093
1094         /*
1095          * Phy lock should not fail in this early stage. If this is the case,
1096          * it is due to an improper exit of the application.
1097          * So force the release of the faulty lock. Release of common lock
1098          * is done automatically by swfw_sync function.
1099          */
1100         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1101         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1102                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1103         }
1104         ixgbe_release_swfw_semaphore(hw, mask);
1105
1106         /*
1107          * These ones are more tricky since they are common to all ports; but
1108          * swfw_sync retries last long enough (1s) to be almost sure that if
1109          * lock can not be taken it is due to an improper lock of the
1110          * semaphore.
1111          */
1112         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1113         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1114                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1115         }
1116         ixgbe_release_swfw_semaphore(hw, mask);
1117 }
1118
1119 /*
1120  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1121  * It returns 0 on success.
1122  */
1123 static int
1124 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1125 {
1126         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1127         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1128         struct ixgbe_hw *hw =
1129                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1130         struct ixgbe_vfta *shadow_vfta =
1131                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1132         struct ixgbe_hwstrip *hwstrip =
1133                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1134         struct ixgbe_dcb_config *dcb_config =
1135                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1136         struct ixgbe_filter_info *filter_info =
1137                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1138         uint32_t ctrl_ext;
1139         uint16_t csum;
1140         int diag, i;
1141
1142         PMD_INIT_FUNC_TRACE();
1143
1144         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1145         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1146         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1147         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1148
1149         /*
1150          * For secondary processes, we don't initialise any further as primary
1151          * has already done this work. Only check we don't need a different
1152          * RX and TX function.
1153          */
1154         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1155                 struct ixgbe_tx_queue *txq;
1156                 /* TX queue function in primary, set by last queue initialized
1157                  * Tx queue may not initialized by primary process
1158                  */
1159                 if (eth_dev->data->tx_queues) {
1160                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1161                         ixgbe_set_tx_function(eth_dev, txq);
1162                 } else {
1163                         /* Use default TX function if we get here */
1164                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1165                                      "Using default TX function.");
1166                 }
1167
1168                 ixgbe_set_rx_function(eth_dev);
1169
1170                 return 0;
1171         }
1172
1173         rte_eth_copy_pci_info(eth_dev, pci_dev);
1174         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1175
1176         /* Vendor and Device ID need to be set before init of shared code */
1177         hw->device_id = pci_dev->id.device_id;
1178         hw->vendor_id = pci_dev->id.vendor_id;
1179         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1180         hw->allow_unsupported_sfp = 1;
1181
1182         /* Initialize the shared code (base driver) */
1183 #ifdef RTE_NIC_BYPASS
1184         diag = ixgbe_bypass_init_shared_code(hw);
1185 #else
1186         diag = ixgbe_init_shared_code(hw);
1187 #endif /* RTE_NIC_BYPASS */
1188
1189         if (diag != IXGBE_SUCCESS) {
1190                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1191                 return -EIO;
1192         }
1193
1194         /* pick up the PCI bus settings for reporting later */
1195         ixgbe_get_bus_info(hw);
1196
1197         /* Unlock any pending hardware semaphore */
1198         ixgbe_swfw_lock_reset(hw);
1199
1200         /* Initialize DCB configuration*/
1201         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1202         ixgbe_dcb_init(hw, dcb_config);
1203         /* Get Hardware Flow Control setting */
1204         hw->fc.requested_mode = ixgbe_fc_full;
1205         hw->fc.current_mode = ixgbe_fc_full;
1206         hw->fc.pause_time = IXGBE_FC_PAUSE;
1207         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1208                 hw->fc.low_water[i] = IXGBE_FC_LO;
1209                 hw->fc.high_water[i] = IXGBE_FC_HI;
1210         }
1211         hw->fc.send_xon = 1;
1212
1213         /* Make sure we have a good EEPROM before we read from it */
1214         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1215         if (diag != IXGBE_SUCCESS) {
1216                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1217                 return -EIO;
1218         }
1219
1220 #ifdef RTE_NIC_BYPASS
1221         diag = ixgbe_bypass_init_hw(hw);
1222 #else
1223         diag = ixgbe_init_hw(hw);
1224 #endif /* RTE_NIC_BYPASS */
1225
1226         /*
1227          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1228          * is called too soon after the kernel driver unbinding/binding occurs.
1229          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1230          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1231          * also called. See ixgbe_identify_phy_82599(). The reason for the
1232          * failure is not known, and only occuts when virtualisation features
1233          * are disabled in the bios. A delay of 100ms  was found to be enough by
1234          * trial-and-error, and is doubled to be safe.
1235          */
1236         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1237                 rte_delay_ms(200);
1238                 diag = ixgbe_init_hw(hw);
1239         }
1240
1241         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1242                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1243                              "LOM.  Please be aware there may be issues associated "
1244                              "with your hardware.");
1245                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1246                              "please contact your Intel or hardware representative "
1247                              "who provided you with this hardware.");
1248         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1249                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1250         if (diag) {
1251                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1252                 return -EIO;
1253         }
1254
1255         /* Reset the hw statistics */
1256         ixgbe_dev_stats_reset(eth_dev);
1257
1258         /* disable interrupt */
1259         ixgbe_disable_intr(hw);
1260
1261         /* reset mappings for queue statistics hw counters*/
1262         ixgbe_reset_qstat_mappings(hw);
1263
1264         /* Allocate memory for storing MAC addresses */
1265         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1266                                                hw->mac.num_rar_entries, 0);
1267         if (eth_dev->data->mac_addrs == NULL) {
1268                 PMD_INIT_LOG(ERR,
1269                              "Failed to allocate %u bytes needed to store "
1270                              "MAC addresses",
1271                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1272                 return -ENOMEM;
1273         }
1274         /* Copy the permanent MAC address */
1275         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1276                         &eth_dev->data->mac_addrs[0]);
1277
1278         /* Allocate memory for storing hash filter MAC addresses */
1279         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1280                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1281         if (eth_dev->data->hash_mac_addrs == NULL) {
1282                 PMD_INIT_LOG(ERR,
1283                              "Failed to allocate %d bytes needed to store MAC addresses",
1284                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1285                 return -ENOMEM;
1286         }
1287
1288         /* initialize the vfta */
1289         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1290
1291         /* initialize the hw strip bitmap*/
1292         memset(hwstrip, 0, sizeof(*hwstrip));
1293
1294         /* initialize PF if max_vfs not zero */
1295         ixgbe_pf_host_init(eth_dev);
1296
1297         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1298         /* let hardware know driver is loaded */
1299         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1300         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1301         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1302         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1303         IXGBE_WRITE_FLUSH(hw);
1304
1305         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1306                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1307                              (int) hw->mac.type, (int) hw->phy.type,
1308                              (int) hw->phy.sfp_type);
1309         else
1310                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1311                              (int) hw->mac.type, (int) hw->phy.type);
1312
1313         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1314                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1315                      pci_dev->id.device_id);
1316
1317         rte_intr_callback_register(intr_handle,
1318                                    ixgbe_dev_interrupt_handler, eth_dev);
1319
1320         /* enable uio/vfio intr/eventfd mapping */
1321         rte_intr_enable(intr_handle);
1322
1323         /* enable support intr */
1324         ixgbe_enable_intr(eth_dev);
1325
1326         /* initialize filter info */
1327         memset(filter_info, 0,
1328                sizeof(struct ixgbe_filter_info));
1329
1330         /* initialize 5tuple filter list */
1331         TAILQ_INIT(&filter_info->fivetuple_list);
1332
1333         return 0;
1334 }
1335
1336 static int
1337 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1338 {
1339         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1340         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1341         struct ixgbe_hw *hw;
1342
1343         PMD_INIT_FUNC_TRACE();
1344
1345         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1346                 return -EPERM;
1347
1348         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1349
1350         if (hw->adapter_stopped == 0)
1351                 ixgbe_dev_close(eth_dev);
1352
1353         eth_dev->dev_ops = NULL;
1354         eth_dev->rx_pkt_burst = NULL;
1355         eth_dev->tx_pkt_burst = NULL;
1356
1357         /* Unlock any pending hardware semaphore */
1358         ixgbe_swfw_lock_reset(hw);
1359
1360         /* disable uio intr before callback unregister */
1361         rte_intr_disable(intr_handle);
1362         rte_intr_callback_unregister(intr_handle,
1363                                      ixgbe_dev_interrupt_handler, eth_dev);
1364
1365         /* uninitialize PF if max_vfs not zero */
1366         ixgbe_pf_host_uninit(eth_dev);
1367
1368         rte_free(eth_dev->data->mac_addrs);
1369         eth_dev->data->mac_addrs = NULL;
1370
1371         rte_free(eth_dev->data->hash_mac_addrs);
1372         eth_dev->data->hash_mac_addrs = NULL;
1373
1374         return 0;
1375 }
1376
1377 /*
1378  * Negotiate mailbox API version with the PF.
1379  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1380  * Then we try to negotiate starting with the most recent one.
1381  * If all negotiation attempts fail, then we will proceed with
1382  * the default one (ixgbe_mbox_api_10).
1383  */
1384 static void
1385 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1386 {
1387         int32_t i;
1388
1389         /* start with highest supported, proceed down */
1390         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1391                 ixgbe_mbox_api_12,
1392                 ixgbe_mbox_api_11,
1393                 ixgbe_mbox_api_10,
1394         };
1395
1396         for (i = 0;
1397                         i != RTE_DIM(sup_ver) &&
1398                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1399                         i++)
1400                 ;
1401 }
1402
1403 static void
1404 generate_random_mac_addr(struct ether_addr *mac_addr)
1405 {
1406         uint64_t random;
1407
1408         /* Set Organizationally Unique Identifier (OUI) prefix. */
1409         mac_addr->addr_bytes[0] = 0x00;
1410         mac_addr->addr_bytes[1] = 0x09;
1411         mac_addr->addr_bytes[2] = 0xC0;
1412         /* Force indication of locally assigned MAC address. */
1413         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1414         /* Generate the last 3 bytes of the MAC address with a random number. */
1415         random = rte_rand();
1416         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1417 }
1418
1419 /*
1420  * Virtual Function device init
1421  */
1422 static int
1423 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1424 {
1425         int diag;
1426         uint32_t tc, tcs;
1427         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1428         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1429         struct ixgbe_hw *hw =
1430                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1431         struct ixgbe_vfta *shadow_vfta =
1432                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1433         struct ixgbe_hwstrip *hwstrip =
1434                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1435         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1436
1437         PMD_INIT_FUNC_TRACE();
1438
1439         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1440         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1441         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1442
1443         /* for secondary processes, we don't initialise any further as primary
1444          * has already done this work. Only check we don't need a different
1445          * RX function
1446          */
1447         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1448                 struct ixgbe_tx_queue *txq;
1449                 /* TX queue function in primary, set by last queue initialized
1450                  * Tx queue may not initialized by primary process
1451                  */
1452                 if (eth_dev->data->tx_queues) {
1453                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1454                         ixgbe_set_tx_function(eth_dev, txq);
1455                 } else {
1456                         /* Use default TX function if we get here */
1457                         PMD_INIT_LOG(NOTICE,
1458                                      "No TX queues configured yet. Using default TX function.");
1459                 }
1460
1461                 ixgbe_set_rx_function(eth_dev);
1462
1463                 return 0;
1464         }
1465
1466         rte_eth_copy_pci_info(eth_dev, pci_dev);
1467         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1468
1469         hw->device_id = pci_dev->id.device_id;
1470         hw->vendor_id = pci_dev->id.vendor_id;
1471         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1472
1473         /* initialize the vfta */
1474         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1475
1476         /* initialize the hw strip bitmap*/
1477         memset(hwstrip, 0, sizeof(*hwstrip));
1478
1479         /* Initialize the shared code (base driver) */
1480         diag = ixgbe_init_shared_code(hw);
1481         if (diag != IXGBE_SUCCESS) {
1482                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1483                 return -EIO;
1484         }
1485
1486         /* init_mailbox_params */
1487         hw->mbx.ops.init_params(hw);
1488
1489         /* Reset the hw statistics */
1490         ixgbevf_dev_stats_reset(eth_dev);
1491
1492         /* Disable the interrupts for VF */
1493         ixgbevf_intr_disable(hw);
1494
1495         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1496         diag = hw->mac.ops.reset_hw(hw);
1497
1498         /*
1499          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1500          * the underlying PF driver has not assigned a MAC address to the VF.
1501          * In this case, assign a random MAC address.
1502          */
1503         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1504                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1505                 return diag;
1506         }
1507
1508         /* negotiate mailbox API version to use with the PF. */
1509         ixgbevf_negotiate_api(hw);
1510
1511         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1512         ixgbevf_get_queues(hw, &tcs, &tc);
1513
1514         /* Allocate memory for storing MAC addresses */
1515         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1516                                                hw->mac.num_rar_entries, 0);
1517         if (eth_dev->data->mac_addrs == NULL) {
1518                 PMD_INIT_LOG(ERR,
1519                              "Failed to allocate %u bytes needed to store "
1520                              "MAC addresses",
1521                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1522                 return -ENOMEM;
1523         }
1524
1525         /* Generate a random MAC address, if none was assigned by PF. */
1526         if (is_zero_ether_addr(perm_addr)) {
1527                 generate_random_mac_addr(perm_addr);
1528                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1529                 if (diag) {
1530                         rte_free(eth_dev->data->mac_addrs);
1531                         eth_dev->data->mac_addrs = NULL;
1532                         return diag;
1533                 }
1534                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1535                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1536                              "%02x:%02x:%02x:%02x:%02x:%02x",
1537                              perm_addr->addr_bytes[0],
1538                              perm_addr->addr_bytes[1],
1539                              perm_addr->addr_bytes[2],
1540                              perm_addr->addr_bytes[3],
1541                              perm_addr->addr_bytes[4],
1542                              perm_addr->addr_bytes[5]);
1543         }
1544
1545         /* Copy the permanent MAC address */
1546         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1547
1548         /* reset the hardware with the new settings */
1549         diag = hw->mac.ops.start_hw(hw);
1550         switch (diag) {
1551         case  0:
1552                 break;
1553
1554         default:
1555                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1556                 return -EIO;
1557         }
1558
1559         rte_intr_callback_register(intr_handle,
1560                                    ixgbevf_dev_interrupt_handler, eth_dev);
1561         rte_intr_enable(intr_handle);
1562         ixgbevf_intr_enable(hw);
1563
1564         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1565                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1566                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1567
1568         return 0;
1569 }
1570
1571 /* Virtual Function device uninit */
1572
1573 static int
1574 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1575 {
1576         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1577         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1578         struct ixgbe_hw *hw;
1579
1580         PMD_INIT_FUNC_TRACE();
1581
1582         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1583                 return -EPERM;
1584
1585         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1586
1587         if (hw->adapter_stopped == 0)
1588                 ixgbevf_dev_close(eth_dev);
1589
1590         eth_dev->dev_ops = NULL;
1591         eth_dev->rx_pkt_burst = NULL;
1592         eth_dev->tx_pkt_burst = NULL;
1593
1594         /* Disable the interrupts for VF */
1595         ixgbevf_intr_disable(hw);
1596
1597         rte_free(eth_dev->data->mac_addrs);
1598         eth_dev->data->mac_addrs = NULL;
1599
1600         rte_intr_disable(intr_handle);
1601         rte_intr_callback_unregister(intr_handle,
1602                                      ixgbevf_dev_interrupt_handler, eth_dev);
1603
1604         return 0;
1605 }
1606
1607 static struct eth_driver rte_ixgbe_pmd = {
1608         .pci_drv = {
1609                 .id_table = pci_id_ixgbe_map,
1610                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1611                 .probe = rte_eth_dev_pci_probe,
1612                 .remove = rte_eth_dev_pci_remove,
1613         },
1614         .eth_dev_init = eth_ixgbe_dev_init,
1615         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1616         .dev_private_size = sizeof(struct ixgbe_adapter),
1617 };
1618
1619 /*
1620  * virtual function driver struct
1621  */
1622 static struct eth_driver rte_ixgbevf_pmd = {
1623         .pci_drv = {
1624                 .id_table = pci_id_ixgbevf_map,
1625                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1626                 .probe = rte_eth_dev_pci_probe,
1627                 .remove = rte_eth_dev_pci_remove,
1628         },
1629         .eth_dev_init = eth_ixgbevf_dev_init,
1630         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1631         .dev_private_size = sizeof(struct ixgbe_adapter),
1632 };
1633
1634 static int
1635 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1636 {
1637         struct ixgbe_hw *hw =
1638                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1639         struct ixgbe_vfta *shadow_vfta =
1640                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1641         uint32_t vfta;
1642         uint32_t vid_idx;
1643         uint32_t vid_bit;
1644
1645         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1646         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1647         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1648         if (on)
1649                 vfta |= vid_bit;
1650         else
1651                 vfta &= ~vid_bit;
1652         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1653
1654         /* update local VFTA copy */
1655         shadow_vfta->vfta[vid_idx] = vfta;
1656
1657         return 0;
1658 }
1659
1660 static void
1661 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1662 {
1663         if (on)
1664                 ixgbe_vlan_hw_strip_enable(dev, queue);
1665         else
1666                 ixgbe_vlan_hw_strip_disable(dev, queue);
1667 }
1668
1669 static int
1670 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1671                     enum rte_vlan_type vlan_type,
1672                     uint16_t tpid)
1673 {
1674         struct ixgbe_hw *hw =
1675                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1676         int ret = 0;
1677         uint32_t reg;
1678         uint32_t qinq;
1679
1680         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1681         qinq &= IXGBE_DMATXCTL_GDV;
1682
1683         switch (vlan_type) {
1684         case ETH_VLAN_TYPE_INNER:
1685                 if (qinq) {
1686                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1687                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1688                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1689                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1690                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1691                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1692                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1693                 } else {
1694                         ret = -ENOTSUP;
1695                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1696                                     " by single VLAN");
1697                 }
1698                 break;
1699         case ETH_VLAN_TYPE_OUTER:
1700                 if (qinq) {
1701                         /* Only the high 16-bits is valid */
1702                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1703                                         IXGBE_EXVET_VET_EXT_SHIFT);
1704                 } else {
1705                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1706                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1707                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1708                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1709                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1710                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1711                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1712                 }
1713
1714                 break;
1715         default:
1716                 ret = -EINVAL;
1717                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1718                 break;
1719         }
1720
1721         return ret;
1722 }
1723
1724 void
1725 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1726 {
1727         struct ixgbe_hw *hw =
1728                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729         uint32_t vlnctrl;
1730
1731         PMD_INIT_FUNC_TRACE();
1732
1733         /* Filter Table Disable */
1734         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1735         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1736
1737         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1738 }
1739
1740 void
1741 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1742 {
1743         struct ixgbe_hw *hw =
1744                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1745         struct ixgbe_vfta *shadow_vfta =
1746                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1747         uint32_t vlnctrl;
1748         uint16_t i;
1749
1750         PMD_INIT_FUNC_TRACE();
1751
1752         /* Filter Table Enable */
1753         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1754         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1755         vlnctrl |= IXGBE_VLNCTRL_VFE;
1756
1757         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1758
1759         /* write whatever is in local vfta copy */
1760         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1761                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1762 }
1763
1764 static void
1765 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1766 {
1767         struct ixgbe_hwstrip *hwstrip =
1768                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1769         struct ixgbe_rx_queue *rxq;
1770
1771         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1772                 return;
1773
1774         if (on)
1775                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1776         else
1777                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1778
1779         if (queue >= dev->data->nb_rx_queues)
1780                 return;
1781
1782         rxq = dev->data->rx_queues[queue];
1783
1784         if (on)
1785                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1786         else
1787                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1788 }
1789
1790 static void
1791 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1792 {
1793         struct ixgbe_hw *hw =
1794                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795         uint32_t ctrl;
1796
1797         PMD_INIT_FUNC_TRACE();
1798
1799         if (hw->mac.type == ixgbe_mac_82598EB) {
1800                 /* No queue level support */
1801                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1802                 return;
1803         }
1804
1805         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1806         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1807         ctrl &= ~IXGBE_RXDCTL_VME;
1808         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1809
1810         /* record those setting for HW strip per queue */
1811         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1812 }
1813
1814 static void
1815 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1816 {
1817         struct ixgbe_hw *hw =
1818                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1819         uint32_t ctrl;
1820
1821         PMD_INIT_FUNC_TRACE();
1822
1823         if (hw->mac.type == ixgbe_mac_82598EB) {
1824                 /* No queue level supported */
1825                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1826                 return;
1827         }
1828
1829         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1830         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1831         ctrl |= IXGBE_RXDCTL_VME;
1832         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1833
1834         /* record those setting for HW strip per queue */
1835         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1836 }
1837
1838 void
1839 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1840 {
1841         struct ixgbe_hw *hw =
1842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843         uint32_t ctrl;
1844         uint16_t i;
1845         struct ixgbe_rx_queue *rxq;
1846
1847         PMD_INIT_FUNC_TRACE();
1848
1849         if (hw->mac.type == ixgbe_mac_82598EB) {
1850                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1851                 ctrl &= ~IXGBE_VLNCTRL_VME;
1852                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1853         } else {
1854                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1855                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1856                         rxq = dev->data->rx_queues[i];
1857                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1858                         ctrl &= ~IXGBE_RXDCTL_VME;
1859                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1860
1861                         /* record those setting for HW strip per queue */
1862                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1863                 }
1864         }
1865 }
1866
1867 void
1868 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         uint32_t ctrl;
1873         uint16_t i;
1874         struct ixgbe_rx_queue *rxq;
1875
1876         PMD_INIT_FUNC_TRACE();
1877
1878         if (hw->mac.type == ixgbe_mac_82598EB) {
1879                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1880                 ctrl |= IXGBE_VLNCTRL_VME;
1881                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1882         } else {
1883                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1884                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1885                         rxq = dev->data->rx_queues[i];
1886                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1887                         ctrl |= IXGBE_RXDCTL_VME;
1888                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1889
1890                         /* record those setting for HW strip per queue */
1891                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1892                 }
1893         }
1894 }
1895
1896 static void
1897 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1898 {
1899         struct ixgbe_hw *hw =
1900                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901         uint32_t ctrl;
1902
1903         PMD_INIT_FUNC_TRACE();
1904
1905         /* DMATXCTRL: Geric Double VLAN Disable */
1906         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1907         ctrl &= ~IXGBE_DMATXCTL_GDV;
1908         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1909
1910         /* CTRL_EXT: Global Double VLAN Disable */
1911         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1912         ctrl &= ~IXGBE_EXTENDED_VLAN;
1913         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1914
1915 }
1916
1917 static void
1918 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         uint32_t ctrl;
1923
1924         PMD_INIT_FUNC_TRACE();
1925
1926         /* DMATXCTRL: Geric Double VLAN Enable */
1927         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1928         ctrl |= IXGBE_DMATXCTL_GDV;
1929         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1930
1931         /* CTRL_EXT: Global Double VLAN Enable */
1932         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1933         ctrl |= IXGBE_EXTENDED_VLAN;
1934         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1935
1936         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1937         if (hw->mac.type == ixgbe_mac_X550 ||
1938             hw->mac.type == ixgbe_mac_X550EM_x ||
1939             hw->mac.type == ixgbe_mac_X550EM_a) {
1940                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1941                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1942                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1943         }
1944
1945         /*
1946          * VET EXT field in the EXVET register = 0x8100 by default
1947          * So no need to change. Same to VT field of DMATXCTL register
1948          */
1949 }
1950
1951 static void
1952 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1953 {
1954         if (mask & ETH_VLAN_STRIP_MASK) {
1955                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1956                         ixgbe_vlan_hw_strip_enable_all(dev);
1957                 else
1958                         ixgbe_vlan_hw_strip_disable_all(dev);
1959         }
1960
1961         if (mask & ETH_VLAN_FILTER_MASK) {
1962                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1963                         ixgbe_vlan_hw_filter_enable(dev);
1964                 else
1965                         ixgbe_vlan_hw_filter_disable(dev);
1966         }
1967
1968         if (mask & ETH_VLAN_EXTEND_MASK) {
1969                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1970                         ixgbe_vlan_hw_extend_enable(dev);
1971                 else
1972                         ixgbe_vlan_hw_extend_disable(dev);
1973         }
1974 }
1975
1976 static void
1977 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1978 {
1979         struct ixgbe_hw *hw =
1980                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1981         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1982         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1983
1984         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1985         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1986 }
1987
1988 static int
1989 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1990 {
1991         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
1992
1993         switch (nb_rx_q) {
1994         case 1:
1995         case 2:
1996                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1997                 break;
1998         case 4:
1999                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2000                 break;
2001         default:
2002                 return -EINVAL;
2003         }
2004
2005         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2006         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2007
2008         return 0;
2009 }
2010
2011 static int
2012 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2013 {
2014         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2015         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2016         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2017         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2018
2019         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2020                 /* check multi-queue mode */
2021                 switch (dev_conf->rxmode.mq_mode) {
2022                 case ETH_MQ_RX_VMDQ_DCB:
2023                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2024                         break;
2025                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2026                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2027                         PMD_INIT_LOG(ERR, "SRIOV active,"
2028                                         " unsupported mq_mode rx %d.",
2029                                         dev_conf->rxmode.mq_mode);
2030                         return -EINVAL;
2031                 case ETH_MQ_RX_RSS:
2032                 case ETH_MQ_RX_VMDQ_RSS:
2033                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2034                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2035                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2036                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2037                                                 " invalid queue number"
2038                                                 " for VMDQ RSS, allowed"
2039                                                 " value are 1, 2 or 4.");
2040                                         return -EINVAL;
2041                                 }
2042                         break;
2043                 case ETH_MQ_RX_VMDQ_ONLY:
2044                 case ETH_MQ_RX_NONE:
2045                         /* if nothing mq mode configure, use default scheme */
2046                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2047                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2048                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2049                         break;
2050                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2051                         /* SRIOV only works in VMDq enable mode */
2052                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2053                                         " wrong mq_mode rx %d.",
2054                                         dev_conf->rxmode.mq_mode);
2055                         return -EINVAL;
2056                 }
2057
2058                 switch (dev_conf->txmode.mq_mode) {
2059                 case ETH_MQ_TX_VMDQ_DCB:
2060                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2061                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2062                         break;
2063                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2064                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2065                         break;
2066                 }
2067
2068                 /* check valid queue number */
2069                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2070                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2071                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2072                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2073                                         " must be less than or equal to %d.",
2074                                         nb_rx_q, nb_tx_q,
2075                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2076                         return -EINVAL;
2077                 }
2078         } else {
2079                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2080                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2081                                           " not supported.");
2082                         return -EINVAL;
2083                 }
2084                 /* check configuration for vmdb+dcb mode */
2085                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2086                         const struct rte_eth_vmdq_dcb_conf *conf;
2087
2088                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2089                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2090                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2091                                 return -EINVAL;
2092                         }
2093                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2094                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2095                                conf->nb_queue_pools == ETH_32_POOLS)) {
2096                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2097                                                 " nb_queue_pools must be %d or %d.",
2098                                                 ETH_16_POOLS, ETH_32_POOLS);
2099                                 return -EINVAL;
2100                         }
2101                 }
2102                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2103                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2104
2105                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2106                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2107                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2108                                 return -EINVAL;
2109                         }
2110                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2111                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2112                                conf->nb_queue_pools == ETH_32_POOLS)) {
2113                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2114                                                 " nb_queue_pools != %d and"
2115                                                 " nb_queue_pools != %d.",
2116                                                 ETH_16_POOLS, ETH_32_POOLS);
2117                                 return -EINVAL;
2118                         }
2119                 }
2120
2121                 /* For DCB mode check our configuration before we go further */
2122                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2123                         const struct rte_eth_dcb_rx_conf *conf;
2124
2125                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2126                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2127                                                  IXGBE_DCB_NB_QUEUES);
2128                                 return -EINVAL;
2129                         }
2130                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2131                         if (!(conf->nb_tcs == ETH_4_TCS ||
2132                                conf->nb_tcs == ETH_8_TCS)) {
2133                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2134                                                 " and nb_tcs != %d.",
2135                                                 ETH_4_TCS, ETH_8_TCS);
2136                                 return -EINVAL;
2137                         }
2138                 }
2139
2140                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2141                         const struct rte_eth_dcb_tx_conf *conf;
2142
2143                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2144                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2145                                                  IXGBE_DCB_NB_QUEUES);
2146                                 return -EINVAL;
2147                         }
2148                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2149                         if (!(conf->nb_tcs == ETH_4_TCS ||
2150                                conf->nb_tcs == ETH_8_TCS)) {
2151                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2152                                                 " and nb_tcs != %d.",
2153                                                 ETH_4_TCS, ETH_8_TCS);
2154                                 return -EINVAL;
2155                         }
2156                 }
2157
2158                 /*
2159                  * When DCB/VT is off, maximum number of queues changes,
2160                  * except for 82598EB, which remains constant.
2161                  */
2162                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2163                                 hw->mac.type != ixgbe_mac_82598EB) {
2164                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2165                                 PMD_INIT_LOG(ERR,
2166                                              "Neither VT nor DCB are enabled, "
2167                                              "nb_tx_q > %d.",
2168                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2169                                 return -EINVAL;
2170                         }
2171                 }
2172         }
2173         return 0;
2174 }
2175
2176 static int
2177 ixgbe_dev_configure(struct rte_eth_dev *dev)
2178 {
2179         struct ixgbe_interrupt *intr =
2180                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2181         struct ixgbe_adapter *adapter =
2182                 (struct ixgbe_adapter *)dev->data->dev_private;
2183         int ret;
2184
2185         PMD_INIT_FUNC_TRACE();
2186         /* multipe queue mode checking */
2187         ret  = ixgbe_check_mq_mode(dev);
2188         if (ret != 0) {
2189                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2190                             ret);
2191                 return ret;
2192         }
2193
2194         /* set flag to update link status after init */
2195         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2196
2197         /*
2198          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2199          * allocation or vector Rx preconditions we will reset it.
2200          */
2201         adapter->rx_bulk_alloc_allowed = true;
2202         adapter->rx_vec_allowed = true;
2203
2204         return 0;
2205 }
2206
2207 static void
2208 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2209 {
2210         struct ixgbe_hw *hw =
2211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         struct ixgbe_interrupt *intr =
2213                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2214         uint32_t gpie;
2215
2216         /* only set up it on X550EM_X */
2217         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2218                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2219                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2220                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2221                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2222                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2223         }
2224 }
2225
2226 /*
2227  * Configure device link speed and setup link.
2228  * It returns 0 on success.
2229  */
2230 static int
2231 ixgbe_dev_start(struct rte_eth_dev *dev)
2232 {
2233         struct ixgbe_hw *hw =
2234                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2235         struct ixgbe_vf_info *vfinfo =
2236                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2237         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2238         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2239         uint32_t intr_vector = 0;
2240         int err, link_up = 0, negotiate = 0;
2241         uint32_t speed = 0;
2242         int mask = 0;
2243         int status;
2244         uint16_t vf, idx;
2245         uint32_t *link_speeds;
2246
2247         PMD_INIT_FUNC_TRACE();
2248
2249         /* IXGBE devices don't support:
2250         *    - half duplex (checked afterwards for valid speeds)
2251         *    - fixed speed: TODO implement
2252         */
2253         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2254                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2255                              dev->data->port_id);
2256                 return -EINVAL;
2257         }
2258
2259         /* disable uio/vfio intr/eventfd mapping */
2260         rte_intr_disable(intr_handle);
2261
2262         /* stop adapter */
2263         hw->adapter_stopped = 0;
2264         ixgbe_stop_adapter(hw);
2265
2266         /* reinitialize adapter
2267          * this calls reset and start
2268          */
2269         status = ixgbe_pf_reset_hw(hw);
2270         if (status != 0)
2271                 return -1;
2272         hw->mac.ops.start_hw(hw);
2273         hw->mac.get_link_status = true;
2274
2275         /* configure PF module if SRIOV enabled */
2276         ixgbe_pf_host_configure(dev);
2277
2278         ixgbe_dev_phy_intr_setup(dev);
2279
2280         /* check and configure queue intr-vector mapping */
2281         if ((rte_intr_cap_multiple(intr_handle) ||
2282              !RTE_ETH_DEV_SRIOV(dev).active) &&
2283             dev->data->dev_conf.intr_conf.rxq != 0) {
2284                 intr_vector = dev->data->nb_rx_queues;
2285                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2286                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2287                                         IXGBE_MAX_INTR_QUEUE_NUM);
2288                         return -ENOTSUP;
2289                 }
2290                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2291                         return -1;
2292         }
2293
2294         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2295                 intr_handle->intr_vec =
2296                         rte_zmalloc("intr_vec",
2297                                     dev->data->nb_rx_queues * sizeof(int), 0);
2298                 if (intr_handle->intr_vec == NULL) {
2299                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2300                                      " intr_vec\n", dev->data->nb_rx_queues);
2301                         return -ENOMEM;
2302                 }
2303         }
2304
2305         /* confiugre msix for sleep until rx interrupt */
2306         ixgbe_configure_msix(dev);
2307
2308         /* initialize transmission unit */
2309         ixgbe_dev_tx_init(dev);
2310
2311         /* This can fail when allocating mbufs for descriptor rings */
2312         err = ixgbe_dev_rx_init(dev);
2313         if (err) {
2314                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2315                 goto error;
2316         }
2317
2318     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2319                 ETH_VLAN_EXTEND_MASK;
2320         ixgbe_vlan_offload_set(dev, mask);
2321
2322         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2323                 /* Enable vlan filtering for VMDq */
2324                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2325         }
2326
2327         /* Configure DCB hw */
2328         ixgbe_configure_dcb(dev);
2329
2330         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2331                 err = ixgbe_fdir_configure(dev);
2332                 if (err)
2333                         goto error;
2334         }
2335
2336         /* Restore vf rate limit */
2337         if (vfinfo != NULL) {
2338                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2339                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2340                                 if (vfinfo[vf].tx_rate[idx] != 0)
2341                                         rte_pmd_ixgbe_set_vf_rate_limit(
2342                                                 dev->data->port_id, vf,
2343                                                 vfinfo[vf].tx_rate[idx],
2344                                                 1 << idx);
2345         }
2346
2347         ixgbe_restore_statistics_mapping(dev);
2348
2349         err = ixgbe_dev_rxtx_start(dev);
2350         if (err < 0) {
2351                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2352                 goto error;
2353         }
2354
2355         /* Skip link setup if loopback mode is enabled for 82599. */
2356         if (hw->mac.type == ixgbe_mac_82599EB &&
2357                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2358                 goto skip_link_setup;
2359
2360         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2361                 err = hw->mac.ops.setup_sfp(hw);
2362                 if (err)
2363                         goto error;
2364         }
2365
2366         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2367                 /* Turn on the copper */
2368                 ixgbe_set_phy_power(hw, true);
2369         } else {
2370                 /* Turn on the laser */
2371                 ixgbe_enable_tx_laser(hw);
2372         }
2373
2374         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2375         if (err)
2376                 goto error;
2377         dev->data->dev_link.link_status = link_up;
2378
2379         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2380         if (err)
2381                 goto error;
2382
2383         link_speeds = &dev->data->dev_conf.link_speeds;
2384         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2385                         ETH_LINK_SPEED_10G)) {
2386                 PMD_INIT_LOG(ERR, "Invalid link setting");
2387                 goto error;
2388         }
2389
2390         speed = 0x0;
2391         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2392                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2393                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2394                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2395         } else {
2396                 if (*link_speeds & ETH_LINK_SPEED_10G)
2397                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2398                 if (*link_speeds & ETH_LINK_SPEED_1G)
2399                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2400                 if (*link_speeds & ETH_LINK_SPEED_100M)
2401                         speed |= IXGBE_LINK_SPEED_100_FULL;
2402         }
2403
2404         err = ixgbe_setup_link(hw, speed, link_up);
2405         if (err)
2406                 goto error;
2407
2408 skip_link_setup:
2409
2410         if (rte_intr_allow_others(intr_handle)) {
2411                 /* check if lsc interrupt is enabled */
2412                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2413                         ixgbe_dev_lsc_interrupt_setup(dev);
2414                 ixgbe_dev_macsec_interrupt_setup(dev);
2415         } else {
2416                 rte_intr_callback_unregister(intr_handle,
2417                                              ixgbe_dev_interrupt_handler, dev);
2418                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2419                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2420                                      " no intr multiplex\n");
2421         }
2422
2423         /* check if rxq interrupt is enabled */
2424         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2425             rte_intr_dp_is_en(intr_handle))
2426                 ixgbe_dev_rxq_interrupt_setup(dev);
2427
2428         /* enable uio/vfio intr/eventfd mapping */
2429         rte_intr_enable(intr_handle);
2430
2431         /* resume enabled intr since hw reset */
2432         ixgbe_enable_intr(dev);
2433
2434         return 0;
2435
2436 error:
2437         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2438         ixgbe_dev_clear_queues(dev);
2439         return -EIO;
2440 }
2441
2442 /*
2443  * Stop device: disable rx and tx functions to allow for reconfiguring.
2444  */
2445 static void
2446 ixgbe_dev_stop(struct rte_eth_dev *dev)
2447 {
2448         struct rte_eth_link link;
2449         struct ixgbe_hw *hw =
2450                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2451         struct ixgbe_vf_info *vfinfo =
2452                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2453         struct ixgbe_filter_info *filter_info =
2454                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2455         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2456         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2457         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2458         int vf;
2459
2460         PMD_INIT_FUNC_TRACE();
2461
2462         /* disable interrupts */
2463         ixgbe_disable_intr(hw);
2464
2465         /* reset the NIC */
2466         ixgbe_pf_reset_hw(hw);
2467         hw->adapter_stopped = 0;
2468
2469         /* stop adapter */
2470         ixgbe_stop_adapter(hw);
2471
2472         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2473                 vfinfo[vf].clear_to_send = false;
2474
2475         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2476                 /* Turn off the copper */
2477                 ixgbe_set_phy_power(hw, false);
2478         } else {
2479                 /* Turn off the laser */
2480                 ixgbe_disable_tx_laser(hw);
2481         }
2482
2483         ixgbe_dev_clear_queues(dev);
2484
2485         /* Clear stored conf */
2486         dev->data->scattered_rx = 0;
2487         dev->data->lro = 0;
2488
2489         /* Clear recorded link status */
2490         memset(&link, 0, sizeof(link));
2491         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2492
2493         /* Remove all ntuple filters of the device */
2494         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2495              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2496                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2497                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2498                              p_5tuple, entries);
2499                 rte_free(p_5tuple);
2500         }
2501         memset(filter_info->fivetuple_mask, 0,
2502                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2503
2504         if (!rte_intr_allow_others(intr_handle))
2505                 /* resume to the default handler */
2506                 rte_intr_callback_register(intr_handle,
2507                                            ixgbe_dev_interrupt_handler,
2508                                            (void *)dev);
2509
2510         /* Clean datapath event and queue/vec mapping */
2511         rte_intr_efd_disable(intr_handle);
2512         if (intr_handle->intr_vec != NULL) {
2513                 rte_free(intr_handle->intr_vec);
2514                 intr_handle->intr_vec = NULL;
2515         }
2516 }
2517
2518 /*
2519  * Set device link up: enable tx.
2520  */
2521 static int
2522 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2523 {
2524         struct ixgbe_hw *hw =
2525                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2526         if (hw->mac.type == ixgbe_mac_82599EB) {
2527 #ifdef RTE_NIC_BYPASS
2528                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2529                         /* Not suported in bypass mode */
2530                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2531                                      "by device id 0x%x", hw->device_id);
2532                         return -ENOTSUP;
2533                 }
2534 #endif
2535         }
2536
2537         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2538                 /* Turn on the copper */
2539                 ixgbe_set_phy_power(hw, true);
2540         } else {
2541                 /* Turn on the laser */
2542                 ixgbe_enable_tx_laser(hw);
2543         }
2544
2545         return 0;
2546 }
2547
2548 /*
2549  * Set device link down: disable tx.
2550  */
2551 static int
2552 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2553 {
2554         struct ixgbe_hw *hw =
2555                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2556         if (hw->mac.type == ixgbe_mac_82599EB) {
2557 #ifdef RTE_NIC_BYPASS
2558                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2559                         /* Not suported in bypass mode */
2560                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2561                                      "by device id 0x%x", hw->device_id);
2562                         return -ENOTSUP;
2563                 }
2564 #endif
2565         }
2566
2567         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2568                 /* Turn off the copper */
2569                 ixgbe_set_phy_power(hw, false);
2570         } else {
2571                 /* Turn off the laser */
2572                 ixgbe_disable_tx_laser(hw);
2573         }
2574
2575         return 0;
2576 }
2577
2578 /*
2579  * Reest and stop device.
2580  */
2581 static void
2582 ixgbe_dev_close(struct rte_eth_dev *dev)
2583 {
2584         struct ixgbe_hw *hw =
2585                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586
2587         PMD_INIT_FUNC_TRACE();
2588
2589         ixgbe_pf_reset_hw(hw);
2590
2591         ixgbe_dev_stop(dev);
2592         hw->adapter_stopped = 1;
2593
2594         ixgbe_dev_free_queues(dev);
2595
2596         ixgbe_disable_pcie_master(hw);
2597
2598         /* reprogram the RAR[0] in case user changed it. */
2599         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2600 }
2601
2602 static void
2603 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2604                            struct ixgbe_hw_stats *hw_stats,
2605                            struct ixgbe_macsec_stats *macsec_stats,
2606                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2607                            uint64_t *total_qprc, uint64_t *total_qprdc)
2608 {
2609         uint32_t bprc, lxon, lxoff, total;
2610         uint32_t delta_gprc = 0;
2611         unsigned i;
2612         /* Workaround for RX byte count not including CRC bytes when CRC
2613          * strip is enabled. CRC bytes are removed from counters when crc_strip
2614          * is disabled.
2615          */
2616         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2617                         IXGBE_HLREG0_RXCRCSTRP);
2618
2619         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2620         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2621         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2622         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2623
2624         for (i = 0; i < 8; i++) {
2625                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2626
2627                 /* global total per queue */
2628                 hw_stats->mpc[i] += mp;
2629                 /* Running comprehensive total for stats display */
2630                 *total_missed_rx += hw_stats->mpc[i];
2631                 if (hw->mac.type == ixgbe_mac_82598EB) {
2632                         hw_stats->rnbc[i] +=
2633                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2634                         hw_stats->pxonrxc[i] +=
2635                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2636                         hw_stats->pxoffrxc[i] +=
2637                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2638                 } else {
2639                         hw_stats->pxonrxc[i] +=
2640                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2641                         hw_stats->pxoffrxc[i] +=
2642                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2643                         hw_stats->pxon2offc[i] +=
2644                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2645                 }
2646                 hw_stats->pxontxc[i] +=
2647                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2648                 hw_stats->pxofftxc[i] +=
2649                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2650         }
2651         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2652                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2653                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2654                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2655
2656                 delta_gprc += delta_qprc;
2657
2658                 hw_stats->qprc[i] += delta_qprc;
2659                 hw_stats->qptc[i] += delta_qptc;
2660
2661                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2662                 hw_stats->qbrc[i] +=
2663                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2664                 if (crc_strip == 0)
2665                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2666
2667                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2668                 hw_stats->qbtc[i] +=
2669                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2670
2671                 hw_stats->qprdc[i] += delta_qprdc;
2672                 *total_qprdc += hw_stats->qprdc[i];
2673
2674                 *total_qprc += hw_stats->qprc[i];
2675                 *total_qbrc += hw_stats->qbrc[i];
2676         }
2677         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2678         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2679         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2680
2681         /*
2682          * An errata states that gprc actually counts good + missed packets:
2683          * Workaround to set gprc to summated queue packet receives
2684          */
2685         hw_stats->gprc = *total_qprc;
2686
2687         if (hw->mac.type != ixgbe_mac_82598EB) {
2688                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2689                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2690                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2691                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2692                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2693                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2694                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2695                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2696         } else {
2697                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2698                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2699                 /* 82598 only has a counter in the high register */
2700                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2701                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2702                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2703         }
2704         uint64_t old_tpr = hw_stats->tpr;
2705
2706         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2707         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2708
2709         if (crc_strip == 0)
2710                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2711
2712         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2713         hw_stats->gptc += delta_gptc;
2714         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2715         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2716
2717         /*
2718          * Workaround: mprc hardware is incorrectly counting
2719          * broadcasts, so for now we subtract those.
2720          */
2721         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2722         hw_stats->bprc += bprc;
2723         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2724         if (hw->mac.type == ixgbe_mac_82598EB)
2725                 hw_stats->mprc -= bprc;
2726
2727         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2728         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2729         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2730         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2731         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2732         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2733
2734         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2735         hw_stats->lxontxc += lxon;
2736         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2737         hw_stats->lxofftxc += lxoff;
2738         total = lxon + lxoff;
2739
2740         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2741         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2742         hw_stats->gptc -= total;
2743         hw_stats->mptc -= total;
2744         hw_stats->ptc64 -= total;
2745         hw_stats->gotc -= total * ETHER_MIN_LEN;
2746
2747         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2748         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2749         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2750         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2751         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2752         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2753         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2754         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2755         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2756         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2757         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2758         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2759         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2760         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2761         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2762         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2763         /* Only read FCOE on 82599 */
2764         if (hw->mac.type != ixgbe_mac_82598EB) {
2765                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2766                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2767                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2768                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2769                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2770         }
2771
2772         /* Flow Director Stats registers */
2773         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2774         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2775
2776         /* MACsec Stats registers */
2777         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2778         macsec_stats->out_pkts_encrypted +=
2779                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2780         macsec_stats->out_pkts_protected +=
2781                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2782         macsec_stats->out_octets_encrypted +=
2783                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2784         macsec_stats->out_octets_protected +=
2785                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2786         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2787         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2788         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2789         macsec_stats->in_pkts_unknownsci +=
2790                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2791         macsec_stats->in_octets_decrypted +=
2792                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2793         macsec_stats->in_octets_validated +=
2794                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2795         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2796         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2797         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2798         for (i = 0; i < 2; i++) {
2799                 macsec_stats->in_pkts_ok +=
2800                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2801                 macsec_stats->in_pkts_invalid +=
2802                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2803                 macsec_stats->in_pkts_notvalid +=
2804                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2805         }
2806         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2807         macsec_stats->in_pkts_notusingsa +=
2808                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2809 }
2810
2811 /*
2812  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2813  */
2814 static void
2815 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2816 {
2817         struct ixgbe_hw *hw =
2818                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819         struct ixgbe_hw_stats *hw_stats =
2820                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2821         struct ixgbe_macsec_stats *macsec_stats =
2822                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2823                                 dev->data->dev_private);
2824         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2825         unsigned i;
2826
2827         total_missed_rx = 0;
2828         total_qbrc = 0;
2829         total_qprc = 0;
2830         total_qprdc = 0;
2831
2832         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2833                         &total_qbrc, &total_qprc, &total_qprdc);
2834
2835         if (stats == NULL)
2836                 return;
2837
2838         /* Fill out the rte_eth_stats statistics structure */
2839         stats->ipackets = total_qprc;
2840         stats->ibytes = total_qbrc;
2841         stats->opackets = hw_stats->gptc;
2842         stats->obytes = hw_stats->gotc;
2843
2844         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2845                 stats->q_ipackets[i] = hw_stats->qprc[i];
2846                 stats->q_opackets[i] = hw_stats->qptc[i];
2847                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2848                 stats->q_obytes[i] = hw_stats->qbtc[i];
2849                 stats->q_errors[i] = hw_stats->qprdc[i];
2850         }
2851
2852         /* Rx Errors */
2853         stats->imissed  = total_missed_rx;
2854         stats->ierrors  = hw_stats->crcerrs +
2855                           hw_stats->mspdc +
2856                           hw_stats->rlec +
2857                           hw_stats->ruc +
2858                           hw_stats->roc +
2859                           hw_stats->illerrc +
2860                           hw_stats->errbc +
2861                           hw_stats->rfc +
2862                           hw_stats->fccrc +
2863                           hw_stats->fclast;
2864
2865         /* Tx Errors */
2866         stats->oerrors  = 0;
2867 }
2868
2869 static void
2870 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2871 {
2872         struct ixgbe_hw_stats *stats =
2873                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2874
2875         /* HW registers are cleared on read */
2876         ixgbe_dev_stats_get(dev, NULL);
2877
2878         /* Reset software totals */
2879         memset(stats, 0, sizeof(*stats));
2880 }
2881
2882 /* This function calculates the number of xstats based on the current config */
2883 static unsigned
2884 ixgbe_xstats_calc_num(void) {
2885         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
2886                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2887                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2888 }
2889
2890 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2891         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2892 {
2893         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2894         unsigned stat, i, count;
2895
2896         if (xstats_names != NULL) {
2897                 count = 0;
2898
2899                 /* Note: limit >= cnt_stats checked upstream
2900                  * in rte_eth_xstats_names()
2901                  */
2902
2903                 /* Extended stats from ixgbe_hw_stats */
2904                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2905                         snprintf(xstats_names[count].name,
2906                                 sizeof(xstats_names[count].name),
2907                                 "%s",
2908                                 rte_ixgbe_stats_strings[i].name);
2909                         count++;
2910                 }
2911
2912                 /* MACsec Stats */
2913                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
2914                         snprintf(xstats_names[count].name,
2915                                 sizeof(xstats_names[count].name),
2916                                 "%s",
2917                                 rte_ixgbe_macsec_strings[i].name);
2918                         count++;
2919                 }
2920
2921                 /* RX Priority Stats */
2922                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2923                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2924                                 snprintf(xstats_names[count].name,
2925                                         sizeof(xstats_names[count].name),
2926                                         "rx_priority%u_%s", i,
2927                                         rte_ixgbe_rxq_strings[stat].name);
2928                                 count++;
2929                         }
2930                 }
2931
2932                 /* TX Priority Stats */
2933                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2934                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2935                                 snprintf(xstats_names[count].name,
2936                                         sizeof(xstats_names[count].name),
2937                                         "tx_priority%u_%s", i,
2938                                         rte_ixgbe_txq_strings[stat].name);
2939                                 count++;
2940                         }
2941                 }
2942         }
2943         return cnt_stats;
2944 }
2945
2946 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2947         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2948 {
2949         unsigned i;
2950
2951         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2952                 return -ENOMEM;
2953
2954         if (xstats_names != NULL)
2955                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2956                         snprintf(xstats_names[i].name,
2957                                 sizeof(xstats_names[i].name),
2958                                 "%s", rte_ixgbevf_stats_strings[i].name);
2959         return IXGBEVF_NB_XSTATS;
2960 }
2961
2962 static int
2963 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2964                                          unsigned n)
2965 {
2966         struct ixgbe_hw *hw =
2967                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968         struct ixgbe_hw_stats *hw_stats =
2969                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2970         struct ixgbe_macsec_stats *macsec_stats =
2971                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2972                                 dev->data->dev_private);
2973         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2974         unsigned i, stat, count = 0;
2975
2976         count = ixgbe_xstats_calc_num();
2977
2978         if (n < count)
2979                 return count;
2980
2981         total_missed_rx = 0;
2982         total_qbrc = 0;
2983         total_qprc = 0;
2984         total_qprdc = 0;
2985
2986         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2987                         &total_qbrc, &total_qprc, &total_qprdc);
2988
2989         /* If this is a reset xstats is NULL, and we have cleared the
2990          * registers by reading them.
2991          */
2992         if (!xstats)
2993                 return 0;
2994
2995         /* Extended stats from ixgbe_hw_stats */
2996         count = 0;
2997         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2998                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2999                                 rte_ixgbe_stats_strings[i].offset);
3000                 xstats[count].id = count;
3001                 count++;
3002         }
3003
3004         /* MACsec Stats */
3005         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3006                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3007                                 rte_ixgbe_macsec_strings[i].offset);
3008                 xstats[count].id = count;
3009                 count++;
3010         }
3011
3012         /* RX Priority Stats */
3013         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3014                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3015                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3016                                         rte_ixgbe_rxq_strings[stat].offset +
3017                                         (sizeof(uint64_t) * i));
3018                         xstats[count].id = count;
3019                         count++;
3020                 }
3021         }
3022
3023         /* TX Priority Stats */
3024         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3025                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3026                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3027                                         rte_ixgbe_txq_strings[stat].offset +
3028                                         (sizeof(uint64_t) * i));
3029                         xstats[count].id = count;
3030                         count++;
3031                 }
3032         }
3033         return count;
3034 }
3035
3036 static void
3037 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3038 {
3039         struct ixgbe_hw_stats *stats =
3040                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3041         struct ixgbe_macsec_stats *macsec_stats =
3042                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3043                                 dev->data->dev_private);
3044
3045         unsigned count = ixgbe_xstats_calc_num();
3046
3047         /* HW registers are cleared on read */
3048         ixgbe_dev_xstats_get(dev, NULL, count);
3049
3050         /* Reset software totals */
3051         memset(stats, 0, sizeof(*stats));
3052         memset(macsec_stats, 0, sizeof(*macsec_stats));
3053 }
3054
3055 static void
3056 ixgbevf_update_stats(struct rte_eth_dev *dev)
3057 {
3058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3059         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3060                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3061
3062         /* Good Rx packet, include VF loopback */
3063         UPDATE_VF_STAT(IXGBE_VFGPRC,
3064             hw_stats->last_vfgprc, hw_stats->vfgprc);
3065
3066         /* Good Rx octets, include VF loopback */
3067         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3068             hw_stats->last_vfgorc, hw_stats->vfgorc);
3069
3070         /* Good Tx packet, include VF loopback */
3071         UPDATE_VF_STAT(IXGBE_VFGPTC,
3072             hw_stats->last_vfgptc, hw_stats->vfgptc);
3073
3074         /* Good Tx octets, include VF loopback */
3075         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3076             hw_stats->last_vfgotc, hw_stats->vfgotc);
3077
3078         /* Rx Multicst Packet */
3079         UPDATE_VF_STAT(IXGBE_VFMPRC,
3080             hw_stats->last_vfmprc, hw_stats->vfmprc);
3081 }
3082
3083 static int
3084 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3085                        unsigned n)
3086 {
3087         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3088                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3089         unsigned i;
3090
3091         if (n < IXGBEVF_NB_XSTATS)
3092                 return IXGBEVF_NB_XSTATS;
3093
3094         ixgbevf_update_stats(dev);
3095
3096         if (!xstats)
3097                 return 0;
3098
3099         /* Extended stats */
3100         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3101                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3102                         rte_ixgbevf_stats_strings[i].offset);
3103         }
3104
3105         return IXGBEVF_NB_XSTATS;
3106 }
3107
3108 static void
3109 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3110 {
3111         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3112                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3113
3114         ixgbevf_update_stats(dev);
3115
3116         if (stats == NULL)
3117                 return;
3118
3119         stats->ipackets = hw_stats->vfgprc;
3120         stats->ibytes = hw_stats->vfgorc;
3121         stats->opackets = hw_stats->vfgptc;
3122         stats->obytes = hw_stats->vfgotc;
3123 }
3124
3125 static void
3126 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3127 {
3128         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3129                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3130
3131         /* Sync HW register to the last stats */
3132         ixgbevf_dev_stats_get(dev, NULL);
3133
3134         /* reset HW current stats*/
3135         hw_stats->vfgprc = 0;
3136         hw_stats->vfgorc = 0;
3137         hw_stats->vfgptc = 0;
3138         hw_stats->vfgotc = 0;
3139 }
3140
3141 static int
3142 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3143 {
3144         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3145         u16 eeprom_verh, eeprom_verl;
3146         u32 etrack_id;
3147         int ret;
3148
3149         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3150         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3151
3152         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3153         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3154
3155         ret += 1; /* add the size of '\0' */
3156         if (fw_size < (u32)ret)
3157                 return ret;
3158         else
3159                 return 0;
3160 }
3161
3162 static void
3163 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3164 {
3165         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3167         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3168
3169         dev_info->pci_dev = pci_dev;
3170         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3171         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3172         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3173                 /*
3174                  * When DCB/VT is off, maximum number of queues changes,
3175                  * except for 82598EB, which remains constant.
3176                  */
3177                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3178                                 hw->mac.type != ixgbe_mac_82598EB)
3179                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3180         }
3181         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3182         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3183         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3184         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3185         dev_info->max_vfs = pci_dev->max_vfs;
3186         if (hw->mac.type == ixgbe_mac_82598EB)
3187                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3188         else
3189                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3190         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3191         dev_info->rx_offload_capa =
3192                 DEV_RX_OFFLOAD_VLAN_STRIP |
3193                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3194                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3195                 DEV_RX_OFFLOAD_TCP_CKSUM;
3196
3197         /*
3198          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3199          * mode.
3200          */
3201         if ((hw->mac.type == ixgbe_mac_82599EB ||
3202              hw->mac.type == ixgbe_mac_X540) &&
3203             !RTE_ETH_DEV_SRIOV(dev).active)
3204                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3205
3206         if (hw->mac.type == ixgbe_mac_82599EB ||
3207             hw->mac.type == ixgbe_mac_X540)
3208                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3209
3210         if (hw->mac.type == ixgbe_mac_X550 ||
3211             hw->mac.type == ixgbe_mac_X550EM_x ||
3212             hw->mac.type == ixgbe_mac_X550EM_a)
3213                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3214
3215         dev_info->tx_offload_capa =
3216                 DEV_TX_OFFLOAD_VLAN_INSERT |
3217                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3218                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3219                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3220                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3221                 DEV_TX_OFFLOAD_TCP_TSO;
3222
3223         if (hw->mac.type == ixgbe_mac_82599EB ||
3224             hw->mac.type == ixgbe_mac_X540)
3225                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3226
3227         if (hw->mac.type == ixgbe_mac_X550 ||
3228             hw->mac.type == ixgbe_mac_X550EM_x ||
3229             hw->mac.type == ixgbe_mac_X550EM_a)
3230                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3231
3232         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3233                 .rx_thresh = {
3234                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3235                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3236                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3237                 },
3238                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3239                 .rx_drop_en = 0,
3240         };
3241
3242         dev_info->default_txconf = (struct rte_eth_txconf) {
3243                 .tx_thresh = {
3244                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3245                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3246                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3247                 },
3248                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3249                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3250                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3251                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3252         };
3253
3254         dev_info->rx_desc_lim = rx_desc_lim;
3255         dev_info->tx_desc_lim = tx_desc_lim;
3256
3257         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3258         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3259         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3260
3261         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3262         if (hw->mac.type == ixgbe_mac_X540 ||
3263             hw->mac.type == ixgbe_mac_X540_vf ||
3264             hw->mac.type == ixgbe_mac_X550 ||
3265             hw->mac.type == ixgbe_mac_X550_vf) {
3266                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3267         }
3268 }
3269
3270 static const uint32_t *
3271 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3272 {
3273         static const uint32_t ptypes[] = {
3274                 /* For non-vec functions,
3275                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3276                  * for vec functions,
3277                  * refers to _recv_raw_pkts_vec().
3278                  */
3279                 RTE_PTYPE_L2_ETHER,
3280                 RTE_PTYPE_L3_IPV4,
3281                 RTE_PTYPE_L3_IPV4_EXT,
3282                 RTE_PTYPE_L3_IPV6,
3283                 RTE_PTYPE_L3_IPV6_EXT,
3284                 RTE_PTYPE_L4_SCTP,
3285                 RTE_PTYPE_L4_TCP,
3286                 RTE_PTYPE_L4_UDP,
3287                 RTE_PTYPE_TUNNEL_IP,
3288                 RTE_PTYPE_INNER_L3_IPV6,
3289                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3290                 RTE_PTYPE_INNER_L4_TCP,
3291                 RTE_PTYPE_INNER_L4_UDP,
3292                 RTE_PTYPE_UNKNOWN
3293         };
3294
3295         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3296             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3297             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3298             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3299                 return ptypes;
3300         return NULL;
3301 }
3302
3303 static void
3304 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3305                      struct rte_eth_dev_info *dev_info)
3306 {
3307         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3308         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3309
3310         dev_info->pci_dev = pci_dev;
3311         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3312         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3313         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3314         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3315         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3316         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3317         dev_info->max_vfs = pci_dev->max_vfs;
3318         if (hw->mac.type == ixgbe_mac_82598EB)
3319                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3320         else
3321                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3322         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3323                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3324                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3325                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3326         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3327                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3328                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3329                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3330                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3331                                 DEV_TX_OFFLOAD_TCP_TSO;
3332
3333         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3334                 .rx_thresh = {
3335                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3336                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3337                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3338                 },
3339                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3340                 .rx_drop_en = 0,
3341         };
3342
3343         dev_info->default_txconf = (struct rte_eth_txconf) {
3344                 .tx_thresh = {
3345                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3346                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3347                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3348                 },
3349                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3350                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3351                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3352                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3353         };
3354
3355         dev_info->rx_desc_lim = rx_desc_lim;
3356         dev_info->tx_desc_lim = tx_desc_lim;
3357 }
3358
3359 /* return 0 means link status changed, -1 means not changed */
3360 static int
3361 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3362 {
3363         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3364         struct rte_eth_link link, old;
3365         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3366         int link_up;
3367         int diag;
3368
3369         link.link_status = ETH_LINK_DOWN;
3370         link.link_speed = 0;
3371         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3372         memset(&old, 0, sizeof(old));
3373         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3374
3375         hw->mac.get_link_status = true;
3376
3377         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3378         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3379                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3380         else
3381                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3382
3383         if (diag != 0) {
3384                 link.link_speed = ETH_SPEED_NUM_100M;
3385                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3386                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3387                 if (link.link_status == old.link_status)
3388                         return -1;
3389                 return 0;
3390         }
3391
3392         if (link_up == 0) {
3393                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3394                 if (link.link_status == old.link_status)
3395                         return -1;
3396                 return 0;
3397         }
3398         link.link_status = ETH_LINK_UP;
3399         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3400
3401         switch (link_speed) {
3402         default:
3403         case IXGBE_LINK_SPEED_UNKNOWN:
3404                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3405                 link.link_speed = ETH_SPEED_NUM_100M;
3406                 break;
3407
3408         case IXGBE_LINK_SPEED_100_FULL:
3409                 link.link_speed = ETH_SPEED_NUM_100M;
3410                 break;
3411
3412         case IXGBE_LINK_SPEED_1GB_FULL:
3413                 link.link_speed = ETH_SPEED_NUM_1G;
3414                 break;
3415
3416         case IXGBE_LINK_SPEED_10GB_FULL:
3417                 link.link_speed = ETH_SPEED_NUM_10G;
3418                 break;
3419         }
3420         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3421
3422         if (link.link_status == old.link_status)
3423                 return -1;
3424
3425         return 0;
3426 }
3427
3428 static void
3429 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3430 {
3431         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3432         uint32_t fctrl;
3433
3434         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3435         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3436         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3437 }
3438
3439 static void
3440 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3441 {
3442         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3443         uint32_t fctrl;
3444
3445         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3446         fctrl &= (~IXGBE_FCTRL_UPE);
3447         if (dev->data->all_multicast == 1)
3448                 fctrl |= IXGBE_FCTRL_MPE;
3449         else
3450                 fctrl &= (~IXGBE_FCTRL_MPE);
3451         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3452 }
3453
3454 static void
3455 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3456 {
3457         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458         uint32_t fctrl;
3459
3460         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3461         fctrl |= IXGBE_FCTRL_MPE;
3462         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3463 }
3464
3465 static void
3466 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3467 {
3468         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469         uint32_t fctrl;
3470
3471         if (dev->data->promiscuous == 1)
3472                 return; /* must remain in all_multicast mode */
3473
3474         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3475         fctrl &= (~IXGBE_FCTRL_MPE);
3476         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3477 }
3478
3479 /**
3480  * It clears the interrupt causes and enables the interrupt.
3481  * It will be called once only during nic initialized.
3482  *
3483  * @param dev
3484  *  Pointer to struct rte_eth_dev.
3485  *
3486  * @return
3487  *  - On success, zero.
3488  *  - On failure, a negative value.
3489  */
3490 static int
3491 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3492 {
3493         struct ixgbe_interrupt *intr =
3494                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3495
3496         ixgbe_dev_link_status_print(dev);
3497         intr->mask |= IXGBE_EICR_LSC;
3498
3499         return 0;
3500 }
3501
3502 /**
3503  * It clears the interrupt causes and enables the interrupt.
3504  * It will be called once only during nic initialized.
3505  *
3506  * @param dev
3507  *  Pointer to struct rte_eth_dev.
3508  *
3509  * @return
3510  *  - On success, zero.
3511  *  - On failure, a negative value.
3512  */
3513 static int
3514 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3515 {
3516         struct ixgbe_interrupt *intr =
3517                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3518
3519         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3520
3521         return 0;
3522 }
3523
3524 /**
3525  * It clears the interrupt causes and enables the interrupt.
3526  * It will be called once only during nic initialized.
3527  *
3528  * @param dev
3529  *  Pointer to struct rte_eth_dev.
3530  *
3531  * @return
3532  *  - On success, zero.
3533  *  - On failure, a negative value.
3534  */
3535 static int
3536 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3537 {
3538         struct ixgbe_interrupt *intr =
3539                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3540
3541         intr->mask |= IXGBE_EICR_LINKSEC;
3542
3543         return 0;
3544 }
3545
3546 /*
3547  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3548  *
3549  * @param dev
3550  *  Pointer to struct rte_eth_dev.
3551  *
3552  * @return
3553  *  - On success, zero.
3554  *  - On failure, a negative value.
3555  */
3556 static int
3557 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3558 {
3559         uint32_t eicr;
3560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3561         struct ixgbe_interrupt *intr =
3562                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3563
3564         /* clear all cause mask */
3565         ixgbe_disable_intr(hw);
3566
3567         /* read-on-clear nic registers here */
3568         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3569         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3570
3571         intr->flags = 0;
3572
3573         /* set flag for async link update */
3574         if (eicr & IXGBE_EICR_LSC)
3575                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3576
3577         if (eicr & IXGBE_EICR_MAILBOX)
3578                 intr->flags |= IXGBE_FLAG_MAILBOX;
3579
3580         if (eicr & IXGBE_EICR_LINKSEC)
3581                 intr->flags |= IXGBE_FLAG_MACSEC;
3582
3583         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3584             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3585             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3586                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3587
3588         return 0;
3589 }
3590
3591 /**
3592  * It gets and then prints the link status.
3593  *
3594  * @param dev
3595  *  Pointer to struct rte_eth_dev.
3596  *
3597  * @return
3598  *  - On success, zero.
3599  *  - On failure, a negative value.
3600  */
3601 static void
3602 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3603 {
3604         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3605         struct rte_eth_link link;
3606
3607         memset(&link, 0, sizeof(link));
3608         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3609         if (link.link_status) {
3610                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3611                                         (int)(dev->data->port_id),
3612                                         (unsigned)link.link_speed,
3613                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3614                                         "full-duplex" : "half-duplex");
3615         } else {
3616                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3617                                 (int)(dev->data->port_id));
3618         }
3619         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3620                                 pci_dev->addr.domain,
3621                                 pci_dev->addr.bus,
3622                                 pci_dev->addr.devid,
3623                                 pci_dev->addr.function);
3624 }
3625
3626 /*
3627  * It executes link_update after knowing an interrupt occurred.
3628  *
3629  * @param dev
3630  *  Pointer to struct rte_eth_dev.
3631  *
3632  * @return
3633  *  - On success, zero.
3634  *  - On failure, a negative value.
3635  */
3636 static int
3637 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3638                            struct rte_intr_handle *intr_handle)
3639 {
3640         struct ixgbe_interrupt *intr =
3641                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3642         int64_t timeout;
3643         struct rte_eth_link link;
3644         int intr_enable_delay = false;
3645         struct ixgbe_hw *hw =
3646                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3647
3648         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3649
3650         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3651                 ixgbe_pf_mbx_process(dev);
3652                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3653         }
3654
3655         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3656                 ixgbe_handle_lasi(hw);
3657                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3658         }
3659
3660         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3661                 /* get the link status before link update, for predicting later */
3662                 memset(&link, 0, sizeof(link));
3663                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3664
3665                 ixgbe_dev_link_update(dev, 0);
3666
3667                 /* likely to up */
3668                 if (!link.link_status)
3669                         /* handle it 1 sec later, wait it being stable */
3670                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3671                 /* likely to down */
3672                 else
3673                         /* handle it 4 sec later, wait it being stable */
3674                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3675
3676                 ixgbe_dev_link_status_print(dev);
3677
3678                 intr_enable_delay = true;
3679         }
3680
3681         if (intr_enable_delay) {
3682                 if (rte_eal_alarm_set(timeout * 1000,
3683                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3684                         PMD_DRV_LOG(ERR, "Error setting alarm");
3685         } else {
3686                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3687                 ixgbe_enable_intr(dev);
3688                 rte_intr_enable(intr_handle);
3689         }
3690
3691
3692         return 0;
3693 }
3694
3695 /**
3696  * Interrupt handler which shall be registered for alarm callback for delayed
3697  * handling specific interrupt to wait for the stable nic state. As the
3698  * NIC interrupt state is not stable for ixgbe after link is just down,
3699  * it needs to wait 4 seconds to get the stable status.
3700  *
3701  * @param handle
3702  *  Pointer to interrupt handle.
3703  * @param param
3704  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3705  *
3706  * @return
3707  *  void
3708  */
3709 static void
3710 ixgbe_dev_interrupt_delayed_handler(void *param)
3711 {
3712         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3713         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3714         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3715         struct ixgbe_interrupt *intr =
3716                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3717         struct ixgbe_hw *hw =
3718                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3719         uint32_t eicr;
3720
3721         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3722         if (eicr & IXGBE_EICR_MAILBOX)
3723                 ixgbe_pf_mbx_process(dev);
3724
3725         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3726                 ixgbe_handle_lasi(hw);
3727                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3728         }
3729
3730         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3731                 ixgbe_dev_link_update(dev, 0);
3732                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3733                 ixgbe_dev_link_status_print(dev);
3734                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3735         }
3736
3737         if (intr->flags & IXGBE_FLAG_MACSEC) {
3738                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3739                                               NULL);
3740                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3741         }
3742
3743         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3744         ixgbe_enable_intr(dev);
3745         rte_intr_enable(intr_handle);
3746 }
3747
3748 /**
3749  * Interrupt handler triggered by NIC  for handling
3750  * specific interrupt.
3751  *
3752  * @param handle
3753  *  Pointer to interrupt handle.
3754  * @param param
3755  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3756  *
3757  * @return
3758  *  void
3759  */
3760 static void
3761 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3762                             void *param)
3763 {
3764         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3765
3766         ixgbe_dev_interrupt_get_status(dev);
3767         ixgbe_dev_interrupt_action(dev, handle);
3768 }
3769
3770 static int
3771 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3772 {
3773         struct ixgbe_hw *hw;
3774
3775         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3776         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3777 }
3778
3779 static int
3780 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3781 {
3782         struct ixgbe_hw *hw;
3783
3784         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3786 }
3787
3788 static int
3789 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3790 {
3791         struct ixgbe_hw *hw;
3792         uint32_t mflcn_reg;
3793         uint32_t fccfg_reg;
3794         int rx_pause;
3795         int tx_pause;
3796
3797         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3798
3799         fc_conf->pause_time = hw->fc.pause_time;
3800         fc_conf->high_water = hw->fc.high_water[0];
3801         fc_conf->low_water = hw->fc.low_water[0];
3802         fc_conf->send_xon = hw->fc.send_xon;
3803         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3804
3805         /*
3806          * Return rx_pause status according to actual setting of
3807          * MFLCN register.
3808          */
3809         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3810         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3811                 rx_pause = 1;
3812         else
3813                 rx_pause = 0;
3814
3815         /*
3816          * Return tx_pause status according to actual setting of
3817          * FCCFG register.
3818          */
3819         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3820         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3821                 tx_pause = 1;
3822         else
3823                 tx_pause = 0;
3824
3825         if (rx_pause && tx_pause)
3826                 fc_conf->mode = RTE_FC_FULL;
3827         else if (rx_pause)
3828                 fc_conf->mode = RTE_FC_RX_PAUSE;
3829         else if (tx_pause)
3830                 fc_conf->mode = RTE_FC_TX_PAUSE;
3831         else
3832                 fc_conf->mode = RTE_FC_NONE;
3833
3834         return 0;
3835 }
3836
3837 static int
3838 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3839 {
3840         struct ixgbe_hw *hw;
3841         int err;
3842         uint32_t rx_buf_size;
3843         uint32_t max_high_water;
3844         uint32_t mflcn;
3845         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3846                 ixgbe_fc_none,
3847                 ixgbe_fc_rx_pause,
3848                 ixgbe_fc_tx_pause,
3849                 ixgbe_fc_full
3850         };
3851
3852         PMD_INIT_FUNC_TRACE();
3853
3854         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3855         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3856         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3857
3858         /*
3859          * At least reserve one Ethernet frame for watermark
3860          * high_water/low_water in kilo bytes for ixgbe
3861          */
3862         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3863         if ((fc_conf->high_water > max_high_water) ||
3864                 (fc_conf->high_water < fc_conf->low_water)) {
3865                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3866                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3867                 return -EINVAL;
3868         }
3869
3870         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3871         hw->fc.pause_time     = fc_conf->pause_time;
3872         hw->fc.high_water[0]  = fc_conf->high_water;
3873         hw->fc.low_water[0]   = fc_conf->low_water;
3874         hw->fc.send_xon       = fc_conf->send_xon;
3875         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3876
3877         err = ixgbe_fc_enable(hw);
3878
3879         /* Not negotiated is not an error case */
3880         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3881
3882                 /* check if we want to forward MAC frames - driver doesn't have native
3883                  * capability to do that, so we'll write the registers ourselves */
3884
3885                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3886
3887                 /* set or clear MFLCN.PMCF bit depending on configuration */
3888                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3889                         mflcn |= IXGBE_MFLCN_PMCF;
3890                 else
3891                         mflcn &= ~IXGBE_MFLCN_PMCF;
3892
3893                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3894                 IXGBE_WRITE_FLUSH(hw);
3895
3896                 return 0;
3897         }
3898
3899         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3900         return -EIO;
3901 }
3902
3903 /**
3904  *  ixgbe_pfc_enable_generic - Enable flow control
3905  *  @hw: pointer to hardware structure
3906  *  @tc_num: traffic class number
3907  *  Enable flow control according to the current settings.
3908  */
3909 static int
3910 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3911 {
3912         int ret_val = 0;
3913         uint32_t mflcn_reg, fccfg_reg;
3914         uint32_t reg;
3915         uint32_t fcrtl, fcrth;
3916         uint8_t i;
3917         uint8_t nb_rx_en;
3918
3919         /* Validate the water mark configuration */
3920         if (!hw->fc.pause_time) {
3921                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3922                 goto out;
3923         }
3924
3925         /* Low water mark of zero causes XOFF floods */
3926         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3927                  /* High/Low water can not be 0 */
3928                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3929                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3930                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3931                         goto out;
3932                 }
3933
3934                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3935                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3936                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3937                         goto out;
3938                 }
3939         }
3940         /* Negotiate the fc mode to use */
3941         ixgbe_fc_autoneg(hw);
3942
3943         /* Disable any previous flow control settings */
3944         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3945         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3946
3947         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3948         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3949
3950         switch (hw->fc.current_mode) {
3951         case ixgbe_fc_none:
3952                 /*
3953                  * If the count of enabled RX Priority Flow control >1,
3954                  * and the TX pause can not be disabled
3955                  */
3956                 nb_rx_en = 0;
3957                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3958                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3959                         if (reg & IXGBE_FCRTH_FCEN)
3960                                 nb_rx_en++;
3961                 }
3962                 if (nb_rx_en > 1)
3963                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3964                 break;
3965         case ixgbe_fc_rx_pause:
3966                 /*
3967                  * Rx Flow control is enabled and Tx Flow control is
3968                  * disabled by software override. Since there really
3969                  * isn't a way to advertise that we are capable of RX
3970                  * Pause ONLY, we will advertise that we support both
3971                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3972                  * disable the adapter's ability to send PAUSE frames.
3973                  */
3974                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3975                 /*
3976                  * If the count of enabled RX Priority Flow control >1,
3977                  * and the TX pause can not be disabled
3978                  */
3979                 nb_rx_en = 0;
3980                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3981                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3982                         if (reg & IXGBE_FCRTH_FCEN)
3983                                 nb_rx_en++;
3984                 }
3985                 if (nb_rx_en > 1)
3986                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3987                 break;
3988         case ixgbe_fc_tx_pause:
3989                 /*
3990                  * Tx Flow control is enabled, and Rx Flow control is
3991                  * disabled by software override.
3992                  */
3993                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3994                 break;
3995         case ixgbe_fc_full:
3996                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3997                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3998                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3999                 break;
4000         default:
4001                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4002                 ret_val = IXGBE_ERR_CONFIG;
4003                 goto out;
4004         }
4005
4006         /* Set 802.3x based flow control settings. */
4007         mflcn_reg |= IXGBE_MFLCN_DPF;
4008         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4009         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4010
4011         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4012         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4013                 hw->fc.high_water[tc_num]) {
4014                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4015                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4016                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4017         } else {
4018                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4019                 /*
4020                  * In order to prevent Tx hangs when the internal Tx
4021                  * switch is enabled we must set the high water mark
4022                  * to the maximum FCRTH value.  This allows the Tx
4023                  * switch to function even under heavy Rx workloads.
4024                  */
4025                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4026         }
4027         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4028
4029         /* Configure pause time (2 TCs per register) */
4030         reg = hw->fc.pause_time * 0x00010001;
4031         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4032                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4033
4034         /* Configure flow control refresh threshold value */
4035         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4036
4037 out:
4038         return ret_val;
4039 }
4040
4041 static int
4042 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4043 {
4044         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4045         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4046
4047         if (hw->mac.type != ixgbe_mac_82598EB) {
4048                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4049         }
4050         return ret_val;
4051 }
4052
4053 static int
4054 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4055 {
4056         int err;
4057         uint32_t rx_buf_size;
4058         uint32_t max_high_water;
4059         uint8_t tc_num;
4060         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4061         struct ixgbe_hw *hw =
4062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4063         struct ixgbe_dcb_config *dcb_config =
4064                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4065
4066         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4067                 ixgbe_fc_none,
4068                 ixgbe_fc_rx_pause,
4069                 ixgbe_fc_tx_pause,
4070                 ixgbe_fc_full
4071         };
4072
4073         PMD_INIT_FUNC_TRACE();
4074
4075         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4076         tc_num = map[pfc_conf->priority];
4077         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4078         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4079         /*
4080          * At least reserve one Ethernet frame for watermark
4081          * high_water/low_water in kilo bytes for ixgbe
4082          */
4083         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4084         if ((pfc_conf->fc.high_water > max_high_water) ||
4085             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4086                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4087                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4088                 return -EINVAL;
4089         }
4090
4091         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4092         hw->fc.pause_time = pfc_conf->fc.pause_time;
4093         hw->fc.send_xon = pfc_conf->fc.send_xon;
4094         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4095         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4096
4097         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4098
4099         /* Not negotiated is not an error case */
4100         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4101                 return 0;
4102
4103         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4104         return -EIO;
4105 }
4106
4107 static int
4108 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4109                           struct rte_eth_rss_reta_entry64 *reta_conf,
4110                           uint16_t reta_size)
4111 {
4112         uint16_t i, sp_reta_size;
4113         uint8_t j, mask;
4114         uint32_t reta, r;
4115         uint16_t idx, shift;
4116         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4117         uint32_t reta_reg;
4118
4119         PMD_INIT_FUNC_TRACE();
4120
4121         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4122                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4123                         "NIC.");
4124                 return -ENOTSUP;
4125         }
4126
4127         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4128         if (reta_size != sp_reta_size) {
4129                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4130                         "(%d) doesn't match the number hardware can supported "
4131                         "(%d)\n", reta_size, sp_reta_size);
4132                 return -EINVAL;
4133         }
4134
4135         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4136                 idx = i / RTE_RETA_GROUP_SIZE;
4137                 shift = i % RTE_RETA_GROUP_SIZE;
4138                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4139                                                 IXGBE_4_BIT_MASK);
4140                 if (!mask)
4141                         continue;
4142                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4143                 if (mask == IXGBE_4_BIT_MASK)
4144                         r = 0;
4145                 else
4146                         r = IXGBE_READ_REG(hw, reta_reg);
4147                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4148                         if (mask & (0x1 << j))
4149                                 reta |= reta_conf[idx].reta[shift + j] <<
4150                                                         (CHAR_BIT * j);
4151                         else
4152                                 reta |= r & (IXGBE_8_BIT_MASK <<
4153                                                 (CHAR_BIT * j));
4154                 }
4155                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4156         }
4157
4158         return 0;
4159 }
4160
4161 static int
4162 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4163                          struct rte_eth_rss_reta_entry64 *reta_conf,
4164                          uint16_t reta_size)
4165 {
4166         uint16_t i, sp_reta_size;
4167         uint8_t j, mask;
4168         uint32_t reta;
4169         uint16_t idx, shift;
4170         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4171         uint32_t reta_reg;
4172
4173         PMD_INIT_FUNC_TRACE();
4174         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4175         if (reta_size != sp_reta_size) {
4176                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4177                         "(%d) doesn't match the number hardware can supported "
4178                         "(%d)\n", reta_size, sp_reta_size);
4179                 return -EINVAL;
4180         }
4181
4182         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4183                 idx = i / RTE_RETA_GROUP_SIZE;
4184                 shift = i % RTE_RETA_GROUP_SIZE;
4185                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4186                                                 IXGBE_4_BIT_MASK);
4187                 if (!mask)
4188                         continue;
4189
4190                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4191                 reta = IXGBE_READ_REG(hw, reta_reg);
4192                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4193                         if (mask & (0x1 << j))
4194                                 reta_conf[idx].reta[shift + j] =
4195                                         ((reta >> (CHAR_BIT * j)) &
4196                                                 IXGBE_8_BIT_MASK);
4197                 }
4198         }
4199
4200         return 0;
4201 }
4202
4203 static void
4204 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4205                                 uint32_t index, uint32_t pool)
4206 {
4207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4208         uint32_t enable_addr = 1;
4209
4210         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4211 }
4212
4213 static void
4214 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4215 {
4216         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4217
4218         ixgbe_clear_rar(hw, index);
4219 }
4220
4221 static void
4222 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4223 {
4224         ixgbe_remove_rar(dev, 0);
4225
4226         ixgbe_add_rar(dev, addr, 0, 0);
4227 }
4228
4229 static int
4230 is_ixgbe_pmd(const char *driver_name)
4231 {
4232         if (!strstr(driver_name, "ixgbe"))
4233                 return -ENOTSUP;
4234
4235         if (strstr(driver_name, "ixgbe_vf"))
4236                 return -ENOTSUP;
4237
4238         return 0;
4239 }
4240
4241 int
4242 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4243                 struct ether_addr *mac_addr)
4244 {
4245         struct ixgbe_hw *hw;
4246         struct ixgbe_vf_info *vfinfo;
4247         int rar_entry;
4248         uint8_t *new_mac = (uint8_t *)(mac_addr);
4249         struct rte_eth_dev *dev;
4250         struct rte_eth_dev_info dev_info;
4251
4252         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4253
4254         dev = &rte_eth_devices[port];
4255         rte_eth_dev_info_get(port, &dev_info);
4256
4257         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4258                 return -ENOTSUP;
4259
4260         if (vf >= dev_info.max_vfs)
4261                 return -EINVAL;
4262
4263         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4264         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4265         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4266
4267         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4268                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4269                                 ETHER_ADDR_LEN);
4270                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4271                                 IXGBE_RAH_AV);
4272         }
4273         return -EINVAL;
4274 }
4275
4276 static int
4277 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4278 {
4279         uint32_t hlreg0;
4280         uint32_t maxfrs;
4281         struct ixgbe_hw *hw;
4282         struct rte_eth_dev_info dev_info;
4283         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4284
4285         ixgbe_dev_info_get(dev, &dev_info);
4286
4287         /* check that mtu is within the allowed range */
4288         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4289                 return -EINVAL;
4290
4291         /* refuse mtu that requires the support of scattered packets when this
4292          * feature has not been enabled before.
4293          */
4294         if (!dev->data->scattered_rx &&
4295             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4296              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4297                 return -EINVAL;
4298
4299         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4300         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4301
4302         /* switch to jumbo mode if needed */
4303         if (frame_size > ETHER_MAX_LEN) {
4304                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4305                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4306         } else {
4307                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4308                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4309         }
4310         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4311
4312         /* update max frame size */
4313         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4314
4315         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4316         maxfrs &= 0x0000FFFF;
4317         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4318         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4319
4320         return 0;
4321 }
4322
4323 /*
4324  * Virtual Function operations
4325  */
4326 static void
4327 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4328 {
4329         PMD_INIT_FUNC_TRACE();
4330
4331         /* Clear interrupt mask to stop from interrupts being generated */
4332         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4333
4334         IXGBE_WRITE_FLUSH(hw);
4335 }
4336
4337 static void
4338 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4339 {
4340         PMD_INIT_FUNC_TRACE();
4341
4342         /* VF enable interrupt autoclean */
4343         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4344         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4345         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4346
4347         IXGBE_WRITE_FLUSH(hw);
4348 }
4349
4350 static int
4351 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4352 {
4353         struct rte_eth_conf *conf = &dev->data->dev_conf;
4354         struct ixgbe_adapter *adapter =
4355                         (struct ixgbe_adapter *)dev->data->dev_private;
4356
4357         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4358                      dev->data->port_id);
4359
4360         /*
4361          * VF has no ability to enable/disable HW CRC
4362          * Keep the persistent behavior the same as Host PF
4363          */
4364 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4365         if (!conf->rxmode.hw_strip_crc) {
4366                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4367                 conf->rxmode.hw_strip_crc = 1;
4368         }
4369 #else
4370         if (conf->rxmode.hw_strip_crc) {
4371                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4372                 conf->rxmode.hw_strip_crc = 0;
4373         }
4374 #endif
4375
4376         /*
4377          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4378          * allocation or vector Rx preconditions we will reset it.
4379          */
4380         adapter->rx_bulk_alloc_allowed = true;
4381         adapter->rx_vec_allowed = true;
4382
4383         return 0;
4384 }
4385
4386 static int
4387 ixgbevf_dev_start(struct rte_eth_dev *dev)
4388 {
4389         struct ixgbe_hw *hw =
4390                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4391         uint32_t intr_vector = 0;
4392         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4393         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4394
4395         int err, mask = 0;
4396
4397         PMD_INIT_FUNC_TRACE();
4398
4399         hw->mac.ops.reset_hw(hw);
4400         hw->mac.get_link_status = true;
4401
4402         /* negotiate mailbox API version to use with the PF. */
4403         ixgbevf_negotiate_api(hw);
4404
4405         ixgbevf_dev_tx_init(dev);
4406
4407         /* This can fail when allocating mbufs for descriptor rings */
4408         err = ixgbevf_dev_rx_init(dev);
4409         if (err) {
4410                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4411                 ixgbe_dev_clear_queues(dev);
4412                 return err;
4413         }
4414
4415         /* Set vfta */
4416         ixgbevf_set_vfta_all(dev, 1);
4417
4418         /* Set HW strip */
4419         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4420                 ETH_VLAN_EXTEND_MASK;
4421         ixgbevf_vlan_offload_set(dev, mask);
4422
4423         ixgbevf_dev_rxtx_start(dev);
4424
4425         /* check and configure queue intr-vector mapping */
4426         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4427                 intr_vector = dev->data->nb_rx_queues;
4428                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4429                         return -1;
4430         }
4431
4432         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4433                 intr_handle->intr_vec =
4434                         rte_zmalloc("intr_vec",
4435                                     dev->data->nb_rx_queues * sizeof(int), 0);
4436                 if (intr_handle->intr_vec == NULL) {
4437                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4438                                      " intr_vec\n", dev->data->nb_rx_queues);
4439                         return -ENOMEM;
4440                 }
4441         }
4442         ixgbevf_configure_msix(dev);
4443
4444         rte_intr_enable(intr_handle);
4445
4446         /* Re-enable interrupt for VF */
4447         ixgbevf_intr_enable(hw);
4448
4449         return 0;
4450 }
4451
4452 static void
4453 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4454 {
4455         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4456         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4457         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4458
4459         PMD_INIT_FUNC_TRACE();
4460
4461         ixgbevf_intr_disable(hw);
4462
4463         hw->adapter_stopped = 1;
4464         ixgbe_stop_adapter(hw);
4465
4466         /*
4467           * Clear what we set, but we still keep shadow_vfta to
4468           * restore after device starts
4469           */
4470         ixgbevf_set_vfta_all(dev, 0);
4471
4472         /* Clear stored conf */
4473         dev->data->scattered_rx = 0;
4474
4475         ixgbe_dev_clear_queues(dev);
4476
4477         /* Clean datapath event and queue/vec mapping */
4478         rte_intr_efd_disable(intr_handle);
4479         if (intr_handle->intr_vec != NULL) {
4480                 rte_free(intr_handle->intr_vec);
4481                 intr_handle->intr_vec = NULL;
4482         }
4483 }
4484
4485 static void
4486 ixgbevf_dev_close(struct rte_eth_dev *dev)
4487 {
4488         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4489
4490         PMD_INIT_FUNC_TRACE();
4491
4492         ixgbe_reset_hw(hw);
4493
4494         ixgbevf_dev_stop(dev);
4495
4496         ixgbe_dev_free_queues(dev);
4497
4498         /**
4499          * Remove the VF MAC address ro ensure
4500          * that the VF traffic goes to the PF
4501          * after stop, close and detach of the VF
4502          **/
4503         ixgbevf_remove_mac_addr(dev, 0);
4504 }
4505
4506 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4507 {
4508         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4509         struct ixgbe_vfta *shadow_vfta =
4510                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4511         int i = 0, j = 0, vfta = 0, mask = 1;
4512
4513         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4514                 vfta = shadow_vfta->vfta[i];
4515                 if (vfta) {
4516                         mask = 1;
4517                         for (j = 0; j < 32; j++) {
4518                                 if (vfta & mask)
4519                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4520                                                        on, false);
4521                                 mask <<= 1;
4522                         }
4523                 }
4524         }
4525
4526 }
4527
4528 static int
4529 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4530 {
4531         struct ixgbe_hw *hw =
4532                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4533         struct ixgbe_vfta *shadow_vfta =
4534                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4535         uint32_t vid_idx = 0;
4536         uint32_t vid_bit = 0;
4537         int ret = 0;
4538
4539         PMD_INIT_FUNC_TRACE();
4540
4541         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4542         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4543         if (ret) {
4544                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4545                 return ret;
4546         }
4547         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4548         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4549
4550         /* Save what we set and retore it after device reset */
4551         if (on)
4552                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4553         else
4554                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4555
4556         return 0;
4557 }
4558
4559 static void
4560 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4561 {
4562         struct ixgbe_hw *hw =
4563                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4564         uint32_t ctrl;
4565
4566         PMD_INIT_FUNC_TRACE();
4567
4568         if (queue >= hw->mac.max_rx_queues)
4569                 return;
4570
4571         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4572         if (on)
4573                 ctrl |= IXGBE_RXDCTL_VME;
4574         else
4575                 ctrl &= ~IXGBE_RXDCTL_VME;
4576         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4577
4578         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4579 }
4580
4581 static void
4582 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4583 {
4584         struct ixgbe_hw *hw =
4585                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4586         uint16_t i;
4587         int on = 0;
4588
4589         /* VF function only support hw strip feature, others are not support */
4590         if (mask & ETH_VLAN_STRIP_MASK) {
4591                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4592
4593                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4594                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4595         }
4596 }
4597
4598 static int
4599 ixgbe_vt_check(struct ixgbe_hw *hw)
4600 {
4601         uint32_t reg_val;
4602
4603         /* if Virtualization Technology is enabled */
4604         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4605         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4606                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4607                 return -1;
4608         }
4609
4610         return 0;
4611 }
4612
4613 static uint32_t
4614 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4615 {
4616         uint32_t vector = 0;
4617
4618         switch (hw->mac.mc_filter_type) {
4619         case 0:   /* use bits [47:36] of the address */
4620                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4621                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4622                 break;
4623         case 1:   /* use bits [46:35] of the address */
4624                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4625                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4626                 break;
4627         case 2:   /* use bits [45:34] of the address */
4628                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4629                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4630                 break;
4631         case 3:   /* use bits [43:32] of the address */
4632                 vector = ((uc_addr->addr_bytes[4]) |
4633                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4634                 break;
4635         default:  /* Invalid mc_filter_type */
4636                 break;
4637         }
4638
4639         /* vector can only be 12-bits or boundary will be exceeded */
4640         vector &= 0xFFF;
4641         return vector;
4642 }
4643
4644 static int
4645 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4646                         uint8_t on)
4647 {
4648         uint32_t vector;
4649         uint32_t uta_idx;
4650         uint32_t reg_val;
4651         uint32_t uta_shift;
4652         uint32_t rc;
4653         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4654         const uint32_t ixgbe_uta_bit_shift = 5;
4655         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4656         const uint32_t bit1 = 0x1;
4657
4658         struct ixgbe_hw *hw =
4659                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4660         struct ixgbe_uta_info *uta_info =
4661                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4662
4663         /* The UTA table only exists on 82599 hardware and newer */
4664         if (hw->mac.type < ixgbe_mac_82599EB)
4665                 return -ENOTSUP;
4666
4667         vector = ixgbe_uta_vector(hw, mac_addr);
4668         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4669         uta_shift = vector & ixgbe_uta_bit_mask;
4670
4671         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4672         if (rc == on)
4673                 return 0;
4674
4675         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4676         if (on) {
4677                 uta_info->uta_in_use++;
4678                 reg_val |= (bit1 << uta_shift);
4679                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4680         } else {
4681                 uta_info->uta_in_use--;
4682                 reg_val &= ~(bit1 << uta_shift);
4683                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4684         }
4685
4686         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4687
4688         if (uta_info->uta_in_use > 0)
4689                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4690                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4691         else
4692                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4693
4694         return 0;
4695 }
4696
4697 static int
4698 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4699 {
4700         int i;
4701         struct ixgbe_hw *hw =
4702                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4703         struct ixgbe_uta_info *uta_info =
4704                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4705
4706         /* The UTA table only exists on 82599 hardware and newer */
4707         if (hw->mac.type < ixgbe_mac_82599EB)
4708                 return -ENOTSUP;
4709
4710         if (on) {
4711                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4712                         uta_info->uta_shadow[i] = ~0;
4713                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4714                 }
4715         } else {
4716                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4717                         uta_info->uta_shadow[i] = 0;
4718                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4719                 }
4720         }
4721         return 0;
4722
4723 }
4724
4725 uint32_t
4726 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4727 {
4728         uint32_t new_val = orig_val;
4729
4730         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4731                 new_val |= IXGBE_VMOLR_AUPE;
4732         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4733                 new_val |= IXGBE_VMOLR_ROMPE;
4734         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4735                 new_val |= IXGBE_VMOLR_ROPE;
4736         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4737                 new_val |= IXGBE_VMOLR_BAM;
4738         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4739                 new_val |= IXGBE_VMOLR_MPE;
4740
4741         return new_val;
4742 }
4743
4744
4745 int
4746 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4747 {
4748         struct ixgbe_hw *hw;
4749         struct ixgbe_mac_info *mac;
4750         struct rte_eth_dev *dev;
4751         struct rte_eth_dev_info dev_info;
4752
4753         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4754
4755         dev = &rte_eth_devices[port];
4756         rte_eth_dev_info_get(port, &dev_info);
4757
4758         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4759                 return -ENOTSUP;
4760
4761         if (vf >= dev_info.max_vfs)
4762                 return -EINVAL;
4763
4764         if (on > 1)
4765                 return -EINVAL;
4766
4767         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4768         mac = &hw->mac;
4769
4770         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4771
4772         return 0;
4773 }
4774
4775 int
4776 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4777 {
4778         struct ixgbe_hw *hw;
4779         struct ixgbe_mac_info *mac;
4780         struct rte_eth_dev *dev;
4781         struct rte_eth_dev_info dev_info;
4782
4783         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4784
4785         dev = &rte_eth_devices[port];
4786         rte_eth_dev_info_get(port, &dev_info);
4787
4788         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4789                 return -ENOTSUP;
4790
4791         if (vf >= dev_info.max_vfs)
4792                 return -EINVAL;
4793
4794         if (on > 1)
4795                 return -EINVAL;
4796
4797         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4798         mac = &hw->mac;
4799         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4800
4801         return 0;
4802 }
4803
4804 int
4805 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4806 {
4807         struct ixgbe_hw *hw;
4808         uint32_t ctrl;
4809         struct rte_eth_dev *dev;
4810         struct rte_eth_dev_info dev_info;
4811
4812         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4813
4814         dev = &rte_eth_devices[port];
4815         rte_eth_dev_info_get(port, &dev_info);
4816
4817         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4818                 return -ENOTSUP;
4819
4820         if (vf >= dev_info.max_vfs)
4821                 return -EINVAL;
4822
4823         if (vlan_id > ETHER_MAX_VLAN_ID)
4824                 return -EINVAL;
4825
4826         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4827         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4828         if (vlan_id) {
4829                 ctrl = vlan_id;
4830                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4831         } else {
4832                 ctrl = 0;
4833         }
4834
4835         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4836
4837         return 0;
4838 }
4839
4840 int
4841 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4842 {
4843         struct ixgbe_hw *hw;
4844         uint32_t ctrl;
4845         struct rte_eth_dev *dev;
4846         struct rte_eth_dev_info dev_info;
4847
4848         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4849
4850         dev = &rte_eth_devices[port];
4851         rte_eth_dev_info_get(port, &dev_info);
4852
4853         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4854                 return -ENOTSUP;
4855
4856         if (on > 1)
4857                 return -EINVAL;
4858
4859         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4860         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4861         /* enable or disable VMDQ loopback */
4862         if (on)
4863                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4864         else
4865                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4866
4867         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4868
4869         return 0;
4870 }
4871
4872 int
4873 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4874 {
4875         struct ixgbe_hw *hw;
4876         uint32_t reg_value;
4877         int i;
4878         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4879         struct rte_eth_dev *dev;
4880         struct rte_eth_dev_info dev_info;
4881
4882         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4883
4884         dev = &rte_eth_devices[port];
4885         rte_eth_dev_info_get(port, &dev_info);
4886
4887         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4888                 return -ENOTSUP;
4889
4890         if (on > 1)
4891                 return -EINVAL;
4892
4893         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4894         for (i = 0; i <= num_queues; i++) {
4895                 reg_value = IXGBE_QDE_WRITE |
4896                                 (i << IXGBE_QDE_IDX_SHIFT) |
4897                                 (on & IXGBE_QDE_ENABLE);
4898                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4899         }
4900
4901         return 0;
4902 }
4903
4904 int
4905 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4906 {
4907         struct ixgbe_hw *hw;
4908         uint32_t reg_value;
4909         struct rte_eth_dev *dev;
4910         struct rte_eth_dev_info dev_info;
4911
4912         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4913
4914         dev = &rte_eth_devices[port];
4915         rte_eth_dev_info_get(port, &dev_info);
4916
4917         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4918                 return -ENOTSUP;
4919
4920         /* only support VF's 0 to 63 */
4921         if ((vf >= dev_info.max_vfs) || (vf > 63))
4922                 return -EINVAL;
4923
4924         if (on > 1)
4925                 return -EINVAL;
4926
4927         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4928         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4929         if (on)
4930                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4931         else
4932                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4933
4934         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4935
4936         return 0;
4937 }
4938
4939 int
4940 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4941 {
4942         struct rte_eth_dev *dev;
4943         struct rte_eth_dev_info dev_info;
4944         uint16_t queues_per_pool;
4945         uint32_t q;
4946
4947         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4948
4949         dev = &rte_eth_devices[port];
4950         rte_eth_dev_info_get(port, &dev_info);
4951
4952         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4953                 return -ENOTSUP;
4954
4955         if (vf >= dev_info.max_vfs)
4956                 return -EINVAL;
4957
4958         if (on > 1)
4959                 return -EINVAL;
4960
4961         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
4962
4963         /* The PF has 128 queue pairs and in SRIOV configuration
4964          * those queues will be assigned to VF's, so RXDCTL
4965          * registers will be dealing with queues which will be
4966          * assigned to VF's.
4967          * Let's say we have SRIOV configured with 31 VF's then the
4968          * first 124 queues 0-123 will be allocated to VF's and only
4969          * the last 4 queues 123-127 will be assigned to the PF.
4970          */
4971
4972         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
4973
4974         for (q = 0; q < queues_per_pool; q++)
4975                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
4976                                 q + vf * queues_per_pool, on);
4977         return 0;
4978 }
4979
4980 int
4981 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
4982 {
4983         int val = 0;
4984         struct rte_eth_dev *dev;
4985         struct rte_eth_dev_info dev_info;
4986         struct ixgbe_hw *hw;
4987         uint32_t vmolr;
4988
4989         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4990
4991         dev = &rte_eth_devices[port];
4992         rte_eth_dev_info_get(port, &dev_info);
4993
4994         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4995                 return -ENOTSUP;
4996
4997         if (vf >= dev_info.max_vfs)
4998                 return -EINVAL;
4999
5000         if (on > 1)
5001                 return -EINVAL;
5002
5003         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5004         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5005
5006         if (hw->mac.type == ixgbe_mac_82598EB) {
5007                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5008                              " on 82599 hardware and newer");
5009                 return -ENOTSUP;
5010         }
5011         if (ixgbe_vt_check(hw) < 0)
5012                 return -ENOTSUP;
5013
5014         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5015
5016         if (on)
5017                 vmolr |= val;
5018         else
5019                 vmolr &= ~val;
5020
5021         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5022
5023         return 0;
5024 }
5025
5026 int
5027 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5028 {
5029         struct rte_eth_dev *dev;
5030         struct rte_eth_dev_info dev_info;
5031         uint32_t reg, addr;
5032         uint32_t val;
5033         const uint8_t bit1 = 0x1;
5034         struct ixgbe_hw *hw;
5035
5036         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5037
5038         dev = &rte_eth_devices[port];
5039         rte_eth_dev_info_get(port, &dev_info);
5040
5041         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5042                 return -ENOTSUP;
5043
5044         if (vf >= dev_info.max_vfs)
5045                 return -EINVAL;
5046
5047         if (on > 1)
5048                 return -EINVAL;
5049
5050         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051
5052         if (ixgbe_vt_check(hw) < 0)
5053                 return -ENOTSUP;
5054
5055         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5056         if (vf >= 32) {
5057                 addr = IXGBE_VFRE(1);
5058                 val = bit1 << (vf - 32);
5059         } else {
5060                 addr = IXGBE_VFRE(0);
5061                 val = bit1 << vf;
5062         }
5063
5064         reg = IXGBE_READ_REG(hw, addr);
5065
5066         if (on)
5067                 reg |= val;
5068         else
5069                 reg &= ~val;
5070
5071         IXGBE_WRITE_REG(hw, addr, reg);
5072
5073         return 0;
5074 }
5075
5076 int
5077 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5078 {
5079         struct rte_eth_dev *dev;
5080         struct rte_eth_dev_info dev_info;
5081         uint32_t reg, addr;
5082         uint32_t val;
5083         const uint8_t bit1 = 0x1;
5084
5085         struct ixgbe_hw *hw;
5086
5087         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5088
5089         dev = &rte_eth_devices[port];
5090         rte_eth_dev_info_get(port, &dev_info);
5091
5092         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5093                 return -ENOTSUP;
5094
5095         if (vf >= dev_info.max_vfs)
5096                 return -EINVAL;
5097
5098         if (on > 1)
5099                 return -EINVAL;
5100
5101         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5102         if (ixgbe_vt_check(hw) < 0)
5103                 return -ENOTSUP;
5104
5105         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5106         if (vf >= 32) {
5107                 addr = IXGBE_VFTE(1);
5108                 val = bit1 << (vf - 32);
5109         } else {
5110                 addr = IXGBE_VFTE(0);
5111                 val = bit1 << vf;
5112         }
5113
5114         reg = IXGBE_READ_REG(hw, addr);
5115
5116         if (on)
5117                 reg |= val;
5118         else
5119                 reg &= ~val;
5120
5121         IXGBE_WRITE_REG(hw, addr, reg);
5122
5123         return 0;
5124 }
5125
5126 int
5127 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5128                         uint64_t vf_mask, uint8_t vlan_on)
5129 {
5130         struct rte_eth_dev *dev;
5131         struct rte_eth_dev_info dev_info;
5132         int ret = 0;
5133         uint16_t vf_idx;
5134         struct ixgbe_hw *hw;
5135
5136         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5137
5138         dev = &rte_eth_devices[port];
5139         rte_eth_dev_info_get(port, &dev_info);
5140
5141         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5142                 return -ENOTSUP;
5143
5144         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5145                 return -EINVAL;
5146
5147         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5148         if (ixgbe_vt_check(hw) < 0)
5149                 return -ENOTSUP;
5150
5151         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5152                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5153                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5154                                                    vlan_on, false);
5155                         if (ret < 0)
5156                                 return ret;
5157                 }
5158         }
5159
5160         return ret;
5161 }
5162
5163 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5164         uint16_t tx_rate, uint64_t q_msk)
5165 {
5166         struct rte_eth_dev *dev;
5167         struct rte_eth_dev_info dev_info;
5168         struct ixgbe_hw *hw;
5169         struct ixgbe_vf_info *vfinfo;
5170         struct rte_eth_link link;
5171         uint8_t  nb_q_per_pool;
5172         uint32_t queue_stride;
5173         uint32_t queue_idx, idx = 0, vf_idx;
5174         uint32_t queue_end;
5175         uint16_t total_rate = 0;
5176         struct rte_pci_device *pci_dev;
5177
5178         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5179
5180         dev = &rte_eth_devices[port];
5181         rte_eth_dev_info_get(port, &dev_info);
5182         rte_eth_link_get_nowait(port, &link);
5183
5184         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5185                 return -ENOTSUP;
5186
5187         if (vf >= dev_info.max_vfs)
5188                 return -EINVAL;
5189
5190         if (tx_rate > link.link_speed)
5191                 return -EINVAL;
5192
5193         if (q_msk == 0)
5194                 return 0;
5195
5196         pci_dev = IXGBE_DEV_TO_PCI(dev);
5197         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5198         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5199         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5200         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5201         queue_idx = vf * queue_stride;
5202         queue_end = queue_idx + nb_q_per_pool - 1;
5203         if (queue_end >= hw->mac.max_tx_queues)
5204                 return -EINVAL;
5205
5206         if (vfinfo) {
5207                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5208                         if (vf_idx == vf)
5209                                 continue;
5210                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5211                                 idx++)
5212                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5213                 }
5214         } else {
5215                 return -EINVAL;
5216         }
5217
5218         /* Store tx_rate for this vf. */
5219         for (idx = 0; idx < nb_q_per_pool; idx++) {
5220                 if (((uint64_t)0x1 << idx) & q_msk) {
5221                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5222                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5223                         total_rate += tx_rate;
5224                 }
5225         }
5226
5227         if (total_rate > dev->data->dev_link.link_speed) {
5228                 /* Reset stored TX rate of the VF if it causes exceed
5229                  * link speed.
5230                  */
5231                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5232                 return -EINVAL;
5233         }
5234
5235         /* Set RTTBCNRC of each queue/pool for vf X  */
5236         for (; queue_idx <= queue_end; queue_idx++) {
5237                 if (0x1 & q_msk)
5238                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5239                 q_msk = q_msk >> 1;
5240         }
5241
5242         return 0;
5243 }
5244
5245 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5246 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5247 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5248 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5249 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5250         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5251         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5252
5253 static int
5254 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5255                         struct rte_eth_mirror_conf *mirror_conf,
5256                         uint8_t rule_id, uint8_t on)
5257 {
5258         uint32_t mr_ctl, vlvf;
5259         uint32_t mp_lsb = 0;
5260         uint32_t mv_msb = 0;
5261         uint32_t mv_lsb = 0;
5262         uint32_t mp_msb = 0;
5263         uint8_t i = 0;
5264         int reg_index = 0;
5265         uint64_t vlan_mask = 0;
5266
5267         const uint8_t pool_mask_offset = 32;
5268         const uint8_t vlan_mask_offset = 32;
5269         const uint8_t dst_pool_offset = 8;
5270         const uint8_t rule_mr_offset  = 4;
5271         const uint8_t mirror_rule_mask = 0x0F;
5272
5273         struct ixgbe_mirror_info *mr_info =
5274                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5275         struct ixgbe_hw *hw =
5276                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5277         uint8_t mirror_type = 0;
5278
5279         if (ixgbe_vt_check(hw) < 0)
5280                 return -ENOTSUP;
5281
5282         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5283                 return -EINVAL;
5284
5285         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5286                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5287                         mirror_conf->rule_type);
5288                 return -EINVAL;
5289         }
5290
5291         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5292                 mirror_type |= IXGBE_MRCTL_VLME;
5293                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5294                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5295                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5296                                 /* search vlan id related pool vlan filter index */
5297                                 reg_index = ixgbe_find_vlvf_slot(hw,
5298                                                  mirror_conf->vlan.vlan_id[i],
5299                                                  false);
5300                                 if (reg_index < 0)
5301                                         return -EINVAL;
5302                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5303                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5304                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5305                                       mirror_conf->vlan.vlan_id[i]))
5306                                         vlan_mask |= (1ULL << reg_index);
5307                                 else
5308                                         return -EINVAL;
5309                         }
5310                 }
5311
5312                 if (on) {
5313                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5314                         mv_msb = vlan_mask >> vlan_mask_offset;
5315
5316                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5317                                                 mirror_conf->vlan.vlan_mask;
5318                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5319                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5320                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5321                                                 mirror_conf->vlan.vlan_id[i];
5322                         }
5323                 } else {
5324                         mv_lsb = 0;
5325                         mv_msb = 0;
5326                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5327                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5328                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5329                 }
5330         }
5331
5332         /*
5333          * if enable pool mirror, write related pool mask register,if disable
5334          * pool mirror, clear PFMRVM register
5335          */
5336         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5337                 mirror_type |= IXGBE_MRCTL_VPME;
5338                 if (on) {
5339                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5340                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5341                         mr_info->mr_conf[rule_id].pool_mask =
5342                                         mirror_conf->pool_mask;
5343
5344                 } else {
5345                         mp_lsb = 0;
5346                         mp_msb = 0;
5347                         mr_info->mr_conf[rule_id].pool_mask = 0;
5348                 }
5349         }
5350         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5351                 mirror_type |= IXGBE_MRCTL_UPME;
5352         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5353                 mirror_type |= IXGBE_MRCTL_DPME;
5354
5355         /* read  mirror control register and recalculate it */
5356         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5357
5358         if (on) {
5359                 mr_ctl |= mirror_type;
5360                 mr_ctl &= mirror_rule_mask;
5361                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5362         } else
5363                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5364
5365         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5366         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5367
5368         /* write mirrror control  register */
5369         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5370
5371         /* write pool mirrror control  register */
5372         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5373                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5374                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5375                                 mp_msb);
5376         }
5377         /* write VLAN mirrror control  register */
5378         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5379                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5380                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5381                                 mv_msb);
5382         }
5383
5384         return 0;
5385 }
5386
5387 static int
5388 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5389 {
5390         int mr_ctl = 0;
5391         uint32_t lsb_val = 0;
5392         uint32_t msb_val = 0;
5393         const uint8_t rule_mr_offset = 4;
5394
5395         struct ixgbe_hw *hw =
5396                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5397         struct ixgbe_mirror_info *mr_info =
5398                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5399
5400         if (ixgbe_vt_check(hw) < 0)
5401                 return -ENOTSUP;
5402
5403         memset(&mr_info->mr_conf[rule_id], 0,
5404                 sizeof(struct rte_eth_mirror_conf));
5405
5406         /* clear PFVMCTL register */
5407         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5408
5409         /* clear pool mask register */
5410         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5411         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5412
5413         /* clear vlan mask register */
5414         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5415         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5416
5417         return 0;
5418 }
5419
5420 static int
5421 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5422 {
5423         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5424         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5425         uint32_t mask;
5426         struct ixgbe_hw *hw =
5427                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5428
5429         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5430         mask |= (1 << IXGBE_MISC_VEC_ID);
5431         RTE_SET_USED(queue_id);
5432         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5433
5434         rte_intr_enable(intr_handle);
5435
5436         return 0;
5437 }
5438
5439 static int
5440 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5441 {
5442         uint32_t mask;
5443         struct ixgbe_hw *hw =
5444                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5445
5446         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5447         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5448         RTE_SET_USED(queue_id);
5449         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5450
5451         return 0;
5452 }
5453
5454 static int
5455 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5456 {
5457         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5458         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5459         uint32_t mask;
5460         struct ixgbe_hw *hw =
5461                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5462         struct ixgbe_interrupt *intr =
5463                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5464
5465         if (queue_id < 16) {
5466                 ixgbe_disable_intr(hw);
5467                 intr->mask |= (1 << queue_id);
5468                 ixgbe_enable_intr(dev);
5469         } else if (queue_id < 32) {
5470                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5471                 mask &= (1 << queue_id);
5472                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5473         } else if (queue_id < 64) {
5474                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5475                 mask &= (1 << (queue_id - 32));
5476                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5477         }
5478         rte_intr_enable(intr_handle);
5479
5480         return 0;
5481 }
5482
5483 static int
5484 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5485 {
5486         uint32_t mask;
5487         struct ixgbe_hw *hw =
5488                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5489         struct ixgbe_interrupt *intr =
5490                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5491
5492         if (queue_id < 16) {
5493                 ixgbe_disable_intr(hw);
5494                 intr->mask &= ~(1 << queue_id);
5495                 ixgbe_enable_intr(dev);
5496         } else if (queue_id < 32) {
5497                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5498                 mask &= ~(1 << queue_id);
5499                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5500         } else if (queue_id < 64) {
5501                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5502                 mask &= ~(1 << (queue_id - 32));
5503                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5504         }
5505
5506         return 0;
5507 }
5508
5509 static void
5510 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5511                      uint8_t queue, uint8_t msix_vector)
5512 {
5513         uint32_t tmp, idx;
5514
5515         if (direction == -1) {
5516                 /* other causes */
5517                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5518                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5519                 tmp &= ~0xFF;
5520                 tmp |= msix_vector;
5521                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5522         } else {
5523                 /* rx or tx cause */
5524                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5525                 idx = ((16 * (queue & 1)) + (8 * direction));
5526                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5527                 tmp &= ~(0xFF << idx);
5528                 tmp |= (msix_vector << idx);
5529                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5530         }
5531 }
5532
5533 /**
5534  * set the IVAR registers, mapping interrupt causes to vectors
5535  * @param hw
5536  *  pointer to ixgbe_hw struct
5537  * @direction
5538  *  0 for Rx, 1 for Tx, -1 for other causes
5539  * @queue
5540  *  queue to map the corresponding interrupt to
5541  * @msix_vector
5542  *  the vector to map to the corresponding queue
5543  */
5544 static void
5545 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5546                    uint8_t queue, uint8_t msix_vector)
5547 {
5548         uint32_t tmp, idx;
5549
5550         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5551         if (hw->mac.type == ixgbe_mac_82598EB) {
5552                 if (direction == -1)
5553                         direction = 0;
5554                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5555                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5556                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5557                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5558                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5559         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5560                         (hw->mac.type == ixgbe_mac_X540)) {
5561                 if (direction == -1) {
5562                         /* other causes */
5563                         idx = ((queue & 1) * 8);
5564                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5565                         tmp &= ~(0xFF << idx);
5566                         tmp |= (msix_vector << idx);
5567                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5568                 } else {
5569                         /* rx or tx causes */
5570                         idx = ((16 * (queue & 1)) + (8 * direction));
5571                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5572                         tmp &= ~(0xFF << idx);
5573                         tmp |= (msix_vector << idx);
5574                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5575                 }
5576         }
5577 }
5578
5579 static void
5580 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5581 {
5582         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5583         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5584         struct ixgbe_hw *hw =
5585                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5586         uint32_t q_idx;
5587         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5588
5589         /* Configure VF other cause ivar */
5590         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5591
5592         /* won't configure msix register if no mapping is done
5593          * between intr vector and event fd.
5594          */
5595         if (!rte_intr_dp_is_en(intr_handle))
5596                 return;
5597
5598         /* Configure all RX queues of VF */
5599         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5600                 /* Force all queue use vector 0,
5601                  * as IXGBE_VF_MAXMSIVECOTR = 1
5602                  */
5603                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5604                 intr_handle->intr_vec[q_idx] = vector_idx;
5605         }
5606 }
5607
5608 /**
5609  * Sets up the hardware to properly generate MSI-X interrupts
5610  * @hw
5611  *  board private structure
5612  */
5613 static void
5614 ixgbe_configure_msix(struct rte_eth_dev *dev)
5615 {
5616         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5617         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5618         struct ixgbe_hw *hw =
5619                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5620         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5621         uint32_t vec = IXGBE_MISC_VEC_ID;
5622         uint32_t mask;
5623         uint32_t gpie;
5624
5625         /* won't configure msix register if no mapping is done
5626          * between intr vector and event fd
5627          */
5628         if (!rte_intr_dp_is_en(intr_handle))
5629                 return;
5630
5631         if (rte_intr_allow_others(intr_handle))
5632                 vec = base = IXGBE_RX_VEC_START;
5633
5634         /* setup GPIE for MSI-x mode */
5635         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5636         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5637                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5638         /* auto clearing and auto setting corresponding bits in EIMS
5639          * when MSI-X interrupt is triggered
5640          */
5641         if (hw->mac.type == ixgbe_mac_82598EB) {
5642                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5643         } else {
5644                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5645                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5646         }
5647         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5648
5649         /* Populate the IVAR table and set the ITR values to the
5650          * corresponding register.
5651          */
5652         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5653              queue_id++) {
5654                 /* by default, 1:1 mapping */
5655                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5656                 intr_handle->intr_vec[queue_id] = vec;
5657                 if (vec < base + intr_handle->nb_efd - 1)
5658                         vec++;
5659         }
5660
5661         switch (hw->mac.type) {
5662         case ixgbe_mac_82598EB:
5663                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5664                                    IXGBE_MISC_VEC_ID);
5665                 break;
5666         case ixgbe_mac_82599EB:
5667         case ixgbe_mac_X540:
5668                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5669                 break;
5670         default:
5671                 break;
5672         }
5673         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5674                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5675
5676         /* set up to autoclear timer, and the vectors */
5677         mask = IXGBE_EIMS_ENABLE_MASK;
5678         mask &= ~(IXGBE_EIMS_OTHER |
5679                   IXGBE_EIMS_MAILBOX |
5680                   IXGBE_EIMS_LSC);
5681
5682         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5683 }
5684
5685 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5686         uint16_t queue_idx, uint16_t tx_rate)
5687 {
5688         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5689         uint32_t rf_dec, rf_int;
5690         uint32_t bcnrc_val;
5691         uint16_t link_speed = dev->data->dev_link.link_speed;
5692
5693         if (queue_idx >= hw->mac.max_tx_queues)
5694                 return -EINVAL;
5695
5696         if (tx_rate != 0) {
5697                 /* Calculate the rate factor values to set */
5698                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5699                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5700                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5701
5702                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5703                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5704                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5705                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5706         } else {
5707                 bcnrc_val = 0;
5708         }
5709
5710         /*
5711          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5712          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5713          * set as 0x4.
5714          */
5715         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5716                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5717                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5718                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5719                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5720         else
5721                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5722                         IXGBE_MMW_SIZE_DEFAULT);
5723
5724         /* Set RTTBCNRC of queue X */
5725         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5726         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5727         IXGBE_WRITE_FLUSH(hw);
5728
5729         return 0;
5730 }
5731
5732 static void
5733 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5734                      __attribute__((unused)) uint32_t index,
5735                      __attribute__((unused)) uint32_t pool)
5736 {
5737         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5738         int diag;
5739
5740         /*
5741          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5742          * operation. Trap this case to avoid exhausting the [very limited]
5743          * set of PF resources used to store VF MAC addresses.
5744          */
5745         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5746                 return;
5747         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5748         if (diag == 0)
5749                 return;
5750         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5751 }
5752
5753 static void
5754 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5755 {
5756         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5757         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5758         struct ether_addr *mac_addr;
5759         uint32_t i;
5760         int diag;
5761
5762         /*
5763          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5764          * not support the deletion of a given MAC address.
5765          * Instead, it imposes to delete all MAC addresses, then to add again
5766          * all MAC addresses with the exception of the one to be deleted.
5767          */
5768         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5769
5770         /*
5771          * Add again all MAC addresses, with the exception of the deleted one
5772          * and of the permanent MAC address.
5773          */
5774         for (i = 0, mac_addr = dev->data->mac_addrs;
5775              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5776                 /* Skip the deleted MAC address */
5777                 if (i == index)
5778                         continue;
5779                 /* Skip NULL MAC addresses */
5780                 if (is_zero_ether_addr(mac_addr))
5781                         continue;
5782                 /* Skip the permanent MAC address */
5783                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5784                         continue;
5785                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5786                 if (diag != 0)
5787                         PMD_DRV_LOG(ERR,
5788                                     "Adding again MAC address "
5789                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5790                                     "diag=%d",
5791                                     mac_addr->addr_bytes[0],
5792                                     mac_addr->addr_bytes[1],
5793                                     mac_addr->addr_bytes[2],
5794                                     mac_addr->addr_bytes[3],
5795                                     mac_addr->addr_bytes[4],
5796                                     mac_addr->addr_bytes[5],
5797                                     diag);
5798         }
5799 }
5800
5801 static void
5802 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5803 {
5804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5805
5806         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5807 }
5808
5809 #define MAC_TYPE_FILTER_SUP(type)    do {\
5810         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5811                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5812                 (type) != ixgbe_mac_X550EM_a)\
5813                 return -ENOTSUP;\
5814 } while (0)
5815
5816 static int
5817 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5818                         struct rte_eth_syn_filter *filter,
5819                         bool add)
5820 {
5821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5822         struct ixgbe_filter_info *filter_info =
5823                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5824         uint32_t syn_info;
5825         uint32_t synqf;
5826
5827         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5828                 return -EINVAL;
5829
5830         syn_info = filter_info->syn_info;
5831
5832         if (add) {
5833                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5834                         return -EINVAL;
5835                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5836                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5837
5838                 if (filter->hig_pri)
5839                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5840                 else
5841                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5842         } else {
5843                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5844                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5845                         return -ENOENT;
5846                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5847         }
5848
5849         filter_info->syn_info = synqf;
5850         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5851         IXGBE_WRITE_FLUSH(hw);
5852         return 0;
5853 }
5854
5855 static int
5856 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5857                         struct rte_eth_syn_filter *filter)
5858 {
5859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5860         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5861
5862         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5863                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5864                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5865                 return 0;
5866         }
5867         return -ENOENT;
5868 }
5869
5870 static int
5871 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5872                         enum rte_filter_op filter_op,
5873                         void *arg)
5874 {
5875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5876         int ret;
5877
5878         MAC_TYPE_FILTER_SUP(hw->mac.type);
5879
5880         if (filter_op == RTE_ETH_FILTER_NOP)
5881                 return 0;
5882
5883         if (arg == NULL) {
5884                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5885                             filter_op);
5886                 return -EINVAL;
5887         }
5888
5889         switch (filter_op) {
5890         case RTE_ETH_FILTER_ADD:
5891                 ret = ixgbe_syn_filter_set(dev,
5892                                 (struct rte_eth_syn_filter *)arg,
5893                                 TRUE);
5894                 break;
5895         case RTE_ETH_FILTER_DELETE:
5896                 ret = ixgbe_syn_filter_set(dev,
5897                                 (struct rte_eth_syn_filter *)arg,
5898                                 FALSE);
5899                 break;
5900         case RTE_ETH_FILTER_GET:
5901                 ret = ixgbe_syn_filter_get(dev,
5902                                 (struct rte_eth_syn_filter *)arg);
5903                 break;
5904         default:
5905                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5906                 ret = -EINVAL;
5907                 break;
5908         }
5909
5910         return ret;
5911 }
5912
5913
5914 static inline enum ixgbe_5tuple_protocol
5915 convert_protocol_type(uint8_t protocol_value)
5916 {
5917         if (protocol_value == IPPROTO_TCP)
5918                 return IXGBE_FILTER_PROTOCOL_TCP;
5919         else if (protocol_value == IPPROTO_UDP)
5920                 return IXGBE_FILTER_PROTOCOL_UDP;
5921         else if (protocol_value == IPPROTO_SCTP)
5922                 return IXGBE_FILTER_PROTOCOL_SCTP;
5923         else
5924                 return IXGBE_FILTER_PROTOCOL_NONE;
5925 }
5926
5927 /*
5928  * add a 5tuple filter
5929  *
5930  * @param
5931  * dev: Pointer to struct rte_eth_dev.
5932  * index: the index the filter allocates.
5933  * filter: ponter to the filter that will be added.
5934  * rx_queue: the queue id the filter assigned to.
5935  *
5936  * @return
5937  *    - On success, zero.
5938  *    - On failure, a negative value.
5939  */
5940 static int
5941 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5942                         struct ixgbe_5tuple_filter *filter)
5943 {
5944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5945         struct ixgbe_filter_info *filter_info =
5946                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5947         int i, idx, shift;
5948         uint32_t ftqf, sdpqf;
5949         uint32_t l34timir = 0;
5950         uint8_t mask = 0xff;
5951
5952         /*
5953          * look for an unused 5tuple filter index,
5954          * and insert the filter to list.
5955          */
5956         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5957                 idx = i / (sizeof(uint32_t) * NBBY);
5958                 shift = i % (sizeof(uint32_t) * NBBY);
5959                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5960                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5961                         filter->index = i;
5962                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5963                                           filter,
5964                                           entries);
5965                         break;
5966                 }
5967         }
5968         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5969                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5970                 return -ENOSYS;
5971         }
5972
5973         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5974                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5975         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5976
5977         ftqf = (uint32_t)(filter->filter_info.proto &
5978                 IXGBE_FTQF_PROTOCOL_MASK);
5979         ftqf |= (uint32_t)((filter->filter_info.priority &
5980                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5981         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5982                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5983         if (filter->filter_info.dst_ip_mask == 0)
5984                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5985         if (filter->filter_info.src_port_mask == 0)
5986                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5987         if (filter->filter_info.dst_port_mask == 0)
5988                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5989         if (filter->filter_info.proto_mask == 0)
5990                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5991         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5992         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5993         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5994
5995         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5996         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5997         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5998         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5999
6000         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6001         l34timir |= (uint32_t)(filter->queue <<
6002                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6003         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6004         return 0;
6005 }
6006
6007 /*
6008  * remove a 5tuple filter
6009  *
6010  * @param
6011  * dev: Pointer to struct rte_eth_dev.
6012  * filter: the pointer of the filter will be removed.
6013  */
6014 static void
6015 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6016                         struct ixgbe_5tuple_filter *filter)
6017 {
6018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6019         struct ixgbe_filter_info *filter_info =
6020                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6021         uint16_t index = filter->index;
6022
6023         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6024                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6025         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6026         rte_free(filter);
6027
6028         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6029         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6030         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6031         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6032         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6033 }
6034
6035 static int
6036 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6037 {
6038         struct ixgbe_hw *hw;
6039         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6040
6041         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6042
6043         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6044                 return -EINVAL;
6045
6046         /* refuse mtu that requires the support of scattered packets when this
6047          * feature has not been enabled before.
6048          */
6049         if (!dev->data->scattered_rx &&
6050             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6051              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6052                 return -EINVAL;
6053
6054         /*
6055          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6056          * request of the version 2.0 of the mailbox API.
6057          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6058          * of the mailbox API.
6059          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6060          * prior to 3.11.33 which contains the following change:
6061          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6062          */
6063         ixgbevf_rlpml_set_vf(hw, max_frame);
6064
6065         /* update max frame size */
6066         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6067         return 0;
6068 }
6069
6070 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
6071         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6072                 return -ENOTSUP;\
6073 } while (0)
6074
6075 static inline struct ixgbe_5tuple_filter *
6076 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6077                         struct ixgbe_5tuple_filter_info *key)
6078 {
6079         struct ixgbe_5tuple_filter *it;
6080
6081         TAILQ_FOREACH(it, filter_list, entries) {
6082                 if (memcmp(key, &it->filter_info,
6083                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6084                         return it;
6085                 }
6086         }
6087         return NULL;
6088 }
6089
6090 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6091 static inline int
6092 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6093                         struct ixgbe_5tuple_filter_info *filter_info)
6094 {
6095         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6096                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6097                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6098                 return -EINVAL;
6099
6100         switch (filter->dst_ip_mask) {
6101         case UINT32_MAX:
6102                 filter_info->dst_ip_mask = 0;
6103                 filter_info->dst_ip = filter->dst_ip;
6104                 break;
6105         case 0:
6106                 filter_info->dst_ip_mask = 1;
6107                 break;
6108         default:
6109                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6110                 return -EINVAL;
6111         }
6112
6113         switch (filter->src_ip_mask) {
6114         case UINT32_MAX:
6115                 filter_info->src_ip_mask = 0;
6116                 filter_info->src_ip = filter->src_ip;
6117                 break;
6118         case 0:
6119                 filter_info->src_ip_mask = 1;
6120                 break;
6121         default:
6122                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6123                 return -EINVAL;
6124         }
6125
6126         switch (filter->dst_port_mask) {
6127         case UINT16_MAX:
6128                 filter_info->dst_port_mask = 0;
6129                 filter_info->dst_port = filter->dst_port;
6130                 break;
6131         case 0:
6132                 filter_info->dst_port_mask = 1;
6133                 break;
6134         default:
6135                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6136                 return -EINVAL;
6137         }
6138
6139         switch (filter->src_port_mask) {
6140         case UINT16_MAX:
6141                 filter_info->src_port_mask = 0;
6142                 filter_info->src_port = filter->src_port;
6143                 break;
6144         case 0:
6145                 filter_info->src_port_mask = 1;
6146                 break;
6147         default:
6148                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6149                 return -EINVAL;
6150         }
6151
6152         switch (filter->proto_mask) {
6153         case UINT8_MAX:
6154                 filter_info->proto_mask = 0;
6155                 filter_info->proto =
6156                         convert_protocol_type(filter->proto);
6157                 break;
6158         case 0:
6159                 filter_info->proto_mask = 1;
6160                 break;
6161         default:
6162                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6163                 return -EINVAL;
6164         }
6165
6166         filter_info->priority = (uint8_t)filter->priority;
6167         return 0;
6168 }
6169
6170 /*
6171  * add or delete a ntuple filter
6172  *
6173  * @param
6174  * dev: Pointer to struct rte_eth_dev.
6175  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6176  * add: if true, add filter, if false, remove filter
6177  *
6178  * @return
6179  *    - On success, zero.
6180  *    - On failure, a negative value.
6181  */
6182 static int
6183 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6184                         struct rte_eth_ntuple_filter *ntuple_filter,
6185                         bool add)
6186 {
6187         struct ixgbe_filter_info *filter_info =
6188                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6189         struct ixgbe_5tuple_filter_info filter_5tuple;
6190         struct ixgbe_5tuple_filter *filter;
6191         int ret;
6192
6193         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6194                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6195                 return -EINVAL;
6196         }
6197
6198         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6199         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6200         if (ret < 0)
6201                 return ret;
6202
6203         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6204                                          &filter_5tuple);
6205         if (filter != NULL && add) {
6206                 PMD_DRV_LOG(ERR, "filter exists.");
6207                 return -EEXIST;
6208         }
6209         if (filter == NULL && !add) {
6210                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6211                 return -ENOENT;
6212         }
6213
6214         if (add) {
6215                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6216                                 sizeof(struct ixgbe_5tuple_filter), 0);
6217                 if (filter == NULL)
6218                         return -ENOMEM;
6219                 (void)rte_memcpy(&filter->filter_info,
6220                                  &filter_5tuple,
6221                                  sizeof(struct ixgbe_5tuple_filter_info));
6222                 filter->queue = ntuple_filter->queue;
6223                 ret = ixgbe_add_5tuple_filter(dev, filter);
6224                 if (ret < 0) {
6225                         rte_free(filter);
6226                         return ret;
6227                 }
6228         } else
6229                 ixgbe_remove_5tuple_filter(dev, filter);
6230
6231         return 0;
6232 }
6233
6234 /*
6235  * get a ntuple filter
6236  *
6237  * @param
6238  * dev: Pointer to struct rte_eth_dev.
6239  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6240  *
6241  * @return
6242  *    - On success, zero.
6243  *    - On failure, a negative value.
6244  */
6245 static int
6246 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6247                         struct rte_eth_ntuple_filter *ntuple_filter)
6248 {
6249         struct ixgbe_filter_info *filter_info =
6250                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6251         struct ixgbe_5tuple_filter_info filter_5tuple;
6252         struct ixgbe_5tuple_filter *filter;
6253         int ret;
6254
6255         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6256                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6257                 return -EINVAL;
6258         }
6259
6260         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6261         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6262         if (ret < 0)
6263                 return ret;
6264
6265         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6266                                          &filter_5tuple);
6267         if (filter == NULL) {
6268                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6269                 return -ENOENT;
6270         }
6271         ntuple_filter->queue = filter->queue;
6272         return 0;
6273 }
6274
6275 /*
6276  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6277  * @dev: pointer to rte_eth_dev structure
6278  * @filter_op:operation will be taken.
6279  * @arg: a pointer to specific structure corresponding to the filter_op
6280  *
6281  * @return
6282  *    - On success, zero.
6283  *    - On failure, a negative value.
6284  */
6285 static int
6286 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6287                                 enum rte_filter_op filter_op,
6288                                 void *arg)
6289 {
6290         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6291         int ret;
6292
6293         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6294
6295         if (filter_op == RTE_ETH_FILTER_NOP)
6296                 return 0;
6297
6298         if (arg == NULL) {
6299                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6300                             filter_op);
6301                 return -EINVAL;
6302         }
6303
6304         switch (filter_op) {
6305         case RTE_ETH_FILTER_ADD:
6306                 ret = ixgbe_add_del_ntuple_filter(dev,
6307                         (struct rte_eth_ntuple_filter *)arg,
6308                         TRUE);
6309                 break;
6310         case RTE_ETH_FILTER_DELETE:
6311                 ret = ixgbe_add_del_ntuple_filter(dev,
6312                         (struct rte_eth_ntuple_filter *)arg,
6313                         FALSE);
6314                 break;
6315         case RTE_ETH_FILTER_GET:
6316                 ret = ixgbe_get_ntuple_filter(dev,
6317                         (struct rte_eth_ntuple_filter *)arg);
6318                 break;
6319         default:
6320                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6321                 ret = -EINVAL;
6322                 break;
6323         }
6324         return ret;
6325 }
6326
6327 static inline int
6328 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6329                         uint16_t ethertype)
6330 {
6331         int i;
6332
6333         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6334                 if (filter_info->ethertype_filters[i] == ethertype &&
6335                     (filter_info->ethertype_mask & (1 << i)))
6336                         return i;
6337         }
6338         return -1;
6339 }
6340
6341 static inline int
6342 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6343                         uint16_t ethertype)
6344 {
6345         int i;
6346
6347         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6348                 if (!(filter_info->ethertype_mask & (1 << i))) {
6349                         filter_info->ethertype_mask |= 1 << i;
6350                         filter_info->ethertype_filters[i] = ethertype;
6351                         return i;
6352                 }
6353         }
6354         return -1;
6355 }
6356
6357 static inline int
6358 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6359                         uint8_t idx)
6360 {
6361         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6362                 return -1;
6363         filter_info->ethertype_mask &= ~(1 << idx);
6364         filter_info->ethertype_filters[idx] = 0;
6365         return idx;
6366 }
6367
6368 static int
6369 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6370                         struct rte_eth_ethertype_filter *filter,
6371                         bool add)
6372 {
6373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6374         struct ixgbe_filter_info *filter_info =
6375                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6376         uint32_t etqf = 0;
6377         uint32_t etqs = 0;
6378         int ret;
6379
6380         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6381                 return -EINVAL;
6382
6383         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6384                 filter->ether_type == ETHER_TYPE_IPv6) {
6385                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6386                         " ethertype filter.", filter->ether_type);
6387                 return -EINVAL;
6388         }
6389
6390         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6391                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6392                 return -EINVAL;
6393         }
6394         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6395                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6396                 return -EINVAL;
6397         }
6398
6399         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6400         if (ret >= 0 && add) {
6401                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6402                             filter->ether_type);
6403                 return -EEXIST;
6404         }
6405         if (ret < 0 && !add) {
6406                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6407                             filter->ether_type);
6408                 return -ENOENT;
6409         }
6410
6411         if (add) {
6412                 ret = ixgbe_ethertype_filter_insert(filter_info,
6413                         filter->ether_type);
6414                 if (ret < 0) {
6415                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6416                         return -ENOSYS;
6417                 }
6418                 etqf = IXGBE_ETQF_FILTER_EN;
6419                 etqf |= (uint32_t)filter->ether_type;
6420                 etqs |= (uint32_t)((filter->queue <<
6421                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6422                                     IXGBE_ETQS_RX_QUEUE);
6423                 etqs |= IXGBE_ETQS_QUEUE_EN;
6424         } else {
6425                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6426                 if (ret < 0)
6427                         return -ENOSYS;
6428         }
6429         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6430         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6431         IXGBE_WRITE_FLUSH(hw);
6432
6433         return 0;
6434 }
6435
6436 static int
6437 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6438                         struct rte_eth_ethertype_filter *filter)
6439 {
6440         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6441         struct ixgbe_filter_info *filter_info =
6442                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6443         uint32_t etqf, etqs;
6444         int ret;
6445
6446         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6447         if (ret < 0) {
6448                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6449                             filter->ether_type);
6450                 return -ENOENT;
6451         }
6452
6453         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6454         if (etqf & IXGBE_ETQF_FILTER_EN) {
6455                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6456                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6457                 filter->flags = 0;
6458                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6459                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6460                 return 0;
6461         }
6462         return -ENOENT;
6463 }
6464
6465 /*
6466  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6467  * @dev: pointer to rte_eth_dev structure
6468  * @filter_op:operation will be taken.
6469  * @arg: a pointer to specific structure corresponding to the filter_op
6470  */
6471 static int
6472 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6473                                 enum rte_filter_op filter_op,
6474                                 void *arg)
6475 {
6476         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6477         int ret;
6478
6479         MAC_TYPE_FILTER_SUP(hw->mac.type);
6480
6481         if (filter_op == RTE_ETH_FILTER_NOP)
6482                 return 0;
6483
6484         if (arg == NULL) {
6485                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6486                             filter_op);
6487                 return -EINVAL;
6488         }
6489
6490         switch (filter_op) {
6491         case RTE_ETH_FILTER_ADD:
6492                 ret = ixgbe_add_del_ethertype_filter(dev,
6493                         (struct rte_eth_ethertype_filter *)arg,
6494                         TRUE);
6495                 break;
6496         case RTE_ETH_FILTER_DELETE:
6497                 ret = ixgbe_add_del_ethertype_filter(dev,
6498                         (struct rte_eth_ethertype_filter *)arg,
6499                         FALSE);
6500                 break;
6501         case RTE_ETH_FILTER_GET:
6502                 ret = ixgbe_get_ethertype_filter(dev,
6503                         (struct rte_eth_ethertype_filter *)arg);
6504                 break;
6505         default:
6506                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6507                 ret = -EINVAL;
6508                 break;
6509         }
6510         return ret;
6511 }
6512
6513 static int
6514 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6515                      enum rte_filter_type filter_type,
6516                      enum rte_filter_op filter_op,
6517                      void *arg)
6518 {
6519         int ret = -EINVAL;
6520
6521         switch (filter_type) {
6522         case RTE_ETH_FILTER_NTUPLE:
6523                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6524                 break;
6525         case RTE_ETH_FILTER_ETHERTYPE:
6526                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6527                 break;
6528         case RTE_ETH_FILTER_SYN:
6529                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6530                 break;
6531         case RTE_ETH_FILTER_FDIR:
6532                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6533                 break;
6534         case RTE_ETH_FILTER_L2_TUNNEL:
6535                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6536                 break;
6537         default:
6538                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6539                                                         filter_type);
6540                 break;
6541         }
6542
6543         return ret;
6544 }
6545
6546 static u8 *
6547 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6548                         u8 **mc_addr_ptr, u32 *vmdq)
6549 {
6550         u8 *mc_addr;
6551
6552         *vmdq = 0;
6553         mc_addr = *mc_addr_ptr;
6554         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6555         return mc_addr;
6556 }
6557
6558 static int
6559 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6560                           struct ether_addr *mc_addr_set,
6561                           uint32_t nb_mc_addr)
6562 {
6563         struct ixgbe_hw *hw;
6564         u8 *mc_addr_list;
6565
6566         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6567         mc_addr_list = (u8 *)mc_addr_set;
6568         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6569                                          ixgbe_dev_addr_list_itr, TRUE);
6570 }
6571
6572 static uint64_t
6573 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6574 {
6575         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6576         uint64_t systime_cycles;
6577
6578         switch (hw->mac.type) {
6579         case ixgbe_mac_X550:
6580         case ixgbe_mac_X550EM_x:
6581         case ixgbe_mac_X550EM_a:
6582                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6583                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6584                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6585                                 * NSEC_PER_SEC;
6586                 break;
6587         default:
6588                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6589                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6590                                 << 32;
6591         }
6592
6593         return systime_cycles;
6594 }
6595
6596 static uint64_t
6597 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6598 {
6599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6600         uint64_t rx_tstamp_cycles;
6601
6602         switch (hw->mac.type) {
6603         case ixgbe_mac_X550:
6604         case ixgbe_mac_X550EM_x:
6605         case ixgbe_mac_X550EM_a:
6606                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6607                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6608                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6609                                 * NSEC_PER_SEC;
6610                 break;
6611         default:
6612                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6613                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6614                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6615                                 << 32;
6616         }
6617
6618         return rx_tstamp_cycles;
6619 }
6620
6621 static uint64_t
6622 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6623 {
6624         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6625         uint64_t tx_tstamp_cycles;
6626
6627         switch (hw->mac.type) {
6628         case ixgbe_mac_X550:
6629         case ixgbe_mac_X550EM_x:
6630         case ixgbe_mac_X550EM_a:
6631                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6632                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6633                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6634                                 * NSEC_PER_SEC;
6635                 break;
6636         default:
6637                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6638                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6639                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6640                                 << 32;
6641         }
6642
6643         return tx_tstamp_cycles;
6644 }
6645
6646 static void
6647 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6648 {
6649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6650         struct ixgbe_adapter *adapter =
6651                 (struct ixgbe_adapter *)dev->data->dev_private;
6652         struct rte_eth_link link;
6653         uint32_t incval = 0;
6654         uint32_t shift = 0;
6655
6656         /* Get current link speed. */
6657         memset(&link, 0, sizeof(link));
6658         ixgbe_dev_link_update(dev, 1);
6659         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6660
6661         switch (link.link_speed) {
6662         case ETH_SPEED_NUM_100M:
6663                 incval = IXGBE_INCVAL_100;
6664                 shift = IXGBE_INCVAL_SHIFT_100;
6665                 break;
6666         case ETH_SPEED_NUM_1G:
6667                 incval = IXGBE_INCVAL_1GB;
6668                 shift = IXGBE_INCVAL_SHIFT_1GB;
6669                 break;
6670         case ETH_SPEED_NUM_10G:
6671         default:
6672                 incval = IXGBE_INCVAL_10GB;
6673                 shift = IXGBE_INCVAL_SHIFT_10GB;
6674                 break;
6675         }
6676
6677         switch (hw->mac.type) {
6678         case ixgbe_mac_X550:
6679         case ixgbe_mac_X550EM_x:
6680         case ixgbe_mac_X550EM_a:
6681                 /* Independent of link speed. */
6682                 incval = 1;
6683                 /* Cycles read will be interpreted as ns. */
6684                 shift = 0;
6685                 /* Fall-through */
6686         case ixgbe_mac_X540:
6687                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6688                 break;
6689         case ixgbe_mac_82599EB:
6690                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6691                 shift -= IXGBE_INCVAL_SHIFT_82599;
6692                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6693                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6694                 break;
6695         default:
6696                 /* Not supported. */
6697                 return;
6698         }
6699
6700         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6701         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6702         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6703
6704         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6705         adapter->systime_tc.cc_shift = shift;
6706         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6707
6708         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6709         adapter->rx_tstamp_tc.cc_shift = shift;
6710         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6711
6712         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6713         adapter->tx_tstamp_tc.cc_shift = shift;
6714         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6715 }
6716
6717 static int
6718 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6719 {
6720         struct ixgbe_adapter *adapter =
6721                         (struct ixgbe_adapter *)dev->data->dev_private;
6722
6723         adapter->systime_tc.nsec += delta;
6724         adapter->rx_tstamp_tc.nsec += delta;
6725         adapter->tx_tstamp_tc.nsec += delta;
6726
6727         return 0;
6728 }
6729
6730 static int
6731 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6732 {
6733         uint64_t ns;
6734         struct ixgbe_adapter *adapter =
6735                         (struct ixgbe_adapter *)dev->data->dev_private;
6736
6737         ns = rte_timespec_to_ns(ts);
6738         /* Set the timecounters to a new value. */
6739         adapter->systime_tc.nsec = ns;
6740         adapter->rx_tstamp_tc.nsec = ns;
6741         adapter->tx_tstamp_tc.nsec = ns;
6742
6743         return 0;
6744 }
6745
6746 static int
6747 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6748 {
6749         uint64_t ns, systime_cycles;
6750         struct ixgbe_adapter *adapter =
6751                         (struct ixgbe_adapter *)dev->data->dev_private;
6752
6753         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6754         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6755         *ts = rte_ns_to_timespec(ns);
6756
6757         return 0;
6758 }
6759
6760 static int
6761 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6762 {
6763         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6764         uint32_t tsync_ctl;
6765         uint32_t tsauxc;
6766
6767         /* Stop the timesync system time. */
6768         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6769         /* Reset the timesync system time value. */
6770         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6771         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6772
6773         /* Enable system time for platforms where it isn't on by default. */
6774         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6775         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6776         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6777
6778         ixgbe_start_timecounters(dev);
6779
6780         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6781         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6782                         (ETHER_TYPE_1588 |
6783                          IXGBE_ETQF_FILTER_EN |
6784                          IXGBE_ETQF_1588));
6785
6786         /* Enable timestamping of received PTP packets. */
6787         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6788         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6789         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6790
6791         /* Enable timestamping of transmitted PTP packets. */
6792         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6793         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6794         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6795
6796         IXGBE_WRITE_FLUSH(hw);
6797
6798         return 0;
6799 }
6800
6801 static int
6802 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6803 {
6804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6805         uint32_t tsync_ctl;
6806
6807         /* Disable timestamping of transmitted PTP packets. */
6808         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6809         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6810         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6811
6812         /* Disable timestamping of received PTP packets. */
6813         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6814         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6815         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6816
6817         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6818         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6819
6820         /* Stop incrementating the System Time registers. */
6821         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6822
6823         return 0;
6824 }
6825
6826 static int
6827 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6828                                  struct timespec *timestamp,
6829                                  uint32_t flags __rte_unused)
6830 {
6831         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6832         struct ixgbe_adapter *adapter =
6833                 (struct ixgbe_adapter *)dev->data->dev_private;
6834         uint32_t tsync_rxctl;
6835         uint64_t rx_tstamp_cycles;
6836         uint64_t ns;
6837
6838         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6839         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6840                 return -EINVAL;
6841
6842         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6843         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6844         *timestamp = rte_ns_to_timespec(ns);
6845
6846         return  0;
6847 }
6848
6849 static int
6850 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6851                                  struct timespec *timestamp)
6852 {
6853         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6854         struct ixgbe_adapter *adapter =
6855                 (struct ixgbe_adapter *)dev->data->dev_private;
6856         uint32_t tsync_txctl;
6857         uint64_t tx_tstamp_cycles;
6858         uint64_t ns;
6859
6860         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6861         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6862                 return -EINVAL;
6863
6864         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6865         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6866         *timestamp = rte_ns_to_timespec(ns);
6867
6868         return 0;
6869 }
6870
6871 static int
6872 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6873 {
6874         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6875         int count = 0;
6876         int g_ind = 0;
6877         const struct reg_info *reg_group;
6878         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6879                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6880
6881         while ((reg_group = reg_set[g_ind++]))
6882                 count += ixgbe_regs_group_count(reg_group);
6883
6884         return count;
6885 }
6886
6887 static int
6888 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6889 {
6890         int count = 0;
6891         int g_ind = 0;
6892         const struct reg_info *reg_group;
6893
6894         while ((reg_group = ixgbevf_regs[g_ind++]))
6895                 count += ixgbe_regs_group_count(reg_group);
6896
6897         return count;
6898 }
6899
6900 static int
6901 ixgbe_get_regs(struct rte_eth_dev *dev,
6902               struct rte_dev_reg_info *regs)
6903 {
6904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6905         uint32_t *data = regs->data;
6906         int g_ind = 0;
6907         int count = 0;
6908         const struct reg_info *reg_group;
6909         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6910                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6911
6912         if (data == NULL) {
6913                 regs->length = ixgbe_get_reg_length(dev);
6914                 regs->width = sizeof(uint32_t);
6915                 return 0;
6916         }
6917
6918         /* Support only full register dump */
6919         if ((regs->length == 0) ||
6920             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6921                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6922                         hw->device_id;
6923                 while ((reg_group = reg_set[g_ind++]))
6924                         count += ixgbe_read_regs_group(dev, &data[count],
6925                                 reg_group);
6926                 return 0;
6927         }
6928
6929         return -ENOTSUP;
6930 }
6931
6932 static int
6933 ixgbevf_get_regs(struct rte_eth_dev *dev,
6934                 struct rte_dev_reg_info *regs)
6935 {
6936         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6937         uint32_t *data = regs->data;
6938         int g_ind = 0;
6939         int count = 0;
6940         const struct reg_info *reg_group;
6941
6942         if (data == NULL) {
6943                 regs->length = ixgbevf_get_reg_length(dev);
6944                 regs->width = sizeof(uint32_t);
6945                 return 0;
6946         }
6947
6948         /* Support only full register dump */
6949         if ((regs->length == 0) ||
6950             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6951                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6952                         hw->device_id;
6953                 while ((reg_group = ixgbevf_regs[g_ind++]))
6954                         count += ixgbe_read_regs_group(dev, &data[count],
6955                                                       reg_group);
6956                 return 0;
6957         }
6958
6959         return -ENOTSUP;
6960 }
6961
6962 static int
6963 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6964 {
6965         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6966
6967         /* Return unit is byte count */
6968         return hw->eeprom.word_size * 2;
6969 }
6970
6971 static int
6972 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6973                 struct rte_dev_eeprom_info *in_eeprom)
6974 {
6975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6976         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6977         uint16_t *data = in_eeprom->data;
6978         int first, length;
6979
6980         first = in_eeprom->offset >> 1;
6981         length = in_eeprom->length >> 1;
6982         if ((first > hw->eeprom.word_size) ||
6983             ((first + length) > hw->eeprom.word_size))
6984                 return -EINVAL;
6985
6986         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6987
6988         return eeprom->ops.read_buffer(hw, first, length, data);
6989 }
6990
6991 static int
6992 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6993                 struct rte_dev_eeprom_info *in_eeprom)
6994 {
6995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6996         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6997         uint16_t *data = in_eeprom->data;
6998         int first, length;
6999
7000         first = in_eeprom->offset >> 1;
7001         length = in_eeprom->length >> 1;
7002         if ((first > hw->eeprom.word_size) ||
7003             ((first + length) > hw->eeprom.word_size))
7004                 return -EINVAL;
7005
7006         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7007
7008         return eeprom->ops.write_buffer(hw,  first, length, data);
7009 }
7010
7011 uint16_t
7012 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7013         switch (mac_type) {
7014         case ixgbe_mac_X550:
7015         case ixgbe_mac_X550EM_x:
7016         case ixgbe_mac_X550EM_a:
7017                 return ETH_RSS_RETA_SIZE_512;
7018         case ixgbe_mac_X550_vf:
7019         case ixgbe_mac_X550EM_x_vf:
7020         case ixgbe_mac_X550EM_a_vf:
7021                 return ETH_RSS_RETA_SIZE_64;
7022         default:
7023                 return ETH_RSS_RETA_SIZE_128;
7024         }
7025 }
7026
7027 uint32_t
7028 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7029         switch (mac_type) {
7030         case ixgbe_mac_X550:
7031         case ixgbe_mac_X550EM_x:
7032         case ixgbe_mac_X550EM_a:
7033                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7034                         return IXGBE_RETA(reta_idx >> 2);
7035                 else
7036                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7037         case ixgbe_mac_X550_vf:
7038         case ixgbe_mac_X550EM_x_vf:
7039         case ixgbe_mac_X550EM_a_vf:
7040                 return IXGBE_VFRETA(reta_idx >> 2);
7041         default:
7042                 return IXGBE_RETA(reta_idx >> 2);
7043         }
7044 }
7045
7046 uint32_t
7047 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7048         switch (mac_type) {
7049         case ixgbe_mac_X550_vf:
7050         case ixgbe_mac_X550EM_x_vf:
7051         case ixgbe_mac_X550EM_a_vf:
7052                 return IXGBE_VFMRQC;
7053         default:
7054                 return IXGBE_MRQC;
7055         }
7056 }
7057
7058 uint32_t
7059 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7060         switch (mac_type) {
7061         case ixgbe_mac_X550_vf:
7062         case ixgbe_mac_X550EM_x_vf:
7063         case ixgbe_mac_X550EM_a_vf:
7064                 return IXGBE_VFRSSRK(i);
7065         default:
7066                 return IXGBE_RSSRK(i);
7067         }
7068 }
7069
7070 bool
7071 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7072         switch (mac_type) {
7073         case ixgbe_mac_82599_vf:
7074         case ixgbe_mac_X540_vf:
7075                 return 0;
7076         default:
7077                 return 1;
7078         }
7079 }
7080
7081 static int
7082 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7083                         struct rte_eth_dcb_info *dcb_info)
7084 {
7085         struct ixgbe_dcb_config *dcb_config =
7086                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7087         struct ixgbe_dcb_tc_config *tc;
7088         uint8_t i, j;
7089
7090         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7091                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7092         else
7093                 dcb_info->nb_tcs = 1;
7094
7095         if (dcb_config->vt_mode) { /* vt is enabled*/
7096                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7097                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7098                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7099                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7100                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7101                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7102                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7103                                                 i * dcb_info->nb_tcs + j;
7104                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7105                                 dcb_info->tc_queue.tc_txq[i][j].base =
7106                                                 i * dcb_info->nb_tcs + j;
7107                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7108                         }
7109                 }
7110         } else { /* vt is disabled*/
7111                 struct rte_eth_dcb_rx_conf *rx_conf =
7112                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7113                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7114                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7115                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7116                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7117                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7118                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7119                         }
7120                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7121                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7122                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7123                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7124                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7125                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7126                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7127                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7128                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7129                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7130                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7131                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7132                         }
7133                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7134                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7135                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7136                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7137                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7138                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7139                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7140                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7141                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7142                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7143                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7144                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7145                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7146                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7147                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7148                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7149                 }
7150         }
7151         for (i = 0; i < dcb_info->nb_tcs; i++) {
7152                 tc = &dcb_config->tc_config[i];
7153                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7154         }
7155         return 0;
7156 }
7157
7158 /* Update e-tag ether type */
7159 static int
7160 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7161                             uint16_t ether_type)
7162 {
7163         uint32_t etag_etype;
7164
7165         if (hw->mac.type != ixgbe_mac_X550 &&
7166             hw->mac.type != ixgbe_mac_X550EM_x &&
7167             hw->mac.type != ixgbe_mac_X550EM_a) {
7168                 return -ENOTSUP;
7169         }
7170
7171         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7172         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7173         etag_etype |= ether_type;
7174         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7175         IXGBE_WRITE_FLUSH(hw);
7176
7177         return 0;
7178 }
7179
7180 /* Config l2 tunnel ether type */
7181 static int
7182 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7183                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7184 {
7185         int ret = 0;
7186         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7187
7188         if (l2_tunnel == NULL)
7189                 return -EINVAL;
7190
7191         switch (l2_tunnel->l2_tunnel_type) {
7192         case RTE_L2_TUNNEL_TYPE_E_TAG:
7193                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7194                 break;
7195         default:
7196                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7197                 ret = -EINVAL;
7198                 break;
7199         }
7200
7201         return ret;
7202 }
7203
7204 /* Enable e-tag tunnel */
7205 static int
7206 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7207 {
7208         uint32_t etag_etype;
7209
7210         if (hw->mac.type != ixgbe_mac_X550 &&
7211             hw->mac.type != ixgbe_mac_X550EM_x &&
7212             hw->mac.type != ixgbe_mac_X550EM_a) {
7213                 return -ENOTSUP;
7214         }
7215
7216         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7217         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7218         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7219         IXGBE_WRITE_FLUSH(hw);
7220
7221         return 0;
7222 }
7223
7224 /* Enable l2 tunnel */
7225 static int
7226 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7227                            enum rte_eth_tunnel_type l2_tunnel_type)
7228 {
7229         int ret = 0;
7230         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7231
7232         switch (l2_tunnel_type) {
7233         case RTE_L2_TUNNEL_TYPE_E_TAG:
7234                 ret = ixgbe_e_tag_enable(hw);
7235                 break;
7236         default:
7237                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7238                 ret = -EINVAL;
7239                 break;
7240         }
7241
7242         return ret;
7243 }
7244
7245 /* Disable e-tag tunnel */
7246 static int
7247 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7248 {
7249         uint32_t etag_etype;
7250
7251         if (hw->mac.type != ixgbe_mac_X550 &&
7252             hw->mac.type != ixgbe_mac_X550EM_x &&
7253             hw->mac.type != ixgbe_mac_X550EM_a) {
7254                 return -ENOTSUP;
7255         }
7256
7257         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7258         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7259         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7260         IXGBE_WRITE_FLUSH(hw);
7261
7262         return 0;
7263 }
7264
7265 /* Disable l2 tunnel */
7266 static int
7267 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7268                             enum rte_eth_tunnel_type l2_tunnel_type)
7269 {
7270         int ret = 0;
7271         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7272
7273         switch (l2_tunnel_type) {
7274         case RTE_L2_TUNNEL_TYPE_E_TAG:
7275                 ret = ixgbe_e_tag_disable(hw);
7276                 break;
7277         default:
7278                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7279                 ret = -EINVAL;
7280                 break;
7281         }
7282
7283         return ret;
7284 }
7285
7286 static int
7287 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7288                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7289 {
7290         int ret = 0;
7291         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7292         uint32_t i, rar_entries;
7293         uint32_t rar_low, rar_high;
7294
7295         if (hw->mac.type != ixgbe_mac_X550 &&
7296             hw->mac.type != ixgbe_mac_X550EM_x &&
7297             hw->mac.type != ixgbe_mac_X550EM_a) {
7298                 return -ENOTSUP;
7299         }
7300
7301         rar_entries = ixgbe_get_num_rx_addrs(hw);
7302
7303         for (i = 1; i < rar_entries; i++) {
7304                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7305                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7306                 if ((rar_high & IXGBE_RAH_AV) &&
7307                     (rar_high & IXGBE_RAH_ADTYPE) &&
7308                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7309                      l2_tunnel->tunnel_id)) {
7310                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7311                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7312
7313                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7314
7315                         return ret;
7316                 }
7317         }
7318
7319         return ret;
7320 }
7321
7322 static int
7323 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7324                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7325 {
7326         int ret = 0;
7327         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7328         uint32_t i, rar_entries;
7329         uint32_t rar_low, rar_high;
7330
7331         if (hw->mac.type != ixgbe_mac_X550 &&
7332             hw->mac.type != ixgbe_mac_X550EM_x &&
7333             hw->mac.type != ixgbe_mac_X550EM_a) {
7334                 return -ENOTSUP;
7335         }
7336
7337         /* One entry for one tunnel. Try to remove potential existing entry. */
7338         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7339
7340         rar_entries = ixgbe_get_num_rx_addrs(hw);
7341
7342         for (i = 1; i < rar_entries; i++) {
7343                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7344                 if (rar_high & IXGBE_RAH_AV) {
7345                         continue;
7346                 } else {
7347                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7348                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7349                         rar_low = l2_tunnel->tunnel_id;
7350
7351                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7352                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7353
7354                         return ret;
7355                 }
7356         }
7357
7358         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7359                      " Please remove a rule before adding a new one.");
7360         return -EINVAL;
7361 }
7362
7363 /* Add l2 tunnel filter */
7364 static int
7365 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7366                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7367 {
7368         int ret = 0;
7369
7370         switch (l2_tunnel->l2_tunnel_type) {
7371         case RTE_L2_TUNNEL_TYPE_E_TAG:
7372                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7373                 break;
7374         default:
7375                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7376                 ret = -EINVAL;
7377                 break;
7378         }
7379
7380         return ret;
7381 }
7382
7383 /* Delete l2 tunnel filter */
7384 static int
7385 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7386                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7387 {
7388         int ret = 0;
7389
7390         switch (l2_tunnel->l2_tunnel_type) {
7391         case RTE_L2_TUNNEL_TYPE_E_TAG:
7392                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7393                 break;
7394         default:
7395                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7396                 ret = -EINVAL;
7397                 break;
7398         }
7399
7400         return ret;
7401 }
7402
7403 /**
7404  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7405  * @dev: pointer to rte_eth_dev structure
7406  * @filter_op:operation will be taken.
7407  * @arg: a pointer to specific structure corresponding to the filter_op
7408  */
7409 static int
7410 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7411                                   enum rte_filter_op filter_op,
7412                                   void *arg)
7413 {
7414         int ret = 0;
7415
7416         if (filter_op == RTE_ETH_FILTER_NOP)
7417                 return 0;
7418
7419         if (arg == NULL) {
7420                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7421                             filter_op);
7422                 return -EINVAL;
7423         }
7424
7425         switch (filter_op) {
7426         case RTE_ETH_FILTER_ADD:
7427                 ret = ixgbe_dev_l2_tunnel_filter_add
7428                         (dev,
7429                          (struct rte_eth_l2_tunnel_conf *)arg);
7430                 break;
7431         case RTE_ETH_FILTER_DELETE:
7432                 ret = ixgbe_dev_l2_tunnel_filter_del
7433                         (dev,
7434                          (struct rte_eth_l2_tunnel_conf *)arg);
7435                 break;
7436         default:
7437                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7438                 ret = -EINVAL;
7439                 break;
7440         }
7441         return ret;
7442 }
7443
7444 static int
7445 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7446 {
7447         int ret = 0;
7448         uint32_t ctrl;
7449         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7450
7451         if (hw->mac.type != ixgbe_mac_X550 &&
7452             hw->mac.type != ixgbe_mac_X550EM_x &&
7453             hw->mac.type != ixgbe_mac_X550EM_a) {
7454                 return -ENOTSUP;
7455         }
7456
7457         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7458         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7459         if (en)
7460                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7461         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7462
7463         return ret;
7464 }
7465
7466 /* Enable l2 tunnel forwarding */
7467 static int
7468 ixgbe_dev_l2_tunnel_forwarding_enable
7469         (struct rte_eth_dev *dev,
7470          enum rte_eth_tunnel_type l2_tunnel_type)
7471 {
7472         int ret = 0;
7473
7474         switch (l2_tunnel_type) {
7475         case RTE_L2_TUNNEL_TYPE_E_TAG:
7476                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7477                 break;
7478         default:
7479                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7480                 ret = -EINVAL;
7481                 break;
7482         }
7483
7484         return ret;
7485 }
7486
7487 /* Disable l2 tunnel forwarding */
7488 static int
7489 ixgbe_dev_l2_tunnel_forwarding_disable
7490         (struct rte_eth_dev *dev,
7491          enum rte_eth_tunnel_type l2_tunnel_type)
7492 {
7493         int ret = 0;
7494
7495         switch (l2_tunnel_type) {
7496         case RTE_L2_TUNNEL_TYPE_E_TAG:
7497                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7498                 break;
7499         default:
7500                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7501                 ret = -EINVAL;
7502                 break;
7503         }
7504
7505         return ret;
7506 }
7507
7508 static int
7509 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7510                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7511                              bool en)
7512 {
7513         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7514         int ret = 0;
7515         uint32_t vmtir, vmvir;
7516         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7517
7518         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7519                 PMD_DRV_LOG(ERR,
7520                             "VF id %u should be less than %u",
7521                             l2_tunnel->vf_id,
7522                             pci_dev->max_vfs);
7523                 return -EINVAL;
7524         }
7525
7526         if (hw->mac.type != ixgbe_mac_X550 &&
7527             hw->mac.type != ixgbe_mac_X550EM_x &&
7528             hw->mac.type != ixgbe_mac_X550EM_a) {
7529                 return -ENOTSUP;
7530         }
7531
7532         if (en)
7533                 vmtir = l2_tunnel->tunnel_id;
7534         else
7535                 vmtir = 0;
7536
7537         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7538
7539         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7540         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7541         if (en)
7542                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7543         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7544
7545         return ret;
7546 }
7547
7548 /* Enable l2 tunnel tag insertion */
7549 static int
7550 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7551                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7552 {
7553         int ret = 0;
7554
7555         switch (l2_tunnel->l2_tunnel_type) {
7556         case RTE_L2_TUNNEL_TYPE_E_TAG:
7557                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7558                 break;
7559         default:
7560                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7561                 ret = -EINVAL;
7562                 break;
7563         }
7564
7565         return ret;
7566 }
7567
7568 /* Disable l2 tunnel tag insertion */
7569 static int
7570 ixgbe_dev_l2_tunnel_insertion_disable
7571         (struct rte_eth_dev *dev,
7572          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7573 {
7574         int ret = 0;
7575
7576         switch (l2_tunnel->l2_tunnel_type) {
7577         case RTE_L2_TUNNEL_TYPE_E_TAG:
7578                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7579                 break;
7580         default:
7581                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7582                 ret = -EINVAL;
7583                 break;
7584         }
7585
7586         return ret;
7587 }
7588
7589 static int
7590 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7591                              bool en)
7592 {
7593         int ret = 0;
7594         uint32_t qde;
7595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7596
7597         if (hw->mac.type != ixgbe_mac_X550 &&
7598             hw->mac.type != ixgbe_mac_X550EM_x &&
7599             hw->mac.type != ixgbe_mac_X550EM_a) {
7600                 return -ENOTSUP;
7601         }
7602
7603         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7604         if (en)
7605                 qde |= IXGBE_QDE_STRIP_TAG;
7606         else
7607                 qde &= ~IXGBE_QDE_STRIP_TAG;
7608         qde &= ~IXGBE_QDE_READ;
7609         qde |= IXGBE_QDE_WRITE;
7610         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7611
7612         return ret;
7613 }
7614
7615 /* Enable l2 tunnel tag stripping */
7616 static int
7617 ixgbe_dev_l2_tunnel_stripping_enable
7618         (struct rte_eth_dev *dev,
7619          enum rte_eth_tunnel_type l2_tunnel_type)
7620 {
7621         int ret = 0;
7622
7623         switch (l2_tunnel_type) {
7624         case RTE_L2_TUNNEL_TYPE_E_TAG:
7625                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7626                 break;
7627         default:
7628                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7629                 ret = -EINVAL;
7630                 break;
7631         }
7632
7633         return ret;
7634 }
7635
7636 /* Disable l2 tunnel tag stripping */
7637 static int
7638 ixgbe_dev_l2_tunnel_stripping_disable
7639         (struct rte_eth_dev *dev,
7640          enum rte_eth_tunnel_type l2_tunnel_type)
7641 {
7642         int ret = 0;
7643
7644         switch (l2_tunnel_type) {
7645         case RTE_L2_TUNNEL_TYPE_E_TAG:
7646                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7647                 break;
7648         default:
7649                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7650                 ret = -EINVAL;
7651                 break;
7652         }
7653
7654         return ret;
7655 }
7656
7657 /* Enable/disable l2 tunnel offload functions */
7658 static int
7659 ixgbe_dev_l2_tunnel_offload_set
7660         (struct rte_eth_dev *dev,
7661          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7662          uint32_t mask,
7663          uint8_t en)
7664 {
7665         int ret = 0;
7666
7667         if (l2_tunnel == NULL)
7668                 return -EINVAL;
7669
7670         ret = -EINVAL;
7671         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7672                 if (en)
7673                         ret = ixgbe_dev_l2_tunnel_enable(
7674                                 dev,
7675                                 l2_tunnel->l2_tunnel_type);
7676                 else
7677                         ret = ixgbe_dev_l2_tunnel_disable(
7678                                 dev,
7679                                 l2_tunnel->l2_tunnel_type);
7680         }
7681
7682         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7683                 if (en)
7684                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7685                                 dev,
7686                                 l2_tunnel);
7687                 else
7688                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7689                                 dev,
7690                                 l2_tunnel);
7691         }
7692
7693         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7694                 if (en)
7695                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7696                                 dev,
7697                                 l2_tunnel->l2_tunnel_type);
7698                 else
7699                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7700                                 dev,
7701                                 l2_tunnel->l2_tunnel_type);
7702         }
7703
7704         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7705                 if (en)
7706                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7707                                 dev,
7708                                 l2_tunnel->l2_tunnel_type);
7709                 else
7710                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7711                                 dev,
7712                                 l2_tunnel->l2_tunnel_type);
7713         }
7714
7715         return ret;
7716 }
7717
7718 static int
7719 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7720                         uint16_t port)
7721 {
7722         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7723         IXGBE_WRITE_FLUSH(hw);
7724
7725         return 0;
7726 }
7727
7728 /* There's only one register for VxLAN UDP port.
7729  * So, we cannot add several ports. Will update it.
7730  */
7731 static int
7732 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7733                      uint16_t port)
7734 {
7735         if (port == 0) {
7736                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7737                 return -EINVAL;
7738         }
7739
7740         return ixgbe_update_vxlan_port(hw, port);
7741 }
7742
7743 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7744  * UDP port, it must have a value.
7745  * So, will reset it to the original value 0.
7746  */
7747 static int
7748 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7749                      uint16_t port)
7750 {
7751         uint16_t cur_port;
7752
7753         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7754
7755         if (cur_port != port) {
7756                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7757                 return -EINVAL;
7758         }
7759
7760         return ixgbe_update_vxlan_port(hw, 0);
7761 }
7762
7763 /* Add UDP tunneling port */
7764 static int
7765 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7766                               struct rte_eth_udp_tunnel *udp_tunnel)
7767 {
7768         int ret = 0;
7769         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7770
7771         if (hw->mac.type != ixgbe_mac_X550 &&
7772             hw->mac.type != ixgbe_mac_X550EM_x &&
7773             hw->mac.type != ixgbe_mac_X550EM_a) {
7774                 return -ENOTSUP;
7775         }
7776
7777         if (udp_tunnel == NULL)
7778                 return -EINVAL;
7779
7780         switch (udp_tunnel->prot_type) {
7781         case RTE_TUNNEL_TYPE_VXLAN:
7782                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7783                 break;
7784
7785         case RTE_TUNNEL_TYPE_GENEVE:
7786         case RTE_TUNNEL_TYPE_TEREDO:
7787                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7788                 ret = -EINVAL;
7789                 break;
7790
7791         default:
7792                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7793                 ret = -EINVAL;
7794                 break;
7795         }
7796
7797         return ret;
7798 }
7799
7800 /* Remove UDP tunneling port */
7801 static int
7802 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7803                               struct rte_eth_udp_tunnel *udp_tunnel)
7804 {
7805         int ret = 0;
7806         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7807
7808         if (hw->mac.type != ixgbe_mac_X550 &&
7809             hw->mac.type != ixgbe_mac_X550EM_x &&
7810             hw->mac.type != ixgbe_mac_X550EM_a) {
7811                 return -ENOTSUP;
7812         }
7813
7814         if (udp_tunnel == NULL)
7815                 return -EINVAL;
7816
7817         switch (udp_tunnel->prot_type) {
7818         case RTE_TUNNEL_TYPE_VXLAN:
7819                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7820                 break;
7821         case RTE_TUNNEL_TYPE_GENEVE:
7822         case RTE_TUNNEL_TYPE_TEREDO:
7823                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7824                 ret = -EINVAL;
7825                 break;
7826         default:
7827                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7828                 ret = -EINVAL;
7829                 break;
7830         }
7831
7832         return ret;
7833 }
7834
7835 static void
7836 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7837 {
7838         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7839
7840         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7841 }
7842
7843 static void
7844 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7845 {
7846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7847
7848         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7849 }
7850
7851 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7852 {
7853         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7854         u32 in_msg = 0;
7855
7856         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7857                 return;
7858
7859         /* PF reset VF event */
7860         if (in_msg == IXGBE_PF_CONTROL_MSG)
7861                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7862 }
7863
7864 static int
7865 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7866 {
7867         uint32_t eicr;
7868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7869         struct ixgbe_interrupt *intr =
7870                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7871         ixgbevf_intr_disable(hw);
7872
7873         /* read-on-clear nic registers here */
7874         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7875         intr->flags = 0;
7876
7877         /* only one misc vector supported - mailbox */
7878         eicr &= IXGBE_VTEICR_MASK;
7879         if (eicr == IXGBE_MISC_VEC_ID)
7880                 intr->flags |= IXGBE_FLAG_MAILBOX;
7881
7882         return 0;
7883 }
7884
7885 static int
7886 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7887 {
7888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7889         struct ixgbe_interrupt *intr =
7890                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7891
7892         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7893                 ixgbevf_mbx_process(dev);
7894                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7895         }
7896
7897         ixgbevf_intr_enable(hw);
7898
7899         return 0;
7900 }
7901
7902 static void
7903 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7904                               void *param)
7905 {
7906         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7907
7908         ixgbevf_dev_interrupt_get_status(dev);
7909         ixgbevf_dev_interrupt_action(dev);
7910 }
7911
7912 /**
7913  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7914  *  @hw: pointer to hardware structure
7915  *
7916  *  Stops the transmit data path and waits for the HW to internally empty
7917  *  the Tx security block
7918  **/
7919 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7920 {
7921 #define IXGBE_MAX_SECTX_POLL 40
7922
7923         int i;
7924         int sectxreg;
7925
7926         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7927         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7928         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7929         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7930                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7931                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7932                         break;
7933                 /* Use interrupt-safe sleep just in case */
7934                 usec_delay(1000);
7935         }
7936
7937         /* For informational purposes only */
7938         if (i >= IXGBE_MAX_SECTX_POLL)
7939                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7940                          "path fully disabled.  Continuing with init.\n");
7941
7942         return IXGBE_SUCCESS;
7943 }
7944
7945 /**
7946  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7947  *  @hw: pointer to hardware structure
7948  *
7949  *  Enables the transmit data path.
7950  **/
7951 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7952 {
7953         uint32_t sectxreg;
7954
7955         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7956         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7957         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7958         IXGBE_WRITE_FLUSH(hw);
7959
7960         return IXGBE_SUCCESS;
7961 }
7962
7963 int
7964 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
7965 {
7966         struct ixgbe_hw *hw;
7967         struct rte_eth_dev *dev;
7968         uint32_t ctrl;
7969
7970         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
7971
7972         dev = &rte_eth_devices[port];
7973         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7974
7975         /* Stop the data paths */
7976         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
7977                 return -ENOTSUP;
7978         /*
7979          * Workaround:
7980          * As no ixgbe_disable_sec_rx_path equivalent is
7981          * implemented for tx in the base code, and we are
7982          * not allowed to modify the base code in DPDK, so
7983          * just call the hand-written one directly for now.
7984          * The hardware support has been checked by
7985          * ixgbe_disable_sec_rx_path().
7986          */
7987         ixgbe_disable_sec_tx_path_generic(hw);
7988
7989         /* Enable Ethernet CRC (required by MACsec offload) */
7990         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
7991         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
7992         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
7993
7994         /* Enable the TX and RX crypto engines */
7995         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7996         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
7997         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
7998
7999         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8000         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8001         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8002
8003         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8004         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8005         ctrl |= 0x3;
8006         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8007
8008         /* Enable SA lookup */
8009         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8010         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8011         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8012                      IXGBE_LSECTXCTRL_AUTH;
8013         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8014         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8015         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8016         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8017
8018         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8019         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8020         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8021         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8022         if (rp)
8023                 ctrl |= IXGBE_LSECRXCTRL_RP;
8024         else
8025                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8026         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8027
8028         /* Start the data paths */
8029         ixgbe_enable_sec_rx_path(hw);
8030         /*
8031          * Workaround:
8032          * As no ixgbe_enable_sec_rx_path equivalent is
8033          * implemented for tx in the base code, and we are
8034          * not allowed to modify the base code in DPDK, so
8035          * just call the hand-written one directly for now.
8036          */
8037         ixgbe_enable_sec_tx_path_generic(hw);
8038
8039         return 0;
8040 }
8041
8042 int
8043 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8044 {
8045         struct ixgbe_hw *hw;
8046         struct rte_eth_dev *dev;
8047         uint32_t ctrl;
8048
8049         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8050
8051         dev = &rte_eth_devices[port];
8052         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8053
8054         /* Stop the data paths */
8055         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8056                 return -ENOTSUP;
8057         /*
8058          * Workaround:
8059          * As no ixgbe_disable_sec_rx_path equivalent is
8060          * implemented for tx in the base code, and we are
8061          * not allowed to modify the base code in DPDK, so
8062          * just call the hand-written one directly for now.
8063          * The hardware support has been checked by
8064          * ixgbe_disable_sec_rx_path().
8065          */
8066         ixgbe_disable_sec_tx_path_generic(hw);
8067
8068         /* Disable the TX and RX crypto engines */
8069         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8070         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8071         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8072
8073         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8074         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8075         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8076
8077         /* Disable SA lookup */
8078         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8079         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8080         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8081         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8082
8083         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8084         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8085         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8086         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8087
8088         /* Start the data paths */
8089         ixgbe_enable_sec_rx_path(hw);
8090         /*
8091          * Workaround:
8092          * As no ixgbe_enable_sec_rx_path equivalent is
8093          * implemented for tx in the base code, and we are
8094          * not allowed to modify the base code in DPDK, so
8095          * just call the hand-written one directly for now.
8096          */
8097         ixgbe_enable_sec_tx_path_generic(hw);
8098
8099         return 0;
8100 }
8101
8102 int
8103 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8104 {
8105         struct ixgbe_hw *hw;
8106         struct rte_eth_dev *dev;
8107         uint32_t ctrl;
8108
8109         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8110
8111         dev = &rte_eth_devices[port];
8112         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8113
8114         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8115         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8116
8117         ctrl = mac[4] | (mac[5] << 8);
8118         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8119
8120         return 0;
8121 }
8122
8123 int
8124 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8125 {
8126         struct ixgbe_hw *hw;
8127         struct rte_eth_dev *dev;
8128         uint32_t ctrl;
8129
8130         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8131
8132         dev = &rte_eth_devices[port];
8133         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8134
8135         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8136         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8137
8138         pi = rte_cpu_to_be_16(pi);
8139         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8140         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8141
8142         return 0;
8143 }
8144
8145 int
8146 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8147                                  uint32_t pn, uint8_t *key)
8148 {
8149         struct ixgbe_hw *hw;
8150         struct rte_eth_dev *dev;
8151         uint32_t ctrl, i;
8152
8153         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8154
8155         dev = &rte_eth_devices[port];
8156         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8157
8158         if (idx != 0 && idx != 1)
8159                 return -EINVAL;
8160
8161         if (an >= 4)
8162                 return -EINVAL;
8163
8164         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8165
8166         /* Set the PN and key */
8167         pn = rte_cpu_to_be_32(pn);
8168         if (idx == 0) {
8169                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8170
8171                 for (i = 0; i < 4; i++) {
8172                         ctrl = (key[i * 4 + 0] <<  0) |
8173                                (key[i * 4 + 1] <<  8) |
8174                                (key[i * 4 + 2] << 16) |
8175                                (key[i * 4 + 3] << 24);
8176                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8177                 }
8178         } else {
8179                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8180
8181                 for (i = 0; i < 4; i++) {
8182                         ctrl = (key[i * 4 + 0] <<  0) |
8183                                (key[i * 4 + 1] <<  8) |
8184                                (key[i * 4 + 2] << 16) |
8185                                (key[i * 4 + 3] << 24);
8186                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8187                 }
8188         }
8189
8190         /* Set AN and select the SA */
8191         ctrl = (an << idx * 2) | (idx << 4);
8192         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8193
8194         return 0;
8195 }
8196
8197 int
8198 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8199                                  uint32_t pn, uint8_t *key)
8200 {
8201         struct ixgbe_hw *hw;
8202         struct rte_eth_dev *dev;
8203         uint32_t ctrl, i;
8204
8205         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8206
8207         dev = &rte_eth_devices[port];
8208         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8209
8210         if (idx != 0 && idx != 1)
8211                 return -EINVAL;
8212
8213         if (an >= 4)
8214                 return -EINVAL;
8215
8216         /* Set the PN */
8217         pn = rte_cpu_to_be_32(pn);
8218         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8219
8220         /* Set the key */
8221         for (i = 0; i < 4; i++) {
8222                 ctrl = (key[i * 4 + 0] <<  0) |
8223                        (key[i * 4 + 1] <<  8) |
8224                        (key[i * 4 + 2] << 16) |
8225                        (key[i * 4 + 3] << 24);
8226                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8227         }
8228
8229         /* Set the AN and validate the SA */
8230         ctrl = an | (1 << 2);
8231         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8232
8233         return 0;
8234 }
8235
8236 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8237 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8238 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8239 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8240 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8241 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");