1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_kvargs.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_hash_crc.h>
36 #ifdef RTE_LIBRTE_SECURITY
37 #include <rte_security_driver.h>
40 #include "ixgbe_logs.h"
41 #include "base/ixgbe_api.h"
42 #include "base/ixgbe_vf.h"
43 #include "base/ixgbe_common.h"
44 #include "ixgbe_ethdev.h"
45 #include "ixgbe_bypass.h"
46 #include "ixgbe_rxtx.h"
47 #include "base/ixgbe_type.h"
48 #include "base/ixgbe_phy.h"
49 #include "ixgbe_regs.h"
52 * High threshold controlling when to start sending XOFF frames. Must be at
53 * least 8 bytes less than receive packet buffer size. This value is in units
56 #define IXGBE_FC_HI 0x80
59 * Low threshold controlling when to start sending XON frames. This value is
60 * in units of 1024 bytes.
62 #define IXGBE_FC_LO 0x40
64 /* Timer value included in XOFF frames. */
65 #define IXGBE_FC_PAUSE 0x680
67 /*Default value of Max Rx Queue*/
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
74 #define IXGBE_MMW_SIZE_DEFAULT 0x4
75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
79 * Default values for RX/TX configuration
81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
82 #define IXGBE_DEFAULT_RX_PTHRESH 8
83 #define IXGBE_DEFAULT_RX_HTHRESH 8
84 #define IXGBE_DEFAULT_RX_WTHRESH 0
86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
87 #define IXGBE_DEFAULT_TX_PTHRESH 32
88 #define IXGBE_DEFAULT_TX_HTHRESH 0
89 #define IXGBE_DEFAULT_TX_WTHRESH 0
90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
95 #define IXGBE_8_BIT_WIDTH CHAR_BIT
96 #define IXGBE_8_BIT_MASK UINT8_MAX
98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
102 /* Additional timesync values. */
103 #define NSEC_PER_SEC 1000000000L
104 #define IXGBE_INCVAL_10GB 0x66666666
105 #define IXGBE_INCVAL_1GB 0x40000000
106 #define IXGBE_INCVAL_100 0x50000000
107 #define IXGBE_INCVAL_SHIFT_10GB 28
108 #define IXGBE_INCVAL_SHIFT_1GB 24
109 #define IXGBE_INCVAL_SHIFT_100 21
110 #define IXGBE_INCVAL_SHIFT_82599 7
111 #define IXGBE_INCPER_SHIFT_82599 24
113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
117 #define IXGBE_ETAG_ETYPE 0x00005084
118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
120 #define IXGBE_RAH_ADTYPE 0x40000000
121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
125 #define IXGBE_QDE_STRIP_TAG 0x00000004
126 #define IXGBE_VTEICR_MASK 0x07
128 #define IXGBE_EXVET_VET_EXT_SHIFT 16
129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk"
133 static const char * const ixgbevf_valid_arguments[] = {
134 IXGBEVF_DEVARG_PFLINK_FULLCHK,
138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
157 int wait_to_complete);
158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
166 uint64_t *values, unsigned int n);
167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names, unsigned limit);
174 static int ixgbe_dev_xstats_get_names_by_id(
175 struct rte_eth_dev *dev,
176 struct rte_eth_xstat_name *xstats_names,
179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_fc_conf *fc_conf);
216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
217 struct rte_eth_pfc_conf *pfc_conf);
218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
222 struct rte_eth_rss_reta_entry64 *reta_conf,
224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
230 static void ixgbe_dev_interrupt_handler(void *param);
231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
235 struct rte_ether_addr *mac_addr,
236 uint32_t index, uint32_t pool);
237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
239 struct rte_ether_addr *mac_addr);
240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
241 static bool is_device_supported(struct rte_eth_dev *dev,
242 struct rte_pci_driver *drv);
244 /* For Virtual Function support */
245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
247 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
248 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
250 int wait_to_complete);
251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
253 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
257 struct rte_eth_stats *stats);
258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
260 uint16_t vlan_id, int on);
261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
262 uint16_t queue, int on);
263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
271 uint8_t queue, uint8_t msix_vector);
272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
275 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
276 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
278 /* For Eth VMDQ APIs support */
279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
280 rte_ether_addr * mac_addr, uint8_t on);
281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
283 struct rte_eth_mirror_conf *mirror_conf,
284 uint8_t rule_id, uint8_t on);
285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
292 uint8_t queue, uint8_t msix_vector);
293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
296 struct rte_ether_addr *mac_addr,
297 uint32_t index, uint32_t pool);
298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
300 struct rte_ether_addr *mac_addr);
301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
302 struct rte_eth_syn_filter *filter);
303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
304 enum rte_filter_op filter_op,
306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
307 struct ixgbe_5tuple_filter *filter);
308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
309 struct ixgbe_5tuple_filter *filter);
310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
311 enum rte_filter_op filter_op,
313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
314 struct rte_eth_ntuple_filter *filter);
315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
316 enum rte_filter_op filter_op,
318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
319 struct rte_eth_ethertype_filter *filter);
320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
321 enum rte_filter_type filter_type,
322 enum rte_filter_op filter_op,
324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
327 struct rte_ether_addr *mc_addr_set,
328 uint32_t nb_mc_addr);
329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
330 struct rte_eth_dcb_info *dcb_info);
332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
334 struct rte_dev_reg_info *regs);
335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
337 struct rte_dev_eeprom_info *eeprom);
338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
339 struct rte_dev_eeprom_info *eeprom);
341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
342 struct rte_eth_dev_module_info *modinfo);
343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
344 struct rte_dev_eeprom_info *info);
346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
348 struct rte_dev_reg_info *regs);
350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
353 struct timespec *timestamp,
355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
359 struct timespec *timestamp);
360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
361 const struct timespec *timestamp);
362 static void ixgbevf_dev_interrupt_handler(void *param);
364 static int ixgbe_dev_l2_tunnel_eth_type_conf
365 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
366 static int ixgbe_dev_l2_tunnel_offload_set
367 (struct rte_eth_dev *dev,
368 struct rte_eth_l2_tunnel_conf *l2_tunnel,
371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
372 enum rte_filter_op filter_op,
375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
376 struct rte_eth_udp_tunnel *udp_tunnel);
377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
378 struct rte_eth_udp_tunnel *udp_tunnel);
379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
381 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
384 * Define VF Stats MACRO for Non "cleared on read" register
386 #define UPDATE_VF_STAT(reg, last, cur) \
388 uint32_t latest = IXGBE_READ_REG(hw, reg); \
389 cur += (latest - last) & UINT_MAX; \
393 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
395 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
396 u64 new_msb = IXGBE_READ_REG(hw, msb); \
397 u64 latest = ((new_msb << 32) | new_lsb); \
398 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
402 #define IXGBE_SET_HWSTRIP(h, q) do {\
403 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
404 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
405 (h)->bitmap[idx] |= 1 << bit;\
408 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
409 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
410 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
411 (h)->bitmap[idx] &= ~(1 << bit);\
414 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
415 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
416 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
417 (r) = (h)->bitmap[idx] >> bit & 1;\
420 int ixgbe_logtype_init;
421 int ixgbe_logtype_driver;
423 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
424 int ixgbe_logtype_rx;
426 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
427 int ixgbe_logtype_tx;
429 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
430 int ixgbe_logtype_tx_free;
434 * The set of PCI devices this driver supports
436 static const struct rte_pci_id pci_id_ixgbe_map[] = {
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
485 #ifdef RTE_LIBRTE_IXGBE_BYPASS
486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
488 { .vendor_id = 0, /* sentinel */ },
492 * The set of PCI devices this driver supports (for 82599 VF)
494 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
504 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
505 { .vendor_id = 0, /* sentinel */ },
508 static const struct rte_eth_desc_lim rx_desc_lim = {
509 .nb_max = IXGBE_MAX_RING_DESC,
510 .nb_min = IXGBE_MIN_RING_DESC,
511 .nb_align = IXGBE_RXD_ALIGN,
514 static const struct rte_eth_desc_lim tx_desc_lim = {
515 .nb_max = IXGBE_MAX_RING_DESC,
516 .nb_min = IXGBE_MIN_RING_DESC,
517 .nb_align = IXGBE_TXD_ALIGN,
518 .nb_seg_max = IXGBE_TX_MAX_SEG,
519 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
522 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
523 .dev_configure = ixgbe_dev_configure,
524 .dev_start = ixgbe_dev_start,
525 .dev_stop = ixgbe_dev_stop,
526 .dev_set_link_up = ixgbe_dev_set_link_up,
527 .dev_set_link_down = ixgbe_dev_set_link_down,
528 .dev_close = ixgbe_dev_close,
529 .dev_reset = ixgbe_dev_reset,
530 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
531 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
532 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
533 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
534 .link_update = ixgbe_dev_link_update,
535 .stats_get = ixgbe_dev_stats_get,
536 .xstats_get = ixgbe_dev_xstats_get,
537 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
538 .stats_reset = ixgbe_dev_stats_reset,
539 .xstats_reset = ixgbe_dev_xstats_reset,
540 .xstats_get_names = ixgbe_dev_xstats_get_names,
541 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
542 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
543 .fw_version_get = ixgbe_fw_version_get,
544 .dev_infos_get = ixgbe_dev_info_get,
545 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
546 .mtu_set = ixgbe_dev_mtu_set,
547 .vlan_filter_set = ixgbe_vlan_filter_set,
548 .vlan_tpid_set = ixgbe_vlan_tpid_set,
549 .vlan_offload_set = ixgbe_vlan_offload_set,
550 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
551 .rx_queue_start = ixgbe_dev_rx_queue_start,
552 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
553 .tx_queue_start = ixgbe_dev_tx_queue_start,
554 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
555 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
556 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
557 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
558 .rx_queue_release = ixgbe_dev_rx_queue_release,
559 .rx_queue_count = ixgbe_dev_rx_queue_count,
560 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
561 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
562 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
563 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
564 .tx_queue_release = ixgbe_dev_tx_queue_release,
565 .dev_led_on = ixgbe_dev_led_on,
566 .dev_led_off = ixgbe_dev_led_off,
567 .flow_ctrl_get = ixgbe_flow_ctrl_get,
568 .flow_ctrl_set = ixgbe_flow_ctrl_set,
569 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
570 .mac_addr_add = ixgbe_add_rar,
571 .mac_addr_remove = ixgbe_remove_rar,
572 .mac_addr_set = ixgbe_set_default_mac_addr,
573 .uc_hash_table_set = ixgbe_uc_hash_table_set,
574 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
575 .mirror_rule_set = ixgbe_mirror_rule_set,
576 .mirror_rule_reset = ixgbe_mirror_rule_reset,
577 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
578 .reta_update = ixgbe_dev_rss_reta_update,
579 .reta_query = ixgbe_dev_rss_reta_query,
580 .rss_hash_update = ixgbe_dev_rss_hash_update,
581 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
582 .filter_ctrl = ixgbe_dev_filter_ctrl,
583 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
584 .rxq_info_get = ixgbe_rxq_info_get,
585 .txq_info_get = ixgbe_txq_info_get,
586 .timesync_enable = ixgbe_timesync_enable,
587 .timesync_disable = ixgbe_timesync_disable,
588 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
589 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
590 .get_reg = ixgbe_get_regs,
591 .get_eeprom_length = ixgbe_get_eeprom_length,
592 .get_eeprom = ixgbe_get_eeprom,
593 .set_eeprom = ixgbe_set_eeprom,
594 .get_module_info = ixgbe_get_module_info,
595 .get_module_eeprom = ixgbe_get_module_eeprom,
596 .get_dcb_info = ixgbe_dev_get_dcb_info,
597 .timesync_adjust_time = ixgbe_timesync_adjust_time,
598 .timesync_read_time = ixgbe_timesync_read_time,
599 .timesync_write_time = ixgbe_timesync_write_time,
600 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
601 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
602 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
603 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
604 .tm_ops_get = ixgbe_tm_ops_get,
605 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
609 * dev_ops for virtual function, bare necessities for basic vf
610 * operation have been implemented
612 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
613 .dev_configure = ixgbevf_dev_configure,
614 .dev_start = ixgbevf_dev_start,
615 .dev_stop = ixgbevf_dev_stop,
616 .link_update = ixgbevf_dev_link_update,
617 .stats_get = ixgbevf_dev_stats_get,
618 .xstats_get = ixgbevf_dev_xstats_get,
619 .stats_reset = ixgbevf_dev_stats_reset,
620 .xstats_reset = ixgbevf_dev_stats_reset,
621 .xstats_get_names = ixgbevf_dev_xstats_get_names,
622 .dev_close = ixgbevf_dev_close,
623 .dev_reset = ixgbevf_dev_reset,
624 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
625 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
626 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
627 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
628 .dev_infos_get = ixgbevf_dev_info_get,
629 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
630 .mtu_set = ixgbevf_dev_set_mtu,
631 .vlan_filter_set = ixgbevf_vlan_filter_set,
632 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
633 .vlan_offload_set = ixgbevf_vlan_offload_set,
634 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
635 .rx_queue_release = ixgbe_dev_rx_queue_release,
636 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
637 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
638 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
639 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
640 .tx_queue_release = ixgbe_dev_tx_queue_release,
641 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
642 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
643 .mac_addr_add = ixgbevf_add_mac_addr,
644 .mac_addr_remove = ixgbevf_remove_mac_addr,
645 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
646 .rxq_info_get = ixgbe_rxq_info_get,
647 .txq_info_get = ixgbe_txq_info_get,
648 .mac_addr_set = ixgbevf_set_default_mac_addr,
649 .get_reg = ixgbevf_get_regs,
650 .reta_update = ixgbe_dev_rss_reta_update,
651 .reta_query = ixgbe_dev_rss_reta_query,
652 .rss_hash_update = ixgbe_dev_rss_hash_update,
653 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
654 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
657 /* store statistics names and its offset in stats structure */
658 struct rte_ixgbe_xstats_name_off {
659 char name[RTE_ETH_XSTATS_NAME_SIZE];
663 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
664 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
665 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
666 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
667 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
668 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
669 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
670 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
671 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
672 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
673 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
674 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
675 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
676 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
677 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
678 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
680 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
682 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
683 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
684 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
685 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
686 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
687 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
688 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
689 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
690 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
691 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
692 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
693 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
694 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
695 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
696 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
697 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
698 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
700 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
702 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
703 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
704 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
705 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
707 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
709 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
711 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
713 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
715 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
717 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
720 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
721 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
722 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
724 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
725 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
726 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
727 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
728 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
730 {"rx_fcoe_no_direct_data_placement_ext_buff",
731 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
733 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
735 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
737 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
739 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
741 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
744 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
745 sizeof(rte_ixgbe_stats_strings[0]))
747 /* MACsec statistics */
748 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
749 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
751 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
752 out_pkts_encrypted)},
753 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
754 out_pkts_protected)},
755 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
756 out_octets_encrypted)},
757 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
758 out_octets_protected)},
759 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
761 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
763 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
765 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
766 in_pkts_unknownsci)},
767 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
768 in_octets_decrypted)},
769 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
770 in_octets_validated)},
771 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
773 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
775 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
777 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
779 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
781 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
783 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
785 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
786 in_pkts_notusingsa)},
789 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
790 sizeof(rte_ixgbe_macsec_strings[0]))
792 /* Per-queue statistics */
793 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
794 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
795 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
796 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
797 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
800 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
801 sizeof(rte_ixgbe_rxq_strings[0]))
802 #define IXGBE_NB_RXQ_PRIO_VALUES 8
804 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
805 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
806 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
807 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
811 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
812 sizeof(rte_ixgbe_txq_strings[0]))
813 #define IXGBE_NB_TXQ_PRIO_VALUES 8
815 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
816 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
819 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
820 sizeof(rte_ixgbevf_stats_strings[0]))
823 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
826 ixgbe_is_sfp(struct ixgbe_hw *hw)
828 switch (hw->phy.type) {
829 case ixgbe_phy_sfp_avago:
830 case ixgbe_phy_sfp_ftl:
831 case ixgbe_phy_sfp_intel:
832 case ixgbe_phy_sfp_unknown:
833 case ixgbe_phy_sfp_passive_tyco:
834 case ixgbe_phy_sfp_passive_unknown:
841 static inline int32_t
842 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
847 status = ixgbe_reset_hw(hw);
849 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
850 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
851 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
852 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
853 IXGBE_WRITE_FLUSH(hw);
855 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
856 status = IXGBE_SUCCESS;
861 ixgbe_enable_intr(struct rte_eth_dev *dev)
863 struct ixgbe_interrupt *intr =
864 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
865 struct ixgbe_hw *hw =
866 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
868 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
869 IXGBE_WRITE_FLUSH(hw);
873 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
876 ixgbe_disable_intr(struct ixgbe_hw *hw)
878 PMD_INIT_FUNC_TRACE();
880 if (hw->mac.type == ixgbe_mac_82598EB) {
881 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
883 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
884 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
885 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
887 IXGBE_WRITE_FLUSH(hw);
891 * This function resets queue statistics mapping registers.
892 * From Niantic datasheet, Initialization of Statistics section:
893 * "...if software requires the queue counters, the RQSMR and TQSM registers
894 * must be re-programmed following a device reset.
897 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
901 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
902 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
903 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
909 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
914 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
915 #define NB_QMAP_FIELDS_PER_QSM_REG 4
916 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
918 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
919 struct ixgbe_stat_mapping_registers *stat_mappings =
920 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
921 uint32_t qsmr_mask = 0;
922 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
926 if ((hw->mac.type != ixgbe_mac_82599EB) &&
927 (hw->mac.type != ixgbe_mac_X540) &&
928 (hw->mac.type != ixgbe_mac_X550) &&
929 (hw->mac.type != ixgbe_mac_X550EM_x) &&
930 (hw->mac.type != ixgbe_mac_X550EM_a))
933 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
934 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
937 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
938 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
939 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
942 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
944 /* Now clear any previous stat_idx set */
945 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
947 stat_mappings->tqsm[n] &= ~clearing_mask;
949 stat_mappings->rqsmr[n] &= ~clearing_mask;
951 q_map = (uint32_t)stat_idx;
952 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
953 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
955 stat_mappings->tqsm[n] |= qsmr_mask;
957 stat_mappings->rqsmr[n] |= qsmr_mask;
959 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
960 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
962 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
963 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
965 /* Now write the mapping in the appropriate register */
967 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
968 stat_mappings->rqsmr[n], n);
969 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
971 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
972 stat_mappings->tqsm[n], n);
973 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
979 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
981 struct ixgbe_stat_mapping_registers *stat_mappings =
982 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
983 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
986 /* write whatever was in stat mapping table to the NIC */
987 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
989 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
992 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
997 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1000 struct ixgbe_dcb_tc_config *tc;
1001 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1003 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1004 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1005 for (i = 0; i < dcb_max_tc; i++) {
1006 tc = &dcb_config->tc_config[i];
1007 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1008 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1009 (uint8_t)(100/dcb_max_tc + (i & 1));
1010 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1011 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1012 (uint8_t)(100/dcb_max_tc + (i & 1));
1013 tc->pfc = ixgbe_dcb_pfc_disabled;
1016 /* Initialize default user to priority mapping, UPx->TC0 */
1017 tc = &dcb_config->tc_config[0];
1018 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1019 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1020 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1021 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1022 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1024 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1025 dcb_config->pfc_mode_enable = false;
1026 dcb_config->vt_mode = true;
1027 dcb_config->round_robin_enable = false;
1028 /* support all DCB capabilities in 82599 */
1029 dcb_config->support.capabilities = 0xFF;
1031 /*we only support 4 Tcs for X540, X550 */
1032 if (hw->mac.type == ixgbe_mac_X540 ||
1033 hw->mac.type == ixgbe_mac_X550 ||
1034 hw->mac.type == ixgbe_mac_X550EM_x ||
1035 hw->mac.type == ixgbe_mac_X550EM_a) {
1036 dcb_config->num_tcs.pg_tcs = 4;
1037 dcb_config->num_tcs.pfc_tcs = 4;
1042 * Ensure that all locks are released before first NVM or PHY access
1045 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1050 * Phy lock should not fail in this early stage. If this is the case,
1051 * it is due to an improper exit of the application.
1052 * So force the release of the faulty lock. Release of common lock
1053 * is done automatically by swfw_sync function.
1055 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1056 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1057 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1059 ixgbe_release_swfw_semaphore(hw, mask);
1062 * These ones are more tricky since they are common to all ports; but
1063 * swfw_sync retries last long enough (1s) to be almost sure that if
1064 * lock can not be taken it is due to an improper lock of the
1067 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1068 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1069 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1071 ixgbe_release_swfw_semaphore(hw, mask);
1075 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1076 * It returns 0 on success.
1079 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1081 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1082 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1083 struct ixgbe_hw *hw =
1084 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1085 struct ixgbe_vfta *shadow_vfta =
1086 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1087 struct ixgbe_hwstrip *hwstrip =
1088 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1089 struct ixgbe_dcb_config *dcb_config =
1090 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1091 struct ixgbe_filter_info *filter_info =
1092 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1093 struct ixgbe_bw_conf *bw_conf =
1094 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1099 PMD_INIT_FUNC_TRACE();
1101 ixgbe_dev_macsec_setting_reset(eth_dev);
1103 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1104 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1105 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1106 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1109 * For secondary processes, we don't initialise any further as primary
1110 * has already done this work. Only check we don't need a different
1111 * RX and TX function.
1113 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1114 struct ixgbe_tx_queue *txq;
1115 /* TX queue function in primary, set by last queue initialized
1116 * Tx queue may not initialized by primary process
1118 if (eth_dev->data->tx_queues) {
1119 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1120 ixgbe_set_tx_function(eth_dev, txq);
1122 /* Use default TX function if we get here */
1123 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1124 "Using default TX function.");
1127 ixgbe_set_rx_function(eth_dev);
1132 rte_eth_copy_pci_info(eth_dev, pci_dev);
1134 /* Vendor and Device ID need to be set before init of shared code */
1135 hw->device_id = pci_dev->id.device_id;
1136 hw->vendor_id = pci_dev->id.vendor_id;
1137 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1138 hw->allow_unsupported_sfp = 1;
1140 /* Initialize the shared code (base driver) */
1141 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1142 diag = ixgbe_bypass_init_shared_code(hw);
1144 diag = ixgbe_init_shared_code(hw);
1145 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1147 if (diag != IXGBE_SUCCESS) {
1148 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1152 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1153 PMD_INIT_LOG(ERR, "\nERROR: "
1154 "Firmware recovery mode detected. Limiting functionality.\n"
1155 "Refer to the Intel(R) Ethernet Adapters and Devices "
1156 "User Guide for details on firmware recovery mode.");
1160 /* pick up the PCI bus settings for reporting later */
1161 ixgbe_get_bus_info(hw);
1163 /* Unlock any pending hardware semaphore */
1164 ixgbe_swfw_lock_reset(hw);
1166 #ifdef RTE_LIBRTE_SECURITY
1167 /* Initialize security_ctx only for primary process*/
1168 if (ixgbe_ipsec_ctx_create(eth_dev))
1172 /* Initialize DCB configuration*/
1173 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1174 ixgbe_dcb_init(hw, dcb_config);
1175 /* Get Hardware Flow Control setting */
1176 hw->fc.requested_mode = ixgbe_fc_full;
1177 hw->fc.current_mode = ixgbe_fc_full;
1178 hw->fc.pause_time = IXGBE_FC_PAUSE;
1179 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1180 hw->fc.low_water[i] = IXGBE_FC_LO;
1181 hw->fc.high_water[i] = IXGBE_FC_HI;
1183 hw->fc.send_xon = 1;
1185 /* Make sure we have a good EEPROM before we read from it */
1186 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1187 if (diag != IXGBE_SUCCESS) {
1188 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1192 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1193 diag = ixgbe_bypass_init_hw(hw);
1195 diag = ixgbe_init_hw(hw);
1196 hw->mac.autotry_restart = false;
1197 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1200 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1201 * is called too soon after the kernel driver unbinding/binding occurs.
1202 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1203 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1204 * also called. See ixgbe_identify_phy_82599(). The reason for the
1205 * failure is not known, and only occuts when virtualisation features
1206 * are disabled in the bios. A delay of 100ms was found to be enough by
1207 * trial-and-error, and is doubled to be safe.
1209 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1211 diag = ixgbe_init_hw(hw);
1214 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1215 diag = IXGBE_SUCCESS;
1217 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1218 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1219 "LOM. Please be aware there may be issues associated "
1220 "with your hardware.");
1221 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1222 "please contact your Intel or hardware representative "
1223 "who provided you with this hardware.");
1224 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1225 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1227 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1231 /* Reset the hw statistics */
1232 ixgbe_dev_stats_reset(eth_dev);
1234 /* disable interrupt */
1235 ixgbe_disable_intr(hw);
1237 /* reset mappings for queue statistics hw counters*/
1238 ixgbe_reset_qstat_mappings(hw);
1240 /* Allocate memory for storing MAC addresses */
1241 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1242 hw->mac.num_rar_entries, 0);
1243 if (eth_dev->data->mac_addrs == NULL) {
1245 "Failed to allocate %u bytes needed to store "
1247 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1250 /* Copy the permanent MAC address */
1251 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1252 ð_dev->data->mac_addrs[0]);
1254 /* Allocate memory for storing hash filter MAC addresses */
1255 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1256 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1257 if (eth_dev->data->hash_mac_addrs == NULL) {
1259 "Failed to allocate %d bytes needed to store MAC addresses",
1260 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1264 /* Pass the information to the rte_eth_dev_close() that it should also
1265 * release the private port resources.
1267 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1269 /* initialize the vfta */
1270 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1272 /* initialize the hw strip bitmap*/
1273 memset(hwstrip, 0, sizeof(*hwstrip));
1275 /* initialize PF if max_vfs not zero */
1276 ixgbe_pf_host_init(eth_dev);
1278 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1279 /* let hardware know driver is loaded */
1280 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1281 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1282 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1283 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1284 IXGBE_WRITE_FLUSH(hw);
1286 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1287 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1288 (int) hw->mac.type, (int) hw->phy.type,
1289 (int) hw->phy.sfp_type);
1291 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1292 (int) hw->mac.type, (int) hw->phy.type);
1294 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1295 eth_dev->data->port_id, pci_dev->id.vendor_id,
1296 pci_dev->id.device_id);
1298 rte_intr_callback_register(intr_handle,
1299 ixgbe_dev_interrupt_handler, eth_dev);
1301 /* enable uio/vfio intr/eventfd mapping */
1302 rte_intr_enable(intr_handle);
1304 /* enable support intr */
1305 ixgbe_enable_intr(eth_dev);
1307 ixgbe_dev_set_link_down(eth_dev);
1309 /* initialize filter info */
1310 memset(filter_info, 0,
1311 sizeof(struct ixgbe_filter_info));
1313 /* initialize 5tuple filter list */
1314 TAILQ_INIT(&filter_info->fivetuple_list);
1316 /* initialize flow director filter list & hash */
1317 ixgbe_fdir_filter_init(eth_dev);
1319 /* initialize l2 tunnel filter list & hash */
1320 ixgbe_l2_tn_filter_init(eth_dev);
1322 /* initialize flow filter lists */
1323 ixgbe_filterlist_init();
1325 /* initialize bandwidth configuration info */
1326 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1328 /* initialize Traffic Manager configuration */
1329 ixgbe_tm_conf_init(eth_dev);
1335 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1337 PMD_INIT_FUNC_TRACE();
1339 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1342 ixgbe_dev_close(eth_dev);
1347 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1349 struct ixgbe_filter_info *filter_info =
1350 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1351 struct ixgbe_5tuple_filter *p_5tuple;
1353 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1354 TAILQ_REMOVE(&filter_info->fivetuple_list,
1359 memset(filter_info->fivetuple_mask, 0,
1360 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1365 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1367 struct ixgbe_hw_fdir_info *fdir_info =
1368 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1369 struct ixgbe_fdir_filter *fdir_filter;
1371 if (fdir_info->hash_map)
1372 rte_free(fdir_info->hash_map);
1373 if (fdir_info->hash_handle)
1374 rte_hash_free(fdir_info->hash_handle);
1376 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1377 TAILQ_REMOVE(&fdir_info->fdir_list,
1380 rte_free(fdir_filter);
1386 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1388 struct ixgbe_l2_tn_info *l2_tn_info =
1389 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1390 struct ixgbe_l2_tn_filter *l2_tn_filter;
1392 if (l2_tn_info->hash_map)
1393 rte_free(l2_tn_info->hash_map);
1394 if (l2_tn_info->hash_handle)
1395 rte_hash_free(l2_tn_info->hash_handle);
1397 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1398 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1401 rte_free(l2_tn_filter);
1407 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1409 struct ixgbe_hw_fdir_info *fdir_info =
1410 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1411 char fdir_hash_name[RTE_HASH_NAMESIZE];
1412 struct rte_hash_parameters fdir_hash_params = {
1413 .name = fdir_hash_name,
1414 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1415 .key_len = sizeof(union ixgbe_atr_input),
1416 .hash_func = rte_hash_crc,
1417 .hash_func_init_val = 0,
1418 .socket_id = rte_socket_id(),
1421 TAILQ_INIT(&fdir_info->fdir_list);
1422 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1423 "fdir_%s", eth_dev->device->name);
1424 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1425 if (!fdir_info->hash_handle) {
1426 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1429 fdir_info->hash_map = rte_zmalloc("ixgbe",
1430 sizeof(struct ixgbe_fdir_filter *) *
1431 IXGBE_MAX_FDIR_FILTER_NUM,
1433 if (!fdir_info->hash_map) {
1435 "Failed to allocate memory for fdir hash map!");
1438 fdir_info->mask_added = FALSE;
1443 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1445 struct ixgbe_l2_tn_info *l2_tn_info =
1446 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1447 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1448 struct rte_hash_parameters l2_tn_hash_params = {
1449 .name = l2_tn_hash_name,
1450 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1451 .key_len = sizeof(struct ixgbe_l2_tn_key),
1452 .hash_func = rte_hash_crc,
1453 .hash_func_init_val = 0,
1454 .socket_id = rte_socket_id(),
1457 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1458 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1459 "l2_tn_%s", eth_dev->device->name);
1460 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1461 if (!l2_tn_info->hash_handle) {
1462 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1465 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1466 sizeof(struct ixgbe_l2_tn_filter *) *
1467 IXGBE_MAX_L2_TN_FILTER_NUM,
1469 if (!l2_tn_info->hash_map) {
1471 "Failed to allocate memory for L2 TN hash map!");
1474 l2_tn_info->e_tag_en = FALSE;
1475 l2_tn_info->e_tag_fwd_en = FALSE;
1476 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1481 * Negotiate mailbox API version with the PF.
1482 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1483 * Then we try to negotiate starting with the most recent one.
1484 * If all negotiation attempts fail, then we will proceed with
1485 * the default one (ixgbe_mbox_api_10).
1488 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1492 /* start with highest supported, proceed down */
1493 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1501 i != RTE_DIM(sup_ver) &&
1502 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1508 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1512 /* Set Organizationally Unique Identifier (OUI) prefix. */
1513 mac_addr->addr_bytes[0] = 0x00;
1514 mac_addr->addr_bytes[1] = 0x09;
1515 mac_addr->addr_bytes[2] = 0xC0;
1516 /* Force indication of locally assigned MAC address. */
1517 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1518 /* Generate the last 3 bytes of the MAC address with a random number. */
1519 random = rte_rand();
1520 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1524 devarg_handle_int(__rte_unused const char *key, const char *value,
1527 uint16_t *n = extra_args;
1529 if (value == NULL || extra_args == NULL)
1532 *n = (uint16_t)strtoul(value, NULL, 0);
1533 if (*n == USHRT_MAX && errno == ERANGE)
1540 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1541 struct rte_devargs *devargs)
1543 struct rte_kvargs *kvlist;
1544 uint16_t pflink_fullchk;
1546 if (devargs == NULL)
1549 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1553 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1554 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1555 devarg_handle_int, &pflink_fullchk) == 0 &&
1556 pflink_fullchk == 1)
1557 adapter->pflink_fullchk = 1;
1559 rte_kvargs_free(kvlist);
1563 * Virtual Function device init
1566 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1570 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1571 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1572 struct ixgbe_hw *hw =
1573 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1574 struct ixgbe_vfta *shadow_vfta =
1575 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1576 struct ixgbe_hwstrip *hwstrip =
1577 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1578 struct rte_ether_addr *perm_addr =
1579 (struct rte_ether_addr *)hw->mac.perm_addr;
1581 PMD_INIT_FUNC_TRACE();
1583 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1584 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1585 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1587 /* for secondary processes, we don't initialise any further as primary
1588 * has already done this work. Only check we don't need a different
1591 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1592 struct ixgbe_tx_queue *txq;
1593 /* TX queue function in primary, set by last queue initialized
1594 * Tx queue may not initialized by primary process
1596 if (eth_dev->data->tx_queues) {
1597 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1598 ixgbe_set_tx_function(eth_dev, txq);
1600 /* Use default TX function if we get here */
1601 PMD_INIT_LOG(NOTICE,
1602 "No TX queues configured yet. Using default TX function.");
1605 ixgbe_set_rx_function(eth_dev);
1610 ixgbevf_parse_devargs(eth_dev->data->dev_private,
1611 pci_dev->device.devargs);
1613 rte_eth_copy_pci_info(eth_dev, pci_dev);
1615 hw->device_id = pci_dev->id.device_id;
1616 hw->vendor_id = pci_dev->id.vendor_id;
1617 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1619 /* initialize the vfta */
1620 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1622 /* initialize the hw strip bitmap*/
1623 memset(hwstrip, 0, sizeof(*hwstrip));
1625 /* Initialize the shared code (base driver) */
1626 diag = ixgbe_init_shared_code(hw);
1627 if (diag != IXGBE_SUCCESS) {
1628 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1632 /* init_mailbox_params */
1633 hw->mbx.ops.init_params(hw);
1635 /* Reset the hw statistics */
1636 ixgbevf_dev_stats_reset(eth_dev);
1638 /* Disable the interrupts for VF */
1639 ixgbevf_intr_disable(eth_dev);
1641 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1642 diag = hw->mac.ops.reset_hw(hw);
1645 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1646 * the underlying PF driver has not assigned a MAC address to the VF.
1647 * In this case, assign a random MAC address.
1649 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1650 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1652 * This error code will be propagated to the app by
1653 * rte_eth_dev_reset, so use a public error code rather than
1654 * the internal-only IXGBE_ERR_RESET_FAILED
1659 /* negotiate mailbox API version to use with the PF. */
1660 ixgbevf_negotiate_api(hw);
1662 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1663 ixgbevf_get_queues(hw, &tcs, &tc);
1665 /* Allocate memory for storing MAC addresses */
1666 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1667 hw->mac.num_rar_entries, 0);
1668 if (eth_dev->data->mac_addrs == NULL) {
1670 "Failed to allocate %u bytes needed to store "
1672 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1676 /* Pass the information to the rte_eth_dev_close() that it should also
1677 * release the private port resources.
1679 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1681 /* Generate a random MAC address, if none was assigned by PF. */
1682 if (rte_is_zero_ether_addr(perm_addr)) {
1683 generate_random_mac_addr(perm_addr);
1684 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1686 rte_free(eth_dev->data->mac_addrs);
1687 eth_dev->data->mac_addrs = NULL;
1690 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1691 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1692 "%02x:%02x:%02x:%02x:%02x:%02x",
1693 perm_addr->addr_bytes[0],
1694 perm_addr->addr_bytes[1],
1695 perm_addr->addr_bytes[2],
1696 perm_addr->addr_bytes[3],
1697 perm_addr->addr_bytes[4],
1698 perm_addr->addr_bytes[5]);
1701 /* Copy the permanent MAC address */
1702 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1704 /* reset the hardware with the new settings */
1705 diag = hw->mac.ops.start_hw(hw);
1711 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1715 rte_intr_callback_register(intr_handle,
1716 ixgbevf_dev_interrupt_handler, eth_dev);
1717 rte_intr_enable(intr_handle);
1718 ixgbevf_intr_enable(eth_dev);
1720 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1721 eth_dev->data->port_id, pci_dev->id.vendor_id,
1722 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1727 /* Virtual Function device uninit */
1730 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1732 PMD_INIT_FUNC_TRACE();
1734 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1737 ixgbevf_dev_close(eth_dev);
1743 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1744 struct rte_pci_device *pci_dev)
1746 char name[RTE_ETH_NAME_MAX_LEN];
1747 struct rte_eth_dev *pf_ethdev;
1748 struct rte_eth_devargs eth_da;
1751 if (pci_dev->device.devargs) {
1752 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1757 memset(ð_da, 0, sizeof(eth_da));
1759 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1760 sizeof(struct ixgbe_adapter),
1761 eth_dev_pci_specific_init, pci_dev,
1762 eth_ixgbe_dev_init, NULL);
1764 if (retval || eth_da.nb_representor_ports < 1)
1767 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1768 if (pf_ethdev == NULL)
1771 /* probe VF representor ports */
1772 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1773 struct ixgbe_vf_info *vfinfo;
1774 struct ixgbe_vf_representor representor;
1776 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1777 pf_ethdev->data->dev_private);
1778 if (vfinfo == NULL) {
1780 "no virtual functions supported by PF");
1784 representor.vf_id = eth_da.representor_ports[i];
1785 representor.switch_domain_id = vfinfo->switch_domain_id;
1786 representor.pf_ethdev = pf_ethdev;
1788 /* representor port net_bdf_port */
1789 snprintf(name, sizeof(name), "net_%s_representor_%d",
1790 pci_dev->device.name,
1791 eth_da.representor_ports[i]);
1793 retval = rte_eth_dev_create(&pci_dev->device, name,
1794 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1795 ixgbe_vf_representor_init, &representor);
1798 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1799 "representor %s.", name);
1805 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1807 struct rte_eth_dev *ethdev;
1809 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1813 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1814 return rte_eth_dev_pci_generic_remove(pci_dev,
1815 ixgbe_vf_representor_uninit);
1817 return rte_eth_dev_pci_generic_remove(pci_dev,
1818 eth_ixgbe_dev_uninit);
1821 static struct rte_pci_driver rte_ixgbe_pmd = {
1822 .id_table = pci_id_ixgbe_map,
1823 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1824 .probe = eth_ixgbe_pci_probe,
1825 .remove = eth_ixgbe_pci_remove,
1828 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1829 struct rte_pci_device *pci_dev)
1831 return rte_eth_dev_pci_generic_probe(pci_dev,
1832 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1835 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1837 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1841 * virtual function driver struct
1843 static struct rte_pci_driver rte_ixgbevf_pmd = {
1844 .id_table = pci_id_ixgbevf_map,
1845 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1846 .probe = eth_ixgbevf_pci_probe,
1847 .remove = eth_ixgbevf_pci_remove,
1851 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1853 struct ixgbe_hw *hw =
1854 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855 struct ixgbe_vfta *shadow_vfta =
1856 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1861 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1862 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1863 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1868 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1870 /* update local VFTA copy */
1871 shadow_vfta->vfta[vid_idx] = vfta;
1877 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1880 ixgbe_vlan_hw_strip_enable(dev, queue);
1882 ixgbe_vlan_hw_strip_disable(dev, queue);
1886 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1887 enum rte_vlan_type vlan_type,
1890 struct ixgbe_hw *hw =
1891 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1896 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1897 qinq &= IXGBE_DMATXCTL_GDV;
1899 switch (vlan_type) {
1900 case ETH_VLAN_TYPE_INNER:
1902 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1903 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1904 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1905 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1906 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1907 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1908 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1911 PMD_DRV_LOG(ERR, "Inner type is not supported"
1915 case ETH_VLAN_TYPE_OUTER:
1917 /* Only the high 16-bits is valid */
1918 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1919 IXGBE_EXVET_VET_EXT_SHIFT);
1921 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1922 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1923 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1924 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1925 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1926 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1927 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1933 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1941 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1943 struct ixgbe_hw *hw =
1944 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1947 PMD_INIT_FUNC_TRACE();
1949 /* Filter Table Disable */
1950 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1951 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1953 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1957 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1959 struct ixgbe_hw *hw =
1960 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961 struct ixgbe_vfta *shadow_vfta =
1962 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1966 PMD_INIT_FUNC_TRACE();
1968 /* Filter Table Enable */
1969 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1970 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1971 vlnctrl |= IXGBE_VLNCTRL_VFE;
1973 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1975 /* write whatever is in local vfta copy */
1976 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1977 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1981 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1983 struct ixgbe_hwstrip *hwstrip =
1984 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1985 struct ixgbe_rx_queue *rxq;
1987 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1991 IXGBE_SET_HWSTRIP(hwstrip, queue);
1993 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1995 if (queue >= dev->data->nb_rx_queues)
1998 rxq = dev->data->rx_queues[queue];
2001 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2002 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2004 rxq->vlan_flags = PKT_RX_VLAN;
2005 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2010 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2012 struct ixgbe_hw *hw =
2013 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2016 PMD_INIT_FUNC_TRACE();
2018 if (hw->mac.type == ixgbe_mac_82598EB) {
2019 /* No queue level support */
2020 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2024 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2025 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2026 ctrl &= ~IXGBE_RXDCTL_VME;
2027 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2029 /* record those setting for HW strip per queue */
2030 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2034 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2036 struct ixgbe_hw *hw =
2037 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2040 PMD_INIT_FUNC_TRACE();
2042 if (hw->mac.type == ixgbe_mac_82598EB) {
2043 /* No queue level supported */
2044 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2048 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2049 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2050 ctrl |= IXGBE_RXDCTL_VME;
2051 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2053 /* record those setting for HW strip per queue */
2054 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2058 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2060 struct ixgbe_hw *hw =
2061 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2064 PMD_INIT_FUNC_TRACE();
2066 /* DMATXCTRL: Geric Double VLAN Disable */
2067 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2068 ctrl &= ~IXGBE_DMATXCTL_GDV;
2069 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2071 /* CTRL_EXT: Global Double VLAN Disable */
2072 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2073 ctrl &= ~IXGBE_EXTENDED_VLAN;
2074 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2079 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2081 struct ixgbe_hw *hw =
2082 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085 PMD_INIT_FUNC_TRACE();
2087 /* DMATXCTRL: Geric Double VLAN Enable */
2088 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2089 ctrl |= IXGBE_DMATXCTL_GDV;
2090 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2092 /* CTRL_EXT: Global Double VLAN Enable */
2093 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2094 ctrl |= IXGBE_EXTENDED_VLAN;
2095 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2097 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2098 if (hw->mac.type == ixgbe_mac_X550 ||
2099 hw->mac.type == ixgbe_mac_X550EM_x ||
2100 hw->mac.type == ixgbe_mac_X550EM_a) {
2101 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2102 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2103 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2107 * VET EXT field in the EXVET register = 0x8100 by default
2108 * So no need to change. Same to VT field of DMATXCTL register
2113 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2115 struct ixgbe_hw *hw =
2116 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2117 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2120 struct ixgbe_rx_queue *rxq;
2123 PMD_INIT_FUNC_TRACE();
2125 if (hw->mac.type == ixgbe_mac_82598EB) {
2126 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2127 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2128 ctrl |= IXGBE_VLNCTRL_VME;
2129 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2131 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2132 ctrl &= ~IXGBE_VLNCTRL_VME;
2133 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2137 * Other 10G NIC, the VLAN strip can be setup
2138 * per queue in RXDCTL
2140 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2141 rxq = dev->data->rx_queues[i];
2142 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2143 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2144 ctrl |= IXGBE_RXDCTL_VME;
2147 ctrl &= ~IXGBE_RXDCTL_VME;
2150 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2152 /* record those setting for HW strip per queue */
2153 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2159 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2162 struct rte_eth_rxmode *rxmode;
2163 struct ixgbe_rx_queue *rxq;
2165 if (mask & ETH_VLAN_STRIP_MASK) {
2166 rxmode = &dev->data->dev_conf.rxmode;
2167 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2168 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2169 rxq = dev->data->rx_queues[i];
2170 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2173 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2174 rxq = dev->data->rx_queues[i];
2175 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2181 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2183 struct rte_eth_rxmode *rxmode;
2184 rxmode = &dev->data->dev_conf.rxmode;
2186 if (mask & ETH_VLAN_STRIP_MASK) {
2187 ixgbe_vlan_hw_strip_config(dev);
2190 if (mask & ETH_VLAN_FILTER_MASK) {
2191 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2192 ixgbe_vlan_hw_filter_enable(dev);
2194 ixgbe_vlan_hw_filter_disable(dev);
2197 if (mask & ETH_VLAN_EXTEND_MASK) {
2198 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2199 ixgbe_vlan_hw_extend_enable(dev);
2201 ixgbe_vlan_hw_extend_disable(dev);
2208 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2210 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2212 ixgbe_vlan_offload_config(dev, mask);
2218 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2220 struct ixgbe_hw *hw =
2221 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2222 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2223 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2225 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2226 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2230 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2232 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2237 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2240 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2246 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2247 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2248 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2249 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2254 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2256 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2257 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2258 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2259 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2261 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2262 /* check multi-queue mode */
2263 switch (dev_conf->rxmode.mq_mode) {
2264 case ETH_MQ_RX_VMDQ_DCB:
2265 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2267 case ETH_MQ_RX_VMDQ_DCB_RSS:
2268 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2269 PMD_INIT_LOG(ERR, "SRIOV active,"
2270 " unsupported mq_mode rx %d.",
2271 dev_conf->rxmode.mq_mode);
2274 case ETH_MQ_RX_VMDQ_RSS:
2275 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2276 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2277 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2278 PMD_INIT_LOG(ERR, "SRIOV is active,"
2279 " invalid queue number"
2280 " for VMDQ RSS, allowed"
2281 " value are 1, 2 or 4.");
2285 case ETH_MQ_RX_VMDQ_ONLY:
2286 case ETH_MQ_RX_NONE:
2287 /* if nothing mq mode configure, use default scheme */
2288 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2290 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2291 /* SRIOV only works in VMDq enable mode */
2292 PMD_INIT_LOG(ERR, "SRIOV is active,"
2293 " wrong mq_mode rx %d.",
2294 dev_conf->rxmode.mq_mode);
2298 switch (dev_conf->txmode.mq_mode) {
2299 case ETH_MQ_TX_VMDQ_DCB:
2300 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2301 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2303 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2304 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2308 /* check valid queue number */
2309 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2310 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2311 PMD_INIT_LOG(ERR, "SRIOV is active,"
2312 " nb_rx_q=%d nb_tx_q=%d queue number"
2313 " must be less than or equal to %d.",
2315 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2319 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2320 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2324 /* check configuration for vmdb+dcb mode */
2325 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2326 const struct rte_eth_vmdq_dcb_conf *conf;
2328 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2329 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2330 IXGBE_VMDQ_DCB_NB_QUEUES);
2333 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2334 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2335 conf->nb_queue_pools == ETH_32_POOLS)) {
2336 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2337 " nb_queue_pools must be %d or %d.",
2338 ETH_16_POOLS, ETH_32_POOLS);
2342 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2343 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2345 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2346 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2347 IXGBE_VMDQ_DCB_NB_QUEUES);
2350 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2351 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2352 conf->nb_queue_pools == ETH_32_POOLS)) {
2353 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2354 " nb_queue_pools != %d and"
2355 " nb_queue_pools != %d.",
2356 ETH_16_POOLS, ETH_32_POOLS);
2361 /* For DCB mode check our configuration before we go further */
2362 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2363 const struct rte_eth_dcb_rx_conf *conf;
2365 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2366 if (!(conf->nb_tcs == ETH_4_TCS ||
2367 conf->nb_tcs == ETH_8_TCS)) {
2368 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2369 " and nb_tcs != %d.",
2370 ETH_4_TCS, ETH_8_TCS);
2375 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2376 const struct rte_eth_dcb_tx_conf *conf;
2378 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2379 if (!(conf->nb_tcs == ETH_4_TCS ||
2380 conf->nb_tcs == ETH_8_TCS)) {
2381 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2382 " and nb_tcs != %d.",
2383 ETH_4_TCS, ETH_8_TCS);
2389 * When DCB/VT is off, maximum number of queues changes,
2390 * except for 82598EB, which remains constant.
2392 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2393 hw->mac.type != ixgbe_mac_82598EB) {
2394 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2396 "Neither VT nor DCB are enabled, "
2398 IXGBE_NONE_MODE_TX_NB_QUEUES);
2407 ixgbe_dev_configure(struct rte_eth_dev *dev)
2409 struct ixgbe_interrupt *intr =
2410 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2411 struct ixgbe_adapter *adapter = dev->data->dev_private;
2414 PMD_INIT_FUNC_TRACE();
2416 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2417 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2419 /* multipe queue mode checking */
2420 ret = ixgbe_check_mq_mode(dev);
2422 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2427 /* set flag to update link status after init */
2428 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2431 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2432 * allocation or vector Rx preconditions we will reset it.
2434 adapter->rx_bulk_alloc_allowed = true;
2435 adapter->rx_vec_allowed = true;
2441 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2443 struct ixgbe_hw *hw =
2444 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445 struct ixgbe_interrupt *intr =
2446 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2449 /* only set up it on X550EM_X */
2450 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2451 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2452 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2453 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2454 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2455 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2460 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2461 uint16_t tx_rate, uint64_t q_msk)
2463 struct ixgbe_hw *hw;
2464 struct ixgbe_vf_info *vfinfo;
2465 struct rte_eth_link link;
2466 uint8_t nb_q_per_pool;
2467 uint32_t queue_stride;
2468 uint32_t queue_idx, idx = 0, vf_idx;
2470 uint16_t total_rate = 0;
2471 struct rte_pci_device *pci_dev;
2474 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2475 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2479 if (vf >= pci_dev->max_vfs)
2482 if (tx_rate > link.link_speed)
2488 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2490 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2491 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2492 queue_idx = vf * queue_stride;
2493 queue_end = queue_idx + nb_q_per_pool - 1;
2494 if (queue_end >= hw->mac.max_tx_queues)
2498 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2501 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2503 total_rate += vfinfo[vf_idx].tx_rate[idx];
2509 /* Store tx_rate for this vf. */
2510 for (idx = 0; idx < nb_q_per_pool; idx++) {
2511 if (((uint64_t)0x1 << idx) & q_msk) {
2512 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2513 vfinfo[vf].tx_rate[idx] = tx_rate;
2514 total_rate += tx_rate;
2518 if (total_rate > dev->data->dev_link.link_speed) {
2519 /* Reset stored TX rate of the VF if it causes exceed
2522 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2526 /* Set RTTBCNRC of each queue/pool for vf X */
2527 for (; queue_idx <= queue_end; queue_idx++) {
2529 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2537 * Configure device link speed and setup link.
2538 * It returns 0 on success.
2541 ixgbe_dev_start(struct rte_eth_dev *dev)
2543 struct ixgbe_hw *hw =
2544 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2545 struct ixgbe_vf_info *vfinfo =
2546 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2547 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2548 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2549 uint32_t intr_vector = 0;
2551 bool link_up = false, negotiate = 0;
2553 uint32_t allowed_speeds = 0;
2557 uint32_t *link_speeds;
2558 struct ixgbe_tm_conf *tm_conf =
2559 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2560 struct ixgbe_macsec_setting *macsec_setting =
2561 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2563 PMD_INIT_FUNC_TRACE();
2565 /* Stop the link setup handler before resetting the HW. */
2566 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2568 /* disable uio/vfio intr/eventfd mapping */
2569 rte_intr_disable(intr_handle);
2572 hw->adapter_stopped = 0;
2573 ixgbe_stop_adapter(hw);
2575 /* reinitialize adapter
2576 * this calls reset and start
2578 status = ixgbe_pf_reset_hw(hw);
2581 hw->mac.ops.start_hw(hw);
2582 hw->mac.get_link_status = true;
2584 /* configure PF module if SRIOV enabled */
2585 ixgbe_pf_host_configure(dev);
2587 ixgbe_dev_phy_intr_setup(dev);
2589 /* check and configure queue intr-vector mapping */
2590 if ((rte_intr_cap_multiple(intr_handle) ||
2591 !RTE_ETH_DEV_SRIOV(dev).active) &&
2592 dev->data->dev_conf.intr_conf.rxq != 0) {
2593 intr_vector = dev->data->nb_rx_queues;
2594 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2595 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2596 IXGBE_MAX_INTR_QUEUE_NUM);
2599 if (rte_intr_efd_enable(intr_handle, intr_vector))
2603 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2604 intr_handle->intr_vec =
2605 rte_zmalloc("intr_vec",
2606 dev->data->nb_rx_queues * sizeof(int), 0);
2607 if (intr_handle->intr_vec == NULL) {
2608 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2609 " intr_vec", dev->data->nb_rx_queues);
2614 /* confiugre msix for sleep until rx interrupt */
2615 ixgbe_configure_msix(dev);
2617 /* initialize transmission unit */
2618 ixgbe_dev_tx_init(dev);
2620 /* This can fail when allocating mbufs for descriptor rings */
2621 err = ixgbe_dev_rx_init(dev);
2623 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2627 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2628 ETH_VLAN_EXTEND_MASK;
2629 err = ixgbe_vlan_offload_config(dev, mask);
2631 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2635 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2636 /* Enable vlan filtering for VMDq */
2637 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2640 /* Configure DCB hw */
2641 ixgbe_configure_dcb(dev);
2643 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2644 err = ixgbe_fdir_configure(dev);
2649 /* Restore vf rate limit */
2650 if (vfinfo != NULL) {
2651 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2652 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2653 if (vfinfo[vf].tx_rate[idx] != 0)
2654 ixgbe_set_vf_rate_limit(
2656 vfinfo[vf].tx_rate[idx],
2660 ixgbe_restore_statistics_mapping(dev);
2662 err = ixgbe_dev_rxtx_start(dev);
2664 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2668 /* Skip link setup if loopback mode is enabled. */
2669 if (dev->data->dev_conf.lpbk_mode != 0) {
2670 err = ixgbe_check_supported_loopback_mode(dev);
2672 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2675 goto skip_link_setup;
2679 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2680 err = hw->mac.ops.setup_sfp(hw);
2685 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2686 /* Turn on the copper */
2687 ixgbe_set_phy_power(hw, true);
2689 /* Turn on the laser */
2690 ixgbe_enable_tx_laser(hw);
2693 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2696 dev->data->dev_link.link_status = link_up;
2698 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2702 switch (hw->mac.type) {
2703 case ixgbe_mac_X550:
2704 case ixgbe_mac_X550EM_x:
2705 case ixgbe_mac_X550EM_a:
2706 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2707 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2709 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2710 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2711 allowed_speeds = ETH_LINK_SPEED_10M |
2712 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2715 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2719 link_speeds = &dev->data->dev_conf.link_speeds;
2721 /* Ignore autoneg flag bit and check the validity ofÂ
2724 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2725 PMD_INIT_LOG(ERR, "Invalid link setting");
2730 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2731 switch (hw->mac.type) {
2732 case ixgbe_mac_82598EB:
2733 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2735 case ixgbe_mac_82599EB:
2736 case ixgbe_mac_X540:
2737 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2739 case ixgbe_mac_X550:
2740 case ixgbe_mac_X550EM_x:
2741 case ixgbe_mac_X550EM_a:
2742 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2745 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2748 if (*link_speeds & ETH_LINK_SPEED_10G)
2749 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2750 if (*link_speeds & ETH_LINK_SPEED_5G)
2751 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2752 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2753 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2754 if (*link_speeds & ETH_LINK_SPEED_1G)
2755 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2756 if (*link_speeds & ETH_LINK_SPEED_100M)
2757 speed |= IXGBE_LINK_SPEED_100_FULL;
2758 if (*link_speeds & ETH_LINK_SPEED_10M)
2759 speed |= IXGBE_LINK_SPEED_10_FULL;
2762 err = ixgbe_setup_link(hw, speed, link_up);
2768 if (rte_intr_allow_others(intr_handle)) {
2769 /* check if lsc interrupt is enabled */
2770 if (dev->data->dev_conf.intr_conf.lsc != 0)
2771 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2773 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2774 ixgbe_dev_macsec_interrupt_setup(dev);
2776 rte_intr_callback_unregister(intr_handle,
2777 ixgbe_dev_interrupt_handler, dev);
2778 if (dev->data->dev_conf.intr_conf.lsc != 0)
2779 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2780 " no intr multiplex");
2783 /* check if rxq interrupt is enabled */
2784 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2785 rte_intr_dp_is_en(intr_handle))
2786 ixgbe_dev_rxq_interrupt_setup(dev);
2788 /* enable uio/vfio intr/eventfd mapping */
2789 rte_intr_enable(intr_handle);
2791 /* resume enabled intr since hw reset */
2792 ixgbe_enable_intr(dev);
2793 ixgbe_l2_tunnel_conf(dev);
2794 ixgbe_filter_restore(dev);
2796 if (tm_conf->root && !tm_conf->committed)
2797 PMD_DRV_LOG(WARNING,
2798 "please call hierarchy_commit() "
2799 "before starting the port");
2801 /* wait for the controller to acquire link */
2802 err = ixgbe_wait_for_link_up(hw);
2807 * Update link status right before return, because it may
2808 * start link configuration process in a separate thread.
2810 ixgbe_dev_link_update(dev, 0);
2812 /* setup the macsec setting register */
2813 if (macsec_setting->offload_en)
2814 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2819 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2820 ixgbe_dev_clear_queues(dev);
2825 * Stop device: disable rx and tx functions to allow for reconfiguring.
2828 ixgbe_dev_stop(struct rte_eth_dev *dev)
2830 struct rte_eth_link link;
2831 struct ixgbe_adapter *adapter = dev->data->dev_private;
2832 struct ixgbe_hw *hw =
2833 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2834 struct ixgbe_vf_info *vfinfo =
2835 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2836 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2837 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2839 struct ixgbe_tm_conf *tm_conf =
2840 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2842 if (hw->adapter_stopped)
2845 PMD_INIT_FUNC_TRACE();
2847 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2849 /* disable interrupts */
2850 ixgbe_disable_intr(hw);
2853 ixgbe_pf_reset_hw(hw);
2854 hw->adapter_stopped = 0;
2857 ixgbe_stop_adapter(hw);
2859 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2860 vfinfo[vf].clear_to_send = false;
2862 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2863 /* Turn off the copper */
2864 ixgbe_set_phy_power(hw, false);
2866 /* Turn off the laser */
2867 ixgbe_disable_tx_laser(hw);
2870 ixgbe_dev_clear_queues(dev);
2872 /* Clear stored conf */
2873 dev->data->scattered_rx = 0;
2876 /* Clear recorded link status */
2877 memset(&link, 0, sizeof(link));
2878 rte_eth_linkstatus_set(dev, &link);
2880 if (!rte_intr_allow_others(intr_handle))
2881 /* resume to the default handler */
2882 rte_intr_callback_register(intr_handle,
2883 ixgbe_dev_interrupt_handler,
2886 /* Clean datapath event and queue/vec mapping */
2887 rte_intr_efd_disable(intr_handle);
2888 if (intr_handle->intr_vec != NULL) {
2889 rte_free(intr_handle->intr_vec);
2890 intr_handle->intr_vec = NULL;
2893 /* reset hierarchy commit */
2894 tm_conf->committed = false;
2896 adapter->rss_reta_updated = 0;
2898 hw->adapter_stopped = true;
2902 * Set device link up: enable tx.
2905 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2907 struct ixgbe_hw *hw =
2908 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2909 if (hw->mac.type == ixgbe_mac_82599EB) {
2910 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2911 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2912 /* Not suported in bypass mode */
2913 PMD_INIT_LOG(ERR, "Set link up is not supported "
2914 "by device id 0x%x", hw->device_id);
2920 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2921 /* Turn on the copper */
2922 ixgbe_set_phy_power(hw, true);
2924 /* Turn on the laser */
2925 ixgbe_enable_tx_laser(hw);
2926 ixgbe_dev_link_update(dev, 0);
2933 * Set device link down: disable tx.
2936 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2938 struct ixgbe_hw *hw =
2939 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2940 if (hw->mac.type == ixgbe_mac_82599EB) {
2941 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2942 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2943 /* Not suported in bypass mode */
2944 PMD_INIT_LOG(ERR, "Set link down is not supported "
2945 "by device id 0x%x", hw->device_id);
2951 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2952 /* Turn off the copper */
2953 ixgbe_set_phy_power(hw, false);
2955 /* Turn off the laser */
2956 ixgbe_disable_tx_laser(hw);
2957 ixgbe_dev_link_update(dev, 0);
2964 * Reset and stop device.
2967 ixgbe_dev_close(struct rte_eth_dev *dev)
2969 struct ixgbe_hw *hw =
2970 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2972 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2976 PMD_INIT_FUNC_TRACE();
2978 ixgbe_pf_reset_hw(hw);
2980 ixgbe_dev_stop(dev);
2982 ixgbe_dev_free_queues(dev);
2984 ixgbe_disable_pcie_master(hw);
2986 /* reprogram the RAR[0] in case user changed it. */
2987 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2989 dev->dev_ops = NULL;
2990 dev->rx_pkt_burst = NULL;
2991 dev->tx_pkt_burst = NULL;
2993 /* Unlock any pending hardware semaphore */
2994 ixgbe_swfw_lock_reset(hw);
2996 /* disable uio intr before callback unregister */
2997 rte_intr_disable(intr_handle);
3000 ret = rte_intr_callback_unregister(intr_handle,
3001 ixgbe_dev_interrupt_handler, dev);
3002 if (ret >= 0 || ret == -ENOENT) {
3004 } else if (ret != -EAGAIN) {
3006 "intr callback unregister failed: %d",
3010 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3012 /* cancel the delay handler before remove dev */
3013 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3015 /* uninitialize PF if max_vfs not zero */
3016 ixgbe_pf_host_uninit(dev);
3018 /* remove all the fdir filters & hash */
3019 ixgbe_fdir_filter_uninit(dev);
3021 /* remove all the L2 tunnel filters & hash */
3022 ixgbe_l2_tn_filter_uninit(dev);
3024 /* Remove all ntuple filters of the device */
3025 ixgbe_ntuple_filter_uninit(dev);
3027 /* clear all the filters list */
3028 ixgbe_filterlist_flush();
3030 /* Remove all Traffic Manager configuration */
3031 ixgbe_tm_conf_uninit(dev);
3033 #ifdef RTE_LIBRTE_SECURITY
3034 rte_free(dev->security_ctx);
3043 ixgbe_dev_reset(struct rte_eth_dev *dev)
3047 /* When a DPDK PMD PF begin to reset PF port, it should notify all
3048 * its VF to make them align with it. The detailed notification
3049 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3050 * To avoid unexpected behavior in VF, currently reset of PF with
3051 * SR-IOV activation is not supported. It might be supported later.
3053 if (dev->data->sriov.active)
3056 ret = eth_ixgbe_dev_uninit(dev);
3060 ret = eth_ixgbe_dev_init(dev, NULL);
3066 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3067 struct ixgbe_hw_stats *hw_stats,
3068 struct ixgbe_macsec_stats *macsec_stats,
3069 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3070 uint64_t *total_qprc, uint64_t *total_qprdc)
3072 uint32_t bprc, lxon, lxoff, total;
3073 uint32_t delta_gprc = 0;
3075 /* Workaround for RX byte count not including CRC bytes when CRC
3076 * strip is enabled. CRC bytes are removed from counters when crc_strip
3079 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3080 IXGBE_HLREG0_RXCRCSTRP);
3082 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3083 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3084 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3085 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3087 for (i = 0; i < 8; i++) {
3088 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3090 /* global total per queue */
3091 hw_stats->mpc[i] += mp;
3092 /* Running comprehensive total for stats display */
3093 *total_missed_rx += hw_stats->mpc[i];
3094 if (hw->mac.type == ixgbe_mac_82598EB) {
3095 hw_stats->rnbc[i] +=
3096 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3097 hw_stats->pxonrxc[i] +=
3098 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3099 hw_stats->pxoffrxc[i] +=
3100 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3102 hw_stats->pxonrxc[i] +=
3103 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3104 hw_stats->pxoffrxc[i] +=
3105 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3106 hw_stats->pxon2offc[i] +=
3107 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3109 hw_stats->pxontxc[i] +=
3110 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3111 hw_stats->pxofftxc[i] +=
3112 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3114 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3115 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3116 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3117 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3119 delta_gprc += delta_qprc;
3121 hw_stats->qprc[i] += delta_qprc;
3122 hw_stats->qptc[i] += delta_qptc;
3124 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3125 hw_stats->qbrc[i] +=
3126 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3128 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3130 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3131 hw_stats->qbtc[i] +=
3132 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3134 hw_stats->qprdc[i] += delta_qprdc;
3135 *total_qprdc += hw_stats->qprdc[i];
3137 *total_qprc += hw_stats->qprc[i];
3138 *total_qbrc += hw_stats->qbrc[i];
3140 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3141 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3142 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3145 * An errata states that gprc actually counts good + missed packets:
3146 * Workaround to set gprc to summated queue packet receives
3148 hw_stats->gprc = *total_qprc;
3150 if (hw->mac.type != ixgbe_mac_82598EB) {
3151 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3152 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3153 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3154 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3155 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3156 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3157 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3158 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3160 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3161 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3162 /* 82598 only has a counter in the high register */
3163 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3164 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3165 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3167 uint64_t old_tpr = hw_stats->tpr;
3169 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3170 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3173 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3175 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3176 hw_stats->gptc += delta_gptc;
3177 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3178 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3181 * Workaround: mprc hardware is incorrectly counting
3182 * broadcasts, so for now we subtract those.
3184 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3185 hw_stats->bprc += bprc;
3186 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3187 if (hw->mac.type == ixgbe_mac_82598EB)
3188 hw_stats->mprc -= bprc;
3190 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3191 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3192 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3193 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3194 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3195 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3197 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3198 hw_stats->lxontxc += lxon;
3199 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3200 hw_stats->lxofftxc += lxoff;
3201 total = lxon + lxoff;
3203 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3204 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3205 hw_stats->gptc -= total;
3206 hw_stats->mptc -= total;
3207 hw_stats->ptc64 -= total;
3208 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3210 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3211 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3212 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3213 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3214 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3215 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3216 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3217 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3218 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3219 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3220 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3221 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3222 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3223 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3224 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3225 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3226 /* Only read FCOE on 82599 */
3227 if (hw->mac.type != ixgbe_mac_82598EB) {
3228 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3229 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3230 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3231 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3232 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3235 /* Flow Director Stats registers */
3236 if (hw->mac.type != ixgbe_mac_82598EB) {
3237 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3238 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3239 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3240 IXGBE_FDIRUSTAT) & 0xFFFF;
3241 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3242 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3243 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3244 IXGBE_FDIRFSTAT) & 0xFFFF;
3245 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3246 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3248 /* MACsec Stats registers */
3249 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3250 macsec_stats->out_pkts_encrypted +=
3251 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3252 macsec_stats->out_pkts_protected +=
3253 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3254 macsec_stats->out_octets_encrypted +=
3255 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3256 macsec_stats->out_octets_protected +=
3257 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3258 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3259 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3260 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3261 macsec_stats->in_pkts_unknownsci +=
3262 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3263 macsec_stats->in_octets_decrypted +=
3264 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3265 macsec_stats->in_octets_validated +=
3266 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3267 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3268 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3269 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3270 for (i = 0; i < 2; i++) {
3271 macsec_stats->in_pkts_ok +=
3272 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3273 macsec_stats->in_pkts_invalid +=
3274 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3275 macsec_stats->in_pkts_notvalid +=
3276 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3278 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3279 macsec_stats->in_pkts_notusingsa +=
3280 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3284 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3287 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3289 struct ixgbe_hw *hw =
3290 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3291 struct ixgbe_hw_stats *hw_stats =
3292 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3293 struct ixgbe_macsec_stats *macsec_stats =
3294 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3295 dev->data->dev_private);
3296 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3299 total_missed_rx = 0;
3304 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3305 &total_qbrc, &total_qprc, &total_qprdc);
3310 /* Fill out the rte_eth_stats statistics structure */
3311 stats->ipackets = total_qprc;
3312 stats->ibytes = total_qbrc;
3313 stats->opackets = hw_stats->gptc;
3314 stats->obytes = hw_stats->gotc;
3316 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3317 stats->q_ipackets[i] = hw_stats->qprc[i];
3318 stats->q_opackets[i] = hw_stats->qptc[i];
3319 stats->q_ibytes[i] = hw_stats->qbrc[i];
3320 stats->q_obytes[i] = hw_stats->qbtc[i];
3321 stats->q_errors[i] = hw_stats->qprdc[i];
3325 stats->imissed = total_missed_rx;
3326 stats->ierrors = hw_stats->crcerrs +
3343 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3345 struct ixgbe_hw_stats *stats =
3346 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3348 /* HW registers are cleared on read */
3349 ixgbe_dev_stats_get(dev, NULL);
3351 /* Reset software totals */
3352 memset(stats, 0, sizeof(*stats));
3357 /* This function calculates the number of xstats based on the current config */
3359 ixgbe_xstats_calc_num(void) {
3360 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3361 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3362 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3365 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3366 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3368 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3369 unsigned stat, i, count;
3371 if (xstats_names != NULL) {
3374 /* Note: limit >= cnt_stats checked upstream
3375 * in rte_eth_xstats_names()
3378 /* Extended stats from ixgbe_hw_stats */
3379 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3380 strlcpy(xstats_names[count].name,
3381 rte_ixgbe_stats_strings[i].name,
3382 sizeof(xstats_names[count].name));
3387 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3388 strlcpy(xstats_names[count].name,
3389 rte_ixgbe_macsec_strings[i].name,
3390 sizeof(xstats_names[count].name));
3394 /* RX Priority Stats */
3395 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3396 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3397 snprintf(xstats_names[count].name,
3398 sizeof(xstats_names[count].name),
3399 "rx_priority%u_%s", i,
3400 rte_ixgbe_rxq_strings[stat].name);
3405 /* TX Priority Stats */
3406 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3407 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3408 snprintf(xstats_names[count].name,
3409 sizeof(xstats_names[count].name),
3410 "tx_priority%u_%s", i,
3411 rte_ixgbe_txq_strings[stat].name);
3419 static int ixgbe_dev_xstats_get_names_by_id(
3420 struct rte_eth_dev *dev,
3421 struct rte_eth_xstat_name *xstats_names,
3422 const uint64_t *ids,
3426 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3427 unsigned int stat, i, count;
3429 if (xstats_names != NULL) {
3432 /* Note: limit >= cnt_stats checked upstream
3433 * in rte_eth_xstats_names()
3436 /* Extended stats from ixgbe_hw_stats */
3437 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3438 strlcpy(xstats_names[count].name,
3439 rte_ixgbe_stats_strings[i].name,
3440 sizeof(xstats_names[count].name));
3445 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3446 strlcpy(xstats_names[count].name,
3447 rte_ixgbe_macsec_strings[i].name,
3448 sizeof(xstats_names[count].name));
3452 /* RX Priority Stats */
3453 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3454 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3455 snprintf(xstats_names[count].name,
3456 sizeof(xstats_names[count].name),
3457 "rx_priority%u_%s", i,
3458 rte_ixgbe_rxq_strings[stat].name);
3463 /* TX Priority Stats */
3464 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3465 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3466 snprintf(xstats_names[count].name,
3467 sizeof(xstats_names[count].name),
3468 "tx_priority%u_%s", i,
3469 rte_ixgbe_txq_strings[stat].name);
3478 uint16_t size = ixgbe_xstats_calc_num();
3479 struct rte_eth_xstat_name xstats_names_copy[size];
3481 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3484 for (i = 0; i < limit; i++) {
3485 if (ids[i] >= size) {
3486 PMD_INIT_LOG(ERR, "id value isn't valid");
3489 strcpy(xstats_names[i].name,
3490 xstats_names_copy[ids[i]].name);
3495 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3496 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3500 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3503 if (xstats_names != NULL)
3504 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3505 strlcpy(xstats_names[i].name,
3506 rte_ixgbevf_stats_strings[i].name,
3507 sizeof(xstats_names[i].name));
3508 return IXGBEVF_NB_XSTATS;
3512 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3515 struct ixgbe_hw *hw =
3516 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3517 struct ixgbe_hw_stats *hw_stats =
3518 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3519 struct ixgbe_macsec_stats *macsec_stats =
3520 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3521 dev->data->dev_private);
3522 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3523 unsigned i, stat, count = 0;
3525 count = ixgbe_xstats_calc_num();
3530 total_missed_rx = 0;
3535 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3536 &total_qbrc, &total_qprc, &total_qprdc);
3538 /* If this is a reset xstats is NULL, and we have cleared the
3539 * registers by reading them.
3544 /* Extended stats from ixgbe_hw_stats */
3546 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3547 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3548 rte_ixgbe_stats_strings[i].offset);
3549 xstats[count].id = count;
3554 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3555 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3556 rte_ixgbe_macsec_strings[i].offset);
3557 xstats[count].id = count;
3561 /* RX Priority Stats */
3562 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3563 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3564 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3565 rte_ixgbe_rxq_strings[stat].offset +
3566 (sizeof(uint64_t) * i));
3567 xstats[count].id = count;
3572 /* TX Priority Stats */
3573 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3574 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3575 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3576 rte_ixgbe_txq_strings[stat].offset +
3577 (sizeof(uint64_t) * i));
3578 xstats[count].id = count;
3586 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3587 uint64_t *values, unsigned int n)
3590 struct ixgbe_hw *hw =
3591 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3592 struct ixgbe_hw_stats *hw_stats =
3593 IXGBE_DEV_PRIVATE_TO_STATS(
3594 dev->data->dev_private);
3595 struct ixgbe_macsec_stats *macsec_stats =
3596 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3597 dev->data->dev_private);
3598 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3599 unsigned int i, stat, count = 0;
3601 count = ixgbe_xstats_calc_num();
3603 if (!ids && n < count)
3606 total_missed_rx = 0;
3611 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3612 &total_missed_rx, &total_qbrc, &total_qprc,
3615 /* If this is a reset xstats is NULL, and we have cleared the
3616 * registers by reading them.
3618 if (!ids && !values)
3621 /* Extended stats from ixgbe_hw_stats */
3623 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3624 values[count] = *(uint64_t *)(((char *)hw_stats) +
3625 rte_ixgbe_stats_strings[i].offset);
3630 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3631 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3632 rte_ixgbe_macsec_strings[i].offset);
3636 /* RX Priority Stats */
3637 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3638 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3640 *(uint64_t *)(((char *)hw_stats) +
3641 rte_ixgbe_rxq_strings[stat].offset +
3642 (sizeof(uint64_t) * i));
3647 /* TX Priority Stats */
3648 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3649 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3651 *(uint64_t *)(((char *)hw_stats) +
3652 rte_ixgbe_txq_strings[stat].offset +
3653 (sizeof(uint64_t) * i));
3661 uint16_t size = ixgbe_xstats_calc_num();
3662 uint64_t values_copy[size];
3664 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3666 for (i = 0; i < n; i++) {
3667 if (ids[i] >= size) {
3668 PMD_INIT_LOG(ERR, "id value isn't valid");
3671 values[i] = values_copy[ids[i]];
3677 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3679 struct ixgbe_hw_stats *stats =
3680 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3681 struct ixgbe_macsec_stats *macsec_stats =
3682 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3683 dev->data->dev_private);
3685 unsigned count = ixgbe_xstats_calc_num();
3687 /* HW registers are cleared on read */
3688 ixgbe_dev_xstats_get(dev, NULL, count);
3690 /* Reset software totals */
3691 memset(stats, 0, sizeof(*stats));
3692 memset(macsec_stats, 0, sizeof(*macsec_stats));
3698 ixgbevf_update_stats(struct rte_eth_dev *dev)
3700 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3701 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3702 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3704 /* Good Rx packet, include VF loopback */
3705 UPDATE_VF_STAT(IXGBE_VFGPRC,
3706 hw_stats->last_vfgprc, hw_stats->vfgprc);
3708 /* Good Rx octets, include VF loopback */
3709 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3710 hw_stats->last_vfgorc, hw_stats->vfgorc);
3712 /* Good Tx packet, include VF loopback */
3713 UPDATE_VF_STAT(IXGBE_VFGPTC,
3714 hw_stats->last_vfgptc, hw_stats->vfgptc);
3716 /* Good Tx octets, include VF loopback */
3717 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3718 hw_stats->last_vfgotc, hw_stats->vfgotc);
3720 /* Rx Multicst Packet */
3721 UPDATE_VF_STAT(IXGBE_VFMPRC,
3722 hw_stats->last_vfmprc, hw_stats->vfmprc);
3726 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3729 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3730 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3733 if (n < IXGBEVF_NB_XSTATS)
3734 return IXGBEVF_NB_XSTATS;
3736 ixgbevf_update_stats(dev);
3741 /* Extended stats */
3742 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3744 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3745 rte_ixgbevf_stats_strings[i].offset);
3748 return IXGBEVF_NB_XSTATS;
3752 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3754 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3755 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3757 ixgbevf_update_stats(dev);
3762 stats->ipackets = hw_stats->vfgprc;
3763 stats->ibytes = hw_stats->vfgorc;
3764 stats->opackets = hw_stats->vfgptc;
3765 stats->obytes = hw_stats->vfgotc;
3770 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3772 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3773 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3775 /* Sync HW register to the last stats */
3776 ixgbevf_dev_stats_get(dev, NULL);
3778 /* reset HW current stats*/
3779 hw_stats->vfgprc = 0;
3780 hw_stats->vfgorc = 0;
3781 hw_stats->vfgptc = 0;
3782 hw_stats->vfgotc = 0;
3788 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3790 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791 u16 eeprom_verh, eeprom_verl;
3795 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3796 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3798 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3799 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3801 ret += 1; /* add the size of '\0' */
3802 if (fw_size < (u32)ret)
3809 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3811 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3812 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3813 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3815 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3816 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3817 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3819 * When DCB/VT is off, maximum number of queues changes,
3820 * except for 82598EB, which remains constant.
3822 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3823 hw->mac.type != ixgbe_mac_82598EB)
3824 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3826 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3827 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3828 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3829 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3830 dev_info->max_vfs = pci_dev->max_vfs;
3831 if (hw->mac.type == ixgbe_mac_82598EB)
3832 dev_info->max_vmdq_pools = ETH_16_POOLS;
3834 dev_info->max_vmdq_pools = ETH_64_POOLS;
3835 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3836 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3837 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3838 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3839 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3840 dev_info->rx_queue_offload_capa);
3841 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3842 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3844 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3846 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3847 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3848 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3850 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3855 dev_info->default_txconf = (struct rte_eth_txconf) {
3857 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3858 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3859 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3861 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3862 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3866 dev_info->rx_desc_lim = rx_desc_lim;
3867 dev_info->tx_desc_lim = tx_desc_lim;
3869 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3870 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3871 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3873 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3874 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3875 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3876 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3877 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3879 if (hw->mac.type == ixgbe_mac_X540 ||
3880 hw->mac.type == ixgbe_mac_X540_vf ||
3881 hw->mac.type == ixgbe_mac_X550 ||
3882 hw->mac.type == ixgbe_mac_X550_vf) {
3883 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3885 if (hw->mac.type == ixgbe_mac_X550) {
3886 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3887 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3890 /* Driver-preferred Rx/Tx parameters */
3891 dev_info->default_rxportconf.burst_size = 32;
3892 dev_info->default_txportconf.burst_size = 32;
3893 dev_info->default_rxportconf.nb_queues = 1;
3894 dev_info->default_txportconf.nb_queues = 1;
3895 dev_info->default_rxportconf.ring_size = 256;
3896 dev_info->default_txportconf.ring_size = 256;
3901 static const uint32_t *
3902 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3904 static const uint32_t ptypes[] = {
3905 /* For non-vec functions,
3906 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3907 * for vec functions,
3908 * refers to _recv_raw_pkts_vec().
3912 RTE_PTYPE_L3_IPV4_EXT,
3914 RTE_PTYPE_L3_IPV6_EXT,
3918 RTE_PTYPE_TUNNEL_IP,
3919 RTE_PTYPE_INNER_L3_IPV6,
3920 RTE_PTYPE_INNER_L3_IPV6_EXT,
3921 RTE_PTYPE_INNER_L4_TCP,
3922 RTE_PTYPE_INNER_L4_UDP,
3926 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3927 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3928 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3929 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3932 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3933 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3934 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3941 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3942 struct rte_eth_dev_info *dev_info)
3944 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3945 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3947 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3948 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3949 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3950 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3951 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3952 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3953 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3954 dev_info->max_vfs = pci_dev->max_vfs;
3955 if (hw->mac.type == ixgbe_mac_82598EB)
3956 dev_info->max_vmdq_pools = ETH_16_POOLS;
3958 dev_info->max_vmdq_pools = ETH_64_POOLS;
3959 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3960 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3961 dev_info->rx_queue_offload_capa);
3962 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3963 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3964 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3965 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3966 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3968 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3970 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3971 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3972 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3974 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3979 dev_info->default_txconf = (struct rte_eth_txconf) {
3981 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3982 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3983 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3985 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3986 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3990 dev_info->rx_desc_lim = rx_desc_lim;
3991 dev_info->tx_desc_lim = tx_desc_lim;
3997 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3998 bool *link_up, int wait_to_complete)
4000 struct ixgbe_adapter *adapter = container_of(hw,
4001 struct ixgbe_adapter, hw);
4002 struct ixgbe_mbx_info *mbx = &hw->mbx;
4003 struct ixgbe_mac_info *mac = &hw->mac;
4004 uint32_t links_reg, in_msg;
4007 /* If we were hit with a reset drop the link */
4008 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4009 mac->get_link_status = true;
4011 if (!mac->get_link_status)
4014 /* if link status is down no point in checking to see if pf is up */
4015 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4016 if (!(links_reg & IXGBE_LINKS_UP))
4019 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4020 * before the link status is correct
4022 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4025 for (i = 0; i < 5; i++) {
4027 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4029 if (!(links_reg & IXGBE_LINKS_UP))
4034 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4035 case IXGBE_LINKS_SPEED_10G_82599:
4036 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4037 if (hw->mac.type >= ixgbe_mac_X550) {
4038 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4039 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4042 case IXGBE_LINKS_SPEED_1G_82599:
4043 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4045 case IXGBE_LINKS_SPEED_100_82599:
4046 *speed = IXGBE_LINK_SPEED_100_FULL;
4047 if (hw->mac.type == ixgbe_mac_X550) {
4048 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4049 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4052 case IXGBE_LINKS_SPEED_10_X550EM_A:
4053 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4054 /* Since Reserved in older MAC's */
4055 if (hw->mac.type >= ixgbe_mac_X550)
4056 *speed = IXGBE_LINK_SPEED_10_FULL;
4059 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4062 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4063 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4064 mac->get_link_status = true;
4066 mac->get_link_status = false;
4071 /* if the read failed it could just be a mailbox collision, best wait
4072 * until we are called again and don't report an error
4074 if (mbx->ops.read(hw, &in_msg, 1, 0))
4077 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4078 /* msg is not CTS and is NACK we must have lost CTS status */
4079 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4080 mac->get_link_status = false;
4084 /* the pf is talking, if we timed out in the past we reinit */
4085 if (!mbx->timeout) {
4090 /* if we passed all the tests above then the link is up and we no
4091 * longer need to check for link
4093 mac->get_link_status = false;
4096 *link_up = !mac->get_link_status;
4101 ixgbe_dev_setup_link_alarm_handler(void *param)
4103 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4104 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4105 struct ixgbe_interrupt *intr =
4106 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4108 bool autoneg = false;
4110 speed = hw->phy.autoneg_advertised;
4112 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4114 ixgbe_setup_link(hw, speed, true);
4116 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4120 * In freebsd environment, nic_uio drivers do not support interrupts,
4121 * rte_intr_callback_register() will fail to register interrupts.
4122 * We can not make link status to change from down to up by interrupt
4123 * callback. So we need to wait for the controller to acquire link
4125 * It returns 0 on link up.
4128 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4130 #ifdef RTE_EXEC_ENV_FREEBSD
4131 const int nb_iter = 25;
4133 const int nb_iter = 0;
4136 bool link_up = false;
4139 for (i = 0; i < nb_iter; i++) {
4140 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4150 /* return 0 means link status changed, -1 means not changed */
4152 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4153 int wait_to_complete, int vf)
4155 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4156 struct rte_eth_link link;
4157 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4158 struct ixgbe_interrupt *intr =
4159 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4165 memset(&link, 0, sizeof(link));
4166 link.link_status = ETH_LINK_DOWN;
4167 link.link_speed = ETH_SPEED_NUM_NONE;
4168 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4169 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4170 ETH_LINK_SPEED_FIXED);
4172 hw->mac.get_link_status = true;
4174 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4175 return rte_eth_linkstatus_set(dev, &link);
4177 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4178 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4182 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4184 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4187 link.link_speed = ETH_SPEED_NUM_100M;
4188 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4189 return rte_eth_linkstatus_set(dev, &link);
4192 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4193 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4194 if ((esdp_reg & IXGBE_ESDP_SDP3))
4199 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4200 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4201 rte_eal_alarm_set(10,
4202 ixgbe_dev_setup_link_alarm_handler, dev);
4204 return rte_eth_linkstatus_set(dev, &link);
4207 link.link_status = ETH_LINK_UP;
4208 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4210 switch (link_speed) {
4212 case IXGBE_LINK_SPEED_UNKNOWN:
4213 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4214 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4215 link.link_speed = ETH_SPEED_NUM_10M;
4217 link.link_speed = ETH_SPEED_NUM_100M;
4220 case IXGBE_LINK_SPEED_100_FULL:
4221 link.link_speed = ETH_SPEED_NUM_100M;
4224 case IXGBE_LINK_SPEED_1GB_FULL:
4225 link.link_speed = ETH_SPEED_NUM_1G;
4228 case IXGBE_LINK_SPEED_2_5GB_FULL:
4229 link.link_speed = ETH_SPEED_NUM_2_5G;
4232 case IXGBE_LINK_SPEED_5GB_FULL:
4233 link.link_speed = ETH_SPEED_NUM_5G;
4236 case IXGBE_LINK_SPEED_10GB_FULL:
4237 link.link_speed = ETH_SPEED_NUM_10G;
4241 return rte_eth_linkstatus_set(dev, &link);
4245 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4247 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4251 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4253 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4257 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4259 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4262 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4263 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4264 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4270 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4272 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4275 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4276 fctrl &= (~IXGBE_FCTRL_UPE);
4277 if (dev->data->all_multicast == 1)
4278 fctrl |= IXGBE_FCTRL_MPE;
4280 fctrl &= (~IXGBE_FCTRL_MPE);
4281 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4287 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4289 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4292 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4293 fctrl |= IXGBE_FCTRL_MPE;
4294 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4300 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4302 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4305 if (dev->data->promiscuous == 1)
4306 return 0; /* must remain in all_multicast mode */
4308 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4309 fctrl &= (~IXGBE_FCTRL_MPE);
4310 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4316 * It clears the interrupt causes and enables the interrupt.
4317 * It will be called once only during nic initialized.
4320 * Pointer to struct rte_eth_dev.
4322 * Enable or Disable.
4325 * - On success, zero.
4326 * - On failure, a negative value.
4329 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4331 struct ixgbe_interrupt *intr =
4332 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4334 ixgbe_dev_link_status_print(dev);
4336 intr->mask |= IXGBE_EICR_LSC;
4338 intr->mask &= ~IXGBE_EICR_LSC;
4344 * It clears the interrupt causes and enables the interrupt.
4345 * It will be called once only during nic initialized.
4348 * Pointer to struct rte_eth_dev.
4351 * - On success, zero.
4352 * - On failure, a negative value.
4355 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4357 struct ixgbe_interrupt *intr =
4358 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4360 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4366 * It clears the interrupt causes and enables the interrupt.
4367 * It will be called once only during nic initialized.
4370 * Pointer to struct rte_eth_dev.
4373 * - On success, zero.
4374 * - On failure, a negative value.
4377 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4379 struct ixgbe_interrupt *intr =
4380 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4382 intr->mask |= IXGBE_EICR_LINKSEC;
4388 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4391 * Pointer to struct rte_eth_dev.
4394 * - On success, zero.
4395 * - On failure, a negative value.
4398 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4401 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4402 struct ixgbe_interrupt *intr =
4403 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4405 /* clear all cause mask */
4406 ixgbe_disable_intr(hw);
4408 /* read-on-clear nic registers here */
4409 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4410 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4414 /* set flag for async link update */
4415 if (eicr & IXGBE_EICR_LSC)
4416 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4418 if (eicr & IXGBE_EICR_MAILBOX)
4419 intr->flags |= IXGBE_FLAG_MAILBOX;
4421 if (eicr & IXGBE_EICR_LINKSEC)
4422 intr->flags |= IXGBE_FLAG_MACSEC;
4424 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4425 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4426 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4427 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4433 * It gets and then prints the link status.
4436 * Pointer to struct rte_eth_dev.
4439 * - On success, zero.
4440 * - On failure, a negative value.
4443 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4445 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4446 struct rte_eth_link link;
4448 rte_eth_linkstatus_get(dev, &link);
4450 if (link.link_status) {
4451 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4452 (int)(dev->data->port_id),
4453 (unsigned)link.link_speed,
4454 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4455 "full-duplex" : "half-duplex");
4457 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4458 (int)(dev->data->port_id));
4460 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4461 pci_dev->addr.domain,
4463 pci_dev->addr.devid,
4464 pci_dev->addr.function);
4468 * It executes link_update after knowing an interrupt occurred.
4471 * Pointer to struct rte_eth_dev.
4474 * - On success, zero.
4475 * - On failure, a negative value.
4478 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4480 struct ixgbe_interrupt *intr =
4481 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4483 struct ixgbe_hw *hw =
4484 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4486 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4488 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4489 ixgbe_pf_mbx_process(dev);
4490 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4493 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4494 ixgbe_handle_lasi(hw);
4495 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4498 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4499 struct rte_eth_link link;
4501 /* get the link status before link update, for predicting later */
4502 rte_eth_linkstatus_get(dev, &link);
4504 ixgbe_dev_link_update(dev, 0);
4507 if (!link.link_status)
4508 /* handle it 1 sec later, wait it being stable */
4509 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4510 /* likely to down */
4512 /* handle it 4 sec later, wait it being stable */
4513 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4515 ixgbe_dev_link_status_print(dev);
4516 if (rte_eal_alarm_set(timeout * 1000,
4517 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4518 PMD_DRV_LOG(ERR, "Error setting alarm");
4520 /* remember original mask */
4521 intr->mask_original = intr->mask;
4522 /* only disable lsc interrupt */
4523 intr->mask &= ~IXGBE_EIMS_LSC;
4527 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4528 ixgbe_enable_intr(dev);
4534 * Interrupt handler which shall be registered for alarm callback for delayed
4535 * handling specific interrupt to wait for the stable nic state. As the
4536 * NIC interrupt state is not stable for ixgbe after link is just down,
4537 * it needs to wait 4 seconds to get the stable status.
4540 * Pointer to interrupt handle.
4542 * The address of parameter (struct rte_eth_dev *) regsitered before.
4548 ixgbe_dev_interrupt_delayed_handler(void *param)
4550 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4551 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4552 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4553 struct ixgbe_interrupt *intr =
4554 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4555 struct ixgbe_hw *hw =
4556 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4559 ixgbe_disable_intr(hw);
4561 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4562 if (eicr & IXGBE_EICR_MAILBOX)
4563 ixgbe_pf_mbx_process(dev);
4565 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4566 ixgbe_handle_lasi(hw);
4567 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4570 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4571 ixgbe_dev_link_update(dev, 0);
4572 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4573 ixgbe_dev_link_status_print(dev);
4574 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4578 if (intr->flags & IXGBE_FLAG_MACSEC) {
4579 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4581 intr->flags &= ~IXGBE_FLAG_MACSEC;
4584 /* restore original mask */
4585 intr->mask = intr->mask_original;
4586 intr->mask_original = 0;
4588 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4589 ixgbe_enable_intr(dev);
4590 rte_intr_ack(intr_handle);
4594 * Interrupt handler triggered by NIC for handling
4595 * specific interrupt.
4598 * Pointer to interrupt handle.
4600 * The address of parameter (struct rte_eth_dev *) regsitered before.
4606 ixgbe_dev_interrupt_handler(void *param)
4608 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4610 ixgbe_dev_interrupt_get_status(dev);
4611 ixgbe_dev_interrupt_action(dev);
4615 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4617 struct ixgbe_hw *hw;
4619 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4620 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4624 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4626 struct ixgbe_hw *hw;
4628 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4633 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4635 struct ixgbe_hw *hw;
4641 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4643 fc_conf->pause_time = hw->fc.pause_time;
4644 fc_conf->high_water = hw->fc.high_water[0];
4645 fc_conf->low_water = hw->fc.low_water[0];
4646 fc_conf->send_xon = hw->fc.send_xon;
4647 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4650 * Return rx_pause status according to actual setting of
4653 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4654 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4660 * Return tx_pause status according to actual setting of
4663 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4664 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4669 if (rx_pause && tx_pause)
4670 fc_conf->mode = RTE_FC_FULL;
4672 fc_conf->mode = RTE_FC_RX_PAUSE;
4674 fc_conf->mode = RTE_FC_TX_PAUSE;
4676 fc_conf->mode = RTE_FC_NONE;
4682 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4684 struct ixgbe_hw *hw;
4686 uint32_t rx_buf_size;
4687 uint32_t max_high_water;
4689 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4696 PMD_INIT_FUNC_TRACE();
4698 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4699 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4700 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4703 * At least reserve one Ethernet frame for watermark
4704 * high_water/low_water in kilo bytes for ixgbe
4706 max_high_water = (rx_buf_size -
4707 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4708 if ((fc_conf->high_water > max_high_water) ||
4709 (fc_conf->high_water < fc_conf->low_water)) {
4710 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4711 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4715 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4716 hw->fc.pause_time = fc_conf->pause_time;
4717 hw->fc.high_water[0] = fc_conf->high_water;
4718 hw->fc.low_water[0] = fc_conf->low_water;
4719 hw->fc.send_xon = fc_conf->send_xon;
4720 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4722 err = ixgbe_fc_enable(hw);
4724 /* Not negotiated is not an error case */
4725 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4727 /* check if we want to forward MAC frames - driver doesn't have native
4728 * capability to do that, so we'll write the registers ourselves */
4730 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4732 /* set or clear MFLCN.PMCF bit depending on configuration */
4733 if (fc_conf->mac_ctrl_frame_fwd != 0)
4734 mflcn |= IXGBE_MFLCN_PMCF;
4736 mflcn &= ~IXGBE_MFLCN_PMCF;
4738 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4739 IXGBE_WRITE_FLUSH(hw);
4744 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4749 * ixgbe_pfc_enable_generic - Enable flow control
4750 * @hw: pointer to hardware structure
4751 * @tc_num: traffic class number
4752 * Enable flow control according to the current settings.
4755 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4758 uint32_t mflcn_reg, fccfg_reg;
4760 uint32_t fcrtl, fcrth;
4764 /* Validate the water mark configuration */
4765 if (!hw->fc.pause_time) {
4766 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4770 /* Low water mark of zero causes XOFF floods */
4771 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4772 /* High/Low water can not be 0 */
4773 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4774 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4775 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4779 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4780 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4781 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4785 /* Negotiate the fc mode to use */
4786 ixgbe_fc_autoneg(hw);
4788 /* Disable any previous flow control settings */
4789 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4790 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4792 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4793 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4795 switch (hw->fc.current_mode) {
4798 * If the count of enabled RX Priority Flow control >1,
4799 * and the TX pause can not be disabled
4802 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4803 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4804 if (reg & IXGBE_FCRTH_FCEN)
4808 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4810 case ixgbe_fc_rx_pause:
4812 * Rx Flow control is enabled and Tx Flow control is
4813 * disabled by software override. Since there really
4814 * isn't a way to advertise that we are capable of RX
4815 * Pause ONLY, we will advertise that we support both
4816 * symmetric and asymmetric Rx PAUSE. Later, we will
4817 * disable the adapter's ability to send PAUSE frames.
4819 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4821 * If the count of enabled RX Priority Flow control >1,
4822 * and the TX pause can not be disabled
4825 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4826 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4827 if (reg & IXGBE_FCRTH_FCEN)
4831 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4833 case ixgbe_fc_tx_pause:
4835 * Tx Flow control is enabled, and Rx Flow control is
4836 * disabled by software override.
4838 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4841 /* Flow control (both Rx and Tx) is enabled by SW override. */
4842 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4843 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4846 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4847 ret_val = IXGBE_ERR_CONFIG;
4851 /* Set 802.3x based flow control settings. */
4852 mflcn_reg |= IXGBE_MFLCN_DPF;
4853 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4854 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4856 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4857 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4858 hw->fc.high_water[tc_num]) {
4859 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4860 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4861 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4863 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4865 * In order to prevent Tx hangs when the internal Tx
4866 * switch is enabled we must set the high water mark
4867 * to the maximum FCRTH value. This allows the Tx
4868 * switch to function even under heavy Rx workloads.
4870 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4872 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4874 /* Configure pause time (2 TCs per register) */
4875 reg = hw->fc.pause_time * 0x00010001;
4876 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4877 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4879 /* Configure flow control refresh threshold value */
4880 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4887 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4889 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4890 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4892 if (hw->mac.type != ixgbe_mac_82598EB) {
4893 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4899 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4902 uint32_t rx_buf_size;
4903 uint32_t max_high_water;
4905 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4906 struct ixgbe_hw *hw =
4907 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4908 struct ixgbe_dcb_config *dcb_config =
4909 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4911 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4918 PMD_INIT_FUNC_TRACE();
4920 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4921 tc_num = map[pfc_conf->priority];
4922 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4923 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4925 * At least reserve one Ethernet frame for watermark
4926 * high_water/low_water in kilo bytes for ixgbe
4928 max_high_water = (rx_buf_size -
4929 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4930 if ((pfc_conf->fc.high_water > max_high_water) ||
4931 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4932 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4933 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4937 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4938 hw->fc.pause_time = pfc_conf->fc.pause_time;
4939 hw->fc.send_xon = pfc_conf->fc.send_xon;
4940 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4941 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4943 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4945 /* Not negotiated is not an error case */
4946 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4949 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4954 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4955 struct rte_eth_rss_reta_entry64 *reta_conf,
4958 uint16_t i, sp_reta_size;
4961 uint16_t idx, shift;
4962 struct ixgbe_adapter *adapter = dev->data->dev_private;
4963 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4966 PMD_INIT_FUNC_TRACE();
4968 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4969 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4974 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4975 if (reta_size != sp_reta_size) {
4976 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4977 "(%d) doesn't match the number hardware can supported "
4978 "(%d)", reta_size, sp_reta_size);
4982 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4983 idx = i / RTE_RETA_GROUP_SIZE;
4984 shift = i % RTE_RETA_GROUP_SIZE;
4985 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4989 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4990 if (mask == IXGBE_4_BIT_MASK)
4993 r = IXGBE_READ_REG(hw, reta_reg);
4994 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4995 if (mask & (0x1 << j))
4996 reta |= reta_conf[idx].reta[shift + j] <<
4999 reta |= r & (IXGBE_8_BIT_MASK <<
5002 IXGBE_WRITE_REG(hw, reta_reg, reta);
5004 adapter->rss_reta_updated = 1;
5010 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5011 struct rte_eth_rss_reta_entry64 *reta_conf,
5014 uint16_t i, sp_reta_size;
5017 uint16_t idx, shift;
5018 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5021 PMD_INIT_FUNC_TRACE();
5022 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5023 if (reta_size != sp_reta_size) {
5024 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5025 "(%d) doesn't match the number hardware can supported "
5026 "(%d)", reta_size, sp_reta_size);
5030 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5031 idx = i / RTE_RETA_GROUP_SIZE;
5032 shift = i % RTE_RETA_GROUP_SIZE;
5033 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5038 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5039 reta = IXGBE_READ_REG(hw, reta_reg);
5040 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5041 if (mask & (0x1 << j))
5042 reta_conf[idx].reta[shift + j] =
5043 ((reta >> (CHAR_BIT * j)) &
5052 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5053 uint32_t index, uint32_t pool)
5055 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5056 uint32_t enable_addr = 1;
5058 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5063 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5065 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5067 ixgbe_clear_rar(hw, index);
5071 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5073 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5075 ixgbe_remove_rar(dev, 0);
5076 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5082 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5084 if (strcmp(dev->device->driver->name, drv->driver.name))
5091 is_ixgbe_supported(struct rte_eth_dev *dev)
5093 return is_device_supported(dev, &rte_ixgbe_pmd);
5097 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5101 struct ixgbe_hw *hw;
5102 struct rte_eth_dev_info dev_info;
5103 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5104 struct rte_eth_dev_data *dev_data = dev->data;
5107 ret = ixgbe_dev_info_get(dev, &dev_info);
5111 /* check that mtu is within the allowed range */
5112 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5115 /* If device is started, refuse mtu that requires the support of
5116 * scattered packets when this feature has not been enabled before.
5118 if (dev_data->dev_started && !dev_data->scattered_rx &&
5119 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5120 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5121 PMD_INIT_LOG(ERR, "Stop port first.");
5125 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5126 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5128 /* switch to jumbo mode if needed */
5129 if (frame_size > RTE_ETHER_MAX_LEN) {
5130 dev->data->dev_conf.rxmode.offloads |=
5131 DEV_RX_OFFLOAD_JUMBO_FRAME;
5132 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5134 dev->data->dev_conf.rxmode.offloads &=
5135 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5136 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5138 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5140 /* update max frame size */
5141 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5143 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5144 maxfrs &= 0x0000FFFF;
5145 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5146 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5152 * Virtual Function operations
5155 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5157 struct ixgbe_interrupt *intr =
5158 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5159 struct ixgbe_hw *hw =
5160 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5162 PMD_INIT_FUNC_TRACE();
5164 /* Clear interrupt mask to stop from interrupts being generated */
5165 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5167 IXGBE_WRITE_FLUSH(hw);
5169 /* Clear mask value. */
5174 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5176 struct ixgbe_interrupt *intr =
5177 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5178 struct ixgbe_hw *hw =
5179 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5181 PMD_INIT_FUNC_TRACE();
5183 /* VF enable interrupt autoclean */
5184 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5185 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5186 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5188 IXGBE_WRITE_FLUSH(hw);
5190 /* Save IXGBE_VTEIMS value to mask. */
5191 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5195 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5197 struct rte_eth_conf *conf = &dev->data->dev_conf;
5198 struct ixgbe_adapter *adapter = dev->data->dev_private;
5200 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5201 dev->data->port_id);
5203 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5204 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5207 * VF has no ability to enable/disable HW CRC
5208 * Keep the persistent behavior the same as Host PF
5210 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5211 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5212 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5213 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5216 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5217 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5218 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5223 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5224 * allocation or vector Rx preconditions we will reset it.
5226 adapter->rx_bulk_alloc_allowed = true;
5227 adapter->rx_vec_allowed = true;
5233 ixgbevf_dev_start(struct rte_eth_dev *dev)
5235 struct ixgbe_hw *hw =
5236 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5237 uint32_t intr_vector = 0;
5238 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5239 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5243 PMD_INIT_FUNC_TRACE();
5245 /* Stop the link setup handler before resetting the HW. */
5246 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5248 err = hw->mac.ops.reset_hw(hw);
5250 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5253 hw->mac.get_link_status = true;
5255 /* negotiate mailbox API version to use with the PF. */
5256 ixgbevf_negotiate_api(hw);
5258 ixgbevf_dev_tx_init(dev);
5260 /* This can fail when allocating mbufs for descriptor rings */
5261 err = ixgbevf_dev_rx_init(dev);
5263 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5264 ixgbe_dev_clear_queues(dev);
5269 ixgbevf_set_vfta_all(dev, 1);
5272 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5273 ETH_VLAN_EXTEND_MASK;
5274 err = ixgbevf_vlan_offload_config(dev, mask);
5276 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5277 ixgbe_dev_clear_queues(dev);
5281 ixgbevf_dev_rxtx_start(dev);
5283 /* check and configure queue intr-vector mapping */
5284 if (rte_intr_cap_multiple(intr_handle) &&
5285 dev->data->dev_conf.intr_conf.rxq) {
5286 /* According to datasheet, only vector 0/1/2 can be used,
5287 * now only one vector is used for Rx queue
5290 if (rte_intr_efd_enable(intr_handle, intr_vector))
5294 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5295 intr_handle->intr_vec =
5296 rte_zmalloc("intr_vec",
5297 dev->data->nb_rx_queues * sizeof(int), 0);
5298 if (intr_handle->intr_vec == NULL) {
5299 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5300 " intr_vec", dev->data->nb_rx_queues);
5304 ixgbevf_configure_msix(dev);
5306 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5307 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5308 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5309 * is not cleared, it will fail when following rte_intr_enable( ) tries
5310 * to map Rx queue interrupt to other VFIO vectors.
5311 * So clear uio/vfio intr/evevnfd first to avoid failure.
5313 rte_intr_disable(intr_handle);
5315 rte_intr_enable(intr_handle);
5317 /* Re-enable interrupt for VF */
5318 ixgbevf_intr_enable(dev);
5321 * Update link status right before return, because it may
5322 * start link configuration process in a separate thread.
5324 ixgbevf_dev_link_update(dev, 0);
5326 hw->adapter_stopped = false;
5332 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5334 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5335 struct ixgbe_adapter *adapter = dev->data->dev_private;
5336 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5337 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5339 if (hw->adapter_stopped)
5342 PMD_INIT_FUNC_TRACE();
5344 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5346 ixgbevf_intr_disable(dev);
5348 hw->adapter_stopped = 1;
5349 ixgbe_stop_adapter(hw);
5352 * Clear what we set, but we still keep shadow_vfta to
5353 * restore after device starts
5355 ixgbevf_set_vfta_all(dev, 0);
5357 /* Clear stored conf */
5358 dev->data->scattered_rx = 0;
5360 ixgbe_dev_clear_queues(dev);
5362 /* Clean datapath event and queue/vec mapping */
5363 rte_intr_efd_disable(intr_handle);
5364 if (intr_handle->intr_vec != NULL) {
5365 rte_free(intr_handle->intr_vec);
5366 intr_handle->intr_vec = NULL;
5369 adapter->rss_reta_updated = 0;
5373 ixgbevf_dev_close(struct rte_eth_dev *dev)
5375 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5376 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5377 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5379 PMD_INIT_FUNC_TRACE();
5383 ixgbevf_dev_stop(dev);
5385 ixgbe_dev_free_queues(dev);
5388 * Remove the VF MAC address ro ensure
5389 * that the VF traffic goes to the PF
5390 * after stop, close and detach of the VF
5392 ixgbevf_remove_mac_addr(dev, 0);
5394 dev->dev_ops = NULL;
5395 dev->rx_pkt_burst = NULL;
5396 dev->tx_pkt_burst = NULL;
5398 rte_intr_disable(intr_handle);
5399 rte_intr_callback_unregister(intr_handle,
5400 ixgbevf_dev_interrupt_handler, dev);
5407 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5411 ret = eth_ixgbevf_dev_uninit(dev);
5415 ret = eth_ixgbevf_dev_init(dev);
5420 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5422 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5423 struct ixgbe_vfta *shadow_vfta =
5424 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5425 int i = 0, j = 0, vfta = 0, mask = 1;
5427 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5428 vfta = shadow_vfta->vfta[i];
5431 for (j = 0; j < 32; j++) {
5433 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5443 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5445 struct ixgbe_hw *hw =
5446 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5447 struct ixgbe_vfta *shadow_vfta =
5448 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5449 uint32_t vid_idx = 0;
5450 uint32_t vid_bit = 0;
5453 PMD_INIT_FUNC_TRACE();
5455 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5456 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5458 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5461 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5462 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5464 /* Save what we set and retore it after device reset */
5466 shadow_vfta->vfta[vid_idx] |= vid_bit;
5468 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5474 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5476 struct ixgbe_hw *hw =
5477 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5480 PMD_INIT_FUNC_TRACE();
5482 if (queue >= hw->mac.max_rx_queues)
5485 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5487 ctrl |= IXGBE_RXDCTL_VME;
5489 ctrl &= ~IXGBE_RXDCTL_VME;
5490 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5492 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5496 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5498 struct ixgbe_rx_queue *rxq;
5502 /* VF function only support hw strip feature, others are not support */
5503 if (mask & ETH_VLAN_STRIP_MASK) {
5504 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5505 rxq = dev->data->rx_queues[i];
5506 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5507 ixgbevf_vlan_strip_queue_set(dev, i, on);
5515 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5517 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5519 ixgbevf_vlan_offload_config(dev, mask);
5525 ixgbe_vt_check(struct ixgbe_hw *hw)
5529 /* if Virtualization Technology is enabled */
5530 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5531 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5532 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5540 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5542 uint32_t vector = 0;
5544 switch (hw->mac.mc_filter_type) {
5545 case 0: /* use bits [47:36] of the address */
5546 vector = ((uc_addr->addr_bytes[4] >> 4) |
5547 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5549 case 1: /* use bits [46:35] of the address */
5550 vector = ((uc_addr->addr_bytes[4] >> 3) |
5551 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5553 case 2: /* use bits [45:34] of the address */
5554 vector = ((uc_addr->addr_bytes[4] >> 2) |
5555 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5557 case 3: /* use bits [43:32] of the address */
5558 vector = ((uc_addr->addr_bytes[4]) |
5559 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5561 default: /* Invalid mc_filter_type */
5565 /* vector can only be 12-bits or boundary will be exceeded */
5571 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5572 struct rte_ether_addr *mac_addr, uint8_t on)
5579 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5580 const uint32_t ixgbe_uta_bit_shift = 5;
5581 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5582 const uint32_t bit1 = 0x1;
5584 struct ixgbe_hw *hw =
5585 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5586 struct ixgbe_uta_info *uta_info =
5587 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5589 /* The UTA table only exists on 82599 hardware and newer */
5590 if (hw->mac.type < ixgbe_mac_82599EB)
5593 vector = ixgbe_uta_vector(hw, mac_addr);
5594 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5595 uta_shift = vector & ixgbe_uta_bit_mask;
5597 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5601 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5603 uta_info->uta_in_use++;
5604 reg_val |= (bit1 << uta_shift);
5605 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5607 uta_info->uta_in_use--;
5608 reg_val &= ~(bit1 << uta_shift);
5609 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5612 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5614 if (uta_info->uta_in_use > 0)
5615 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5616 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5618 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5624 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5627 struct ixgbe_hw *hw =
5628 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5629 struct ixgbe_uta_info *uta_info =
5630 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5632 /* The UTA table only exists on 82599 hardware and newer */
5633 if (hw->mac.type < ixgbe_mac_82599EB)
5637 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5638 uta_info->uta_shadow[i] = ~0;
5639 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5642 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5643 uta_info->uta_shadow[i] = 0;
5644 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5652 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5654 uint32_t new_val = orig_val;
5656 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5657 new_val |= IXGBE_VMOLR_AUPE;
5658 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5659 new_val |= IXGBE_VMOLR_ROMPE;
5660 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5661 new_val |= IXGBE_VMOLR_ROPE;
5662 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5663 new_val |= IXGBE_VMOLR_BAM;
5664 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5665 new_val |= IXGBE_VMOLR_MPE;
5670 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5671 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5672 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5673 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5674 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5675 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5676 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5679 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5680 struct rte_eth_mirror_conf *mirror_conf,
5681 uint8_t rule_id, uint8_t on)
5683 uint32_t mr_ctl, vlvf;
5684 uint32_t mp_lsb = 0;
5685 uint32_t mv_msb = 0;
5686 uint32_t mv_lsb = 0;
5687 uint32_t mp_msb = 0;
5690 uint64_t vlan_mask = 0;
5692 const uint8_t pool_mask_offset = 32;
5693 const uint8_t vlan_mask_offset = 32;
5694 const uint8_t dst_pool_offset = 8;
5695 const uint8_t rule_mr_offset = 4;
5696 const uint8_t mirror_rule_mask = 0x0F;
5698 struct ixgbe_mirror_info *mr_info =
5699 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5700 struct ixgbe_hw *hw =
5701 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5702 uint8_t mirror_type = 0;
5704 if (ixgbe_vt_check(hw) < 0)
5707 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5710 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5711 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5712 mirror_conf->rule_type);
5716 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5717 mirror_type |= IXGBE_MRCTL_VLME;
5718 /* Check if vlan id is valid and find conresponding VLAN ID
5721 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5722 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5723 /* search vlan id related pool vlan filter
5726 reg_index = ixgbe_find_vlvf_slot(
5728 mirror_conf->vlan.vlan_id[i],
5732 vlvf = IXGBE_READ_REG(hw,
5733 IXGBE_VLVF(reg_index));
5734 if ((vlvf & IXGBE_VLVF_VIEN) &&
5735 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5736 mirror_conf->vlan.vlan_id[i]))
5737 vlan_mask |= (1ULL << reg_index);
5744 mv_lsb = vlan_mask & 0xFFFFFFFF;
5745 mv_msb = vlan_mask >> vlan_mask_offset;
5747 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5748 mirror_conf->vlan.vlan_mask;
5749 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5750 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5751 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5752 mirror_conf->vlan.vlan_id[i];
5757 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5758 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5759 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5764 * if enable pool mirror, write related pool mask register,if disable
5765 * pool mirror, clear PFMRVM register
5767 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5768 mirror_type |= IXGBE_MRCTL_VPME;
5770 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5771 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5772 mr_info->mr_conf[rule_id].pool_mask =
5773 mirror_conf->pool_mask;
5778 mr_info->mr_conf[rule_id].pool_mask = 0;
5781 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5782 mirror_type |= IXGBE_MRCTL_UPME;
5783 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5784 mirror_type |= IXGBE_MRCTL_DPME;
5786 /* read mirror control register and recalculate it */
5787 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5790 mr_ctl |= mirror_type;
5791 mr_ctl &= mirror_rule_mask;
5792 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5794 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5797 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5798 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5800 /* write mirrror control register */
5801 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5803 /* write pool mirrror control register */
5804 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5805 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5806 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5809 /* write VLAN mirrror control register */
5810 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5811 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5812 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5820 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5823 uint32_t lsb_val = 0;
5824 uint32_t msb_val = 0;
5825 const uint8_t rule_mr_offset = 4;
5827 struct ixgbe_hw *hw =
5828 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5829 struct ixgbe_mirror_info *mr_info =
5830 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5832 if (ixgbe_vt_check(hw) < 0)
5835 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5838 memset(&mr_info->mr_conf[rule_id], 0,
5839 sizeof(struct rte_eth_mirror_conf));
5841 /* clear PFVMCTL register */
5842 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5844 /* clear pool mask register */
5845 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5846 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5848 /* clear vlan mask register */
5849 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5850 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5856 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5858 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5859 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5860 struct ixgbe_interrupt *intr =
5861 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5862 struct ixgbe_hw *hw =
5863 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5864 uint32_t vec = IXGBE_MISC_VEC_ID;
5866 if (rte_intr_allow_others(intr_handle))
5867 vec = IXGBE_RX_VEC_START;
5868 intr->mask |= (1 << vec);
5869 RTE_SET_USED(queue_id);
5870 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5872 rte_intr_ack(intr_handle);
5878 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5880 struct ixgbe_interrupt *intr =
5881 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5882 struct ixgbe_hw *hw =
5883 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5884 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5885 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5886 uint32_t vec = IXGBE_MISC_VEC_ID;
5888 if (rte_intr_allow_others(intr_handle))
5889 vec = IXGBE_RX_VEC_START;
5890 intr->mask &= ~(1 << vec);
5891 RTE_SET_USED(queue_id);
5892 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5898 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5900 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5901 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5903 struct ixgbe_hw *hw =
5904 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5905 struct ixgbe_interrupt *intr =
5906 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5908 if (queue_id < 16) {
5909 ixgbe_disable_intr(hw);
5910 intr->mask |= (1 << queue_id);
5911 ixgbe_enable_intr(dev);
5912 } else if (queue_id < 32) {
5913 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5914 mask &= (1 << queue_id);
5915 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5916 } else if (queue_id < 64) {
5917 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5918 mask &= (1 << (queue_id - 32));
5919 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5921 rte_intr_ack(intr_handle);
5927 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5930 struct ixgbe_hw *hw =
5931 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5932 struct ixgbe_interrupt *intr =
5933 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5935 if (queue_id < 16) {
5936 ixgbe_disable_intr(hw);
5937 intr->mask &= ~(1 << queue_id);
5938 ixgbe_enable_intr(dev);
5939 } else if (queue_id < 32) {
5940 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5941 mask &= ~(1 << queue_id);
5942 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5943 } else if (queue_id < 64) {
5944 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5945 mask &= ~(1 << (queue_id - 32));
5946 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5953 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5954 uint8_t queue, uint8_t msix_vector)
5958 if (direction == -1) {
5960 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5961 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5964 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5966 /* rx or tx cause */
5967 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5968 idx = ((16 * (queue & 1)) + (8 * direction));
5969 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5970 tmp &= ~(0xFF << idx);
5971 tmp |= (msix_vector << idx);
5972 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5977 * set the IVAR registers, mapping interrupt causes to vectors
5979 * pointer to ixgbe_hw struct
5981 * 0 for Rx, 1 for Tx, -1 for other causes
5983 * queue to map the corresponding interrupt to
5985 * the vector to map to the corresponding queue
5988 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5989 uint8_t queue, uint8_t msix_vector)
5993 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5994 if (hw->mac.type == ixgbe_mac_82598EB) {
5995 if (direction == -1)
5997 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5998 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5999 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6000 tmp |= (msix_vector << (8 * (queue & 0x3)));
6001 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6002 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6003 (hw->mac.type == ixgbe_mac_X540) ||
6004 (hw->mac.type == ixgbe_mac_X550) ||
6005 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6006 if (direction == -1) {
6008 idx = ((queue & 1) * 8);
6009 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6010 tmp &= ~(0xFF << idx);
6011 tmp |= (msix_vector << idx);
6012 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6014 /* rx or tx causes */
6015 idx = ((16 * (queue & 1)) + (8 * direction));
6016 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6017 tmp &= ~(0xFF << idx);
6018 tmp |= (msix_vector << idx);
6019 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6025 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6027 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6028 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6029 struct ixgbe_hw *hw =
6030 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6032 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6033 uint32_t base = IXGBE_MISC_VEC_ID;
6035 /* Configure VF other cause ivar */
6036 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6038 /* won't configure msix register if no mapping is done
6039 * between intr vector and event fd.
6041 if (!rte_intr_dp_is_en(intr_handle))
6044 if (rte_intr_allow_others(intr_handle)) {
6045 base = IXGBE_RX_VEC_START;
6046 vector_idx = IXGBE_RX_VEC_START;
6049 /* Configure all RX queues of VF */
6050 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6051 /* Force all queue use vector 0,
6052 * as IXGBE_VF_MAXMSIVECOTR = 1
6054 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6055 intr_handle->intr_vec[q_idx] = vector_idx;
6056 if (vector_idx < base + intr_handle->nb_efd - 1)
6060 /* As RX queue setting above show, all queues use the vector 0.
6061 * Set only the ITR value of IXGBE_MISC_VEC_ID.
6063 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6064 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6065 | IXGBE_EITR_CNT_WDIS);
6069 * Sets up the hardware to properly generate MSI-X interrupts
6071 * board private structure
6074 ixgbe_configure_msix(struct rte_eth_dev *dev)
6076 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6077 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6078 struct ixgbe_hw *hw =
6079 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6080 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6081 uint32_t vec = IXGBE_MISC_VEC_ID;
6085 /* won't configure msix register if no mapping is done
6086 * between intr vector and event fd
6087 * but if misx has been enabled already, need to configure
6088 * auto clean, auto mask and throttling.
6090 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6091 if (!rte_intr_dp_is_en(intr_handle) &&
6092 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6095 if (rte_intr_allow_others(intr_handle))
6096 vec = base = IXGBE_RX_VEC_START;
6098 /* setup GPIE for MSI-x mode */
6099 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6100 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6101 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6102 /* auto clearing and auto setting corresponding bits in EIMS
6103 * when MSI-X interrupt is triggered
6105 if (hw->mac.type == ixgbe_mac_82598EB) {
6106 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6108 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6109 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6111 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6113 /* Populate the IVAR table and set the ITR values to the
6114 * corresponding register.
6116 if (rte_intr_dp_is_en(intr_handle)) {
6117 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6119 /* by default, 1:1 mapping */
6120 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6121 intr_handle->intr_vec[queue_id] = vec;
6122 if (vec < base + intr_handle->nb_efd - 1)
6126 switch (hw->mac.type) {
6127 case ixgbe_mac_82598EB:
6128 ixgbe_set_ivar_map(hw, -1,
6129 IXGBE_IVAR_OTHER_CAUSES_INDEX,
6132 case ixgbe_mac_82599EB:
6133 case ixgbe_mac_X540:
6134 case ixgbe_mac_X550:
6135 case ixgbe_mac_X550EM_x:
6136 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6142 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6143 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6144 | IXGBE_EITR_CNT_WDIS);
6146 /* set up to autoclear timer, and the vectors */
6147 mask = IXGBE_EIMS_ENABLE_MASK;
6148 mask &= ~(IXGBE_EIMS_OTHER |
6149 IXGBE_EIMS_MAILBOX |
6152 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6156 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6157 uint16_t queue_idx, uint16_t tx_rate)
6159 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6160 struct rte_eth_rxmode *rxmode;
6161 uint32_t rf_dec, rf_int;
6163 uint16_t link_speed = dev->data->dev_link.link_speed;
6165 if (queue_idx >= hw->mac.max_tx_queues)
6169 /* Calculate the rate factor values to set */
6170 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6171 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6172 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6174 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6175 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6176 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6177 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6182 rxmode = &dev->data->dev_conf.rxmode;
6184 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6185 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6188 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6189 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6190 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6191 IXGBE_MMW_SIZE_JUMBO_FRAME);
6193 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6194 IXGBE_MMW_SIZE_DEFAULT);
6196 /* Set RTTBCNRC of queue X */
6197 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6198 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6199 IXGBE_WRITE_FLUSH(hw);
6205 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6206 __attribute__((unused)) uint32_t index,
6207 __attribute__((unused)) uint32_t pool)
6209 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6213 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6214 * operation. Trap this case to avoid exhausting the [very limited]
6215 * set of PF resources used to store VF MAC addresses.
6217 if (memcmp(hw->mac.perm_addr, mac_addr,
6218 sizeof(struct rte_ether_addr)) == 0)
6220 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6222 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6223 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6224 mac_addr->addr_bytes[0],
6225 mac_addr->addr_bytes[1],
6226 mac_addr->addr_bytes[2],
6227 mac_addr->addr_bytes[3],
6228 mac_addr->addr_bytes[4],
6229 mac_addr->addr_bytes[5],
6235 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6237 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6238 struct rte_ether_addr *perm_addr =
6239 (struct rte_ether_addr *)hw->mac.perm_addr;
6240 struct rte_ether_addr *mac_addr;
6245 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6246 * not support the deletion of a given MAC address.
6247 * Instead, it imposes to delete all MAC addresses, then to add again
6248 * all MAC addresses with the exception of the one to be deleted.
6250 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6253 * Add again all MAC addresses, with the exception of the deleted one
6254 * and of the permanent MAC address.
6256 for (i = 0, mac_addr = dev->data->mac_addrs;
6257 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6258 /* Skip the deleted MAC address */
6261 /* Skip NULL MAC addresses */
6262 if (rte_is_zero_ether_addr(mac_addr))
6264 /* Skip the permanent MAC address */
6265 if (memcmp(perm_addr, mac_addr,
6266 sizeof(struct rte_ether_addr)) == 0)
6268 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6271 "Adding again MAC address "
6272 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6274 mac_addr->addr_bytes[0],
6275 mac_addr->addr_bytes[1],
6276 mac_addr->addr_bytes[2],
6277 mac_addr->addr_bytes[3],
6278 mac_addr->addr_bytes[4],
6279 mac_addr->addr_bytes[5],
6285 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6286 struct rte_ether_addr *addr)
6288 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6290 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6296 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6297 struct rte_eth_syn_filter *filter,
6300 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6301 struct ixgbe_filter_info *filter_info =
6302 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6306 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6309 syn_info = filter_info->syn_info;
6312 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6314 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6315 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6317 if (filter->hig_pri)
6318 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6320 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6322 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6323 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6325 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6328 filter_info->syn_info = synqf;
6329 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6330 IXGBE_WRITE_FLUSH(hw);
6335 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6336 struct rte_eth_syn_filter *filter)
6338 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6339 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6341 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6342 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6343 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6350 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6351 enum rte_filter_op filter_op,
6354 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6357 MAC_TYPE_FILTER_SUP(hw->mac.type);
6359 if (filter_op == RTE_ETH_FILTER_NOP)
6363 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6368 switch (filter_op) {
6369 case RTE_ETH_FILTER_ADD:
6370 ret = ixgbe_syn_filter_set(dev,
6371 (struct rte_eth_syn_filter *)arg,
6374 case RTE_ETH_FILTER_DELETE:
6375 ret = ixgbe_syn_filter_set(dev,
6376 (struct rte_eth_syn_filter *)arg,
6379 case RTE_ETH_FILTER_GET:
6380 ret = ixgbe_syn_filter_get(dev,
6381 (struct rte_eth_syn_filter *)arg);
6384 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6393 static inline enum ixgbe_5tuple_protocol
6394 convert_protocol_type(uint8_t protocol_value)
6396 if (protocol_value == IPPROTO_TCP)
6397 return IXGBE_FILTER_PROTOCOL_TCP;
6398 else if (protocol_value == IPPROTO_UDP)
6399 return IXGBE_FILTER_PROTOCOL_UDP;
6400 else if (protocol_value == IPPROTO_SCTP)
6401 return IXGBE_FILTER_PROTOCOL_SCTP;
6403 return IXGBE_FILTER_PROTOCOL_NONE;
6406 /* inject a 5-tuple filter to HW */
6408 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6409 struct ixgbe_5tuple_filter *filter)
6411 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6413 uint32_t ftqf, sdpqf;
6414 uint32_t l34timir = 0;
6415 uint8_t mask = 0xff;
6419 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6420 IXGBE_SDPQF_DSTPORT_SHIFT);
6421 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6423 ftqf = (uint32_t)(filter->filter_info.proto &
6424 IXGBE_FTQF_PROTOCOL_MASK);
6425 ftqf |= (uint32_t)((filter->filter_info.priority &
6426 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6427 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6428 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6429 if (filter->filter_info.dst_ip_mask == 0)
6430 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6431 if (filter->filter_info.src_port_mask == 0)
6432 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6433 if (filter->filter_info.dst_port_mask == 0)
6434 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6435 if (filter->filter_info.proto_mask == 0)
6436 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6437 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6438 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6439 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6441 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6442 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6443 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6444 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6446 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6447 l34timir |= (uint32_t)(filter->queue <<
6448 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6449 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6453 * add a 5tuple filter
6456 * dev: Pointer to struct rte_eth_dev.
6457 * index: the index the filter allocates.
6458 * filter: ponter to the filter that will be added.
6459 * rx_queue: the queue id the filter assigned to.
6462 * - On success, zero.
6463 * - On failure, a negative value.
6466 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6467 struct ixgbe_5tuple_filter *filter)
6469 struct ixgbe_filter_info *filter_info =
6470 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6474 * look for an unused 5tuple filter index,
6475 * and insert the filter to list.
6477 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6478 idx = i / (sizeof(uint32_t) * NBBY);
6479 shift = i % (sizeof(uint32_t) * NBBY);
6480 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6481 filter_info->fivetuple_mask[idx] |= 1 << shift;
6483 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6489 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6490 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6494 ixgbe_inject_5tuple_filter(dev, filter);
6500 * remove a 5tuple filter
6503 * dev: Pointer to struct rte_eth_dev.
6504 * filter: the pointer of the filter will be removed.
6507 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6508 struct ixgbe_5tuple_filter *filter)
6510 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6511 struct ixgbe_filter_info *filter_info =
6512 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6513 uint16_t index = filter->index;
6515 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6516 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6517 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6520 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6521 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6522 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6523 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6524 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6528 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6530 struct ixgbe_hw *hw;
6531 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6532 struct rte_eth_dev_data *dev_data = dev->data;
6534 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6536 if (mtu < RTE_ETHER_MIN_MTU ||
6537 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6540 /* If device is started, refuse mtu that requires the support of
6541 * scattered packets when this feature has not been enabled before.
6543 if (dev_data->dev_started && !dev_data->scattered_rx &&
6544 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6545 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6546 PMD_INIT_LOG(ERR, "Stop port first.");
6551 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6552 * request of the version 2.0 of the mailbox API.
6553 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6554 * of the mailbox API.
6555 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6556 * prior to 3.11.33 which contains the following change:
6557 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6559 ixgbevf_rlpml_set_vf(hw, max_frame);
6561 /* update max frame size */
6562 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6566 static inline struct ixgbe_5tuple_filter *
6567 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6568 struct ixgbe_5tuple_filter_info *key)
6570 struct ixgbe_5tuple_filter *it;
6572 TAILQ_FOREACH(it, filter_list, entries) {
6573 if (memcmp(key, &it->filter_info,
6574 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6581 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6583 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6584 struct ixgbe_5tuple_filter_info *filter_info)
6586 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6587 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6588 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6591 switch (filter->dst_ip_mask) {
6593 filter_info->dst_ip_mask = 0;
6594 filter_info->dst_ip = filter->dst_ip;
6597 filter_info->dst_ip_mask = 1;
6600 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6604 switch (filter->src_ip_mask) {
6606 filter_info->src_ip_mask = 0;
6607 filter_info->src_ip = filter->src_ip;
6610 filter_info->src_ip_mask = 1;
6613 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6617 switch (filter->dst_port_mask) {
6619 filter_info->dst_port_mask = 0;
6620 filter_info->dst_port = filter->dst_port;
6623 filter_info->dst_port_mask = 1;
6626 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6630 switch (filter->src_port_mask) {
6632 filter_info->src_port_mask = 0;
6633 filter_info->src_port = filter->src_port;
6636 filter_info->src_port_mask = 1;
6639 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6643 switch (filter->proto_mask) {
6645 filter_info->proto_mask = 0;
6646 filter_info->proto =
6647 convert_protocol_type(filter->proto);
6650 filter_info->proto_mask = 1;
6653 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6657 filter_info->priority = (uint8_t)filter->priority;
6662 * add or delete a ntuple filter
6665 * dev: Pointer to struct rte_eth_dev.
6666 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6667 * add: if true, add filter, if false, remove filter
6670 * - On success, zero.
6671 * - On failure, a negative value.
6674 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6675 struct rte_eth_ntuple_filter *ntuple_filter,
6678 struct ixgbe_filter_info *filter_info =
6679 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6680 struct ixgbe_5tuple_filter_info filter_5tuple;
6681 struct ixgbe_5tuple_filter *filter;
6684 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6685 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6689 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6690 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6694 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6696 if (filter != NULL && add) {
6697 PMD_DRV_LOG(ERR, "filter exists.");
6700 if (filter == NULL && !add) {
6701 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6706 filter = rte_zmalloc("ixgbe_5tuple_filter",
6707 sizeof(struct ixgbe_5tuple_filter), 0);
6710 rte_memcpy(&filter->filter_info,
6712 sizeof(struct ixgbe_5tuple_filter_info));
6713 filter->queue = ntuple_filter->queue;
6714 ret = ixgbe_add_5tuple_filter(dev, filter);
6720 ixgbe_remove_5tuple_filter(dev, filter);
6726 * get a ntuple filter
6729 * dev: Pointer to struct rte_eth_dev.
6730 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6733 * - On success, zero.
6734 * - On failure, a negative value.
6737 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6738 struct rte_eth_ntuple_filter *ntuple_filter)
6740 struct ixgbe_filter_info *filter_info =
6741 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6742 struct ixgbe_5tuple_filter_info filter_5tuple;
6743 struct ixgbe_5tuple_filter *filter;
6746 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6747 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6751 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6752 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6756 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6758 if (filter == NULL) {
6759 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6762 ntuple_filter->queue = filter->queue;
6767 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6768 * @dev: pointer to rte_eth_dev structure
6769 * @filter_op:operation will be taken.
6770 * @arg: a pointer to specific structure corresponding to the filter_op
6773 * - On success, zero.
6774 * - On failure, a negative value.
6777 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6778 enum rte_filter_op filter_op,
6781 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6784 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6786 if (filter_op == RTE_ETH_FILTER_NOP)
6790 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6795 switch (filter_op) {
6796 case RTE_ETH_FILTER_ADD:
6797 ret = ixgbe_add_del_ntuple_filter(dev,
6798 (struct rte_eth_ntuple_filter *)arg,
6801 case RTE_ETH_FILTER_DELETE:
6802 ret = ixgbe_add_del_ntuple_filter(dev,
6803 (struct rte_eth_ntuple_filter *)arg,
6806 case RTE_ETH_FILTER_GET:
6807 ret = ixgbe_get_ntuple_filter(dev,
6808 (struct rte_eth_ntuple_filter *)arg);
6811 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6819 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6820 struct rte_eth_ethertype_filter *filter,
6823 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6824 struct ixgbe_filter_info *filter_info =
6825 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6829 struct ixgbe_ethertype_filter ethertype_filter;
6831 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6834 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6835 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6836 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6837 " ethertype filter.", filter->ether_type);
6841 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6842 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6845 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6846 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6850 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6851 if (ret >= 0 && add) {
6852 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6853 filter->ether_type);
6856 if (ret < 0 && !add) {
6857 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6858 filter->ether_type);
6863 etqf = IXGBE_ETQF_FILTER_EN;
6864 etqf |= (uint32_t)filter->ether_type;
6865 etqs |= (uint32_t)((filter->queue <<
6866 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6867 IXGBE_ETQS_RX_QUEUE);
6868 etqs |= IXGBE_ETQS_QUEUE_EN;
6870 ethertype_filter.ethertype = filter->ether_type;
6871 ethertype_filter.etqf = etqf;
6872 ethertype_filter.etqs = etqs;
6873 ethertype_filter.conf = FALSE;
6874 ret = ixgbe_ethertype_filter_insert(filter_info,
6877 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6881 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6885 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6886 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6887 IXGBE_WRITE_FLUSH(hw);
6893 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6894 struct rte_eth_ethertype_filter *filter)
6896 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6897 struct ixgbe_filter_info *filter_info =
6898 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6899 uint32_t etqf, etqs;
6902 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6904 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6905 filter->ether_type);
6909 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6910 if (etqf & IXGBE_ETQF_FILTER_EN) {
6911 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6912 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6914 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6915 IXGBE_ETQS_RX_QUEUE_SHIFT;
6922 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6923 * @dev: pointer to rte_eth_dev structure
6924 * @filter_op:operation will be taken.
6925 * @arg: a pointer to specific structure corresponding to the filter_op
6928 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6929 enum rte_filter_op filter_op,
6932 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6935 MAC_TYPE_FILTER_SUP(hw->mac.type);
6937 if (filter_op == RTE_ETH_FILTER_NOP)
6941 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6946 switch (filter_op) {
6947 case RTE_ETH_FILTER_ADD:
6948 ret = ixgbe_add_del_ethertype_filter(dev,
6949 (struct rte_eth_ethertype_filter *)arg,
6952 case RTE_ETH_FILTER_DELETE:
6953 ret = ixgbe_add_del_ethertype_filter(dev,
6954 (struct rte_eth_ethertype_filter *)arg,
6957 case RTE_ETH_FILTER_GET:
6958 ret = ixgbe_get_ethertype_filter(dev,
6959 (struct rte_eth_ethertype_filter *)arg);
6962 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6970 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6971 enum rte_filter_type filter_type,
6972 enum rte_filter_op filter_op,
6977 switch (filter_type) {
6978 case RTE_ETH_FILTER_NTUPLE:
6979 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6981 case RTE_ETH_FILTER_ETHERTYPE:
6982 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6984 case RTE_ETH_FILTER_SYN:
6985 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6987 case RTE_ETH_FILTER_FDIR:
6988 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6990 case RTE_ETH_FILTER_L2_TUNNEL:
6991 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6993 case RTE_ETH_FILTER_GENERIC:
6994 if (filter_op != RTE_ETH_FILTER_GET)
6996 *(const void **)arg = &ixgbe_flow_ops;
6999 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7009 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
7010 u8 **mc_addr_ptr, u32 *vmdq)
7015 mc_addr = *mc_addr_ptr;
7016 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7021 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7022 struct rte_ether_addr *mc_addr_set,
7023 uint32_t nb_mc_addr)
7025 struct ixgbe_hw *hw;
7028 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7029 mc_addr_list = (u8 *)mc_addr_set;
7030 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7031 ixgbe_dev_addr_list_itr, TRUE);
7035 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7037 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7038 uint64_t systime_cycles;
7040 switch (hw->mac.type) {
7041 case ixgbe_mac_X550:
7042 case ixgbe_mac_X550EM_x:
7043 case ixgbe_mac_X550EM_a:
7044 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7045 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7046 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7050 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7051 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7055 return systime_cycles;
7059 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7061 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7062 uint64_t rx_tstamp_cycles;
7064 switch (hw->mac.type) {
7065 case ixgbe_mac_X550:
7066 case ixgbe_mac_X550EM_x:
7067 case ixgbe_mac_X550EM_a:
7068 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7069 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7070 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7074 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7075 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7076 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7080 return rx_tstamp_cycles;
7084 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7086 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7087 uint64_t tx_tstamp_cycles;
7089 switch (hw->mac.type) {
7090 case ixgbe_mac_X550:
7091 case ixgbe_mac_X550EM_x:
7092 case ixgbe_mac_X550EM_a:
7093 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7094 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7095 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7099 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7100 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7101 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7105 return tx_tstamp_cycles;
7109 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7111 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7112 struct ixgbe_adapter *adapter = dev->data->dev_private;
7113 struct rte_eth_link link;
7114 uint32_t incval = 0;
7117 /* Get current link speed. */
7118 ixgbe_dev_link_update(dev, 1);
7119 rte_eth_linkstatus_get(dev, &link);
7121 switch (link.link_speed) {
7122 case ETH_SPEED_NUM_100M:
7123 incval = IXGBE_INCVAL_100;
7124 shift = IXGBE_INCVAL_SHIFT_100;
7126 case ETH_SPEED_NUM_1G:
7127 incval = IXGBE_INCVAL_1GB;
7128 shift = IXGBE_INCVAL_SHIFT_1GB;
7130 case ETH_SPEED_NUM_10G:
7132 incval = IXGBE_INCVAL_10GB;
7133 shift = IXGBE_INCVAL_SHIFT_10GB;
7137 switch (hw->mac.type) {
7138 case ixgbe_mac_X550:
7139 case ixgbe_mac_X550EM_x:
7140 case ixgbe_mac_X550EM_a:
7141 /* Independent of link speed. */
7143 /* Cycles read will be interpreted as ns. */
7146 case ixgbe_mac_X540:
7147 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7149 case ixgbe_mac_82599EB:
7150 incval >>= IXGBE_INCVAL_SHIFT_82599;
7151 shift -= IXGBE_INCVAL_SHIFT_82599;
7152 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7153 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7156 /* Not supported. */
7160 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7161 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7162 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7164 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7165 adapter->systime_tc.cc_shift = shift;
7166 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7168 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7169 adapter->rx_tstamp_tc.cc_shift = shift;
7170 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7172 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7173 adapter->tx_tstamp_tc.cc_shift = shift;
7174 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7178 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7180 struct ixgbe_adapter *adapter = dev->data->dev_private;
7182 adapter->systime_tc.nsec += delta;
7183 adapter->rx_tstamp_tc.nsec += delta;
7184 adapter->tx_tstamp_tc.nsec += delta;
7190 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7193 struct ixgbe_adapter *adapter = dev->data->dev_private;
7195 ns = rte_timespec_to_ns(ts);
7196 /* Set the timecounters to a new value. */
7197 adapter->systime_tc.nsec = ns;
7198 adapter->rx_tstamp_tc.nsec = ns;
7199 adapter->tx_tstamp_tc.nsec = ns;
7205 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7207 uint64_t ns, systime_cycles;
7208 struct ixgbe_adapter *adapter = dev->data->dev_private;
7210 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7211 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7212 *ts = rte_ns_to_timespec(ns);
7218 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7220 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7224 /* Stop the timesync system time. */
7225 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7226 /* Reset the timesync system time value. */
7227 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7228 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7230 /* Enable system time for platforms where it isn't on by default. */
7231 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7232 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7233 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7235 ixgbe_start_timecounters(dev);
7237 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7238 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7239 (RTE_ETHER_TYPE_1588 |
7240 IXGBE_ETQF_FILTER_EN |
7243 /* Enable timestamping of received PTP packets. */
7244 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7245 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7246 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7248 /* Enable timestamping of transmitted PTP packets. */
7249 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7250 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7251 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7253 IXGBE_WRITE_FLUSH(hw);
7259 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7261 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7264 /* Disable timestamping of transmitted PTP packets. */
7265 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7266 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7267 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7269 /* Disable timestamping of received PTP packets. */
7270 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7271 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7272 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7274 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7275 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7277 /* Stop incrementating the System Time registers. */
7278 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7284 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7285 struct timespec *timestamp,
7286 uint32_t flags __rte_unused)
7288 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7289 struct ixgbe_adapter *adapter = dev->data->dev_private;
7290 uint32_t tsync_rxctl;
7291 uint64_t rx_tstamp_cycles;
7294 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7295 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7298 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7299 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7300 *timestamp = rte_ns_to_timespec(ns);
7306 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7307 struct timespec *timestamp)
7309 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7310 struct ixgbe_adapter *adapter = dev->data->dev_private;
7311 uint32_t tsync_txctl;
7312 uint64_t tx_tstamp_cycles;
7315 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7316 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7319 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7320 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7321 *timestamp = rte_ns_to_timespec(ns);
7327 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7329 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7332 const struct reg_info *reg_group;
7333 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7334 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7336 while ((reg_group = reg_set[g_ind++]))
7337 count += ixgbe_regs_group_count(reg_group);
7343 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7347 const struct reg_info *reg_group;
7349 while ((reg_group = ixgbevf_regs[g_ind++]))
7350 count += ixgbe_regs_group_count(reg_group);
7356 ixgbe_get_regs(struct rte_eth_dev *dev,
7357 struct rte_dev_reg_info *regs)
7359 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7360 uint32_t *data = regs->data;
7363 const struct reg_info *reg_group;
7364 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7365 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7368 regs->length = ixgbe_get_reg_length(dev);
7369 regs->width = sizeof(uint32_t);
7373 /* Support only full register dump */
7374 if ((regs->length == 0) ||
7375 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7376 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7378 while ((reg_group = reg_set[g_ind++]))
7379 count += ixgbe_read_regs_group(dev, &data[count],
7388 ixgbevf_get_regs(struct rte_eth_dev *dev,
7389 struct rte_dev_reg_info *regs)
7391 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7392 uint32_t *data = regs->data;
7395 const struct reg_info *reg_group;
7398 regs->length = ixgbevf_get_reg_length(dev);
7399 regs->width = sizeof(uint32_t);
7403 /* Support only full register dump */
7404 if ((regs->length == 0) ||
7405 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7406 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7408 while ((reg_group = ixgbevf_regs[g_ind++]))
7409 count += ixgbe_read_regs_group(dev, &data[count],
7418 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7420 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7422 /* Return unit is byte count */
7423 return hw->eeprom.word_size * 2;
7427 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7428 struct rte_dev_eeprom_info *in_eeprom)
7430 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7431 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7432 uint16_t *data = in_eeprom->data;
7435 first = in_eeprom->offset >> 1;
7436 length = in_eeprom->length >> 1;
7437 if ((first > hw->eeprom.word_size) ||
7438 ((first + length) > hw->eeprom.word_size))
7441 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7443 return eeprom->ops.read_buffer(hw, first, length, data);
7447 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7448 struct rte_dev_eeprom_info *in_eeprom)
7450 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7451 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7452 uint16_t *data = in_eeprom->data;
7455 first = in_eeprom->offset >> 1;
7456 length = in_eeprom->length >> 1;
7457 if ((first > hw->eeprom.word_size) ||
7458 ((first + length) > hw->eeprom.word_size))
7461 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7463 return eeprom->ops.write_buffer(hw, first, length, data);
7467 ixgbe_get_module_info(struct rte_eth_dev *dev,
7468 struct rte_eth_dev_module_info *modinfo)
7470 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7472 uint8_t sff8472_rev, addr_mode;
7473 bool page_swap = false;
7475 /* Check whether we support SFF-8472 or not */
7476 status = hw->phy.ops.read_i2c_eeprom(hw,
7477 IXGBE_SFF_SFF_8472_COMP,
7482 /* addressing mode is not supported */
7483 status = hw->phy.ops.read_i2c_eeprom(hw,
7484 IXGBE_SFF_SFF_8472_SWAP,
7489 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7491 "Address change required to access page 0xA2, "
7492 "but not supported. Please report the module "
7493 "type to the driver maintainers.");
7497 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7498 /* We have a SFP, but it does not support SFF-8472 */
7499 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7500 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7502 /* We have a SFP which supports a revision of SFF-8472. */
7503 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7504 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7511 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7512 struct rte_dev_eeprom_info *info)
7514 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7515 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7516 uint8_t databyte = 0xFF;
7517 uint8_t *data = info->data;
7520 if (info->length == 0)
7523 for (i = info->offset; i < info->offset + info->length; i++) {
7524 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7525 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7527 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7532 data[i - info->offset] = databyte;
7539 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7541 case ixgbe_mac_X550:
7542 case ixgbe_mac_X550EM_x:
7543 case ixgbe_mac_X550EM_a:
7544 return ETH_RSS_RETA_SIZE_512;
7545 case ixgbe_mac_X550_vf:
7546 case ixgbe_mac_X550EM_x_vf:
7547 case ixgbe_mac_X550EM_a_vf:
7548 return ETH_RSS_RETA_SIZE_64;
7549 case ixgbe_mac_X540_vf:
7550 case ixgbe_mac_82599_vf:
7553 return ETH_RSS_RETA_SIZE_128;
7558 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7560 case ixgbe_mac_X550:
7561 case ixgbe_mac_X550EM_x:
7562 case ixgbe_mac_X550EM_a:
7563 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7564 return IXGBE_RETA(reta_idx >> 2);
7566 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7567 case ixgbe_mac_X550_vf:
7568 case ixgbe_mac_X550EM_x_vf:
7569 case ixgbe_mac_X550EM_a_vf:
7570 return IXGBE_VFRETA(reta_idx >> 2);
7572 return IXGBE_RETA(reta_idx >> 2);
7577 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7579 case ixgbe_mac_X550_vf:
7580 case ixgbe_mac_X550EM_x_vf:
7581 case ixgbe_mac_X550EM_a_vf:
7582 return IXGBE_VFMRQC;
7589 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7591 case ixgbe_mac_X550_vf:
7592 case ixgbe_mac_X550EM_x_vf:
7593 case ixgbe_mac_X550EM_a_vf:
7594 return IXGBE_VFRSSRK(i);
7596 return IXGBE_RSSRK(i);
7601 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7603 case ixgbe_mac_82599_vf:
7604 case ixgbe_mac_X540_vf:
7612 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7613 struct rte_eth_dcb_info *dcb_info)
7615 struct ixgbe_dcb_config *dcb_config =
7616 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7617 struct ixgbe_dcb_tc_config *tc;
7618 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7622 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7623 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7625 dcb_info->nb_tcs = 1;
7627 tc_queue = &dcb_info->tc_queue;
7628 nb_tcs = dcb_info->nb_tcs;
7630 if (dcb_config->vt_mode) { /* vt is enabled*/
7631 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7632 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7633 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7634 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7635 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7636 for (j = 0; j < nb_tcs; j++) {
7637 tc_queue->tc_rxq[0][j].base = j;
7638 tc_queue->tc_rxq[0][j].nb_queue = 1;
7639 tc_queue->tc_txq[0][j].base = j;
7640 tc_queue->tc_txq[0][j].nb_queue = 1;
7643 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7644 for (j = 0; j < nb_tcs; j++) {
7645 tc_queue->tc_rxq[i][j].base =
7647 tc_queue->tc_rxq[i][j].nb_queue = 1;
7648 tc_queue->tc_txq[i][j].base =
7650 tc_queue->tc_txq[i][j].nb_queue = 1;
7654 } else { /* vt is disabled*/
7655 struct rte_eth_dcb_rx_conf *rx_conf =
7656 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7657 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7658 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7659 if (dcb_info->nb_tcs == ETH_4_TCS) {
7660 for (i = 0; i < dcb_info->nb_tcs; i++) {
7661 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7662 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7664 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7665 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7666 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7667 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7668 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7669 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7670 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7671 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7672 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7673 for (i = 0; i < dcb_info->nb_tcs; i++) {
7674 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7675 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7677 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7678 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7679 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7680 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7681 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7682 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7683 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7684 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7685 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7686 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7687 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7688 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7689 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7690 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7691 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7692 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7695 for (i = 0; i < dcb_info->nb_tcs; i++) {
7696 tc = &dcb_config->tc_config[i];
7697 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7702 /* Update e-tag ether type */
7704 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7705 uint16_t ether_type)
7707 uint32_t etag_etype;
7709 if (hw->mac.type != ixgbe_mac_X550 &&
7710 hw->mac.type != ixgbe_mac_X550EM_x &&
7711 hw->mac.type != ixgbe_mac_X550EM_a) {
7715 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7716 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7717 etag_etype |= ether_type;
7718 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7719 IXGBE_WRITE_FLUSH(hw);
7724 /* Config l2 tunnel ether type */
7726 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7727 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7730 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7731 struct ixgbe_l2_tn_info *l2_tn_info =
7732 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7734 if (l2_tunnel == NULL)
7737 switch (l2_tunnel->l2_tunnel_type) {
7738 case RTE_L2_TUNNEL_TYPE_E_TAG:
7739 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7740 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7743 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7751 /* Enable e-tag tunnel */
7753 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7755 uint32_t etag_etype;
7757 if (hw->mac.type != ixgbe_mac_X550 &&
7758 hw->mac.type != ixgbe_mac_X550EM_x &&
7759 hw->mac.type != ixgbe_mac_X550EM_a) {
7763 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7764 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7765 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7766 IXGBE_WRITE_FLUSH(hw);
7771 /* Enable l2 tunnel */
7773 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7774 enum rte_eth_tunnel_type l2_tunnel_type)
7777 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7778 struct ixgbe_l2_tn_info *l2_tn_info =
7779 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7781 switch (l2_tunnel_type) {
7782 case RTE_L2_TUNNEL_TYPE_E_TAG:
7783 l2_tn_info->e_tag_en = TRUE;
7784 ret = ixgbe_e_tag_enable(hw);
7787 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7795 /* Disable e-tag tunnel */
7797 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7799 uint32_t etag_etype;
7801 if (hw->mac.type != ixgbe_mac_X550 &&
7802 hw->mac.type != ixgbe_mac_X550EM_x &&
7803 hw->mac.type != ixgbe_mac_X550EM_a) {
7807 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7808 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7809 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7810 IXGBE_WRITE_FLUSH(hw);
7815 /* Disable l2 tunnel */
7817 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7818 enum rte_eth_tunnel_type l2_tunnel_type)
7821 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7822 struct ixgbe_l2_tn_info *l2_tn_info =
7823 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7825 switch (l2_tunnel_type) {
7826 case RTE_L2_TUNNEL_TYPE_E_TAG:
7827 l2_tn_info->e_tag_en = FALSE;
7828 ret = ixgbe_e_tag_disable(hw);
7831 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7840 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7841 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7844 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7845 uint32_t i, rar_entries;
7846 uint32_t rar_low, rar_high;
7848 if (hw->mac.type != ixgbe_mac_X550 &&
7849 hw->mac.type != ixgbe_mac_X550EM_x &&
7850 hw->mac.type != ixgbe_mac_X550EM_a) {
7854 rar_entries = ixgbe_get_num_rx_addrs(hw);
7856 for (i = 1; i < rar_entries; i++) {
7857 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7858 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7859 if ((rar_high & IXGBE_RAH_AV) &&
7860 (rar_high & IXGBE_RAH_ADTYPE) &&
7861 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7862 l2_tunnel->tunnel_id)) {
7863 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7864 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7866 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7876 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7877 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7880 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7881 uint32_t i, rar_entries;
7882 uint32_t rar_low, rar_high;
7884 if (hw->mac.type != ixgbe_mac_X550 &&
7885 hw->mac.type != ixgbe_mac_X550EM_x &&
7886 hw->mac.type != ixgbe_mac_X550EM_a) {
7890 /* One entry for one tunnel. Try to remove potential existing entry. */
7891 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7893 rar_entries = ixgbe_get_num_rx_addrs(hw);
7895 for (i = 1; i < rar_entries; i++) {
7896 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7897 if (rar_high & IXGBE_RAH_AV) {
7900 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7901 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7902 rar_low = l2_tunnel->tunnel_id;
7904 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7905 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7911 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7912 " Please remove a rule before adding a new one.");
7916 static inline struct ixgbe_l2_tn_filter *
7917 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7918 struct ixgbe_l2_tn_key *key)
7922 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7926 return l2_tn_info->hash_map[ret];
7930 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7931 struct ixgbe_l2_tn_filter *l2_tn_filter)
7935 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7936 &l2_tn_filter->key);
7940 "Failed to insert L2 tunnel filter"
7941 " to hash table %d!",
7946 l2_tn_info->hash_map[ret] = l2_tn_filter;
7948 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7954 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7955 struct ixgbe_l2_tn_key *key)
7958 struct ixgbe_l2_tn_filter *l2_tn_filter;
7960 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7964 "No such L2 tunnel filter to delete %d!",
7969 l2_tn_filter = l2_tn_info->hash_map[ret];
7970 l2_tn_info->hash_map[ret] = NULL;
7972 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7973 rte_free(l2_tn_filter);
7978 /* Add l2 tunnel filter */
7980 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7981 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7985 struct ixgbe_l2_tn_info *l2_tn_info =
7986 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7987 struct ixgbe_l2_tn_key key;
7988 struct ixgbe_l2_tn_filter *node;
7991 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7992 key.tn_id = l2_tunnel->tunnel_id;
7994 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7998 "The L2 tunnel filter already exists!");
8002 node = rte_zmalloc("ixgbe_l2_tn",
8003 sizeof(struct ixgbe_l2_tn_filter),
8008 rte_memcpy(&node->key,
8010 sizeof(struct ixgbe_l2_tn_key));
8011 node->pool = l2_tunnel->pool;
8012 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8019 switch (l2_tunnel->l2_tunnel_type) {
8020 case RTE_L2_TUNNEL_TYPE_E_TAG:
8021 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8024 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8029 if ((!restore) && (ret < 0))
8030 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8035 /* Delete l2 tunnel filter */
8037 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8038 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8041 struct ixgbe_l2_tn_info *l2_tn_info =
8042 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8043 struct ixgbe_l2_tn_key key;
8045 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8046 key.tn_id = l2_tunnel->tunnel_id;
8047 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8051 switch (l2_tunnel->l2_tunnel_type) {
8052 case RTE_L2_TUNNEL_TYPE_E_TAG:
8053 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8056 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8065 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8066 * @dev: pointer to rte_eth_dev structure
8067 * @filter_op:operation will be taken.
8068 * @arg: a pointer to specific structure corresponding to the filter_op
8071 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8072 enum rte_filter_op filter_op,
8077 if (filter_op == RTE_ETH_FILTER_NOP)
8081 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8086 switch (filter_op) {
8087 case RTE_ETH_FILTER_ADD:
8088 ret = ixgbe_dev_l2_tunnel_filter_add
8090 (struct rte_eth_l2_tunnel_conf *)arg,
8093 case RTE_ETH_FILTER_DELETE:
8094 ret = ixgbe_dev_l2_tunnel_filter_del
8096 (struct rte_eth_l2_tunnel_conf *)arg);
8099 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8107 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8111 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8113 if (hw->mac.type != ixgbe_mac_X550 &&
8114 hw->mac.type != ixgbe_mac_X550EM_x &&
8115 hw->mac.type != ixgbe_mac_X550EM_a) {
8119 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8120 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8122 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8123 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8128 /* Enable l2 tunnel forwarding */
8130 ixgbe_dev_l2_tunnel_forwarding_enable
8131 (struct rte_eth_dev *dev,
8132 enum rte_eth_tunnel_type l2_tunnel_type)
8134 struct ixgbe_l2_tn_info *l2_tn_info =
8135 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8138 switch (l2_tunnel_type) {
8139 case RTE_L2_TUNNEL_TYPE_E_TAG:
8140 l2_tn_info->e_tag_fwd_en = TRUE;
8141 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8144 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8152 /* Disable l2 tunnel forwarding */
8154 ixgbe_dev_l2_tunnel_forwarding_disable
8155 (struct rte_eth_dev *dev,
8156 enum rte_eth_tunnel_type l2_tunnel_type)
8158 struct ixgbe_l2_tn_info *l2_tn_info =
8159 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8162 switch (l2_tunnel_type) {
8163 case RTE_L2_TUNNEL_TYPE_E_TAG:
8164 l2_tn_info->e_tag_fwd_en = FALSE;
8165 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8168 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8177 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8178 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8181 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8183 uint32_t vmtir, vmvir;
8184 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8186 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8188 "VF id %u should be less than %u",
8194 if (hw->mac.type != ixgbe_mac_X550 &&
8195 hw->mac.type != ixgbe_mac_X550EM_x &&
8196 hw->mac.type != ixgbe_mac_X550EM_a) {
8201 vmtir = l2_tunnel->tunnel_id;
8205 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8207 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8208 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8210 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8211 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8216 /* Enable l2 tunnel tag insertion */
8218 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8219 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8223 switch (l2_tunnel->l2_tunnel_type) {
8224 case RTE_L2_TUNNEL_TYPE_E_TAG:
8225 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8228 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8236 /* Disable l2 tunnel tag insertion */
8238 ixgbe_dev_l2_tunnel_insertion_disable
8239 (struct rte_eth_dev *dev,
8240 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8244 switch (l2_tunnel->l2_tunnel_type) {
8245 case RTE_L2_TUNNEL_TYPE_E_TAG:
8246 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8249 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8258 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8263 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8265 if (hw->mac.type != ixgbe_mac_X550 &&
8266 hw->mac.type != ixgbe_mac_X550EM_x &&
8267 hw->mac.type != ixgbe_mac_X550EM_a) {
8271 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8273 qde |= IXGBE_QDE_STRIP_TAG;
8275 qde &= ~IXGBE_QDE_STRIP_TAG;
8276 qde &= ~IXGBE_QDE_READ;
8277 qde |= IXGBE_QDE_WRITE;
8278 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8283 /* Enable l2 tunnel tag stripping */
8285 ixgbe_dev_l2_tunnel_stripping_enable
8286 (struct rte_eth_dev *dev,
8287 enum rte_eth_tunnel_type l2_tunnel_type)
8291 switch (l2_tunnel_type) {
8292 case RTE_L2_TUNNEL_TYPE_E_TAG:
8293 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8296 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8304 /* Disable l2 tunnel tag stripping */
8306 ixgbe_dev_l2_tunnel_stripping_disable
8307 (struct rte_eth_dev *dev,
8308 enum rte_eth_tunnel_type l2_tunnel_type)
8312 switch (l2_tunnel_type) {
8313 case RTE_L2_TUNNEL_TYPE_E_TAG:
8314 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8317 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8325 /* Enable/disable l2 tunnel offload functions */
8327 ixgbe_dev_l2_tunnel_offload_set
8328 (struct rte_eth_dev *dev,
8329 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8335 if (l2_tunnel == NULL)
8339 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8341 ret = ixgbe_dev_l2_tunnel_enable(
8343 l2_tunnel->l2_tunnel_type);
8345 ret = ixgbe_dev_l2_tunnel_disable(
8347 l2_tunnel->l2_tunnel_type);
8350 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8352 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8356 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8361 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8363 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8365 l2_tunnel->l2_tunnel_type);
8367 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8369 l2_tunnel->l2_tunnel_type);
8372 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8374 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8376 l2_tunnel->l2_tunnel_type);
8378 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8380 l2_tunnel->l2_tunnel_type);
8387 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8390 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8391 IXGBE_WRITE_FLUSH(hw);
8396 /* There's only one register for VxLAN UDP port.
8397 * So, we cannot add several ports. Will update it.
8400 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8404 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8408 return ixgbe_update_vxlan_port(hw, port);
8411 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8412 * UDP port, it must have a value.
8413 * So, will reset it to the original value 0.
8416 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8421 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8423 if (cur_port != port) {
8424 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8428 return ixgbe_update_vxlan_port(hw, 0);
8431 /* Add UDP tunneling port */
8433 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8434 struct rte_eth_udp_tunnel *udp_tunnel)
8437 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8439 if (hw->mac.type != ixgbe_mac_X550 &&
8440 hw->mac.type != ixgbe_mac_X550EM_x &&
8441 hw->mac.type != ixgbe_mac_X550EM_a) {
8445 if (udp_tunnel == NULL)
8448 switch (udp_tunnel->prot_type) {
8449 case RTE_TUNNEL_TYPE_VXLAN:
8450 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8453 case RTE_TUNNEL_TYPE_GENEVE:
8454 case RTE_TUNNEL_TYPE_TEREDO:
8455 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8460 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8468 /* Remove UDP tunneling port */
8470 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8471 struct rte_eth_udp_tunnel *udp_tunnel)
8474 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8476 if (hw->mac.type != ixgbe_mac_X550 &&
8477 hw->mac.type != ixgbe_mac_X550EM_x &&
8478 hw->mac.type != ixgbe_mac_X550EM_a) {
8482 if (udp_tunnel == NULL)
8485 switch (udp_tunnel->prot_type) {
8486 case RTE_TUNNEL_TYPE_VXLAN:
8487 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8489 case RTE_TUNNEL_TYPE_GENEVE:
8490 case RTE_TUNNEL_TYPE_TEREDO:
8491 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8495 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8504 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8506 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8509 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8513 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8525 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8527 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8530 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8534 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8546 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8548 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8550 int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8552 switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8556 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8568 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8570 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8573 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8577 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8588 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8590 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8593 /* peek the message first */
8594 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8596 /* PF reset VF event */
8597 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8598 /* dummy mbx read to ack pf */
8599 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8601 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8607 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8610 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8611 struct ixgbe_interrupt *intr =
8612 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8613 ixgbevf_intr_disable(dev);
8615 /* read-on-clear nic registers here */
8616 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8619 /* only one misc vector supported - mailbox */
8620 eicr &= IXGBE_VTEICR_MASK;
8621 if (eicr == IXGBE_MISC_VEC_ID)
8622 intr->flags |= IXGBE_FLAG_MAILBOX;
8628 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8630 struct ixgbe_interrupt *intr =
8631 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8633 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8634 ixgbevf_mbx_process(dev);
8635 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8638 ixgbevf_intr_enable(dev);
8644 ixgbevf_dev_interrupt_handler(void *param)
8646 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8648 ixgbevf_dev_interrupt_get_status(dev);
8649 ixgbevf_dev_interrupt_action(dev);
8653 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8654 * @hw: pointer to hardware structure
8656 * Stops the transmit data path and waits for the HW to internally empty
8657 * the Tx security block
8659 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8661 #define IXGBE_MAX_SECTX_POLL 40
8666 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8667 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8668 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8669 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8670 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8671 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8673 /* Use interrupt-safe sleep just in case */
8677 /* For informational purposes only */
8678 if (i >= IXGBE_MAX_SECTX_POLL)
8679 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8680 "path fully disabled. Continuing with init.");
8682 return IXGBE_SUCCESS;
8686 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8687 * @hw: pointer to hardware structure
8689 * Enables the transmit data path.
8691 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8695 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8696 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8697 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8698 IXGBE_WRITE_FLUSH(hw);
8700 return IXGBE_SUCCESS;
8703 /* restore n-tuple filter */
8705 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8707 struct ixgbe_filter_info *filter_info =
8708 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8709 struct ixgbe_5tuple_filter *node;
8711 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8712 ixgbe_inject_5tuple_filter(dev, node);
8716 /* restore ethernet type filter */
8718 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8720 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8721 struct ixgbe_filter_info *filter_info =
8722 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8725 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8726 if (filter_info->ethertype_mask & (1 << i)) {
8727 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8728 filter_info->ethertype_filters[i].etqf);
8729 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8730 filter_info->ethertype_filters[i].etqs);
8731 IXGBE_WRITE_FLUSH(hw);
8736 /* restore SYN filter */
8738 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8740 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8741 struct ixgbe_filter_info *filter_info =
8742 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8745 synqf = filter_info->syn_info;
8747 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8748 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8749 IXGBE_WRITE_FLUSH(hw);
8753 /* restore L2 tunnel filter */
8755 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8757 struct ixgbe_l2_tn_info *l2_tn_info =
8758 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8759 struct ixgbe_l2_tn_filter *node;
8760 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8762 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8763 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8764 l2_tn_conf.tunnel_id = node->key.tn_id;
8765 l2_tn_conf.pool = node->pool;
8766 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8770 /* restore rss filter */
8772 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8774 struct ixgbe_filter_info *filter_info =
8775 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8777 if (filter_info->rss_info.conf.queue_num)
8778 ixgbe_config_rss_filter(dev,
8779 &filter_info->rss_info, TRUE);
8783 ixgbe_filter_restore(struct rte_eth_dev *dev)
8785 ixgbe_ntuple_filter_restore(dev);
8786 ixgbe_ethertype_filter_restore(dev);
8787 ixgbe_syn_filter_restore(dev);
8788 ixgbe_fdir_filter_restore(dev);
8789 ixgbe_l2_tn_filter_restore(dev);
8790 ixgbe_rss_filter_restore(dev);
8796 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8798 struct ixgbe_l2_tn_info *l2_tn_info =
8799 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8800 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8802 if (l2_tn_info->e_tag_en)
8803 (void)ixgbe_e_tag_enable(hw);
8805 if (l2_tn_info->e_tag_fwd_en)
8806 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8808 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8811 /* remove all the n-tuple filters */
8813 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8815 struct ixgbe_filter_info *filter_info =
8816 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8817 struct ixgbe_5tuple_filter *p_5tuple;
8819 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8820 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8823 /* remove all the ether type filters */
8825 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8827 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8828 struct ixgbe_filter_info *filter_info =
8829 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8832 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8833 if (filter_info->ethertype_mask & (1 << i) &&
8834 !filter_info->ethertype_filters[i].conf) {
8835 (void)ixgbe_ethertype_filter_remove(filter_info,
8837 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8838 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8839 IXGBE_WRITE_FLUSH(hw);
8844 /* remove the SYN filter */
8846 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8848 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8849 struct ixgbe_filter_info *filter_info =
8850 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8852 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8853 filter_info->syn_info = 0;
8855 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8856 IXGBE_WRITE_FLUSH(hw);
8860 /* remove all the L2 tunnel filters */
8862 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8864 struct ixgbe_l2_tn_info *l2_tn_info =
8865 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8866 struct ixgbe_l2_tn_filter *l2_tn_filter;
8867 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8870 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8871 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8872 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8873 l2_tn_conf.pool = l2_tn_filter->pool;
8874 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8883 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8884 struct ixgbe_macsec_setting *macsec_setting)
8886 struct ixgbe_macsec_setting *macsec =
8887 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8889 macsec->offload_en = macsec_setting->offload_en;
8890 macsec->encrypt_en = macsec_setting->encrypt_en;
8891 macsec->replayprotect_en = macsec_setting->replayprotect_en;
8895 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8897 struct ixgbe_macsec_setting *macsec =
8898 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8900 macsec->offload_en = 0;
8901 macsec->encrypt_en = 0;
8902 macsec->replayprotect_en = 0;
8906 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8907 struct ixgbe_macsec_setting *macsec_setting)
8909 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8911 uint8_t en = macsec_setting->encrypt_en;
8912 uint8_t rp = macsec_setting->replayprotect_en;
8916 * As no ixgbe_disable_sec_rx_path equivalent is
8917 * implemented for tx in the base code, and we are
8918 * not allowed to modify the base code in DPDK, so
8919 * just call the hand-written one directly for now.
8920 * The hardware support has been checked by
8921 * ixgbe_disable_sec_rx_path().
8923 ixgbe_disable_sec_tx_path_generic(hw);
8925 /* Enable Ethernet CRC (required by MACsec offload) */
8926 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8927 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8928 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8930 /* Enable the TX and RX crypto engines */
8931 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8932 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8933 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8935 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8936 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8937 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8939 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8940 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8942 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8944 /* Enable SA lookup */
8945 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8946 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8947 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8948 IXGBE_LSECTXCTRL_AUTH;
8949 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8950 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8951 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8952 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8954 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8955 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8956 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8957 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8959 ctrl |= IXGBE_LSECRXCTRL_RP;
8961 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8962 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8964 /* Start the data paths */
8965 ixgbe_enable_sec_rx_path(hw);
8968 * As no ixgbe_enable_sec_rx_path equivalent is
8969 * implemented for tx in the base code, and we are
8970 * not allowed to modify the base code in DPDK, so
8971 * just call the hand-written one directly for now.
8973 ixgbe_enable_sec_tx_path_generic(hw);
8977 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8979 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8984 * As no ixgbe_disable_sec_rx_path equivalent is
8985 * implemented for tx in the base code, and we are
8986 * not allowed to modify the base code in DPDK, so
8987 * just call the hand-written one directly for now.
8988 * The hardware support has been checked by
8989 * ixgbe_disable_sec_rx_path().
8991 ixgbe_disable_sec_tx_path_generic(hw);
8993 /* Disable the TX and RX crypto engines */
8994 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8995 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8996 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8998 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8999 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9000 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9002 /* Disable SA lookup */
9003 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9004 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9005 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9006 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9008 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9009 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9010 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9011 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9013 /* Start the data paths */
9014 ixgbe_enable_sec_rx_path(hw);
9017 * As no ixgbe_enable_sec_rx_path equivalent is
9018 * implemented for tx in the base code, and we are
9019 * not allowed to modify the base code in DPDK, so
9020 * just call the hand-written one directly for now.
9022 ixgbe_enable_sec_tx_path_generic(hw);
9025 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9026 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9027 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9028 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9029 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9030 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9031 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9032 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9034 RTE_INIT(ixgbe_init_log)
9036 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
9037 if (ixgbe_logtype_init >= 0)
9038 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
9039 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
9040 if (ixgbe_logtype_driver >= 0)
9041 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
9042 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9043 ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
9044 if (ixgbe_logtype_rx >= 0)
9045 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
9048 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9049 ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9050 if (ixgbe_logtype_tx >= 0)
9051 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9054 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9055 ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9056 if (ixgbe_logtype_tx_free >= 0)
9057 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);