4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
65 #include "ixgbe_logs.h"
66 #include "base/ixgbe_api.h"
67 #include "base/ixgbe_vf.h"
68 #include "base/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
72 #include "base/ixgbe_type.h"
73 #include "base/ixgbe_phy.h"
74 #include "ixgbe_regs.h"
76 #include "rte_pmd_ixgbe.h"
79 * High threshold controlling when to start sending XOFF frames. Must be at
80 * least 8 bytes less than receive packet buffer size. This value is in units
83 #define IXGBE_FC_HI 0x80
86 * Low threshold controlling when to start sending XON frames. This value is
87 * in units of 1024 bytes.
89 #define IXGBE_FC_LO 0x40
91 /* Default minimum inter-interrupt interval for EITR configuration */
92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
94 /* Timer value included in XOFF frames. */
95 #define IXGBE_FC_PAUSE 0x680
97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
98 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
99 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
101 #define IXGBE_MMW_SIZE_DEFAULT 0x4
102 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
103 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
106 * Default values for RX/TX configuration
108 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
109 #define IXGBE_DEFAULT_RX_PTHRESH 8
110 #define IXGBE_DEFAULT_RX_HTHRESH 8
111 #define IXGBE_DEFAULT_RX_WTHRESH 0
113 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
114 #define IXGBE_DEFAULT_TX_PTHRESH 32
115 #define IXGBE_DEFAULT_TX_HTHRESH 0
116 #define IXGBE_DEFAULT_TX_WTHRESH 0
117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
119 /* Bit shift and mask */
120 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
121 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
122 #define IXGBE_8_BIT_WIDTH CHAR_BIT
123 #define IXGBE_8_BIT_MASK UINT8_MAX
125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
129 #define IXGBE_HKEY_MAX_INDEX 10
131 /* Additional timesync values. */
132 #define NSEC_PER_SEC 1000000000L
133 #define IXGBE_INCVAL_10GB 0x66666666
134 #define IXGBE_INCVAL_1GB 0x40000000
135 #define IXGBE_INCVAL_100 0x50000000
136 #define IXGBE_INCVAL_SHIFT_10GB 28
137 #define IXGBE_INCVAL_SHIFT_1GB 24
138 #define IXGBE_INCVAL_SHIFT_100 21
139 #define IXGBE_INCVAL_SHIFT_82599 7
140 #define IXGBE_INCPER_SHIFT_82599 24
142 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
144 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
146 #define DEFAULT_ETAG_ETYPE 0x893f
147 #define IXGBE_ETAG_ETYPE 0x00005084
148 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
149 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
150 #define IXGBE_RAH_ADTYPE 0x40000000
151 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
152 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
155 #define IXGBE_QDE_STRIP_TAG 0x00000004
156 #define IXGBE_VTEICR_MASK 0x07
158 enum ixgbevf_xcast_modes {
159 IXGBEVF_XCAST_MODE_NONE = 0,
160 IXGBEVF_XCAST_MODE_MULTI,
161 IXGBEVF_XCAST_MODE_ALLMULTI,
164 #define IXGBE_EXVET_VET_EXT_SHIFT 16
165 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
167 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
168 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
169 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
170 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
171 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
172 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
173 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
174 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
175 static int ixgbe_dev_start(struct rte_eth_dev *dev);
176 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
177 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
178 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
179 static void ixgbe_dev_close(struct rte_eth_dev *dev);
180 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
181 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
182 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
183 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
184 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
185 int wait_to_complete);
186 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
187 struct rte_eth_stats *stats);
188 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
189 struct rte_eth_xstat *xstats, unsigned n);
190 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
191 struct rte_eth_xstat *xstats, unsigned n);
192 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
193 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
194 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
195 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
196 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
197 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
198 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
202 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
204 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
205 struct rte_eth_dev_info *dev_info);
206 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
207 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
208 struct rte_eth_dev_info *dev_info);
209 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
211 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
212 uint16_t vlan_id, int on);
213 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
214 enum rte_vlan_type vlan_type,
216 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
217 uint16_t queue, bool on);
218 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
220 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
221 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
222 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
223 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
224 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
226 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
227 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
228 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
229 struct rte_eth_fc_conf *fc_conf);
230 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
231 struct rte_eth_fc_conf *fc_conf);
232 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
233 struct rte_eth_pfc_conf *pfc_conf);
234 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
235 struct rte_eth_rss_reta_entry64 *reta_conf,
237 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
238 struct rte_eth_rss_reta_entry64 *reta_conf,
240 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
241 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
242 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
243 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
244 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
245 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
246 struct rte_intr_handle *handle);
247 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
250 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
251 uint32_t index, uint32_t pool);
252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
254 struct ether_addr *mac_addr);
255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
256 static int is_ixgbe_pmd(const char *driver_name);
258 /* For Virtual Function support */
259 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
260 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
261 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
262 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
263 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
264 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
265 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
266 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
267 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
268 struct rte_eth_stats *stats);
269 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
270 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
271 uint16_t vlan_id, int on);
272 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
273 uint16_t queue, int on);
274 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
275 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
276 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
278 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
280 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
281 uint8_t queue, uint8_t msix_vector);
282 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
283 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
284 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
286 /* For Eth VMDQ APIs support */
287 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
288 ether_addr * mac_addr, uint8_t on);
289 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
291 struct rte_eth_mirror_conf *mirror_conf,
292 uint8_t rule_id, uint8_t on);
293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
300 uint8_t queue, uint8_t msix_vector);
301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
304 uint16_t queue_idx, uint16_t tx_rate);
306 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
307 struct ether_addr *mac_addr,
308 uint32_t index, uint32_t pool);
309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
311 struct ether_addr *mac_addr);
312 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
313 struct rte_eth_syn_filter *filter);
314 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
315 enum rte_filter_op filter_op,
317 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
318 struct ixgbe_5tuple_filter *filter);
319 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
320 struct ixgbe_5tuple_filter *filter);
321 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
322 enum rte_filter_op filter_op,
324 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
325 struct rte_eth_ntuple_filter *filter);
326 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
327 enum rte_filter_op filter_op,
329 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
330 struct rte_eth_ethertype_filter *filter);
331 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
332 enum rte_filter_type filter_type,
333 enum rte_filter_op filter_op,
335 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
337 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
338 struct ether_addr *mc_addr_set,
339 uint32_t nb_mc_addr);
340 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
341 struct rte_eth_dcb_info *dcb_info);
343 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
344 static int ixgbe_get_regs(struct rte_eth_dev *dev,
345 struct rte_dev_reg_info *regs);
346 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
347 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
348 struct rte_dev_eeprom_info *eeprom);
349 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
350 struct rte_dev_eeprom_info *eeprom);
352 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
353 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
354 struct rte_dev_reg_info *regs);
356 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
357 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
358 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
359 struct timespec *timestamp,
361 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
362 struct timespec *timestamp);
363 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
364 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
365 struct timespec *timestamp);
366 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
367 const struct timespec *timestamp);
368 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
371 static int ixgbe_dev_l2_tunnel_eth_type_conf
372 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
373 static int ixgbe_dev_l2_tunnel_offload_set
374 (struct rte_eth_dev *dev,
375 struct rte_eth_l2_tunnel_conf *l2_tunnel,
378 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
379 enum rte_filter_op filter_op,
382 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
383 struct rte_eth_udp_tunnel *udp_tunnel);
384 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
385 struct rte_eth_udp_tunnel *udp_tunnel);
386 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
387 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
390 * Define VF Stats MACRO for Non "cleared on read" register
392 #define UPDATE_VF_STAT(reg, last, cur) \
394 uint32_t latest = IXGBE_READ_REG(hw, reg); \
395 cur += (latest - last) & UINT_MAX; \
399 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
401 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
402 u64 new_msb = IXGBE_READ_REG(hw, msb); \
403 u64 latest = ((new_msb << 32) | new_lsb); \
404 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
408 #define IXGBE_SET_HWSTRIP(h, q) do {\
409 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
410 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
411 (h)->bitmap[idx] |= 1 << bit;\
414 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
415 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
416 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
417 (h)->bitmap[idx] &= ~(1 << bit);\
420 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
421 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
422 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
423 (r) = (h)->bitmap[idx] >> bit & 1;\
427 * The set of PCI devices this driver supports
429 static const struct rte_pci_id pci_id_ixgbe_map[] = {
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
483 #ifdef RTE_NIC_BYPASS
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
486 { .vendor_id = 0, /* sentinel */ },
490 * The set of PCI devices this driver supports (for 82599 VF)
492 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
503 { .vendor_id = 0, /* sentinel */ },
506 static const struct rte_eth_desc_lim rx_desc_lim = {
507 .nb_max = IXGBE_MAX_RING_DESC,
508 .nb_min = IXGBE_MIN_RING_DESC,
509 .nb_align = IXGBE_RXD_ALIGN,
512 static const struct rte_eth_desc_lim tx_desc_lim = {
513 .nb_max = IXGBE_MAX_RING_DESC,
514 .nb_min = IXGBE_MIN_RING_DESC,
515 .nb_align = IXGBE_TXD_ALIGN,
516 .nb_seg_max = IXGBE_TX_MAX_SEG,
517 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
520 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
521 .dev_configure = ixgbe_dev_configure,
522 .dev_start = ixgbe_dev_start,
523 .dev_stop = ixgbe_dev_stop,
524 .dev_set_link_up = ixgbe_dev_set_link_up,
525 .dev_set_link_down = ixgbe_dev_set_link_down,
526 .dev_close = ixgbe_dev_close,
527 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
528 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
529 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
530 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
531 .link_update = ixgbe_dev_link_update,
532 .stats_get = ixgbe_dev_stats_get,
533 .xstats_get = ixgbe_dev_xstats_get,
534 .stats_reset = ixgbe_dev_stats_reset,
535 .xstats_reset = ixgbe_dev_xstats_reset,
536 .xstats_get_names = ixgbe_dev_xstats_get_names,
537 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
538 .fw_version_get = ixgbe_fw_version_get,
539 .dev_infos_get = ixgbe_dev_info_get,
540 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
541 .mtu_set = ixgbe_dev_mtu_set,
542 .vlan_filter_set = ixgbe_vlan_filter_set,
543 .vlan_tpid_set = ixgbe_vlan_tpid_set,
544 .vlan_offload_set = ixgbe_vlan_offload_set,
545 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
546 .rx_queue_start = ixgbe_dev_rx_queue_start,
547 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
548 .tx_queue_start = ixgbe_dev_tx_queue_start,
549 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
550 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
551 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
552 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
553 .rx_queue_release = ixgbe_dev_rx_queue_release,
554 .rx_queue_count = ixgbe_dev_rx_queue_count,
555 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
556 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
557 .tx_queue_release = ixgbe_dev_tx_queue_release,
558 .dev_led_on = ixgbe_dev_led_on,
559 .dev_led_off = ixgbe_dev_led_off,
560 .flow_ctrl_get = ixgbe_flow_ctrl_get,
561 .flow_ctrl_set = ixgbe_flow_ctrl_set,
562 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
563 .mac_addr_add = ixgbe_add_rar,
564 .mac_addr_remove = ixgbe_remove_rar,
565 .mac_addr_set = ixgbe_set_default_mac_addr,
566 .uc_hash_table_set = ixgbe_uc_hash_table_set,
567 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
568 .mirror_rule_set = ixgbe_mirror_rule_set,
569 .mirror_rule_reset = ixgbe_mirror_rule_reset,
570 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
571 .reta_update = ixgbe_dev_rss_reta_update,
572 .reta_query = ixgbe_dev_rss_reta_query,
573 #ifdef RTE_NIC_BYPASS
574 .bypass_init = ixgbe_bypass_init,
575 .bypass_state_set = ixgbe_bypass_state_store,
576 .bypass_state_show = ixgbe_bypass_state_show,
577 .bypass_event_set = ixgbe_bypass_event_store,
578 .bypass_event_show = ixgbe_bypass_event_show,
579 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
580 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
581 .bypass_ver_show = ixgbe_bypass_ver_show,
582 .bypass_wd_reset = ixgbe_bypass_wd_reset,
583 #endif /* RTE_NIC_BYPASS */
584 .rss_hash_update = ixgbe_dev_rss_hash_update,
585 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
586 .filter_ctrl = ixgbe_dev_filter_ctrl,
587 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
588 .rxq_info_get = ixgbe_rxq_info_get,
589 .txq_info_get = ixgbe_txq_info_get,
590 .timesync_enable = ixgbe_timesync_enable,
591 .timesync_disable = ixgbe_timesync_disable,
592 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
593 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
594 .get_reg = ixgbe_get_regs,
595 .get_eeprom_length = ixgbe_get_eeprom_length,
596 .get_eeprom = ixgbe_get_eeprom,
597 .set_eeprom = ixgbe_set_eeprom,
598 .get_dcb_info = ixgbe_dev_get_dcb_info,
599 .timesync_adjust_time = ixgbe_timesync_adjust_time,
600 .timesync_read_time = ixgbe_timesync_read_time,
601 .timesync_write_time = ixgbe_timesync_write_time,
602 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
603 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
604 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
605 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
609 * dev_ops for virtual function, bare necessities for basic vf
610 * operation have been implemented
612 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
613 .dev_configure = ixgbevf_dev_configure,
614 .dev_start = ixgbevf_dev_start,
615 .dev_stop = ixgbevf_dev_stop,
616 .link_update = ixgbe_dev_link_update,
617 .stats_get = ixgbevf_dev_stats_get,
618 .xstats_get = ixgbevf_dev_xstats_get,
619 .stats_reset = ixgbevf_dev_stats_reset,
620 .xstats_reset = ixgbevf_dev_stats_reset,
621 .xstats_get_names = ixgbevf_dev_xstats_get_names,
622 .dev_close = ixgbevf_dev_close,
623 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
624 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
625 .dev_infos_get = ixgbevf_dev_info_get,
626 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
627 .mtu_set = ixgbevf_dev_set_mtu,
628 .vlan_filter_set = ixgbevf_vlan_filter_set,
629 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
630 .vlan_offload_set = ixgbevf_vlan_offload_set,
631 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
632 .rx_queue_release = ixgbe_dev_rx_queue_release,
633 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
634 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
635 .tx_queue_release = ixgbe_dev_tx_queue_release,
636 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
637 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
638 .mac_addr_add = ixgbevf_add_mac_addr,
639 .mac_addr_remove = ixgbevf_remove_mac_addr,
640 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
641 .rxq_info_get = ixgbe_rxq_info_get,
642 .txq_info_get = ixgbe_txq_info_get,
643 .mac_addr_set = ixgbevf_set_default_mac_addr,
644 .get_reg = ixgbevf_get_regs,
645 .reta_update = ixgbe_dev_rss_reta_update,
646 .reta_query = ixgbe_dev_rss_reta_query,
647 .rss_hash_update = ixgbe_dev_rss_hash_update,
648 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
651 /* store statistics names and its offset in stats structure */
652 struct rte_ixgbe_xstats_name_off {
653 char name[RTE_ETH_XSTATS_NAME_SIZE];
657 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
658 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
659 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
660 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
661 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
662 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
663 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
664 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
665 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
666 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
667 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
668 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
669 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
670 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
671 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
672 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
674 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
676 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
677 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
678 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
679 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
680 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
681 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
682 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
683 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
684 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
685 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
686 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
687 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
688 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
689 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
690 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
691 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
692 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
694 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
696 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
697 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
698 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
699 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
701 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
703 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
705 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
707 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
709 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
711 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
714 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
715 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
716 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
718 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
719 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
720 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
721 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
722 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
724 {"rx_fcoe_no_direct_data_placement_ext_buff",
725 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
727 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
729 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
731 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
733 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
735 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
738 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
739 sizeof(rte_ixgbe_stats_strings[0]))
741 /* MACsec statistics */
742 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
743 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
745 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
746 out_pkts_encrypted)},
747 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
748 out_pkts_protected)},
749 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
750 out_octets_encrypted)},
751 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
752 out_octets_protected)},
753 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
755 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
757 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
759 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
760 in_pkts_unknownsci)},
761 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
762 in_octets_decrypted)},
763 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
764 in_octets_validated)},
765 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
769 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
771 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
773 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
775 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
777 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
779 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
780 in_pkts_notusingsa)},
783 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
784 sizeof(rte_ixgbe_macsec_strings[0]))
786 /* Per-queue statistics */
787 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
788 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
789 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
790 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
791 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
794 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
795 sizeof(rte_ixgbe_rxq_strings[0]))
796 #define IXGBE_NB_RXQ_PRIO_VALUES 8
798 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
799 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
800 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
801 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
805 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
806 sizeof(rte_ixgbe_txq_strings[0]))
807 #define IXGBE_NB_TXQ_PRIO_VALUES 8
809 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
810 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
813 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
814 sizeof(rte_ixgbevf_stats_strings[0]))
817 * Atomically reads the link status information from global
818 * structure rte_eth_dev.
821 * - Pointer to the structure rte_eth_dev to read from.
822 * - Pointer to the buffer to be saved with the link status.
825 * - On success, zero.
826 * - On failure, negative value.
829 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
830 struct rte_eth_link *link)
832 struct rte_eth_link *dst = link;
833 struct rte_eth_link *src = &(dev->data->dev_link);
835 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
836 *(uint64_t *)src) == 0)
843 * Atomically writes the link status information into global
844 * structure rte_eth_dev.
847 * - Pointer to the structure rte_eth_dev to read from.
848 * - Pointer to the buffer to be saved with the link status.
851 * - On success, zero.
852 * - On failure, negative value.
855 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
856 struct rte_eth_link *link)
858 struct rte_eth_link *dst = &(dev->data->dev_link);
859 struct rte_eth_link *src = link;
861 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
862 *(uint64_t *)src) == 0)
869 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
872 ixgbe_is_sfp(struct ixgbe_hw *hw)
874 switch (hw->phy.type) {
875 case ixgbe_phy_sfp_avago:
876 case ixgbe_phy_sfp_ftl:
877 case ixgbe_phy_sfp_intel:
878 case ixgbe_phy_sfp_unknown:
879 case ixgbe_phy_sfp_passive_tyco:
880 case ixgbe_phy_sfp_passive_unknown:
887 static inline int32_t
888 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
893 status = ixgbe_reset_hw(hw);
895 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
896 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
897 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
898 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
899 IXGBE_WRITE_FLUSH(hw);
905 ixgbe_enable_intr(struct rte_eth_dev *dev)
907 struct ixgbe_interrupt *intr =
908 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
909 struct ixgbe_hw *hw =
910 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
912 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
913 IXGBE_WRITE_FLUSH(hw);
917 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
920 ixgbe_disable_intr(struct ixgbe_hw *hw)
922 PMD_INIT_FUNC_TRACE();
924 if (hw->mac.type == ixgbe_mac_82598EB) {
925 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
927 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
928 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
929 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
931 IXGBE_WRITE_FLUSH(hw);
935 * This function resets queue statistics mapping registers.
936 * From Niantic datasheet, Initialization of Statistics section:
937 * "...if software requires the queue counters, the RQSMR and TQSM registers
938 * must be re-programmed following a device reset.
941 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
945 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
946 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
947 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
953 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
958 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
959 #define NB_QMAP_FIELDS_PER_QSM_REG 4
960 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
962 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
963 struct ixgbe_stat_mapping_registers *stat_mappings =
964 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
965 uint32_t qsmr_mask = 0;
966 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
970 if ((hw->mac.type != ixgbe_mac_82599EB) &&
971 (hw->mac.type != ixgbe_mac_X540) &&
972 (hw->mac.type != ixgbe_mac_X550) &&
973 (hw->mac.type != ixgbe_mac_X550EM_x) &&
974 (hw->mac.type != ixgbe_mac_X550EM_a))
977 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
978 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
981 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
982 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
983 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
986 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
988 /* Now clear any previous stat_idx set */
989 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
991 stat_mappings->tqsm[n] &= ~clearing_mask;
993 stat_mappings->rqsmr[n] &= ~clearing_mask;
995 q_map = (uint32_t)stat_idx;
996 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
997 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
999 stat_mappings->tqsm[n] |= qsmr_mask;
1001 stat_mappings->rqsmr[n] |= qsmr_mask;
1003 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1004 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1005 queue_id, stat_idx);
1006 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1007 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1009 /* Now write the mapping in the appropriate register */
1011 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1012 stat_mappings->rqsmr[n], n);
1013 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1015 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1016 stat_mappings->tqsm[n], n);
1017 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1023 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1025 struct ixgbe_stat_mapping_registers *stat_mappings =
1026 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1027 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030 /* write whatever was in stat mapping table to the NIC */
1031 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1033 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1036 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1041 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1044 struct ixgbe_dcb_tc_config *tc;
1045 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1047 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1048 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1049 for (i = 0; i < dcb_max_tc; i++) {
1050 tc = &dcb_config->tc_config[i];
1051 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1052 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1053 (uint8_t)(100/dcb_max_tc + (i & 1));
1054 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1055 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1056 (uint8_t)(100/dcb_max_tc + (i & 1));
1057 tc->pfc = ixgbe_dcb_pfc_disabled;
1060 /* Initialize default user to priority mapping, UPx->TC0 */
1061 tc = &dcb_config->tc_config[0];
1062 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1063 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1064 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1065 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1066 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1068 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1069 dcb_config->pfc_mode_enable = false;
1070 dcb_config->vt_mode = true;
1071 dcb_config->round_robin_enable = false;
1072 /* support all DCB capabilities in 82599 */
1073 dcb_config->support.capabilities = 0xFF;
1075 /*we only support 4 Tcs for X540, X550 */
1076 if (hw->mac.type == ixgbe_mac_X540 ||
1077 hw->mac.type == ixgbe_mac_X550 ||
1078 hw->mac.type == ixgbe_mac_X550EM_x ||
1079 hw->mac.type == ixgbe_mac_X550EM_a) {
1080 dcb_config->num_tcs.pg_tcs = 4;
1081 dcb_config->num_tcs.pfc_tcs = 4;
1086 * Ensure that all locks are released before first NVM or PHY access
1089 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1094 * Phy lock should not fail in this early stage. If this is the case,
1095 * it is due to an improper exit of the application.
1096 * So force the release of the faulty lock. Release of common lock
1097 * is done automatically by swfw_sync function.
1099 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1100 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1101 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1103 ixgbe_release_swfw_semaphore(hw, mask);
1106 * These ones are more tricky since they are common to all ports; but
1107 * swfw_sync retries last long enough (1s) to be almost sure that if
1108 * lock can not be taken it is due to an improper lock of the
1111 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1112 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1113 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1115 ixgbe_release_swfw_semaphore(hw, mask);
1119 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1120 * It returns 0 on success.
1123 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1125 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1126 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1127 struct ixgbe_hw *hw =
1128 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1129 struct ixgbe_vfta *shadow_vfta =
1130 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1131 struct ixgbe_hwstrip *hwstrip =
1132 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1133 struct ixgbe_dcb_config *dcb_config =
1134 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1135 struct ixgbe_filter_info *filter_info =
1136 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1141 PMD_INIT_FUNC_TRACE();
1143 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1144 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1145 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1146 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1149 * For secondary processes, we don't initialise any further as primary
1150 * has already done this work. Only check we don't need a different
1151 * RX and TX function.
1153 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1154 struct ixgbe_tx_queue *txq;
1155 /* TX queue function in primary, set by last queue initialized
1156 * Tx queue may not initialized by primary process
1158 if (eth_dev->data->tx_queues) {
1159 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1160 ixgbe_set_tx_function(eth_dev, txq);
1162 /* Use default TX function if we get here */
1163 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1164 "Using default TX function.");
1167 ixgbe_set_rx_function(eth_dev);
1172 rte_eth_copy_pci_info(eth_dev, pci_dev);
1173 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1175 /* Vendor and Device ID need to be set before init of shared code */
1176 hw->device_id = pci_dev->id.device_id;
1177 hw->vendor_id = pci_dev->id.vendor_id;
1178 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1179 hw->allow_unsupported_sfp = 1;
1181 /* Initialize the shared code (base driver) */
1182 #ifdef RTE_NIC_BYPASS
1183 diag = ixgbe_bypass_init_shared_code(hw);
1185 diag = ixgbe_init_shared_code(hw);
1186 #endif /* RTE_NIC_BYPASS */
1188 if (diag != IXGBE_SUCCESS) {
1189 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1193 /* pick up the PCI bus settings for reporting later */
1194 ixgbe_get_bus_info(hw);
1196 /* Unlock any pending hardware semaphore */
1197 ixgbe_swfw_lock_reset(hw);
1199 /* Initialize DCB configuration*/
1200 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1201 ixgbe_dcb_init(hw, dcb_config);
1202 /* Get Hardware Flow Control setting */
1203 hw->fc.requested_mode = ixgbe_fc_full;
1204 hw->fc.current_mode = ixgbe_fc_full;
1205 hw->fc.pause_time = IXGBE_FC_PAUSE;
1206 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1207 hw->fc.low_water[i] = IXGBE_FC_LO;
1208 hw->fc.high_water[i] = IXGBE_FC_HI;
1210 hw->fc.send_xon = 1;
1212 /* Make sure we have a good EEPROM before we read from it */
1213 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1214 if (diag != IXGBE_SUCCESS) {
1215 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1219 #ifdef RTE_NIC_BYPASS
1220 diag = ixgbe_bypass_init_hw(hw);
1222 diag = ixgbe_init_hw(hw);
1223 #endif /* RTE_NIC_BYPASS */
1226 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1227 * is called too soon after the kernel driver unbinding/binding occurs.
1228 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1229 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1230 * also called. See ixgbe_identify_phy_82599(). The reason for the
1231 * failure is not known, and only occuts when virtualisation features
1232 * are disabled in the bios. A delay of 100ms was found to be enough by
1233 * trial-and-error, and is doubled to be safe.
1235 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1237 diag = ixgbe_init_hw(hw);
1240 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1241 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1242 "LOM. Please be aware there may be issues associated "
1243 "with your hardware.");
1244 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1245 "please contact your Intel or hardware representative "
1246 "who provided you with this hardware.");
1247 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1248 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1250 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1254 /* Reset the hw statistics */
1255 ixgbe_dev_stats_reset(eth_dev);
1257 /* disable interrupt */
1258 ixgbe_disable_intr(hw);
1260 /* reset mappings for queue statistics hw counters*/
1261 ixgbe_reset_qstat_mappings(hw);
1263 /* Allocate memory for storing MAC addresses */
1264 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1265 hw->mac.num_rar_entries, 0);
1266 if (eth_dev->data->mac_addrs == NULL) {
1268 "Failed to allocate %u bytes needed to store "
1270 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1273 /* Copy the permanent MAC address */
1274 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1275 ð_dev->data->mac_addrs[0]);
1277 /* Allocate memory for storing hash filter MAC addresses */
1278 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1279 IXGBE_VMDQ_NUM_UC_MAC, 0);
1280 if (eth_dev->data->hash_mac_addrs == NULL) {
1282 "Failed to allocate %d bytes needed to store MAC addresses",
1283 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1287 /* initialize the vfta */
1288 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1290 /* initialize the hw strip bitmap*/
1291 memset(hwstrip, 0, sizeof(*hwstrip));
1293 /* initialize PF if max_vfs not zero */
1294 ixgbe_pf_host_init(eth_dev);
1296 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1297 /* let hardware know driver is loaded */
1298 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1299 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1300 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1301 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1302 IXGBE_WRITE_FLUSH(hw);
1304 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1305 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1306 (int) hw->mac.type, (int) hw->phy.type,
1307 (int) hw->phy.sfp_type);
1309 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1310 (int) hw->mac.type, (int) hw->phy.type);
1312 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1313 eth_dev->data->port_id, pci_dev->id.vendor_id,
1314 pci_dev->id.device_id);
1316 rte_intr_callback_register(intr_handle,
1317 ixgbe_dev_interrupt_handler, eth_dev);
1319 /* enable uio/vfio intr/eventfd mapping */
1320 rte_intr_enable(intr_handle);
1322 /* enable support intr */
1323 ixgbe_enable_intr(eth_dev);
1325 /* initialize filter info */
1326 memset(filter_info, 0,
1327 sizeof(struct ixgbe_filter_info));
1329 /* initialize 5tuple filter list */
1330 TAILQ_INIT(&filter_info->fivetuple_list);
1332 /* initialize flow director filter list & hash */
1333 ixgbe_fdir_filter_init(eth_dev);
1335 /* initialize l2 tunnel filter list & hash */
1336 ixgbe_l2_tn_filter_init(eth_dev);
1338 TAILQ_INIT(&filter_ntuple_list);
1339 TAILQ_INIT(&filter_ethertype_list);
1340 TAILQ_INIT(&filter_syn_list);
1341 TAILQ_INIT(&filter_fdir_list);
1342 TAILQ_INIT(&filter_l2_tunnel_list);
1343 TAILQ_INIT(&ixgbe_flow_list);
1349 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1351 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1352 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1353 struct ixgbe_hw *hw;
1355 PMD_INIT_FUNC_TRACE();
1357 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1360 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1362 if (hw->adapter_stopped == 0)
1363 ixgbe_dev_close(eth_dev);
1365 eth_dev->dev_ops = NULL;
1366 eth_dev->rx_pkt_burst = NULL;
1367 eth_dev->tx_pkt_burst = NULL;
1369 /* Unlock any pending hardware semaphore */
1370 ixgbe_swfw_lock_reset(hw);
1372 /* disable uio intr before callback unregister */
1373 rte_intr_disable(intr_handle);
1374 rte_intr_callback_unregister(intr_handle,
1375 ixgbe_dev_interrupt_handler, eth_dev);
1377 /* uninitialize PF if max_vfs not zero */
1378 ixgbe_pf_host_uninit(eth_dev);
1380 rte_free(eth_dev->data->mac_addrs);
1381 eth_dev->data->mac_addrs = NULL;
1383 rte_free(eth_dev->data->hash_mac_addrs);
1384 eth_dev->data->hash_mac_addrs = NULL;
1386 /* remove all the fdir filters & hash */
1387 ixgbe_fdir_filter_uninit(eth_dev);
1389 /* remove all the L2 tunnel filters & hash */
1390 ixgbe_l2_tn_filter_uninit(eth_dev);
1392 /* Remove all ntuple filters of the device */
1393 ixgbe_ntuple_filter_uninit(eth_dev);
1398 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1400 struct ixgbe_filter_info *filter_info =
1401 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1402 struct ixgbe_5tuple_filter *p_5tuple;
1404 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1405 TAILQ_REMOVE(&filter_info->fivetuple_list,
1410 memset(filter_info->fivetuple_mask, 0,
1411 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1416 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1418 struct ixgbe_hw_fdir_info *fdir_info =
1419 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1420 struct ixgbe_fdir_filter *fdir_filter;
1422 if (fdir_info->hash_map)
1423 rte_free(fdir_info->hash_map);
1424 if (fdir_info->hash_handle)
1425 rte_hash_free(fdir_info->hash_handle);
1427 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1428 TAILQ_REMOVE(&fdir_info->fdir_list,
1431 rte_free(fdir_filter);
1437 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1439 struct ixgbe_l2_tn_info *l2_tn_info =
1440 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1441 struct ixgbe_l2_tn_filter *l2_tn_filter;
1443 if (l2_tn_info->hash_map)
1444 rte_free(l2_tn_info->hash_map);
1445 if (l2_tn_info->hash_handle)
1446 rte_hash_free(l2_tn_info->hash_handle);
1448 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1449 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1452 rte_free(l2_tn_filter);
1458 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1460 struct ixgbe_hw_fdir_info *fdir_info =
1461 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1462 char fdir_hash_name[RTE_HASH_NAMESIZE];
1463 struct rte_hash_parameters fdir_hash_params = {
1464 .name = fdir_hash_name,
1465 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1466 .key_len = sizeof(union ixgbe_atr_input),
1467 .hash_func = rte_hash_crc,
1468 .hash_func_init_val = 0,
1469 .socket_id = rte_socket_id(),
1472 TAILQ_INIT(&fdir_info->fdir_list);
1473 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1474 "fdir_%s", eth_dev->data->name);
1475 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1476 if (!fdir_info->hash_handle) {
1477 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1480 fdir_info->hash_map = rte_zmalloc("ixgbe",
1481 sizeof(struct ixgbe_fdir_filter *) *
1482 IXGBE_MAX_FDIR_FILTER_NUM,
1484 if (!fdir_info->hash_map) {
1486 "Failed to allocate memory for fdir hash map!");
1489 fdir_info->mask_added = FALSE;
1494 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1496 struct ixgbe_l2_tn_info *l2_tn_info =
1497 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1498 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1499 struct rte_hash_parameters l2_tn_hash_params = {
1500 .name = l2_tn_hash_name,
1501 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1502 .key_len = sizeof(struct ixgbe_l2_tn_key),
1503 .hash_func = rte_hash_crc,
1504 .hash_func_init_val = 0,
1505 .socket_id = rte_socket_id(),
1508 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1509 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1510 "l2_tn_%s", eth_dev->data->name);
1511 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1512 if (!l2_tn_info->hash_handle) {
1513 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1516 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1517 sizeof(struct ixgbe_l2_tn_filter *) *
1518 IXGBE_MAX_L2_TN_FILTER_NUM,
1520 if (!l2_tn_info->hash_map) {
1522 "Failed to allocate memory for L2 TN hash map!");
1525 l2_tn_info->e_tag_en = FALSE;
1526 l2_tn_info->e_tag_fwd_en = FALSE;
1527 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1532 * Negotiate mailbox API version with the PF.
1533 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1534 * Then we try to negotiate starting with the most recent one.
1535 * If all negotiation attempts fail, then we will proceed with
1536 * the default one (ixgbe_mbox_api_10).
1539 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1543 /* start with highest supported, proceed down */
1544 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1551 i != RTE_DIM(sup_ver) &&
1552 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1558 generate_random_mac_addr(struct ether_addr *mac_addr)
1562 /* Set Organizationally Unique Identifier (OUI) prefix. */
1563 mac_addr->addr_bytes[0] = 0x00;
1564 mac_addr->addr_bytes[1] = 0x09;
1565 mac_addr->addr_bytes[2] = 0xC0;
1566 /* Force indication of locally assigned MAC address. */
1567 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1568 /* Generate the last 3 bytes of the MAC address with a random number. */
1569 random = rte_rand();
1570 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1574 * Virtual Function device init
1577 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1581 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1582 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1583 struct ixgbe_hw *hw =
1584 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1585 struct ixgbe_vfta *shadow_vfta =
1586 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1587 struct ixgbe_hwstrip *hwstrip =
1588 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1589 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1591 PMD_INIT_FUNC_TRACE();
1593 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1594 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1595 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1597 /* for secondary processes, we don't initialise any further as primary
1598 * has already done this work. Only check we don't need a different
1601 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1602 struct ixgbe_tx_queue *txq;
1603 /* TX queue function in primary, set by last queue initialized
1604 * Tx queue may not initialized by primary process
1606 if (eth_dev->data->tx_queues) {
1607 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1608 ixgbe_set_tx_function(eth_dev, txq);
1610 /* Use default TX function if we get here */
1611 PMD_INIT_LOG(NOTICE,
1612 "No TX queues configured yet. Using default TX function.");
1615 ixgbe_set_rx_function(eth_dev);
1620 rte_eth_copy_pci_info(eth_dev, pci_dev);
1621 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1623 hw->device_id = pci_dev->id.device_id;
1624 hw->vendor_id = pci_dev->id.vendor_id;
1625 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1627 /* initialize the vfta */
1628 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1630 /* initialize the hw strip bitmap*/
1631 memset(hwstrip, 0, sizeof(*hwstrip));
1633 /* Initialize the shared code (base driver) */
1634 diag = ixgbe_init_shared_code(hw);
1635 if (diag != IXGBE_SUCCESS) {
1636 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1640 /* init_mailbox_params */
1641 hw->mbx.ops.init_params(hw);
1643 /* Reset the hw statistics */
1644 ixgbevf_dev_stats_reset(eth_dev);
1646 /* Disable the interrupts for VF */
1647 ixgbevf_intr_disable(hw);
1649 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1650 diag = hw->mac.ops.reset_hw(hw);
1653 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1654 * the underlying PF driver has not assigned a MAC address to the VF.
1655 * In this case, assign a random MAC address.
1657 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1658 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1662 /* negotiate mailbox API version to use with the PF. */
1663 ixgbevf_negotiate_api(hw);
1665 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1666 ixgbevf_get_queues(hw, &tcs, &tc);
1668 /* Allocate memory for storing MAC addresses */
1669 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1670 hw->mac.num_rar_entries, 0);
1671 if (eth_dev->data->mac_addrs == NULL) {
1673 "Failed to allocate %u bytes needed to store "
1675 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1679 /* Generate a random MAC address, if none was assigned by PF. */
1680 if (is_zero_ether_addr(perm_addr)) {
1681 generate_random_mac_addr(perm_addr);
1682 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1684 rte_free(eth_dev->data->mac_addrs);
1685 eth_dev->data->mac_addrs = NULL;
1688 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1689 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1690 "%02x:%02x:%02x:%02x:%02x:%02x",
1691 perm_addr->addr_bytes[0],
1692 perm_addr->addr_bytes[1],
1693 perm_addr->addr_bytes[2],
1694 perm_addr->addr_bytes[3],
1695 perm_addr->addr_bytes[4],
1696 perm_addr->addr_bytes[5]);
1699 /* Copy the permanent MAC address */
1700 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1702 /* reset the hardware with the new settings */
1703 diag = hw->mac.ops.start_hw(hw);
1709 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1713 rte_intr_callback_register(intr_handle,
1714 ixgbevf_dev_interrupt_handler, eth_dev);
1715 rte_intr_enable(intr_handle);
1716 ixgbevf_intr_enable(hw);
1718 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1719 eth_dev->data->port_id, pci_dev->id.vendor_id,
1720 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1725 /* Virtual Function device uninit */
1728 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1730 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1731 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1732 struct ixgbe_hw *hw;
1734 PMD_INIT_FUNC_TRACE();
1736 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1739 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1741 if (hw->adapter_stopped == 0)
1742 ixgbevf_dev_close(eth_dev);
1744 eth_dev->dev_ops = NULL;
1745 eth_dev->rx_pkt_burst = NULL;
1746 eth_dev->tx_pkt_burst = NULL;
1748 /* Disable the interrupts for VF */
1749 ixgbevf_intr_disable(hw);
1751 rte_free(eth_dev->data->mac_addrs);
1752 eth_dev->data->mac_addrs = NULL;
1754 rte_intr_disable(intr_handle);
1755 rte_intr_callback_unregister(intr_handle,
1756 ixgbevf_dev_interrupt_handler, eth_dev);
1761 static struct eth_driver rte_ixgbe_pmd = {
1763 .id_table = pci_id_ixgbe_map,
1764 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1765 .probe = rte_eth_dev_pci_probe,
1766 .remove = rte_eth_dev_pci_remove,
1768 .eth_dev_init = eth_ixgbe_dev_init,
1769 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1770 .dev_private_size = sizeof(struct ixgbe_adapter),
1774 * virtual function driver struct
1776 static struct eth_driver rte_ixgbevf_pmd = {
1778 .id_table = pci_id_ixgbevf_map,
1779 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1780 .probe = rte_eth_dev_pci_probe,
1781 .remove = rte_eth_dev_pci_remove,
1783 .eth_dev_init = eth_ixgbevf_dev_init,
1784 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1785 .dev_private_size = sizeof(struct ixgbe_adapter),
1789 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1791 struct ixgbe_hw *hw =
1792 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1793 struct ixgbe_vfta *shadow_vfta =
1794 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1799 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1800 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1801 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1806 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1808 /* update local VFTA copy */
1809 shadow_vfta->vfta[vid_idx] = vfta;
1815 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1818 ixgbe_vlan_hw_strip_enable(dev, queue);
1820 ixgbe_vlan_hw_strip_disable(dev, queue);
1824 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1825 enum rte_vlan_type vlan_type,
1828 struct ixgbe_hw *hw =
1829 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1834 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1835 qinq &= IXGBE_DMATXCTL_GDV;
1837 switch (vlan_type) {
1838 case ETH_VLAN_TYPE_INNER:
1840 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1841 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1842 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1843 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1844 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1845 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1846 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1849 PMD_DRV_LOG(ERR, "Inner type is not supported"
1853 case ETH_VLAN_TYPE_OUTER:
1855 /* Only the high 16-bits is valid */
1856 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1857 IXGBE_EXVET_VET_EXT_SHIFT);
1859 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1860 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1861 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1862 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1863 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1864 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1865 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1871 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1879 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1881 struct ixgbe_hw *hw =
1882 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1885 PMD_INIT_FUNC_TRACE();
1887 /* Filter Table Disable */
1888 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1889 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1891 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1895 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1897 struct ixgbe_hw *hw =
1898 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1899 struct ixgbe_vfta *shadow_vfta =
1900 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1904 PMD_INIT_FUNC_TRACE();
1906 /* Filter Table Enable */
1907 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1908 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1909 vlnctrl |= IXGBE_VLNCTRL_VFE;
1911 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1913 /* write whatever is in local vfta copy */
1914 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1915 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1919 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1921 struct ixgbe_hwstrip *hwstrip =
1922 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1923 struct ixgbe_rx_queue *rxq;
1925 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1929 IXGBE_SET_HWSTRIP(hwstrip, queue);
1931 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1933 if (queue >= dev->data->nb_rx_queues)
1936 rxq = dev->data->rx_queues[queue];
1939 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1941 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1945 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1947 struct ixgbe_hw *hw =
1948 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951 PMD_INIT_FUNC_TRACE();
1953 if (hw->mac.type == ixgbe_mac_82598EB) {
1954 /* No queue level support */
1955 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1959 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1960 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1961 ctrl &= ~IXGBE_RXDCTL_VME;
1962 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1964 /* record those setting for HW strip per queue */
1965 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1969 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1971 struct ixgbe_hw *hw =
1972 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1975 PMD_INIT_FUNC_TRACE();
1977 if (hw->mac.type == ixgbe_mac_82598EB) {
1978 /* No queue level supported */
1979 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1983 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1984 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1985 ctrl |= IXGBE_RXDCTL_VME;
1986 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1988 /* record those setting for HW strip per queue */
1989 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1993 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1995 struct ixgbe_hw *hw =
1996 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1999 struct ixgbe_rx_queue *rxq;
2001 PMD_INIT_FUNC_TRACE();
2003 if (hw->mac.type == ixgbe_mac_82598EB) {
2004 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2005 ctrl &= ~IXGBE_VLNCTRL_VME;
2006 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2008 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2009 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2010 rxq = dev->data->rx_queues[i];
2011 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2012 ctrl &= ~IXGBE_RXDCTL_VME;
2013 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2015 /* record those setting for HW strip per queue */
2016 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2022 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2024 struct ixgbe_hw *hw =
2025 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028 struct ixgbe_rx_queue *rxq;
2030 PMD_INIT_FUNC_TRACE();
2032 if (hw->mac.type == ixgbe_mac_82598EB) {
2033 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2034 ctrl |= IXGBE_VLNCTRL_VME;
2035 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2037 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2038 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2039 rxq = dev->data->rx_queues[i];
2040 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2041 ctrl |= IXGBE_RXDCTL_VME;
2042 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2044 /* record those setting for HW strip per queue */
2045 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2051 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2053 struct ixgbe_hw *hw =
2054 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057 PMD_INIT_FUNC_TRACE();
2059 /* DMATXCTRL: Geric Double VLAN Disable */
2060 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2061 ctrl &= ~IXGBE_DMATXCTL_GDV;
2062 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2064 /* CTRL_EXT: Global Double VLAN Disable */
2065 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2066 ctrl &= ~IXGBE_EXTENDED_VLAN;
2067 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2072 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2074 struct ixgbe_hw *hw =
2075 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078 PMD_INIT_FUNC_TRACE();
2080 /* DMATXCTRL: Geric Double VLAN Enable */
2081 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2082 ctrl |= IXGBE_DMATXCTL_GDV;
2083 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2085 /* CTRL_EXT: Global Double VLAN Enable */
2086 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2087 ctrl |= IXGBE_EXTENDED_VLAN;
2088 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2090 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2091 if (hw->mac.type == ixgbe_mac_X550 ||
2092 hw->mac.type == ixgbe_mac_X550EM_x ||
2093 hw->mac.type == ixgbe_mac_X550EM_a) {
2094 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2095 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2096 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2100 * VET EXT field in the EXVET register = 0x8100 by default
2101 * So no need to change. Same to VT field of DMATXCTL register
2106 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2108 if (mask & ETH_VLAN_STRIP_MASK) {
2109 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2110 ixgbe_vlan_hw_strip_enable_all(dev);
2112 ixgbe_vlan_hw_strip_disable_all(dev);
2115 if (mask & ETH_VLAN_FILTER_MASK) {
2116 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2117 ixgbe_vlan_hw_filter_enable(dev);
2119 ixgbe_vlan_hw_filter_disable(dev);
2122 if (mask & ETH_VLAN_EXTEND_MASK) {
2123 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2124 ixgbe_vlan_hw_extend_enable(dev);
2126 ixgbe_vlan_hw_extend_disable(dev);
2131 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2133 struct ixgbe_hw *hw =
2134 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2135 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2136 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2138 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2139 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2143 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2145 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2150 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2153 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2159 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2160 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2166 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2168 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2169 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2170 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2171 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2173 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2174 /* check multi-queue mode */
2175 switch (dev_conf->rxmode.mq_mode) {
2176 case ETH_MQ_RX_VMDQ_DCB:
2177 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2179 case ETH_MQ_RX_VMDQ_DCB_RSS:
2180 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2181 PMD_INIT_LOG(ERR, "SRIOV active,"
2182 " unsupported mq_mode rx %d.",
2183 dev_conf->rxmode.mq_mode);
2186 case ETH_MQ_RX_VMDQ_RSS:
2187 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2188 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2189 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2190 PMD_INIT_LOG(ERR, "SRIOV is active,"
2191 " invalid queue number"
2192 " for VMDQ RSS, allowed"
2193 " value are 1, 2 or 4.");
2197 case ETH_MQ_RX_VMDQ_ONLY:
2198 case ETH_MQ_RX_NONE:
2199 /* if nothing mq mode configure, use default scheme */
2200 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2201 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2202 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2204 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2205 /* SRIOV only works in VMDq enable mode */
2206 PMD_INIT_LOG(ERR, "SRIOV is active,"
2207 " wrong mq_mode rx %d.",
2208 dev_conf->rxmode.mq_mode);
2212 switch (dev_conf->txmode.mq_mode) {
2213 case ETH_MQ_TX_VMDQ_DCB:
2214 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2215 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2217 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2218 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2222 /* check valid queue number */
2223 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2224 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2225 PMD_INIT_LOG(ERR, "SRIOV is active,"
2226 " nb_rx_q=%d nb_tx_q=%d queue number"
2227 " must be less than or equal to %d.",
2229 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2233 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2234 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2238 /* check configuration for vmdb+dcb mode */
2239 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2240 const struct rte_eth_vmdq_dcb_conf *conf;
2242 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2243 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2244 IXGBE_VMDQ_DCB_NB_QUEUES);
2247 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2248 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2249 conf->nb_queue_pools == ETH_32_POOLS)) {
2250 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2251 " nb_queue_pools must be %d or %d.",
2252 ETH_16_POOLS, ETH_32_POOLS);
2256 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2257 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2259 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2260 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2261 IXGBE_VMDQ_DCB_NB_QUEUES);
2264 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2265 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2266 conf->nb_queue_pools == ETH_32_POOLS)) {
2267 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2268 " nb_queue_pools != %d and"
2269 " nb_queue_pools != %d.",
2270 ETH_16_POOLS, ETH_32_POOLS);
2275 /* For DCB mode check our configuration before we go further */
2276 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2277 const struct rte_eth_dcb_rx_conf *conf;
2279 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2280 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2281 IXGBE_DCB_NB_QUEUES);
2284 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2285 if (!(conf->nb_tcs == ETH_4_TCS ||
2286 conf->nb_tcs == ETH_8_TCS)) {
2287 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2288 " and nb_tcs != %d.",
2289 ETH_4_TCS, ETH_8_TCS);
2294 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2295 const struct rte_eth_dcb_tx_conf *conf;
2297 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2298 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2299 IXGBE_DCB_NB_QUEUES);
2302 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2303 if (!(conf->nb_tcs == ETH_4_TCS ||
2304 conf->nb_tcs == ETH_8_TCS)) {
2305 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2306 " and nb_tcs != %d.",
2307 ETH_4_TCS, ETH_8_TCS);
2313 * When DCB/VT is off, maximum number of queues changes,
2314 * except for 82598EB, which remains constant.
2316 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2317 hw->mac.type != ixgbe_mac_82598EB) {
2318 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2320 "Neither VT nor DCB are enabled, "
2322 IXGBE_NONE_MODE_TX_NB_QUEUES);
2331 ixgbe_dev_configure(struct rte_eth_dev *dev)
2333 struct ixgbe_interrupt *intr =
2334 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2335 struct ixgbe_adapter *adapter =
2336 (struct ixgbe_adapter *)dev->data->dev_private;
2339 PMD_INIT_FUNC_TRACE();
2340 /* multipe queue mode checking */
2341 ret = ixgbe_check_mq_mode(dev);
2343 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2348 /* set flag to update link status after init */
2349 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2352 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2353 * allocation or vector Rx preconditions we will reset it.
2355 adapter->rx_bulk_alloc_allowed = true;
2356 adapter->rx_vec_allowed = true;
2362 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2364 struct ixgbe_hw *hw =
2365 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366 struct ixgbe_interrupt *intr =
2367 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2370 /* only set up it on X550EM_X */
2371 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2372 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2373 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2374 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2375 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2376 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2381 * Configure device link speed and setup link.
2382 * It returns 0 on success.
2385 ixgbe_dev_start(struct rte_eth_dev *dev)
2387 struct ixgbe_hw *hw =
2388 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389 struct ixgbe_vf_info *vfinfo =
2390 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2391 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2392 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2393 uint32_t intr_vector = 0;
2394 int err, link_up = 0, negotiate = 0;
2399 uint32_t *link_speeds;
2401 PMD_INIT_FUNC_TRACE();
2403 /* IXGBE devices don't support:
2404 * - half duplex (checked afterwards for valid speeds)
2405 * - fixed speed: TODO implement
2407 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2408 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2409 dev->data->port_id);
2413 /* disable uio/vfio intr/eventfd mapping */
2414 rte_intr_disable(intr_handle);
2417 hw->adapter_stopped = 0;
2418 ixgbe_stop_adapter(hw);
2420 /* reinitialize adapter
2421 * this calls reset and start
2423 status = ixgbe_pf_reset_hw(hw);
2426 hw->mac.ops.start_hw(hw);
2427 hw->mac.get_link_status = true;
2429 /* configure PF module if SRIOV enabled */
2430 ixgbe_pf_host_configure(dev);
2432 ixgbe_dev_phy_intr_setup(dev);
2434 /* check and configure queue intr-vector mapping */
2435 if ((rte_intr_cap_multiple(intr_handle) ||
2436 !RTE_ETH_DEV_SRIOV(dev).active) &&
2437 dev->data->dev_conf.intr_conf.rxq != 0) {
2438 intr_vector = dev->data->nb_rx_queues;
2439 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2440 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2441 IXGBE_MAX_INTR_QUEUE_NUM);
2444 if (rte_intr_efd_enable(intr_handle, intr_vector))
2448 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2449 intr_handle->intr_vec =
2450 rte_zmalloc("intr_vec",
2451 dev->data->nb_rx_queues * sizeof(int), 0);
2452 if (intr_handle->intr_vec == NULL) {
2453 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2454 " intr_vec\n", dev->data->nb_rx_queues);
2459 /* confiugre msix for sleep until rx interrupt */
2460 ixgbe_configure_msix(dev);
2462 /* initialize transmission unit */
2463 ixgbe_dev_tx_init(dev);
2465 /* This can fail when allocating mbufs for descriptor rings */
2466 err = ixgbe_dev_rx_init(dev);
2468 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2472 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2473 ETH_VLAN_EXTEND_MASK;
2474 ixgbe_vlan_offload_set(dev, mask);
2476 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2477 /* Enable vlan filtering for VMDq */
2478 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2481 /* Configure DCB hw */
2482 ixgbe_configure_dcb(dev);
2484 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2485 err = ixgbe_fdir_configure(dev);
2490 /* Restore vf rate limit */
2491 if (vfinfo != NULL) {
2492 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2493 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2494 if (vfinfo[vf].tx_rate[idx] != 0)
2495 rte_pmd_ixgbe_set_vf_rate_limit(
2496 dev->data->port_id, vf,
2497 vfinfo[vf].tx_rate[idx],
2501 ixgbe_restore_statistics_mapping(dev);
2503 err = ixgbe_dev_rxtx_start(dev);
2505 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2509 /* Skip link setup if loopback mode is enabled for 82599. */
2510 if (hw->mac.type == ixgbe_mac_82599EB &&
2511 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2512 goto skip_link_setup;
2514 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2515 err = hw->mac.ops.setup_sfp(hw);
2520 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2521 /* Turn on the copper */
2522 ixgbe_set_phy_power(hw, true);
2524 /* Turn on the laser */
2525 ixgbe_enable_tx_laser(hw);
2528 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2531 dev->data->dev_link.link_status = link_up;
2533 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2537 link_speeds = &dev->data->dev_conf.link_speeds;
2538 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2539 ETH_LINK_SPEED_10G)) {
2540 PMD_INIT_LOG(ERR, "Invalid link setting");
2545 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2546 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2547 IXGBE_LINK_SPEED_82599_AUTONEG :
2548 IXGBE_LINK_SPEED_82598_AUTONEG;
2550 if (*link_speeds & ETH_LINK_SPEED_10G)
2551 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2552 if (*link_speeds & ETH_LINK_SPEED_1G)
2553 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2554 if (*link_speeds & ETH_LINK_SPEED_100M)
2555 speed |= IXGBE_LINK_SPEED_100_FULL;
2558 err = ixgbe_setup_link(hw, speed, link_up);
2564 if (rte_intr_allow_others(intr_handle)) {
2565 /* check if lsc interrupt is enabled */
2566 if (dev->data->dev_conf.intr_conf.lsc != 0)
2567 ixgbe_dev_lsc_interrupt_setup(dev);
2568 ixgbe_dev_macsec_interrupt_setup(dev);
2570 rte_intr_callback_unregister(intr_handle,
2571 ixgbe_dev_interrupt_handler, dev);
2572 if (dev->data->dev_conf.intr_conf.lsc != 0)
2573 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2574 " no intr multiplex\n");
2577 /* check if rxq interrupt is enabled */
2578 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2579 rte_intr_dp_is_en(intr_handle))
2580 ixgbe_dev_rxq_interrupt_setup(dev);
2582 /* enable uio/vfio intr/eventfd mapping */
2583 rte_intr_enable(intr_handle);
2585 /* resume enabled intr since hw reset */
2586 ixgbe_enable_intr(dev);
2587 ixgbe_l2_tunnel_conf(dev);
2588 ixgbe_filter_restore(dev);
2593 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2594 ixgbe_dev_clear_queues(dev);
2599 * Stop device: disable rx and tx functions to allow for reconfiguring.
2602 ixgbe_dev_stop(struct rte_eth_dev *dev)
2604 struct rte_eth_link link;
2605 struct ixgbe_hw *hw =
2606 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2607 struct ixgbe_vf_info *vfinfo =
2608 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2609 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2610 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2613 PMD_INIT_FUNC_TRACE();
2615 /* disable interrupts */
2616 ixgbe_disable_intr(hw);
2619 ixgbe_pf_reset_hw(hw);
2620 hw->adapter_stopped = 0;
2623 ixgbe_stop_adapter(hw);
2625 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2626 vfinfo[vf].clear_to_send = false;
2628 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2629 /* Turn off the copper */
2630 ixgbe_set_phy_power(hw, false);
2632 /* Turn off the laser */
2633 ixgbe_disable_tx_laser(hw);
2636 ixgbe_dev_clear_queues(dev);
2638 /* Clear stored conf */
2639 dev->data->scattered_rx = 0;
2642 /* Clear recorded link status */
2643 memset(&link, 0, sizeof(link));
2644 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2646 if (!rte_intr_allow_others(intr_handle))
2647 /* resume to the default handler */
2648 rte_intr_callback_register(intr_handle,
2649 ixgbe_dev_interrupt_handler,
2652 /* Clean datapath event and queue/vec mapping */
2653 rte_intr_efd_disable(intr_handle);
2654 if (intr_handle->intr_vec != NULL) {
2655 rte_free(intr_handle->intr_vec);
2656 intr_handle->intr_vec = NULL;
2661 * Set device link up: enable tx.
2664 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2666 struct ixgbe_hw *hw =
2667 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668 if (hw->mac.type == ixgbe_mac_82599EB) {
2669 #ifdef RTE_NIC_BYPASS
2670 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2671 /* Not suported in bypass mode */
2672 PMD_INIT_LOG(ERR, "Set link up is not supported "
2673 "by device id 0x%x", hw->device_id);
2679 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2680 /* Turn on the copper */
2681 ixgbe_set_phy_power(hw, true);
2683 /* Turn on the laser */
2684 ixgbe_enable_tx_laser(hw);
2691 * Set device link down: disable tx.
2694 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2696 struct ixgbe_hw *hw =
2697 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2698 if (hw->mac.type == ixgbe_mac_82599EB) {
2699 #ifdef RTE_NIC_BYPASS
2700 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2701 /* Not suported in bypass mode */
2702 PMD_INIT_LOG(ERR, "Set link down is not supported "
2703 "by device id 0x%x", hw->device_id);
2709 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2710 /* Turn off the copper */
2711 ixgbe_set_phy_power(hw, false);
2713 /* Turn off the laser */
2714 ixgbe_disable_tx_laser(hw);
2721 * Reest and stop device.
2724 ixgbe_dev_close(struct rte_eth_dev *dev)
2726 struct ixgbe_hw *hw =
2727 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2729 PMD_INIT_FUNC_TRACE();
2731 ixgbe_pf_reset_hw(hw);
2733 ixgbe_dev_stop(dev);
2734 hw->adapter_stopped = 1;
2736 ixgbe_dev_free_queues(dev);
2738 ixgbe_disable_pcie_master(hw);
2740 /* reprogram the RAR[0] in case user changed it. */
2741 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2745 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2746 struct ixgbe_hw_stats *hw_stats,
2747 struct ixgbe_macsec_stats *macsec_stats,
2748 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2749 uint64_t *total_qprc, uint64_t *total_qprdc)
2751 uint32_t bprc, lxon, lxoff, total;
2752 uint32_t delta_gprc = 0;
2754 /* Workaround for RX byte count not including CRC bytes when CRC
2755 * strip is enabled. CRC bytes are removed from counters when crc_strip
2758 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2759 IXGBE_HLREG0_RXCRCSTRP);
2761 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2762 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2763 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2764 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2766 for (i = 0; i < 8; i++) {
2767 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2769 /* global total per queue */
2770 hw_stats->mpc[i] += mp;
2771 /* Running comprehensive total for stats display */
2772 *total_missed_rx += hw_stats->mpc[i];
2773 if (hw->mac.type == ixgbe_mac_82598EB) {
2774 hw_stats->rnbc[i] +=
2775 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2776 hw_stats->pxonrxc[i] +=
2777 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2778 hw_stats->pxoffrxc[i] +=
2779 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2781 hw_stats->pxonrxc[i] +=
2782 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2783 hw_stats->pxoffrxc[i] +=
2784 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2785 hw_stats->pxon2offc[i] +=
2786 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2788 hw_stats->pxontxc[i] +=
2789 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2790 hw_stats->pxofftxc[i] +=
2791 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2793 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2794 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2795 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2796 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2798 delta_gprc += delta_qprc;
2800 hw_stats->qprc[i] += delta_qprc;
2801 hw_stats->qptc[i] += delta_qptc;
2803 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2804 hw_stats->qbrc[i] +=
2805 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2807 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2809 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2810 hw_stats->qbtc[i] +=
2811 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2813 hw_stats->qprdc[i] += delta_qprdc;
2814 *total_qprdc += hw_stats->qprdc[i];
2816 *total_qprc += hw_stats->qprc[i];
2817 *total_qbrc += hw_stats->qbrc[i];
2819 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2820 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2821 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2824 * An errata states that gprc actually counts good + missed packets:
2825 * Workaround to set gprc to summated queue packet receives
2827 hw_stats->gprc = *total_qprc;
2829 if (hw->mac.type != ixgbe_mac_82598EB) {
2830 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2831 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2832 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2833 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2834 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2835 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2836 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2837 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2839 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2840 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2841 /* 82598 only has a counter in the high register */
2842 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2843 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2844 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2846 uint64_t old_tpr = hw_stats->tpr;
2848 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2849 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2852 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2854 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2855 hw_stats->gptc += delta_gptc;
2856 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2857 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2860 * Workaround: mprc hardware is incorrectly counting
2861 * broadcasts, so for now we subtract those.
2863 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2864 hw_stats->bprc += bprc;
2865 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2866 if (hw->mac.type == ixgbe_mac_82598EB)
2867 hw_stats->mprc -= bprc;
2869 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2870 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2871 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2872 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2873 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2874 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2876 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2877 hw_stats->lxontxc += lxon;
2878 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2879 hw_stats->lxofftxc += lxoff;
2880 total = lxon + lxoff;
2882 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2883 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2884 hw_stats->gptc -= total;
2885 hw_stats->mptc -= total;
2886 hw_stats->ptc64 -= total;
2887 hw_stats->gotc -= total * ETHER_MIN_LEN;
2889 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2890 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2891 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2892 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2893 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2894 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2895 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2896 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2897 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2898 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2899 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2900 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2901 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2902 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2903 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2904 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2905 /* Only read FCOE on 82599 */
2906 if (hw->mac.type != ixgbe_mac_82598EB) {
2907 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2908 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2909 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2910 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2911 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2914 /* Flow Director Stats registers */
2915 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2916 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2918 /* MACsec Stats registers */
2919 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2920 macsec_stats->out_pkts_encrypted +=
2921 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2922 macsec_stats->out_pkts_protected +=
2923 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2924 macsec_stats->out_octets_encrypted +=
2925 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2926 macsec_stats->out_octets_protected +=
2927 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2928 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2929 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2930 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2931 macsec_stats->in_pkts_unknownsci +=
2932 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2933 macsec_stats->in_octets_decrypted +=
2934 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2935 macsec_stats->in_octets_validated +=
2936 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2937 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2938 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2939 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2940 for (i = 0; i < 2; i++) {
2941 macsec_stats->in_pkts_ok +=
2942 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2943 macsec_stats->in_pkts_invalid +=
2944 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2945 macsec_stats->in_pkts_notvalid +=
2946 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2948 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2949 macsec_stats->in_pkts_notusingsa +=
2950 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2954 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2957 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2959 struct ixgbe_hw *hw =
2960 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2961 struct ixgbe_hw_stats *hw_stats =
2962 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2963 struct ixgbe_macsec_stats *macsec_stats =
2964 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2965 dev->data->dev_private);
2966 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2969 total_missed_rx = 0;
2974 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2975 &total_qbrc, &total_qprc, &total_qprdc);
2980 /* Fill out the rte_eth_stats statistics structure */
2981 stats->ipackets = total_qprc;
2982 stats->ibytes = total_qbrc;
2983 stats->opackets = hw_stats->gptc;
2984 stats->obytes = hw_stats->gotc;
2986 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2987 stats->q_ipackets[i] = hw_stats->qprc[i];
2988 stats->q_opackets[i] = hw_stats->qptc[i];
2989 stats->q_ibytes[i] = hw_stats->qbrc[i];
2990 stats->q_obytes[i] = hw_stats->qbtc[i];
2991 stats->q_errors[i] = hw_stats->qprdc[i];
2995 stats->imissed = total_missed_rx;
2996 stats->ierrors = hw_stats->crcerrs +
3012 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3014 struct ixgbe_hw_stats *stats =
3015 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3017 /* HW registers are cleared on read */
3018 ixgbe_dev_stats_get(dev, NULL);
3020 /* Reset software totals */
3021 memset(stats, 0, sizeof(*stats));
3024 /* This function calculates the number of xstats based on the current config */
3026 ixgbe_xstats_calc_num(void) {
3027 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3028 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3029 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3032 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3033 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3035 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3036 unsigned stat, i, count;
3038 if (xstats_names != NULL) {
3041 /* Note: limit >= cnt_stats checked upstream
3042 * in rte_eth_xstats_names()
3045 /* Extended stats from ixgbe_hw_stats */
3046 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3047 snprintf(xstats_names[count].name,
3048 sizeof(xstats_names[count].name),
3050 rte_ixgbe_stats_strings[i].name);
3055 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3056 snprintf(xstats_names[count].name,
3057 sizeof(xstats_names[count].name),
3059 rte_ixgbe_macsec_strings[i].name);
3063 /* RX Priority Stats */
3064 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3065 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3066 snprintf(xstats_names[count].name,
3067 sizeof(xstats_names[count].name),
3068 "rx_priority%u_%s", i,
3069 rte_ixgbe_rxq_strings[stat].name);
3074 /* TX Priority Stats */
3075 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3076 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3077 snprintf(xstats_names[count].name,
3078 sizeof(xstats_names[count].name),
3079 "tx_priority%u_%s", i,
3080 rte_ixgbe_txq_strings[stat].name);
3088 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3089 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3093 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3096 if (xstats_names != NULL)
3097 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3098 snprintf(xstats_names[i].name,
3099 sizeof(xstats_names[i].name),
3100 "%s", rte_ixgbevf_stats_strings[i].name);
3101 return IXGBEVF_NB_XSTATS;
3105 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3108 struct ixgbe_hw *hw =
3109 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3110 struct ixgbe_hw_stats *hw_stats =
3111 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3112 struct ixgbe_macsec_stats *macsec_stats =
3113 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3114 dev->data->dev_private);
3115 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3116 unsigned i, stat, count = 0;
3118 count = ixgbe_xstats_calc_num();
3123 total_missed_rx = 0;
3128 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3129 &total_qbrc, &total_qprc, &total_qprdc);
3131 /* If this is a reset xstats is NULL, and we have cleared the
3132 * registers by reading them.
3137 /* Extended stats from ixgbe_hw_stats */
3139 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3140 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3141 rte_ixgbe_stats_strings[i].offset);
3142 xstats[count].id = count;
3147 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3148 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3149 rte_ixgbe_macsec_strings[i].offset);
3150 xstats[count].id = count;
3154 /* RX Priority Stats */
3155 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3156 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3157 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3158 rte_ixgbe_rxq_strings[stat].offset +
3159 (sizeof(uint64_t) * i));
3160 xstats[count].id = count;
3165 /* TX Priority Stats */
3166 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3167 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3168 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3169 rte_ixgbe_txq_strings[stat].offset +
3170 (sizeof(uint64_t) * i));
3171 xstats[count].id = count;
3179 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3181 struct ixgbe_hw_stats *stats =
3182 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3183 struct ixgbe_macsec_stats *macsec_stats =
3184 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3185 dev->data->dev_private);
3187 unsigned count = ixgbe_xstats_calc_num();
3189 /* HW registers are cleared on read */
3190 ixgbe_dev_xstats_get(dev, NULL, count);
3192 /* Reset software totals */
3193 memset(stats, 0, sizeof(*stats));
3194 memset(macsec_stats, 0, sizeof(*macsec_stats));
3198 ixgbevf_update_stats(struct rte_eth_dev *dev)
3200 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3201 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3202 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3204 /* Good Rx packet, include VF loopback */
3205 UPDATE_VF_STAT(IXGBE_VFGPRC,
3206 hw_stats->last_vfgprc, hw_stats->vfgprc);
3208 /* Good Rx octets, include VF loopback */
3209 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3210 hw_stats->last_vfgorc, hw_stats->vfgorc);
3212 /* Good Tx packet, include VF loopback */
3213 UPDATE_VF_STAT(IXGBE_VFGPTC,
3214 hw_stats->last_vfgptc, hw_stats->vfgptc);
3216 /* Good Tx octets, include VF loopback */
3217 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3218 hw_stats->last_vfgotc, hw_stats->vfgotc);
3220 /* Rx Multicst Packet */
3221 UPDATE_VF_STAT(IXGBE_VFMPRC,
3222 hw_stats->last_vfmprc, hw_stats->vfmprc);
3226 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3229 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3230 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3233 if (n < IXGBEVF_NB_XSTATS)
3234 return IXGBEVF_NB_XSTATS;
3236 ixgbevf_update_stats(dev);
3241 /* Extended stats */
3242 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3243 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3244 rte_ixgbevf_stats_strings[i].offset);
3247 return IXGBEVF_NB_XSTATS;
3251 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3253 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3254 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3256 ixgbevf_update_stats(dev);
3261 stats->ipackets = hw_stats->vfgprc;
3262 stats->ibytes = hw_stats->vfgorc;
3263 stats->opackets = hw_stats->vfgptc;
3264 stats->obytes = hw_stats->vfgotc;
3268 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3270 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3271 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3273 /* Sync HW register to the last stats */
3274 ixgbevf_dev_stats_get(dev, NULL);
3276 /* reset HW current stats*/
3277 hw_stats->vfgprc = 0;
3278 hw_stats->vfgorc = 0;
3279 hw_stats->vfgptc = 0;
3280 hw_stats->vfgotc = 0;
3284 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3286 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3287 u16 eeprom_verh, eeprom_verl;
3291 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3292 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3294 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3295 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3297 ret += 1; /* add the size of '\0' */
3298 if (fw_size < (u32)ret)
3305 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3307 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3308 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3309 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3311 dev_info->pci_dev = pci_dev;
3312 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3313 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3314 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3316 * When DCB/VT is off, maximum number of queues changes,
3317 * except for 82598EB, which remains constant.
3319 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3320 hw->mac.type != ixgbe_mac_82598EB)
3321 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3323 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3324 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3325 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3326 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3327 dev_info->max_vfs = pci_dev->max_vfs;
3328 if (hw->mac.type == ixgbe_mac_82598EB)
3329 dev_info->max_vmdq_pools = ETH_16_POOLS;
3331 dev_info->max_vmdq_pools = ETH_64_POOLS;
3332 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3333 dev_info->rx_offload_capa =
3334 DEV_RX_OFFLOAD_VLAN_STRIP |
3335 DEV_RX_OFFLOAD_IPV4_CKSUM |
3336 DEV_RX_OFFLOAD_UDP_CKSUM |
3337 DEV_RX_OFFLOAD_TCP_CKSUM;
3340 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3343 if ((hw->mac.type == ixgbe_mac_82599EB ||
3344 hw->mac.type == ixgbe_mac_X540) &&
3345 !RTE_ETH_DEV_SRIOV(dev).active)
3346 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3348 if (hw->mac.type == ixgbe_mac_82599EB ||
3349 hw->mac.type == ixgbe_mac_X540)
3350 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3352 if (hw->mac.type == ixgbe_mac_X550 ||
3353 hw->mac.type == ixgbe_mac_X550EM_x ||
3354 hw->mac.type == ixgbe_mac_X550EM_a)
3355 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3357 dev_info->tx_offload_capa =
3358 DEV_TX_OFFLOAD_VLAN_INSERT |
3359 DEV_TX_OFFLOAD_IPV4_CKSUM |
3360 DEV_TX_OFFLOAD_UDP_CKSUM |
3361 DEV_TX_OFFLOAD_TCP_CKSUM |
3362 DEV_TX_OFFLOAD_SCTP_CKSUM |
3363 DEV_TX_OFFLOAD_TCP_TSO;
3365 if (hw->mac.type == ixgbe_mac_82599EB ||
3366 hw->mac.type == ixgbe_mac_X540)
3367 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3369 if (hw->mac.type == ixgbe_mac_X550 ||
3370 hw->mac.type == ixgbe_mac_X550EM_x ||
3371 hw->mac.type == ixgbe_mac_X550EM_a)
3372 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3374 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3376 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3377 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3378 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3380 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3384 dev_info->default_txconf = (struct rte_eth_txconf) {
3386 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3387 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3388 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3390 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3391 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3392 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3393 ETH_TXQ_FLAGS_NOOFFLOADS,
3396 dev_info->rx_desc_lim = rx_desc_lim;
3397 dev_info->tx_desc_lim = tx_desc_lim;
3399 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3400 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3401 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3403 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3404 if (hw->mac.type == ixgbe_mac_X540 ||
3405 hw->mac.type == ixgbe_mac_X540_vf ||
3406 hw->mac.type == ixgbe_mac_X550 ||
3407 hw->mac.type == ixgbe_mac_X550_vf) {
3408 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3412 static const uint32_t *
3413 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3415 static const uint32_t ptypes[] = {
3416 /* For non-vec functions,
3417 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3418 * for vec functions,
3419 * refers to _recv_raw_pkts_vec().
3423 RTE_PTYPE_L3_IPV4_EXT,
3425 RTE_PTYPE_L3_IPV6_EXT,
3429 RTE_PTYPE_TUNNEL_IP,
3430 RTE_PTYPE_INNER_L3_IPV6,
3431 RTE_PTYPE_INNER_L3_IPV6_EXT,
3432 RTE_PTYPE_INNER_L4_TCP,
3433 RTE_PTYPE_INNER_L4_UDP,
3437 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3438 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3439 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3440 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3446 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3447 struct rte_eth_dev_info *dev_info)
3449 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3450 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3452 dev_info->pci_dev = pci_dev;
3453 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3454 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3455 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3456 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3457 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3458 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3459 dev_info->max_vfs = pci_dev->max_vfs;
3460 if (hw->mac.type == ixgbe_mac_82598EB)
3461 dev_info->max_vmdq_pools = ETH_16_POOLS;
3463 dev_info->max_vmdq_pools = ETH_64_POOLS;
3464 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3465 DEV_RX_OFFLOAD_IPV4_CKSUM |
3466 DEV_RX_OFFLOAD_UDP_CKSUM |
3467 DEV_RX_OFFLOAD_TCP_CKSUM;
3468 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3469 DEV_TX_OFFLOAD_IPV4_CKSUM |
3470 DEV_TX_OFFLOAD_UDP_CKSUM |
3471 DEV_TX_OFFLOAD_TCP_CKSUM |
3472 DEV_TX_OFFLOAD_SCTP_CKSUM |
3473 DEV_TX_OFFLOAD_TCP_TSO;
3475 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3477 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3478 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3479 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3481 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3485 dev_info->default_txconf = (struct rte_eth_txconf) {
3487 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3488 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3489 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3491 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3492 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3493 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3494 ETH_TXQ_FLAGS_NOOFFLOADS,
3497 dev_info->rx_desc_lim = rx_desc_lim;
3498 dev_info->tx_desc_lim = tx_desc_lim;
3501 /* return 0 means link status changed, -1 means not changed */
3503 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3505 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3506 struct rte_eth_link link, old;
3507 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3511 link.link_status = ETH_LINK_DOWN;
3512 link.link_speed = 0;
3513 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3514 memset(&old, 0, sizeof(old));
3515 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3517 hw->mac.get_link_status = true;
3519 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3520 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3521 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3523 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3526 link.link_speed = ETH_SPEED_NUM_100M;
3527 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3528 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3529 if (link.link_status == old.link_status)
3535 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3536 if (link.link_status == old.link_status)
3540 link.link_status = ETH_LINK_UP;
3541 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3543 switch (link_speed) {
3545 case IXGBE_LINK_SPEED_UNKNOWN:
3546 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3547 link.link_speed = ETH_SPEED_NUM_100M;
3550 case IXGBE_LINK_SPEED_100_FULL:
3551 link.link_speed = ETH_SPEED_NUM_100M;
3554 case IXGBE_LINK_SPEED_1GB_FULL:
3555 link.link_speed = ETH_SPEED_NUM_1G;
3558 case IXGBE_LINK_SPEED_10GB_FULL:
3559 link.link_speed = ETH_SPEED_NUM_10G;
3562 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3564 if (link.link_status == old.link_status)
3571 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3573 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3576 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3577 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3578 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3582 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3584 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3588 fctrl &= (~IXGBE_FCTRL_UPE);
3589 if (dev->data->all_multicast == 1)
3590 fctrl |= IXGBE_FCTRL_MPE;
3592 fctrl &= (~IXGBE_FCTRL_MPE);
3593 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3597 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3599 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3602 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3603 fctrl |= IXGBE_FCTRL_MPE;
3604 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3608 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3610 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3613 if (dev->data->promiscuous == 1)
3614 return; /* must remain in all_multicast mode */
3616 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3617 fctrl &= (~IXGBE_FCTRL_MPE);
3618 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3622 * It clears the interrupt causes and enables the interrupt.
3623 * It will be called once only during nic initialized.
3626 * Pointer to struct rte_eth_dev.
3629 * - On success, zero.
3630 * - On failure, a negative value.
3633 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3635 struct ixgbe_interrupt *intr =
3636 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3638 ixgbe_dev_link_status_print(dev);
3639 intr->mask |= IXGBE_EICR_LSC;
3645 * It clears the interrupt causes and enables the interrupt.
3646 * It will be called once only during nic initialized.
3649 * Pointer to struct rte_eth_dev.
3652 * - On success, zero.
3653 * - On failure, a negative value.
3656 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3658 struct ixgbe_interrupt *intr =
3659 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3661 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3667 * It clears the interrupt causes and enables the interrupt.
3668 * It will be called once only during nic initialized.
3671 * Pointer to struct rte_eth_dev.
3674 * - On success, zero.
3675 * - On failure, a negative value.
3678 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3680 struct ixgbe_interrupt *intr =
3681 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3683 intr->mask |= IXGBE_EICR_LINKSEC;
3689 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3692 * Pointer to struct rte_eth_dev.
3695 * - On success, zero.
3696 * - On failure, a negative value.
3699 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3702 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3703 struct ixgbe_interrupt *intr =
3704 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3706 /* clear all cause mask */
3707 ixgbe_disable_intr(hw);
3709 /* read-on-clear nic registers here */
3710 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3711 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3715 /* set flag for async link update */
3716 if (eicr & IXGBE_EICR_LSC)
3717 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3719 if (eicr & IXGBE_EICR_MAILBOX)
3720 intr->flags |= IXGBE_FLAG_MAILBOX;
3722 if (eicr & IXGBE_EICR_LINKSEC)
3723 intr->flags |= IXGBE_FLAG_MACSEC;
3725 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3726 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3727 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3728 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3734 * It gets and then prints the link status.
3737 * Pointer to struct rte_eth_dev.
3740 * - On success, zero.
3741 * - On failure, a negative value.
3744 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3746 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3747 struct rte_eth_link link;
3749 memset(&link, 0, sizeof(link));
3750 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3751 if (link.link_status) {
3752 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3753 (int)(dev->data->port_id),
3754 (unsigned)link.link_speed,
3755 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3756 "full-duplex" : "half-duplex");
3758 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3759 (int)(dev->data->port_id));
3761 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3762 pci_dev->addr.domain,
3764 pci_dev->addr.devid,
3765 pci_dev->addr.function);
3769 * It executes link_update after knowing an interrupt occurred.
3772 * Pointer to struct rte_eth_dev.
3775 * - On success, zero.
3776 * - On failure, a negative value.
3779 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3780 struct rte_intr_handle *intr_handle)
3782 struct ixgbe_interrupt *intr =
3783 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3785 struct rte_eth_link link;
3786 int intr_enable_delay = false;
3787 struct ixgbe_hw *hw =
3788 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3790 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3792 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3793 ixgbe_pf_mbx_process(dev);
3794 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3797 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3798 ixgbe_handle_lasi(hw);
3799 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3802 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3803 /* get the link status before link update, for predicting later */
3804 memset(&link, 0, sizeof(link));
3805 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3807 ixgbe_dev_link_update(dev, 0);
3810 if (!link.link_status)
3811 /* handle it 1 sec later, wait it being stable */
3812 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3813 /* likely to down */
3815 /* handle it 4 sec later, wait it being stable */
3816 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3818 ixgbe_dev_link_status_print(dev);
3820 intr_enable_delay = true;
3823 if (intr_enable_delay) {
3824 if (rte_eal_alarm_set(timeout * 1000,
3825 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3826 PMD_DRV_LOG(ERR, "Error setting alarm");
3828 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3829 ixgbe_enable_intr(dev);
3830 rte_intr_enable(intr_handle);
3838 * Interrupt handler which shall be registered for alarm callback for delayed
3839 * handling specific interrupt to wait for the stable nic state. As the
3840 * NIC interrupt state is not stable for ixgbe after link is just down,
3841 * it needs to wait 4 seconds to get the stable status.
3844 * Pointer to interrupt handle.
3846 * The address of parameter (struct rte_eth_dev *) regsitered before.
3852 ixgbe_dev_interrupt_delayed_handler(void *param)
3854 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3855 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3856 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3857 struct ixgbe_interrupt *intr =
3858 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3859 struct ixgbe_hw *hw =
3860 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3863 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3864 if (eicr & IXGBE_EICR_MAILBOX)
3865 ixgbe_pf_mbx_process(dev);
3867 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3868 ixgbe_handle_lasi(hw);
3869 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3872 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3873 ixgbe_dev_link_update(dev, 0);
3874 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3875 ixgbe_dev_link_status_print(dev);
3876 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3879 if (intr->flags & IXGBE_FLAG_MACSEC) {
3880 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3882 intr->flags &= ~IXGBE_FLAG_MACSEC;
3885 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3886 ixgbe_enable_intr(dev);
3887 rte_intr_enable(intr_handle);
3891 * Interrupt handler triggered by NIC for handling
3892 * specific interrupt.
3895 * Pointer to interrupt handle.
3897 * The address of parameter (struct rte_eth_dev *) regsitered before.
3903 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3906 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3908 ixgbe_dev_interrupt_get_status(dev);
3909 ixgbe_dev_interrupt_action(dev, handle);
3913 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3915 struct ixgbe_hw *hw;
3917 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3918 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3922 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3924 struct ixgbe_hw *hw;
3926 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3927 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3931 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3933 struct ixgbe_hw *hw;
3939 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3941 fc_conf->pause_time = hw->fc.pause_time;
3942 fc_conf->high_water = hw->fc.high_water[0];
3943 fc_conf->low_water = hw->fc.low_water[0];
3944 fc_conf->send_xon = hw->fc.send_xon;
3945 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3948 * Return rx_pause status according to actual setting of
3951 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3952 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3958 * Return tx_pause status according to actual setting of
3961 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3962 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3967 if (rx_pause && tx_pause)
3968 fc_conf->mode = RTE_FC_FULL;
3970 fc_conf->mode = RTE_FC_RX_PAUSE;
3972 fc_conf->mode = RTE_FC_TX_PAUSE;
3974 fc_conf->mode = RTE_FC_NONE;
3980 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3982 struct ixgbe_hw *hw;
3984 uint32_t rx_buf_size;
3985 uint32_t max_high_water;
3987 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3994 PMD_INIT_FUNC_TRACE();
3996 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3997 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3998 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4001 * At least reserve one Ethernet frame for watermark
4002 * high_water/low_water in kilo bytes for ixgbe
4004 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4005 if ((fc_conf->high_water > max_high_water) ||
4006 (fc_conf->high_water < fc_conf->low_water)) {
4007 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4008 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4012 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4013 hw->fc.pause_time = fc_conf->pause_time;
4014 hw->fc.high_water[0] = fc_conf->high_water;
4015 hw->fc.low_water[0] = fc_conf->low_water;
4016 hw->fc.send_xon = fc_conf->send_xon;
4017 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4019 err = ixgbe_fc_enable(hw);
4021 /* Not negotiated is not an error case */
4022 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4024 /* check if we want to forward MAC frames - driver doesn't have native
4025 * capability to do that, so we'll write the registers ourselves */
4027 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4029 /* set or clear MFLCN.PMCF bit depending on configuration */
4030 if (fc_conf->mac_ctrl_frame_fwd != 0)
4031 mflcn |= IXGBE_MFLCN_PMCF;
4033 mflcn &= ~IXGBE_MFLCN_PMCF;
4035 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4036 IXGBE_WRITE_FLUSH(hw);
4041 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4046 * ixgbe_pfc_enable_generic - Enable flow control
4047 * @hw: pointer to hardware structure
4048 * @tc_num: traffic class number
4049 * Enable flow control according to the current settings.
4052 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4055 uint32_t mflcn_reg, fccfg_reg;
4057 uint32_t fcrtl, fcrth;
4061 /* Validate the water mark configuration */
4062 if (!hw->fc.pause_time) {
4063 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4067 /* Low water mark of zero causes XOFF floods */
4068 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4069 /* High/Low water can not be 0 */
4070 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4071 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4072 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4076 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4077 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4078 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4082 /* Negotiate the fc mode to use */
4083 ixgbe_fc_autoneg(hw);
4085 /* Disable any previous flow control settings */
4086 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4087 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4089 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4090 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4092 switch (hw->fc.current_mode) {
4095 * If the count of enabled RX Priority Flow control >1,
4096 * and the TX pause can not be disabled
4099 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4100 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4101 if (reg & IXGBE_FCRTH_FCEN)
4105 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4107 case ixgbe_fc_rx_pause:
4109 * Rx Flow control is enabled and Tx Flow control is
4110 * disabled by software override. Since there really
4111 * isn't a way to advertise that we are capable of RX
4112 * Pause ONLY, we will advertise that we support both
4113 * symmetric and asymmetric Rx PAUSE. Later, we will
4114 * disable the adapter's ability to send PAUSE frames.
4116 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4118 * If the count of enabled RX Priority Flow control >1,
4119 * and the TX pause can not be disabled
4122 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4123 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4124 if (reg & IXGBE_FCRTH_FCEN)
4128 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4130 case ixgbe_fc_tx_pause:
4132 * Tx Flow control is enabled, and Rx Flow control is
4133 * disabled by software override.
4135 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4138 /* Flow control (both Rx and Tx) is enabled by SW override. */
4139 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4140 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4143 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4144 ret_val = IXGBE_ERR_CONFIG;
4148 /* Set 802.3x based flow control settings. */
4149 mflcn_reg |= IXGBE_MFLCN_DPF;
4150 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4151 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4153 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4154 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4155 hw->fc.high_water[tc_num]) {
4156 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4157 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4158 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4160 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4162 * In order to prevent Tx hangs when the internal Tx
4163 * switch is enabled we must set the high water mark
4164 * to the maximum FCRTH value. This allows the Tx
4165 * switch to function even under heavy Rx workloads.
4167 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4169 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4171 /* Configure pause time (2 TCs per register) */
4172 reg = hw->fc.pause_time * 0x00010001;
4173 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4174 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4176 /* Configure flow control refresh threshold value */
4177 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4184 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4186 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4187 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4189 if (hw->mac.type != ixgbe_mac_82598EB) {
4190 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4196 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4199 uint32_t rx_buf_size;
4200 uint32_t max_high_water;
4202 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4203 struct ixgbe_hw *hw =
4204 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4205 struct ixgbe_dcb_config *dcb_config =
4206 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4208 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4215 PMD_INIT_FUNC_TRACE();
4217 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4218 tc_num = map[pfc_conf->priority];
4219 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4220 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4222 * At least reserve one Ethernet frame for watermark
4223 * high_water/low_water in kilo bytes for ixgbe
4225 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4226 if ((pfc_conf->fc.high_water > max_high_water) ||
4227 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4228 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4229 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4233 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4234 hw->fc.pause_time = pfc_conf->fc.pause_time;
4235 hw->fc.send_xon = pfc_conf->fc.send_xon;
4236 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4237 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4239 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4241 /* Not negotiated is not an error case */
4242 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4245 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4250 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4251 struct rte_eth_rss_reta_entry64 *reta_conf,
4254 uint16_t i, sp_reta_size;
4257 uint16_t idx, shift;
4258 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4261 PMD_INIT_FUNC_TRACE();
4263 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4264 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4269 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4270 if (reta_size != sp_reta_size) {
4271 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4272 "(%d) doesn't match the number hardware can supported "
4273 "(%d)\n", reta_size, sp_reta_size);
4277 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4278 idx = i / RTE_RETA_GROUP_SIZE;
4279 shift = i % RTE_RETA_GROUP_SIZE;
4280 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4284 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4285 if (mask == IXGBE_4_BIT_MASK)
4288 r = IXGBE_READ_REG(hw, reta_reg);
4289 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4290 if (mask & (0x1 << j))
4291 reta |= reta_conf[idx].reta[shift + j] <<
4294 reta |= r & (IXGBE_8_BIT_MASK <<
4297 IXGBE_WRITE_REG(hw, reta_reg, reta);
4304 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4305 struct rte_eth_rss_reta_entry64 *reta_conf,
4308 uint16_t i, sp_reta_size;
4311 uint16_t idx, shift;
4312 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4315 PMD_INIT_FUNC_TRACE();
4316 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4317 if (reta_size != sp_reta_size) {
4318 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4319 "(%d) doesn't match the number hardware can supported "
4320 "(%d)\n", reta_size, sp_reta_size);
4324 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4325 idx = i / RTE_RETA_GROUP_SIZE;
4326 shift = i % RTE_RETA_GROUP_SIZE;
4327 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4332 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4333 reta = IXGBE_READ_REG(hw, reta_reg);
4334 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4335 if (mask & (0x1 << j))
4336 reta_conf[idx].reta[shift + j] =
4337 ((reta >> (CHAR_BIT * j)) &
4346 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4347 uint32_t index, uint32_t pool)
4349 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4350 uint32_t enable_addr = 1;
4352 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4356 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4358 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4360 ixgbe_clear_rar(hw, index);
4364 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4366 ixgbe_remove_rar(dev, 0);
4368 ixgbe_add_rar(dev, addr, 0, 0);
4372 is_ixgbe_pmd(const char *driver_name)
4374 if (!strstr(driver_name, "ixgbe"))
4377 if (strstr(driver_name, "ixgbe_vf"))
4384 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4385 struct ether_addr *mac_addr)
4387 struct ixgbe_hw *hw;
4388 struct ixgbe_vf_info *vfinfo;
4390 uint8_t *new_mac = (uint8_t *)(mac_addr);
4391 struct rte_eth_dev *dev;
4392 struct rte_eth_dev_info dev_info;
4394 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4396 dev = &rte_eth_devices[port];
4397 rte_eth_dev_info_get(port, &dev_info);
4399 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4402 if (vf >= dev_info.max_vfs)
4405 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4406 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4407 rar_entry = hw->mac.num_rar_entries - (vf + 1);
4409 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4410 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4412 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4419 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4423 struct ixgbe_hw *hw;
4424 struct rte_eth_dev_info dev_info;
4425 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4427 ixgbe_dev_info_get(dev, &dev_info);
4429 /* check that mtu is within the allowed range */
4430 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4433 /* refuse mtu that requires the support of scattered packets when this
4434 * feature has not been enabled before.
4436 if (!dev->data->scattered_rx &&
4437 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4438 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4441 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4442 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4444 /* switch to jumbo mode if needed */
4445 if (frame_size > ETHER_MAX_LEN) {
4446 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4447 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4449 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4450 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4452 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4454 /* update max frame size */
4455 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4457 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4458 maxfrs &= 0x0000FFFF;
4459 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4460 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4466 * Virtual Function operations
4469 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4471 PMD_INIT_FUNC_TRACE();
4473 /* Clear interrupt mask to stop from interrupts being generated */
4474 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4476 IXGBE_WRITE_FLUSH(hw);
4480 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4482 PMD_INIT_FUNC_TRACE();
4484 /* VF enable interrupt autoclean */
4485 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4486 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4487 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4489 IXGBE_WRITE_FLUSH(hw);
4493 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4495 struct rte_eth_conf *conf = &dev->data->dev_conf;
4496 struct ixgbe_adapter *adapter =
4497 (struct ixgbe_adapter *)dev->data->dev_private;
4499 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4500 dev->data->port_id);
4503 * VF has no ability to enable/disable HW CRC
4504 * Keep the persistent behavior the same as Host PF
4506 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4507 if (!conf->rxmode.hw_strip_crc) {
4508 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4509 conf->rxmode.hw_strip_crc = 1;
4512 if (conf->rxmode.hw_strip_crc) {
4513 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4514 conf->rxmode.hw_strip_crc = 0;
4519 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4520 * allocation or vector Rx preconditions we will reset it.
4522 adapter->rx_bulk_alloc_allowed = true;
4523 adapter->rx_vec_allowed = true;
4529 ixgbevf_dev_start(struct rte_eth_dev *dev)
4531 struct ixgbe_hw *hw =
4532 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4533 uint32_t intr_vector = 0;
4534 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4535 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4539 PMD_INIT_FUNC_TRACE();
4541 hw->mac.ops.reset_hw(hw);
4542 hw->mac.get_link_status = true;
4544 /* negotiate mailbox API version to use with the PF. */
4545 ixgbevf_negotiate_api(hw);
4547 ixgbevf_dev_tx_init(dev);
4549 /* This can fail when allocating mbufs for descriptor rings */
4550 err = ixgbevf_dev_rx_init(dev);
4552 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4553 ixgbe_dev_clear_queues(dev);
4558 ixgbevf_set_vfta_all(dev, 1);
4561 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4562 ETH_VLAN_EXTEND_MASK;
4563 ixgbevf_vlan_offload_set(dev, mask);
4565 ixgbevf_dev_rxtx_start(dev);
4567 /* check and configure queue intr-vector mapping */
4568 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4569 intr_vector = dev->data->nb_rx_queues;
4570 if (rte_intr_efd_enable(intr_handle, intr_vector))
4574 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4575 intr_handle->intr_vec =
4576 rte_zmalloc("intr_vec",
4577 dev->data->nb_rx_queues * sizeof(int), 0);
4578 if (intr_handle->intr_vec == NULL) {
4579 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4580 " intr_vec\n", dev->data->nb_rx_queues);
4584 ixgbevf_configure_msix(dev);
4586 rte_intr_enable(intr_handle);
4588 /* Re-enable interrupt for VF */
4589 ixgbevf_intr_enable(hw);
4595 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4597 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4598 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4599 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4601 PMD_INIT_FUNC_TRACE();
4603 ixgbevf_intr_disable(hw);
4605 hw->adapter_stopped = 1;
4606 ixgbe_stop_adapter(hw);
4609 * Clear what we set, but we still keep shadow_vfta to
4610 * restore after device starts
4612 ixgbevf_set_vfta_all(dev, 0);
4614 /* Clear stored conf */
4615 dev->data->scattered_rx = 0;
4617 ixgbe_dev_clear_queues(dev);
4619 /* Clean datapath event and queue/vec mapping */
4620 rte_intr_efd_disable(intr_handle);
4621 if (intr_handle->intr_vec != NULL) {
4622 rte_free(intr_handle->intr_vec);
4623 intr_handle->intr_vec = NULL;
4628 ixgbevf_dev_close(struct rte_eth_dev *dev)
4630 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4632 PMD_INIT_FUNC_TRACE();
4636 ixgbevf_dev_stop(dev);
4638 ixgbe_dev_free_queues(dev);
4641 * Remove the VF MAC address ro ensure
4642 * that the VF traffic goes to the PF
4643 * after stop, close and detach of the VF
4645 ixgbevf_remove_mac_addr(dev, 0);
4648 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4650 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4651 struct ixgbe_vfta *shadow_vfta =
4652 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4653 int i = 0, j = 0, vfta = 0, mask = 1;
4655 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4656 vfta = shadow_vfta->vfta[i];
4659 for (j = 0; j < 32; j++) {
4661 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4671 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4673 struct ixgbe_hw *hw =
4674 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4675 struct ixgbe_vfta *shadow_vfta =
4676 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4677 uint32_t vid_idx = 0;
4678 uint32_t vid_bit = 0;
4681 PMD_INIT_FUNC_TRACE();
4683 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4684 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4686 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4689 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4690 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4692 /* Save what we set and retore it after device reset */
4694 shadow_vfta->vfta[vid_idx] |= vid_bit;
4696 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4702 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4704 struct ixgbe_hw *hw =
4705 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4708 PMD_INIT_FUNC_TRACE();
4710 if (queue >= hw->mac.max_rx_queues)
4713 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4715 ctrl |= IXGBE_RXDCTL_VME;
4717 ctrl &= ~IXGBE_RXDCTL_VME;
4718 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4720 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4724 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4726 struct ixgbe_hw *hw =
4727 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4731 /* VF function only support hw strip feature, others are not support */
4732 if (mask & ETH_VLAN_STRIP_MASK) {
4733 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4735 for (i = 0; i < hw->mac.max_rx_queues; i++)
4736 ixgbevf_vlan_strip_queue_set(dev, i, on);
4741 ixgbe_vt_check(struct ixgbe_hw *hw)
4745 /* if Virtualization Technology is enabled */
4746 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4747 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4748 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4756 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4758 uint32_t vector = 0;
4760 switch (hw->mac.mc_filter_type) {
4761 case 0: /* use bits [47:36] of the address */
4762 vector = ((uc_addr->addr_bytes[4] >> 4) |
4763 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4765 case 1: /* use bits [46:35] of the address */
4766 vector = ((uc_addr->addr_bytes[4] >> 3) |
4767 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4769 case 2: /* use bits [45:34] of the address */
4770 vector = ((uc_addr->addr_bytes[4] >> 2) |
4771 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4773 case 3: /* use bits [43:32] of the address */
4774 vector = ((uc_addr->addr_bytes[4]) |
4775 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4777 default: /* Invalid mc_filter_type */
4781 /* vector can only be 12-bits or boundary will be exceeded */
4787 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4795 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4796 const uint32_t ixgbe_uta_bit_shift = 5;
4797 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4798 const uint32_t bit1 = 0x1;
4800 struct ixgbe_hw *hw =
4801 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4802 struct ixgbe_uta_info *uta_info =
4803 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4805 /* The UTA table only exists on 82599 hardware and newer */
4806 if (hw->mac.type < ixgbe_mac_82599EB)
4809 vector = ixgbe_uta_vector(hw, mac_addr);
4810 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4811 uta_shift = vector & ixgbe_uta_bit_mask;
4813 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4817 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4819 uta_info->uta_in_use++;
4820 reg_val |= (bit1 << uta_shift);
4821 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4823 uta_info->uta_in_use--;
4824 reg_val &= ~(bit1 << uta_shift);
4825 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4828 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4830 if (uta_info->uta_in_use > 0)
4831 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4832 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4834 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4840 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4843 struct ixgbe_hw *hw =
4844 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845 struct ixgbe_uta_info *uta_info =
4846 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4848 /* The UTA table only exists on 82599 hardware and newer */
4849 if (hw->mac.type < ixgbe_mac_82599EB)
4853 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4854 uta_info->uta_shadow[i] = ~0;
4855 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4858 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4859 uta_info->uta_shadow[i] = 0;
4860 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4868 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4870 uint32_t new_val = orig_val;
4872 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4873 new_val |= IXGBE_VMOLR_AUPE;
4874 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4875 new_val |= IXGBE_VMOLR_ROMPE;
4876 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4877 new_val |= IXGBE_VMOLR_ROPE;
4878 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4879 new_val |= IXGBE_VMOLR_BAM;
4880 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4881 new_val |= IXGBE_VMOLR_MPE;
4888 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4890 struct ixgbe_hw *hw;
4891 struct ixgbe_mac_info *mac;
4892 struct rte_eth_dev *dev;
4893 struct rte_eth_dev_info dev_info;
4895 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4897 dev = &rte_eth_devices[port];
4898 rte_eth_dev_info_get(port, &dev_info);
4900 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4903 if (vf >= dev_info.max_vfs)
4909 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4912 mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4918 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4920 struct ixgbe_hw *hw;
4921 struct ixgbe_mac_info *mac;
4922 struct rte_eth_dev *dev;
4923 struct rte_eth_dev_info dev_info;
4925 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4927 dev = &rte_eth_devices[port];
4928 rte_eth_dev_info_get(port, &dev_info);
4930 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4933 if (vf >= dev_info.max_vfs)
4939 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4941 mac->ops.set_mac_anti_spoofing(hw, on, vf);
4947 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4949 struct ixgbe_hw *hw;
4951 struct rte_eth_dev *dev;
4952 struct rte_eth_dev_info dev_info;
4954 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4956 dev = &rte_eth_devices[port];
4957 rte_eth_dev_info_get(port, &dev_info);
4959 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4962 if (vf >= dev_info.max_vfs)
4965 if (vlan_id > ETHER_MAX_VLAN_ID)
4968 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4969 ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4972 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4977 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4983 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4985 struct ixgbe_hw *hw;
4987 struct rte_eth_dev *dev;
4988 struct rte_eth_dev_info dev_info;
4990 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4992 dev = &rte_eth_devices[port];
4993 rte_eth_dev_info_get(port, &dev_info);
4995 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5001 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5002 ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5003 /* enable or disable VMDQ loopback */
5005 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5007 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5009 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5015 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5017 struct ixgbe_hw *hw;
5020 int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5021 struct rte_eth_dev *dev;
5022 struct rte_eth_dev_info dev_info;
5024 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5026 dev = &rte_eth_devices[port];
5027 rte_eth_dev_info_get(port, &dev_info);
5029 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5035 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5036 for (i = 0; i <= num_queues; i++) {
5037 reg_value = IXGBE_QDE_WRITE |
5038 (i << IXGBE_QDE_IDX_SHIFT) |
5039 (on & IXGBE_QDE_ENABLE);
5040 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5047 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5049 struct ixgbe_hw *hw;
5051 struct rte_eth_dev *dev;
5052 struct rte_eth_dev_info dev_info;
5054 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5056 dev = &rte_eth_devices[port];
5057 rte_eth_dev_info_get(port, &dev_info);
5059 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5062 /* only support VF's 0 to 63 */
5063 if ((vf >= dev_info.max_vfs) || (vf > 63))
5069 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5070 reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5072 reg_value |= IXGBE_SRRCTL_DROP_EN;
5074 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5076 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5082 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5084 struct rte_eth_dev *dev;
5085 struct rte_eth_dev_info dev_info;
5086 uint16_t queues_per_pool;
5089 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5091 dev = &rte_eth_devices[port];
5092 rte_eth_dev_info_get(port, &dev_info);
5094 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5097 if (vf >= dev_info.max_vfs)
5103 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5105 /* The PF has 128 queue pairs and in SRIOV configuration
5106 * those queues will be assigned to VF's, so RXDCTL
5107 * registers will be dealing with queues which will be
5109 * Let's say we have SRIOV configured with 31 VF's then the
5110 * first 124 queues 0-123 will be allocated to VF's and only
5111 * the last 4 queues 123-127 will be assigned to the PF.
5114 queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5116 for (q = 0; q < queues_per_pool; q++)
5117 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5118 q + vf * queues_per_pool, on);
5123 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5126 struct rte_eth_dev *dev;
5127 struct rte_eth_dev_info dev_info;
5128 struct ixgbe_hw *hw;
5131 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5133 dev = &rte_eth_devices[port];
5134 rte_eth_dev_info_get(port, &dev_info);
5136 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5139 if (vf >= dev_info.max_vfs)
5145 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5146 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5148 if (hw->mac.type == ixgbe_mac_82598EB) {
5149 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5150 " on 82599 hardware and newer");
5153 if (ixgbe_vt_check(hw) < 0)
5156 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5163 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5169 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5171 struct rte_eth_dev *dev;
5172 struct rte_eth_dev_info dev_info;
5175 const uint8_t bit1 = 0x1;
5176 struct ixgbe_hw *hw;
5178 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5180 dev = &rte_eth_devices[port];
5181 rte_eth_dev_info_get(port, &dev_info);
5183 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5186 if (vf >= dev_info.max_vfs)
5192 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5194 if (ixgbe_vt_check(hw) < 0)
5197 /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5199 addr = IXGBE_VFRE(1);
5200 val = bit1 << (vf - 32);
5202 addr = IXGBE_VFRE(0);
5206 reg = IXGBE_READ_REG(hw, addr);
5213 IXGBE_WRITE_REG(hw, addr, reg);
5219 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5221 struct rte_eth_dev *dev;
5222 struct rte_eth_dev_info dev_info;
5225 const uint8_t bit1 = 0x1;
5227 struct ixgbe_hw *hw;
5229 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5231 dev = &rte_eth_devices[port];
5232 rte_eth_dev_info_get(port, &dev_info);
5234 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5237 if (vf >= dev_info.max_vfs)
5243 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5244 if (ixgbe_vt_check(hw) < 0)
5247 /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5249 addr = IXGBE_VFTE(1);
5250 val = bit1 << (vf - 32);
5252 addr = IXGBE_VFTE(0);
5256 reg = IXGBE_READ_REG(hw, addr);
5263 IXGBE_WRITE_REG(hw, addr, reg);
5269 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5270 uint64_t vf_mask, uint8_t vlan_on)
5272 struct rte_eth_dev *dev;
5273 struct rte_eth_dev_info dev_info;
5276 struct ixgbe_hw *hw;
5278 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5280 dev = &rte_eth_devices[port];
5281 rte_eth_dev_info_get(port, &dev_info);
5283 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5286 if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5289 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5290 if (ixgbe_vt_check(hw) < 0)
5293 for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5294 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5295 ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5305 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5306 uint16_t tx_rate, uint64_t q_msk)
5308 struct rte_eth_dev *dev;
5309 struct rte_eth_dev_info dev_info;
5310 struct ixgbe_hw *hw;
5311 struct ixgbe_vf_info *vfinfo;
5312 struct rte_eth_link link;
5313 uint8_t nb_q_per_pool;
5314 uint32_t queue_stride;
5315 uint32_t queue_idx, idx = 0, vf_idx;
5317 uint16_t total_rate = 0;
5318 struct rte_pci_device *pci_dev;
5320 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5322 dev = &rte_eth_devices[port];
5323 rte_eth_dev_info_get(port, &dev_info);
5324 rte_eth_link_get_nowait(port, &link);
5326 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5329 if (vf >= dev_info.max_vfs)
5332 if (tx_rate > link.link_speed)
5338 pci_dev = IXGBE_DEV_TO_PCI(dev);
5339 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5340 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5341 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5342 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5343 queue_idx = vf * queue_stride;
5344 queue_end = queue_idx + nb_q_per_pool - 1;
5345 if (queue_end >= hw->mac.max_tx_queues)
5349 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5352 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5354 total_rate += vfinfo[vf_idx].tx_rate[idx];
5360 /* Store tx_rate for this vf. */
5361 for (idx = 0; idx < nb_q_per_pool; idx++) {
5362 if (((uint64_t)0x1 << idx) & q_msk) {
5363 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5364 vfinfo[vf].tx_rate[idx] = tx_rate;
5365 total_rate += tx_rate;
5369 if (total_rate > dev->data->dev_link.link_speed) {
5370 /* Reset stored TX rate of the VF if it causes exceed
5373 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5377 /* Set RTTBCNRC of each queue/pool for vf X */
5378 for (; queue_idx <= queue_end; queue_idx++) {
5380 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5387 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5388 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5389 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5390 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5391 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5392 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5393 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5396 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5397 struct rte_eth_mirror_conf *mirror_conf,
5398 uint8_t rule_id, uint8_t on)
5400 uint32_t mr_ctl, vlvf;
5401 uint32_t mp_lsb = 0;
5402 uint32_t mv_msb = 0;
5403 uint32_t mv_lsb = 0;
5404 uint32_t mp_msb = 0;
5407 uint64_t vlan_mask = 0;
5409 const uint8_t pool_mask_offset = 32;
5410 const uint8_t vlan_mask_offset = 32;
5411 const uint8_t dst_pool_offset = 8;
5412 const uint8_t rule_mr_offset = 4;
5413 const uint8_t mirror_rule_mask = 0x0F;
5415 struct ixgbe_mirror_info *mr_info =
5416 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5417 struct ixgbe_hw *hw =
5418 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5419 uint8_t mirror_type = 0;
5421 if (ixgbe_vt_check(hw) < 0)
5424 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5427 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5428 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5429 mirror_conf->rule_type);
5433 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5434 mirror_type |= IXGBE_MRCTL_VLME;
5435 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5436 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5437 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5438 /* search vlan id related pool vlan filter index */
5439 reg_index = ixgbe_find_vlvf_slot(hw,
5440 mirror_conf->vlan.vlan_id[i],
5444 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5445 if ((vlvf & IXGBE_VLVF_VIEN) &&
5446 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5447 mirror_conf->vlan.vlan_id[i]))
5448 vlan_mask |= (1ULL << reg_index);
5455 mv_lsb = vlan_mask & 0xFFFFFFFF;
5456 mv_msb = vlan_mask >> vlan_mask_offset;
5458 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5459 mirror_conf->vlan.vlan_mask;
5460 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5461 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5462 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5463 mirror_conf->vlan.vlan_id[i];
5468 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5469 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5470 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5475 * if enable pool mirror, write related pool mask register,if disable
5476 * pool mirror, clear PFMRVM register
5478 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5479 mirror_type |= IXGBE_MRCTL_VPME;
5481 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5482 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5483 mr_info->mr_conf[rule_id].pool_mask =
5484 mirror_conf->pool_mask;
5489 mr_info->mr_conf[rule_id].pool_mask = 0;
5492 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5493 mirror_type |= IXGBE_MRCTL_UPME;
5494 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5495 mirror_type |= IXGBE_MRCTL_DPME;
5497 /* read mirror control register and recalculate it */
5498 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5501 mr_ctl |= mirror_type;
5502 mr_ctl &= mirror_rule_mask;
5503 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5505 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5507 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5508 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5510 /* write mirrror control register */
5511 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5513 /* write pool mirrror control register */
5514 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5515 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5516 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5519 /* write VLAN mirrror control register */
5520 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5521 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5522 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5530 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5533 uint32_t lsb_val = 0;
5534 uint32_t msb_val = 0;
5535 const uint8_t rule_mr_offset = 4;
5537 struct ixgbe_hw *hw =
5538 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5539 struct ixgbe_mirror_info *mr_info =
5540 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5542 if (ixgbe_vt_check(hw) < 0)
5545 memset(&mr_info->mr_conf[rule_id], 0,
5546 sizeof(struct rte_eth_mirror_conf));
5548 /* clear PFVMCTL register */
5549 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5551 /* clear pool mask register */
5552 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5553 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5555 /* clear vlan mask register */
5556 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5557 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5563 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5565 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5566 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5568 struct ixgbe_hw *hw =
5569 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5571 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5572 mask |= (1 << IXGBE_MISC_VEC_ID);
5573 RTE_SET_USED(queue_id);
5574 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5576 rte_intr_enable(intr_handle);
5582 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5585 struct ixgbe_hw *hw =
5586 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5588 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5589 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5590 RTE_SET_USED(queue_id);
5591 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5597 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5599 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5600 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5602 struct ixgbe_hw *hw =
5603 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5604 struct ixgbe_interrupt *intr =
5605 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5607 if (queue_id < 16) {
5608 ixgbe_disable_intr(hw);
5609 intr->mask |= (1 << queue_id);
5610 ixgbe_enable_intr(dev);
5611 } else if (queue_id < 32) {
5612 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5613 mask &= (1 << queue_id);
5614 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5615 } else if (queue_id < 64) {
5616 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5617 mask &= (1 << (queue_id - 32));
5618 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5620 rte_intr_enable(intr_handle);
5626 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5629 struct ixgbe_hw *hw =
5630 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5631 struct ixgbe_interrupt *intr =
5632 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5634 if (queue_id < 16) {
5635 ixgbe_disable_intr(hw);
5636 intr->mask &= ~(1 << queue_id);
5637 ixgbe_enable_intr(dev);
5638 } else if (queue_id < 32) {
5639 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5640 mask &= ~(1 << queue_id);
5641 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5642 } else if (queue_id < 64) {
5643 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5644 mask &= ~(1 << (queue_id - 32));
5645 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5652 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5653 uint8_t queue, uint8_t msix_vector)
5657 if (direction == -1) {
5659 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5660 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5663 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5665 /* rx or tx cause */
5666 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5667 idx = ((16 * (queue & 1)) + (8 * direction));
5668 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5669 tmp &= ~(0xFF << idx);
5670 tmp |= (msix_vector << idx);
5671 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5676 * set the IVAR registers, mapping interrupt causes to vectors
5678 * pointer to ixgbe_hw struct
5680 * 0 for Rx, 1 for Tx, -1 for other causes
5682 * queue to map the corresponding interrupt to
5684 * the vector to map to the corresponding queue
5687 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5688 uint8_t queue, uint8_t msix_vector)
5692 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5693 if (hw->mac.type == ixgbe_mac_82598EB) {
5694 if (direction == -1)
5696 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5697 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5698 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5699 tmp |= (msix_vector << (8 * (queue & 0x3)));
5700 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5701 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5702 (hw->mac.type == ixgbe_mac_X540)) {
5703 if (direction == -1) {
5705 idx = ((queue & 1) * 8);
5706 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5707 tmp &= ~(0xFF << idx);
5708 tmp |= (msix_vector << idx);
5709 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5711 /* rx or tx causes */
5712 idx = ((16 * (queue & 1)) + (8 * direction));
5713 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5714 tmp &= ~(0xFF << idx);
5715 tmp |= (msix_vector << idx);
5716 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5722 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5724 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5725 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5726 struct ixgbe_hw *hw =
5727 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5729 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5731 /* Configure VF other cause ivar */
5732 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5734 /* won't configure msix register if no mapping is done
5735 * between intr vector and event fd.
5737 if (!rte_intr_dp_is_en(intr_handle))
5740 /* Configure all RX queues of VF */
5741 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5742 /* Force all queue use vector 0,
5743 * as IXGBE_VF_MAXMSIVECOTR = 1
5745 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5746 intr_handle->intr_vec[q_idx] = vector_idx;
5751 * Sets up the hardware to properly generate MSI-X interrupts
5753 * board private structure
5756 ixgbe_configure_msix(struct rte_eth_dev *dev)
5758 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5759 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5760 struct ixgbe_hw *hw =
5761 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5762 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5763 uint32_t vec = IXGBE_MISC_VEC_ID;
5767 /* won't configure msix register if no mapping is done
5768 * between intr vector and event fd
5770 if (!rte_intr_dp_is_en(intr_handle))
5773 if (rte_intr_allow_others(intr_handle))
5774 vec = base = IXGBE_RX_VEC_START;
5776 /* setup GPIE for MSI-x mode */
5777 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5778 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5779 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5780 /* auto clearing and auto setting corresponding bits in EIMS
5781 * when MSI-X interrupt is triggered
5783 if (hw->mac.type == ixgbe_mac_82598EB) {
5784 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5786 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5787 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5789 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5791 /* Populate the IVAR table and set the ITR values to the
5792 * corresponding register.
5794 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5796 /* by default, 1:1 mapping */
5797 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5798 intr_handle->intr_vec[queue_id] = vec;
5799 if (vec < base + intr_handle->nb_efd - 1)
5803 switch (hw->mac.type) {
5804 case ixgbe_mac_82598EB:
5805 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5808 case ixgbe_mac_82599EB:
5809 case ixgbe_mac_X540:
5810 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5815 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5816 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5818 /* set up to autoclear timer, and the vectors */
5819 mask = IXGBE_EIMS_ENABLE_MASK;
5820 mask &= ~(IXGBE_EIMS_OTHER |
5821 IXGBE_EIMS_MAILBOX |
5824 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5827 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5828 uint16_t queue_idx, uint16_t tx_rate)
5830 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5831 uint32_t rf_dec, rf_int;
5833 uint16_t link_speed = dev->data->dev_link.link_speed;
5835 if (queue_idx >= hw->mac.max_tx_queues)
5839 /* Calculate the rate factor values to set */
5840 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5841 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5842 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5844 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5845 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5846 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5847 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5853 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5854 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5857 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5858 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5859 IXGBE_MAX_JUMBO_FRAME_SIZE))
5860 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5861 IXGBE_MMW_SIZE_JUMBO_FRAME);
5863 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5864 IXGBE_MMW_SIZE_DEFAULT);
5866 /* Set RTTBCNRC of queue X */
5867 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5868 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5869 IXGBE_WRITE_FLUSH(hw);
5875 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5876 __attribute__((unused)) uint32_t index,
5877 __attribute__((unused)) uint32_t pool)
5879 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5883 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5884 * operation. Trap this case to avoid exhausting the [very limited]
5885 * set of PF resources used to store VF MAC addresses.
5887 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5889 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5892 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5896 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5898 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5899 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5900 struct ether_addr *mac_addr;
5905 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5906 * not support the deletion of a given MAC address.
5907 * Instead, it imposes to delete all MAC addresses, then to add again
5908 * all MAC addresses with the exception of the one to be deleted.
5910 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5913 * Add again all MAC addresses, with the exception of the deleted one
5914 * and of the permanent MAC address.
5916 for (i = 0, mac_addr = dev->data->mac_addrs;
5917 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5918 /* Skip the deleted MAC address */
5921 /* Skip NULL MAC addresses */
5922 if (is_zero_ether_addr(mac_addr))
5924 /* Skip the permanent MAC address */
5925 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5927 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5930 "Adding again MAC address "
5931 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5933 mac_addr->addr_bytes[0],
5934 mac_addr->addr_bytes[1],
5935 mac_addr->addr_bytes[2],
5936 mac_addr->addr_bytes[3],
5937 mac_addr->addr_bytes[4],
5938 mac_addr->addr_bytes[5],
5944 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5946 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5948 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5951 #define MAC_TYPE_FILTER_SUP(type) do {\
5952 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5953 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5954 (type) != ixgbe_mac_X550EM_a)\
5959 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5960 struct rte_eth_syn_filter *filter,
5963 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5964 struct ixgbe_filter_info *filter_info =
5965 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5969 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5972 syn_info = filter_info->syn_info;
5975 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5977 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5978 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5980 if (filter->hig_pri)
5981 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5983 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5985 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5986 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5988 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5991 filter_info->syn_info = synqf;
5992 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5993 IXGBE_WRITE_FLUSH(hw);
5998 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5999 struct rte_eth_syn_filter *filter)
6001 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6002 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6004 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6005 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6006 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6013 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6014 enum rte_filter_op filter_op,
6017 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6020 MAC_TYPE_FILTER_SUP(hw->mac.type);
6022 if (filter_op == RTE_ETH_FILTER_NOP)
6026 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6031 switch (filter_op) {
6032 case RTE_ETH_FILTER_ADD:
6033 ret = ixgbe_syn_filter_set(dev,
6034 (struct rte_eth_syn_filter *)arg,
6037 case RTE_ETH_FILTER_DELETE:
6038 ret = ixgbe_syn_filter_set(dev,
6039 (struct rte_eth_syn_filter *)arg,
6042 case RTE_ETH_FILTER_GET:
6043 ret = ixgbe_syn_filter_get(dev,
6044 (struct rte_eth_syn_filter *)arg);
6047 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6056 static inline enum ixgbe_5tuple_protocol
6057 convert_protocol_type(uint8_t protocol_value)
6059 if (protocol_value == IPPROTO_TCP)
6060 return IXGBE_FILTER_PROTOCOL_TCP;
6061 else if (protocol_value == IPPROTO_UDP)
6062 return IXGBE_FILTER_PROTOCOL_UDP;
6063 else if (protocol_value == IPPROTO_SCTP)
6064 return IXGBE_FILTER_PROTOCOL_SCTP;
6066 return IXGBE_FILTER_PROTOCOL_NONE;
6069 /* inject a 5-tuple filter to HW */
6071 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6072 struct ixgbe_5tuple_filter *filter)
6074 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6076 uint32_t ftqf, sdpqf;
6077 uint32_t l34timir = 0;
6078 uint8_t mask = 0xff;
6082 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6083 IXGBE_SDPQF_DSTPORT_SHIFT);
6084 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6086 ftqf = (uint32_t)(filter->filter_info.proto &
6087 IXGBE_FTQF_PROTOCOL_MASK);
6088 ftqf |= (uint32_t)((filter->filter_info.priority &
6089 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6090 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6091 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6092 if (filter->filter_info.dst_ip_mask == 0)
6093 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6094 if (filter->filter_info.src_port_mask == 0)
6095 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6096 if (filter->filter_info.dst_port_mask == 0)
6097 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6098 if (filter->filter_info.proto_mask == 0)
6099 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6100 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6101 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6102 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6104 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6105 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6106 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6107 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6109 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6110 l34timir |= (uint32_t)(filter->queue <<
6111 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6112 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6116 * add a 5tuple filter
6119 * dev: Pointer to struct rte_eth_dev.
6120 * index: the index the filter allocates.
6121 * filter: ponter to the filter that will be added.
6122 * rx_queue: the queue id the filter assigned to.
6125 * - On success, zero.
6126 * - On failure, a negative value.
6129 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6130 struct ixgbe_5tuple_filter *filter)
6132 struct ixgbe_filter_info *filter_info =
6133 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6137 * look for an unused 5tuple filter index,
6138 * and insert the filter to list.
6140 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6141 idx = i / (sizeof(uint32_t) * NBBY);
6142 shift = i % (sizeof(uint32_t) * NBBY);
6143 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6144 filter_info->fivetuple_mask[idx] |= 1 << shift;
6146 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6152 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6153 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6157 ixgbe_inject_5tuple_filter(dev, filter);
6163 * remove a 5tuple filter
6166 * dev: Pointer to struct rte_eth_dev.
6167 * filter: the pointer of the filter will be removed.
6170 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6171 struct ixgbe_5tuple_filter *filter)
6173 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6174 struct ixgbe_filter_info *filter_info =
6175 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6176 uint16_t index = filter->index;
6178 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6179 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6180 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6183 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6184 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6185 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6186 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6187 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6191 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6193 struct ixgbe_hw *hw;
6194 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6196 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6198 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6201 /* refuse mtu that requires the support of scattered packets when this
6202 * feature has not been enabled before.
6204 if (!dev->data->scattered_rx &&
6205 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6206 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6210 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6211 * request of the version 2.0 of the mailbox API.
6212 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6213 * of the mailbox API.
6214 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6215 * prior to 3.11.33 which contains the following change:
6216 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6218 ixgbevf_rlpml_set_vf(hw, max_frame);
6220 /* update max frame size */
6221 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6225 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
6226 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6230 static inline struct ixgbe_5tuple_filter *
6231 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6232 struct ixgbe_5tuple_filter_info *key)
6234 struct ixgbe_5tuple_filter *it;
6236 TAILQ_FOREACH(it, filter_list, entries) {
6237 if (memcmp(key, &it->filter_info,
6238 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6245 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6247 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6248 struct ixgbe_5tuple_filter_info *filter_info)
6250 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6251 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6252 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6255 switch (filter->dst_ip_mask) {
6257 filter_info->dst_ip_mask = 0;
6258 filter_info->dst_ip = filter->dst_ip;
6261 filter_info->dst_ip_mask = 1;
6264 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6268 switch (filter->src_ip_mask) {
6270 filter_info->src_ip_mask = 0;
6271 filter_info->src_ip = filter->src_ip;
6274 filter_info->src_ip_mask = 1;
6277 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6281 switch (filter->dst_port_mask) {
6283 filter_info->dst_port_mask = 0;
6284 filter_info->dst_port = filter->dst_port;
6287 filter_info->dst_port_mask = 1;
6290 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6294 switch (filter->src_port_mask) {
6296 filter_info->src_port_mask = 0;
6297 filter_info->src_port = filter->src_port;
6300 filter_info->src_port_mask = 1;
6303 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6307 switch (filter->proto_mask) {
6309 filter_info->proto_mask = 0;
6310 filter_info->proto =
6311 convert_protocol_type(filter->proto);
6314 filter_info->proto_mask = 1;
6317 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6321 filter_info->priority = (uint8_t)filter->priority;
6326 * add or delete a ntuple filter
6329 * dev: Pointer to struct rte_eth_dev.
6330 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6331 * add: if true, add filter, if false, remove filter
6334 * - On success, zero.
6335 * - On failure, a negative value.
6338 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6339 struct rte_eth_ntuple_filter *ntuple_filter,
6342 struct ixgbe_filter_info *filter_info =
6343 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6344 struct ixgbe_5tuple_filter_info filter_5tuple;
6345 struct ixgbe_5tuple_filter *filter;
6348 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6349 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6353 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6354 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6358 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6360 if (filter != NULL && add) {
6361 PMD_DRV_LOG(ERR, "filter exists.");
6364 if (filter == NULL && !add) {
6365 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6370 filter = rte_zmalloc("ixgbe_5tuple_filter",
6371 sizeof(struct ixgbe_5tuple_filter), 0);
6374 (void)rte_memcpy(&filter->filter_info,
6376 sizeof(struct ixgbe_5tuple_filter_info));
6377 filter->queue = ntuple_filter->queue;
6378 ret = ixgbe_add_5tuple_filter(dev, filter);
6384 ixgbe_remove_5tuple_filter(dev, filter);
6390 * get a ntuple filter
6393 * dev: Pointer to struct rte_eth_dev.
6394 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6397 * - On success, zero.
6398 * - On failure, a negative value.
6401 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6402 struct rte_eth_ntuple_filter *ntuple_filter)
6404 struct ixgbe_filter_info *filter_info =
6405 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6406 struct ixgbe_5tuple_filter_info filter_5tuple;
6407 struct ixgbe_5tuple_filter *filter;
6410 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6411 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6415 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6416 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6420 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6422 if (filter == NULL) {
6423 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6426 ntuple_filter->queue = filter->queue;
6431 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6432 * @dev: pointer to rte_eth_dev structure
6433 * @filter_op:operation will be taken.
6434 * @arg: a pointer to specific structure corresponding to the filter_op
6437 * - On success, zero.
6438 * - On failure, a negative value.
6441 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6442 enum rte_filter_op filter_op,
6445 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6448 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6450 if (filter_op == RTE_ETH_FILTER_NOP)
6454 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6459 switch (filter_op) {
6460 case RTE_ETH_FILTER_ADD:
6461 ret = ixgbe_add_del_ntuple_filter(dev,
6462 (struct rte_eth_ntuple_filter *)arg,
6465 case RTE_ETH_FILTER_DELETE:
6466 ret = ixgbe_add_del_ntuple_filter(dev,
6467 (struct rte_eth_ntuple_filter *)arg,
6470 case RTE_ETH_FILTER_GET:
6471 ret = ixgbe_get_ntuple_filter(dev,
6472 (struct rte_eth_ntuple_filter *)arg);
6475 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6483 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6484 struct rte_eth_ethertype_filter *filter,
6487 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6488 struct ixgbe_filter_info *filter_info =
6489 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6493 struct ixgbe_ethertype_filter ethertype_filter;
6495 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6498 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6499 filter->ether_type == ETHER_TYPE_IPv6) {
6500 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6501 " ethertype filter.", filter->ether_type);
6505 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6506 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6509 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6510 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6514 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6515 if (ret >= 0 && add) {
6516 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6517 filter->ether_type);
6520 if (ret < 0 && !add) {
6521 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6522 filter->ether_type);
6527 etqf = IXGBE_ETQF_FILTER_EN;
6528 etqf |= (uint32_t)filter->ether_type;
6529 etqs |= (uint32_t)((filter->queue <<
6530 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6531 IXGBE_ETQS_RX_QUEUE);
6532 etqs |= IXGBE_ETQS_QUEUE_EN;
6534 ethertype_filter.ethertype = filter->ether_type;
6535 ethertype_filter.etqf = etqf;
6536 ethertype_filter.etqs = etqs;
6537 ethertype_filter.conf = FALSE;
6538 ret = ixgbe_ethertype_filter_insert(filter_info,
6541 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6545 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6549 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6550 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6551 IXGBE_WRITE_FLUSH(hw);
6557 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6558 struct rte_eth_ethertype_filter *filter)
6560 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6561 struct ixgbe_filter_info *filter_info =
6562 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6563 uint32_t etqf, etqs;
6566 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6568 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6569 filter->ether_type);
6573 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6574 if (etqf & IXGBE_ETQF_FILTER_EN) {
6575 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6576 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6578 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6579 IXGBE_ETQS_RX_QUEUE_SHIFT;
6586 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6587 * @dev: pointer to rte_eth_dev structure
6588 * @filter_op:operation will be taken.
6589 * @arg: a pointer to specific structure corresponding to the filter_op
6592 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6593 enum rte_filter_op filter_op,
6596 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6599 MAC_TYPE_FILTER_SUP(hw->mac.type);
6601 if (filter_op == RTE_ETH_FILTER_NOP)
6605 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6610 switch (filter_op) {
6611 case RTE_ETH_FILTER_ADD:
6612 ret = ixgbe_add_del_ethertype_filter(dev,
6613 (struct rte_eth_ethertype_filter *)arg,
6616 case RTE_ETH_FILTER_DELETE:
6617 ret = ixgbe_add_del_ethertype_filter(dev,
6618 (struct rte_eth_ethertype_filter *)arg,
6621 case RTE_ETH_FILTER_GET:
6622 ret = ixgbe_get_ethertype_filter(dev,
6623 (struct rte_eth_ethertype_filter *)arg);
6626 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6634 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6635 enum rte_filter_type filter_type,
6636 enum rte_filter_op filter_op,
6641 switch (filter_type) {
6642 case RTE_ETH_FILTER_NTUPLE:
6643 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6645 case RTE_ETH_FILTER_ETHERTYPE:
6646 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6648 case RTE_ETH_FILTER_SYN:
6649 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6651 case RTE_ETH_FILTER_FDIR:
6652 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6654 case RTE_ETH_FILTER_L2_TUNNEL:
6655 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6657 case RTE_ETH_FILTER_GENERIC:
6658 if (filter_op != RTE_ETH_FILTER_GET)
6660 *(const void **)arg = &ixgbe_flow_ops;
6663 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6673 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6674 u8 **mc_addr_ptr, u32 *vmdq)
6679 mc_addr = *mc_addr_ptr;
6680 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6685 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6686 struct ether_addr *mc_addr_set,
6687 uint32_t nb_mc_addr)
6689 struct ixgbe_hw *hw;
6692 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6693 mc_addr_list = (u8 *)mc_addr_set;
6694 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6695 ixgbe_dev_addr_list_itr, TRUE);
6699 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6701 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6702 uint64_t systime_cycles;
6704 switch (hw->mac.type) {
6705 case ixgbe_mac_X550:
6706 case ixgbe_mac_X550EM_x:
6707 case ixgbe_mac_X550EM_a:
6708 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6709 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6710 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6714 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6715 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6719 return systime_cycles;
6723 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6725 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6726 uint64_t rx_tstamp_cycles;
6728 switch (hw->mac.type) {
6729 case ixgbe_mac_X550:
6730 case ixgbe_mac_X550EM_x:
6731 case ixgbe_mac_X550EM_a:
6732 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6733 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6734 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6738 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6739 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6740 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6744 return rx_tstamp_cycles;
6748 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6750 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6751 uint64_t tx_tstamp_cycles;
6753 switch (hw->mac.type) {
6754 case ixgbe_mac_X550:
6755 case ixgbe_mac_X550EM_x:
6756 case ixgbe_mac_X550EM_a:
6757 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6758 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6759 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6763 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6764 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6765 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6769 return tx_tstamp_cycles;
6773 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6775 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6776 struct ixgbe_adapter *adapter =
6777 (struct ixgbe_adapter *)dev->data->dev_private;
6778 struct rte_eth_link link;
6779 uint32_t incval = 0;
6782 /* Get current link speed. */
6783 memset(&link, 0, sizeof(link));
6784 ixgbe_dev_link_update(dev, 1);
6785 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6787 switch (link.link_speed) {
6788 case ETH_SPEED_NUM_100M:
6789 incval = IXGBE_INCVAL_100;
6790 shift = IXGBE_INCVAL_SHIFT_100;
6792 case ETH_SPEED_NUM_1G:
6793 incval = IXGBE_INCVAL_1GB;
6794 shift = IXGBE_INCVAL_SHIFT_1GB;
6796 case ETH_SPEED_NUM_10G:
6798 incval = IXGBE_INCVAL_10GB;
6799 shift = IXGBE_INCVAL_SHIFT_10GB;
6803 switch (hw->mac.type) {
6804 case ixgbe_mac_X550:
6805 case ixgbe_mac_X550EM_x:
6806 case ixgbe_mac_X550EM_a:
6807 /* Independent of link speed. */
6809 /* Cycles read will be interpreted as ns. */
6812 case ixgbe_mac_X540:
6813 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6815 case ixgbe_mac_82599EB:
6816 incval >>= IXGBE_INCVAL_SHIFT_82599;
6817 shift -= IXGBE_INCVAL_SHIFT_82599;
6818 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6819 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6822 /* Not supported. */
6826 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6827 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6828 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6830 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6831 adapter->systime_tc.cc_shift = shift;
6832 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6834 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6835 adapter->rx_tstamp_tc.cc_shift = shift;
6836 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6838 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6839 adapter->tx_tstamp_tc.cc_shift = shift;
6840 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6844 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6846 struct ixgbe_adapter *adapter =
6847 (struct ixgbe_adapter *)dev->data->dev_private;
6849 adapter->systime_tc.nsec += delta;
6850 adapter->rx_tstamp_tc.nsec += delta;
6851 adapter->tx_tstamp_tc.nsec += delta;
6857 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6860 struct ixgbe_adapter *adapter =
6861 (struct ixgbe_adapter *)dev->data->dev_private;
6863 ns = rte_timespec_to_ns(ts);
6864 /* Set the timecounters to a new value. */
6865 adapter->systime_tc.nsec = ns;
6866 adapter->rx_tstamp_tc.nsec = ns;
6867 adapter->tx_tstamp_tc.nsec = ns;
6873 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6875 uint64_t ns, systime_cycles;
6876 struct ixgbe_adapter *adapter =
6877 (struct ixgbe_adapter *)dev->data->dev_private;
6879 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6880 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6881 *ts = rte_ns_to_timespec(ns);
6887 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6889 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6893 /* Stop the timesync system time. */
6894 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6895 /* Reset the timesync system time value. */
6896 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6897 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6899 /* Enable system time for platforms where it isn't on by default. */
6900 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6901 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6902 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6904 ixgbe_start_timecounters(dev);
6906 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6907 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6909 IXGBE_ETQF_FILTER_EN |
6912 /* Enable timestamping of received PTP packets. */
6913 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6914 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6915 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6917 /* Enable timestamping of transmitted PTP packets. */
6918 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6919 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6920 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6922 IXGBE_WRITE_FLUSH(hw);
6928 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6930 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6933 /* Disable timestamping of transmitted PTP packets. */
6934 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6935 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6936 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6938 /* Disable timestamping of received PTP packets. */
6939 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6940 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6941 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6943 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6944 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6946 /* Stop incrementating the System Time registers. */
6947 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6953 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6954 struct timespec *timestamp,
6955 uint32_t flags __rte_unused)
6957 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6958 struct ixgbe_adapter *adapter =
6959 (struct ixgbe_adapter *)dev->data->dev_private;
6960 uint32_t tsync_rxctl;
6961 uint64_t rx_tstamp_cycles;
6964 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6965 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6968 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6969 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6970 *timestamp = rte_ns_to_timespec(ns);
6976 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6977 struct timespec *timestamp)
6979 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6980 struct ixgbe_adapter *adapter =
6981 (struct ixgbe_adapter *)dev->data->dev_private;
6982 uint32_t tsync_txctl;
6983 uint64_t tx_tstamp_cycles;
6986 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6987 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6990 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6991 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6992 *timestamp = rte_ns_to_timespec(ns);
6998 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7000 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7003 const struct reg_info *reg_group;
7004 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7005 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7007 while ((reg_group = reg_set[g_ind++]))
7008 count += ixgbe_regs_group_count(reg_group);
7014 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7018 const struct reg_info *reg_group;
7020 while ((reg_group = ixgbevf_regs[g_ind++]))
7021 count += ixgbe_regs_group_count(reg_group);
7027 ixgbe_get_regs(struct rte_eth_dev *dev,
7028 struct rte_dev_reg_info *regs)
7030 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7031 uint32_t *data = regs->data;
7034 const struct reg_info *reg_group;
7035 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7036 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7039 regs->length = ixgbe_get_reg_length(dev);
7040 regs->width = sizeof(uint32_t);
7044 /* Support only full register dump */
7045 if ((regs->length == 0) ||
7046 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7047 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7049 while ((reg_group = reg_set[g_ind++]))
7050 count += ixgbe_read_regs_group(dev, &data[count],
7059 ixgbevf_get_regs(struct rte_eth_dev *dev,
7060 struct rte_dev_reg_info *regs)
7062 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7063 uint32_t *data = regs->data;
7066 const struct reg_info *reg_group;
7069 regs->length = ixgbevf_get_reg_length(dev);
7070 regs->width = sizeof(uint32_t);
7074 /* Support only full register dump */
7075 if ((regs->length == 0) ||
7076 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7077 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7079 while ((reg_group = ixgbevf_regs[g_ind++]))
7080 count += ixgbe_read_regs_group(dev, &data[count],
7089 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7091 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7093 /* Return unit is byte count */
7094 return hw->eeprom.word_size * 2;
7098 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7099 struct rte_dev_eeprom_info *in_eeprom)
7101 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7102 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7103 uint16_t *data = in_eeprom->data;
7106 first = in_eeprom->offset >> 1;
7107 length = in_eeprom->length >> 1;
7108 if ((first > hw->eeprom.word_size) ||
7109 ((first + length) > hw->eeprom.word_size))
7112 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7114 return eeprom->ops.read_buffer(hw, first, length, data);
7118 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7119 struct rte_dev_eeprom_info *in_eeprom)
7121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7123 uint16_t *data = in_eeprom->data;
7126 first = in_eeprom->offset >> 1;
7127 length = in_eeprom->length >> 1;
7128 if ((first > hw->eeprom.word_size) ||
7129 ((first + length) > hw->eeprom.word_size))
7132 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7134 return eeprom->ops.write_buffer(hw, first, length, data);
7138 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7140 case ixgbe_mac_X550:
7141 case ixgbe_mac_X550EM_x:
7142 case ixgbe_mac_X550EM_a:
7143 return ETH_RSS_RETA_SIZE_512;
7144 case ixgbe_mac_X550_vf:
7145 case ixgbe_mac_X550EM_x_vf:
7146 case ixgbe_mac_X550EM_a_vf:
7147 return ETH_RSS_RETA_SIZE_64;
7149 return ETH_RSS_RETA_SIZE_128;
7154 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7156 case ixgbe_mac_X550:
7157 case ixgbe_mac_X550EM_x:
7158 case ixgbe_mac_X550EM_a:
7159 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7160 return IXGBE_RETA(reta_idx >> 2);
7162 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7163 case ixgbe_mac_X550_vf:
7164 case ixgbe_mac_X550EM_x_vf:
7165 case ixgbe_mac_X550EM_a_vf:
7166 return IXGBE_VFRETA(reta_idx >> 2);
7168 return IXGBE_RETA(reta_idx >> 2);
7173 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7175 case ixgbe_mac_X550_vf:
7176 case ixgbe_mac_X550EM_x_vf:
7177 case ixgbe_mac_X550EM_a_vf:
7178 return IXGBE_VFMRQC;
7185 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7187 case ixgbe_mac_X550_vf:
7188 case ixgbe_mac_X550EM_x_vf:
7189 case ixgbe_mac_X550EM_a_vf:
7190 return IXGBE_VFRSSRK(i);
7192 return IXGBE_RSSRK(i);
7197 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7199 case ixgbe_mac_82599_vf:
7200 case ixgbe_mac_X540_vf:
7208 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7209 struct rte_eth_dcb_info *dcb_info)
7211 struct ixgbe_dcb_config *dcb_config =
7212 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7213 struct ixgbe_dcb_tc_config *tc;
7216 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7217 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7219 dcb_info->nb_tcs = 1;
7221 if (dcb_config->vt_mode) { /* vt is enabled*/
7222 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7223 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7224 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7225 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7226 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7227 for (j = 0; j < dcb_info->nb_tcs; j++) {
7228 dcb_info->tc_queue.tc_rxq[i][j].base =
7229 i * dcb_info->nb_tcs + j;
7230 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7231 dcb_info->tc_queue.tc_txq[i][j].base =
7232 i * dcb_info->nb_tcs + j;
7233 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7236 } else { /* vt is disabled*/
7237 struct rte_eth_dcb_rx_conf *rx_conf =
7238 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7239 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7240 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7241 if (dcb_info->nb_tcs == ETH_4_TCS) {
7242 for (i = 0; i < dcb_info->nb_tcs; i++) {
7243 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7244 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7246 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7247 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7248 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7249 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7250 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7251 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7252 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7253 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7254 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7255 for (i = 0; i < dcb_info->nb_tcs; i++) {
7256 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7257 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7259 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7260 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7261 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7262 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7263 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7264 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7265 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7266 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7267 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7268 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7269 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7270 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7271 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7272 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7273 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7274 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7277 for (i = 0; i < dcb_info->nb_tcs; i++) {
7278 tc = &dcb_config->tc_config[i];
7279 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7284 /* Update e-tag ether type */
7286 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7287 uint16_t ether_type)
7289 uint32_t etag_etype;
7291 if (hw->mac.type != ixgbe_mac_X550 &&
7292 hw->mac.type != ixgbe_mac_X550EM_x &&
7293 hw->mac.type != ixgbe_mac_X550EM_a) {
7297 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7298 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7299 etag_etype |= ether_type;
7300 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7301 IXGBE_WRITE_FLUSH(hw);
7306 /* Config l2 tunnel ether type */
7308 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7309 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7312 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7313 struct ixgbe_l2_tn_info *l2_tn_info =
7314 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7316 if (l2_tunnel == NULL)
7319 switch (l2_tunnel->l2_tunnel_type) {
7320 case RTE_L2_TUNNEL_TYPE_E_TAG:
7321 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7322 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7325 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7333 /* Enable e-tag tunnel */
7335 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7337 uint32_t etag_etype;
7339 if (hw->mac.type != ixgbe_mac_X550 &&
7340 hw->mac.type != ixgbe_mac_X550EM_x &&
7341 hw->mac.type != ixgbe_mac_X550EM_a) {
7345 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7346 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7347 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7348 IXGBE_WRITE_FLUSH(hw);
7353 /* Enable l2 tunnel */
7355 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7356 enum rte_eth_tunnel_type l2_tunnel_type)
7359 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7360 struct ixgbe_l2_tn_info *l2_tn_info =
7361 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7363 switch (l2_tunnel_type) {
7364 case RTE_L2_TUNNEL_TYPE_E_TAG:
7365 l2_tn_info->e_tag_en = TRUE;
7366 ret = ixgbe_e_tag_enable(hw);
7369 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7377 /* Disable e-tag tunnel */
7379 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7381 uint32_t etag_etype;
7383 if (hw->mac.type != ixgbe_mac_X550 &&
7384 hw->mac.type != ixgbe_mac_X550EM_x &&
7385 hw->mac.type != ixgbe_mac_X550EM_a) {
7389 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7390 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7391 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7392 IXGBE_WRITE_FLUSH(hw);
7397 /* Disable l2 tunnel */
7399 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7400 enum rte_eth_tunnel_type l2_tunnel_type)
7403 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7404 struct ixgbe_l2_tn_info *l2_tn_info =
7405 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7407 switch (l2_tunnel_type) {
7408 case RTE_L2_TUNNEL_TYPE_E_TAG:
7409 l2_tn_info->e_tag_en = FALSE;
7410 ret = ixgbe_e_tag_disable(hw);
7413 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7422 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7423 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7426 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7427 uint32_t i, rar_entries;
7428 uint32_t rar_low, rar_high;
7430 if (hw->mac.type != ixgbe_mac_X550 &&
7431 hw->mac.type != ixgbe_mac_X550EM_x &&
7432 hw->mac.type != ixgbe_mac_X550EM_a) {
7436 rar_entries = ixgbe_get_num_rx_addrs(hw);
7438 for (i = 1; i < rar_entries; i++) {
7439 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7440 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7441 if ((rar_high & IXGBE_RAH_AV) &&
7442 (rar_high & IXGBE_RAH_ADTYPE) &&
7443 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7444 l2_tunnel->tunnel_id)) {
7445 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7446 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7448 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7458 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7459 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7462 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7463 uint32_t i, rar_entries;
7464 uint32_t rar_low, rar_high;
7466 if (hw->mac.type != ixgbe_mac_X550 &&
7467 hw->mac.type != ixgbe_mac_X550EM_x &&
7468 hw->mac.type != ixgbe_mac_X550EM_a) {
7472 /* One entry for one tunnel. Try to remove potential existing entry. */
7473 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7475 rar_entries = ixgbe_get_num_rx_addrs(hw);
7477 for (i = 1; i < rar_entries; i++) {
7478 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7479 if (rar_high & IXGBE_RAH_AV) {
7482 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7483 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7484 rar_low = l2_tunnel->tunnel_id;
7486 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7487 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7493 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7494 " Please remove a rule before adding a new one.");
7498 static inline struct ixgbe_l2_tn_filter *
7499 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7500 struct ixgbe_l2_tn_key *key)
7504 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7508 return l2_tn_info->hash_map[ret];
7512 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7513 struct ixgbe_l2_tn_filter *l2_tn_filter)
7517 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7518 &l2_tn_filter->key);
7522 "Failed to insert L2 tunnel filter"
7523 " to hash table %d!",
7528 l2_tn_info->hash_map[ret] = l2_tn_filter;
7530 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7536 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7537 struct ixgbe_l2_tn_key *key)
7540 struct ixgbe_l2_tn_filter *l2_tn_filter;
7542 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7546 "No such L2 tunnel filter to delete %d!",
7551 l2_tn_filter = l2_tn_info->hash_map[ret];
7552 l2_tn_info->hash_map[ret] = NULL;
7554 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7555 rte_free(l2_tn_filter);
7560 /* Add l2 tunnel filter */
7562 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7563 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7567 struct ixgbe_l2_tn_info *l2_tn_info =
7568 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7569 struct ixgbe_l2_tn_key key;
7570 struct ixgbe_l2_tn_filter *node;
7573 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7574 key.tn_id = l2_tunnel->tunnel_id;
7576 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7580 "The L2 tunnel filter already exists!");
7584 node = rte_zmalloc("ixgbe_l2_tn",
7585 sizeof(struct ixgbe_l2_tn_filter),
7590 (void)rte_memcpy(&node->key,
7592 sizeof(struct ixgbe_l2_tn_key));
7593 node->pool = l2_tunnel->pool;
7594 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7601 switch (l2_tunnel->l2_tunnel_type) {
7602 case RTE_L2_TUNNEL_TYPE_E_TAG:
7603 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7606 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7611 if ((!restore) && (ret < 0))
7612 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7617 /* Delete l2 tunnel filter */
7619 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7620 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7623 struct ixgbe_l2_tn_info *l2_tn_info =
7624 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7625 struct ixgbe_l2_tn_key key;
7627 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7628 key.tn_id = l2_tunnel->tunnel_id;
7629 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7633 switch (l2_tunnel->l2_tunnel_type) {
7634 case RTE_L2_TUNNEL_TYPE_E_TAG:
7635 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7638 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7647 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7648 * @dev: pointer to rte_eth_dev structure
7649 * @filter_op:operation will be taken.
7650 * @arg: a pointer to specific structure corresponding to the filter_op
7653 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7654 enum rte_filter_op filter_op,
7659 if (filter_op == RTE_ETH_FILTER_NOP)
7663 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7668 switch (filter_op) {
7669 case RTE_ETH_FILTER_ADD:
7670 ret = ixgbe_dev_l2_tunnel_filter_add
7672 (struct rte_eth_l2_tunnel_conf *)arg,
7675 case RTE_ETH_FILTER_DELETE:
7676 ret = ixgbe_dev_l2_tunnel_filter_del
7678 (struct rte_eth_l2_tunnel_conf *)arg);
7681 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7689 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7693 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7695 if (hw->mac.type != ixgbe_mac_X550 &&
7696 hw->mac.type != ixgbe_mac_X550EM_x &&
7697 hw->mac.type != ixgbe_mac_X550EM_a) {
7701 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7702 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7704 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7705 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7710 /* Enable l2 tunnel forwarding */
7712 ixgbe_dev_l2_tunnel_forwarding_enable
7713 (struct rte_eth_dev *dev,
7714 enum rte_eth_tunnel_type l2_tunnel_type)
7716 struct ixgbe_l2_tn_info *l2_tn_info =
7717 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7720 switch (l2_tunnel_type) {
7721 case RTE_L2_TUNNEL_TYPE_E_TAG:
7722 l2_tn_info->e_tag_fwd_en = TRUE;
7723 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7726 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7734 /* Disable l2 tunnel forwarding */
7736 ixgbe_dev_l2_tunnel_forwarding_disable
7737 (struct rte_eth_dev *dev,
7738 enum rte_eth_tunnel_type l2_tunnel_type)
7740 struct ixgbe_l2_tn_info *l2_tn_info =
7741 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7744 switch (l2_tunnel_type) {
7745 case RTE_L2_TUNNEL_TYPE_E_TAG:
7746 l2_tn_info->e_tag_fwd_en = FALSE;
7747 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7750 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7759 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7760 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7763 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7765 uint32_t vmtir, vmvir;
7766 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7768 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7770 "VF id %u should be less than %u",
7776 if (hw->mac.type != ixgbe_mac_X550 &&
7777 hw->mac.type != ixgbe_mac_X550EM_x &&
7778 hw->mac.type != ixgbe_mac_X550EM_a) {
7783 vmtir = l2_tunnel->tunnel_id;
7787 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7789 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7790 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7792 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7793 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7798 /* Enable l2 tunnel tag insertion */
7800 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7801 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7805 switch (l2_tunnel->l2_tunnel_type) {
7806 case RTE_L2_TUNNEL_TYPE_E_TAG:
7807 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7810 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7818 /* Disable l2 tunnel tag insertion */
7820 ixgbe_dev_l2_tunnel_insertion_disable
7821 (struct rte_eth_dev *dev,
7822 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7826 switch (l2_tunnel->l2_tunnel_type) {
7827 case RTE_L2_TUNNEL_TYPE_E_TAG:
7828 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7831 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7840 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7845 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7847 if (hw->mac.type != ixgbe_mac_X550 &&
7848 hw->mac.type != ixgbe_mac_X550EM_x &&
7849 hw->mac.type != ixgbe_mac_X550EM_a) {
7853 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7855 qde |= IXGBE_QDE_STRIP_TAG;
7857 qde &= ~IXGBE_QDE_STRIP_TAG;
7858 qde &= ~IXGBE_QDE_READ;
7859 qde |= IXGBE_QDE_WRITE;
7860 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7865 /* Enable l2 tunnel tag stripping */
7867 ixgbe_dev_l2_tunnel_stripping_enable
7868 (struct rte_eth_dev *dev,
7869 enum rte_eth_tunnel_type l2_tunnel_type)
7873 switch (l2_tunnel_type) {
7874 case RTE_L2_TUNNEL_TYPE_E_TAG:
7875 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7878 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7886 /* Disable l2 tunnel tag stripping */
7888 ixgbe_dev_l2_tunnel_stripping_disable
7889 (struct rte_eth_dev *dev,
7890 enum rte_eth_tunnel_type l2_tunnel_type)
7894 switch (l2_tunnel_type) {
7895 case RTE_L2_TUNNEL_TYPE_E_TAG:
7896 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7899 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7907 /* Enable/disable l2 tunnel offload functions */
7909 ixgbe_dev_l2_tunnel_offload_set
7910 (struct rte_eth_dev *dev,
7911 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7917 if (l2_tunnel == NULL)
7921 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7923 ret = ixgbe_dev_l2_tunnel_enable(
7925 l2_tunnel->l2_tunnel_type);
7927 ret = ixgbe_dev_l2_tunnel_disable(
7929 l2_tunnel->l2_tunnel_type);
7932 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7934 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7938 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7943 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7945 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7947 l2_tunnel->l2_tunnel_type);
7949 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7951 l2_tunnel->l2_tunnel_type);
7954 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7956 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7958 l2_tunnel->l2_tunnel_type);
7960 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7962 l2_tunnel->l2_tunnel_type);
7969 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7972 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7973 IXGBE_WRITE_FLUSH(hw);
7978 /* There's only one register for VxLAN UDP port.
7979 * So, we cannot add several ports. Will update it.
7982 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7986 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7990 return ixgbe_update_vxlan_port(hw, port);
7993 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7994 * UDP port, it must have a value.
7995 * So, will reset it to the original value 0.
7998 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8003 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8005 if (cur_port != port) {
8006 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8010 return ixgbe_update_vxlan_port(hw, 0);
8013 /* Add UDP tunneling port */
8015 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8016 struct rte_eth_udp_tunnel *udp_tunnel)
8019 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8021 if (hw->mac.type != ixgbe_mac_X550 &&
8022 hw->mac.type != ixgbe_mac_X550EM_x &&
8023 hw->mac.type != ixgbe_mac_X550EM_a) {
8027 if (udp_tunnel == NULL)
8030 switch (udp_tunnel->prot_type) {
8031 case RTE_TUNNEL_TYPE_VXLAN:
8032 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8035 case RTE_TUNNEL_TYPE_GENEVE:
8036 case RTE_TUNNEL_TYPE_TEREDO:
8037 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8042 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8050 /* Remove UDP tunneling port */
8052 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8053 struct rte_eth_udp_tunnel *udp_tunnel)
8056 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8058 if (hw->mac.type != ixgbe_mac_X550 &&
8059 hw->mac.type != ixgbe_mac_X550EM_x &&
8060 hw->mac.type != ixgbe_mac_X550EM_a) {
8064 if (udp_tunnel == NULL)
8067 switch (udp_tunnel->prot_type) {
8068 case RTE_TUNNEL_TYPE_VXLAN:
8069 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8071 case RTE_TUNNEL_TYPE_GENEVE:
8072 case RTE_TUNNEL_TYPE_TEREDO:
8073 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8077 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8086 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8088 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8090 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8094 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8096 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8098 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8101 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8103 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8106 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8109 /* PF reset VF event */
8110 if (in_msg == IXGBE_PF_CONTROL_MSG)
8111 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8115 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8118 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8119 struct ixgbe_interrupt *intr =
8120 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8121 ixgbevf_intr_disable(hw);
8123 /* read-on-clear nic registers here */
8124 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8127 /* only one misc vector supported - mailbox */
8128 eicr &= IXGBE_VTEICR_MASK;
8129 if (eicr == IXGBE_MISC_VEC_ID)
8130 intr->flags |= IXGBE_FLAG_MAILBOX;
8136 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8138 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8139 struct ixgbe_interrupt *intr =
8140 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8142 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8143 ixgbevf_mbx_process(dev);
8144 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8147 ixgbevf_intr_enable(hw);
8153 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8156 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8158 ixgbevf_dev_interrupt_get_status(dev);
8159 ixgbevf_dev_interrupt_action(dev);
8163 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8164 * @hw: pointer to hardware structure
8166 * Stops the transmit data path and waits for the HW to internally empty
8167 * the Tx security block
8169 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8171 #define IXGBE_MAX_SECTX_POLL 40
8176 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8177 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8178 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8179 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8180 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8181 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8183 /* Use interrupt-safe sleep just in case */
8187 /* For informational purposes only */
8188 if (i >= IXGBE_MAX_SECTX_POLL)
8189 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8190 "path fully disabled. Continuing with init.\n");
8192 return IXGBE_SUCCESS;
8196 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8197 * @hw: pointer to hardware structure
8199 * Enables the transmit data path.
8201 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8205 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8206 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8207 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8208 IXGBE_WRITE_FLUSH(hw);
8210 return IXGBE_SUCCESS;
8214 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8216 struct ixgbe_hw *hw;
8217 struct rte_eth_dev *dev;
8220 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8222 dev = &rte_eth_devices[port];
8223 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8225 /* Stop the data paths */
8226 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8230 * As no ixgbe_disable_sec_rx_path equivalent is
8231 * implemented for tx in the base code, and we are
8232 * not allowed to modify the base code in DPDK, so
8233 * just call the hand-written one directly for now.
8234 * The hardware support has been checked by
8235 * ixgbe_disable_sec_rx_path().
8237 ixgbe_disable_sec_tx_path_generic(hw);
8239 /* Enable Ethernet CRC (required by MACsec offload) */
8240 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8241 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8242 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8244 /* Enable the TX and RX crypto engines */
8245 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8246 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8247 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8249 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8250 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8251 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8253 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8254 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8256 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8258 /* Enable SA lookup */
8259 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8260 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8261 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8262 IXGBE_LSECTXCTRL_AUTH;
8263 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8264 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8265 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8266 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8268 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8269 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8270 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8271 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8273 ctrl |= IXGBE_LSECRXCTRL_RP;
8275 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8276 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8278 /* Start the data paths */
8279 ixgbe_enable_sec_rx_path(hw);
8282 * As no ixgbe_enable_sec_rx_path equivalent is
8283 * implemented for tx in the base code, and we are
8284 * not allowed to modify the base code in DPDK, so
8285 * just call the hand-written one directly for now.
8287 ixgbe_enable_sec_tx_path_generic(hw);
8293 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8295 struct ixgbe_hw *hw;
8296 struct rte_eth_dev *dev;
8299 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8301 dev = &rte_eth_devices[port];
8302 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8304 /* Stop the data paths */
8305 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8309 * As no ixgbe_disable_sec_rx_path equivalent is
8310 * implemented for tx in the base code, and we are
8311 * not allowed to modify the base code in DPDK, so
8312 * just call the hand-written one directly for now.
8313 * The hardware support has been checked by
8314 * ixgbe_disable_sec_rx_path().
8316 ixgbe_disable_sec_tx_path_generic(hw);
8318 /* Disable the TX and RX crypto engines */
8319 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8320 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8321 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8323 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8324 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8325 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8327 /* Disable SA lookup */
8328 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8329 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8330 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8331 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8333 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8334 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8335 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8336 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8338 /* Start the data paths */
8339 ixgbe_enable_sec_rx_path(hw);
8342 * As no ixgbe_enable_sec_rx_path equivalent is
8343 * implemented for tx in the base code, and we are
8344 * not allowed to modify the base code in DPDK, so
8345 * just call the hand-written one directly for now.
8347 ixgbe_enable_sec_tx_path_generic(hw);
8353 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8355 struct ixgbe_hw *hw;
8356 struct rte_eth_dev *dev;
8359 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8361 dev = &rte_eth_devices[port];
8362 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8364 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8365 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8367 ctrl = mac[4] | (mac[5] << 8);
8368 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8374 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8376 struct ixgbe_hw *hw;
8377 struct rte_eth_dev *dev;
8380 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8382 dev = &rte_eth_devices[port];
8383 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8385 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8386 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8388 pi = rte_cpu_to_be_16(pi);
8389 ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8390 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8396 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8397 uint32_t pn, uint8_t *key)
8399 struct ixgbe_hw *hw;
8400 struct rte_eth_dev *dev;
8403 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8405 dev = &rte_eth_devices[port];
8406 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8408 if (idx != 0 && idx != 1)
8414 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8416 /* Set the PN and key */
8417 pn = rte_cpu_to_be_32(pn);
8419 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8421 for (i = 0; i < 4; i++) {
8422 ctrl = (key[i * 4 + 0] << 0) |
8423 (key[i * 4 + 1] << 8) |
8424 (key[i * 4 + 2] << 16) |
8425 (key[i * 4 + 3] << 24);
8426 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8429 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8431 for (i = 0; i < 4; i++) {
8432 ctrl = (key[i * 4 + 0] << 0) |
8433 (key[i * 4 + 1] << 8) |
8434 (key[i * 4 + 2] << 16) |
8435 (key[i * 4 + 3] << 24);
8436 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8440 /* Set AN and select the SA */
8441 ctrl = (an << idx * 2) | (idx << 4);
8442 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8448 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8449 uint32_t pn, uint8_t *key)
8451 struct ixgbe_hw *hw;
8452 struct rte_eth_dev *dev;
8455 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8457 dev = &rte_eth_devices[port];
8458 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8460 if (idx != 0 && idx != 1)
8467 pn = rte_cpu_to_be_32(pn);
8468 IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8471 for (i = 0; i < 4; i++) {
8472 ctrl = (key[i * 4 + 0] << 0) |
8473 (key[i * 4 + 1] << 8) |
8474 (key[i * 4 + 2] << 16) |
8475 (key[i * 4 + 3] << 24);
8476 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8479 /* Set the AN and validate the SA */
8480 ctrl = an | (1 << 2);
8481 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8486 /* restore n-tuple filter */
8488 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8490 struct ixgbe_filter_info *filter_info =
8491 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8492 struct ixgbe_5tuple_filter *node;
8494 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8495 ixgbe_inject_5tuple_filter(dev, node);
8499 /* restore ethernet type filter */
8501 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8503 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8504 struct ixgbe_filter_info *filter_info =
8505 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8508 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8509 if (filter_info->ethertype_mask & (1 << i)) {
8510 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8511 filter_info->ethertype_filters[i].etqf);
8512 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8513 filter_info->ethertype_filters[i].etqs);
8514 IXGBE_WRITE_FLUSH(hw);
8519 /* restore SYN filter */
8521 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8523 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8524 struct ixgbe_filter_info *filter_info =
8525 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8528 synqf = filter_info->syn_info;
8530 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8531 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8532 IXGBE_WRITE_FLUSH(hw);
8536 /* restore L2 tunnel filter */
8538 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8540 struct ixgbe_l2_tn_info *l2_tn_info =
8541 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8542 struct ixgbe_l2_tn_filter *node;
8543 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8545 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8546 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8547 l2_tn_conf.tunnel_id = node->key.tn_id;
8548 l2_tn_conf.pool = node->pool;
8549 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8554 ixgbe_filter_restore(struct rte_eth_dev *dev)
8556 ixgbe_ntuple_filter_restore(dev);
8557 ixgbe_ethertype_filter_restore(dev);
8558 ixgbe_syn_filter_restore(dev);
8559 ixgbe_fdir_filter_restore(dev);
8560 ixgbe_l2_tn_filter_restore(dev);
8566 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8568 struct ixgbe_l2_tn_info *l2_tn_info =
8569 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8570 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8572 if (l2_tn_info->e_tag_en)
8573 (void)ixgbe_e_tag_enable(hw);
8575 if (l2_tn_info->e_tag_fwd_en)
8576 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8578 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8581 /* remove all the n-tuple filters */
8583 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8585 struct ixgbe_filter_info *filter_info =
8586 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8587 struct ixgbe_5tuple_filter *p_5tuple;
8589 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8590 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8593 /* remove all the ether type filters */
8595 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8597 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8598 struct ixgbe_filter_info *filter_info =
8599 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8602 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8603 if (filter_info->ethertype_mask & (1 << i) &&
8604 !filter_info->ethertype_filters[i].conf) {
8605 (void)ixgbe_ethertype_filter_remove(filter_info,
8607 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8608 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8609 IXGBE_WRITE_FLUSH(hw);
8614 /* remove the SYN filter */
8616 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8618 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8619 struct ixgbe_filter_info *filter_info =
8620 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8622 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8623 filter_info->syn_info = 0;
8625 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8626 IXGBE_WRITE_FLUSH(hw);
8630 /* remove all the L2 tunnel filters */
8632 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8634 struct ixgbe_l2_tn_info *l2_tn_info =
8635 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8636 struct ixgbe_l2_tn_filter *l2_tn_filter;
8637 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8640 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8641 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8642 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8643 l2_tn_conf.pool = l2_tn_filter->pool;
8644 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8652 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8653 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8654 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8655 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8656 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8657 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");