1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
18 #include <rte_interrupts.h>
20 #include <rte_debug.h>
22 #include <rte_bus_pci.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
31 #include <rte_random.h>
33 #include <rte_hash_crc.h>
34 #ifdef RTE_LIBRTE_SECURITY
35 #include <rte_security_driver.h>
38 #include "ixgbe_logs.h"
39 #include "base/ixgbe_api.h"
40 #include "base/ixgbe_vf.h"
41 #include "base/ixgbe_common.h"
42 #include "ixgbe_ethdev.h"
43 #include "ixgbe_bypass.h"
44 #include "ixgbe_rxtx.h"
45 #include "base/ixgbe_type.h"
46 #include "base/ixgbe_phy.h"
47 #include "ixgbe_regs.h"
50 * High threshold controlling when to start sending XOFF frames. Must be at
51 * least 8 bytes less than receive packet buffer size. This value is in units
54 #define IXGBE_FC_HI 0x80
57 * Low threshold controlling when to start sending XON frames. This value is
58 * in units of 1024 bytes.
60 #define IXGBE_FC_LO 0x40
62 /* Timer value included in XOFF frames. */
63 #define IXGBE_FC_PAUSE 0x680
65 /*Default value of Max Rx Queue*/
66 #define IXGBE_MAX_RX_QUEUE_NUM 128
68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
69 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
70 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
72 #define IXGBE_MMW_SIZE_DEFAULT 0x4
73 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
74 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
77 * Default values for RX/TX configuration
79 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
80 #define IXGBE_DEFAULT_RX_PTHRESH 8
81 #define IXGBE_DEFAULT_RX_HTHRESH 8
82 #define IXGBE_DEFAULT_RX_WTHRESH 0
84 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
85 #define IXGBE_DEFAULT_TX_PTHRESH 32
86 #define IXGBE_DEFAULT_TX_HTHRESH 0
87 #define IXGBE_DEFAULT_TX_WTHRESH 0
88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
90 /* Bit shift and mask */
91 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
92 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
93 #define IXGBE_8_BIT_WIDTH CHAR_BIT
94 #define IXGBE_8_BIT_MASK UINT8_MAX
96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
100 /* Additional timesync values. */
101 #define NSEC_PER_SEC 1000000000L
102 #define IXGBE_INCVAL_10GB 0x66666666
103 #define IXGBE_INCVAL_1GB 0x40000000
104 #define IXGBE_INCVAL_100 0x50000000
105 #define IXGBE_INCVAL_SHIFT_10GB 28
106 #define IXGBE_INCVAL_SHIFT_1GB 24
107 #define IXGBE_INCVAL_SHIFT_100 21
108 #define IXGBE_INCVAL_SHIFT_82599 7
109 #define IXGBE_INCPER_SHIFT_82599 24
111 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
113 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
115 #define IXGBE_ETAG_ETYPE 0x00005084
116 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
117 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
118 #define IXGBE_RAH_ADTYPE 0x40000000
119 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
120 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
123 #define IXGBE_QDE_STRIP_TAG 0x00000004
124 #define IXGBE_VTEICR_MASK 0x07
126 #define IXGBE_EXVET_VET_EXT_SHIFT 16
127 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
148 int wait_to_complete);
149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
150 struct rte_eth_stats *stats);
151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
152 struct rte_eth_xstat *xstats, unsigned n);
153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
154 struct rte_eth_xstat *xstats, unsigned n);
156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
157 uint64_t *values, unsigned int n);
158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
161 struct rte_eth_xstat_name *xstats_names,
163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
164 struct rte_eth_xstat_name *xstats_names, unsigned limit);
165 static int ixgbe_dev_xstats_get_names_by_id(
166 struct rte_eth_dev *dev,
167 struct rte_eth_xstat_name *xstats_names,
170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
177 struct rte_eth_dev_info *dev_info);
178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
180 struct rte_eth_dev_info *dev_info);
181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
184 uint16_t vlan_id, int on);
185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
186 enum rte_vlan_type vlan_type,
188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
189 uint16_t queue, bool on);
190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
204 struct rte_eth_fc_conf *fc_conf);
205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
206 struct rte_eth_fc_conf *fc_conf);
207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
208 struct rte_eth_pfc_conf *pfc_conf);
209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
210 struct rte_eth_rss_reta_entry64 *reta_conf,
212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
221 struct rte_intr_handle *handle);
222 static void ixgbe_dev_interrupt_handler(void *param);
223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
224 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
225 uint32_t index, uint32_t pool);
226 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
227 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
228 struct ether_addr *mac_addr);
229 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
230 static bool is_device_supported(struct rte_eth_dev *dev,
231 struct rte_pci_driver *drv);
233 /* For Virtual Function support */
234 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
235 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
236 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
237 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
238 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
239 int wait_to_complete);
240 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
241 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
242 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
243 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
244 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
245 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
246 struct rte_eth_stats *stats);
247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
249 uint16_t vlan_id, int on);
250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
251 uint16_t queue, int on);
252 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
253 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
260 uint8_t queue, uint8_t msix_vector);
261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
265 /* For Eth VMDQ APIs support */
266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
267 ether_addr * mac_addr, uint8_t on);
268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
269 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
270 struct rte_eth_mirror_conf *mirror_conf,
271 uint8_t rule_id, uint8_t on);
272 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
274 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
276 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
278 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
279 uint8_t queue, uint8_t msix_vector);
280 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
282 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
283 struct ether_addr *mac_addr,
284 uint32_t index, uint32_t pool);
285 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
286 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
287 struct ether_addr *mac_addr);
288 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
289 struct rte_eth_syn_filter *filter);
290 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
291 enum rte_filter_op filter_op,
293 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
294 struct ixgbe_5tuple_filter *filter);
295 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
296 struct ixgbe_5tuple_filter *filter);
297 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
298 enum rte_filter_op filter_op,
300 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
301 struct rte_eth_ntuple_filter *filter);
302 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
303 enum rte_filter_op filter_op,
305 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
306 struct rte_eth_ethertype_filter *filter);
307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
308 enum rte_filter_type filter_type,
309 enum rte_filter_op filter_op,
311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
314 struct ether_addr *mc_addr_set,
315 uint32_t nb_mc_addr);
316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
317 struct rte_eth_dcb_info *dcb_info);
319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
320 static int ixgbe_get_regs(struct rte_eth_dev *dev,
321 struct rte_dev_reg_info *regs);
322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
324 struct rte_dev_eeprom_info *eeprom);
325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
326 struct rte_dev_eeprom_info *eeprom);
328 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
329 struct rte_eth_dev_module_info *modinfo);
330 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
331 struct rte_dev_eeprom_info *info);
333 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
334 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
335 struct rte_dev_reg_info *regs);
337 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
338 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
339 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
340 struct timespec *timestamp,
342 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
343 struct timespec *timestamp);
344 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
345 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
346 struct timespec *timestamp);
347 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
348 const struct timespec *timestamp);
349 static void ixgbevf_dev_interrupt_handler(void *param);
351 static int ixgbe_dev_l2_tunnel_eth_type_conf
352 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
353 static int ixgbe_dev_l2_tunnel_offload_set
354 (struct rte_eth_dev *dev,
355 struct rte_eth_l2_tunnel_conf *l2_tunnel,
358 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
359 enum rte_filter_op filter_op,
362 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
363 struct rte_eth_udp_tunnel *udp_tunnel);
364 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
365 struct rte_eth_udp_tunnel *udp_tunnel);
366 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
367 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
370 * Define VF Stats MACRO for Non "cleared on read" register
372 #define UPDATE_VF_STAT(reg, last, cur) \
374 uint32_t latest = IXGBE_READ_REG(hw, reg); \
375 cur += (latest - last) & UINT_MAX; \
379 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
381 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
382 u64 new_msb = IXGBE_READ_REG(hw, msb); \
383 u64 latest = ((new_msb << 32) | new_lsb); \
384 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
388 #define IXGBE_SET_HWSTRIP(h, q) do {\
389 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
390 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
391 (h)->bitmap[idx] |= 1 << bit;\
394 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
395 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
396 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
397 (h)->bitmap[idx] &= ~(1 << bit);\
400 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
401 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
402 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
403 (r) = (h)->bitmap[idx] >> bit & 1;\
406 int ixgbe_logtype_init;
407 int ixgbe_logtype_driver;
410 * The set of PCI devices this driver supports
412 static const struct rte_pci_id pci_id_ixgbe_map[] = {
413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
461 #ifdef RTE_LIBRTE_IXGBE_BYPASS
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
464 { .vendor_id = 0, /* sentinel */ },
468 * The set of PCI devices this driver supports (for 82599 VF)
470 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
481 { .vendor_id = 0, /* sentinel */ },
484 static const struct rte_eth_desc_lim rx_desc_lim = {
485 .nb_max = IXGBE_MAX_RING_DESC,
486 .nb_min = IXGBE_MIN_RING_DESC,
487 .nb_align = IXGBE_RXD_ALIGN,
490 static const struct rte_eth_desc_lim tx_desc_lim = {
491 .nb_max = IXGBE_MAX_RING_DESC,
492 .nb_min = IXGBE_MIN_RING_DESC,
493 .nb_align = IXGBE_TXD_ALIGN,
494 .nb_seg_max = IXGBE_TX_MAX_SEG,
495 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
498 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
499 .dev_configure = ixgbe_dev_configure,
500 .dev_start = ixgbe_dev_start,
501 .dev_stop = ixgbe_dev_stop,
502 .dev_set_link_up = ixgbe_dev_set_link_up,
503 .dev_set_link_down = ixgbe_dev_set_link_down,
504 .dev_close = ixgbe_dev_close,
505 .dev_reset = ixgbe_dev_reset,
506 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
507 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
508 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
509 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
510 .link_update = ixgbe_dev_link_update,
511 .stats_get = ixgbe_dev_stats_get,
512 .xstats_get = ixgbe_dev_xstats_get,
513 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
514 .stats_reset = ixgbe_dev_stats_reset,
515 .xstats_reset = ixgbe_dev_xstats_reset,
516 .xstats_get_names = ixgbe_dev_xstats_get_names,
517 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
518 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
519 .fw_version_get = ixgbe_fw_version_get,
520 .dev_infos_get = ixgbe_dev_info_get,
521 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
522 .mtu_set = ixgbe_dev_mtu_set,
523 .vlan_filter_set = ixgbe_vlan_filter_set,
524 .vlan_tpid_set = ixgbe_vlan_tpid_set,
525 .vlan_offload_set = ixgbe_vlan_offload_set,
526 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
527 .rx_queue_start = ixgbe_dev_rx_queue_start,
528 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
529 .tx_queue_start = ixgbe_dev_tx_queue_start,
530 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
531 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
532 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
533 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
534 .rx_queue_release = ixgbe_dev_rx_queue_release,
535 .rx_queue_count = ixgbe_dev_rx_queue_count,
536 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
537 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
538 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
539 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
540 .tx_queue_release = ixgbe_dev_tx_queue_release,
541 .dev_led_on = ixgbe_dev_led_on,
542 .dev_led_off = ixgbe_dev_led_off,
543 .flow_ctrl_get = ixgbe_flow_ctrl_get,
544 .flow_ctrl_set = ixgbe_flow_ctrl_set,
545 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
546 .mac_addr_add = ixgbe_add_rar,
547 .mac_addr_remove = ixgbe_remove_rar,
548 .mac_addr_set = ixgbe_set_default_mac_addr,
549 .uc_hash_table_set = ixgbe_uc_hash_table_set,
550 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
551 .mirror_rule_set = ixgbe_mirror_rule_set,
552 .mirror_rule_reset = ixgbe_mirror_rule_reset,
553 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
554 .reta_update = ixgbe_dev_rss_reta_update,
555 .reta_query = ixgbe_dev_rss_reta_query,
556 .rss_hash_update = ixgbe_dev_rss_hash_update,
557 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
558 .filter_ctrl = ixgbe_dev_filter_ctrl,
559 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
560 .rxq_info_get = ixgbe_rxq_info_get,
561 .txq_info_get = ixgbe_txq_info_get,
562 .timesync_enable = ixgbe_timesync_enable,
563 .timesync_disable = ixgbe_timesync_disable,
564 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
565 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
566 .get_reg = ixgbe_get_regs,
567 .get_eeprom_length = ixgbe_get_eeprom_length,
568 .get_eeprom = ixgbe_get_eeprom,
569 .set_eeprom = ixgbe_set_eeprom,
570 .get_module_info = ixgbe_get_module_info,
571 .get_module_eeprom = ixgbe_get_module_eeprom,
572 .get_dcb_info = ixgbe_dev_get_dcb_info,
573 .timesync_adjust_time = ixgbe_timesync_adjust_time,
574 .timesync_read_time = ixgbe_timesync_read_time,
575 .timesync_write_time = ixgbe_timesync_write_time,
576 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
577 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
578 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
579 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
580 .tm_ops_get = ixgbe_tm_ops_get,
584 * dev_ops for virtual function, bare necessities for basic vf
585 * operation have been implemented
587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
588 .dev_configure = ixgbevf_dev_configure,
589 .dev_start = ixgbevf_dev_start,
590 .dev_stop = ixgbevf_dev_stop,
591 .link_update = ixgbevf_dev_link_update,
592 .stats_get = ixgbevf_dev_stats_get,
593 .xstats_get = ixgbevf_dev_xstats_get,
594 .stats_reset = ixgbevf_dev_stats_reset,
595 .xstats_reset = ixgbevf_dev_stats_reset,
596 .xstats_get_names = ixgbevf_dev_xstats_get_names,
597 .dev_close = ixgbevf_dev_close,
598 .dev_reset = ixgbevf_dev_reset,
599 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
600 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
601 .dev_infos_get = ixgbevf_dev_info_get,
602 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
603 .mtu_set = ixgbevf_dev_set_mtu,
604 .vlan_filter_set = ixgbevf_vlan_filter_set,
605 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
606 .vlan_offload_set = ixgbevf_vlan_offload_set,
607 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
608 .rx_queue_release = ixgbe_dev_rx_queue_release,
609 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
610 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
611 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
612 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
613 .tx_queue_release = ixgbe_dev_tx_queue_release,
614 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
615 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
616 .mac_addr_add = ixgbevf_add_mac_addr,
617 .mac_addr_remove = ixgbevf_remove_mac_addr,
618 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
619 .rxq_info_get = ixgbe_rxq_info_get,
620 .txq_info_get = ixgbe_txq_info_get,
621 .mac_addr_set = ixgbevf_set_default_mac_addr,
622 .get_reg = ixgbevf_get_regs,
623 .reta_update = ixgbe_dev_rss_reta_update,
624 .reta_query = ixgbe_dev_rss_reta_query,
625 .rss_hash_update = ixgbe_dev_rss_hash_update,
626 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
629 /* store statistics names and its offset in stats structure */
630 struct rte_ixgbe_xstats_name_off {
631 char name[RTE_ETH_XSTATS_NAME_SIZE];
635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
636 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
637 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
638 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
639 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
640 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
641 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
642 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
643 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
644 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
645 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
646 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
647 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
648 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
649 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
650 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
652 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
654 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
655 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
656 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
657 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
658 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
659 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
660 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
661 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
662 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
663 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
664 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
665 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
666 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
667 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
668 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
669 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
670 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
672 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
674 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
675 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
676 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
677 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
679 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
681 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
683 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
685 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
687 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
689 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
692 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
693 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
694 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
696 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
697 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
698 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
699 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
700 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
702 {"rx_fcoe_no_direct_data_placement_ext_buff",
703 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
705 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
707 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
709 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
711 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
713 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
717 sizeof(rte_ixgbe_stats_strings[0]))
719 /* MACsec statistics */
720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
721 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
723 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
724 out_pkts_encrypted)},
725 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
726 out_pkts_protected)},
727 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
728 out_octets_encrypted)},
729 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
730 out_octets_protected)},
731 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
733 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
735 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
737 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
738 in_pkts_unknownsci)},
739 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
740 in_octets_decrypted)},
741 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
742 in_octets_validated)},
743 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
745 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
747 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
749 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
751 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
753 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
755 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
757 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
758 in_pkts_notusingsa)},
761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
762 sizeof(rte_ixgbe_macsec_strings[0]))
764 /* Per-queue statistics */
765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
766 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
767 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
768 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
769 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
773 sizeof(rte_ixgbe_rxq_strings[0]))
774 #define IXGBE_NB_RXQ_PRIO_VALUES 8
776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
777 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
778 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
779 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
784 sizeof(rte_ixgbe_txq_strings[0]))
785 #define IXGBE_NB_TXQ_PRIO_VALUES 8
787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
788 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
792 sizeof(rte_ixgbevf_stats_strings[0]))
795 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
798 ixgbe_is_sfp(struct ixgbe_hw *hw)
800 switch (hw->phy.type) {
801 case ixgbe_phy_sfp_avago:
802 case ixgbe_phy_sfp_ftl:
803 case ixgbe_phy_sfp_intel:
804 case ixgbe_phy_sfp_unknown:
805 case ixgbe_phy_sfp_passive_tyco:
806 case ixgbe_phy_sfp_passive_unknown:
813 static inline int32_t
814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
819 status = ixgbe_reset_hw(hw);
821 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
822 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
823 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
824 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
825 IXGBE_WRITE_FLUSH(hw);
827 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
828 status = IXGBE_SUCCESS;
833 ixgbe_enable_intr(struct rte_eth_dev *dev)
835 struct ixgbe_interrupt *intr =
836 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
837 struct ixgbe_hw *hw =
838 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
840 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
841 IXGBE_WRITE_FLUSH(hw);
845 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
848 ixgbe_disable_intr(struct ixgbe_hw *hw)
850 PMD_INIT_FUNC_TRACE();
852 if (hw->mac.type == ixgbe_mac_82598EB) {
853 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
855 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
856 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
857 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
859 IXGBE_WRITE_FLUSH(hw);
863 * This function resets queue statistics mapping registers.
864 * From Niantic datasheet, Initialization of Statistics section:
865 * "...if software requires the queue counters, the RQSMR and TQSM registers
866 * must be re-programmed following a device reset.
869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
873 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
874 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
875 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
887 #define NB_QMAP_FIELDS_PER_QSM_REG 4
888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
890 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
891 struct ixgbe_stat_mapping_registers *stat_mappings =
892 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
893 uint32_t qsmr_mask = 0;
894 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
898 if ((hw->mac.type != ixgbe_mac_82599EB) &&
899 (hw->mac.type != ixgbe_mac_X540) &&
900 (hw->mac.type != ixgbe_mac_X550) &&
901 (hw->mac.type != ixgbe_mac_X550EM_x) &&
902 (hw->mac.type != ixgbe_mac_X550EM_a))
905 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
906 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
909 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
910 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
911 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
914 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
916 /* Now clear any previous stat_idx set */
917 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
919 stat_mappings->tqsm[n] &= ~clearing_mask;
921 stat_mappings->rqsmr[n] &= ~clearing_mask;
923 q_map = (uint32_t)stat_idx;
924 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
925 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
927 stat_mappings->tqsm[n] |= qsmr_mask;
929 stat_mappings->rqsmr[n] |= qsmr_mask;
931 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
932 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
934 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
935 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
937 /* Now write the mapping in the appropriate register */
939 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
940 stat_mappings->rqsmr[n], n);
941 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
943 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
944 stat_mappings->tqsm[n], n);
945 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
953 struct ixgbe_stat_mapping_registers *stat_mappings =
954 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
955 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
958 /* write whatever was in stat mapping table to the NIC */
959 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
961 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
964 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
972 struct ixgbe_dcb_tc_config *tc;
973 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
975 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
976 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
977 for (i = 0; i < dcb_max_tc; i++) {
978 tc = &dcb_config->tc_config[i];
979 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
980 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
981 (uint8_t)(100/dcb_max_tc + (i & 1));
982 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
983 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
984 (uint8_t)(100/dcb_max_tc + (i & 1));
985 tc->pfc = ixgbe_dcb_pfc_disabled;
988 /* Initialize default user to priority mapping, UPx->TC0 */
989 tc = &dcb_config->tc_config[0];
990 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
991 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
992 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
993 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
994 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
996 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
997 dcb_config->pfc_mode_enable = false;
998 dcb_config->vt_mode = true;
999 dcb_config->round_robin_enable = false;
1000 /* support all DCB capabilities in 82599 */
1001 dcb_config->support.capabilities = 0xFF;
1003 /*we only support 4 Tcs for X540, X550 */
1004 if (hw->mac.type == ixgbe_mac_X540 ||
1005 hw->mac.type == ixgbe_mac_X550 ||
1006 hw->mac.type == ixgbe_mac_X550EM_x ||
1007 hw->mac.type == ixgbe_mac_X550EM_a) {
1008 dcb_config->num_tcs.pg_tcs = 4;
1009 dcb_config->num_tcs.pfc_tcs = 4;
1014 * Ensure that all locks are released before first NVM or PHY access
1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1022 * Phy lock should not fail in this early stage. If this is the case,
1023 * it is due to an improper exit of the application.
1024 * So force the release of the faulty lock. Release of common lock
1025 * is done automatically by swfw_sync function.
1027 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1028 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1029 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1031 ixgbe_release_swfw_semaphore(hw, mask);
1034 * These ones are more tricky since they are common to all ports; but
1035 * swfw_sync retries last long enough (1s) to be almost sure that if
1036 * lock can not be taken it is due to an improper lock of the
1039 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1040 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1041 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1043 ixgbe_release_swfw_semaphore(hw, mask);
1047 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1048 * It returns 0 on success.
1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1053 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1055 struct ixgbe_hw *hw =
1056 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1057 struct ixgbe_vfta *shadow_vfta =
1058 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1059 struct ixgbe_hwstrip *hwstrip =
1060 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1061 struct ixgbe_dcb_config *dcb_config =
1062 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1063 struct ixgbe_filter_info *filter_info =
1064 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1065 struct ixgbe_bw_conf *bw_conf =
1066 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1071 PMD_INIT_FUNC_TRACE();
1073 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1074 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1075 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1076 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1079 * For secondary processes, we don't initialise any further as primary
1080 * has already done this work. Only check we don't need a different
1081 * RX and TX function.
1083 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1084 struct ixgbe_tx_queue *txq;
1085 /* TX queue function in primary, set by last queue initialized
1086 * Tx queue may not initialized by primary process
1088 if (eth_dev->data->tx_queues) {
1089 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1090 ixgbe_set_tx_function(eth_dev, txq);
1092 /* Use default TX function if we get here */
1093 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1094 "Using default TX function.");
1097 ixgbe_set_rx_function(eth_dev);
1102 rte_eth_copy_pci_info(eth_dev, pci_dev);
1104 /* Vendor and Device ID need to be set before init of shared code */
1105 hw->device_id = pci_dev->id.device_id;
1106 hw->vendor_id = pci_dev->id.vendor_id;
1107 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1108 hw->allow_unsupported_sfp = 1;
1110 /* Initialize the shared code (base driver) */
1111 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1112 diag = ixgbe_bypass_init_shared_code(hw);
1114 diag = ixgbe_init_shared_code(hw);
1115 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1117 if (diag != IXGBE_SUCCESS) {
1118 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1122 /* pick up the PCI bus settings for reporting later */
1123 ixgbe_get_bus_info(hw);
1125 /* Unlock any pending hardware semaphore */
1126 ixgbe_swfw_lock_reset(hw);
1128 #ifdef RTE_LIBRTE_SECURITY
1129 /* Initialize security_ctx only for primary process*/
1130 if (ixgbe_ipsec_ctx_create(eth_dev))
1134 /* Initialize DCB configuration*/
1135 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1136 ixgbe_dcb_init(hw, dcb_config);
1137 /* Get Hardware Flow Control setting */
1138 hw->fc.requested_mode = ixgbe_fc_full;
1139 hw->fc.current_mode = ixgbe_fc_full;
1140 hw->fc.pause_time = IXGBE_FC_PAUSE;
1141 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1142 hw->fc.low_water[i] = IXGBE_FC_LO;
1143 hw->fc.high_water[i] = IXGBE_FC_HI;
1145 hw->fc.send_xon = 1;
1147 /* Make sure we have a good EEPROM before we read from it */
1148 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1149 if (diag != IXGBE_SUCCESS) {
1150 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1154 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1155 diag = ixgbe_bypass_init_hw(hw);
1157 diag = ixgbe_init_hw(hw);
1158 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1161 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1162 * is called too soon after the kernel driver unbinding/binding occurs.
1163 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1164 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1165 * also called. See ixgbe_identify_phy_82599(). The reason for the
1166 * failure is not known, and only occuts when virtualisation features
1167 * are disabled in the bios. A delay of 100ms was found to be enough by
1168 * trial-and-error, and is doubled to be safe.
1170 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1172 diag = ixgbe_init_hw(hw);
1175 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1176 diag = IXGBE_SUCCESS;
1178 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1179 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1180 "LOM. Please be aware there may be issues associated "
1181 "with your hardware.");
1182 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1183 "please contact your Intel or hardware representative "
1184 "who provided you with this hardware.");
1185 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1186 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1188 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1192 /* Reset the hw statistics */
1193 ixgbe_dev_stats_reset(eth_dev);
1195 /* disable interrupt */
1196 ixgbe_disable_intr(hw);
1198 /* reset mappings for queue statistics hw counters*/
1199 ixgbe_reset_qstat_mappings(hw);
1201 /* Allocate memory for storing MAC addresses */
1202 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1203 hw->mac.num_rar_entries, 0);
1204 if (eth_dev->data->mac_addrs == NULL) {
1206 "Failed to allocate %u bytes needed to store "
1208 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1211 /* Copy the permanent MAC address */
1212 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1213 ð_dev->data->mac_addrs[0]);
1215 /* Allocate memory for storing hash filter MAC addresses */
1216 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1217 IXGBE_VMDQ_NUM_UC_MAC, 0);
1218 if (eth_dev->data->hash_mac_addrs == NULL) {
1220 "Failed to allocate %d bytes needed to store MAC addresses",
1221 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1225 /* initialize the vfta */
1226 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1228 /* initialize the hw strip bitmap*/
1229 memset(hwstrip, 0, sizeof(*hwstrip));
1231 /* initialize PF if max_vfs not zero */
1232 ixgbe_pf_host_init(eth_dev);
1234 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1235 /* let hardware know driver is loaded */
1236 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1237 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1238 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1239 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1240 IXGBE_WRITE_FLUSH(hw);
1242 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1243 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1244 (int) hw->mac.type, (int) hw->phy.type,
1245 (int) hw->phy.sfp_type);
1247 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1248 (int) hw->mac.type, (int) hw->phy.type);
1250 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1251 eth_dev->data->port_id, pci_dev->id.vendor_id,
1252 pci_dev->id.device_id);
1254 rte_intr_callback_register(intr_handle,
1255 ixgbe_dev_interrupt_handler, eth_dev);
1257 /* enable uio/vfio intr/eventfd mapping */
1258 rte_intr_enable(intr_handle);
1260 /* enable support intr */
1261 ixgbe_enable_intr(eth_dev);
1263 /* initialize filter info */
1264 memset(filter_info, 0,
1265 sizeof(struct ixgbe_filter_info));
1267 /* initialize 5tuple filter list */
1268 TAILQ_INIT(&filter_info->fivetuple_list);
1270 /* initialize flow director filter list & hash */
1271 ixgbe_fdir_filter_init(eth_dev);
1273 /* initialize l2 tunnel filter list & hash */
1274 ixgbe_l2_tn_filter_init(eth_dev);
1276 /* initialize flow filter lists */
1277 ixgbe_filterlist_init();
1279 /* initialize bandwidth configuration info */
1280 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1282 /* initialize Traffic Manager configuration */
1283 ixgbe_tm_conf_init(eth_dev);
1289 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1291 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1292 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1293 struct ixgbe_hw *hw;
1297 PMD_INIT_FUNC_TRACE();
1299 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1302 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1304 if (hw->adapter_stopped == 0)
1305 ixgbe_dev_close(eth_dev);
1307 eth_dev->dev_ops = NULL;
1308 eth_dev->rx_pkt_burst = NULL;
1309 eth_dev->tx_pkt_burst = NULL;
1311 /* Unlock any pending hardware semaphore */
1312 ixgbe_swfw_lock_reset(hw);
1314 /* disable uio intr before callback unregister */
1315 rte_intr_disable(intr_handle);
1318 ret = rte_intr_callback_unregister(intr_handle,
1319 ixgbe_dev_interrupt_handler, eth_dev);
1322 } else if (ret != -EAGAIN) {
1324 "intr callback unregister failed: %d",
1329 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1331 /* uninitialize PF if max_vfs not zero */
1332 ixgbe_pf_host_uninit(eth_dev);
1334 rte_free(eth_dev->data->mac_addrs);
1335 eth_dev->data->mac_addrs = NULL;
1337 rte_free(eth_dev->data->hash_mac_addrs);
1338 eth_dev->data->hash_mac_addrs = NULL;
1340 /* remove all the fdir filters & hash */
1341 ixgbe_fdir_filter_uninit(eth_dev);
1343 /* remove all the L2 tunnel filters & hash */
1344 ixgbe_l2_tn_filter_uninit(eth_dev);
1346 /* Remove all ntuple filters of the device */
1347 ixgbe_ntuple_filter_uninit(eth_dev);
1349 /* clear all the filters list */
1350 ixgbe_filterlist_flush();
1352 /* Remove all Traffic Manager configuration */
1353 ixgbe_tm_conf_uninit(eth_dev);
1355 #ifdef RTE_LIBRTE_SECURITY
1356 rte_free(eth_dev->security_ctx);
1362 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1364 struct ixgbe_filter_info *filter_info =
1365 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1366 struct ixgbe_5tuple_filter *p_5tuple;
1368 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1369 TAILQ_REMOVE(&filter_info->fivetuple_list,
1374 memset(filter_info->fivetuple_mask, 0,
1375 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1380 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1382 struct ixgbe_hw_fdir_info *fdir_info =
1383 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1384 struct ixgbe_fdir_filter *fdir_filter;
1386 if (fdir_info->hash_map)
1387 rte_free(fdir_info->hash_map);
1388 if (fdir_info->hash_handle)
1389 rte_hash_free(fdir_info->hash_handle);
1391 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1392 TAILQ_REMOVE(&fdir_info->fdir_list,
1395 rte_free(fdir_filter);
1401 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1403 struct ixgbe_l2_tn_info *l2_tn_info =
1404 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1405 struct ixgbe_l2_tn_filter *l2_tn_filter;
1407 if (l2_tn_info->hash_map)
1408 rte_free(l2_tn_info->hash_map);
1409 if (l2_tn_info->hash_handle)
1410 rte_hash_free(l2_tn_info->hash_handle);
1412 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1413 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1416 rte_free(l2_tn_filter);
1422 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1424 struct ixgbe_hw_fdir_info *fdir_info =
1425 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1426 char fdir_hash_name[RTE_HASH_NAMESIZE];
1427 struct rte_hash_parameters fdir_hash_params = {
1428 .name = fdir_hash_name,
1429 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1430 .key_len = sizeof(union ixgbe_atr_input),
1431 .hash_func = rte_hash_crc,
1432 .hash_func_init_val = 0,
1433 .socket_id = rte_socket_id(),
1436 TAILQ_INIT(&fdir_info->fdir_list);
1437 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1438 "fdir_%s", eth_dev->device->name);
1439 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1440 if (!fdir_info->hash_handle) {
1441 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1444 fdir_info->hash_map = rte_zmalloc("ixgbe",
1445 sizeof(struct ixgbe_fdir_filter *) *
1446 IXGBE_MAX_FDIR_FILTER_NUM,
1448 if (!fdir_info->hash_map) {
1450 "Failed to allocate memory for fdir hash map!");
1453 fdir_info->mask_added = FALSE;
1458 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1460 struct ixgbe_l2_tn_info *l2_tn_info =
1461 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1462 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1463 struct rte_hash_parameters l2_tn_hash_params = {
1464 .name = l2_tn_hash_name,
1465 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1466 .key_len = sizeof(struct ixgbe_l2_tn_key),
1467 .hash_func = rte_hash_crc,
1468 .hash_func_init_val = 0,
1469 .socket_id = rte_socket_id(),
1472 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1473 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1474 "l2_tn_%s", eth_dev->device->name);
1475 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1476 if (!l2_tn_info->hash_handle) {
1477 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1480 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1481 sizeof(struct ixgbe_l2_tn_filter *) *
1482 IXGBE_MAX_L2_TN_FILTER_NUM,
1484 if (!l2_tn_info->hash_map) {
1486 "Failed to allocate memory for L2 TN hash map!");
1489 l2_tn_info->e_tag_en = FALSE;
1490 l2_tn_info->e_tag_fwd_en = FALSE;
1491 l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1496 * Negotiate mailbox API version with the PF.
1497 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1498 * Then we try to negotiate starting with the most recent one.
1499 * If all negotiation attempts fail, then we will proceed with
1500 * the default one (ixgbe_mbox_api_10).
1503 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1507 /* start with highest supported, proceed down */
1508 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1515 i != RTE_DIM(sup_ver) &&
1516 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1522 generate_random_mac_addr(struct ether_addr *mac_addr)
1526 /* Set Organizationally Unique Identifier (OUI) prefix. */
1527 mac_addr->addr_bytes[0] = 0x00;
1528 mac_addr->addr_bytes[1] = 0x09;
1529 mac_addr->addr_bytes[2] = 0xC0;
1530 /* Force indication of locally assigned MAC address. */
1531 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1532 /* Generate the last 3 bytes of the MAC address with a random number. */
1533 random = rte_rand();
1534 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1538 * Virtual Function device init
1541 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1545 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1546 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1547 struct ixgbe_hw *hw =
1548 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1549 struct ixgbe_vfta *shadow_vfta =
1550 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1551 struct ixgbe_hwstrip *hwstrip =
1552 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1553 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1555 PMD_INIT_FUNC_TRACE();
1557 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1558 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1559 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1561 /* for secondary processes, we don't initialise any further as primary
1562 * has already done this work. Only check we don't need a different
1565 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1566 struct ixgbe_tx_queue *txq;
1567 /* TX queue function in primary, set by last queue initialized
1568 * Tx queue may not initialized by primary process
1570 if (eth_dev->data->tx_queues) {
1571 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1572 ixgbe_set_tx_function(eth_dev, txq);
1574 /* Use default TX function if we get here */
1575 PMD_INIT_LOG(NOTICE,
1576 "No TX queues configured yet. Using default TX function.");
1579 ixgbe_set_rx_function(eth_dev);
1584 rte_eth_copy_pci_info(eth_dev, pci_dev);
1586 hw->device_id = pci_dev->id.device_id;
1587 hw->vendor_id = pci_dev->id.vendor_id;
1588 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1590 /* initialize the vfta */
1591 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1593 /* initialize the hw strip bitmap*/
1594 memset(hwstrip, 0, sizeof(*hwstrip));
1596 /* Initialize the shared code (base driver) */
1597 diag = ixgbe_init_shared_code(hw);
1598 if (diag != IXGBE_SUCCESS) {
1599 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1603 /* init_mailbox_params */
1604 hw->mbx.ops.init_params(hw);
1606 /* Reset the hw statistics */
1607 ixgbevf_dev_stats_reset(eth_dev);
1609 /* Disable the interrupts for VF */
1610 ixgbevf_intr_disable(eth_dev);
1612 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1613 diag = hw->mac.ops.reset_hw(hw);
1616 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1617 * the underlying PF driver has not assigned a MAC address to the VF.
1618 * In this case, assign a random MAC address.
1620 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1621 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1625 /* negotiate mailbox API version to use with the PF. */
1626 ixgbevf_negotiate_api(hw);
1628 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1629 ixgbevf_get_queues(hw, &tcs, &tc);
1631 /* Allocate memory for storing MAC addresses */
1632 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1633 hw->mac.num_rar_entries, 0);
1634 if (eth_dev->data->mac_addrs == NULL) {
1636 "Failed to allocate %u bytes needed to store "
1638 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1642 /* Generate a random MAC address, if none was assigned by PF. */
1643 if (is_zero_ether_addr(perm_addr)) {
1644 generate_random_mac_addr(perm_addr);
1645 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1647 rte_free(eth_dev->data->mac_addrs);
1648 eth_dev->data->mac_addrs = NULL;
1651 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1652 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1653 "%02x:%02x:%02x:%02x:%02x:%02x",
1654 perm_addr->addr_bytes[0],
1655 perm_addr->addr_bytes[1],
1656 perm_addr->addr_bytes[2],
1657 perm_addr->addr_bytes[3],
1658 perm_addr->addr_bytes[4],
1659 perm_addr->addr_bytes[5]);
1662 /* Copy the permanent MAC address */
1663 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1665 /* reset the hardware with the new settings */
1666 diag = hw->mac.ops.start_hw(hw);
1672 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1676 rte_intr_callback_register(intr_handle,
1677 ixgbevf_dev_interrupt_handler, eth_dev);
1678 rte_intr_enable(intr_handle);
1679 ixgbevf_intr_enable(eth_dev);
1681 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1682 eth_dev->data->port_id, pci_dev->id.vendor_id,
1683 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1688 /* Virtual Function device uninit */
1691 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1693 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1694 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1695 struct ixgbe_hw *hw;
1697 PMD_INIT_FUNC_TRACE();
1699 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1702 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1704 if (hw->adapter_stopped == 0)
1705 ixgbevf_dev_close(eth_dev);
1707 eth_dev->dev_ops = NULL;
1708 eth_dev->rx_pkt_burst = NULL;
1709 eth_dev->tx_pkt_burst = NULL;
1711 /* Disable the interrupts for VF */
1712 ixgbevf_intr_disable(eth_dev);
1714 rte_free(eth_dev->data->mac_addrs);
1715 eth_dev->data->mac_addrs = NULL;
1717 rte_intr_disable(intr_handle);
1718 rte_intr_callback_unregister(intr_handle,
1719 ixgbevf_dev_interrupt_handler, eth_dev);
1725 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1726 struct rte_pci_device *pci_dev)
1728 char name[RTE_ETH_NAME_MAX_LEN];
1729 struct rte_eth_dev *pf_ethdev;
1730 struct rte_eth_devargs eth_da;
1733 if (pci_dev->device.devargs) {
1734 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1739 memset(ð_da, 0, sizeof(eth_da));
1741 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1742 sizeof(struct ixgbe_adapter),
1743 eth_dev_pci_specific_init, pci_dev,
1744 eth_ixgbe_dev_init, NULL);
1746 if (retval || eth_da.nb_representor_ports < 1)
1749 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1750 if (pf_ethdev == NULL)
1753 /* probe VF representor ports */
1754 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1755 struct ixgbe_vf_info *vfinfo;
1756 struct ixgbe_vf_representor representor;
1758 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1759 pf_ethdev->data->dev_private);
1760 if (vfinfo == NULL) {
1762 "no virtual functions supported by PF");
1766 representor.vf_id = eth_da.representor_ports[i];
1767 representor.switch_domain_id = vfinfo->switch_domain_id;
1768 representor.pf_ethdev = pf_ethdev;
1770 /* representor port net_bdf_port */
1771 snprintf(name, sizeof(name), "net_%s_representor_%d",
1772 pci_dev->device.name,
1773 eth_da.representor_ports[i]);
1775 retval = rte_eth_dev_create(&pci_dev->device, name,
1776 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1777 ixgbe_vf_representor_init, &representor);
1780 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1781 "representor %s.", name);
1787 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1789 struct rte_eth_dev *ethdev;
1791 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1795 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1796 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1798 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1801 static struct rte_pci_driver rte_ixgbe_pmd = {
1802 .id_table = pci_id_ixgbe_map,
1803 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1804 RTE_PCI_DRV_IOVA_AS_VA,
1805 .probe = eth_ixgbe_pci_probe,
1806 .remove = eth_ixgbe_pci_remove,
1809 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1810 struct rte_pci_device *pci_dev)
1812 return rte_eth_dev_pci_generic_probe(pci_dev,
1813 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1816 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1818 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1822 * virtual function driver struct
1824 static struct rte_pci_driver rte_ixgbevf_pmd = {
1825 .id_table = pci_id_ixgbevf_map,
1826 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1827 .probe = eth_ixgbevf_pci_probe,
1828 .remove = eth_ixgbevf_pci_remove,
1832 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1834 struct ixgbe_hw *hw =
1835 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836 struct ixgbe_vfta *shadow_vfta =
1837 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1842 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1843 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1844 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1849 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1851 /* update local VFTA copy */
1852 shadow_vfta->vfta[vid_idx] = vfta;
1858 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1861 ixgbe_vlan_hw_strip_enable(dev, queue);
1863 ixgbe_vlan_hw_strip_disable(dev, queue);
1867 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1868 enum rte_vlan_type vlan_type,
1871 struct ixgbe_hw *hw =
1872 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1878 qinq &= IXGBE_DMATXCTL_GDV;
1880 switch (vlan_type) {
1881 case ETH_VLAN_TYPE_INNER:
1883 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1884 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1885 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1886 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1888 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1889 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1892 PMD_DRV_LOG(ERR, "Inner type is not supported"
1896 case ETH_VLAN_TYPE_OUTER:
1898 /* Only the high 16-bits is valid */
1899 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1900 IXGBE_EXVET_VET_EXT_SHIFT);
1902 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1903 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1904 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1905 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1906 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1907 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1908 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1914 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1922 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1924 struct ixgbe_hw *hw =
1925 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928 PMD_INIT_FUNC_TRACE();
1930 /* Filter Table Disable */
1931 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1932 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1934 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1938 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1940 struct ixgbe_hw *hw =
1941 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942 struct ixgbe_vfta *shadow_vfta =
1943 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1947 PMD_INIT_FUNC_TRACE();
1949 /* Filter Table Enable */
1950 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1951 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1952 vlnctrl |= IXGBE_VLNCTRL_VFE;
1954 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1956 /* write whatever is in local vfta copy */
1957 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1958 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1962 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1964 struct ixgbe_hwstrip *hwstrip =
1965 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1966 struct ixgbe_rx_queue *rxq;
1968 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1972 IXGBE_SET_HWSTRIP(hwstrip, queue);
1974 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1976 if (queue >= dev->data->nb_rx_queues)
1979 rxq = dev->data->rx_queues[queue];
1982 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1983 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1985 rxq->vlan_flags = PKT_RX_VLAN;
1986 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1991 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1993 struct ixgbe_hw *hw =
1994 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997 PMD_INIT_FUNC_TRACE();
1999 if (hw->mac.type == ixgbe_mac_82598EB) {
2000 /* No queue level support */
2001 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2005 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2006 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2007 ctrl &= ~IXGBE_RXDCTL_VME;
2008 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2010 /* record those setting for HW strip per queue */
2011 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2015 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2017 struct ixgbe_hw *hw =
2018 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2021 PMD_INIT_FUNC_TRACE();
2023 if (hw->mac.type == ixgbe_mac_82598EB) {
2024 /* No queue level supported */
2025 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2029 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2030 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2031 ctrl |= IXGBE_RXDCTL_VME;
2032 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2034 /* record those setting for HW strip per queue */
2035 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2039 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2041 struct ixgbe_hw *hw =
2042 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045 PMD_INIT_FUNC_TRACE();
2047 /* DMATXCTRL: Geric Double VLAN Disable */
2048 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2049 ctrl &= ~IXGBE_DMATXCTL_GDV;
2050 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2052 /* CTRL_EXT: Global Double VLAN Disable */
2053 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2054 ctrl &= ~IXGBE_EXTENDED_VLAN;
2055 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2060 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2062 struct ixgbe_hw *hw =
2063 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2066 PMD_INIT_FUNC_TRACE();
2068 /* DMATXCTRL: Geric Double VLAN Enable */
2069 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2070 ctrl |= IXGBE_DMATXCTL_GDV;
2071 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2073 /* CTRL_EXT: Global Double VLAN Enable */
2074 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2075 ctrl |= IXGBE_EXTENDED_VLAN;
2076 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2078 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2079 if (hw->mac.type == ixgbe_mac_X550 ||
2080 hw->mac.type == ixgbe_mac_X550EM_x ||
2081 hw->mac.type == ixgbe_mac_X550EM_a) {
2082 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2083 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2084 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2088 * VET EXT field in the EXVET register = 0x8100 by default
2089 * So no need to change. Same to VT field of DMATXCTL register
2094 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2096 struct ixgbe_hw *hw =
2097 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2101 struct ixgbe_rx_queue *rxq;
2104 PMD_INIT_FUNC_TRACE();
2106 if (hw->mac.type == ixgbe_mac_82598EB) {
2107 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2108 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2109 ctrl |= IXGBE_VLNCTRL_VME;
2110 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2112 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2113 ctrl &= ~IXGBE_VLNCTRL_VME;
2114 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2118 * Other 10G NIC, the VLAN strip can be setup
2119 * per queue in RXDCTL
2121 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2122 rxq = dev->data->rx_queues[i];
2123 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2124 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2125 ctrl |= IXGBE_RXDCTL_VME;
2128 ctrl &= ~IXGBE_RXDCTL_VME;
2131 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2133 /* record those setting for HW strip per queue */
2134 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2140 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2143 struct rte_eth_rxmode *rxmode;
2144 struct ixgbe_rx_queue *rxq;
2146 if (mask & ETH_VLAN_STRIP_MASK) {
2147 rxmode = &dev->data->dev_conf.rxmode;
2148 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2149 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2150 rxq = dev->data->rx_queues[i];
2151 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2154 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2155 rxq = dev->data->rx_queues[i];
2156 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2162 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2164 struct rte_eth_rxmode *rxmode;
2165 rxmode = &dev->data->dev_conf.rxmode;
2167 if (mask & ETH_VLAN_STRIP_MASK) {
2168 ixgbe_vlan_hw_strip_config(dev);
2171 if (mask & ETH_VLAN_FILTER_MASK) {
2172 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2173 ixgbe_vlan_hw_filter_enable(dev);
2175 ixgbe_vlan_hw_filter_disable(dev);
2178 if (mask & ETH_VLAN_EXTEND_MASK) {
2179 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2180 ixgbe_vlan_hw_extend_enable(dev);
2182 ixgbe_vlan_hw_extend_disable(dev);
2189 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2191 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2193 ixgbe_vlan_offload_config(dev, mask);
2199 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2201 struct ixgbe_hw *hw =
2202 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2203 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2204 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2206 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2207 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2211 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2213 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2218 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2221 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2227 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2228 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2229 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2230 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2235 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2237 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2238 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2240 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2242 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2243 /* check multi-queue mode */
2244 switch (dev_conf->rxmode.mq_mode) {
2245 case ETH_MQ_RX_VMDQ_DCB:
2246 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2248 case ETH_MQ_RX_VMDQ_DCB_RSS:
2249 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2250 PMD_INIT_LOG(ERR, "SRIOV active,"
2251 " unsupported mq_mode rx %d.",
2252 dev_conf->rxmode.mq_mode);
2255 case ETH_MQ_RX_VMDQ_RSS:
2256 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2257 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2258 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2259 PMD_INIT_LOG(ERR, "SRIOV is active,"
2260 " invalid queue number"
2261 " for VMDQ RSS, allowed"
2262 " value are 1, 2 or 4.");
2266 case ETH_MQ_RX_VMDQ_ONLY:
2267 case ETH_MQ_RX_NONE:
2268 /* if nothing mq mode configure, use default scheme */
2269 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2271 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2272 /* SRIOV only works in VMDq enable mode */
2273 PMD_INIT_LOG(ERR, "SRIOV is active,"
2274 " wrong mq_mode rx %d.",
2275 dev_conf->rxmode.mq_mode);
2279 switch (dev_conf->txmode.mq_mode) {
2280 case ETH_MQ_TX_VMDQ_DCB:
2281 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2282 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2284 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2285 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2289 /* check valid queue number */
2290 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2291 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2292 PMD_INIT_LOG(ERR, "SRIOV is active,"
2293 " nb_rx_q=%d nb_tx_q=%d queue number"
2294 " must be less than or equal to %d.",
2296 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2300 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2301 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2305 /* check configuration for vmdb+dcb mode */
2306 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2307 const struct rte_eth_vmdq_dcb_conf *conf;
2309 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2310 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2311 IXGBE_VMDQ_DCB_NB_QUEUES);
2314 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2315 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2316 conf->nb_queue_pools == ETH_32_POOLS)) {
2317 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2318 " nb_queue_pools must be %d or %d.",
2319 ETH_16_POOLS, ETH_32_POOLS);
2323 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2324 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2326 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2327 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2328 IXGBE_VMDQ_DCB_NB_QUEUES);
2331 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2332 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2333 conf->nb_queue_pools == ETH_32_POOLS)) {
2334 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2335 " nb_queue_pools != %d and"
2336 " nb_queue_pools != %d.",
2337 ETH_16_POOLS, ETH_32_POOLS);
2342 /* For DCB mode check our configuration before we go further */
2343 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2344 const struct rte_eth_dcb_rx_conf *conf;
2346 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2347 if (!(conf->nb_tcs == ETH_4_TCS ||
2348 conf->nb_tcs == ETH_8_TCS)) {
2349 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2350 " and nb_tcs != %d.",
2351 ETH_4_TCS, ETH_8_TCS);
2356 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2357 const struct rte_eth_dcb_tx_conf *conf;
2359 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2360 if (!(conf->nb_tcs == ETH_4_TCS ||
2361 conf->nb_tcs == ETH_8_TCS)) {
2362 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2363 " and nb_tcs != %d.",
2364 ETH_4_TCS, ETH_8_TCS);
2370 * When DCB/VT is off, maximum number of queues changes,
2371 * except for 82598EB, which remains constant.
2373 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2374 hw->mac.type != ixgbe_mac_82598EB) {
2375 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2377 "Neither VT nor DCB are enabled, "
2379 IXGBE_NONE_MODE_TX_NB_QUEUES);
2388 ixgbe_dev_configure(struct rte_eth_dev *dev)
2390 struct ixgbe_interrupt *intr =
2391 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2392 struct ixgbe_adapter *adapter =
2393 (struct ixgbe_adapter *)dev->data->dev_private;
2396 PMD_INIT_FUNC_TRACE();
2397 /* multipe queue mode checking */
2398 ret = ixgbe_check_mq_mode(dev);
2400 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2405 /* set flag to update link status after init */
2406 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2409 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2410 * allocation or vector Rx preconditions we will reset it.
2412 adapter->rx_bulk_alloc_allowed = true;
2413 adapter->rx_vec_allowed = true;
2419 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2421 struct ixgbe_hw *hw =
2422 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423 struct ixgbe_interrupt *intr =
2424 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2427 /* only set up it on X550EM_X */
2428 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2429 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2430 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2431 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2432 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2433 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2438 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2439 uint16_t tx_rate, uint64_t q_msk)
2441 struct ixgbe_hw *hw;
2442 struct ixgbe_vf_info *vfinfo;
2443 struct rte_eth_link link;
2444 uint8_t nb_q_per_pool;
2445 uint32_t queue_stride;
2446 uint32_t queue_idx, idx = 0, vf_idx;
2448 uint16_t total_rate = 0;
2449 struct rte_pci_device *pci_dev;
2451 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2452 rte_eth_link_get_nowait(dev->data->port_id, &link);
2454 if (vf >= pci_dev->max_vfs)
2457 if (tx_rate > link.link_speed)
2463 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2464 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2465 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2466 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2467 queue_idx = vf * queue_stride;
2468 queue_end = queue_idx + nb_q_per_pool - 1;
2469 if (queue_end >= hw->mac.max_tx_queues)
2473 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2476 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2478 total_rate += vfinfo[vf_idx].tx_rate[idx];
2484 /* Store tx_rate for this vf. */
2485 for (idx = 0; idx < nb_q_per_pool; idx++) {
2486 if (((uint64_t)0x1 << idx) & q_msk) {
2487 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2488 vfinfo[vf].tx_rate[idx] = tx_rate;
2489 total_rate += tx_rate;
2493 if (total_rate > dev->data->dev_link.link_speed) {
2494 /* Reset stored TX rate of the VF if it causes exceed
2497 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2501 /* Set RTTBCNRC of each queue/pool for vf X */
2502 for (; queue_idx <= queue_end; queue_idx++) {
2504 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2512 * Configure device link speed and setup link.
2513 * It returns 0 on success.
2516 ixgbe_dev_start(struct rte_eth_dev *dev)
2518 struct ixgbe_hw *hw =
2519 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2520 struct ixgbe_vf_info *vfinfo =
2521 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2522 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2523 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2524 uint32_t intr_vector = 0;
2525 int err, link_up = 0, negotiate = 0;
2527 uint32_t allowed_speeds = 0;
2531 uint32_t *link_speeds;
2532 struct ixgbe_tm_conf *tm_conf =
2533 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2535 PMD_INIT_FUNC_TRACE();
2537 /* IXGBE devices don't support:
2538 * - half duplex (checked afterwards for valid speeds)
2539 * - fixed speed: TODO implement
2541 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2543 "Invalid link_speeds for port %u, fix speed not supported",
2544 dev->data->port_id);
2548 /* disable uio/vfio intr/eventfd mapping */
2549 rte_intr_disable(intr_handle);
2552 hw->adapter_stopped = 0;
2553 ixgbe_stop_adapter(hw);
2555 /* reinitialize adapter
2556 * this calls reset and start
2558 status = ixgbe_pf_reset_hw(hw);
2561 hw->mac.ops.start_hw(hw);
2562 hw->mac.get_link_status = true;
2564 /* configure PF module if SRIOV enabled */
2565 ixgbe_pf_host_configure(dev);
2567 ixgbe_dev_phy_intr_setup(dev);
2569 /* check and configure queue intr-vector mapping */
2570 if ((rte_intr_cap_multiple(intr_handle) ||
2571 !RTE_ETH_DEV_SRIOV(dev).active) &&
2572 dev->data->dev_conf.intr_conf.rxq != 0) {
2573 intr_vector = dev->data->nb_rx_queues;
2574 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2575 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2576 IXGBE_MAX_INTR_QUEUE_NUM);
2579 if (rte_intr_efd_enable(intr_handle, intr_vector))
2583 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2584 intr_handle->intr_vec =
2585 rte_zmalloc("intr_vec",
2586 dev->data->nb_rx_queues * sizeof(int), 0);
2587 if (intr_handle->intr_vec == NULL) {
2588 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2589 " intr_vec", dev->data->nb_rx_queues);
2594 /* confiugre msix for sleep until rx interrupt */
2595 ixgbe_configure_msix(dev);
2597 /* initialize transmission unit */
2598 ixgbe_dev_tx_init(dev);
2600 /* This can fail when allocating mbufs for descriptor rings */
2601 err = ixgbe_dev_rx_init(dev);
2603 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2607 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2608 ETH_VLAN_EXTEND_MASK;
2609 err = ixgbe_vlan_offload_config(dev, mask);
2611 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2615 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2616 /* Enable vlan filtering for VMDq */
2617 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2620 /* Configure DCB hw */
2621 ixgbe_configure_dcb(dev);
2623 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2624 err = ixgbe_fdir_configure(dev);
2629 /* Restore vf rate limit */
2630 if (vfinfo != NULL) {
2631 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2632 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2633 if (vfinfo[vf].tx_rate[idx] != 0)
2634 ixgbe_set_vf_rate_limit(
2636 vfinfo[vf].tx_rate[idx],
2640 ixgbe_restore_statistics_mapping(dev);
2642 err = ixgbe_dev_rxtx_start(dev);
2644 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2648 /* Skip link setup if loopback mode is enabled for 82599. */
2649 if (hw->mac.type == ixgbe_mac_82599EB &&
2650 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2651 goto skip_link_setup;
2653 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2654 err = hw->mac.ops.setup_sfp(hw);
2659 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2660 /* Turn on the copper */
2661 ixgbe_set_phy_power(hw, true);
2663 /* Turn on the laser */
2664 ixgbe_enable_tx_laser(hw);
2667 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2670 dev->data->dev_link.link_status = link_up;
2672 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2676 switch (hw->mac.type) {
2677 case ixgbe_mac_X550:
2678 case ixgbe_mac_X550EM_x:
2679 case ixgbe_mac_X550EM_a:
2680 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2681 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2685 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2689 link_speeds = &dev->data->dev_conf.link_speeds;
2690 if (*link_speeds & ~allowed_speeds) {
2691 PMD_INIT_LOG(ERR, "Invalid link setting");
2696 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2697 switch (hw->mac.type) {
2698 case ixgbe_mac_82598EB:
2699 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2701 case ixgbe_mac_82599EB:
2702 case ixgbe_mac_X540:
2703 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2705 case ixgbe_mac_X550:
2706 case ixgbe_mac_X550EM_x:
2707 case ixgbe_mac_X550EM_a:
2708 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2711 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2714 if (*link_speeds & ETH_LINK_SPEED_10G)
2715 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2716 if (*link_speeds & ETH_LINK_SPEED_5G)
2717 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2718 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2719 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2720 if (*link_speeds & ETH_LINK_SPEED_1G)
2721 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2722 if (*link_speeds & ETH_LINK_SPEED_100M)
2723 speed |= IXGBE_LINK_SPEED_100_FULL;
2726 err = ixgbe_setup_link(hw, speed, link_up);
2730 ixgbe_dev_link_update(dev, 0);
2734 if (rte_intr_allow_others(intr_handle)) {
2735 /* check if lsc interrupt is enabled */
2736 if (dev->data->dev_conf.intr_conf.lsc != 0)
2737 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2739 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2740 ixgbe_dev_macsec_interrupt_setup(dev);
2742 rte_intr_callback_unregister(intr_handle,
2743 ixgbe_dev_interrupt_handler, dev);
2744 if (dev->data->dev_conf.intr_conf.lsc != 0)
2745 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2746 " no intr multiplex");
2749 /* check if rxq interrupt is enabled */
2750 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2751 rte_intr_dp_is_en(intr_handle))
2752 ixgbe_dev_rxq_interrupt_setup(dev);
2754 /* enable uio/vfio intr/eventfd mapping */
2755 rte_intr_enable(intr_handle);
2757 /* resume enabled intr since hw reset */
2758 ixgbe_enable_intr(dev);
2759 ixgbe_l2_tunnel_conf(dev);
2760 ixgbe_filter_restore(dev);
2762 if (tm_conf->root && !tm_conf->committed)
2763 PMD_DRV_LOG(WARNING,
2764 "please call hierarchy_commit() "
2765 "before starting the port");
2770 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2771 ixgbe_dev_clear_queues(dev);
2776 * Stop device: disable rx and tx functions to allow for reconfiguring.
2779 ixgbe_dev_stop(struct rte_eth_dev *dev)
2781 struct rte_eth_link link;
2782 struct ixgbe_hw *hw =
2783 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784 struct ixgbe_vf_info *vfinfo =
2785 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2786 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2787 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2789 struct ixgbe_tm_conf *tm_conf =
2790 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2792 PMD_INIT_FUNC_TRACE();
2794 /* disable interrupts */
2795 ixgbe_disable_intr(hw);
2798 ixgbe_pf_reset_hw(hw);
2799 hw->adapter_stopped = 0;
2802 ixgbe_stop_adapter(hw);
2804 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2805 vfinfo[vf].clear_to_send = false;
2807 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2808 /* Turn off the copper */
2809 ixgbe_set_phy_power(hw, false);
2811 /* Turn off the laser */
2812 ixgbe_disable_tx_laser(hw);
2815 ixgbe_dev_clear_queues(dev);
2817 /* Clear stored conf */
2818 dev->data->scattered_rx = 0;
2821 /* Clear recorded link status */
2822 memset(&link, 0, sizeof(link));
2823 rte_eth_linkstatus_set(dev, &link);
2825 if (!rte_intr_allow_others(intr_handle))
2826 /* resume to the default handler */
2827 rte_intr_callback_register(intr_handle,
2828 ixgbe_dev_interrupt_handler,
2831 /* Clean datapath event and queue/vec mapping */
2832 rte_intr_efd_disable(intr_handle);
2833 if (intr_handle->intr_vec != NULL) {
2834 rte_free(intr_handle->intr_vec);
2835 intr_handle->intr_vec = NULL;
2838 /* reset hierarchy commit */
2839 tm_conf->committed = false;
2843 * Set device link up: enable tx.
2846 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2848 struct ixgbe_hw *hw =
2849 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2850 if (hw->mac.type == ixgbe_mac_82599EB) {
2851 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2852 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2853 /* Not suported in bypass mode */
2854 PMD_INIT_LOG(ERR, "Set link up is not supported "
2855 "by device id 0x%x", hw->device_id);
2861 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2862 /* Turn on the copper */
2863 ixgbe_set_phy_power(hw, true);
2865 /* Turn on the laser */
2866 ixgbe_enable_tx_laser(hw);
2873 * Set device link down: disable tx.
2876 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2878 struct ixgbe_hw *hw =
2879 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2880 if (hw->mac.type == ixgbe_mac_82599EB) {
2881 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2882 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2883 /* Not suported in bypass mode */
2884 PMD_INIT_LOG(ERR, "Set link down is not supported "
2885 "by device id 0x%x", hw->device_id);
2891 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2892 /* Turn off the copper */
2893 ixgbe_set_phy_power(hw, false);
2895 /* Turn off the laser */
2896 ixgbe_disable_tx_laser(hw);
2903 * Reset and stop device.
2906 ixgbe_dev_close(struct rte_eth_dev *dev)
2908 struct ixgbe_hw *hw =
2909 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2911 PMD_INIT_FUNC_TRACE();
2913 ixgbe_pf_reset_hw(hw);
2915 ixgbe_dev_stop(dev);
2916 hw->adapter_stopped = 1;
2918 ixgbe_dev_free_queues(dev);
2920 ixgbe_disable_pcie_master(hw);
2922 /* reprogram the RAR[0] in case user changed it. */
2923 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2930 ixgbe_dev_reset(struct rte_eth_dev *dev)
2934 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2935 * its VF to make them align with it. The detailed notification
2936 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2937 * To avoid unexpected behavior in VF, currently reset of PF with
2938 * SR-IOV activation is not supported. It might be supported later.
2940 if (dev->data->sriov.active)
2943 ret = eth_ixgbe_dev_uninit(dev);
2947 ret = eth_ixgbe_dev_init(dev, NULL);
2953 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2954 struct ixgbe_hw_stats *hw_stats,
2955 struct ixgbe_macsec_stats *macsec_stats,
2956 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2957 uint64_t *total_qprc, uint64_t *total_qprdc)
2959 uint32_t bprc, lxon, lxoff, total;
2960 uint32_t delta_gprc = 0;
2962 /* Workaround for RX byte count not including CRC bytes when CRC
2963 * strip is enabled. CRC bytes are removed from counters when crc_strip
2966 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2967 IXGBE_HLREG0_RXCRCSTRP);
2969 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2970 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2971 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2972 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2974 for (i = 0; i < 8; i++) {
2975 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2977 /* global total per queue */
2978 hw_stats->mpc[i] += mp;
2979 /* Running comprehensive total for stats display */
2980 *total_missed_rx += hw_stats->mpc[i];
2981 if (hw->mac.type == ixgbe_mac_82598EB) {
2982 hw_stats->rnbc[i] +=
2983 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2984 hw_stats->pxonrxc[i] +=
2985 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2986 hw_stats->pxoffrxc[i] +=
2987 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2989 hw_stats->pxonrxc[i] +=
2990 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2991 hw_stats->pxoffrxc[i] +=
2992 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2993 hw_stats->pxon2offc[i] +=
2994 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2996 hw_stats->pxontxc[i] +=
2997 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2998 hw_stats->pxofftxc[i] +=
2999 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3001 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3002 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3003 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3004 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3006 delta_gprc += delta_qprc;
3008 hw_stats->qprc[i] += delta_qprc;
3009 hw_stats->qptc[i] += delta_qptc;
3011 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3012 hw_stats->qbrc[i] +=
3013 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3015 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3017 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3018 hw_stats->qbtc[i] +=
3019 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3021 hw_stats->qprdc[i] += delta_qprdc;
3022 *total_qprdc += hw_stats->qprdc[i];
3024 *total_qprc += hw_stats->qprc[i];
3025 *total_qbrc += hw_stats->qbrc[i];
3027 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3028 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3029 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3032 * An errata states that gprc actually counts good + missed packets:
3033 * Workaround to set gprc to summated queue packet receives
3035 hw_stats->gprc = *total_qprc;
3037 if (hw->mac.type != ixgbe_mac_82598EB) {
3038 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3039 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3040 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3041 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3042 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3043 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3044 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3045 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3047 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3048 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3049 /* 82598 only has a counter in the high register */
3050 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3051 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3052 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3054 uint64_t old_tpr = hw_stats->tpr;
3056 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3057 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3060 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3062 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3063 hw_stats->gptc += delta_gptc;
3064 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3065 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3068 * Workaround: mprc hardware is incorrectly counting
3069 * broadcasts, so for now we subtract those.
3071 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3072 hw_stats->bprc += bprc;
3073 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3074 if (hw->mac.type == ixgbe_mac_82598EB)
3075 hw_stats->mprc -= bprc;
3077 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3078 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3079 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3080 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3081 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3082 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3084 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3085 hw_stats->lxontxc += lxon;
3086 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3087 hw_stats->lxofftxc += lxoff;
3088 total = lxon + lxoff;
3090 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3091 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3092 hw_stats->gptc -= total;
3093 hw_stats->mptc -= total;
3094 hw_stats->ptc64 -= total;
3095 hw_stats->gotc -= total * ETHER_MIN_LEN;
3097 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3098 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3099 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3100 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3101 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3102 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3103 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3104 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3105 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3106 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3107 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3108 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3109 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3110 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3111 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3112 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3113 /* Only read FCOE on 82599 */
3114 if (hw->mac.type != ixgbe_mac_82598EB) {
3115 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3116 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3117 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3118 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3119 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3122 /* Flow Director Stats registers */
3123 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3124 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3126 /* MACsec Stats registers */
3127 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3128 macsec_stats->out_pkts_encrypted +=
3129 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3130 macsec_stats->out_pkts_protected +=
3131 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3132 macsec_stats->out_octets_encrypted +=
3133 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3134 macsec_stats->out_octets_protected +=
3135 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3136 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3137 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3138 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3139 macsec_stats->in_pkts_unknownsci +=
3140 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3141 macsec_stats->in_octets_decrypted +=
3142 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3143 macsec_stats->in_octets_validated +=
3144 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3145 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3146 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3147 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3148 for (i = 0; i < 2; i++) {
3149 macsec_stats->in_pkts_ok +=
3150 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3151 macsec_stats->in_pkts_invalid +=
3152 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3153 macsec_stats->in_pkts_notvalid +=
3154 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3156 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3157 macsec_stats->in_pkts_notusingsa +=
3158 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3162 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3165 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3167 struct ixgbe_hw *hw =
3168 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169 struct ixgbe_hw_stats *hw_stats =
3170 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3171 struct ixgbe_macsec_stats *macsec_stats =
3172 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3173 dev->data->dev_private);
3174 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3177 total_missed_rx = 0;
3182 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3183 &total_qbrc, &total_qprc, &total_qprdc);
3188 /* Fill out the rte_eth_stats statistics structure */
3189 stats->ipackets = total_qprc;
3190 stats->ibytes = total_qbrc;
3191 stats->opackets = hw_stats->gptc;
3192 stats->obytes = hw_stats->gotc;
3194 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3195 stats->q_ipackets[i] = hw_stats->qprc[i];
3196 stats->q_opackets[i] = hw_stats->qptc[i];
3197 stats->q_ibytes[i] = hw_stats->qbrc[i];
3198 stats->q_obytes[i] = hw_stats->qbtc[i];
3199 stats->q_errors[i] = hw_stats->qprdc[i];
3203 stats->imissed = total_missed_rx;
3204 stats->ierrors = hw_stats->crcerrs +
3221 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3223 struct ixgbe_hw_stats *stats =
3224 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3226 /* HW registers are cleared on read */
3227 ixgbe_dev_stats_get(dev, NULL);
3229 /* Reset software totals */
3230 memset(stats, 0, sizeof(*stats));
3233 /* This function calculates the number of xstats based on the current config */
3235 ixgbe_xstats_calc_num(void) {
3236 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3237 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3238 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3241 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3242 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3244 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3245 unsigned stat, i, count;
3247 if (xstats_names != NULL) {
3250 /* Note: limit >= cnt_stats checked upstream
3251 * in rte_eth_xstats_names()
3254 /* Extended stats from ixgbe_hw_stats */
3255 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3256 snprintf(xstats_names[count].name,
3257 sizeof(xstats_names[count].name),
3259 rte_ixgbe_stats_strings[i].name);
3264 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3265 snprintf(xstats_names[count].name,
3266 sizeof(xstats_names[count].name),
3268 rte_ixgbe_macsec_strings[i].name);
3272 /* RX Priority Stats */
3273 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3274 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3275 snprintf(xstats_names[count].name,
3276 sizeof(xstats_names[count].name),
3277 "rx_priority%u_%s", i,
3278 rte_ixgbe_rxq_strings[stat].name);
3283 /* TX Priority Stats */
3284 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3285 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3286 snprintf(xstats_names[count].name,
3287 sizeof(xstats_names[count].name),
3288 "tx_priority%u_%s", i,
3289 rte_ixgbe_txq_strings[stat].name);
3297 static int ixgbe_dev_xstats_get_names_by_id(
3298 struct rte_eth_dev *dev,
3299 struct rte_eth_xstat_name *xstats_names,
3300 const uint64_t *ids,
3304 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3305 unsigned int stat, i, count;
3307 if (xstats_names != NULL) {
3310 /* Note: limit >= cnt_stats checked upstream
3311 * in rte_eth_xstats_names()
3314 /* Extended stats from ixgbe_hw_stats */
3315 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3316 snprintf(xstats_names[count].name,
3317 sizeof(xstats_names[count].name),
3319 rte_ixgbe_stats_strings[i].name);
3324 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3325 snprintf(xstats_names[count].name,
3326 sizeof(xstats_names[count].name),
3328 rte_ixgbe_macsec_strings[i].name);
3332 /* RX Priority Stats */
3333 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3334 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3335 snprintf(xstats_names[count].name,
3336 sizeof(xstats_names[count].name),
3337 "rx_priority%u_%s", i,
3338 rte_ixgbe_rxq_strings[stat].name);
3343 /* TX Priority Stats */
3344 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3345 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3346 snprintf(xstats_names[count].name,
3347 sizeof(xstats_names[count].name),
3348 "tx_priority%u_%s", i,
3349 rte_ixgbe_txq_strings[stat].name);
3358 uint16_t size = ixgbe_xstats_calc_num();
3359 struct rte_eth_xstat_name xstats_names_copy[size];
3361 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3364 for (i = 0; i < limit; i++) {
3365 if (ids[i] >= size) {
3366 PMD_INIT_LOG(ERR, "id value isn't valid");
3369 strcpy(xstats_names[i].name,
3370 xstats_names_copy[ids[i]].name);
3375 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3376 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3380 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3383 if (xstats_names != NULL)
3384 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3385 snprintf(xstats_names[i].name,
3386 sizeof(xstats_names[i].name),
3387 "%s", rte_ixgbevf_stats_strings[i].name);
3388 return IXGBEVF_NB_XSTATS;
3392 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3395 struct ixgbe_hw *hw =
3396 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3397 struct ixgbe_hw_stats *hw_stats =
3398 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3399 struct ixgbe_macsec_stats *macsec_stats =
3400 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3401 dev->data->dev_private);
3402 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3403 unsigned i, stat, count = 0;
3405 count = ixgbe_xstats_calc_num();
3410 total_missed_rx = 0;
3415 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3416 &total_qbrc, &total_qprc, &total_qprdc);
3418 /* If this is a reset xstats is NULL, and we have cleared the
3419 * registers by reading them.
3424 /* Extended stats from ixgbe_hw_stats */
3426 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3427 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3428 rte_ixgbe_stats_strings[i].offset);
3429 xstats[count].id = count;
3434 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3435 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3436 rte_ixgbe_macsec_strings[i].offset);
3437 xstats[count].id = count;
3441 /* RX Priority Stats */
3442 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3443 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3444 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3445 rte_ixgbe_rxq_strings[stat].offset +
3446 (sizeof(uint64_t) * i));
3447 xstats[count].id = count;
3452 /* TX Priority Stats */
3453 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3454 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3455 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3456 rte_ixgbe_txq_strings[stat].offset +
3457 (sizeof(uint64_t) * i));
3458 xstats[count].id = count;
3466 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3467 uint64_t *values, unsigned int n)
3470 struct ixgbe_hw *hw =
3471 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3472 struct ixgbe_hw_stats *hw_stats =
3473 IXGBE_DEV_PRIVATE_TO_STATS(
3474 dev->data->dev_private);
3475 struct ixgbe_macsec_stats *macsec_stats =
3476 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3477 dev->data->dev_private);
3478 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3479 unsigned int i, stat, count = 0;
3481 count = ixgbe_xstats_calc_num();
3483 if (!ids && n < count)
3486 total_missed_rx = 0;
3491 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3492 &total_missed_rx, &total_qbrc, &total_qprc,
3495 /* If this is a reset xstats is NULL, and we have cleared the
3496 * registers by reading them.
3498 if (!ids && !values)
3501 /* Extended stats from ixgbe_hw_stats */
3503 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3504 values[count] = *(uint64_t *)(((char *)hw_stats) +
3505 rte_ixgbe_stats_strings[i].offset);
3510 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3511 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3512 rte_ixgbe_macsec_strings[i].offset);
3516 /* RX Priority Stats */
3517 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3518 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3520 *(uint64_t *)(((char *)hw_stats) +
3521 rte_ixgbe_rxq_strings[stat].offset +
3522 (sizeof(uint64_t) * i));
3527 /* TX Priority Stats */
3528 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3529 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3531 *(uint64_t *)(((char *)hw_stats) +
3532 rte_ixgbe_txq_strings[stat].offset +
3533 (sizeof(uint64_t) * i));
3541 uint16_t size = ixgbe_xstats_calc_num();
3542 uint64_t values_copy[size];
3544 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3546 for (i = 0; i < n; i++) {
3547 if (ids[i] >= size) {
3548 PMD_INIT_LOG(ERR, "id value isn't valid");
3551 values[i] = values_copy[ids[i]];
3557 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3559 struct ixgbe_hw_stats *stats =
3560 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3561 struct ixgbe_macsec_stats *macsec_stats =
3562 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3563 dev->data->dev_private);
3565 unsigned count = ixgbe_xstats_calc_num();
3567 /* HW registers are cleared on read */
3568 ixgbe_dev_xstats_get(dev, NULL, count);
3570 /* Reset software totals */
3571 memset(stats, 0, sizeof(*stats));
3572 memset(macsec_stats, 0, sizeof(*macsec_stats));
3576 ixgbevf_update_stats(struct rte_eth_dev *dev)
3578 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3579 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3580 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3582 /* Good Rx packet, include VF loopback */
3583 UPDATE_VF_STAT(IXGBE_VFGPRC,
3584 hw_stats->last_vfgprc, hw_stats->vfgprc);
3586 /* Good Rx octets, include VF loopback */
3587 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3588 hw_stats->last_vfgorc, hw_stats->vfgorc);
3590 /* Good Tx packet, include VF loopback */
3591 UPDATE_VF_STAT(IXGBE_VFGPTC,
3592 hw_stats->last_vfgptc, hw_stats->vfgptc);
3594 /* Good Tx octets, include VF loopback */
3595 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3596 hw_stats->last_vfgotc, hw_stats->vfgotc);
3598 /* Rx Multicst Packet */
3599 UPDATE_VF_STAT(IXGBE_VFMPRC,
3600 hw_stats->last_vfmprc, hw_stats->vfmprc);
3604 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3607 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3608 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3611 if (n < IXGBEVF_NB_XSTATS)
3612 return IXGBEVF_NB_XSTATS;
3614 ixgbevf_update_stats(dev);
3619 /* Extended stats */
3620 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3622 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3623 rte_ixgbevf_stats_strings[i].offset);
3626 return IXGBEVF_NB_XSTATS;
3630 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3632 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3633 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3635 ixgbevf_update_stats(dev);
3640 stats->ipackets = hw_stats->vfgprc;
3641 stats->ibytes = hw_stats->vfgorc;
3642 stats->opackets = hw_stats->vfgptc;
3643 stats->obytes = hw_stats->vfgotc;
3648 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3650 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3651 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3653 /* Sync HW register to the last stats */
3654 ixgbevf_dev_stats_get(dev, NULL);
3656 /* reset HW current stats*/
3657 hw_stats->vfgprc = 0;
3658 hw_stats->vfgorc = 0;
3659 hw_stats->vfgptc = 0;
3660 hw_stats->vfgotc = 0;
3664 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3666 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3667 u16 eeprom_verh, eeprom_verl;
3671 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3672 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3674 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3675 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3677 ret += 1; /* add the size of '\0' */
3678 if (fw_size < (u32)ret)
3685 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3687 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3688 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3689 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3691 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3692 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3693 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3695 * When DCB/VT is off, maximum number of queues changes,
3696 * except for 82598EB, which remains constant.
3698 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3699 hw->mac.type != ixgbe_mac_82598EB)
3700 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3702 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3703 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3704 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3705 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3706 dev_info->max_vfs = pci_dev->max_vfs;
3707 if (hw->mac.type == ixgbe_mac_82598EB)
3708 dev_info->max_vmdq_pools = ETH_16_POOLS;
3710 dev_info->max_vmdq_pools = ETH_64_POOLS;
3711 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3712 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3713 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3714 dev_info->rx_queue_offload_capa);
3715 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3716 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3718 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3720 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3721 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3722 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3724 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3729 dev_info->default_txconf = (struct rte_eth_txconf) {
3731 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3732 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3733 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3735 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3736 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3740 dev_info->rx_desc_lim = rx_desc_lim;
3741 dev_info->tx_desc_lim = tx_desc_lim;
3743 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3744 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3745 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3747 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3748 if (hw->mac.type == ixgbe_mac_X540 ||
3749 hw->mac.type == ixgbe_mac_X540_vf ||
3750 hw->mac.type == ixgbe_mac_X550 ||
3751 hw->mac.type == ixgbe_mac_X550_vf) {
3752 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3754 if (hw->mac.type == ixgbe_mac_X550) {
3755 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3756 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3760 static const uint32_t *
3761 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3763 static const uint32_t ptypes[] = {
3764 /* For non-vec functions,
3765 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3766 * for vec functions,
3767 * refers to _recv_raw_pkts_vec().
3771 RTE_PTYPE_L3_IPV4_EXT,
3773 RTE_PTYPE_L3_IPV6_EXT,
3777 RTE_PTYPE_TUNNEL_IP,
3778 RTE_PTYPE_INNER_L3_IPV6,
3779 RTE_PTYPE_INNER_L3_IPV6_EXT,
3780 RTE_PTYPE_INNER_L4_TCP,
3781 RTE_PTYPE_INNER_L4_UDP,
3785 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3786 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3787 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3788 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3791 #if defined(RTE_ARCH_X86)
3792 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3793 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3800 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3801 struct rte_eth_dev_info *dev_info)
3803 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3804 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3806 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3807 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3808 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3809 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3810 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3811 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3812 dev_info->max_vfs = pci_dev->max_vfs;
3813 if (hw->mac.type == ixgbe_mac_82598EB)
3814 dev_info->max_vmdq_pools = ETH_16_POOLS;
3816 dev_info->max_vmdq_pools = ETH_64_POOLS;
3817 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3818 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3819 dev_info->rx_queue_offload_capa);
3820 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3821 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3823 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3825 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3826 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3827 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3829 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3834 dev_info->default_txconf = (struct rte_eth_txconf) {
3836 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3837 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3838 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3840 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3841 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3845 dev_info->rx_desc_lim = rx_desc_lim;
3846 dev_info->tx_desc_lim = tx_desc_lim;
3850 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3851 int *link_up, int wait_to_complete)
3854 * for a quick link status checking, wait_to_compelet == 0,
3855 * skip PF link status checking
3857 bool no_pflink_check = wait_to_complete == 0;
3858 struct ixgbe_mbx_info *mbx = &hw->mbx;
3859 struct ixgbe_mac_info *mac = &hw->mac;
3860 uint32_t links_reg, in_msg;
3863 /* If we were hit with a reset drop the link */
3864 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3865 mac->get_link_status = true;
3867 if (!mac->get_link_status)
3870 /* if link status is down no point in checking to see if pf is up */
3871 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3872 if (!(links_reg & IXGBE_LINKS_UP))
3875 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3876 * before the link status is correct
3878 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3881 for (i = 0; i < 5; i++) {
3883 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3885 if (!(links_reg & IXGBE_LINKS_UP))
3890 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3891 case IXGBE_LINKS_SPEED_10G_82599:
3892 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3893 if (hw->mac.type >= ixgbe_mac_X550) {
3894 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3895 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3898 case IXGBE_LINKS_SPEED_1G_82599:
3899 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3901 case IXGBE_LINKS_SPEED_100_82599:
3902 *speed = IXGBE_LINK_SPEED_100_FULL;
3903 if (hw->mac.type == ixgbe_mac_X550) {
3904 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3905 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3908 case IXGBE_LINKS_SPEED_10_X550EM_A:
3909 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3910 /* Since Reserved in older MAC's */
3911 if (hw->mac.type >= ixgbe_mac_X550)
3912 *speed = IXGBE_LINK_SPEED_10_FULL;
3915 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3918 if (no_pflink_check) {
3919 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3920 mac->get_link_status = true;
3922 mac->get_link_status = false;
3926 /* if the read failed it could just be a mailbox collision, best wait
3927 * until we are called again and don't report an error
3929 if (mbx->ops.read(hw, &in_msg, 1, 0))
3932 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3933 /* msg is not CTS and is NACK we must have lost CTS status */
3934 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3939 /* the pf is talking, if we timed out in the past we reinit */
3940 if (!mbx->timeout) {
3945 /* if we passed all the tests above then the link is up and we no
3946 * longer need to check for link
3948 mac->get_link_status = false;
3951 *link_up = !mac->get_link_status;
3955 /* return 0 means link status changed, -1 means not changed */
3957 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3958 int wait_to_complete, int vf)
3960 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3961 struct rte_eth_link link;
3962 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3963 struct ixgbe_interrupt *intr =
3964 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3969 bool autoneg = false;
3971 memset(&link, 0, sizeof(link));
3972 link.link_status = ETH_LINK_DOWN;
3973 link.link_speed = ETH_SPEED_NUM_NONE;
3974 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3975 link.link_autoneg = ETH_LINK_AUTONEG;
3977 hw->mac.get_link_status = true;
3979 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3980 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3981 speed = hw->phy.autoneg_advertised;
3983 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3984 ixgbe_setup_link(hw, speed, true);
3987 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3988 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3992 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3994 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3997 link.link_speed = ETH_SPEED_NUM_100M;
3998 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3999 return rte_eth_linkstatus_set(dev, &link);
4003 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4004 return rte_eth_linkstatus_set(dev, &link);
4007 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4008 link.link_status = ETH_LINK_UP;
4009 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4011 switch (link_speed) {
4013 case IXGBE_LINK_SPEED_UNKNOWN:
4014 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4015 link.link_speed = ETH_SPEED_NUM_100M;
4018 case IXGBE_LINK_SPEED_100_FULL:
4019 link.link_speed = ETH_SPEED_NUM_100M;
4022 case IXGBE_LINK_SPEED_1GB_FULL:
4023 link.link_speed = ETH_SPEED_NUM_1G;
4026 case IXGBE_LINK_SPEED_2_5GB_FULL:
4027 link.link_speed = ETH_SPEED_NUM_2_5G;
4030 case IXGBE_LINK_SPEED_5GB_FULL:
4031 link.link_speed = ETH_SPEED_NUM_5G;
4034 case IXGBE_LINK_SPEED_10GB_FULL:
4035 link.link_speed = ETH_SPEED_NUM_10G;
4039 return rte_eth_linkstatus_set(dev, &link);
4043 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4045 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4049 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4051 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4055 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4057 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4060 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4061 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4062 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4066 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4068 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4071 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4072 fctrl &= (~IXGBE_FCTRL_UPE);
4073 if (dev->data->all_multicast == 1)
4074 fctrl |= IXGBE_FCTRL_MPE;
4076 fctrl &= (~IXGBE_FCTRL_MPE);
4077 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4081 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4083 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4086 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4087 fctrl |= IXGBE_FCTRL_MPE;
4088 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4092 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4094 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4097 if (dev->data->promiscuous == 1)
4098 return; /* must remain in all_multicast mode */
4100 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4101 fctrl &= (~IXGBE_FCTRL_MPE);
4102 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4106 * It clears the interrupt causes and enables the interrupt.
4107 * It will be called once only during nic initialized.
4110 * Pointer to struct rte_eth_dev.
4112 * Enable or Disable.
4115 * - On success, zero.
4116 * - On failure, a negative value.
4119 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4121 struct ixgbe_interrupt *intr =
4122 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4124 ixgbe_dev_link_status_print(dev);
4126 intr->mask |= IXGBE_EICR_LSC;
4128 intr->mask &= ~IXGBE_EICR_LSC;
4134 * It clears the interrupt causes and enables the interrupt.
4135 * It will be called once only during nic initialized.
4138 * Pointer to struct rte_eth_dev.
4141 * - On success, zero.
4142 * - On failure, a negative value.
4145 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4147 struct ixgbe_interrupt *intr =
4148 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4150 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4156 * It clears the interrupt causes and enables the interrupt.
4157 * It will be called once only during nic initialized.
4160 * Pointer to struct rte_eth_dev.
4163 * - On success, zero.
4164 * - On failure, a negative value.
4167 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4169 struct ixgbe_interrupt *intr =
4170 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4172 intr->mask |= IXGBE_EICR_LINKSEC;
4178 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4181 * Pointer to struct rte_eth_dev.
4184 * - On success, zero.
4185 * - On failure, a negative value.
4188 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4191 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4192 struct ixgbe_interrupt *intr =
4193 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4195 /* clear all cause mask */
4196 ixgbe_disable_intr(hw);
4198 /* read-on-clear nic registers here */
4199 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4200 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4204 /* set flag for async link update */
4205 if (eicr & IXGBE_EICR_LSC)
4206 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4208 if (eicr & IXGBE_EICR_MAILBOX)
4209 intr->flags |= IXGBE_FLAG_MAILBOX;
4211 if (eicr & IXGBE_EICR_LINKSEC)
4212 intr->flags |= IXGBE_FLAG_MACSEC;
4214 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4215 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4216 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4217 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4223 * It gets and then prints the link status.
4226 * Pointer to struct rte_eth_dev.
4229 * - On success, zero.
4230 * - On failure, a negative value.
4233 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4235 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4236 struct rte_eth_link link;
4238 rte_eth_linkstatus_get(dev, &link);
4240 if (link.link_status) {
4241 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4242 (int)(dev->data->port_id),
4243 (unsigned)link.link_speed,
4244 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4245 "full-duplex" : "half-duplex");
4247 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4248 (int)(dev->data->port_id));
4250 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4251 pci_dev->addr.domain,
4253 pci_dev->addr.devid,
4254 pci_dev->addr.function);
4258 * It executes link_update after knowing an interrupt occurred.
4261 * Pointer to struct rte_eth_dev.
4264 * - On success, zero.
4265 * - On failure, a negative value.
4268 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4269 struct rte_intr_handle *intr_handle)
4271 struct ixgbe_interrupt *intr =
4272 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4274 struct ixgbe_hw *hw =
4275 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4277 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4279 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4280 ixgbe_pf_mbx_process(dev);
4281 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4284 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4285 ixgbe_handle_lasi(hw);
4286 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4289 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4290 struct rte_eth_link link;
4292 /* get the link status before link update, for predicting later */
4293 rte_eth_linkstatus_get(dev, &link);
4295 ixgbe_dev_link_update(dev, 0);
4298 if (!link.link_status)
4299 /* handle it 1 sec later, wait it being stable */
4300 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4301 /* likely to down */
4303 /* handle it 4 sec later, wait it being stable */
4304 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4306 ixgbe_dev_link_status_print(dev);
4307 if (rte_eal_alarm_set(timeout * 1000,
4308 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4309 PMD_DRV_LOG(ERR, "Error setting alarm");
4311 /* remember original mask */
4312 intr->mask_original = intr->mask;
4313 /* only disable lsc interrupt */
4314 intr->mask &= ~IXGBE_EIMS_LSC;
4318 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4319 ixgbe_enable_intr(dev);
4320 rte_intr_enable(intr_handle);
4326 * Interrupt handler which shall be registered for alarm callback for delayed
4327 * handling specific interrupt to wait for the stable nic state. As the
4328 * NIC interrupt state is not stable for ixgbe after link is just down,
4329 * it needs to wait 4 seconds to get the stable status.
4332 * Pointer to interrupt handle.
4334 * The address of parameter (struct rte_eth_dev *) regsitered before.
4340 ixgbe_dev_interrupt_delayed_handler(void *param)
4342 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4343 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4344 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4345 struct ixgbe_interrupt *intr =
4346 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4347 struct ixgbe_hw *hw =
4348 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351 ixgbe_disable_intr(hw);
4353 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4354 if (eicr & IXGBE_EICR_MAILBOX)
4355 ixgbe_pf_mbx_process(dev);
4357 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4358 ixgbe_handle_lasi(hw);
4359 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4362 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4363 ixgbe_dev_link_update(dev, 0);
4364 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4365 ixgbe_dev_link_status_print(dev);
4366 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4370 if (intr->flags & IXGBE_FLAG_MACSEC) {
4371 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4373 intr->flags &= ~IXGBE_FLAG_MACSEC;
4376 /* restore original mask */
4377 intr->mask = intr->mask_original;
4378 intr->mask_original = 0;
4380 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4381 ixgbe_enable_intr(dev);
4382 rte_intr_enable(intr_handle);
4386 * Interrupt handler triggered by NIC for handling
4387 * specific interrupt.
4390 * Pointer to interrupt handle.
4392 * The address of parameter (struct rte_eth_dev *) regsitered before.
4398 ixgbe_dev_interrupt_handler(void *param)
4400 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4402 ixgbe_dev_interrupt_get_status(dev);
4403 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4407 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4409 struct ixgbe_hw *hw;
4411 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4412 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4416 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4418 struct ixgbe_hw *hw;
4420 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4425 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4427 struct ixgbe_hw *hw;
4433 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4435 fc_conf->pause_time = hw->fc.pause_time;
4436 fc_conf->high_water = hw->fc.high_water[0];
4437 fc_conf->low_water = hw->fc.low_water[0];
4438 fc_conf->send_xon = hw->fc.send_xon;
4439 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4442 * Return rx_pause status according to actual setting of
4445 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4446 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4452 * Return tx_pause status according to actual setting of
4455 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4456 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4461 if (rx_pause && tx_pause)
4462 fc_conf->mode = RTE_FC_FULL;
4464 fc_conf->mode = RTE_FC_RX_PAUSE;
4466 fc_conf->mode = RTE_FC_TX_PAUSE;
4468 fc_conf->mode = RTE_FC_NONE;
4474 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4476 struct ixgbe_hw *hw;
4478 uint32_t rx_buf_size;
4479 uint32_t max_high_water;
4481 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4488 PMD_INIT_FUNC_TRACE();
4490 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4491 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4492 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4495 * At least reserve one Ethernet frame for watermark
4496 * high_water/low_water in kilo bytes for ixgbe
4498 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4499 if ((fc_conf->high_water > max_high_water) ||
4500 (fc_conf->high_water < fc_conf->low_water)) {
4501 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4502 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4506 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4507 hw->fc.pause_time = fc_conf->pause_time;
4508 hw->fc.high_water[0] = fc_conf->high_water;
4509 hw->fc.low_water[0] = fc_conf->low_water;
4510 hw->fc.send_xon = fc_conf->send_xon;
4511 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4513 err = ixgbe_fc_enable(hw);
4515 /* Not negotiated is not an error case */
4516 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4518 /* check if we want to forward MAC frames - driver doesn't have native
4519 * capability to do that, so we'll write the registers ourselves */
4521 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4523 /* set or clear MFLCN.PMCF bit depending on configuration */
4524 if (fc_conf->mac_ctrl_frame_fwd != 0)
4525 mflcn |= IXGBE_MFLCN_PMCF;
4527 mflcn &= ~IXGBE_MFLCN_PMCF;
4529 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4530 IXGBE_WRITE_FLUSH(hw);
4535 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4540 * ixgbe_pfc_enable_generic - Enable flow control
4541 * @hw: pointer to hardware structure
4542 * @tc_num: traffic class number
4543 * Enable flow control according to the current settings.
4546 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4549 uint32_t mflcn_reg, fccfg_reg;
4551 uint32_t fcrtl, fcrth;
4555 /* Validate the water mark configuration */
4556 if (!hw->fc.pause_time) {
4557 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4561 /* Low water mark of zero causes XOFF floods */
4562 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4563 /* High/Low water can not be 0 */
4564 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4565 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4566 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4570 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4571 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4572 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4576 /* Negotiate the fc mode to use */
4577 ixgbe_fc_autoneg(hw);
4579 /* Disable any previous flow control settings */
4580 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4581 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4583 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4584 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4586 switch (hw->fc.current_mode) {
4589 * If the count of enabled RX Priority Flow control >1,
4590 * and the TX pause can not be disabled
4593 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4594 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4595 if (reg & IXGBE_FCRTH_FCEN)
4599 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4601 case ixgbe_fc_rx_pause:
4603 * Rx Flow control is enabled and Tx Flow control is
4604 * disabled by software override. Since there really
4605 * isn't a way to advertise that we are capable of RX
4606 * Pause ONLY, we will advertise that we support both
4607 * symmetric and asymmetric Rx PAUSE. Later, we will
4608 * disable the adapter's ability to send PAUSE frames.
4610 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4612 * If the count of enabled RX Priority Flow control >1,
4613 * and the TX pause can not be disabled
4616 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4617 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4618 if (reg & IXGBE_FCRTH_FCEN)
4622 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4624 case ixgbe_fc_tx_pause:
4626 * Tx Flow control is enabled, and Rx Flow control is
4627 * disabled by software override.
4629 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4632 /* Flow control (both Rx and Tx) is enabled by SW override. */
4633 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4634 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4637 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4638 ret_val = IXGBE_ERR_CONFIG;
4642 /* Set 802.3x based flow control settings. */
4643 mflcn_reg |= IXGBE_MFLCN_DPF;
4644 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4645 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4647 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4648 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4649 hw->fc.high_water[tc_num]) {
4650 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4651 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4652 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4654 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4656 * In order to prevent Tx hangs when the internal Tx
4657 * switch is enabled we must set the high water mark
4658 * to the maximum FCRTH value. This allows the Tx
4659 * switch to function even under heavy Rx workloads.
4661 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4663 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4665 /* Configure pause time (2 TCs per register) */
4666 reg = hw->fc.pause_time * 0x00010001;
4667 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4668 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4670 /* Configure flow control refresh threshold value */
4671 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4678 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4680 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4681 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4683 if (hw->mac.type != ixgbe_mac_82598EB) {
4684 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4690 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4693 uint32_t rx_buf_size;
4694 uint32_t max_high_water;
4696 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4697 struct ixgbe_hw *hw =
4698 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4699 struct ixgbe_dcb_config *dcb_config =
4700 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4702 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4709 PMD_INIT_FUNC_TRACE();
4711 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4712 tc_num = map[pfc_conf->priority];
4713 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4714 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4716 * At least reserve one Ethernet frame for watermark
4717 * high_water/low_water in kilo bytes for ixgbe
4719 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4720 if ((pfc_conf->fc.high_water > max_high_water) ||
4721 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4722 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4723 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4727 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4728 hw->fc.pause_time = pfc_conf->fc.pause_time;
4729 hw->fc.send_xon = pfc_conf->fc.send_xon;
4730 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4731 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4733 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4735 /* Not negotiated is not an error case */
4736 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4739 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4744 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4745 struct rte_eth_rss_reta_entry64 *reta_conf,
4748 uint16_t i, sp_reta_size;
4751 uint16_t idx, shift;
4752 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4755 PMD_INIT_FUNC_TRACE();
4757 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4758 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4763 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4764 if (reta_size != sp_reta_size) {
4765 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4766 "(%d) doesn't match the number hardware can supported "
4767 "(%d)", reta_size, sp_reta_size);
4771 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4772 idx = i / RTE_RETA_GROUP_SIZE;
4773 shift = i % RTE_RETA_GROUP_SIZE;
4774 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4778 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4779 if (mask == IXGBE_4_BIT_MASK)
4782 r = IXGBE_READ_REG(hw, reta_reg);
4783 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4784 if (mask & (0x1 << j))
4785 reta |= reta_conf[idx].reta[shift + j] <<
4788 reta |= r & (IXGBE_8_BIT_MASK <<
4791 IXGBE_WRITE_REG(hw, reta_reg, reta);
4798 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4799 struct rte_eth_rss_reta_entry64 *reta_conf,
4802 uint16_t i, sp_reta_size;
4805 uint16_t idx, shift;
4806 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4809 PMD_INIT_FUNC_TRACE();
4810 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4811 if (reta_size != sp_reta_size) {
4812 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4813 "(%d) doesn't match the number hardware can supported "
4814 "(%d)", reta_size, sp_reta_size);
4818 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4819 idx = i / RTE_RETA_GROUP_SIZE;
4820 shift = i % RTE_RETA_GROUP_SIZE;
4821 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4826 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4827 reta = IXGBE_READ_REG(hw, reta_reg);
4828 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4829 if (mask & (0x1 << j))
4830 reta_conf[idx].reta[shift + j] =
4831 ((reta >> (CHAR_BIT * j)) &
4840 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4841 uint32_t index, uint32_t pool)
4843 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4844 uint32_t enable_addr = 1;
4846 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4851 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4853 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4855 ixgbe_clear_rar(hw, index);
4859 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4861 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4863 ixgbe_remove_rar(dev, 0);
4864 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4870 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4872 if (strcmp(dev->device->driver->name, drv->driver.name))
4879 is_ixgbe_supported(struct rte_eth_dev *dev)
4881 return is_device_supported(dev, &rte_ixgbe_pmd);
4885 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4889 struct ixgbe_hw *hw;
4890 struct rte_eth_dev_info dev_info;
4891 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4892 struct rte_eth_dev_data *dev_data = dev->data;
4894 ixgbe_dev_info_get(dev, &dev_info);
4896 /* check that mtu is within the allowed range */
4897 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4900 /* If device is started, refuse mtu that requires the support of
4901 * scattered packets when this feature has not been enabled before.
4903 if (dev_data->dev_started && !dev_data->scattered_rx &&
4904 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4905 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4906 PMD_INIT_LOG(ERR, "Stop port first.");
4910 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4911 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4913 /* switch to jumbo mode if needed */
4914 if (frame_size > ETHER_MAX_LEN) {
4915 dev->data->dev_conf.rxmode.offloads |=
4916 DEV_RX_OFFLOAD_JUMBO_FRAME;
4917 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4919 dev->data->dev_conf.rxmode.offloads &=
4920 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4921 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4923 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4925 /* update max frame size */
4926 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4928 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4929 maxfrs &= 0x0000FFFF;
4930 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4931 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4937 * Virtual Function operations
4940 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4942 struct ixgbe_interrupt *intr =
4943 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4944 struct ixgbe_hw *hw =
4945 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4947 PMD_INIT_FUNC_TRACE();
4949 /* Clear interrupt mask to stop from interrupts being generated */
4950 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4952 IXGBE_WRITE_FLUSH(hw);
4954 /* Clear mask value. */
4959 ixgbevf_intr_enable(struct rte_eth_dev *dev)
4961 struct ixgbe_interrupt *intr =
4962 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4963 struct ixgbe_hw *hw =
4964 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4966 PMD_INIT_FUNC_TRACE();
4968 /* VF enable interrupt autoclean */
4969 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4970 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4971 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4973 IXGBE_WRITE_FLUSH(hw);
4975 /* Save IXGBE_VTEIMS value to mask. */
4976 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
4980 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4982 struct rte_eth_conf *conf = &dev->data->dev_conf;
4983 struct ixgbe_adapter *adapter =
4984 (struct ixgbe_adapter *)dev->data->dev_private;
4986 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4987 dev->data->port_id);
4990 * VF has no ability to enable/disable HW CRC
4991 * Keep the persistent behavior the same as Host PF
4993 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4994 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4995 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4996 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4999 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
5000 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5001 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
5006 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5007 * allocation or vector Rx preconditions we will reset it.
5009 adapter->rx_bulk_alloc_allowed = true;
5010 adapter->rx_vec_allowed = true;
5016 ixgbevf_dev_start(struct rte_eth_dev *dev)
5018 struct ixgbe_hw *hw =
5019 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5020 uint32_t intr_vector = 0;
5021 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5022 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5026 PMD_INIT_FUNC_TRACE();
5028 err = hw->mac.ops.reset_hw(hw);
5030 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5033 hw->mac.get_link_status = true;
5035 /* negotiate mailbox API version to use with the PF. */
5036 ixgbevf_negotiate_api(hw);
5038 ixgbevf_dev_tx_init(dev);
5040 /* This can fail when allocating mbufs for descriptor rings */
5041 err = ixgbevf_dev_rx_init(dev);
5043 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5044 ixgbe_dev_clear_queues(dev);
5049 ixgbevf_set_vfta_all(dev, 1);
5052 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5053 ETH_VLAN_EXTEND_MASK;
5054 err = ixgbevf_vlan_offload_config(dev, mask);
5056 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5057 ixgbe_dev_clear_queues(dev);
5061 ixgbevf_dev_rxtx_start(dev);
5063 ixgbevf_dev_link_update(dev, 0);
5065 /* check and configure queue intr-vector mapping */
5066 if (rte_intr_cap_multiple(intr_handle) &&
5067 dev->data->dev_conf.intr_conf.rxq) {
5068 /* According to datasheet, only vector 0/1/2 can be used,
5069 * now only one vector is used for Rx queue
5072 if (rte_intr_efd_enable(intr_handle, intr_vector))
5076 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5077 intr_handle->intr_vec =
5078 rte_zmalloc("intr_vec",
5079 dev->data->nb_rx_queues * sizeof(int), 0);
5080 if (intr_handle->intr_vec == NULL) {
5081 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5082 " intr_vec", dev->data->nb_rx_queues);
5086 ixgbevf_configure_msix(dev);
5088 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5089 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5090 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5091 * is not cleared, it will fail when following rte_intr_enable( ) tries
5092 * to map Rx queue interrupt to other VFIO vectors.
5093 * So clear uio/vfio intr/evevnfd first to avoid failure.
5095 rte_intr_disable(intr_handle);
5097 rte_intr_enable(intr_handle);
5099 /* Re-enable interrupt for VF */
5100 ixgbevf_intr_enable(dev);
5106 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5108 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5110 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5112 PMD_INIT_FUNC_TRACE();
5114 ixgbevf_intr_disable(dev);
5116 hw->adapter_stopped = 1;
5117 ixgbe_stop_adapter(hw);
5120 * Clear what we set, but we still keep shadow_vfta to
5121 * restore after device starts
5123 ixgbevf_set_vfta_all(dev, 0);
5125 /* Clear stored conf */
5126 dev->data->scattered_rx = 0;
5128 ixgbe_dev_clear_queues(dev);
5130 /* Clean datapath event and queue/vec mapping */
5131 rte_intr_efd_disable(intr_handle);
5132 if (intr_handle->intr_vec != NULL) {
5133 rte_free(intr_handle->intr_vec);
5134 intr_handle->intr_vec = NULL;
5139 ixgbevf_dev_close(struct rte_eth_dev *dev)
5141 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5143 PMD_INIT_FUNC_TRACE();
5147 ixgbevf_dev_stop(dev);
5149 ixgbe_dev_free_queues(dev);
5152 * Remove the VF MAC address ro ensure
5153 * that the VF traffic goes to the PF
5154 * after stop, close and detach of the VF
5156 ixgbevf_remove_mac_addr(dev, 0);
5163 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5167 ret = eth_ixgbevf_dev_uninit(dev);
5171 ret = eth_ixgbevf_dev_init(dev);
5176 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5178 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5179 struct ixgbe_vfta *shadow_vfta =
5180 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5181 int i = 0, j = 0, vfta = 0, mask = 1;
5183 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5184 vfta = shadow_vfta->vfta[i];
5187 for (j = 0; j < 32; j++) {
5189 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5199 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5201 struct ixgbe_hw *hw =
5202 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5203 struct ixgbe_vfta *shadow_vfta =
5204 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5205 uint32_t vid_idx = 0;
5206 uint32_t vid_bit = 0;
5209 PMD_INIT_FUNC_TRACE();
5211 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5212 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5214 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5217 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5218 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5220 /* Save what we set and retore it after device reset */
5222 shadow_vfta->vfta[vid_idx] |= vid_bit;
5224 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5230 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5232 struct ixgbe_hw *hw =
5233 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5236 PMD_INIT_FUNC_TRACE();
5238 if (queue >= hw->mac.max_rx_queues)
5241 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5243 ctrl |= IXGBE_RXDCTL_VME;
5245 ctrl &= ~IXGBE_RXDCTL_VME;
5246 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5248 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5252 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5254 struct ixgbe_rx_queue *rxq;
5258 /* VF function only support hw strip feature, others are not support */
5259 if (mask & ETH_VLAN_STRIP_MASK) {
5260 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5261 rxq = dev->data->rx_queues[i];
5262 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5263 ixgbevf_vlan_strip_queue_set(dev, i, on);
5271 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5273 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5275 ixgbevf_vlan_offload_config(dev, mask);
5281 ixgbe_vt_check(struct ixgbe_hw *hw)
5285 /* if Virtualization Technology is enabled */
5286 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5287 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5288 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5296 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5298 uint32_t vector = 0;
5300 switch (hw->mac.mc_filter_type) {
5301 case 0: /* use bits [47:36] of the address */
5302 vector = ((uc_addr->addr_bytes[4] >> 4) |
5303 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5305 case 1: /* use bits [46:35] of the address */
5306 vector = ((uc_addr->addr_bytes[4] >> 3) |
5307 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5309 case 2: /* use bits [45:34] of the address */
5310 vector = ((uc_addr->addr_bytes[4] >> 2) |
5311 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5313 case 3: /* use bits [43:32] of the address */
5314 vector = ((uc_addr->addr_bytes[4]) |
5315 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5317 default: /* Invalid mc_filter_type */
5321 /* vector can only be 12-bits or boundary will be exceeded */
5327 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5335 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5336 const uint32_t ixgbe_uta_bit_shift = 5;
5337 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5338 const uint32_t bit1 = 0x1;
5340 struct ixgbe_hw *hw =
5341 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5342 struct ixgbe_uta_info *uta_info =
5343 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5345 /* The UTA table only exists on 82599 hardware and newer */
5346 if (hw->mac.type < ixgbe_mac_82599EB)
5349 vector = ixgbe_uta_vector(hw, mac_addr);
5350 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5351 uta_shift = vector & ixgbe_uta_bit_mask;
5353 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5357 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5359 uta_info->uta_in_use++;
5360 reg_val |= (bit1 << uta_shift);
5361 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5363 uta_info->uta_in_use--;
5364 reg_val &= ~(bit1 << uta_shift);
5365 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5368 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5370 if (uta_info->uta_in_use > 0)
5371 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5372 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5374 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5380 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5383 struct ixgbe_hw *hw =
5384 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5385 struct ixgbe_uta_info *uta_info =
5386 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5388 /* The UTA table only exists on 82599 hardware and newer */
5389 if (hw->mac.type < ixgbe_mac_82599EB)
5393 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5394 uta_info->uta_shadow[i] = ~0;
5395 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5398 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5399 uta_info->uta_shadow[i] = 0;
5400 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5408 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5410 uint32_t new_val = orig_val;
5412 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5413 new_val |= IXGBE_VMOLR_AUPE;
5414 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5415 new_val |= IXGBE_VMOLR_ROMPE;
5416 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5417 new_val |= IXGBE_VMOLR_ROPE;
5418 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5419 new_val |= IXGBE_VMOLR_BAM;
5420 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5421 new_val |= IXGBE_VMOLR_MPE;
5426 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5427 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5428 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5429 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5430 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5431 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5432 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5435 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5436 struct rte_eth_mirror_conf *mirror_conf,
5437 uint8_t rule_id, uint8_t on)
5439 uint32_t mr_ctl, vlvf;
5440 uint32_t mp_lsb = 0;
5441 uint32_t mv_msb = 0;
5442 uint32_t mv_lsb = 0;
5443 uint32_t mp_msb = 0;
5446 uint64_t vlan_mask = 0;
5448 const uint8_t pool_mask_offset = 32;
5449 const uint8_t vlan_mask_offset = 32;
5450 const uint8_t dst_pool_offset = 8;
5451 const uint8_t rule_mr_offset = 4;
5452 const uint8_t mirror_rule_mask = 0x0F;
5454 struct ixgbe_mirror_info *mr_info =
5455 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5456 struct ixgbe_hw *hw =
5457 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5458 uint8_t mirror_type = 0;
5460 if (ixgbe_vt_check(hw) < 0)
5463 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5466 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5467 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5468 mirror_conf->rule_type);
5472 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5473 mirror_type |= IXGBE_MRCTL_VLME;
5474 /* Check if vlan id is valid and find conresponding VLAN ID
5477 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5478 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5479 /* search vlan id related pool vlan filter
5482 reg_index = ixgbe_find_vlvf_slot(
5484 mirror_conf->vlan.vlan_id[i],
5488 vlvf = IXGBE_READ_REG(hw,
5489 IXGBE_VLVF(reg_index));
5490 if ((vlvf & IXGBE_VLVF_VIEN) &&
5491 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5492 mirror_conf->vlan.vlan_id[i]))
5493 vlan_mask |= (1ULL << reg_index);
5500 mv_lsb = vlan_mask & 0xFFFFFFFF;
5501 mv_msb = vlan_mask >> vlan_mask_offset;
5503 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5504 mirror_conf->vlan.vlan_mask;
5505 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5506 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5507 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5508 mirror_conf->vlan.vlan_id[i];
5513 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5514 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5515 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5520 * if enable pool mirror, write related pool mask register,if disable
5521 * pool mirror, clear PFMRVM register
5523 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5524 mirror_type |= IXGBE_MRCTL_VPME;
5526 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5527 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5528 mr_info->mr_conf[rule_id].pool_mask =
5529 mirror_conf->pool_mask;
5534 mr_info->mr_conf[rule_id].pool_mask = 0;
5537 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5538 mirror_type |= IXGBE_MRCTL_UPME;
5539 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5540 mirror_type |= IXGBE_MRCTL_DPME;
5542 /* read mirror control register and recalculate it */
5543 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5546 mr_ctl |= mirror_type;
5547 mr_ctl &= mirror_rule_mask;
5548 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5550 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5553 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5554 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5556 /* write mirrror control register */
5557 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5559 /* write pool mirrror control register */
5560 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5561 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5562 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5565 /* write VLAN mirrror control register */
5566 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5567 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5568 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5576 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5579 uint32_t lsb_val = 0;
5580 uint32_t msb_val = 0;
5581 const uint8_t rule_mr_offset = 4;
5583 struct ixgbe_hw *hw =
5584 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5585 struct ixgbe_mirror_info *mr_info =
5586 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5588 if (ixgbe_vt_check(hw) < 0)
5591 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5594 memset(&mr_info->mr_conf[rule_id], 0,
5595 sizeof(struct rte_eth_mirror_conf));
5597 /* clear PFVMCTL register */
5598 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5600 /* clear pool mask register */
5601 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5602 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5604 /* clear vlan mask register */
5605 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5606 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5612 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5614 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5615 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5616 struct ixgbe_interrupt *intr =
5617 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5618 struct ixgbe_hw *hw =
5619 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5620 uint32_t vec = IXGBE_MISC_VEC_ID;
5622 if (rte_intr_allow_others(intr_handle))
5623 vec = IXGBE_RX_VEC_START;
5624 intr->mask |= (1 << vec);
5625 RTE_SET_USED(queue_id);
5626 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5628 rte_intr_enable(intr_handle);
5634 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5636 struct ixgbe_interrupt *intr =
5637 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5638 struct ixgbe_hw *hw =
5639 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5640 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5641 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5642 uint32_t vec = IXGBE_MISC_VEC_ID;
5644 if (rte_intr_allow_others(intr_handle))
5645 vec = IXGBE_RX_VEC_START;
5646 intr->mask &= ~(1 << vec);
5647 RTE_SET_USED(queue_id);
5648 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5654 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5656 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5657 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5659 struct ixgbe_hw *hw =
5660 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5661 struct ixgbe_interrupt *intr =
5662 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5664 if (queue_id < 16) {
5665 ixgbe_disable_intr(hw);
5666 intr->mask |= (1 << queue_id);
5667 ixgbe_enable_intr(dev);
5668 } else if (queue_id < 32) {
5669 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5670 mask &= (1 << queue_id);
5671 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5672 } else if (queue_id < 64) {
5673 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5674 mask &= (1 << (queue_id - 32));
5675 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5677 rte_intr_enable(intr_handle);
5683 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5686 struct ixgbe_hw *hw =
5687 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5688 struct ixgbe_interrupt *intr =
5689 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5691 if (queue_id < 16) {
5692 ixgbe_disable_intr(hw);
5693 intr->mask &= ~(1 << queue_id);
5694 ixgbe_enable_intr(dev);
5695 } else if (queue_id < 32) {
5696 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5697 mask &= ~(1 << queue_id);
5698 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5699 } else if (queue_id < 64) {
5700 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5701 mask &= ~(1 << (queue_id - 32));
5702 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5709 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5710 uint8_t queue, uint8_t msix_vector)
5714 if (direction == -1) {
5716 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5717 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5720 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5722 /* rx or tx cause */
5723 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5724 idx = ((16 * (queue & 1)) + (8 * direction));
5725 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5726 tmp &= ~(0xFF << idx);
5727 tmp |= (msix_vector << idx);
5728 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5733 * set the IVAR registers, mapping interrupt causes to vectors
5735 * pointer to ixgbe_hw struct
5737 * 0 for Rx, 1 for Tx, -1 for other causes
5739 * queue to map the corresponding interrupt to
5741 * the vector to map to the corresponding queue
5744 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5745 uint8_t queue, uint8_t msix_vector)
5749 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5750 if (hw->mac.type == ixgbe_mac_82598EB) {
5751 if (direction == -1)
5753 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5754 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5755 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5756 tmp |= (msix_vector << (8 * (queue & 0x3)));
5757 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5758 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5759 (hw->mac.type == ixgbe_mac_X540) ||
5760 (hw->mac.type == ixgbe_mac_X550)) {
5761 if (direction == -1) {
5763 idx = ((queue & 1) * 8);
5764 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5765 tmp &= ~(0xFF << idx);
5766 tmp |= (msix_vector << idx);
5767 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5769 /* rx or tx causes */
5770 idx = ((16 * (queue & 1)) + (8 * direction));
5771 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5772 tmp &= ~(0xFF << idx);
5773 tmp |= (msix_vector << idx);
5774 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5780 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5782 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5783 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5784 struct ixgbe_hw *hw =
5785 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5787 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5788 uint32_t base = IXGBE_MISC_VEC_ID;
5790 /* Configure VF other cause ivar */
5791 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5793 /* won't configure msix register if no mapping is done
5794 * between intr vector and event fd.
5796 if (!rte_intr_dp_is_en(intr_handle))
5799 if (rte_intr_allow_others(intr_handle)) {
5800 base = IXGBE_RX_VEC_START;
5801 vector_idx = IXGBE_RX_VEC_START;
5804 /* Configure all RX queues of VF */
5805 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5806 /* Force all queue use vector 0,
5807 * as IXGBE_VF_MAXMSIVECOTR = 1
5809 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5810 intr_handle->intr_vec[q_idx] = vector_idx;
5811 if (vector_idx < base + intr_handle->nb_efd - 1)
5815 /* As RX queue setting above show, all queues use the vector 0.
5816 * Set only the ITR value of IXGBE_MISC_VEC_ID.
5818 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5819 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5820 | IXGBE_EITR_CNT_WDIS);
5824 * Sets up the hardware to properly generate MSI-X interrupts
5826 * board private structure
5829 ixgbe_configure_msix(struct rte_eth_dev *dev)
5831 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5832 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5833 struct ixgbe_hw *hw =
5834 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5835 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5836 uint32_t vec = IXGBE_MISC_VEC_ID;
5840 /* won't configure msix register if no mapping is done
5841 * between intr vector and event fd
5842 * but if misx has been enabled already, need to configure
5843 * auto clean, auto mask and throttling.
5845 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5846 if (!rte_intr_dp_is_en(intr_handle) &&
5847 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5850 if (rte_intr_allow_others(intr_handle))
5851 vec = base = IXGBE_RX_VEC_START;
5853 /* setup GPIE for MSI-x mode */
5854 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5855 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5856 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5857 /* auto clearing and auto setting corresponding bits in EIMS
5858 * when MSI-X interrupt is triggered
5860 if (hw->mac.type == ixgbe_mac_82598EB) {
5861 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5863 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5864 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5866 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5868 /* Populate the IVAR table and set the ITR values to the
5869 * corresponding register.
5871 if (rte_intr_dp_is_en(intr_handle)) {
5872 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5874 /* by default, 1:1 mapping */
5875 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5876 intr_handle->intr_vec[queue_id] = vec;
5877 if (vec < base + intr_handle->nb_efd - 1)
5881 switch (hw->mac.type) {
5882 case ixgbe_mac_82598EB:
5883 ixgbe_set_ivar_map(hw, -1,
5884 IXGBE_IVAR_OTHER_CAUSES_INDEX,
5887 case ixgbe_mac_82599EB:
5888 case ixgbe_mac_X540:
5889 case ixgbe_mac_X550:
5890 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5896 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5897 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5898 | IXGBE_EITR_CNT_WDIS);
5900 /* set up to autoclear timer, and the vectors */
5901 mask = IXGBE_EIMS_ENABLE_MASK;
5902 mask &= ~(IXGBE_EIMS_OTHER |
5903 IXGBE_EIMS_MAILBOX |
5906 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5910 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5911 uint16_t queue_idx, uint16_t tx_rate)
5913 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5914 struct rte_eth_rxmode *rxmode;
5915 uint32_t rf_dec, rf_int;
5917 uint16_t link_speed = dev->data->dev_link.link_speed;
5919 if (queue_idx >= hw->mac.max_tx_queues)
5923 /* Calculate the rate factor values to set */
5924 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5925 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5926 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5928 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5929 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5930 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5931 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5936 rxmode = &dev->data->dev_conf.rxmode;
5938 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5939 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5942 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5943 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5944 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5945 IXGBE_MMW_SIZE_JUMBO_FRAME);
5947 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5948 IXGBE_MMW_SIZE_DEFAULT);
5950 /* Set RTTBCNRC of queue X */
5951 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5952 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5953 IXGBE_WRITE_FLUSH(hw);
5959 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5960 __attribute__((unused)) uint32_t index,
5961 __attribute__((unused)) uint32_t pool)
5963 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5967 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5968 * operation. Trap this case to avoid exhausting the [very limited]
5969 * set of PF resources used to store VF MAC addresses.
5971 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5973 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5975 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5976 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5977 mac_addr->addr_bytes[0],
5978 mac_addr->addr_bytes[1],
5979 mac_addr->addr_bytes[2],
5980 mac_addr->addr_bytes[3],
5981 mac_addr->addr_bytes[4],
5982 mac_addr->addr_bytes[5],
5988 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5990 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5991 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5992 struct ether_addr *mac_addr;
5997 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5998 * not support the deletion of a given MAC address.
5999 * Instead, it imposes to delete all MAC addresses, then to add again
6000 * all MAC addresses with the exception of the one to be deleted.
6002 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6005 * Add again all MAC addresses, with the exception of the deleted one
6006 * and of the permanent MAC address.
6008 for (i = 0, mac_addr = dev->data->mac_addrs;
6009 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6010 /* Skip the deleted MAC address */
6013 /* Skip NULL MAC addresses */
6014 if (is_zero_ether_addr(mac_addr))
6016 /* Skip the permanent MAC address */
6017 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6019 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6022 "Adding again MAC address "
6023 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6025 mac_addr->addr_bytes[0],
6026 mac_addr->addr_bytes[1],
6027 mac_addr->addr_bytes[2],
6028 mac_addr->addr_bytes[3],
6029 mac_addr->addr_bytes[4],
6030 mac_addr->addr_bytes[5],
6036 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6038 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6040 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6046 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6047 struct rte_eth_syn_filter *filter,
6050 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6051 struct ixgbe_filter_info *filter_info =
6052 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6056 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6059 syn_info = filter_info->syn_info;
6062 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6064 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6065 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6067 if (filter->hig_pri)
6068 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6070 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6072 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6073 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6075 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6078 filter_info->syn_info = synqf;
6079 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6080 IXGBE_WRITE_FLUSH(hw);
6085 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6086 struct rte_eth_syn_filter *filter)
6088 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6089 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6091 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6092 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6093 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6100 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6101 enum rte_filter_op filter_op,
6104 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6107 MAC_TYPE_FILTER_SUP(hw->mac.type);
6109 if (filter_op == RTE_ETH_FILTER_NOP)
6113 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6118 switch (filter_op) {
6119 case RTE_ETH_FILTER_ADD:
6120 ret = ixgbe_syn_filter_set(dev,
6121 (struct rte_eth_syn_filter *)arg,
6124 case RTE_ETH_FILTER_DELETE:
6125 ret = ixgbe_syn_filter_set(dev,
6126 (struct rte_eth_syn_filter *)arg,
6129 case RTE_ETH_FILTER_GET:
6130 ret = ixgbe_syn_filter_get(dev,
6131 (struct rte_eth_syn_filter *)arg);
6134 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6143 static inline enum ixgbe_5tuple_protocol
6144 convert_protocol_type(uint8_t protocol_value)
6146 if (protocol_value == IPPROTO_TCP)
6147 return IXGBE_FILTER_PROTOCOL_TCP;
6148 else if (protocol_value == IPPROTO_UDP)
6149 return IXGBE_FILTER_PROTOCOL_UDP;
6150 else if (protocol_value == IPPROTO_SCTP)
6151 return IXGBE_FILTER_PROTOCOL_SCTP;
6153 return IXGBE_FILTER_PROTOCOL_NONE;
6156 /* inject a 5-tuple filter to HW */
6158 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6159 struct ixgbe_5tuple_filter *filter)
6161 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6163 uint32_t ftqf, sdpqf;
6164 uint32_t l34timir = 0;
6165 uint8_t mask = 0xff;
6169 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6170 IXGBE_SDPQF_DSTPORT_SHIFT);
6171 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6173 ftqf = (uint32_t)(filter->filter_info.proto &
6174 IXGBE_FTQF_PROTOCOL_MASK);
6175 ftqf |= (uint32_t)((filter->filter_info.priority &
6176 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6177 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6178 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6179 if (filter->filter_info.dst_ip_mask == 0)
6180 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6181 if (filter->filter_info.src_port_mask == 0)
6182 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6183 if (filter->filter_info.dst_port_mask == 0)
6184 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6185 if (filter->filter_info.proto_mask == 0)
6186 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6187 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6188 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6189 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6191 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6192 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6193 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6194 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6196 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6197 l34timir |= (uint32_t)(filter->queue <<
6198 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6199 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6203 * add a 5tuple filter
6206 * dev: Pointer to struct rte_eth_dev.
6207 * index: the index the filter allocates.
6208 * filter: ponter to the filter that will be added.
6209 * rx_queue: the queue id the filter assigned to.
6212 * - On success, zero.
6213 * - On failure, a negative value.
6216 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6217 struct ixgbe_5tuple_filter *filter)
6219 struct ixgbe_filter_info *filter_info =
6220 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6224 * look for an unused 5tuple filter index,
6225 * and insert the filter to list.
6227 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6228 idx = i / (sizeof(uint32_t) * NBBY);
6229 shift = i % (sizeof(uint32_t) * NBBY);
6230 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6231 filter_info->fivetuple_mask[idx] |= 1 << shift;
6233 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6239 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6240 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6244 ixgbe_inject_5tuple_filter(dev, filter);
6250 * remove a 5tuple filter
6253 * dev: Pointer to struct rte_eth_dev.
6254 * filter: the pointer of the filter will be removed.
6257 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6258 struct ixgbe_5tuple_filter *filter)
6260 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6261 struct ixgbe_filter_info *filter_info =
6262 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6263 uint16_t index = filter->index;
6265 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6266 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6267 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6270 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6271 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6272 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6273 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6274 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6278 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6280 struct ixgbe_hw *hw;
6281 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6282 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6284 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6286 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6289 /* refuse mtu that requires the support of scattered packets when this
6290 * feature has not been enabled before.
6292 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6293 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6294 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6298 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6299 * request of the version 2.0 of the mailbox API.
6300 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6301 * of the mailbox API.
6302 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6303 * prior to 3.11.33 which contains the following change:
6304 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6306 ixgbevf_rlpml_set_vf(hw, max_frame);
6308 /* update max frame size */
6309 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6313 static inline struct ixgbe_5tuple_filter *
6314 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6315 struct ixgbe_5tuple_filter_info *key)
6317 struct ixgbe_5tuple_filter *it;
6319 TAILQ_FOREACH(it, filter_list, entries) {
6320 if (memcmp(key, &it->filter_info,
6321 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6328 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6330 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6331 struct ixgbe_5tuple_filter_info *filter_info)
6333 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6334 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6335 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6338 switch (filter->dst_ip_mask) {
6340 filter_info->dst_ip_mask = 0;
6341 filter_info->dst_ip = filter->dst_ip;
6344 filter_info->dst_ip_mask = 1;
6347 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6351 switch (filter->src_ip_mask) {
6353 filter_info->src_ip_mask = 0;
6354 filter_info->src_ip = filter->src_ip;
6357 filter_info->src_ip_mask = 1;
6360 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6364 switch (filter->dst_port_mask) {
6366 filter_info->dst_port_mask = 0;
6367 filter_info->dst_port = filter->dst_port;
6370 filter_info->dst_port_mask = 1;
6373 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6377 switch (filter->src_port_mask) {
6379 filter_info->src_port_mask = 0;
6380 filter_info->src_port = filter->src_port;
6383 filter_info->src_port_mask = 1;
6386 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6390 switch (filter->proto_mask) {
6392 filter_info->proto_mask = 0;
6393 filter_info->proto =
6394 convert_protocol_type(filter->proto);
6397 filter_info->proto_mask = 1;
6400 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6404 filter_info->priority = (uint8_t)filter->priority;
6409 * add or delete a ntuple filter
6412 * dev: Pointer to struct rte_eth_dev.
6413 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6414 * add: if true, add filter, if false, remove filter
6417 * - On success, zero.
6418 * - On failure, a negative value.
6421 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6422 struct rte_eth_ntuple_filter *ntuple_filter,
6425 struct ixgbe_filter_info *filter_info =
6426 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6427 struct ixgbe_5tuple_filter_info filter_5tuple;
6428 struct ixgbe_5tuple_filter *filter;
6431 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6432 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6436 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6437 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6441 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6443 if (filter != NULL && add) {
6444 PMD_DRV_LOG(ERR, "filter exists.");
6447 if (filter == NULL && !add) {
6448 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6453 filter = rte_zmalloc("ixgbe_5tuple_filter",
6454 sizeof(struct ixgbe_5tuple_filter), 0);
6457 rte_memcpy(&filter->filter_info,
6459 sizeof(struct ixgbe_5tuple_filter_info));
6460 filter->queue = ntuple_filter->queue;
6461 ret = ixgbe_add_5tuple_filter(dev, filter);
6467 ixgbe_remove_5tuple_filter(dev, filter);
6473 * get a ntuple filter
6476 * dev: Pointer to struct rte_eth_dev.
6477 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6480 * - On success, zero.
6481 * - On failure, a negative value.
6484 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6485 struct rte_eth_ntuple_filter *ntuple_filter)
6487 struct ixgbe_filter_info *filter_info =
6488 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6489 struct ixgbe_5tuple_filter_info filter_5tuple;
6490 struct ixgbe_5tuple_filter *filter;
6493 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6494 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6498 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6499 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6503 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6505 if (filter == NULL) {
6506 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6509 ntuple_filter->queue = filter->queue;
6514 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6515 * @dev: pointer to rte_eth_dev structure
6516 * @filter_op:operation will be taken.
6517 * @arg: a pointer to specific structure corresponding to the filter_op
6520 * - On success, zero.
6521 * - On failure, a negative value.
6524 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6525 enum rte_filter_op filter_op,
6528 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6531 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6533 if (filter_op == RTE_ETH_FILTER_NOP)
6537 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6542 switch (filter_op) {
6543 case RTE_ETH_FILTER_ADD:
6544 ret = ixgbe_add_del_ntuple_filter(dev,
6545 (struct rte_eth_ntuple_filter *)arg,
6548 case RTE_ETH_FILTER_DELETE:
6549 ret = ixgbe_add_del_ntuple_filter(dev,
6550 (struct rte_eth_ntuple_filter *)arg,
6553 case RTE_ETH_FILTER_GET:
6554 ret = ixgbe_get_ntuple_filter(dev,
6555 (struct rte_eth_ntuple_filter *)arg);
6558 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6566 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6567 struct rte_eth_ethertype_filter *filter,
6570 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6571 struct ixgbe_filter_info *filter_info =
6572 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6576 struct ixgbe_ethertype_filter ethertype_filter;
6578 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6581 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6582 filter->ether_type == ETHER_TYPE_IPv6) {
6583 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6584 " ethertype filter.", filter->ether_type);
6588 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6589 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6592 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6593 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6597 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6598 if (ret >= 0 && add) {
6599 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6600 filter->ether_type);
6603 if (ret < 0 && !add) {
6604 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6605 filter->ether_type);
6610 etqf = IXGBE_ETQF_FILTER_EN;
6611 etqf |= (uint32_t)filter->ether_type;
6612 etqs |= (uint32_t)((filter->queue <<
6613 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6614 IXGBE_ETQS_RX_QUEUE);
6615 etqs |= IXGBE_ETQS_QUEUE_EN;
6617 ethertype_filter.ethertype = filter->ether_type;
6618 ethertype_filter.etqf = etqf;
6619 ethertype_filter.etqs = etqs;
6620 ethertype_filter.conf = FALSE;
6621 ret = ixgbe_ethertype_filter_insert(filter_info,
6624 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6628 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6632 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6633 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6634 IXGBE_WRITE_FLUSH(hw);
6640 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6641 struct rte_eth_ethertype_filter *filter)
6643 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6644 struct ixgbe_filter_info *filter_info =
6645 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6646 uint32_t etqf, etqs;
6649 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6651 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6652 filter->ether_type);
6656 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6657 if (etqf & IXGBE_ETQF_FILTER_EN) {
6658 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6659 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6661 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6662 IXGBE_ETQS_RX_QUEUE_SHIFT;
6669 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6670 * @dev: pointer to rte_eth_dev structure
6671 * @filter_op:operation will be taken.
6672 * @arg: a pointer to specific structure corresponding to the filter_op
6675 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6676 enum rte_filter_op filter_op,
6679 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6682 MAC_TYPE_FILTER_SUP(hw->mac.type);
6684 if (filter_op == RTE_ETH_FILTER_NOP)
6688 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6693 switch (filter_op) {
6694 case RTE_ETH_FILTER_ADD:
6695 ret = ixgbe_add_del_ethertype_filter(dev,
6696 (struct rte_eth_ethertype_filter *)arg,
6699 case RTE_ETH_FILTER_DELETE:
6700 ret = ixgbe_add_del_ethertype_filter(dev,
6701 (struct rte_eth_ethertype_filter *)arg,
6704 case RTE_ETH_FILTER_GET:
6705 ret = ixgbe_get_ethertype_filter(dev,
6706 (struct rte_eth_ethertype_filter *)arg);
6709 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6717 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6718 enum rte_filter_type filter_type,
6719 enum rte_filter_op filter_op,
6724 switch (filter_type) {
6725 case RTE_ETH_FILTER_NTUPLE:
6726 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6728 case RTE_ETH_FILTER_ETHERTYPE:
6729 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6731 case RTE_ETH_FILTER_SYN:
6732 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6734 case RTE_ETH_FILTER_FDIR:
6735 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6737 case RTE_ETH_FILTER_L2_TUNNEL:
6738 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6740 case RTE_ETH_FILTER_GENERIC:
6741 if (filter_op != RTE_ETH_FILTER_GET)
6743 *(const void **)arg = &ixgbe_flow_ops;
6746 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6756 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6757 u8 **mc_addr_ptr, u32 *vmdq)
6762 mc_addr = *mc_addr_ptr;
6763 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6768 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6769 struct ether_addr *mc_addr_set,
6770 uint32_t nb_mc_addr)
6772 struct ixgbe_hw *hw;
6775 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6776 mc_addr_list = (u8 *)mc_addr_set;
6777 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6778 ixgbe_dev_addr_list_itr, TRUE);
6782 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6784 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6785 uint64_t systime_cycles;
6787 switch (hw->mac.type) {
6788 case ixgbe_mac_X550:
6789 case ixgbe_mac_X550EM_x:
6790 case ixgbe_mac_X550EM_a:
6791 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6792 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6793 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6797 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6798 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6802 return systime_cycles;
6806 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6808 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6809 uint64_t rx_tstamp_cycles;
6811 switch (hw->mac.type) {
6812 case ixgbe_mac_X550:
6813 case ixgbe_mac_X550EM_x:
6814 case ixgbe_mac_X550EM_a:
6815 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6816 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6817 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6821 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6822 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6823 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6827 return rx_tstamp_cycles;
6831 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6833 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6834 uint64_t tx_tstamp_cycles;
6836 switch (hw->mac.type) {
6837 case ixgbe_mac_X550:
6838 case ixgbe_mac_X550EM_x:
6839 case ixgbe_mac_X550EM_a:
6840 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6841 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6842 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6846 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6847 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6848 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6852 return tx_tstamp_cycles;
6856 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6859 struct ixgbe_adapter *adapter =
6860 (struct ixgbe_adapter *)dev->data->dev_private;
6861 struct rte_eth_link link;
6862 uint32_t incval = 0;
6865 /* Get current link speed. */
6866 ixgbe_dev_link_update(dev, 1);
6867 rte_eth_linkstatus_get(dev, &link);
6869 switch (link.link_speed) {
6870 case ETH_SPEED_NUM_100M:
6871 incval = IXGBE_INCVAL_100;
6872 shift = IXGBE_INCVAL_SHIFT_100;
6874 case ETH_SPEED_NUM_1G:
6875 incval = IXGBE_INCVAL_1GB;
6876 shift = IXGBE_INCVAL_SHIFT_1GB;
6878 case ETH_SPEED_NUM_10G:
6880 incval = IXGBE_INCVAL_10GB;
6881 shift = IXGBE_INCVAL_SHIFT_10GB;
6885 switch (hw->mac.type) {
6886 case ixgbe_mac_X550:
6887 case ixgbe_mac_X550EM_x:
6888 case ixgbe_mac_X550EM_a:
6889 /* Independent of link speed. */
6891 /* Cycles read will be interpreted as ns. */
6894 case ixgbe_mac_X540:
6895 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6897 case ixgbe_mac_82599EB:
6898 incval >>= IXGBE_INCVAL_SHIFT_82599;
6899 shift -= IXGBE_INCVAL_SHIFT_82599;
6900 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6901 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6904 /* Not supported. */
6908 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6909 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6910 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6912 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6913 adapter->systime_tc.cc_shift = shift;
6914 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6916 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6917 adapter->rx_tstamp_tc.cc_shift = shift;
6918 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6920 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6921 adapter->tx_tstamp_tc.cc_shift = shift;
6922 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6926 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6928 struct ixgbe_adapter *adapter =
6929 (struct ixgbe_adapter *)dev->data->dev_private;
6931 adapter->systime_tc.nsec += delta;
6932 adapter->rx_tstamp_tc.nsec += delta;
6933 adapter->tx_tstamp_tc.nsec += delta;
6939 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6942 struct ixgbe_adapter *adapter =
6943 (struct ixgbe_adapter *)dev->data->dev_private;
6945 ns = rte_timespec_to_ns(ts);
6946 /* Set the timecounters to a new value. */
6947 adapter->systime_tc.nsec = ns;
6948 adapter->rx_tstamp_tc.nsec = ns;
6949 adapter->tx_tstamp_tc.nsec = ns;
6955 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6957 uint64_t ns, systime_cycles;
6958 struct ixgbe_adapter *adapter =
6959 (struct ixgbe_adapter *)dev->data->dev_private;
6961 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6962 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6963 *ts = rte_ns_to_timespec(ns);
6969 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6971 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6975 /* Stop the timesync system time. */
6976 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6977 /* Reset the timesync system time value. */
6978 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6979 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6981 /* Enable system time for platforms where it isn't on by default. */
6982 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6983 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6984 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6986 ixgbe_start_timecounters(dev);
6988 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6989 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6991 IXGBE_ETQF_FILTER_EN |
6994 /* Enable timestamping of received PTP packets. */
6995 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6996 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6997 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6999 /* Enable timestamping of transmitted PTP packets. */
7000 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7001 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7002 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7004 IXGBE_WRITE_FLUSH(hw);
7010 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7012 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7015 /* Disable timestamping of transmitted PTP packets. */
7016 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7017 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7018 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7020 /* Disable timestamping of received PTP packets. */
7021 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7022 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7023 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7025 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7026 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7028 /* Stop incrementating the System Time registers. */
7029 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7035 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7036 struct timespec *timestamp,
7037 uint32_t flags __rte_unused)
7039 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7040 struct ixgbe_adapter *adapter =
7041 (struct ixgbe_adapter *)dev->data->dev_private;
7042 uint32_t tsync_rxctl;
7043 uint64_t rx_tstamp_cycles;
7046 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7047 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7050 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7051 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7052 *timestamp = rte_ns_to_timespec(ns);
7058 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7059 struct timespec *timestamp)
7061 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7062 struct ixgbe_adapter *adapter =
7063 (struct ixgbe_adapter *)dev->data->dev_private;
7064 uint32_t tsync_txctl;
7065 uint64_t tx_tstamp_cycles;
7068 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7069 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7072 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7073 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7074 *timestamp = rte_ns_to_timespec(ns);
7080 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7082 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7085 const struct reg_info *reg_group;
7086 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7087 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7089 while ((reg_group = reg_set[g_ind++]))
7090 count += ixgbe_regs_group_count(reg_group);
7096 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7100 const struct reg_info *reg_group;
7102 while ((reg_group = ixgbevf_regs[g_ind++]))
7103 count += ixgbe_regs_group_count(reg_group);
7109 ixgbe_get_regs(struct rte_eth_dev *dev,
7110 struct rte_dev_reg_info *regs)
7112 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7113 uint32_t *data = regs->data;
7116 const struct reg_info *reg_group;
7117 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7118 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7121 regs->length = ixgbe_get_reg_length(dev);
7122 regs->width = sizeof(uint32_t);
7126 /* Support only full register dump */
7127 if ((regs->length == 0) ||
7128 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7129 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7131 while ((reg_group = reg_set[g_ind++]))
7132 count += ixgbe_read_regs_group(dev, &data[count],
7141 ixgbevf_get_regs(struct rte_eth_dev *dev,
7142 struct rte_dev_reg_info *regs)
7144 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7145 uint32_t *data = regs->data;
7148 const struct reg_info *reg_group;
7151 regs->length = ixgbevf_get_reg_length(dev);
7152 regs->width = sizeof(uint32_t);
7156 /* Support only full register dump */
7157 if ((regs->length == 0) ||
7158 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7159 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7161 while ((reg_group = ixgbevf_regs[g_ind++]))
7162 count += ixgbe_read_regs_group(dev, &data[count],
7171 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7173 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7175 /* Return unit is byte count */
7176 return hw->eeprom.word_size * 2;
7180 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7181 struct rte_dev_eeprom_info *in_eeprom)
7183 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7184 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7185 uint16_t *data = in_eeprom->data;
7188 first = in_eeprom->offset >> 1;
7189 length = in_eeprom->length >> 1;
7190 if ((first > hw->eeprom.word_size) ||
7191 ((first + length) > hw->eeprom.word_size))
7194 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7196 return eeprom->ops.read_buffer(hw, first, length, data);
7200 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7201 struct rte_dev_eeprom_info *in_eeprom)
7203 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7204 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7205 uint16_t *data = in_eeprom->data;
7208 first = in_eeprom->offset >> 1;
7209 length = in_eeprom->length >> 1;
7210 if ((first > hw->eeprom.word_size) ||
7211 ((first + length) > hw->eeprom.word_size))
7214 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7216 return eeprom->ops.write_buffer(hw, first, length, data);
7220 ixgbe_get_module_info(struct rte_eth_dev *dev,
7221 struct rte_eth_dev_module_info *modinfo)
7223 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7225 uint8_t sff8472_rev, addr_mode;
7226 bool page_swap = false;
7228 /* Check whether we support SFF-8472 or not */
7229 status = hw->phy.ops.read_i2c_eeprom(hw,
7230 IXGBE_SFF_SFF_8472_COMP,
7235 /* addressing mode is not supported */
7236 status = hw->phy.ops.read_i2c_eeprom(hw,
7237 IXGBE_SFF_SFF_8472_SWAP,
7242 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7244 "Address change required to access page 0xA2, "
7245 "but not supported. Please report the module "
7246 "type to the driver maintainers.");
7250 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7251 /* We have a SFP, but it does not support SFF-8472 */
7252 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7253 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7255 /* We have a SFP which supports a revision of SFF-8472. */
7256 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7257 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7264 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7265 struct rte_dev_eeprom_info *info)
7267 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7268 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7269 uint8_t databyte = 0xFF;
7270 uint8_t *data = info->data;
7273 if (info->length == 0)
7276 for (i = info->offset; i < info->offset + info->length; i++) {
7277 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7278 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7280 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7285 data[i - info->offset] = databyte;
7292 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7294 case ixgbe_mac_X550:
7295 case ixgbe_mac_X550EM_x:
7296 case ixgbe_mac_X550EM_a:
7297 return ETH_RSS_RETA_SIZE_512;
7298 case ixgbe_mac_X550_vf:
7299 case ixgbe_mac_X550EM_x_vf:
7300 case ixgbe_mac_X550EM_a_vf:
7301 return ETH_RSS_RETA_SIZE_64;
7303 return ETH_RSS_RETA_SIZE_128;
7308 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7310 case ixgbe_mac_X550:
7311 case ixgbe_mac_X550EM_x:
7312 case ixgbe_mac_X550EM_a:
7313 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7314 return IXGBE_RETA(reta_idx >> 2);
7316 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7317 case ixgbe_mac_X550_vf:
7318 case ixgbe_mac_X550EM_x_vf:
7319 case ixgbe_mac_X550EM_a_vf:
7320 return IXGBE_VFRETA(reta_idx >> 2);
7322 return IXGBE_RETA(reta_idx >> 2);
7327 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7329 case ixgbe_mac_X550_vf:
7330 case ixgbe_mac_X550EM_x_vf:
7331 case ixgbe_mac_X550EM_a_vf:
7332 return IXGBE_VFMRQC;
7339 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7341 case ixgbe_mac_X550_vf:
7342 case ixgbe_mac_X550EM_x_vf:
7343 case ixgbe_mac_X550EM_a_vf:
7344 return IXGBE_VFRSSRK(i);
7346 return IXGBE_RSSRK(i);
7351 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7353 case ixgbe_mac_82599_vf:
7354 case ixgbe_mac_X540_vf:
7362 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7363 struct rte_eth_dcb_info *dcb_info)
7365 struct ixgbe_dcb_config *dcb_config =
7366 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7367 struct ixgbe_dcb_tc_config *tc;
7368 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7372 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7373 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7375 dcb_info->nb_tcs = 1;
7377 tc_queue = &dcb_info->tc_queue;
7378 nb_tcs = dcb_info->nb_tcs;
7380 if (dcb_config->vt_mode) { /* vt is enabled*/
7381 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7382 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7383 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7384 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7385 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7386 for (j = 0; j < nb_tcs; j++) {
7387 tc_queue->tc_rxq[0][j].base = j;
7388 tc_queue->tc_rxq[0][j].nb_queue = 1;
7389 tc_queue->tc_txq[0][j].base = j;
7390 tc_queue->tc_txq[0][j].nb_queue = 1;
7393 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7394 for (j = 0; j < nb_tcs; j++) {
7395 tc_queue->tc_rxq[i][j].base =
7397 tc_queue->tc_rxq[i][j].nb_queue = 1;
7398 tc_queue->tc_txq[i][j].base =
7400 tc_queue->tc_txq[i][j].nb_queue = 1;
7404 } else { /* vt is disabled*/
7405 struct rte_eth_dcb_rx_conf *rx_conf =
7406 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7407 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7408 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7409 if (dcb_info->nb_tcs == ETH_4_TCS) {
7410 for (i = 0; i < dcb_info->nb_tcs; i++) {
7411 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7412 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7414 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7415 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7416 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7417 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7418 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7419 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7420 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7421 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7422 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7423 for (i = 0; i < dcb_info->nb_tcs; i++) {
7424 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7425 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7427 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7428 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7429 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7430 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7431 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7432 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7433 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7434 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7435 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7436 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7437 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7438 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7439 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7440 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7441 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7442 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7445 for (i = 0; i < dcb_info->nb_tcs; i++) {
7446 tc = &dcb_config->tc_config[i];
7447 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7452 /* Update e-tag ether type */
7454 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7455 uint16_t ether_type)
7457 uint32_t etag_etype;
7459 if (hw->mac.type != ixgbe_mac_X550 &&
7460 hw->mac.type != ixgbe_mac_X550EM_x &&
7461 hw->mac.type != ixgbe_mac_X550EM_a) {
7465 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7466 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7467 etag_etype |= ether_type;
7468 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7469 IXGBE_WRITE_FLUSH(hw);
7474 /* Config l2 tunnel ether type */
7476 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7477 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7480 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7481 struct ixgbe_l2_tn_info *l2_tn_info =
7482 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7484 if (l2_tunnel == NULL)
7487 switch (l2_tunnel->l2_tunnel_type) {
7488 case RTE_L2_TUNNEL_TYPE_E_TAG:
7489 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7490 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7493 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7501 /* Enable e-tag tunnel */
7503 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7505 uint32_t etag_etype;
7507 if (hw->mac.type != ixgbe_mac_X550 &&
7508 hw->mac.type != ixgbe_mac_X550EM_x &&
7509 hw->mac.type != ixgbe_mac_X550EM_a) {
7513 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7514 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7515 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7516 IXGBE_WRITE_FLUSH(hw);
7521 /* Enable l2 tunnel */
7523 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7524 enum rte_eth_tunnel_type l2_tunnel_type)
7527 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7528 struct ixgbe_l2_tn_info *l2_tn_info =
7529 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7531 switch (l2_tunnel_type) {
7532 case RTE_L2_TUNNEL_TYPE_E_TAG:
7533 l2_tn_info->e_tag_en = TRUE;
7534 ret = ixgbe_e_tag_enable(hw);
7537 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7545 /* Disable e-tag tunnel */
7547 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7549 uint32_t etag_etype;
7551 if (hw->mac.type != ixgbe_mac_X550 &&
7552 hw->mac.type != ixgbe_mac_X550EM_x &&
7553 hw->mac.type != ixgbe_mac_X550EM_a) {
7557 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7558 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7559 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7560 IXGBE_WRITE_FLUSH(hw);
7565 /* Disable l2 tunnel */
7567 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7568 enum rte_eth_tunnel_type l2_tunnel_type)
7571 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7572 struct ixgbe_l2_tn_info *l2_tn_info =
7573 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7575 switch (l2_tunnel_type) {
7576 case RTE_L2_TUNNEL_TYPE_E_TAG:
7577 l2_tn_info->e_tag_en = FALSE;
7578 ret = ixgbe_e_tag_disable(hw);
7581 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7590 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7591 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7594 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7595 uint32_t i, rar_entries;
7596 uint32_t rar_low, rar_high;
7598 if (hw->mac.type != ixgbe_mac_X550 &&
7599 hw->mac.type != ixgbe_mac_X550EM_x &&
7600 hw->mac.type != ixgbe_mac_X550EM_a) {
7604 rar_entries = ixgbe_get_num_rx_addrs(hw);
7606 for (i = 1; i < rar_entries; i++) {
7607 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7608 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7609 if ((rar_high & IXGBE_RAH_AV) &&
7610 (rar_high & IXGBE_RAH_ADTYPE) &&
7611 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7612 l2_tunnel->tunnel_id)) {
7613 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7614 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7616 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7626 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7627 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7630 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7631 uint32_t i, rar_entries;
7632 uint32_t rar_low, rar_high;
7634 if (hw->mac.type != ixgbe_mac_X550 &&
7635 hw->mac.type != ixgbe_mac_X550EM_x &&
7636 hw->mac.type != ixgbe_mac_X550EM_a) {
7640 /* One entry for one tunnel. Try to remove potential existing entry. */
7641 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7643 rar_entries = ixgbe_get_num_rx_addrs(hw);
7645 for (i = 1; i < rar_entries; i++) {
7646 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7647 if (rar_high & IXGBE_RAH_AV) {
7650 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7651 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7652 rar_low = l2_tunnel->tunnel_id;
7654 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7655 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7661 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7662 " Please remove a rule before adding a new one.");
7666 static inline struct ixgbe_l2_tn_filter *
7667 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7668 struct ixgbe_l2_tn_key *key)
7672 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7676 return l2_tn_info->hash_map[ret];
7680 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7681 struct ixgbe_l2_tn_filter *l2_tn_filter)
7685 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7686 &l2_tn_filter->key);
7690 "Failed to insert L2 tunnel filter"
7691 " to hash table %d!",
7696 l2_tn_info->hash_map[ret] = l2_tn_filter;
7698 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7704 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7705 struct ixgbe_l2_tn_key *key)
7708 struct ixgbe_l2_tn_filter *l2_tn_filter;
7710 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7714 "No such L2 tunnel filter to delete %d!",
7719 l2_tn_filter = l2_tn_info->hash_map[ret];
7720 l2_tn_info->hash_map[ret] = NULL;
7722 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7723 rte_free(l2_tn_filter);
7728 /* Add l2 tunnel filter */
7730 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7731 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7735 struct ixgbe_l2_tn_info *l2_tn_info =
7736 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7737 struct ixgbe_l2_tn_key key;
7738 struct ixgbe_l2_tn_filter *node;
7741 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7742 key.tn_id = l2_tunnel->tunnel_id;
7744 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7748 "The L2 tunnel filter already exists!");
7752 node = rte_zmalloc("ixgbe_l2_tn",
7753 sizeof(struct ixgbe_l2_tn_filter),
7758 rte_memcpy(&node->key,
7760 sizeof(struct ixgbe_l2_tn_key));
7761 node->pool = l2_tunnel->pool;
7762 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7769 switch (l2_tunnel->l2_tunnel_type) {
7770 case RTE_L2_TUNNEL_TYPE_E_TAG:
7771 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7774 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7779 if ((!restore) && (ret < 0))
7780 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7785 /* Delete l2 tunnel filter */
7787 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7788 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7791 struct ixgbe_l2_tn_info *l2_tn_info =
7792 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7793 struct ixgbe_l2_tn_key key;
7795 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7796 key.tn_id = l2_tunnel->tunnel_id;
7797 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7801 switch (l2_tunnel->l2_tunnel_type) {
7802 case RTE_L2_TUNNEL_TYPE_E_TAG:
7803 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7806 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7815 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7816 * @dev: pointer to rte_eth_dev structure
7817 * @filter_op:operation will be taken.
7818 * @arg: a pointer to specific structure corresponding to the filter_op
7821 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7822 enum rte_filter_op filter_op,
7827 if (filter_op == RTE_ETH_FILTER_NOP)
7831 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7836 switch (filter_op) {
7837 case RTE_ETH_FILTER_ADD:
7838 ret = ixgbe_dev_l2_tunnel_filter_add
7840 (struct rte_eth_l2_tunnel_conf *)arg,
7843 case RTE_ETH_FILTER_DELETE:
7844 ret = ixgbe_dev_l2_tunnel_filter_del
7846 (struct rte_eth_l2_tunnel_conf *)arg);
7849 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7857 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7861 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7863 if (hw->mac.type != ixgbe_mac_X550 &&
7864 hw->mac.type != ixgbe_mac_X550EM_x &&
7865 hw->mac.type != ixgbe_mac_X550EM_a) {
7869 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7870 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7872 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7873 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7878 /* Enable l2 tunnel forwarding */
7880 ixgbe_dev_l2_tunnel_forwarding_enable
7881 (struct rte_eth_dev *dev,
7882 enum rte_eth_tunnel_type l2_tunnel_type)
7884 struct ixgbe_l2_tn_info *l2_tn_info =
7885 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7888 switch (l2_tunnel_type) {
7889 case RTE_L2_TUNNEL_TYPE_E_TAG:
7890 l2_tn_info->e_tag_fwd_en = TRUE;
7891 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7894 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7902 /* Disable l2 tunnel forwarding */
7904 ixgbe_dev_l2_tunnel_forwarding_disable
7905 (struct rte_eth_dev *dev,
7906 enum rte_eth_tunnel_type l2_tunnel_type)
7908 struct ixgbe_l2_tn_info *l2_tn_info =
7909 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7912 switch (l2_tunnel_type) {
7913 case RTE_L2_TUNNEL_TYPE_E_TAG:
7914 l2_tn_info->e_tag_fwd_en = FALSE;
7915 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7918 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7927 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7928 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7931 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7933 uint32_t vmtir, vmvir;
7934 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7936 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7938 "VF id %u should be less than %u",
7944 if (hw->mac.type != ixgbe_mac_X550 &&
7945 hw->mac.type != ixgbe_mac_X550EM_x &&
7946 hw->mac.type != ixgbe_mac_X550EM_a) {
7951 vmtir = l2_tunnel->tunnel_id;
7955 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7957 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7958 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7960 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7961 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7966 /* Enable l2 tunnel tag insertion */
7968 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7969 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7973 switch (l2_tunnel->l2_tunnel_type) {
7974 case RTE_L2_TUNNEL_TYPE_E_TAG:
7975 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7978 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7986 /* Disable l2 tunnel tag insertion */
7988 ixgbe_dev_l2_tunnel_insertion_disable
7989 (struct rte_eth_dev *dev,
7990 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7994 switch (l2_tunnel->l2_tunnel_type) {
7995 case RTE_L2_TUNNEL_TYPE_E_TAG:
7996 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7999 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8008 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8013 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8015 if (hw->mac.type != ixgbe_mac_X550 &&
8016 hw->mac.type != ixgbe_mac_X550EM_x &&
8017 hw->mac.type != ixgbe_mac_X550EM_a) {
8021 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8023 qde |= IXGBE_QDE_STRIP_TAG;
8025 qde &= ~IXGBE_QDE_STRIP_TAG;
8026 qde &= ~IXGBE_QDE_READ;
8027 qde |= IXGBE_QDE_WRITE;
8028 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8033 /* Enable l2 tunnel tag stripping */
8035 ixgbe_dev_l2_tunnel_stripping_enable
8036 (struct rte_eth_dev *dev,
8037 enum rte_eth_tunnel_type l2_tunnel_type)
8041 switch (l2_tunnel_type) {
8042 case RTE_L2_TUNNEL_TYPE_E_TAG:
8043 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8046 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8054 /* Disable l2 tunnel tag stripping */
8056 ixgbe_dev_l2_tunnel_stripping_disable
8057 (struct rte_eth_dev *dev,
8058 enum rte_eth_tunnel_type l2_tunnel_type)
8062 switch (l2_tunnel_type) {
8063 case RTE_L2_TUNNEL_TYPE_E_TAG:
8064 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8067 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8075 /* Enable/disable l2 tunnel offload functions */
8077 ixgbe_dev_l2_tunnel_offload_set
8078 (struct rte_eth_dev *dev,
8079 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8085 if (l2_tunnel == NULL)
8089 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8091 ret = ixgbe_dev_l2_tunnel_enable(
8093 l2_tunnel->l2_tunnel_type);
8095 ret = ixgbe_dev_l2_tunnel_disable(
8097 l2_tunnel->l2_tunnel_type);
8100 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8102 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8106 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8111 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8113 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8115 l2_tunnel->l2_tunnel_type);
8117 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8119 l2_tunnel->l2_tunnel_type);
8122 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8124 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8126 l2_tunnel->l2_tunnel_type);
8128 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8130 l2_tunnel->l2_tunnel_type);
8137 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8140 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8141 IXGBE_WRITE_FLUSH(hw);
8146 /* There's only one register for VxLAN UDP port.
8147 * So, we cannot add several ports. Will update it.
8150 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8154 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8158 return ixgbe_update_vxlan_port(hw, port);
8161 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8162 * UDP port, it must have a value.
8163 * So, will reset it to the original value 0.
8166 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8171 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8173 if (cur_port != port) {
8174 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8178 return ixgbe_update_vxlan_port(hw, 0);
8181 /* Add UDP tunneling port */
8183 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8184 struct rte_eth_udp_tunnel *udp_tunnel)
8187 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8189 if (hw->mac.type != ixgbe_mac_X550 &&
8190 hw->mac.type != ixgbe_mac_X550EM_x &&
8191 hw->mac.type != ixgbe_mac_X550EM_a) {
8195 if (udp_tunnel == NULL)
8198 switch (udp_tunnel->prot_type) {
8199 case RTE_TUNNEL_TYPE_VXLAN:
8200 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8203 case RTE_TUNNEL_TYPE_GENEVE:
8204 case RTE_TUNNEL_TYPE_TEREDO:
8205 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8210 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8218 /* Remove UDP tunneling port */
8220 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8221 struct rte_eth_udp_tunnel *udp_tunnel)
8224 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8226 if (hw->mac.type != ixgbe_mac_X550 &&
8227 hw->mac.type != ixgbe_mac_X550EM_x &&
8228 hw->mac.type != ixgbe_mac_X550EM_a) {
8232 if (udp_tunnel == NULL)
8235 switch (udp_tunnel->prot_type) {
8236 case RTE_TUNNEL_TYPE_VXLAN:
8237 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8239 case RTE_TUNNEL_TYPE_GENEVE:
8240 case RTE_TUNNEL_TYPE_TEREDO:
8241 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8245 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8254 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8256 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8258 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8262 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8264 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8266 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8269 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8271 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8274 /* peek the message first */
8275 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8277 /* PF reset VF event */
8278 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8279 /* dummy mbx read to ack pf */
8280 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8282 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8288 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8291 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8292 struct ixgbe_interrupt *intr =
8293 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8294 ixgbevf_intr_disable(dev);
8296 /* read-on-clear nic registers here */
8297 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8300 /* only one misc vector supported - mailbox */
8301 eicr &= IXGBE_VTEICR_MASK;
8302 if (eicr == IXGBE_MISC_VEC_ID)
8303 intr->flags |= IXGBE_FLAG_MAILBOX;
8309 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8311 struct ixgbe_interrupt *intr =
8312 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8314 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8315 ixgbevf_mbx_process(dev);
8316 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8319 ixgbevf_intr_enable(dev);
8325 ixgbevf_dev_interrupt_handler(void *param)
8327 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8329 ixgbevf_dev_interrupt_get_status(dev);
8330 ixgbevf_dev_interrupt_action(dev);
8334 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8335 * @hw: pointer to hardware structure
8337 * Stops the transmit data path and waits for the HW to internally empty
8338 * the Tx security block
8340 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8342 #define IXGBE_MAX_SECTX_POLL 40
8347 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8348 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8349 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8350 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8351 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8352 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8354 /* Use interrupt-safe sleep just in case */
8358 /* For informational purposes only */
8359 if (i >= IXGBE_MAX_SECTX_POLL)
8360 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8361 "path fully disabled. Continuing with init.");
8363 return IXGBE_SUCCESS;
8367 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8368 * @hw: pointer to hardware structure
8370 * Enables the transmit data path.
8372 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8376 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8377 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8378 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8379 IXGBE_WRITE_FLUSH(hw);
8381 return IXGBE_SUCCESS;
8384 /* restore n-tuple filter */
8386 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8388 struct ixgbe_filter_info *filter_info =
8389 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8390 struct ixgbe_5tuple_filter *node;
8392 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8393 ixgbe_inject_5tuple_filter(dev, node);
8397 /* restore ethernet type filter */
8399 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8401 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8402 struct ixgbe_filter_info *filter_info =
8403 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8406 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8407 if (filter_info->ethertype_mask & (1 << i)) {
8408 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8409 filter_info->ethertype_filters[i].etqf);
8410 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8411 filter_info->ethertype_filters[i].etqs);
8412 IXGBE_WRITE_FLUSH(hw);
8417 /* restore SYN filter */
8419 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8421 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8422 struct ixgbe_filter_info *filter_info =
8423 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8426 synqf = filter_info->syn_info;
8428 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8429 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8430 IXGBE_WRITE_FLUSH(hw);
8434 /* restore L2 tunnel filter */
8436 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8438 struct ixgbe_l2_tn_info *l2_tn_info =
8439 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8440 struct ixgbe_l2_tn_filter *node;
8441 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8443 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8444 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8445 l2_tn_conf.tunnel_id = node->key.tn_id;
8446 l2_tn_conf.pool = node->pool;
8447 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8451 /* restore rss filter */
8453 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8455 struct ixgbe_filter_info *filter_info =
8456 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8458 if (filter_info->rss_info.conf.queue_num)
8459 ixgbe_config_rss_filter(dev,
8460 &filter_info->rss_info, TRUE);
8464 ixgbe_filter_restore(struct rte_eth_dev *dev)
8466 ixgbe_ntuple_filter_restore(dev);
8467 ixgbe_ethertype_filter_restore(dev);
8468 ixgbe_syn_filter_restore(dev);
8469 ixgbe_fdir_filter_restore(dev);
8470 ixgbe_l2_tn_filter_restore(dev);
8471 ixgbe_rss_filter_restore(dev);
8477 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8479 struct ixgbe_l2_tn_info *l2_tn_info =
8480 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8481 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8483 if (l2_tn_info->e_tag_en)
8484 (void)ixgbe_e_tag_enable(hw);
8486 if (l2_tn_info->e_tag_fwd_en)
8487 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8489 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8492 /* remove all the n-tuple filters */
8494 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8496 struct ixgbe_filter_info *filter_info =
8497 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8498 struct ixgbe_5tuple_filter *p_5tuple;
8500 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8501 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8504 /* remove all the ether type filters */
8506 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8508 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8509 struct ixgbe_filter_info *filter_info =
8510 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8513 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8514 if (filter_info->ethertype_mask & (1 << i) &&
8515 !filter_info->ethertype_filters[i].conf) {
8516 (void)ixgbe_ethertype_filter_remove(filter_info,
8518 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8519 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8520 IXGBE_WRITE_FLUSH(hw);
8525 /* remove the SYN filter */
8527 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8529 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8530 struct ixgbe_filter_info *filter_info =
8531 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8533 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8534 filter_info->syn_info = 0;
8536 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8537 IXGBE_WRITE_FLUSH(hw);
8541 /* remove all the L2 tunnel filters */
8543 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8545 struct ixgbe_l2_tn_info *l2_tn_info =
8546 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8547 struct ixgbe_l2_tn_filter *l2_tn_filter;
8548 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8551 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8552 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8553 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8554 l2_tn_conf.pool = l2_tn_filter->pool;
8555 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8563 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8564 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8565 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8566 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8567 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8568 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8570 RTE_INIT(ixgbe_init_log);
8572 ixgbe_init_log(void)
8574 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8575 if (ixgbe_logtype_init >= 0)
8576 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8577 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8578 if (ixgbe_logtype_driver >= 0)
8579 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);