drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 183                                              uint16_t queue_id,
 184                                              uint8_t stat_idx,
 185                                              uint8_t is_rx);
 186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 187                                struct rte_eth_dev_info *dev_info);
 188 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 190                                  struct rte_eth_dev_info *dev_info);
 191 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 192
 193 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 194                 uint16_t vlan_id, int on);
 195 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 196                                enum rte_vlan_type vlan_type,
 197                                uint16_t tpid_id);
 198 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 199                 uint16_t queue, bool on);
 200 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 201                 int on);
 202 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 203 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 204 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 205 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 206 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 207
 208 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 209 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 210 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 211                                struct rte_eth_fc_conf *fc_conf);
 212 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_pfc_conf *pfc_conf);
 216 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 217                         struct rte_eth_rss_reta_entry64 *reta_conf,
 218                         uint16_t reta_size);
 219 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 220                         struct rte_eth_rss_reta_entry64 *reta_conf,
 221                         uint16_t reta_size);
 222 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 226 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 227 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 228                 void *param);
 229 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 230 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 231                 uint32_t index, uint32_t pool);
 232 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 233 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 234                                            struct ether_addr *mac_addr);
 235 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 236
 237 /* For Virtual Function support */
 238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 240 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 241 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 246 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr* mac_addr,uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 269 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 270                 uint16_t rx_mask, uint8_t on);
 271 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 272 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 273 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 274                 uint64_t pool_mask,uint8_t vlan_on);
 275 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 276                 struct rte_eth_mirror_conf *mirror_conf,
 277                 uint8_t rule_id, uint8_t on);
 278 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 279                 uint8_t rule_id);
 280 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 281                                           uint16_t queue_id);
 282 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 283                                            uint16_t queue_id);
 284 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 285                                uint8_t queue, uint8_t msix_vector);
 286 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 287
 288 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 289                 uint16_t queue_idx, uint16_t tx_rate);
 290 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 291                 uint16_t tx_rate, uint64_t q_msk);
 292
 293 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 294                                  struct ether_addr *mac_addr,
 295                                  uint32_t index, uint32_t pool);
 296 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 297 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 298                                              struct ether_addr *mac_addr);
 299 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 300                         struct rte_eth_syn_filter *filter,
 301                         bool add);
 302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 303                         struct rte_eth_syn_filter *filter);
 304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 305                         enum rte_filter_op filter_op,
 306                         void *arg);
 307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 308                         struct ixgbe_5tuple_filter *filter);
 309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 310                         struct ixgbe_5tuple_filter *filter);
 311 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 312                         struct rte_eth_ntuple_filter *filter,
 313                         bool add);
 314 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 315                                 enum rte_filter_op filter_op,
 316                                 void *arg);
 317 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 318                         struct rte_eth_ntuple_filter *filter);
 319 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ethertype_filter *filter,
 321                         bool add);
 322 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ethertype_filter *filter);
 327 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 328                      enum rte_filter_type filter_type,
 329                      enum rte_filter_op filter_op,
 330                      void *arg);
 331 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 332
 333 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 334                                       struct ether_addr *mc_addr_set,
 335                                       uint32_t nb_mc_addr);
 336 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 337                                    struct rte_eth_dcb_info *dcb_info);
 338
 339 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 340 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 341                             struct rte_dev_reg_info *regs);
 342 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 343 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 344                                 struct rte_dev_eeprom_info *eeprom);
 345 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 346                                 struct rte_dev_eeprom_info *eeprom);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364
 365 static int ixgbe_dev_l2_tunnel_eth_type_conf
 366         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 367 static int ixgbe_dev_l2_tunnel_offload_set
 368         (struct rte_eth_dev *dev,
 369          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 370          uint32_t mask,
 371          uint8_t en);
 372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 373                                              enum rte_filter_op filter_op,
 374                                              void *arg);
 375
 376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 377                                          struct rte_eth_udp_tunnel *udp_tunnel);
 378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 379                                          struct rte_eth_udp_tunnel *udp_tunnel);
 380
 381 /*
 382  * Define VF Stats MACRO for Non "cleared on read" register
 383  */
 384 #define UPDATE_VF_STAT(reg, last, cur)                          \
 385 {                                                               \
 386         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 387         cur += (latest - last) & UINT_MAX;                      \
 388         last = latest;                                          \
 389 }
 390
 391 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 392 {                                                                \
 393         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 394         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 395         u64 latest = ((new_msb << 32) | new_lsb);                \
 396         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 397         last = latest;                                           \
 398 }
 399
 400 #define IXGBE_SET_HWSTRIP(h, q) do{\
 401                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 403                 (h)->bitmap[idx] |= 1 << bit;\
 404         } while (0)
 405
 406 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 407                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 408                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 409                 (h)->bitmap[idx] &= ~(1 << bit);\
 410         } while (0)
 411
 412 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 413                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 414                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 415                 (r) = (h)->bitmap[idx] >> bit & 1;\
 416         } while (0)
 417
 418 /*
 419  * The set of PCI devices this driver supports
 420  */
 421 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 422
 423 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 424 #include "rte_pci_dev_ids.h"
 425
 426 { .vendor_id = 0, /* sentinel */ },
 427 };
 428
 429
 430 /*
 431  * The set of PCI devices this driver supports (for 82599 VF)
 432  */
 433 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 434
 435 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 436 #include "rte_pci_dev_ids.h"
 437 { .vendor_id = 0, /* sentinel */ },
 438
 439 };
 440
 441 static const struct rte_eth_desc_lim rx_desc_lim = {
 442         .nb_max = IXGBE_MAX_RING_DESC,
 443         .nb_min = IXGBE_MIN_RING_DESC,
 444         .nb_align = IXGBE_RXD_ALIGN,
 445 };
 446
 447 static const struct rte_eth_desc_lim tx_desc_lim = {
 448         .nb_max = IXGBE_MAX_RING_DESC,
 449         .nb_min = IXGBE_MIN_RING_DESC,
 450         .nb_align = IXGBE_TXD_ALIGN,
 451 };
 452
 453 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 454         .dev_configure        = ixgbe_dev_configure,
 455         .dev_start            = ixgbe_dev_start,
 456         .dev_stop             = ixgbe_dev_stop,
 457         .dev_set_link_up    = ixgbe_dev_set_link_up,
 458         .dev_set_link_down  = ixgbe_dev_set_link_down,
 459         .dev_close            = ixgbe_dev_close,
 460         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 461         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 462         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 463         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 464         .link_update          = ixgbe_dev_link_update,
 465         .stats_get            = ixgbe_dev_stats_get,
 466         .xstats_get           = ixgbe_dev_xstats_get,
 467         .stats_reset          = ixgbe_dev_stats_reset,
 468         .xstats_reset         = ixgbe_dev_xstats_reset,
 469         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 470         .dev_infos_get        = ixgbe_dev_info_get,
 471         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 472         .mtu_set              = ixgbe_dev_mtu_set,
 473         .vlan_filter_set      = ixgbe_vlan_filter_set,
 474         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 475         .vlan_offload_set     = ixgbe_vlan_offload_set,
 476         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 477         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 478         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 479         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 480         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 481         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 482         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 483         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 484         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 485         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 486         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 487         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 488         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 489         .dev_led_on           = ixgbe_dev_led_on,
 490         .dev_led_off          = ixgbe_dev_led_off,
 491         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 492         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 493         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 494         .mac_addr_add         = ixgbe_add_rar,
 495         .mac_addr_remove      = ixgbe_remove_rar,
 496         .mac_addr_set         = ixgbe_set_default_mac_addr,
 497         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 498         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 499         .mirror_rule_set      = ixgbe_mirror_rule_set,
 500         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 501         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 502         .set_vf_rx            = ixgbe_set_pool_rx,
 503         .set_vf_tx            = ixgbe_set_pool_tx,
 504         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 505         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 506         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 507         .reta_update          = ixgbe_dev_rss_reta_update,
 508         .reta_query           = ixgbe_dev_rss_reta_query,
 509 #ifdef RTE_NIC_BYPASS
 510         .bypass_init          = ixgbe_bypass_init,
 511         .bypass_state_set     = ixgbe_bypass_state_store,
 512         .bypass_state_show    = ixgbe_bypass_state_show,
 513         .bypass_event_set     = ixgbe_bypass_event_store,
 514         .bypass_event_show    = ixgbe_bypass_event_show,
 515         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 516         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 517         .bypass_ver_show      = ixgbe_bypass_ver_show,
 518         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 519 #endif /* RTE_NIC_BYPASS */
 520         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 521         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 522         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 523         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 524         .rxq_info_get         = ixgbe_rxq_info_get,
 525         .txq_info_get         = ixgbe_txq_info_get,
 526         .timesync_enable      = ixgbe_timesync_enable,
 527         .timesync_disable     = ixgbe_timesync_disable,
 528         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 529         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 530         .get_reg_length       = ixgbe_get_reg_length,
 531         .get_reg              = ixgbe_get_regs,
 532         .get_eeprom_length    = ixgbe_get_eeprom_length,
 533         .get_eeprom           = ixgbe_get_eeprom,
 534         .set_eeprom           = ixgbe_set_eeprom,
 535         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 536         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 537         .timesync_read_time   = ixgbe_timesync_read_time,
 538         .timesync_write_time  = ixgbe_timesync_write_time,
 539         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 540         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 541         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 542         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 543 };
 544
 545 /*
 546  * dev_ops for virtual function, bare necessities for basic vf
 547  * operation have been implemented
 548  */
 549 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 550         .dev_configure        = ixgbevf_dev_configure,
 551         .dev_start            = ixgbevf_dev_start,
 552         .dev_stop             = ixgbevf_dev_stop,
 553         .link_update          = ixgbe_dev_link_update,
 554         .stats_get            = ixgbevf_dev_stats_get,
 555         .xstats_get           = ixgbevf_dev_xstats_get,
 556         .stats_reset          = ixgbevf_dev_stats_reset,
 557         .xstats_reset         = ixgbevf_dev_stats_reset,
 558         .dev_close            = ixgbevf_dev_close,
 559         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 560         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 561         .dev_infos_get        = ixgbevf_dev_info_get,
 562         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 563         .mtu_set              = ixgbevf_dev_set_mtu,
 564         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 565         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 566         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 567         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 568         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 569         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 570         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 571         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 572         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 573         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 574         .mac_addr_add         = ixgbevf_add_mac_addr,
 575         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 576         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 577         .rxq_info_get         = ixgbe_rxq_info_get,
 578         .txq_info_get         = ixgbe_txq_info_get,
 579         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 580         .get_reg_length       = ixgbevf_get_reg_length,
 581         .get_reg              = ixgbevf_get_regs,
 582         .reta_update          = ixgbe_dev_rss_reta_update,
 583         .reta_query           = ixgbe_dev_rss_reta_query,
 584         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 585         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 586 };
 587
 588 /* store statistics names and its offset in stats structure */
 589 struct rte_ixgbe_xstats_name_off {
 590         char name[RTE_ETH_XSTATS_NAME_SIZE];
 591         unsigned offset;
 592 };
 593
 594 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 595         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 596         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 597         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 598         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 599         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 600         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 601         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 602         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 603         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 604         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 605         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 606         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 607         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 608         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 609         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 610                 prc1023)},
 611         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 612                 prc1522)},
 613         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 614         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 615         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 616         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 617         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 618         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 619         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 620         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 621         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 622         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 623         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 624         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 625         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 626         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 627         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 628         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 629         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 630                 ptc1023)},
 631         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 632                 ptc1522)},
 633         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 634         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 635         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 636         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 637
 638         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 639                 fdirustat_add)},
 640         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 641                 fdirustat_remove)},
 642         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 643                 fdirfstat_fadd)},
 644         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 645                 fdirfstat_fremove)},
 646         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 647                 fdirmatch)},
 648         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 649                 fdirmiss)},
 650
 651         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 652         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 653         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 654                 fclast)},
 655         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 656         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 657         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 658         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 659         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 660                 fcoe_noddp)},
 661         {"rx_fcoe_no_direct_data_placement_ext_buff",
 662                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 663
 664         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 665                 lxontxc)},
 666         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 667                 lxonrxc)},
 668         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 669                 lxofftxc)},
 670         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 671                 lxoffrxc)},
 672         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 673 };
 674
 675 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 676                            sizeof(rte_ixgbe_stats_strings[0]))
 677
 678 /* Per-queue statistics */
 679 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 680         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 681         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 682         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 683         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 684 };
 685
 686 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 687                            sizeof(rte_ixgbe_rxq_strings[0]))
 688
 689 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 690         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 691         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 692         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 693                 pxon2offc)},
 694 };
 695
 696 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 697                            sizeof(rte_ixgbe_txq_strings[0]))
 698
 699 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 700         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 701 };
 702
 703 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 704                 sizeof(rte_ixgbevf_stats_strings[0]))
 705
 706 /**
 707  * Atomically reads the link status information from global
 708  * structure rte_eth_dev.
 709  *
 710  * @param dev
 711  *   - Pointer to the structure rte_eth_dev to read from.
 712  *   - Pointer to the buffer to be saved with the link status.
 713  *
 714  * @return
 715  *   - On success, zero.
 716  *   - On failure, negative value.
 717  */
 718 static inline int
 719 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 720                                 struct rte_eth_link *link)
 721 {
 722         struct rte_eth_link *dst = link;
 723         struct rte_eth_link *src = &(dev->data->dev_link);
 724
 725         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 726                                         *(uint64_t *)src) == 0)
 727                 return -1;
 728
 729         return 0;
 730 }
 731
 732 /**
 733  * Atomically writes the link status information into global
 734  * structure rte_eth_dev.
 735  *
 736  * @param dev
 737  *   - Pointer to the structure rte_eth_dev to read from.
 738  *   - Pointer to the buffer to be saved with the link status.
 739  *
 740  * @return
 741  *   - On success, zero.
 742  *   - On failure, negative value.
 743  */
 744 static inline int
 745 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 746                                 struct rte_eth_link *link)
 747 {
 748         struct rte_eth_link *dst = &(dev->data->dev_link);
 749         struct rte_eth_link *src = link;
 750
 751         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 752                                         *(uint64_t *)src) == 0)
 753                 return -1;
 754
 755         return 0;
 756 }
 757
 758 /*
 759  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 760  */
 761 static inline int
 762 ixgbe_is_sfp(struct ixgbe_hw *hw)
 763 {
 764         switch (hw->phy.type) {
 765         case ixgbe_phy_sfp_avago:
 766         case ixgbe_phy_sfp_ftl:
 767         case ixgbe_phy_sfp_intel:
 768         case ixgbe_phy_sfp_unknown:
 769         case ixgbe_phy_sfp_passive_tyco:
 770         case ixgbe_phy_sfp_passive_unknown:
 771                 return 1;
 772         default:
 773                 return 0;
 774         }
 775 }
 776
 777 static inline int32_t
 778 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 779 {
 780         uint32_t ctrl_ext;
 781         int32_t status;
 782
 783         status = ixgbe_reset_hw(hw);
 784
 785         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 786         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 787         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 788         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 789         IXGBE_WRITE_FLUSH(hw);
 790
 791         return status;
 792 }
 793
 794 static inline void
 795 ixgbe_enable_intr(struct rte_eth_dev *dev)
 796 {
 797         struct ixgbe_interrupt *intr =
 798                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 799         struct ixgbe_hw *hw =
 800                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 801
 802         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 803         IXGBE_WRITE_FLUSH(hw);
 804 }
 805
 806 /*
 807  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 808  */
 809 static void
 810 ixgbe_disable_intr(struct ixgbe_hw *hw)
 811 {
 812         PMD_INIT_FUNC_TRACE();
 813
 814         if (hw->mac.type == ixgbe_mac_82598EB) {
 815                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 816         } else {
 817                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 818                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 819                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 820         }
 821         IXGBE_WRITE_FLUSH(hw);
 822 }
 823
 824 /*
 825  * This function resets queue statistics mapping registers.
 826  * From Niantic datasheet, Initialization of Statistics section:
 827  * "...if software requires the queue counters, the RQSMR and TQSM registers
 828  * must be re-programmed following a device reset.
 829  */
 830 static void
 831 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 832 {
 833         uint32_t i;
 834
 835         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 836                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 837                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 838         }
 839 }
 840
 841
 842 static int
 843 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 844                                   uint16_t queue_id,
 845                                   uint8_t stat_idx,
 846                                   uint8_t is_rx)
 847 {
 848 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 849 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 850 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 851
 852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 853         struct ixgbe_stat_mapping_registers *stat_mappings =
 854                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 855         uint32_t qsmr_mask = 0;
 856         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 857         uint32_t q_map;
 858         uint8_t n, offset;
 859
 860         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 861                 (hw->mac.type != ixgbe_mac_X540) &&
 862                 (hw->mac.type != ixgbe_mac_X550) &&
 863                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 864                 (hw->mac.type != ixgbe_mac_X550EM_a))
 865                 return -ENOSYS;
 866
 867         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 868                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 869                      queue_id, stat_idx);
 870
 871         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 872         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 873                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 874                 return -EIO;
 875         }
 876         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 877
 878         /* Now clear any previous stat_idx set */
 879         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 880         if (!is_rx)
 881                 stat_mappings->tqsm[n] &= ~clearing_mask;
 882         else
 883                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 884
 885         q_map = (uint32_t)stat_idx;
 886         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 887         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 888         if (!is_rx)
 889                 stat_mappings->tqsm[n] |= qsmr_mask;
 890         else
 891                 stat_mappings->rqsmr[n] |= qsmr_mask;
 892
 893         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 894                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 895                      queue_id, stat_idx);
 896         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 897                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 898
 899         /* Now write the mapping in the appropriate register */
 900         if (is_rx) {
 901                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 902                              stat_mappings->rqsmr[n], n);
 903                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 904         }
 905         else {
 906                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 907                              stat_mappings->tqsm[n], n);
 908                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 909         }
 910         return 0;
 911 }
 912
 913 static void
 914 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 915 {
 916         struct ixgbe_stat_mapping_registers *stat_mappings =
 917                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 919         int i;
 920
 921         /* write whatever was in stat mapping table to the NIC */
 922         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 923                 /* rx */
 924                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 925
 926                 /* tx */
 927                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 928         }
 929 }
 930
 931 static void
 932 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 933 {
 934         uint8_t i;
 935         struct ixgbe_dcb_tc_config *tc;
 936         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 937
 938         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 939         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 940         for (i = 0; i < dcb_max_tc; i++) {
 941                 tc = &dcb_config->tc_config[i];
 942                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 943                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 944                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 945                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 946                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 947                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 948                 tc->pfc = ixgbe_dcb_pfc_disabled;
 949         }
 950
 951         /* Initialize default user to priority mapping, UPx->TC0 */
 952         tc = &dcb_config->tc_config[0];
 953         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 954         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 955         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 956                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 957                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 958         }
 959         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 960         dcb_config->pfc_mode_enable = false;
 961         dcb_config->vt_mode = true;
 962         dcb_config->round_robin_enable = false;
 963         /* support all DCB capabilities in 82599 */
 964         dcb_config->support.capabilities = 0xFF;
 965
 966         /*we only support 4 Tcs for X540, X550 */
 967         if (hw->mac.type == ixgbe_mac_X540 ||
 968                 hw->mac.type == ixgbe_mac_X550 ||
 969                 hw->mac.type == ixgbe_mac_X550EM_x ||
 970                 hw->mac.type == ixgbe_mac_X550EM_a) {
 971                 dcb_config->num_tcs.pg_tcs = 4;
 972                 dcb_config->num_tcs.pfc_tcs = 4;
 973         }
 974 }
 975
 976 /*
 977  * Ensure that all locks are released before first NVM or PHY access
 978  */
 979 static void
 980 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 981 {
 982         uint16_t mask;
 983
 984         /*
 985          * Phy lock should not fail in this early stage. If this is the case,
 986          * it is due to an improper exit of the application.
 987          * So force the release of the faulty lock. Release of common lock
 988          * is done automatically by swfw_sync function.
 989          */
 990         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 991         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 992                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 993         }
 994         ixgbe_release_swfw_semaphore(hw, mask);
 995
 996         /*
 997          * These ones are more tricky since they are common to all ports; but
 998          * swfw_sync retries last long enough (1s) to be almost sure that if
 999          * lock can not be taken it is due to an improper lock of the
1000          * semaphore.
1001          */
1002         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1003         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1004                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1005         }
1006         ixgbe_release_swfw_semaphore(hw, mask);
1007 }
1008
1009 /*
1010  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1011  * It returns 0 on success.
1012  */
1013 static int
1014 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1015 {
1016         struct rte_pci_device *pci_dev;
1017         struct ixgbe_hw *hw =
1018                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1019         struct ixgbe_vfta * shadow_vfta =
1020                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1021         struct ixgbe_hwstrip *hwstrip =
1022                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1023         struct ixgbe_dcb_config *dcb_config =
1024                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1025         struct ixgbe_filter_info *filter_info =
1026                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1027         uint32_t ctrl_ext;
1028         uint16_t csum;
1029         int diag, i;
1030
1031         PMD_INIT_FUNC_TRACE();
1032
1033         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1034         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1035         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1036
1037         /*
1038          * For secondary processes, we don't initialise any further as primary
1039          * has already done this work. Only check we don't need a different
1040          * RX and TX function.
1041          */
1042         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1043                 struct ixgbe_tx_queue *txq;
1044                 /* TX queue function in primary, set by last queue initialized
1045                  * Tx queue may not initialized by primary process */
1046                 if (eth_dev->data->tx_queues) {
1047                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1048                         ixgbe_set_tx_function(eth_dev, txq);
1049                 } else {
1050                         /* Use default TX function if we get here */
1051                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1052                                              "Using default TX function.");
1053                 }
1054
1055                 ixgbe_set_rx_function(eth_dev);
1056
1057                 return 0;
1058         }
1059         pci_dev = eth_dev->pci_dev;
1060
1061         rte_eth_copy_pci_info(eth_dev, pci_dev);
1062
1063         /* Vendor and Device ID need to be set before init of shared code */
1064         hw->device_id = pci_dev->id.device_id;
1065         hw->vendor_id = pci_dev->id.vendor_id;
1066         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1067         hw->allow_unsupported_sfp = 1;
1068
1069         /* Initialize the shared code (base driver) */
1070 #ifdef RTE_NIC_BYPASS
1071         diag = ixgbe_bypass_init_shared_code(hw);
1072 #else
1073         diag = ixgbe_init_shared_code(hw);
1074 #endif /* RTE_NIC_BYPASS */
1075
1076         if (diag != IXGBE_SUCCESS) {
1077                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1078                 return -EIO;
1079         }
1080
1081         /* pick up the PCI bus settings for reporting later */
1082         ixgbe_get_bus_info(hw);
1083
1084         /* Unlock any pending hardware semaphore */
1085         ixgbe_swfw_lock_reset(hw);
1086
1087         /* Initialize DCB configuration*/
1088         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1089         ixgbe_dcb_init(hw,dcb_config);
1090         /* Get Hardware Flow Control setting */
1091         hw->fc.requested_mode = ixgbe_fc_full;
1092         hw->fc.current_mode = ixgbe_fc_full;
1093         hw->fc.pause_time = IXGBE_FC_PAUSE;
1094         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1095                 hw->fc.low_water[i] = IXGBE_FC_LO;
1096                 hw->fc.high_water[i] = IXGBE_FC_HI;
1097         }
1098         hw->fc.send_xon = 1;
1099
1100         /* Make sure we have a good EEPROM before we read from it */
1101         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1102         if (diag != IXGBE_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1104                 return -EIO;
1105         }
1106
1107 #ifdef RTE_NIC_BYPASS
1108         diag = ixgbe_bypass_init_hw(hw);
1109 #else
1110         diag = ixgbe_init_hw(hw);
1111 #endif /* RTE_NIC_BYPASS */
1112
1113         /*
1114          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1115          * is called too soon after the kernel driver unbinding/binding occurs.
1116          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1117          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1118          * also called. See ixgbe_identify_phy_82599(). The reason for the
1119          * failure is not known, and only occuts when virtualisation features
1120          * are disabled in the bios. A delay of 100ms  was found to be enough by
1121          * trial-and-error, and is doubled to be safe.
1122          */
1123         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1124                 rte_delay_ms(200);
1125                 diag = ixgbe_init_hw(hw);
1126         }
1127
1128         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1129                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1130                     "LOM.  Please be aware there may be issues associated "
1131                     "with your hardware.");
1132                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1133                     "please contact your Intel or hardware representative "
1134                     "who provided you with this hardware.");
1135         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1136                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1137         if (diag) {
1138                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1139                 return -EIO;
1140         }
1141
1142         /* Reset the hw statistics */
1143         ixgbe_dev_stats_reset(eth_dev);
1144
1145         /* disable interrupt */
1146         ixgbe_disable_intr(hw);
1147
1148         /* reset mappings for queue statistics hw counters*/
1149         ixgbe_reset_qstat_mappings(hw);
1150
1151         /* Allocate memory for storing MAC addresses */
1152         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1153                         hw->mac.num_rar_entries, 0);
1154         if (eth_dev->data->mac_addrs == NULL) {
1155                 PMD_INIT_LOG(ERR,
1156                         "Failed to allocate %u bytes needed to store "
1157                         "MAC addresses",
1158                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1159                 return -ENOMEM;
1160         }
1161         /* Copy the permanent MAC address */
1162         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1163                         &eth_dev->data->mac_addrs[0]);
1164
1165         /* Allocate memory for storing hash filter MAC addresses */
1166         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1168         if (eth_dev->data->hash_mac_addrs == NULL) {
1169                 PMD_INIT_LOG(ERR,
1170                         "Failed to allocate %d bytes needed to store MAC addresses",
1171                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1172                 return -ENOMEM;
1173         }
1174
1175         /* initialize the vfta */
1176         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1177
1178         /* initialize the hw strip bitmap*/
1179         memset(hwstrip, 0, sizeof(*hwstrip));
1180
1181         /* initialize PF if max_vfs not zero */
1182         ixgbe_pf_host_init(eth_dev);
1183
1184         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1185         /* let hardware know driver is loaded */
1186         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1187         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1188         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1189         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1190         IXGBE_WRITE_FLUSH(hw);
1191
1192         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1193                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1194                              (int) hw->mac.type, (int) hw->phy.type,
1195                              (int) hw->phy.sfp_type);
1196         else
1197                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1198                              (int) hw->mac.type, (int) hw->phy.type);
1199
1200         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1201                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1202                         pci_dev->id.device_id);
1203
1204         rte_intr_callback_register(&pci_dev->intr_handle,
1205                                    ixgbe_dev_interrupt_handler,
1206                                    (void *)eth_dev);
1207
1208         /* enable uio/vfio intr/eventfd mapping */
1209         rte_intr_enable(&pci_dev->intr_handle);
1210
1211         /* enable support intr */
1212         ixgbe_enable_intr(eth_dev);
1213
1214         /* initialize 5tuple filter list */
1215         TAILQ_INIT(&filter_info->fivetuple_list);
1216         memset(filter_info->fivetuple_mask, 0,
1217                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1218
1219         return 0;
1220 }
1221
1222 static int
1223 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1224 {
1225         struct rte_pci_device *pci_dev;
1226         struct ixgbe_hw *hw;
1227
1228         PMD_INIT_FUNC_TRACE();
1229
1230         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1231                 return -EPERM;
1232
1233         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1234         pci_dev = eth_dev->pci_dev;
1235
1236         if (hw->adapter_stopped == 0)
1237                 ixgbe_dev_close(eth_dev);
1238
1239         eth_dev->dev_ops = NULL;
1240         eth_dev->rx_pkt_burst = NULL;
1241         eth_dev->tx_pkt_burst = NULL;
1242
1243         /* Unlock any pending hardware semaphore */
1244         ixgbe_swfw_lock_reset(hw);
1245
1246         /* disable uio intr before callback unregister */
1247         rte_intr_disable(&(pci_dev->intr_handle));
1248         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1249                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1250
1251         /* uninitialize PF if max_vfs not zero */
1252         ixgbe_pf_host_uninit(eth_dev);
1253
1254         rte_free(eth_dev->data->mac_addrs);
1255         eth_dev->data->mac_addrs = NULL;
1256
1257         rte_free(eth_dev->data->hash_mac_addrs);
1258         eth_dev->data->hash_mac_addrs = NULL;
1259
1260         return 0;
1261 }
1262
1263 /*
1264  * Negotiate mailbox API version with the PF.
1265  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1266  * Then we try to negotiate starting with the most recent one.
1267  * If all negotiation attempts fail, then we will proceed with
1268  * the default one (ixgbe_mbox_api_10).
1269  */
1270 static void
1271 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1272 {
1273         int32_t i;
1274
1275         /* start with highest supported, proceed down */
1276         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1277                 ixgbe_mbox_api_12,
1278                 ixgbe_mbox_api_11,
1279                 ixgbe_mbox_api_10,
1280         };
1281
1282         for (i = 0;
1283                         i != RTE_DIM(sup_ver) &&
1284                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1285                         i++)
1286                 ;
1287 }
1288
1289 static void
1290 generate_random_mac_addr(struct ether_addr *mac_addr)
1291 {
1292         uint64_t random;
1293
1294         /* Set Organizationally Unique Identifier (OUI) prefix. */
1295         mac_addr->addr_bytes[0] = 0x00;
1296         mac_addr->addr_bytes[1] = 0x09;
1297         mac_addr->addr_bytes[2] = 0xC0;
1298         /* Force indication of locally assigned MAC address. */
1299         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1300         /* Generate the last 3 bytes of the MAC address with a random number. */
1301         random = rte_rand();
1302         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1303 }
1304
1305 /*
1306  * Virtual Function device init
1307  */
1308 static int
1309 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1310 {
1311         int diag;
1312         uint32_t tc, tcs;
1313         struct rte_pci_device *pci_dev;
1314         struct ixgbe_hw *hw =
1315                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316         struct ixgbe_vfta * shadow_vfta =
1317                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1318         struct ixgbe_hwstrip *hwstrip =
1319                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1320         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1321
1322         PMD_INIT_FUNC_TRACE();
1323
1324         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1325         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1326         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1327
1328         /* for secondary processes, we don't initialise any further as primary
1329          * has already done this work. Only check we don't need a different
1330          * RX function */
1331         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1332                 struct ixgbe_tx_queue *txq;
1333                 /* TX queue function in primary, set by last queue initialized
1334                  * Tx queue may not initialized by primary process
1335                  */
1336                 if (eth_dev->data->tx_queues) {
1337                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1338                         ixgbe_set_tx_function(eth_dev, txq);
1339                 } else {
1340                         /* Use default TX function if we get here */
1341                         PMD_INIT_LOG(NOTICE,
1342                                 "No TX queues configured yet. Using default TX function.");
1343                 }
1344
1345                 ixgbe_set_rx_function(eth_dev);
1346
1347                 return 0;
1348         }
1349
1350         pci_dev = eth_dev->pci_dev;
1351
1352         rte_eth_copy_pci_info(eth_dev, pci_dev);
1353
1354         hw->device_id = pci_dev->id.device_id;
1355         hw->vendor_id = pci_dev->id.vendor_id;
1356         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1357
1358         /* initialize the vfta */
1359         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1360
1361         /* initialize the hw strip bitmap*/
1362         memset(hwstrip, 0, sizeof(*hwstrip));
1363
1364         /* Initialize the shared code (base driver) */
1365         diag = ixgbe_init_shared_code(hw);
1366         if (diag != IXGBE_SUCCESS) {
1367                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1368                 return -EIO;
1369         }
1370
1371         /* init_mailbox_params */
1372         hw->mbx.ops.init_params(hw);
1373
1374         /* Reset the hw statistics */
1375         ixgbevf_dev_stats_reset(eth_dev);
1376
1377         /* Disable the interrupts for VF */
1378         ixgbevf_intr_disable(hw);
1379
1380         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1381         diag = hw->mac.ops.reset_hw(hw);
1382
1383         /*
1384          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1385          * the underlying PF driver has not assigned a MAC address to the VF.
1386          * In this case, assign a random MAC address.
1387          */
1388         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1389                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1390                 return diag;
1391         }
1392
1393         /* negotiate mailbox API version to use with the PF. */
1394         ixgbevf_negotiate_api(hw);
1395
1396         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1397         ixgbevf_get_queues(hw, &tcs, &tc);
1398
1399         /* Allocate memory for storing MAC addresses */
1400         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1401                         hw->mac.num_rar_entries, 0);
1402         if (eth_dev->data->mac_addrs == NULL) {
1403                 PMD_INIT_LOG(ERR,
1404                         "Failed to allocate %u bytes needed to store "
1405                         "MAC addresses",
1406                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1407                 return -ENOMEM;
1408         }
1409
1410         /* Generate a random MAC address, if none was assigned by PF. */
1411         if (is_zero_ether_addr(perm_addr)) {
1412                 generate_random_mac_addr(perm_addr);
1413                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1414                 if (diag) {
1415                         rte_free(eth_dev->data->mac_addrs);
1416                         eth_dev->data->mac_addrs = NULL;
1417                         return diag;
1418                 }
1419                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1420                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1421                              "%02x:%02x:%02x:%02x:%02x:%02x",
1422                              perm_addr->addr_bytes[0],
1423                              perm_addr->addr_bytes[1],
1424                              perm_addr->addr_bytes[2],
1425                              perm_addr->addr_bytes[3],
1426                              perm_addr->addr_bytes[4],
1427                              perm_addr->addr_bytes[5]);
1428         }
1429
1430         /* Copy the permanent MAC address */
1431         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1432
1433         /* reset the hardware with the new settings */
1434         diag = hw->mac.ops.start_hw(hw);
1435         switch (diag) {
1436                 case  0:
1437                         break;
1438
1439                 default:
1440                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1441                         return -EIO;
1442         }
1443
1444         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1445                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1446                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1447
1448         return 0;
1449 }
1450
1451 /* Virtual Function device uninit */
1452
1453 static int
1454 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1455 {
1456         struct ixgbe_hw *hw;
1457
1458         PMD_INIT_FUNC_TRACE();
1459
1460         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1461                 return -EPERM;
1462
1463         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1464
1465         if (hw->adapter_stopped == 0)
1466                 ixgbevf_dev_close(eth_dev);
1467
1468         eth_dev->dev_ops = NULL;
1469         eth_dev->rx_pkt_burst = NULL;
1470         eth_dev->tx_pkt_burst = NULL;
1471
1472         /* Disable the interrupts for VF */
1473         ixgbevf_intr_disable(hw);
1474
1475         rte_free(eth_dev->data->mac_addrs);
1476         eth_dev->data->mac_addrs = NULL;
1477
1478         return 0;
1479 }
1480
1481 static struct eth_driver rte_ixgbe_pmd = {
1482         .pci_drv = {
1483                 .name = "rte_ixgbe_pmd",
1484                 .id_table = pci_id_ixgbe_map,
1485                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1486                         RTE_PCI_DRV_DETACHABLE,
1487         },
1488         .eth_dev_init = eth_ixgbe_dev_init,
1489         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1490         .dev_private_size = sizeof(struct ixgbe_adapter),
1491 };
1492
1493 /*
1494  * virtual function driver struct
1495  */
1496 static struct eth_driver rte_ixgbevf_pmd = {
1497         .pci_drv = {
1498                 .name = "rte_ixgbevf_pmd",
1499                 .id_table = pci_id_ixgbevf_map,
1500                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1501         },
1502         .eth_dev_init = eth_ixgbevf_dev_init,
1503         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1504         .dev_private_size = sizeof(struct ixgbe_adapter),
1505 };
1506
1507 /*
1508  * Driver initialization routine.
1509  * Invoked once at EAL init time.
1510  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1511  */
1512 static int
1513 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1514 {
1515         PMD_INIT_FUNC_TRACE();
1516
1517         rte_eth_driver_register(&rte_ixgbe_pmd);
1518         return 0;
1519 }
1520
1521 /*
1522  * VF Driver initialization routine.
1523  * Invoked one at EAL init time.
1524  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1525  */
1526 static int
1527 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1528 {
1529         PMD_INIT_FUNC_TRACE();
1530
1531         rte_eth_driver_register(&rte_ixgbevf_pmd);
1532         return 0;
1533 }
1534
1535 static int
1536 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1537 {
1538         struct ixgbe_hw *hw =
1539                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540         struct ixgbe_vfta * shadow_vfta =
1541                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1542         uint32_t vfta;
1543         uint32_t vid_idx;
1544         uint32_t vid_bit;
1545
1546         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1547         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1548         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1549         if (on)
1550                 vfta |= vid_bit;
1551         else
1552                 vfta &= ~vid_bit;
1553         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1554
1555         /* update local VFTA copy */
1556         shadow_vfta->vfta[vid_idx] = vfta;
1557
1558         return 0;
1559 }
1560
1561 static void
1562 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1563 {
1564         if (on)
1565                 ixgbe_vlan_hw_strip_enable(dev, queue);
1566         else
1567                 ixgbe_vlan_hw_strip_disable(dev, queue);
1568 }
1569
1570 static int
1571 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1572                     enum rte_vlan_type vlan_type,
1573                     uint16_t tpid)
1574 {
1575         struct ixgbe_hw *hw =
1576                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577         int ret = 0;
1578
1579         switch (vlan_type) {
1580         case ETH_VLAN_TYPE_INNER:
1581                 /* Only the high 16-bits is valid */
1582                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1583                 break;
1584         default:
1585                 ret = -EINVAL;
1586                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1587                 break;
1588         }
1589
1590         return ret;
1591 }
1592
1593 void
1594 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1595 {
1596         struct ixgbe_hw *hw =
1597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598         uint32_t vlnctrl;
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         /* Filter Table Disable */
1603         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1604         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1605
1606         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1607 }
1608
1609 void
1610 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1611 {
1612         struct ixgbe_hw *hw =
1613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614         struct ixgbe_vfta * shadow_vfta =
1615                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1616         uint32_t vlnctrl;
1617         uint16_t i;
1618
1619         PMD_INIT_FUNC_TRACE();
1620
1621         /* Filter Table Enable */
1622         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1623         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1624         vlnctrl |= IXGBE_VLNCTRL_VFE;
1625
1626         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1627
1628         /* write whatever is in local vfta copy */
1629         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1630                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1631 }
1632
1633 static void
1634 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1635 {
1636         struct ixgbe_hwstrip *hwstrip =
1637                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1638
1639         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1640                 return;
1641
1642         if (on)
1643                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1644         else
1645                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1646 }
1647
1648 static void
1649 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1650 {
1651         struct ixgbe_hw *hw =
1652                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653         uint32_t ctrl;
1654
1655         PMD_INIT_FUNC_TRACE();
1656
1657         if (hw->mac.type == ixgbe_mac_82598EB) {
1658                 /* No queue level support */
1659                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1660                 return;
1661         }
1662         else {
1663                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1664                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1665                 ctrl &= ~IXGBE_RXDCTL_VME;
1666                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1667         }
1668         /* record those setting for HW strip per queue */
1669         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1670 }
1671
1672 static void
1673 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1674 {
1675         struct ixgbe_hw *hw =
1676                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         uint32_t ctrl;
1678
1679         PMD_INIT_FUNC_TRACE();
1680
1681         if (hw->mac.type == ixgbe_mac_82598EB) {
1682                 /* No queue level supported */
1683                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1684                 return;
1685         }
1686         else {
1687                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1688                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1689                 ctrl |= IXGBE_RXDCTL_VME;
1690                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1691         }
1692         /* record those setting for HW strip per queue */
1693         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1694 }
1695
1696 void
1697 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1698 {
1699         struct ixgbe_hw *hw =
1700                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701         uint32_t ctrl;
1702         uint16_t i;
1703
1704         PMD_INIT_FUNC_TRACE();
1705
1706         if (hw->mac.type == ixgbe_mac_82598EB) {
1707                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1708                 ctrl &= ~IXGBE_VLNCTRL_VME;
1709                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1710         }
1711         else {
1712                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1713                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1714                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1715                         ctrl &= ~IXGBE_RXDCTL_VME;
1716                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1717
1718                         /* record those setting for HW strip per queue */
1719                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1720                 }
1721         }
1722 }
1723
1724 void
1725 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1726 {
1727         struct ixgbe_hw *hw =
1728                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729         uint32_t ctrl;
1730         uint16_t i;
1731
1732         PMD_INIT_FUNC_TRACE();
1733
1734         if (hw->mac.type == ixgbe_mac_82598EB) {
1735                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1736                 ctrl |= IXGBE_VLNCTRL_VME;
1737                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1738         }
1739         else {
1740                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1741                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1742                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1743                         ctrl |= IXGBE_RXDCTL_VME;
1744                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1745
1746                         /* record those setting for HW strip per queue */
1747                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1748                 }
1749         }
1750 }
1751
1752 static void
1753 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1754 {
1755         struct ixgbe_hw *hw =
1756                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757         uint32_t ctrl;
1758
1759         PMD_INIT_FUNC_TRACE();
1760
1761         /* DMATXCTRL: Geric Double VLAN Disable */
1762         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1763         ctrl &= ~IXGBE_DMATXCTL_GDV;
1764         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1765
1766         /* CTRL_EXT: Global Double VLAN Disable */
1767         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1768         ctrl &= ~IXGBE_EXTENDED_VLAN;
1769         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1770
1771 }
1772
1773 static void
1774 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1775 {
1776         struct ixgbe_hw *hw =
1777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1778         uint32_t ctrl;
1779
1780         PMD_INIT_FUNC_TRACE();
1781
1782         /* DMATXCTRL: Geric Double VLAN Enable */
1783         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1784         ctrl |= IXGBE_DMATXCTL_GDV;
1785         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1786
1787         /* CTRL_EXT: Global Double VLAN Enable */
1788         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1789         ctrl |= IXGBE_EXTENDED_VLAN;
1790         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1791
1792         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1793         if (hw->mac.type == ixgbe_mac_X550 ||
1794             hw->mac.type == ixgbe_mac_X550EM_x ||
1795             hw->mac.type == ixgbe_mac_X550EM_a) {
1796                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1797                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1798                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1799         }
1800
1801         /*
1802          * VET EXT field in the EXVET register = 0x8100 by default
1803          * So no need to change. Same to VT field of DMATXCTL register
1804          */
1805 }
1806
1807 static void
1808 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1809 {
1810         if (mask & ETH_VLAN_STRIP_MASK) {
1811                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1812                         ixgbe_vlan_hw_strip_enable_all(dev);
1813                 else
1814                         ixgbe_vlan_hw_strip_disable_all(dev);
1815         }
1816
1817         if (mask & ETH_VLAN_FILTER_MASK) {
1818                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1819                         ixgbe_vlan_hw_filter_enable(dev);
1820                 else
1821                         ixgbe_vlan_hw_filter_disable(dev);
1822         }
1823
1824         if (mask & ETH_VLAN_EXTEND_MASK) {
1825                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1826                         ixgbe_vlan_hw_extend_enable(dev);
1827                 else
1828                         ixgbe_vlan_hw_extend_disable(dev);
1829         }
1830 }
1831
1832 static void
1833 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1834 {
1835         struct ixgbe_hw *hw =
1836                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1838         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1839         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1840         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1841 }
1842
1843 static int
1844 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1845 {
1846         switch (nb_rx_q) {
1847         case 1:
1848         case 2:
1849                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1850                 break;
1851         case 4:
1852                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1853                 break;
1854         default:
1855                 return -EINVAL;
1856         }
1857
1858         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1859         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1860
1861         return 0;
1862 }
1863
1864 static int
1865 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1866 {
1867         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1870         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1871
1872         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1873                 /* check multi-queue mode */
1874                 switch (dev_conf->rxmode.mq_mode) {
1875                 case ETH_MQ_RX_VMDQ_DCB:
1876                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1877                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1878                         PMD_INIT_LOG(ERR, "SRIOV active,"
1879                                         " unsupported mq_mode rx %d.",
1880                                         dev_conf->rxmode.mq_mode);
1881                         return -EINVAL;
1882                 case ETH_MQ_RX_RSS:
1883                 case ETH_MQ_RX_VMDQ_RSS:
1884                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1885                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1886                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1887                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1888                                                 " invalid queue number"
1889                                                 " for VMDQ RSS, allowed"
1890                                                 " value are 1, 2 or 4.");
1891                                         return -EINVAL;
1892                                 }
1893                         break;
1894                 case ETH_MQ_RX_VMDQ_ONLY:
1895                 case ETH_MQ_RX_NONE:
1896                         /* if nothing mq mode configure, use default scheme */
1897                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1898                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1899                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1900                         break;
1901                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1902                         /* SRIOV only works in VMDq enable mode */
1903                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1904                                         " wrong mq_mode rx %d.",
1905                                         dev_conf->rxmode.mq_mode);
1906                         return -EINVAL;
1907                 }
1908
1909                 switch (dev_conf->txmode.mq_mode) {
1910                 case ETH_MQ_TX_VMDQ_DCB:
1911                         /* DCB VMDQ in SRIOV mode, not implement yet */
1912                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1913                                         " unsupported VMDQ mq_mode tx %d.",
1914                                         dev_conf->txmode.mq_mode);
1915                         return -EINVAL;
1916                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1917                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1918                         break;
1919                 }
1920
1921                 /* check valid queue number */
1922                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1923                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1924                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1925                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1926                                         " must be less than or equal to %d.",
1927                                         nb_rx_q, nb_tx_q,
1928                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1929                         return -EINVAL;
1930                 }
1931         } else {
1932                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1933                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1934                                           " not supported.");
1935                         return -EINVAL;
1936                 }
1937                 /* check configuration for vmdb+dcb mode */
1938                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1939                         const struct rte_eth_vmdq_dcb_conf *conf;
1940
1941                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1942                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1943                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1944                                 return -EINVAL;
1945                         }
1946                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1947                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1948                                conf->nb_queue_pools == ETH_32_POOLS)) {
1949                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1950                                                 " nb_queue_pools must be %d or %d.",
1951                                                 ETH_16_POOLS, ETH_32_POOLS);
1952                                 return -EINVAL;
1953                         }
1954                 }
1955                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1956                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1957
1958                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1959                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1960                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1961                                 return -EINVAL;
1962                         }
1963                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1964                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1965                                conf->nb_queue_pools == ETH_32_POOLS)) {
1966                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1967                                                 " nb_queue_pools != %d and"
1968                                                 " nb_queue_pools != %d.",
1969                                                 ETH_16_POOLS, ETH_32_POOLS);
1970                                 return -EINVAL;
1971                         }
1972                 }
1973
1974                 /* For DCB mode check our configuration before we go further */
1975                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1976                         const struct rte_eth_dcb_rx_conf *conf;
1977
1978                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1979                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1980                                                  IXGBE_DCB_NB_QUEUES);
1981                                 return -EINVAL;
1982                         }
1983                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1984                         if (!(conf->nb_tcs == ETH_4_TCS ||
1985                                conf->nb_tcs == ETH_8_TCS)) {
1986                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1987                                                 " and nb_tcs != %d.",
1988                                                 ETH_4_TCS, ETH_8_TCS);
1989                                 return -EINVAL;
1990                         }
1991                 }
1992
1993                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1994                         const struct rte_eth_dcb_tx_conf *conf;
1995
1996                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1997                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1998                                                  IXGBE_DCB_NB_QUEUES);
1999                                 return -EINVAL;
2000                         }
2001                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2002                         if (!(conf->nb_tcs == ETH_4_TCS ||
2003                                conf->nb_tcs == ETH_8_TCS)) {
2004                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2005                                                 " and nb_tcs != %d.",
2006                                                 ETH_4_TCS, ETH_8_TCS);
2007                                 return -EINVAL;
2008                         }
2009                 }
2010
2011                 /*
2012                  * When DCB/VT is off, maximum number of queues changes,
2013                  * except for 82598EB, which remains constant.
2014                  */
2015                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2016                                 hw->mac.type != ixgbe_mac_82598EB) {
2017                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2018                                 PMD_INIT_LOG(ERR,
2019                                              "Neither VT nor DCB are enabled, "
2020                                              "nb_tx_q > %d.",
2021                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2022                                 return -EINVAL;
2023                         }
2024                 }
2025         }
2026         return 0;
2027 }
2028
2029 static int
2030 ixgbe_dev_configure(struct rte_eth_dev *dev)
2031 {
2032         struct ixgbe_interrupt *intr =
2033                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2034         struct ixgbe_adapter *adapter =
2035                 (struct ixgbe_adapter *)dev->data->dev_private;
2036         int ret;
2037
2038         PMD_INIT_FUNC_TRACE();
2039         /* multipe queue mode checking */
2040         ret  = ixgbe_check_mq_mode(dev);
2041         if (ret != 0) {
2042                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2043                             ret);
2044                 return ret;
2045         }
2046
2047         /* set flag to update link status after init */
2048         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2049
2050         /*
2051          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2052          * allocation or vector Rx preconditions we will reset it.
2053          */
2054         adapter->rx_bulk_alloc_allowed = true;
2055         adapter->rx_vec_allowed = true;
2056
2057         return 0;
2058 }
2059
2060 static void
2061 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2062 {
2063         struct ixgbe_hw *hw =
2064                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         struct ixgbe_interrupt *intr =
2066                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2067         uint32_t gpie;
2068
2069         /* only set up it on X550EM_X */
2070         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2071                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2072                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2073                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2074                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2075                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2076         }
2077 }
2078
2079 /*
2080  * Configure device link speed and setup link.
2081  * It returns 0 on success.
2082  */
2083 static int
2084 ixgbe_dev_start(struct rte_eth_dev *dev)
2085 {
2086         struct ixgbe_hw *hw =
2087                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088         struct ixgbe_vf_info *vfinfo =
2089                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2090         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2091         uint32_t intr_vector = 0;
2092         int err, link_up = 0, negotiate = 0;
2093         uint32_t speed = 0;
2094         int mask = 0;
2095         int status;
2096         uint16_t vf, idx;
2097
2098         PMD_INIT_FUNC_TRACE();
2099
2100         /* IXGBE devices don't support half duplex */
2101         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2102                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2103                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2104                              dev->data->dev_conf.link_duplex,
2105                              dev->data->port_id);
2106                 return -EINVAL;
2107         }
2108
2109         /* disable uio/vfio intr/eventfd mapping */
2110         rte_intr_disable(intr_handle);
2111
2112         /* stop adapter */
2113         hw->adapter_stopped = 0;
2114         ixgbe_stop_adapter(hw);
2115
2116         /* reinitialize adapter
2117          * this calls reset and start */
2118         status = ixgbe_pf_reset_hw(hw);
2119         if (status != 0)
2120                 return -1;
2121         hw->mac.ops.start_hw(hw);
2122         hw->mac.get_link_status = true;
2123
2124         /* configure PF module if SRIOV enabled */
2125         ixgbe_pf_host_configure(dev);
2126
2127         ixgbe_dev_phy_intr_setup(dev);
2128
2129         /* check and configure queue intr-vector mapping */
2130         if ((rte_intr_cap_multiple(intr_handle) ||
2131              !RTE_ETH_DEV_SRIOV(dev).active) &&
2132             dev->data->dev_conf.intr_conf.rxq != 0) {
2133                 intr_vector = dev->data->nb_rx_queues;
2134                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2135                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2136                                         IXGBE_MAX_INTR_QUEUE_NUM);
2137                         return -ENOTSUP;
2138                 }
2139                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2140                         return -1;
2141         }
2142
2143         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2144                 intr_handle->intr_vec =
2145                         rte_zmalloc("intr_vec",
2146                                     dev->data->nb_rx_queues * sizeof(int), 0);
2147                 if (intr_handle->intr_vec == NULL) {
2148                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2149                                      " intr_vec\n", dev->data->nb_rx_queues);
2150                         return -ENOMEM;
2151                 }
2152         }
2153
2154         /* confiugre msix for sleep until rx interrupt */
2155         ixgbe_configure_msix(dev);
2156
2157         /* initialize transmission unit */
2158         ixgbe_dev_tx_init(dev);
2159
2160         /* This can fail when allocating mbufs for descriptor rings */
2161         err = ixgbe_dev_rx_init(dev);
2162         if (err) {
2163                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2164                 goto error;
2165         }
2166
2167         err = ixgbe_dev_rxtx_start(dev);
2168         if (err < 0) {
2169                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2170                 goto error;
2171         }
2172
2173         /* Skip link setup if loopback mode is enabled for 82599. */
2174         if (hw->mac.type == ixgbe_mac_82599EB &&
2175                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2176                 goto skip_link_setup;
2177
2178         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2179                 err = hw->mac.ops.setup_sfp(hw);
2180                 if (err)
2181                         goto error;
2182         }
2183
2184         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2185                 /* Turn on the copper */
2186                 ixgbe_set_phy_power(hw, true);
2187         } else {
2188                 /* Turn on the laser */
2189                 ixgbe_enable_tx_laser(hw);
2190         }
2191
2192         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2193         if (err)
2194                 goto error;
2195         dev->data->dev_link.link_status = link_up;
2196
2197         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2198         if (err)
2199                 goto error;
2200
2201         switch(dev->data->dev_conf.link_speed) {
2202         case ETH_LINK_SPEED_AUTONEG:
2203                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2204                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2205                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2206                 break;
2207         case ETH_LINK_SPEED_100:
2208                 /*
2209                  * Invalid for 82598 but error will be detected by
2210                  * ixgbe_setup_link()
2211                  */
2212                 speed = IXGBE_LINK_SPEED_100_FULL;
2213                 break;
2214         case ETH_LINK_SPEED_1000:
2215                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2216                 break;
2217         case ETH_LINK_SPEED_10000:
2218                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2219                 break;
2220         default:
2221                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2222                              dev->data->dev_conf.link_speed,
2223                              dev->data->port_id);
2224                 goto error;
2225         }
2226
2227         err = ixgbe_setup_link(hw, speed, link_up);
2228         if (err)
2229                 goto error;
2230
2231 skip_link_setup:
2232
2233         if (rte_intr_allow_others(intr_handle)) {
2234                 /* check if lsc interrupt is enabled */
2235                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2236                         ixgbe_dev_lsc_interrupt_setup(dev);
2237         } else {
2238                 rte_intr_callback_unregister(intr_handle,
2239                                              ixgbe_dev_interrupt_handler,
2240                                              (void *)dev);
2241                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2242                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2243                                      " no intr multiplex\n");
2244         }
2245
2246         /* check if rxq interrupt is enabled */
2247         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2248             rte_intr_dp_is_en(intr_handle))
2249                 ixgbe_dev_rxq_interrupt_setup(dev);
2250
2251         /* enable uio/vfio intr/eventfd mapping */
2252         rte_intr_enable(intr_handle);
2253
2254         /* resume enabled intr since hw reset */
2255         ixgbe_enable_intr(dev);
2256
2257         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2258                 ETH_VLAN_EXTEND_MASK;
2259         ixgbe_vlan_offload_set(dev, mask);
2260
2261         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2262                 /* Enable vlan filtering for VMDq */
2263                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2264         }
2265
2266         /* Configure DCB hw */
2267         ixgbe_configure_dcb(dev);
2268
2269         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2270                 err = ixgbe_fdir_configure(dev);
2271                 if (err)
2272                         goto error;
2273         }
2274
2275         /* Restore vf rate limit */
2276         if (vfinfo != NULL) {
2277                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2278                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2279                                 if (vfinfo[vf].tx_rate[idx] != 0)
2280                                         ixgbe_set_vf_rate_limit(dev, vf,
2281                                                 vfinfo[vf].tx_rate[idx],
2282                                                 1 << idx);
2283         }
2284
2285         ixgbe_restore_statistics_mapping(dev);
2286
2287         return 0;
2288
2289 error:
2290         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2291         ixgbe_dev_clear_queues(dev);
2292         return -EIO;
2293 }
2294
2295 /*
2296  * Stop device: disable rx and tx functions to allow for reconfiguring.
2297  */
2298 static void
2299 ixgbe_dev_stop(struct rte_eth_dev *dev)
2300 {
2301         struct rte_eth_link link;
2302         struct ixgbe_hw *hw =
2303                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304         struct ixgbe_vf_info *vfinfo =
2305                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2306         struct ixgbe_filter_info *filter_info =
2307                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2308         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2309         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2310         int vf;
2311
2312         PMD_INIT_FUNC_TRACE();
2313
2314         /* disable interrupts */
2315         ixgbe_disable_intr(hw);
2316
2317         /* reset the NIC */
2318         ixgbe_pf_reset_hw(hw);
2319         hw->adapter_stopped = 0;
2320
2321         /* stop adapter */
2322         ixgbe_stop_adapter(hw);
2323
2324         for (vf = 0; vfinfo != NULL &&
2325                      vf < dev->pci_dev->max_vfs; vf++)
2326                 vfinfo[vf].clear_to_send = false;
2327
2328         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2329                 /* Turn off the copper */
2330                 ixgbe_set_phy_power(hw, false);
2331         } else {
2332                 /* Turn off the laser */
2333                 ixgbe_disable_tx_laser(hw);
2334         }
2335
2336         ixgbe_dev_clear_queues(dev);
2337
2338         /* Clear stored conf */
2339         dev->data->scattered_rx = 0;
2340         dev->data->lro = 0;
2341
2342         /* Clear recorded link status */
2343         memset(&link, 0, sizeof(link));
2344         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2345
2346         /* Remove all ntuple filters of the device */
2347         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2348              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2349                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2350                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2351                              p_5tuple, entries);
2352                 rte_free(p_5tuple);
2353         }
2354         memset(filter_info->fivetuple_mask, 0,
2355                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2356
2357         if (!rte_intr_allow_others(intr_handle))
2358                 /* resume to the default handler */
2359                 rte_intr_callback_register(intr_handle,
2360                                            ixgbe_dev_interrupt_handler,
2361                                            (void *)dev);
2362
2363         /* Clean datapath event and queue/vec mapping */
2364         rte_intr_efd_disable(intr_handle);
2365         if (intr_handle->intr_vec != NULL) {
2366                 rte_free(intr_handle->intr_vec);
2367                 intr_handle->intr_vec = NULL;
2368         }
2369 }
2370
2371 /*
2372  * Set device link up: enable tx.
2373  */
2374 static int
2375 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2376 {
2377         struct ixgbe_hw *hw =
2378                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379         if (hw->mac.type == ixgbe_mac_82599EB) {
2380 #ifdef RTE_NIC_BYPASS
2381                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2382                         /* Not suported in bypass mode */
2383                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2384                                      "by device id 0x%x", hw->device_id);
2385                         return -ENOTSUP;
2386                 }
2387 #endif
2388         }
2389
2390         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2391                 /* Turn on the copper */
2392                 ixgbe_set_phy_power(hw, true);
2393         } else {
2394                 /* Turn on the laser */
2395                 ixgbe_enable_tx_laser(hw);
2396         }
2397
2398         return 0;
2399 }
2400
2401 /*
2402  * Set device link down: disable tx.
2403  */
2404 static int
2405 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2406 {
2407         struct ixgbe_hw *hw =
2408                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409         if (hw->mac.type == ixgbe_mac_82599EB) {
2410 #ifdef RTE_NIC_BYPASS
2411                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2412                         /* Not suported in bypass mode */
2413                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2414                                      "by device id 0x%x", hw->device_id);
2415                         return -ENOTSUP;
2416                 }
2417 #endif
2418         }
2419
2420         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2421                 /* Turn off the copper */
2422                 ixgbe_set_phy_power(hw, false);
2423         } else {
2424                 /* Turn off the laser */
2425                 ixgbe_disable_tx_laser(hw);
2426         }
2427
2428         return 0;
2429 }
2430
2431 /*
2432  * Reest and stop device.
2433  */
2434 static void
2435 ixgbe_dev_close(struct rte_eth_dev *dev)
2436 {
2437         struct ixgbe_hw *hw =
2438                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439
2440         PMD_INIT_FUNC_TRACE();
2441
2442         ixgbe_pf_reset_hw(hw);
2443
2444         ixgbe_dev_stop(dev);
2445         hw->adapter_stopped = 1;
2446
2447         ixgbe_dev_free_queues(dev);
2448
2449         ixgbe_disable_pcie_master(hw);
2450
2451         /* reprogram the RAR[0] in case user changed it. */
2452         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2453 }
2454
2455 static void
2456 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2457                            struct ixgbe_hw_stats *hw_stats,
2458                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2459                            uint64_t *total_qprc, uint64_t *total_qprdc)
2460 {
2461         uint32_t bprc, lxon, lxoff, total;
2462         uint32_t delta_gprc = 0;
2463         unsigned i;
2464         /* Workaround for RX byte count not including CRC bytes when CRC
2465 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2466          * is disabled.
2467 +        */
2468         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2469                         IXGBE_HLREG0_RXCRCSTRP);
2470
2471         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2472         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2473         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2474         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2475
2476         for (i = 0; i < 8; i++) {
2477                 uint32_t mp;
2478                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2479                 /* global total per queue */
2480                 hw_stats->mpc[i] += mp;
2481                 /* Running comprehensive total for stats display */
2482                 *total_missed_rx += hw_stats->mpc[i];
2483                 if (hw->mac.type == ixgbe_mac_82598EB) {
2484                         hw_stats->rnbc[i] +=
2485                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2486                         hw_stats->pxonrxc[i] +=
2487                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2488                         hw_stats->pxoffrxc[i] +=
2489                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2490                 } else {
2491                         hw_stats->pxonrxc[i] +=
2492                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2493                         hw_stats->pxoffrxc[i] +=
2494                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2495                         hw_stats->pxon2offc[i] +=
2496                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2497                 }
2498                 hw_stats->pxontxc[i] +=
2499                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2500                 hw_stats->pxofftxc[i] +=
2501                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2502         }
2503         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2504                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2505                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2506                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2507
2508                 delta_gprc += delta_qprc;
2509
2510                 hw_stats->qprc[i] += delta_qprc;
2511                 hw_stats->qptc[i] += delta_qptc;
2512
2513                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2514                 hw_stats->qbrc[i] +=
2515                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2516                 if (crc_strip == 0)
2517                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2518
2519                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2520                 hw_stats->qbtc[i] +=
2521                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2522
2523                 hw_stats->qprdc[i] += delta_qprdc;
2524                 *total_qprdc += hw_stats->qprdc[i];
2525
2526                 *total_qprc += hw_stats->qprc[i];
2527                 *total_qbrc += hw_stats->qbrc[i];
2528         }
2529         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2530         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2531         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2532
2533         /*
2534          * An errata states that gprc actually counts good + missed packets:
2535          * Workaround to set gprc to summated queue packet receives
2536          */
2537         hw_stats->gprc = *total_qprc;
2538
2539         if (hw->mac.type != ixgbe_mac_82598EB) {
2540                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2541                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2542                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2543                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2544                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2545                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2546                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2547                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2548         } else {
2549                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2550                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2551                 /* 82598 only has a counter in the high register */
2552                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2553                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2554                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2555         }
2556         uint64_t old_tpr = hw_stats->tpr;
2557
2558         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2559         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2560
2561         if (crc_strip == 0)
2562                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2563
2564         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2565         hw_stats->gptc += delta_gptc;
2566         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2567         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2568
2569         /*
2570          * Workaround: mprc hardware is incorrectly counting
2571          * broadcasts, so for now we subtract those.
2572          */
2573         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2574         hw_stats->bprc += bprc;
2575         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2576         if (hw->mac.type == ixgbe_mac_82598EB)
2577                 hw_stats->mprc -= bprc;
2578
2579         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2580         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2581         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2582         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2583         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2584         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2585
2586         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2587         hw_stats->lxontxc += lxon;
2588         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2589         hw_stats->lxofftxc += lxoff;
2590         total = lxon + lxoff;
2591
2592         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2593         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2594         hw_stats->gptc -= total;
2595         hw_stats->mptc -= total;
2596         hw_stats->ptc64 -= total;
2597         hw_stats->gotc -= total * ETHER_MIN_LEN;
2598
2599         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2600         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2601         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2602         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2603         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2604         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2605         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2606         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2607         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2608         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2609         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2610         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2611         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2612         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2613         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2614         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2615         /* Only read FCOE on 82599 */
2616         if (hw->mac.type != ixgbe_mac_82598EB) {
2617                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2618                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2619                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2620                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2621                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2622         }
2623
2624         /* Flow Director Stats registers */
2625         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2626         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2627 }
2628
2629 /*
2630  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2631  */
2632 static void
2633 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2634 {
2635         struct ixgbe_hw *hw =
2636                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2637         struct ixgbe_hw_stats *hw_stats =
2638                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2639         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2640         unsigned i;
2641
2642         total_missed_rx = 0;
2643         total_qbrc = 0;
2644         total_qprc = 0;
2645         total_qprdc = 0;
2646
2647         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2648                         &total_qprc, &total_qprdc);
2649
2650         if (stats == NULL)
2651                 return;
2652
2653         /* Fill out the rte_eth_stats statistics structure */
2654         stats->ipackets = total_qprc;
2655         stats->ibytes = total_qbrc;
2656         stats->opackets = hw_stats->gptc;
2657         stats->obytes = hw_stats->gotc;
2658
2659         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2660                 stats->q_ipackets[i] = hw_stats->qprc[i];
2661                 stats->q_opackets[i] = hw_stats->qptc[i];
2662                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2663                 stats->q_obytes[i] = hw_stats->qbtc[i];
2664                 stats->q_errors[i] = hw_stats->qprdc[i];
2665         }
2666
2667         /* Rx Errors */
2668         stats->imissed  = total_missed_rx;
2669         stats->ierrors  = hw_stats->crcerrs +
2670                           hw_stats->mspdc +
2671                           hw_stats->rlec +
2672                           hw_stats->ruc +
2673                           hw_stats->roc +
2674                           hw_stats->illerrc +
2675                           hw_stats->errbc +
2676                           hw_stats->rfc +
2677                           hw_stats->fccrc +
2678                           hw_stats->fclast;
2679
2680         /* Tx Errors */
2681         stats->oerrors  = 0;
2682 }
2683
2684 static void
2685 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2686 {
2687         struct ixgbe_hw_stats *stats =
2688                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2689
2690         /* HW registers are cleared on read */
2691         ixgbe_dev_stats_get(dev, NULL);
2692
2693         /* Reset software totals */
2694         memset(stats, 0, sizeof(*stats));
2695 }
2696
2697 /* This function calculates the number of xstats based on the current config */
2698 static unsigned
2699 ixgbe_xstats_calc_num(void) {
2700         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2701                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2702 }
2703
2704 static int
2705 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2706                                          unsigned n)
2707 {
2708         struct ixgbe_hw *hw =
2709                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2710         struct ixgbe_hw_stats *hw_stats =
2711                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2712         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2713         unsigned i, stat, count = 0;
2714
2715         count = ixgbe_xstats_calc_num();
2716
2717         if (n < count)
2718                 return count;
2719
2720         total_missed_rx = 0;
2721         total_qbrc = 0;
2722         total_qprc = 0;
2723         total_qprdc = 0;
2724
2725         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2726                                    &total_qprc, &total_qprdc);
2727
2728         /* If this is a reset xstats is NULL, and we have cleared the
2729          * registers by reading them.
2730          */
2731         if (!xstats)
2732                 return 0;
2733
2734         /* Extended stats from ixgbe_hw_stats */
2735         count = 0;
2736         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2737                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2738                          rte_ixgbe_stats_strings[i].name);
2739                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2740                                 rte_ixgbe_stats_strings[i].offset);
2741                 count++;
2742         }
2743
2744         /* RX Priority Stats */
2745         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2746                 for (i = 0; i < 8; i++) {
2747                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2748                                  "rx_priority%u_%s", i,
2749                                  rte_ixgbe_rxq_strings[stat].name);
2750                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2751                                         rte_ixgbe_rxq_strings[stat].offset +
2752                                         (sizeof(uint64_t) * i));
2753                         count++;
2754                 }
2755         }
2756
2757         /* TX Priority Stats */
2758         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2759                 for (i = 0; i < 8; i++) {
2760                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2761                                  "tx_priority%u_%s", i,
2762                                  rte_ixgbe_txq_strings[stat].name);
2763                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2764                                         rte_ixgbe_txq_strings[stat].offset +
2765                                         (sizeof(uint64_t) * i));
2766                         count++;
2767                 }
2768         }
2769
2770         return count;
2771 }
2772
2773 static void
2774 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2775 {
2776         struct ixgbe_hw_stats *stats =
2777                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2778
2779         unsigned count = ixgbe_xstats_calc_num();
2780
2781         /* HW registers are cleared on read */
2782         ixgbe_dev_xstats_get(dev, NULL, count);
2783
2784         /* Reset software totals */
2785         memset(stats, 0, sizeof(*stats));
2786 }
2787
2788 static void
2789 ixgbevf_update_stats(struct rte_eth_dev *dev)
2790 {
2791         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2792         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2793                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2794
2795         /* Good Rx packet, include VF loopback */
2796         UPDATE_VF_STAT(IXGBE_VFGPRC,
2797             hw_stats->last_vfgprc, hw_stats->vfgprc);
2798
2799         /* Good Rx octets, include VF loopback */
2800         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2801             hw_stats->last_vfgorc, hw_stats->vfgorc);
2802
2803         /* Good Tx packet, include VF loopback */
2804         UPDATE_VF_STAT(IXGBE_VFGPTC,
2805             hw_stats->last_vfgptc, hw_stats->vfgptc);
2806
2807         /* Good Tx octets, include VF loopback */
2808         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2809             hw_stats->last_vfgotc, hw_stats->vfgotc);
2810
2811         /* Rx Multicst Packet */
2812         UPDATE_VF_STAT(IXGBE_VFMPRC,
2813             hw_stats->last_vfmprc, hw_stats->vfmprc);
2814 }
2815
2816 static int
2817 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2818                        unsigned n)
2819 {
2820         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2821                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2822         unsigned i;
2823
2824         if (n < IXGBEVF_NB_XSTATS)
2825                 return IXGBEVF_NB_XSTATS;
2826
2827         ixgbevf_update_stats(dev);
2828
2829         if (!xstats)
2830                 return 0;
2831
2832         /* Extended stats */
2833         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2834                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2835                          "%s", rte_ixgbevf_stats_strings[i].name);
2836                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2837                         rte_ixgbevf_stats_strings[i].offset);
2838         }
2839
2840         return IXGBEVF_NB_XSTATS;
2841 }
2842
2843 static void
2844 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2845 {
2846         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2847                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2848
2849         ixgbevf_update_stats(dev);
2850
2851         if (stats == NULL)
2852                 return;
2853
2854         stats->ipackets = hw_stats->vfgprc;
2855         stats->ibytes = hw_stats->vfgorc;
2856         stats->opackets = hw_stats->vfgptc;
2857         stats->obytes = hw_stats->vfgotc;
2858         stats->imcasts = hw_stats->vfmprc;
2859         /* stats->imcasts should be removed as imcasts is deprecated */
2860 }
2861
2862 static void
2863 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2864 {
2865         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2866                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2867
2868         /* Sync HW register to the last stats */
2869         ixgbevf_dev_stats_get(dev, NULL);
2870
2871         /* reset HW current stats*/
2872         hw_stats->vfgprc = 0;
2873         hw_stats->vfgorc = 0;
2874         hw_stats->vfgptc = 0;
2875         hw_stats->vfgotc = 0;
2876         hw_stats->vfmprc = 0;
2877
2878 }
2879
2880 static void
2881 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2882 {
2883         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2885
2886         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2887         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2888         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
2889                 /*
2890                  * When DCB/VT is off, maximum number of queues changes,
2891                  * except for 82598EB, which remains constant.
2892                  */
2893                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2894                                 hw->mac.type != ixgbe_mac_82598EB)
2895                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
2896         }
2897         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2898         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2899         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2900         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2901         dev_info->max_vfs = dev->pci_dev->max_vfs;
2902         if (hw->mac.type == ixgbe_mac_82598EB)
2903                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2904         else
2905                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2906         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2907         dev_info->rx_offload_capa =
2908                 DEV_RX_OFFLOAD_VLAN_STRIP |
2909                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2910                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2911                 DEV_RX_OFFLOAD_TCP_CKSUM;
2912
2913         /*
2914          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2915          * mode.
2916          */
2917         if ((hw->mac.type == ixgbe_mac_82599EB ||
2918              hw->mac.type == ixgbe_mac_X540) &&
2919             !RTE_ETH_DEV_SRIOV(dev).active)
2920                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2921
2922         if (hw->mac.type == ixgbe_mac_X550 ||
2923             hw->mac.type == ixgbe_mac_X550EM_x ||
2924             hw->mac.type == ixgbe_mac_X550EM_a)
2925                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2926
2927         dev_info->tx_offload_capa =
2928                 DEV_TX_OFFLOAD_VLAN_INSERT |
2929                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2930                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2931                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2932                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2933                 DEV_TX_OFFLOAD_TCP_TSO;
2934
2935         if (hw->mac.type == ixgbe_mac_X550 ||
2936             hw->mac.type == ixgbe_mac_X550EM_x ||
2937             hw->mac.type == ixgbe_mac_X550EM_a)
2938                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2939
2940         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2941                 .rx_thresh = {
2942                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2943                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2944                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2945                 },
2946                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2947                 .rx_drop_en = 0,
2948         };
2949
2950         dev_info->default_txconf = (struct rte_eth_txconf) {
2951                 .tx_thresh = {
2952                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2953                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2954                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2955                 },
2956                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2957                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2958                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2959                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2960         };
2961
2962         dev_info->rx_desc_lim = rx_desc_lim;
2963         dev_info->tx_desc_lim = tx_desc_lim;
2964
2965         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2966         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2967         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2968 }
2969
2970 static const uint32_t *
2971 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2972 {
2973         static const uint32_t ptypes[] = {
2974                 /* For non-vec functions,
2975                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
2976                  * for vec functions,
2977                  * refers to _recv_raw_pkts_vec().
2978                  */
2979                 RTE_PTYPE_L2_ETHER,
2980                 RTE_PTYPE_L3_IPV4,
2981                 RTE_PTYPE_L3_IPV4_EXT,
2982                 RTE_PTYPE_L3_IPV6,
2983                 RTE_PTYPE_L3_IPV6_EXT,
2984                 RTE_PTYPE_L4_SCTP,
2985                 RTE_PTYPE_L4_TCP,
2986                 RTE_PTYPE_L4_UDP,
2987                 RTE_PTYPE_TUNNEL_IP,
2988                 RTE_PTYPE_INNER_L3_IPV6,
2989                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2990                 RTE_PTYPE_INNER_L4_TCP,
2991                 RTE_PTYPE_INNER_L4_UDP,
2992                 RTE_PTYPE_UNKNOWN
2993         };
2994
2995         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
2996             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
2997             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
2998             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
2999                 return ptypes;
3000         return NULL;
3001 }
3002
3003 static void
3004 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3005                      struct rte_eth_dev_info *dev_info)
3006 {
3007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3008
3009         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3010         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3011         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3012         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3013         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3014         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3015         dev_info->max_vfs = dev->pci_dev->max_vfs;
3016         if (hw->mac.type == ixgbe_mac_82598EB)
3017                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3018         else
3019                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3020         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3021                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3022                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3023                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3024         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3025                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3026                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3027                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3028                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3029                                 DEV_TX_OFFLOAD_TCP_TSO;
3030
3031         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3032                 .rx_thresh = {
3033                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3034                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3035                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3036                 },
3037                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3038                 .rx_drop_en = 0,
3039         };
3040
3041         dev_info->default_txconf = (struct rte_eth_txconf) {
3042                 .tx_thresh = {
3043                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3044                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3045                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3046                 },
3047                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3048                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3049                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3050                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3051         };
3052
3053         dev_info->rx_desc_lim = rx_desc_lim;
3054         dev_info->tx_desc_lim = tx_desc_lim;
3055 }
3056
3057 /* return 0 means link status changed, -1 means not changed */
3058 static int
3059 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3060 {
3061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3062         struct rte_eth_link link, old;
3063         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3064         int link_up;
3065         int diag;
3066
3067         link.link_status = 0;
3068         link.link_speed = 0;
3069         link.link_duplex = 0;
3070         memset(&old, 0, sizeof(old));
3071         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3072
3073         hw->mac.get_link_status = true;
3074
3075         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3076         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3077                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3078         else
3079                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3080
3081         if (diag != 0) {
3082                 link.link_speed = ETH_LINK_SPEED_100;
3083                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3084                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3085                 if (link.link_status == old.link_status)
3086                         return -1;
3087                 return 0;
3088         }
3089
3090         if (link_up == 0) {
3091                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3092                 if (link.link_status == old.link_status)
3093                         return -1;
3094                 return 0;
3095         }
3096         link.link_status = 1;
3097         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3098
3099         switch (link_speed) {
3100         default:
3101         case IXGBE_LINK_SPEED_UNKNOWN:
3102                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3103                 link.link_speed = ETH_LINK_SPEED_100;
3104                 break;
3105
3106         case IXGBE_LINK_SPEED_100_FULL:
3107                 link.link_speed = ETH_LINK_SPEED_100;
3108                 break;
3109
3110         case IXGBE_LINK_SPEED_1GB_FULL:
3111                 link.link_speed = ETH_LINK_SPEED_1000;
3112                 break;
3113
3114         case IXGBE_LINK_SPEED_10GB_FULL:
3115                 link.link_speed = ETH_LINK_SPEED_10000;
3116                 break;
3117         }
3118         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3119
3120         if (link.link_status == old.link_status)
3121                 return -1;
3122
3123         return 0;
3124 }
3125
3126 static void
3127 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3128 {
3129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3130         uint32_t fctrl;
3131
3132         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3133         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3134         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3135 }
3136
3137 static void
3138 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3139 {
3140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3141         uint32_t fctrl;
3142
3143         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3144         fctrl &= (~IXGBE_FCTRL_UPE);
3145         if (dev->data->all_multicast == 1)
3146                 fctrl |= IXGBE_FCTRL_MPE;
3147         else
3148                 fctrl &= (~IXGBE_FCTRL_MPE);
3149         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3150 }
3151
3152 static void
3153 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3154 {
3155         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3156         uint32_t fctrl;
3157
3158         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3159         fctrl |= IXGBE_FCTRL_MPE;
3160         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3161 }
3162
3163 static void
3164 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3165 {
3166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3167         uint32_t fctrl;
3168
3169         if (dev->data->promiscuous == 1)
3170                 return; /* must remain in all_multicast mode */
3171
3172         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3173         fctrl &= (~IXGBE_FCTRL_MPE);
3174         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3175 }
3176
3177 /**
3178  * It clears the interrupt causes and enables the interrupt.
3179  * It will be called once only during nic initialized.
3180  *
3181  * @param dev
3182  *  Pointer to struct rte_eth_dev.
3183  *
3184  * @return
3185  *  - On success, zero.
3186  *  - On failure, a negative value.
3187  */
3188 static int
3189 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3190 {
3191         struct ixgbe_interrupt *intr =
3192                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3193
3194         ixgbe_dev_link_status_print(dev);
3195         intr->mask |= IXGBE_EICR_LSC;
3196
3197         return 0;
3198 }
3199
3200 /**
3201  * It clears the interrupt causes and enables the interrupt.
3202  * It will be called once only during nic initialized.
3203  *
3204  * @param dev
3205  *  Pointer to struct rte_eth_dev.
3206  *
3207  * @return
3208  *  - On success, zero.
3209  *  - On failure, a negative value.
3210  */
3211 static int
3212 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3213 {
3214         struct ixgbe_interrupt *intr =
3215                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3216
3217         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3218
3219         return 0;
3220 }
3221
3222 /*
3223  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3224  *
3225  * @param dev
3226  *  Pointer to struct rte_eth_dev.
3227  *
3228  * @return
3229  *  - On success, zero.
3230  *  - On failure, a negative value.
3231  */
3232 static int
3233 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3234 {
3235         uint32_t eicr;
3236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3237         struct ixgbe_interrupt *intr =
3238                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3239
3240         /* clear all cause mask */
3241         ixgbe_disable_intr(hw);
3242
3243         /* read-on-clear nic registers here */
3244         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3245         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3246
3247         intr->flags = 0;
3248
3249         /* set flag for async link update */
3250         if (eicr & IXGBE_EICR_LSC)
3251                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3252
3253         if (eicr & IXGBE_EICR_MAILBOX)
3254                 intr->flags |= IXGBE_FLAG_MAILBOX;
3255
3256         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3257             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3258             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3259                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3260
3261         return 0;
3262 }
3263
3264 /**
3265  * It gets and then prints the link status.
3266  *
3267  * @param dev
3268  *  Pointer to struct rte_eth_dev.
3269  *
3270  * @return
3271  *  - On success, zero.
3272  *  - On failure, a negative value.
3273  */
3274 static void
3275 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3276 {
3277         struct rte_eth_link link;
3278
3279         memset(&link, 0, sizeof(link));
3280         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3281         if (link.link_status) {
3282                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3283                                         (int)(dev->data->port_id),
3284                                         (unsigned)link.link_speed,
3285                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3286                                         "full-duplex" : "half-duplex");
3287         } else {
3288                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3289                                 (int)(dev->data->port_id));
3290         }
3291         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3292                                 dev->pci_dev->addr.domain,
3293                                 dev->pci_dev->addr.bus,
3294                                 dev->pci_dev->addr.devid,
3295                                 dev->pci_dev->addr.function);
3296 }
3297
3298 /*
3299  * It executes link_update after knowing an interrupt occurred.
3300  *
3301  * @param dev
3302  *  Pointer to struct rte_eth_dev.
3303  *
3304  * @return
3305  *  - On success, zero.
3306  *  - On failure, a negative value.
3307  */
3308 static int
3309 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3310 {
3311         struct ixgbe_interrupt *intr =
3312                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3313         int64_t timeout;
3314         struct rte_eth_link link;
3315         int intr_enable_delay = false;
3316         struct ixgbe_hw *hw =
3317                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3318
3319         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3320
3321         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3322                 ixgbe_pf_mbx_process(dev);
3323                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3324         }
3325
3326         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3327                 ixgbe_handle_lasi(hw);
3328                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3329         }
3330
3331         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3332                 /* get the link status before link update, for predicting later */
3333                 memset(&link, 0, sizeof(link));
3334                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3335
3336                 ixgbe_dev_link_update(dev, 0);
3337
3338                 /* likely to up */
3339                 if (!link.link_status)
3340                         /* handle it 1 sec later, wait it being stable */
3341                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3342                 /* likely to down */
3343                 else
3344                         /* handle it 4 sec later, wait it being stable */
3345                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3346
3347                 ixgbe_dev_link_status_print(dev);
3348
3349                 intr_enable_delay = true;
3350         }
3351
3352         if (intr_enable_delay) {
3353                 if (rte_eal_alarm_set(timeout * 1000,
3354                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3355                         PMD_DRV_LOG(ERR, "Error setting alarm");
3356         } else {
3357                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3358                 ixgbe_enable_intr(dev);
3359                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3360         }
3361
3362
3363         return 0;
3364 }
3365
3366 /**
3367  * Interrupt handler which shall be registered for alarm callback for delayed
3368  * handling specific interrupt to wait for the stable nic state. As the
3369  * NIC interrupt state is not stable for ixgbe after link is just down,
3370  * it needs to wait 4 seconds to get the stable status.
3371  *
3372  * @param handle
3373  *  Pointer to interrupt handle.
3374  * @param param
3375  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3376  *
3377  * @return
3378  *  void
3379  */
3380 static void
3381 ixgbe_dev_interrupt_delayed_handler(void *param)
3382 {
3383         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3384         struct ixgbe_interrupt *intr =
3385                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3386         struct ixgbe_hw *hw =
3387                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3388         uint32_t eicr;
3389
3390         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3391         if (eicr & IXGBE_EICR_MAILBOX)
3392                 ixgbe_pf_mbx_process(dev);
3393
3394         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3395                 ixgbe_handle_lasi(hw);
3396                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3397         }
3398
3399         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3400                 ixgbe_dev_link_update(dev, 0);
3401                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3402                 ixgbe_dev_link_status_print(dev);
3403                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3404         }
3405
3406         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3407         ixgbe_enable_intr(dev);
3408         rte_intr_enable(&(dev->pci_dev->intr_handle));
3409 }
3410
3411 /**
3412  * Interrupt handler triggered by NIC  for handling
3413  * specific interrupt.
3414  *
3415  * @param handle
3416  *  Pointer to interrupt handle.
3417  * @param param
3418  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3419  *
3420  * @return
3421  *  void
3422  */
3423 static void
3424 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3425                             void *param)
3426 {
3427         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3428
3429         ixgbe_dev_interrupt_get_status(dev);
3430         ixgbe_dev_interrupt_action(dev);
3431 }
3432
3433 static int
3434 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3435 {
3436         struct ixgbe_hw *hw;
3437
3438         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3440 }
3441
3442 static int
3443 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3444 {
3445         struct ixgbe_hw *hw;
3446
3447         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3448         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3449 }
3450
3451 static int
3452 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3453 {
3454         struct ixgbe_hw *hw;
3455         uint32_t mflcn_reg;
3456         uint32_t fccfg_reg;
3457         int rx_pause;
3458         int tx_pause;
3459
3460         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3461
3462         fc_conf->pause_time = hw->fc.pause_time;
3463         fc_conf->high_water = hw->fc.high_water[0];
3464         fc_conf->low_water = hw->fc.low_water[0];
3465         fc_conf->send_xon = hw->fc.send_xon;
3466         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3467
3468         /*
3469          * Return rx_pause status according to actual setting of
3470          * MFLCN register.
3471          */
3472         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3473         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3474                 rx_pause = 1;
3475         else
3476                 rx_pause = 0;
3477
3478         /*
3479          * Return tx_pause status according to actual setting of
3480          * FCCFG register.
3481          */
3482         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3483         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3484                 tx_pause = 1;
3485         else
3486                 tx_pause = 0;
3487
3488         if (rx_pause && tx_pause)
3489                 fc_conf->mode = RTE_FC_FULL;
3490         else if (rx_pause)
3491                 fc_conf->mode = RTE_FC_RX_PAUSE;
3492         else if (tx_pause)
3493                 fc_conf->mode = RTE_FC_TX_PAUSE;
3494         else
3495                 fc_conf->mode = RTE_FC_NONE;
3496
3497         return 0;
3498 }
3499
3500 static int
3501 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3502 {
3503         struct ixgbe_hw *hw;
3504         int err;
3505         uint32_t rx_buf_size;
3506         uint32_t max_high_water;
3507         uint32_t mflcn;
3508         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3509                 ixgbe_fc_none,
3510                 ixgbe_fc_rx_pause,
3511                 ixgbe_fc_tx_pause,
3512                 ixgbe_fc_full
3513         };
3514
3515         PMD_INIT_FUNC_TRACE();
3516
3517         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3519         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3520
3521         /*
3522          * At least reserve one Ethernet frame for watermark
3523          * high_water/low_water in kilo bytes for ixgbe
3524          */
3525         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3526         if ((fc_conf->high_water > max_high_water) ||
3527                 (fc_conf->high_water < fc_conf->low_water)) {
3528                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3529                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3530                 return -EINVAL;
3531         }
3532
3533         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3534         hw->fc.pause_time     = fc_conf->pause_time;
3535         hw->fc.high_water[0]  = fc_conf->high_water;
3536         hw->fc.low_water[0]   = fc_conf->low_water;
3537         hw->fc.send_xon       = fc_conf->send_xon;
3538         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3539
3540         err = ixgbe_fc_enable(hw);
3541
3542         /* Not negotiated is not an error case */
3543         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3544
3545                 /* check if we want to forward MAC frames - driver doesn't have native
3546                  * capability to do that, so we'll write the registers ourselves */
3547
3548                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3549
3550                 /* set or clear MFLCN.PMCF bit depending on configuration */
3551                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3552                         mflcn |= IXGBE_MFLCN_PMCF;
3553                 else
3554                         mflcn &= ~IXGBE_MFLCN_PMCF;
3555
3556                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3557                 IXGBE_WRITE_FLUSH(hw);
3558
3559                 return 0;
3560         }
3561
3562         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3563         return -EIO;
3564 }
3565
3566 /**
3567  *  ixgbe_pfc_enable_generic - Enable flow control
3568  *  @hw: pointer to hardware structure
3569  *  @tc_num: traffic class number
3570  *  Enable flow control according to the current settings.
3571  */
3572 static int
3573 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3574 {
3575         int ret_val = 0;
3576         uint32_t mflcn_reg, fccfg_reg;
3577         uint32_t reg;
3578         uint32_t fcrtl, fcrth;
3579         uint8_t i;
3580         uint8_t nb_rx_en;
3581
3582         /* Validate the water mark configuration */
3583         if (!hw->fc.pause_time) {
3584                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3585                 goto out;
3586         }
3587
3588         /* Low water mark of zero causes XOFF floods */
3589         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3590                  /* High/Low water can not be 0 */
3591                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3592                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3593                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3594                         goto out;
3595                 }
3596
3597                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3598                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3599                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3600                         goto out;
3601                 }
3602         }
3603         /* Negotiate the fc mode to use */
3604         ixgbe_fc_autoneg(hw);
3605
3606         /* Disable any previous flow control settings */
3607         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3608         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3609
3610         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3611         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3612
3613         switch (hw->fc.current_mode) {
3614         case ixgbe_fc_none:
3615                 /*
3616                  * If the count of enabled RX Priority Flow control >1,
3617                  * and the TX pause can not be disabled
3618                  */
3619                 nb_rx_en = 0;
3620                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3621                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3622                         if (reg & IXGBE_FCRTH_FCEN)
3623                                 nb_rx_en++;
3624                 }
3625                 if (nb_rx_en > 1)
3626                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3627                 break;
3628         case ixgbe_fc_rx_pause:
3629                 /*
3630                  * Rx Flow control is enabled and Tx Flow control is
3631                  * disabled by software override. Since there really
3632                  * isn't a way to advertise that we are capable of RX
3633                  * Pause ONLY, we will advertise that we support both
3634                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3635                  * disable the adapter's ability to send PAUSE frames.
3636                  */
3637                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3638                 /*
3639                  * If the count of enabled RX Priority Flow control >1,
3640                  * and the TX pause can not be disabled
3641                  */
3642                 nb_rx_en = 0;
3643                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3644                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3645                         if (reg & IXGBE_FCRTH_FCEN)
3646                                 nb_rx_en++;
3647                 }
3648                 if (nb_rx_en > 1)
3649                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3650                 break;
3651         case ixgbe_fc_tx_pause:
3652                 /*
3653                  * Tx Flow control is enabled, and Rx Flow control is
3654                  * disabled by software override.
3655                  */
3656                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3657                 break;
3658         case ixgbe_fc_full:
3659                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3660                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3661                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3662                 break;
3663         default:
3664                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3665                 ret_val = IXGBE_ERR_CONFIG;
3666                 goto out;
3667                 break;
3668         }
3669
3670         /* Set 802.3x based flow control settings. */
3671         mflcn_reg |= IXGBE_MFLCN_DPF;
3672         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3673         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3674
3675         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3676         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3677                 hw->fc.high_water[tc_num]) {
3678                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3679                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3680                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3681         } else {
3682                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3683                 /*
3684                  * In order to prevent Tx hangs when the internal Tx
3685                  * switch is enabled we must set the high water mark
3686                  * to the maximum FCRTH value.  This allows the Tx
3687                  * switch to function even under heavy Rx workloads.
3688                  */
3689                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3690         }
3691         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3692
3693         /* Configure pause time (2 TCs per register) */
3694         reg = hw->fc.pause_time * 0x00010001;
3695         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3696                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3697
3698         /* Configure flow control refresh threshold value */
3699         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3700
3701 out:
3702         return ret_val;
3703 }
3704
3705 static int
3706 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3707 {
3708         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3710
3711         if (hw->mac.type != ixgbe_mac_82598EB) {
3712                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3713         }
3714         return ret_val;
3715 }
3716
3717 static int
3718 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3719 {
3720         int err;
3721         uint32_t rx_buf_size;
3722         uint32_t max_high_water;
3723         uint8_t tc_num;
3724         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3725         struct ixgbe_hw *hw =
3726                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3727         struct ixgbe_dcb_config *dcb_config =
3728                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3729
3730         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3731                 ixgbe_fc_none,
3732                 ixgbe_fc_rx_pause,
3733                 ixgbe_fc_tx_pause,
3734                 ixgbe_fc_full
3735         };
3736
3737         PMD_INIT_FUNC_TRACE();
3738
3739         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3740         tc_num = map[pfc_conf->priority];
3741         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3742         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3743         /*
3744          * At least reserve one Ethernet frame for watermark
3745          * high_water/low_water in kilo bytes for ixgbe
3746          */
3747         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3748         if ((pfc_conf->fc.high_water > max_high_water) ||
3749             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3750                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3751                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3752                 return -EINVAL;
3753         }
3754
3755         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3756         hw->fc.pause_time = pfc_conf->fc.pause_time;
3757         hw->fc.send_xon = pfc_conf->fc.send_xon;
3758         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3759         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3760
3761         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3762
3763         /* Not negotiated is not an error case */
3764         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3765                 return 0;
3766
3767         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3768         return -EIO;
3769 }
3770
3771 static int
3772 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3773                           struct rte_eth_rss_reta_entry64 *reta_conf,
3774                           uint16_t reta_size)
3775 {
3776         uint16_t i, sp_reta_size;
3777         uint8_t j, mask;
3778         uint32_t reta, r;
3779         uint16_t idx, shift;
3780         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3781         uint32_t reta_reg;
3782
3783         PMD_INIT_FUNC_TRACE();
3784
3785         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3786                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3787                         "NIC.");
3788                 return -ENOTSUP;
3789         }
3790
3791         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3792         if (reta_size != sp_reta_size) {
3793                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3794                         "(%d) doesn't match the number hardware can supported "
3795                         "(%d)\n", reta_size, sp_reta_size);
3796                 return -EINVAL;
3797         }
3798
3799         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3800                 idx = i / RTE_RETA_GROUP_SIZE;
3801                 shift = i % RTE_RETA_GROUP_SIZE;
3802                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3803                                                 IXGBE_4_BIT_MASK);
3804                 if (!mask)
3805                         continue;
3806                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3807                 if (mask == IXGBE_4_BIT_MASK)
3808                         r = 0;
3809                 else
3810                         r = IXGBE_READ_REG(hw, reta_reg);
3811                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3812                         if (mask & (0x1 << j))
3813                                 reta |= reta_conf[idx].reta[shift + j] <<
3814                                                         (CHAR_BIT * j);
3815                         else
3816                                 reta |= r & (IXGBE_8_BIT_MASK <<
3817                                                 (CHAR_BIT * j));
3818                 }
3819                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3820         }
3821
3822         return 0;
3823 }
3824
3825 static int
3826 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3827                          struct rte_eth_rss_reta_entry64 *reta_conf,
3828                          uint16_t reta_size)
3829 {
3830         uint16_t i, sp_reta_size;
3831         uint8_t j, mask;
3832         uint32_t reta;
3833         uint16_t idx, shift;
3834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3835         uint32_t reta_reg;
3836
3837         PMD_INIT_FUNC_TRACE();
3838         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3839         if (reta_size != sp_reta_size) {
3840                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3841                         "(%d) doesn't match the number hardware can supported "
3842                         "(%d)\n", reta_size, sp_reta_size);
3843                 return -EINVAL;
3844         }
3845
3846         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3847                 idx = i / RTE_RETA_GROUP_SIZE;
3848                 shift = i % RTE_RETA_GROUP_SIZE;
3849                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3850                                                 IXGBE_4_BIT_MASK);
3851                 if (!mask)
3852                         continue;
3853
3854                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3855                 reta = IXGBE_READ_REG(hw, reta_reg);
3856                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3857                         if (mask & (0x1 << j))
3858                                 reta_conf[idx].reta[shift + j] =
3859                                         ((reta >> (CHAR_BIT * j)) &
3860                                                 IXGBE_8_BIT_MASK);
3861                 }
3862         }
3863
3864         return 0;
3865 }
3866
3867 static void
3868 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3869                                 uint32_t index, uint32_t pool)
3870 {
3871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3872         uint32_t enable_addr = 1;
3873
3874         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3875 }
3876
3877 static void
3878 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3879 {
3880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3881
3882         ixgbe_clear_rar(hw, index);
3883 }
3884
3885 static void
3886 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3887 {
3888         ixgbe_remove_rar(dev, 0);
3889
3890         ixgbe_add_rar(dev, addr, 0, 0);
3891 }
3892
3893 static int
3894 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3895 {
3896         uint32_t hlreg0;
3897         uint32_t maxfrs;
3898         struct ixgbe_hw *hw;
3899         struct rte_eth_dev_info dev_info;
3900         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3901
3902         ixgbe_dev_info_get(dev, &dev_info);
3903
3904         /* check that mtu is within the allowed range */
3905         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3906                 return -EINVAL;
3907
3908         /* refuse mtu that requires the support of scattered packets when this
3909          * feature has not been enabled before. */
3910         if (!dev->data->scattered_rx &&
3911             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3912              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3913                 return -EINVAL;
3914
3915         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3916         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3917
3918         /* switch to jumbo mode if needed */
3919         if (frame_size > ETHER_MAX_LEN) {
3920                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3921                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3922         } else {
3923                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3924                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3925         }
3926         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3927
3928         /* update max frame size */
3929         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3930
3931         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3932         maxfrs &= 0x0000FFFF;
3933         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3934         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3935
3936         return 0;
3937 }
3938
3939 /*
3940  * Virtual Function operations
3941  */
3942 static void
3943 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3944 {
3945         PMD_INIT_FUNC_TRACE();
3946
3947         /* Clear interrupt mask to stop from interrupts being generated */
3948         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3949
3950         IXGBE_WRITE_FLUSH(hw);
3951 }
3952
3953 static void
3954 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3955 {
3956         PMD_INIT_FUNC_TRACE();
3957
3958         /* VF enable interrupt autoclean */
3959         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3960         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3961         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3962
3963         IXGBE_WRITE_FLUSH(hw);
3964 }
3965
3966 static int
3967 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3968 {
3969         struct rte_eth_conf* conf = &dev->data->dev_conf;
3970         struct ixgbe_adapter *adapter =
3971                         (struct ixgbe_adapter *)dev->data->dev_private;
3972
3973         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3974                      dev->data->port_id);
3975
3976         /*
3977          * VF has no ability to enable/disable HW CRC
3978          * Keep the persistent behavior the same as Host PF
3979          */
3980 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3981         if (!conf->rxmode.hw_strip_crc) {
3982                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3983                 conf->rxmode.hw_strip_crc = 1;
3984         }
3985 #else
3986         if (conf->rxmode.hw_strip_crc) {
3987                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3988                 conf->rxmode.hw_strip_crc = 0;
3989         }
3990 #endif
3991
3992         /*
3993          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3994          * allocation or vector Rx preconditions we will reset it.
3995          */
3996         adapter->rx_bulk_alloc_allowed = true;
3997         adapter->rx_vec_allowed = true;
3998
3999         return 0;
4000 }
4001
4002 static int
4003 ixgbevf_dev_start(struct rte_eth_dev *dev)
4004 {
4005         struct ixgbe_hw *hw =
4006                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4007         uint32_t intr_vector = 0;
4008         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4009
4010         int err, mask = 0;
4011
4012         PMD_INIT_FUNC_TRACE();
4013
4014         hw->mac.ops.reset_hw(hw);
4015         hw->mac.get_link_status = true;
4016
4017         /* negotiate mailbox API version to use with the PF. */
4018         ixgbevf_negotiate_api(hw);
4019
4020         ixgbevf_dev_tx_init(dev);
4021
4022         /* This can fail when allocating mbufs for descriptor rings */
4023         err = ixgbevf_dev_rx_init(dev);
4024         if (err) {
4025                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4026                 ixgbe_dev_clear_queues(dev);
4027                 return err;
4028         }
4029
4030         /* Set vfta */
4031         ixgbevf_set_vfta_all(dev,1);
4032
4033         /* Set HW strip */
4034         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
4035                 ETH_VLAN_EXTEND_MASK;
4036         ixgbevf_vlan_offload_set(dev, mask);
4037
4038         ixgbevf_dev_rxtx_start(dev);
4039
4040         /* check and configure queue intr-vector mapping */
4041         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4042                 intr_vector = dev->data->nb_rx_queues;
4043                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4044                         return -1;
4045         }
4046
4047         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4048                 intr_handle->intr_vec =
4049                         rte_zmalloc("intr_vec",
4050                                     dev->data->nb_rx_queues * sizeof(int), 0);
4051                 if (intr_handle->intr_vec == NULL) {
4052                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4053                                      " intr_vec\n", dev->data->nb_rx_queues);
4054                         return -ENOMEM;
4055                 }
4056         }
4057         ixgbevf_configure_msix(dev);
4058
4059         rte_intr_enable(intr_handle);
4060
4061         /* Re-enable interrupt for VF */
4062         ixgbevf_intr_enable(hw);
4063
4064         return 0;
4065 }
4066
4067 static void
4068 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4069 {
4070         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4071         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4072
4073         PMD_INIT_FUNC_TRACE();
4074
4075         hw->adapter_stopped = 1;
4076         ixgbe_stop_adapter(hw);
4077
4078         /*
4079           * Clear what we set, but we still keep shadow_vfta to
4080           * restore after device starts
4081           */
4082         ixgbevf_set_vfta_all(dev,0);
4083
4084         /* Clear stored conf */
4085         dev->data->scattered_rx = 0;
4086
4087         ixgbe_dev_clear_queues(dev);
4088
4089         /* Clean datapath event and queue/vec mapping */
4090         rte_intr_efd_disable(intr_handle);
4091         if (intr_handle->intr_vec != NULL) {
4092                 rte_free(intr_handle->intr_vec);
4093                 intr_handle->intr_vec = NULL;
4094         }
4095 }
4096
4097 static void
4098 ixgbevf_dev_close(struct rte_eth_dev *dev)
4099 {
4100         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4101
4102         PMD_INIT_FUNC_TRACE();
4103
4104         ixgbe_reset_hw(hw);
4105
4106         ixgbevf_dev_stop(dev);
4107
4108         ixgbe_dev_free_queues(dev);
4109
4110         /**
4111          * Remove the VF MAC address ro ensure
4112          * that the VF traffic goes to the PF
4113          * after stop, close and detach of the VF
4114          **/
4115         ixgbevf_remove_mac_addr(dev, 0);
4116 }
4117
4118 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4119 {
4120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4121         struct ixgbe_vfta * shadow_vfta =
4122                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4123         int i = 0, j = 0, vfta = 0, mask = 1;
4124
4125         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4126                 vfta = shadow_vfta->vfta[i];
4127                 if (vfta) {
4128                         mask = 1;
4129                         for (j = 0; j < 32; j++){
4130                                 if (vfta & mask)
4131                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4132                                 mask<<=1;
4133                         }
4134                 }
4135         }
4136
4137 }
4138
4139 static int
4140 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4141 {
4142         struct ixgbe_hw *hw =
4143                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4144         struct ixgbe_vfta * shadow_vfta =
4145                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4146         uint32_t vid_idx = 0;
4147         uint32_t vid_bit = 0;
4148         int ret = 0;
4149
4150         PMD_INIT_FUNC_TRACE();
4151
4152         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4153         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4154         if (ret) {
4155                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4156                 return ret;
4157         }
4158         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4159         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4160
4161         /* Save what we set and retore it after device reset */
4162         if (on)
4163                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4164         else
4165                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4166
4167         return 0;
4168 }
4169
4170 static void
4171 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4172 {
4173         struct ixgbe_hw *hw =
4174                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4175         uint32_t ctrl;
4176
4177         PMD_INIT_FUNC_TRACE();
4178
4179         if (queue >= hw->mac.max_rx_queues)
4180                 return;
4181
4182         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4183         if (on)
4184                 ctrl |= IXGBE_RXDCTL_VME;
4185         else
4186                 ctrl &= ~IXGBE_RXDCTL_VME;
4187         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4188
4189         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4190 }
4191
4192 static void
4193 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4194 {
4195         struct ixgbe_hw *hw =
4196                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4197         uint16_t i;
4198         int on = 0;
4199
4200         /* VF function only support hw strip feature, others are not support */
4201         if (mask & ETH_VLAN_STRIP_MASK) {
4202                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4203
4204                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4205                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4206         }
4207 }
4208
4209 static int
4210 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4211 {
4212         uint32_t reg_val;
4213
4214         /* we only need to do this if VMDq is enabled */
4215         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4216         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4217                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4218                 return -1;
4219         }
4220
4221         return 0;
4222 }
4223
4224 static uint32_t
4225 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4226 {
4227         uint32_t vector = 0;
4228         switch (hw->mac.mc_filter_type) {
4229         case 0:   /* use bits [47:36] of the address */
4230                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4231                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4232                 break;
4233         case 1:   /* use bits [46:35] of the address */
4234                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4235                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4236                 break;
4237         case 2:   /* use bits [45:34] of the address */
4238                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4239                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4240                 break;
4241         case 3:   /* use bits [43:32] of the address */
4242                 vector = ((uc_addr->addr_bytes[4]) |
4243                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4244                 break;
4245         default:  /* Invalid mc_filter_type */
4246                 break;
4247         }
4248
4249         /* vector can only be 12-bits or boundary will be exceeded */
4250         vector &= 0xFFF;
4251         return vector;
4252 }
4253
4254 static int
4255 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4256                                uint8_t on)
4257 {
4258         uint32_t vector;
4259         uint32_t uta_idx;
4260         uint32_t reg_val;
4261         uint32_t uta_shift;
4262         uint32_t rc;
4263         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4264         const uint32_t ixgbe_uta_bit_shift = 5;
4265         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4266         const uint32_t bit1 = 0x1;
4267
4268         struct ixgbe_hw *hw =
4269                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4270         struct ixgbe_uta_info *uta_info =
4271                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4272
4273         /* The UTA table only exists on 82599 hardware and newer */
4274         if (hw->mac.type < ixgbe_mac_82599EB)
4275                 return -ENOTSUP;
4276
4277         vector = ixgbe_uta_vector(hw,mac_addr);
4278         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4279         uta_shift = vector & ixgbe_uta_bit_mask;
4280
4281         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4282         if (rc == on)
4283                 return 0;
4284
4285         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4286         if (on) {
4287                 uta_info->uta_in_use++;
4288                 reg_val |= (bit1 << uta_shift);
4289                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4290         } else {
4291                 uta_info->uta_in_use--;
4292                 reg_val &= ~(bit1 << uta_shift);
4293                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4294         }
4295
4296         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4297
4298         if (uta_info->uta_in_use > 0)
4299                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4300                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4301         else
4302                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4303
4304         return 0;
4305 }
4306
4307 static int
4308 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4309 {
4310         int i;
4311         struct ixgbe_hw *hw =
4312                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4313         struct ixgbe_uta_info *uta_info =
4314                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4315
4316         /* The UTA table only exists on 82599 hardware and newer */
4317         if (hw->mac.type < ixgbe_mac_82599EB)
4318                 return -ENOTSUP;
4319
4320         if (on) {
4321                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4322                         uta_info->uta_shadow[i] = ~0;
4323                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4324                 }
4325         } else {
4326                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4327                         uta_info->uta_shadow[i] = 0;
4328                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4329                 }
4330         }
4331         return 0;
4332
4333 }
4334
4335 uint32_t
4336 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4337 {
4338         uint32_t new_val = orig_val;
4339
4340         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4341                 new_val |= IXGBE_VMOLR_AUPE;
4342         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4343                 new_val |= IXGBE_VMOLR_ROMPE;
4344         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4345                 new_val |= IXGBE_VMOLR_ROPE;
4346         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4347                 new_val |= IXGBE_VMOLR_BAM;
4348         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4349                 new_val |= IXGBE_VMOLR_MPE;
4350
4351         return new_val;
4352 }
4353
4354 static int
4355 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4356                                uint16_t rx_mask, uint8_t on)
4357 {
4358         int val = 0;
4359
4360         struct ixgbe_hw *hw =
4361                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4363
4364         if (hw->mac.type == ixgbe_mac_82598EB) {
4365                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4366                              " on 82599 hardware and newer");
4367                 return -ENOTSUP;
4368         }
4369         if (ixgbe_vmdq_mode_check(hw) < 0)
4370                 return -ENOTSUP;
4371
4372         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4373
4374         if (on)
4375                 vmolr |= val;
4376         else
4377                 vmolr &= ~val;
4378
4379         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4380
4381         return 0;
4382 }
4383
4384 static int
4385 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4386 {
4387         uint32_t reg,addr;
4388         uint32_t val;
4389         const uint8_t bit1 = 0x1;
4390
4391         struct ixgbe_hw *hw =
4392                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4393
4394         if (ixgbe_vmdq_mode_check(hw) < 0)
4395                 return -ENOTSUP;
4396
4397         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4398         reg = IXGBE_READ_REG(hw, addr);
4399         val = bit1 << pool;
4400
4401         if (on)
4402                 reg |= val;
4403         else
4404                 reg &= ~val;
4405
4406         IXGBE_WRITE_REG(hw, addr,reg);
4407
4408         return 0;
4409 }
4410
4411 static int
4412 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4413 {
4414         uint32_t reg,addr;
4415         uint32_t val;
4416         const uint8_t bit1 = 0x1;
4417
4418         struct ixgbe_hw *hw =
4419                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4420
4421         if (ixgbe_vmdq_mode_check(hw) < 0)
4422                 return -ENOTSUP;
4423
4424         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4425         reg = IXGBE_READ_REG(hw, addr);
4426         val = bit1 << pool;
4427
4428         if (on)
4429                 reg |= val;
4430         else
4431                 reg &= ~val;
4432
4433         IXGBE_WRITE_REG(hw, addr,reg);
4434
4435         return 0;
4436 }
4437
4438 static int
4439 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4440                         uint64_t pool_mask, uint8_t vlan_on)
4441 {
4442         int ret = 0;
4443         uint16_t pool_idx;
4444         struct ixgbe_hw *hw =
4445                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4446
4447         if (ixgbe_vmdq_mode_check(hw) < 0)
4448                 return -ENOTSUP;
4449         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4450                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4451                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4452                         if (ret < 0)
4453                                 return ret;
4454         }
4455
4456         return ret;
4457 }
4458
4459 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4460 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4461 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4462 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4463 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4464         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4465         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4466
4467 static int
4468 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4469                         struct rte_eth_mirror_conf *mirror_conf,
4470                         uint8_t rule_id, uint8_t on)
4471 {
4472         uint32_t mr_ctl,vlvf;
4473         uint32_t mp_lsb = 0;
4474         uint32_t mv_msb = 0;
4475         uint32_t mv_lsb = 0;
4476         uint32_t mp_msb = 0;
4477         uint8_t i = 0;
4478         int reg_index = 0;
4479         uint64_t vlan_mask = 0;
4480
4481         const uint8_t pool_mask_offset = 32;
4482         const uint8_t vlan_mask_offset = 32;
4483         const uint8_t dst_pool_offset = 8;
4484         const uint8_t rule_mr_offset  = 4;
4485         const uint8_t mirror_rule_mask= 0x0F;
4486
4487         struct ixgbe_mirror_info *mr_info =
4488                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4489         struct ixgbe_hw *hw =
4490                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4491         uint8_t mirror_type = 0;
4492
4493         if (ixgbe_vmdq_mode_check(hw) < 0)
4494                 return -ENOTSUP;
4495
4496         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4497                 return -EINVAL;
4498
4499         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4500                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4501                         mirror_conf->rule_type);
4502                 return -EINVAL;
4503         }
4504
4505         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4506                 mirror_type |= IXGBE_MRCTL_VLME;
4507                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4508                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4509                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4510                                 /* search vlan id related pool vlan filter index */
4511                                 reg_index = ixgbe_find_vlvf_slot(hw,
4512                                                 mirror_conf->vlan.vlan_id[i]);
4513                                 if (reg_index < 0)
4514                                         return -EINVAL;
4515                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4516                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4517                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4518                                       mirror_conf->vlan.vlan_id[i]))
4519                                         vlan_mask |= (1ULL << reg_index);
4520                                 else
4521                                         return -EINVAL;
4522                         }
4523                 }
4524
4525                 if (on) {
4526                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4527                         mv_msb = vlan_mask >> vlan_mask_offset;
4528
4529                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4530                                                 mirror_conf->vlan.vlan_mask;
4531                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4532                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4533                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4534                                                 mirror_conf->vlan.vlan_id[i];
4535                         }
4536                 } else {
4537                         mv_lsb = 0;
4538                         mv_msb = 0;
4539                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4540                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4541                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4542                 }
4543         }
4544
4545         /*
4546          * if enable pool mirror, write related pool mask register,if disable
4547          * pool mirror, clear PFMRVM register
4548          */
4549         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4550                 mirror_type |= IXGBE_MRCTL_VPME;
4551                 if (on) {
4552                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4553                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4554                         mr_info->mr_conf[rule_id].pool_mask =
4555                                         mirror_conf->pool_mask;
4556
4557                 } else {
4558                         mp_lsb = 0;
4559                         mp_msb = 0;
4560                         mr_info->mr_conf[rule_id].pool_mask = 0;
4561                 }
4562         }
4563         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4564                 mirror_type |= IXGBE_MRCTL_UPME;
4565         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4566                 mirror_type |= IXGBE_MRCTL_DPME;
4567
4568         /* read  mirror control register and recalculate it */
4569         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4570
4571         if (on) {
4572                 mr_ctl |= mirror_type;
4573                 mr_ctl &= mirror_rule_mask;
4574                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4575         } else
4576                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4577
4578         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4579         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4580
4581         /* write mirrror control  register */
4582         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4583
4584         /* write pool mirrror control  register */
4585         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4586                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4587                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4588                                 mp_msb);
4589         }
4590         /* write VLAN mirrror control  register */
4591         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4592                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4593                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4594                                 mv_msb);
4595         }
4596
4597         return 0;
4598 }
4599
4600 static int
4601 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4602 {
4603         int mr_ctl = 0;
4604         uint32_t lsb_val = 0;
4605         uint32_t msb_val = 0;
4606         const uint8_t rule_mr_offset = 4;
4607
4608         struct ixgbe_hw *hw =
4609                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4610         struct ixgbe_mirror_info *mr_info =
4611                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4612
4613         if (ixgbe_vmdq_mode_check(hw) < 0)
4614                 return -ENOTSUP;
4615
4616         memset(&mr_info->mr_conf[rule_id], 0,
4617                 sizeof(struct rte_eth_mirror_conf));
4618
4619         /* clear PFVMCTL register */
4620         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4621
4622         /* clear pool mask register */
4623         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4624         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4625
4626         /* clear vlan mask register */
4627         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4628         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4629
4630         return 0;
4631 }
4632
4633 static int
4634 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4635 {
4636         uint32_t mask;
4637         struct ixgbe_hw *hw =
4638                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4639
4640         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4641         mask |= (1 << IXGBE_MISC_VEC_ID);
4642         RTE_SET_USED(queue_id);
4643         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4644
4645         rte_intr_enable(&dev->pci_dev->intr_handle);
4646
4647         return 0;
4648 }
4649
4650 static int
4651 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4652 {
4653         uint32_t mask;
4654         struct ixgbe_hw *hw =
4655                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4656
4657         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4658         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4659         RTE_SET_USED(queue_id);
4660         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4661
4662         return 0;
4663 }
4664
4665 static int
4666 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4667 {
4668         uint32_t mask;
4669         struct ixgbe_hw *hw =
4670                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4671         struct ixgbe_interrupt *intr =
4672                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4673
4674         if (queue_id < 16) {
4675                 ixgbe_disable_intr(hw);
4676                 intr->mask |= (1 << queue_id);
4677                 ixgbe_enable_intr(dev);
4678         } else if (queue_id < 32) {
4679                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4680                 mask &= (1 << queue_id);
4681                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4682         } else if (queue_id < 64) {
4683                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4684                 mask &= (1 << (queue_id - 32));
4685                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4686         }
4687         rte_intr_enable(&dev->pci_dev->intr_handle);
4688
4689         return 0;
4690 }
4691
4692 static int
4693 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4694 {
4695         uint32_t mask;
4696         struct ixgbe_hw *hw =
4697                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4698         struct ixgbe_interrupt *intr =
4699                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4700
4701         if (queue_id < 16) {
4702                 ixgbe_disable_intr(hw);
4703                 intr->mask &= ~(1 << queue_id);
4704                 ixgbe_enable_intr(dev);
4705         } else if (queue_id < 32) {
4706                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4707                 mask &= ~(1 << queue_id);
4708                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4709         } else if (queue_id < 64) {
4710                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4711                 mask &= ~(1 << (queue_id - 32));
4712                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4713         }
4714
4715         return 0;
4716 }
4717
4718 static void
4719 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4720                      uint8_t queue, uint8_t msix_vector)
4721 {
4722         uint32_t tmp, idx;
4723
4724         if (direction == -1) {
4725                 /* other causes */
4726                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4727                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4728                 tmp &= ~0xFF;
4729                 tmp |= msix_vector;
4730                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4731         } else {
4732                 /* rx or tx cause */
4733                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4734                 idx = ((16 * (queue & 1)) + (8 * direction));
4735                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4736                 tmp &= ~(0xFF << idx);
4737                 tmp |= (msix_vector << idx);
4738                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4739         }
4740 }
4741
4742 /**
4743  * set the IVAR registers, mapping interrupt causes to vectors
4744  * @param hw
4745  *  pointer to ixgbe_hw struct
4746  * @direction
4747  *  0 for Rx, 1 for Tx, -1 for other causes
4748  * @queue
4749  *  queue to map the corresponding interrupt to
4750  * @msix_vector
4751  *  the vector to map to the corresponding queue
4752  */
4753 static void
4754 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4755                    uint8_t queue, uint8_t msix_vector)
4756 {
4757         uint32_t tmp, idx;
4758
4759         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4760         if (hw->mac.type == ixgbe_mac_82598EB) {
4761                 if (direction == -1)
4762                         direction = 0;
4763                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4764                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4765                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4766                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4767                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4768         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4769                         (hw->mac.type == ixgbe_mac_X540)) {
4770                 if (direction == -1) {
4771                         /* other causes */
4772                         idx = ((queue & 1) * 8);
4773                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4774                         tmp &= ~(0xFF << idx);
4775                         tmp |= (msix_vector << idx);
4776                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4777                 } else {
4778                         /* rx or tx causes */
4779                         idx = ((16 * (queue & 1)) + (8 * direction));
4780                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4781                         tmp &= ~(0xFF << idx);
4782                         tmp |= (msix_vector << idx);
4783                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4784                 }
4785         }
4786 }
4787
4788 static void
4789 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4790 {
4791         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4792         struct ixgbe_hw *hw =
4793                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4794         uint32_t q_idx;
4795         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4796
4797         /* won't configure msix register if no mapping is done
4798          * between intr vector and event fd.
4799          */
4800         if (!rte_intr_dp_is_en(intr_handle))
4801                 return;
4802
4803         /* Configure all RX queues of VF */
4804         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4805                 /* Force all queue use vector 0,
4806                  * as IXGBE_VF_MAXMSIVECOTR = 1
4807                  */
4808                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4809                 intr_handle->intr_vec[q_idx] = vector_idx;
4810         }
4811
4812         /* Configure VF other cause ivar */
4813         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4814 }
4815
4816 /**
4817  * Sets up the hardware to properly generate MSI-X interrupts
4818  * @hw
4819  *  board private structure
4820  */
4821 static void
4822 ixgbe_configure_msix(struct rte_eth_dev *dev)
4823 {
4824         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4825         struct ixgbe_hw *hw =
4826                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4827         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4828         uint32_t vec = IXGBE_MISC_VEC_ID;
4829         uint32_t mask;
4830         uint32_t gpie;
4831
4832         /* won't configure msix register if no mapping is done
4833          * between intr vector and event fd
4834          */
4835         if (!rte_intr_dp_is_en(intr_handle))
4836                 return;
4837
4838         if (rte_intr_allow_others(intr_handle))
4839                 vec = base = IXGBE_RX_VEC_START;
4840
4841         /* setup GPIE for MSI-x mode */
4842         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4843         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4844                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4845         /* auto clearing and auto setting corresponding bits in EIMS
4846          * when MSI-X interrupt is triggered
4847          */
4848         if (hw->mac.type == ixgbe_mac_82598EB) {
4849                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4850         } else {
4851                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4852                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4853         }
4854         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4855
4856         /* Populate the IVAR table and set the ITR values to the
4857          * corresponding register.
4858          */
4859         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4860              queue_id++) {
4861                 /* by default, 1:1 mapping */
4862                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4863                 intr_handle->intr_vec[queue_id] = vec;
4864                 if (vec < base + intr_handle->nb_efd - 1)
4865                         vec++;
4866         }
4867
4868         switch (hw->mac.type) {
4869         case ixgbe_mac_82598EB:
4870                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4871                                    IXGBE_MISC_VEC_ID);
4872                 break;
4873         case ixgbe_mac_82599EB:
4874         case ixgbe_mac_X540:
4875                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4876                 break;
4877         default:
4878                 break;
4879         }
4880         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4881                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4882
4883         /* set up to autoclear timer, and the vectors */
4884         mask = IXGBE_EIMS_ENABLE_MASK;
4885         mask &= ~(IXGBE_EIMS_OTHER |
4886                   IXGBE_EIMS_MAILBOX |
4887                   IXGBE_EIMS_LSC);
4888
4889         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4890 }
4891
4892 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4893         uint16_t queue_idx, uint16_t tx_rate)
4894 {
4895         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4896         uint32_t rf_dec, rf_int;
4897         uint32_t bcnrc_val;
4898         uint16_t link_speed = dev->data->dev_link.link_speed;
4899
4900         if (queue_idx >= hw->mac.max_tx_queues)
4901                 return -EINVAL;
4902
4903         if (tx_rate != 0) {
4904                 /* Calculate the rate factor values to set */
4905                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4906                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4907                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4908
4909                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4910                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4911                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4912                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4913         } else {
4914                 bcnrc_val = 0;
4915         }
4916
4917         /*
4918          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4919          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4920          * set as 0x4.
4921          */
4922         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4923                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4924                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4925                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4926                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4927         else
4928                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4929                         IXGBE_MMW_SIZE_DEFAULT);
4930
4931         /* Set RTTBCNRC of queue X */
4932         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4933         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4934         IXGBE_WRITE_FLUSH(hw);
4935
4936         return 0;
4937 }
4938
4939 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4940         uint16_t tx_rate, uint64_t q_msk)
4941 {
4942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4943         struct ixgbe_vf_info *vfinfo =
4944                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4945         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4946         uint32_t queue_stride =
4947                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4948         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4949         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4950         uint16_t total_rate = 0;
4951
4952         if (queue_end >= hw->mac.max_tx_queues)
4953                 return -EINVAL;
4954
4955         if (vfinfo != NULL) {
4956                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4957                         if (vf_idx == vf)
4958                                 continue;
4959                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4960                                 idx++)
4961                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4962                 }
4963         } else
4964                 return -EINVAL;
4965
4966         /* Store tx_rate for this vf. */
4967         for (idx = 0; idx < nb_q_per_pool; idx++) {
4968                 if (((uint64_t)0x1 << idx) & q_msk) {
4969                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4970                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4971                         total_rate += tx_rate;
4972                 }
4973         }
4974
4975         if (total_rate > dev->data->dev_link.link_speed) {
4976                 /*
4977                  * Reset stored TX rate of the VF if it causes exceed
4978                  * link speed.
4979                  */
4980                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4981                 return -EINVAL;
4982         }
4983
4984         /* Set RTTBCNRC of each queue/pool for vf X  */
4985         for (; queue_idx <= queue_end; queue_idx++) {
4986                 if (0x1 & q_msk)
4987                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4988                 q_msk = q_msk >> 1;
4989         }
4990
4991         return 0;
4992 }
4993
4994 static void
4995 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4996                      __attribute__((unused)) uint32_t index,
4997                      __attribute__((unused)) uint32_t pool)
4998 {
4999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5000         int diag;
5001
5002         /*
5003          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5004          * operation. Trap this case to avoid exhausting the [very limited]
5005          * set of PF resources used to store VF MAC addresses.
5006          */
5007         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5008                 return;
5009         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5010         if (diag == 0)
5011                 return;
5012         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5013 }
5014
5015 static void
5016 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5017 {
5018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5019         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5020         struct ether_addr *mac_addr;
5021         uint32_t i;
5022         int diag;
5023
5024         /*
5025          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5026          * not support the deletion of a given MAC address.
5027          * Instead, it imposes to delete all MAC addresses, then to add again
5028          * all MAC addresses with the exception of the one to be deleted.
5029          */
5030         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5031
5032         /*
5033          * Add again all MAC addresses, with the exception of the deleted one
5034          * and of the permanent MAC address.
5035          */
5036         for (i = 0, mac_addr = dev->data->mac_addrs;
5037              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5038                 /* Skip the deleted MAC address */
5039                 if (i == index)
5040                         continue;
5041                 /* Skip NULL MAC addresses */
5042                 if (is_zero_ether_addr(mac_addr))
5043                         continue;
5044                 /* Skip the permanent MAC address */
5045                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5046                         continue;
5047                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5048                 if (diag != 0)
5049                         PMD_DRV_LOG(ERR,
5050                                     "Adding again MAC address "
5051                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5052                                     "diag=%d",
5053                                     mac_addr->addr_bytes[0],
5054                                     mac_addr->addr_bytes[1],
5055                                     mac_addr->addr_bytes[2],
5056                                     mac_addr->addr_bytes[3],
5057                                     mac_addr->addr_bytes[4],
5058                                     mac_addr->addr_bytes[5],
5059                                     diag);
5060         }
5061 }
5062
5063 static void
5064 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5065 {
5066         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5067
5068         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5069 }
5070
5071 #define MAC_TYPE_FILTER_SUP(type)    do {\
5072         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5073                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5074                 (type) != ixgbe_mac_X550EM_a)\
5075                 return -ENOTSUP;\
5076 } while (0)
5077
5078 static int
5079 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5080                         struct rte_eth_syn_filter *filter,
5081                         bool add)
5082 {
5083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084         uint32_t synqf;
5085
5086         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5087                 return -EINVAL;
5088
5089         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5090
5091         if (add) {
5092                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5093                         return -EINVAL;
5094                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5095                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5096
5097                 if (filter->hig_pri)
5098                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5099                 else
5100                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5101         } else {
5102                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5103                         return -ENOENT;
5104                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5105         }
5106         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5107         IXGBE_WRITE_FLUSH(hw);
5108         return 0;
5109 }
5110
5111 static int
5112 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5113                         struct rte_eth_syn_filter *filter)
5114 {
5115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5116         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5117
5118         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5119                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5120                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5121                 return 0;
5122         }
5123         return -ENOENT;
5124 }
5125
5126 static int
5127 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5128                         enum rte_filter_op filter_op,
5129                         void *arg)
5130 {
5131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5132         int ret;
5133
5134         MAC_TYPE_FILTER_SUP(hw->mac.type);
5135
5136         if (filter_op == RTE_ETH_FILTER_NOP)
5137                 return 0;
5138
5139         if (arg == NULL) {
5140                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5141                             filter_op);
5142                 return -EINVAL;
5143         }
5144
5145         switch (filter_op) {
5146         case RTE_ETH_FILTER_ADD:
5147                 ret = ixgbe_syn_filter_set(dev,
5148                                 (struct rte_eth_syn_filter *)arg,
5149                                 TRUE);
5150                 break;
5151         case RTE_ETH_FILTER_DELETE:
5152                 ret = ixgbe_syn_filter_set(dev,
5153                                 (struct rte_eth_syn_filter *)arg,
5154                                 FALSE);
5155                 break;
5156         case RTE_ETH_FILTER_GET:
5157                 ret = ixgbe_syn_filter_get(dev,
5158                                 (struct rte_eth_syn_filter *)arg);
5159                 break;
5160         default:
5161                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5162                 ret = -EINVAL;
5163                 break;
5164         }
5165
5166         return ret;
5167 }
5168
5169
5170 static inline enum ixgbe_5tuple_protocol
5171 convert_protocol_type(uint8_t protocol_value)
5172 {
5173         if (protocol_value == IPPROTO_TCP)
5174                 return IXGBE_FILTER_PROTOCOL_TCP;
5175         else if (protocol_value == IPPROTO_UDP)
5176                 return IXGBE_FILTER_PROTOCOL_UDP;
5177         else if (protocol_value == IPPROTO_SCTP)
5178                 return IXGBE_FILTER_PROTOCOL_SCTP;
5179         else
5180                 return IXGBE_FILTER_PROTOCOL_NONE;
5181 }
5182
5183 /*
5184  * add a 5tuple filter
5185  *
5186  * @param
5187  * dev: Pointer to struct rte_eth_dev.
5188  * index: the index the filter allocates.
5189  * filter: ponter to the filter that will be added.
5190  * rx_queue: the queue id the filter assigned to.
5191  *
5192  * @return
5193  *    - On success, zero.
5194  *    - On failure, a negative value.
5195  */
5196 static int
5197 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5198                         struct ixgbe_5tuple_filter *filter)
5199 {
5200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201         struct ixgbe_filter_info *filter_info =
5202                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5203         int i, idx, shift;
5204         uint32_t ftqf, sdpqf;
5205         uint32_t l34timir = 0;
5206         uint8_t mask = 0xff;
5207
5208         /*
5209          * look for an unused 5tuple filter index,
5210          * and insert the filter to list.
5211          */
5212         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5213                 idx = i / (sizeof(uint32_t) * NBBY);
5214                 shift = i % (sizeof(uint32_t) * NBBY);
5215                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5216                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5217                         filter->index = i;
5218                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5219                                           filter,
5220                                           entries);
5221                         break;
5222                 }
5223         }
5224         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5225                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5226                 return -ENOSYS;
5227         }
5228
5229         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5230                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5231         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5232
5233         ftqf = (uint32_t)(filter->filter_info.proto &
5234                 IXGBE_FTQF_PROTOCOL_MASK);
5235         ftqf |= (uint32_t)((filter->filter_info.priority &
5236                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5237         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5238                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5239         if (filter->filter_info.dst_ip_mask == 0)
5240                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5241         if (filter->filter_info.src_port_mask == 0)
5242                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5243         if (filter->filter_info.dst_port_mask == 0)
5244                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5245         if (filter->filter_info.proto_mask == 0)
5246                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5247         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5248         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5249         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5250
5251         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5252         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5253         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5254         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5255
5256         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5257         l34timir |= (uint32_t)(filter->queue <<
5258                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5259         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5260         return 0;
5261 }
5262
5263 /*
5264  * remove a 5tuple filter
5265  *
5266  * @param
5267  * dev: Pointer to struct rte_eth_dev.
5268  * filter: the pointer of the filter will be removed.
5269  */
5270 static void
5271 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5272                         struct ixgbe_5tuple_filter *filter)
5273 {
5274         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5275         struct ixgbe_filter_info *filter_info =
5276                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5277         uint16_t index = filter->index;
5278
5279         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5280                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5281         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5282         rte_free(filter);
5283
5284         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5285         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5286         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5287         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5288         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5289 }
5290
5291 static int
5292 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5293 {
5294         struct ixgbe_hw *hw;
5295         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5296
5297         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5298
5299         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5300                 return -EINVAL;
5301
5302         /* refuse mtu that requires the support of scattered packets when this
5303          * feature has not been enabled before. */
5304         if (!dev->data->scattered_rx &&
5305             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5306              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5307                 return -EINVAL;
5308
5309         /*
5310          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5311          * request of the version 2.0 of the mailbox API.
5312          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5313          * of the mailbox API.
5314          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5315          * prior to 3.11.33 which contains the following change:
5316          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5317          */
5318         ixgbevf_rlpml_set_vf(hw, max_frame);
5319
5320         /* update max frame size */
5321         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5322         return 0;
5323 }
5324
5325 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5326         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5327                 return -ENOTSUP;\
5328 } while (0)
5329
5330 static inline struct ixgbe_5tuple_filter *
5331 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5332                         struct ixgbe_5tuple_filter_info *key)
5333 {
5334         struct ixgbe_5tuple_filter *it;
5335
5336         TAILQ_FOREACH(it, filter_list, entries) {
5337                 if (memcmp(key, &it->filter_info,
5338                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5339                         return it;
5340                 }
5341         }
5342         return NULL;
5343 }
5344
5345 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5346 static inline int
5347 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5348                         struct ixgbe_5tuple_filter_info *filter_info)
5349 {
5350         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5351                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5352                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5353                 return -EINVAL;
5354
5355         switch (filter->dst_ip_mask) {
5356         case UINT32_MAX:
5357                 filter_info->dst_ip_mask = 0;
5358                 filter_info->dst_ip = filter->dst_ip;
5359                 break;
5360         case 0:
5361                 filter_info->dst_ip_mask = 1;
5362                 break;
5363         default:
5364                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5365                 return -EINVAL;
5366         }
5367
5368         switch (filter->src_ip_mask) {
5369         case UINT32_MAX:
5370                 filter_info->src_ip_mask = 0;
5371                 filter_info->src_ip = filter->src_ip;
5372                 break;
5373         case 0:
5374                 filter_info->src_ip_mask = 1;
5375                 break;
5376         default:
5377                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5378                 return -EINVAL;
5379         }
5380
5381         switch (filter->dst_port_mask) {
5382         case UINT16_MAX:
5383                 filter_info->dst_port_mask = 0;
5384                 filter_info->dst_port = filter->dst_port;
5385                 break;
5386         case 0:
5387                 filter_info->dst_port_mask = 1;
5388                 break;
5389         default:
5390                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5391                 return -EINVAL;
5392         }
5393
5394         switch (filter->src_port_mask) {
5395         case UINT16_MAX:
5396                 filter_info->src_port_mask = 0;
5397                 filter_info->src_port = filter->src_port;
5398                 break;
5399         case 0:
5400                 filter_info->src_port_mask = 1;
5401                 break;
5402         default:
5403                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5404                 return -EINVAL;
5405         }
5406
5407         switch (filter->proto_mask) {
5408         case UINT8_MAX:
5409                 filter_info->proto_mask = 0;
5410                 filter_info->proto =
5411                         convert_protocol_type(filter->proto);
5412                 break;
5413         case 0:
5414                 filter_info->proto_mask = 1;
5415                 break;
5416         default:
5417                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5418                 return -EINVAL;
5419         }
5420
5421         filter_info->priority = (uint8_t)filter->priority;
5422         return 0;
5423 }
5424
5425 /*
5426  * add or delete a ntuple filter
5427  *
5428  * @param
5429  * dev: Pointer to struct rte_eth_dev.
5430  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5431  * add: if true, add filter, if false, remove filter
5432  *
5433  * @return
5434  *    - On success, zero.
5435  *    - On failure, a negative value.
5436  */
5437 static int
5438 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5439                         struct rte_eth_ntuple_filter *ntuple_filter,
5440                         bool add)
5441 {
5442         struct ixgbe_filter_info *filter_info =
5443                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5444         struct ixgbe_5tuple_filter_info filter_5tuple;
5445         struct ixgbe_5tuple_filter *filter;
5446         int ret;
5447
5448         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5449                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5450                 return -EINVAL;
5451         }
5452
5453         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5454         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5455         if (ret < 0)
5456                 return ret;
5457
5458         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5459                                          &filter_5tuple);
5460         if (filter != NULL && add) {
5461                 PMD_DRV_LOG(ERR, "filter exists.");
5462                 return -EEXIST;
5463         }
5464         if (filter == NULL && !add) {
5465                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5466                 return -ENOENT;
5467         }
5468
5469         if (add) {
5470                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5471                                 sizeof(struct ixgbe_5tuple_filter), 0);
5472                 if (filter == NULL)
5473                         return -ENOMEM;
5474                 (void)rte_memcpy(&filter->filter_info,
5475                                  &filter_5tuple,
5476                                  sizeof(struct ixgbe_5tuple_filter_info));
5477                 filter->queue = ntuple_filter->queue;
5478                 ret = ixgbe_add_5tuple_filter(dev, filter);
5479                 if (ret < 0) {
5480                         rte_free(filter);
5481                         return ret;
5482                 }
5483         } else
5484                 ixgbe_remove_5tuple_filter(dev, filter);
5485
5486         return 0;
5487 }
5488
5489 /*
5490  * get a ntuple filter
5491  *
5492  * @param
5493  * dev: Pointer to struct rte_eth_dev.
5494  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5495  *
5496  * @return
5497  *    - On success, zero.
5498  *    - On failure, a negative value.
5499  */
5500 static int
5501 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5502                         struct rte_eth_ntuple_filter *ntuple_filter)
5503 {
5504         struct ixgbe_filter_info *filter_info =
5505                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5506         struct ixgbe_5tuple_filter_info filter_5tuple;
5507         struct ixgbe_5tuple_filter *filter;
5508         int ret;
5509
5510         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5511                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5512                 return -EINVAL;
5513         }
5514
5515         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5516         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5517         if (ret < 0)
5518                 return ret;
5519
5520         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5521                                          &filter_5tuple);
5522         if (filter == NULL) {
5523                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5524                 return -ENOENT;
5525         }
5526         ntuple_filter->queue = filter->queue;
5527         return 0;
5528 }
5529
5530 /*
5531  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5532  * @dev: pointer to rte_eth_dev structure
5533  * @filter_op:operation will be taken.
5534  * @arg: a pointer to specific structure corresponding to the filter_op
5535  *
5536  * @return
5537  *    - On success, zero.
5538  *    - On failure, a negative value.
5539  */
5540 static int
5541 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5542                                 enum rte_filter_op filter_op,
5543                                 void *arg)
5544 {
5545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5546         int ret;
5547
5548         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5549
5550         if (filter_op == RTE_ETH_FILTER_NOP)
5551                 return 0;
5552
5553         if (arg == NULL) {
5554                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5555                             filter_op);
5556                 return -EINVAL;
5557         }
5558
5559         switch (filter_op) {
5560         case RTE_ETH_FILTER_ADD:
5561                 ret = ixgbe_add_del_ntuple_filter(dev,
5562                         (struct rte_eth_ntuple_filter *)arg,
5563                         TRUE);
5564                 break;
5565         case RTE_ETH_FILTER_DELETE:
5566                 ret = ixgbe_add_del_ntuple_filter(dev,
5567                         (struct rte_eth_ntuple_filter *)arg,
5568                         FALSE);
5569                 break;
5570         case RTE_ETH_FILTER_GET:
5571                 ret = ixgbe_get_ntuple_filter(dev,
5572                         (struct rte_eth_ntuple_filter *)arg);
5573                 break;
5574         default:
5575                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5576                 ret = -EINVAL;
5577                 break;
5578         }
5579         return ret;
5580 }
5581
5582 static inline int
5583 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5584                         uint16_t ethertype)
5585 {
5586         int i;
5587
5588         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5589                 if (filter_info->ethertype_filters[i] == ethertype &&
5590                     (filter_info->ethertype_mask & (1 << i)))
5591                         return i;
5592         }
5593         return -1;
5594 }
5595
5596 static inline int
5597 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5598                         uint16_t ethertype)
5599 {
5600         int i;
5601
5602         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5603                 if (!(filter_info->ethertype_mask & (1 << i))) {
5604                         filter_info->ethertype_mask |= 1 << i;
5605                         filter_info->ethertype_filters[i] = ethertype;
5606                         return i;
5607                 }
5608         }
5609         return -1;
5610 }
5611
5612 static inline int
5613 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5614                         uint8_t idx)
5615 {
5616         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5617                 return -1;
5618         filter_info->ethertype_mask &= ~(1 << idx);
5619         filter_info->ethertype_filters[idx] = 0;
5620         return idx;
5621 }
5622
5623 static int
5624 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5625                         struct rte_eth_ethertype_filter *filter,
5626                         bool add)
5627 {
5628         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5629         struct ixgbe_filter_info *filter_info =
5630                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5631         uint32_t etqf = 0;
5632         uint32_t etqs = 0;
5633         int ret;
5634
5635         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5636                 return -EINVAL;
5637
5638         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5639                 filter->ether_type == ETHER_TYPE_IPv6) {
5640                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5641                         " ethertype filter.", filter->ether_type);
5642                 return -EINVAL;
5643         }
5644
5645         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5646                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5647                 return -EINVAL;
5648         }
5649         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5650                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5651                 return -EINVAL;
5652         }
5653
5654         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5655         if (ret >= 0 && add) {
5656                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5657                             filter->ether_type);
5658                 return -EEXIST;
5659         }
5660         if (ret < 0 && !add) {
5661                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5662                             filter->ether_type);
5663                 return -ENOENT;
5664         }
5665
5666         if (add) {
5667                 ret = ixgbe_ethertype_filter_insert(filter_info,
5668                         filter->ether_type);
5669                 if (ret < 0) {
5670                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5671                         return -ENOSYS;
5672                 }
5673                 etqf = IXGBE_ETQF_FILTER_EN;
5674                 etqf |= (uint32_t)filter->ether_type;
5675                 etqs |= (uint32_t)((filter->queue <<
5676                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5677                                     IXGBE_ETQS_RX_QUEUE);
5678                 etqs |= IXGBE_ETQS_QUEUE_EN;
5679         } else {
5680                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5681                 if (ret < 0)
5682                         return -ENOSYS;
5683         }
5684         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5685         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5686         IXGBE_WRITE_FLUSH(hw);
5687
5688         return 0;
5689 }
5690
5691 static int
5692 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5693                         struct rte_eth_ethertype_filter *filter)
5694 {
5695         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5696         struct ixgbe_filter_info *filter_info =
5697                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5698         uint32_t etqf, etqs;
5699         int ret;
5700
5701         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5702         if (ret < 0) {
5703                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5704                             filter->ether_type);
5705                 return -ENOENT;
5706         }
5707
5708         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5709         if (etqf & IXGBE_ETQF_FILTER_EN) {
5710                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5711                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5712                 filter->flags = 0;
5713                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5714                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5715                 return 0;
5716         }
5717         return -ENOENT;
5718 }
5719
5720 /*
5721  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5722  * @dev: pointer to rte_eth_dev structure
5723  * @filter_op:operation will be taken.
5724  * @arg: a pointer to specific structure corresponding to the filter_op
5725  */
5726 static int
5727 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5728                                 enum rte_filter_op filter_op,
5729                                 void *arg)
5730 {
5731         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5732         int ret;
5733
5734         MAC_TYPE_FILTER_SUP(hw->mac.type);
5735
5736         if (filter_op == RTE_ETH_FILTER_NOP)
5737                 return 0;
5738
5739         if (arg == NULL) {
5740                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5741                             filter_op);
5742                 return -EINVAL;
5743         }
5744
5745         switch (filter_op) {
5746         case RTE_ETH_FILTER_ADD:
5747                 ret = ixgbe_add_del_ethertype_filter(dev,
5748                         (struct rte_eth_ethertype_filter *)arg,
5749                         TRUE);
5750                 break;
5751         case RTE_ETH_FILTER_DELETE:
5752                 ret = ixgbe_add_del_ethertype_filter(dev,
5753                         (struct rte_eth_ethertype_filter *)arg,
5754                         FALSE);
5755                 break;
5756         case RTE_ETH_FILTER_GET:
5757                 ret = ixgbe_get_ethertype_filter(dev,
5758                         (struct rte_eth_ethertype_filter *)arg);
5759                 break;
5760         default:
5761                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5762                 ret = -EINVAL;
5763                 break;
5764         }
5765         return ret;
5766 }
5767
5768 static int
5769 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5770                      enum rte_filter_type filter_type,
5771                      enum rte_filter_op filter_op,
5772                      void *arg)
5773 {
5774         int ret = -EINVAL;
5775
5776         switch (filter_type) {
5777         case RTE_ETH_FILTER_NTUPLE:
5778                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5779                 break;
5780         case RTE_ETH_FILTER_ETHERTYPE:
5781                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5782                 break;
5783         case RTE_ETH_FILTER_SYN:
5784                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5785                 break;
5786         case RTE_ETH_FILTER_FDIR:
5787                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5788                 break;
5789         case RTE_ETH_FILTER_L2_TUNNEL:
5790                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5791                 break;
5792         default:
5793                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5794                                                         filter_type);
5795                 break;
5796         }
5797
5798         return ret;
5799 }
5800
5801 static u8 *
5802 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5803                         u8 **mc_addr_ptr, u32 *vmdq)
5804 {
5805         u8 *mc_addr;
5806
5807         *vmdq = 0;
5808         mc_addr = *mc_addr_ptr;
5809         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5810         return mc_addr;
5811 }
5812
5813 static int
5814 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5815                           struct ether_addr *mc_addr_set,
5816                           uint32_t nb_mc_addr)
5817 {
5818         struct ixgbe_hw *hw;
5819         u8 *mc_addr_list;
5820
5821         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5822         mc_addr_list = (u8 *)mc_addr_set;
5823         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5824                                          ixgbe_dev_addr_list_itr, TRUE);
5825 }
5826
5827 static uint64_t
5828 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5829 {
5830         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5831         uint64_t systime_cycles;
5832
5833         switch (hw->mac.type) {
5834         case ixgbe_mac_X550:
5835         case ixgbe_mac_X550EM_x:
5836         case ixgbe_mac_X550EM_a:
5837                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5838                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5839                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5840                                 * NSEC_PER_SEC;
5841                 break;
5842         default:
5843                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5844                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5845                                 << 32;
5846         }
5847
5848         return systime_cycles;
5849 }
5850
5851 static uint64_t
5852 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5853 {
5854         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5855         uint64_t rx_tstamp_cycles;
5856
5857         switch (hw->mac.type) {
5858         case ixgbe_mac_X550:
5859         case ixgbe_mac_X550EM_x:
5860         case ixgbe_mac_X550EM_a:
5861                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5862                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5863                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5864                                 * NSEC_PER_SEC;
5865                 break;
5866         default:
5867                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5868                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5869                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5870                                 << 32;
5871         }
5872
5873         return rx_tstamp_cycles;
5874 }
5875
5876 static uint64_t
5877 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5878 {
5879         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5880         uint64_t tx_tstamp_cycles;
5881
5882         switch (hw->mac.type) {
5883         case ixgbe_mac_X550:
5884         case ixgbe_mac_X550EM_x:
5885         case ixgbe_mac_X550EM_a:
5886                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5887                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5888                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5889                                 * NSEC_PER_SEC;
5890                 break;
5891         default:
5892                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5893                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5894                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5895                                 << 32;
5896         }
5897
5898         return tx_tstamp_cycles;
5899 }
5900
5901 static void
5902 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5903 {
5904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5905         struct ixgbe_adapter *adapter =
5906                 (struct ixgbe_adapter *)dev->data->dev_private;
5907         struct rte_eth_link link;
5908         uint32_t incval = 0;
5909         uint32_t shift = 0;
5910
5911         /* Get current link speed. */
5912         memset(&link, 0, sizeof(link));
5913         ixgbe_dev_link_update(dev, 1);
5914         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5915
5916         switch (link.link_speed) {
5917         case ETH_LINK_SPEED_100:
5918                 incval = IXGBE_INCVAL_100;
5919                 shift = IXGBE_INCVAL_SHIFT_100;
5920                 break;
5921         case ETH_LINK_SPEED_1000:
5922                 incval = IXGBE_INCVAL_1GB;
5923                 shift = IXGBE_INCVAL_SHIFT_1GB;
5924                 break;
5925         case ETH_LINK_SPEED_10000:
5926         default:
5927                 incval = IXGBE_INCVAL_10GB;
5928                 shift = IXGBE_INCVAL_SHIFT_10GB;
5929                 break;
5930         }
5931
5932         switch (hw->mac.type) {
5933         case ixgbe_mac_X550:
5934         case ixgbe_mac_X550EM_x:
5935         case ixgbe_mac_X550EM_a:
5936                 /* Independent of link speed. */
5937                 incval = 1;
5938                 /* Cycles read will be interpreted as ns. */
5939                 shift = 0;
5940                 /* Fall-through */
5941         case ixgbe_mac_X540:
5942                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5943                 break;
5944         case ixgbe_mac_82599EB:
5945                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5946                 shift -= IXGBE_INCVAL_SHIFT_82599;
5947                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5948                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5949                 break;
5950         default:
5951                 /* Not supported. */
5952                 return;
5953         }
5954
5955         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5956         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5957         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5958
5959         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5960         adapter->systime_tc.cc_shift = shift;
5961         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5962
5963         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5964         adapter->rx_tstamp_tc.cc_shift = shift;
5965         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5966
5967         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5968         adapter->tx_tstamp_tc.cc_shift = shift;
5969         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5970 }
5971
5972 static int
5973 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5974 {
5975         struct ixgbe_adapter *adapter =
5976                         (struct ixgbe_adapter *)dev->data->dev_private;
5977
5978         adapter->systime_tc.nsec += delta;
5979         adapter->rx_tstamp_tc.nsec += delta;
5980         adapter->tx_tstamp_tc.nsec += delta;
5981
5982         return 0;
5983 }
5984
5985 static int
5986 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5987 {
5988         uint64_t ns;
5989         struct ixgbe_adapter *adapter =
5990                         (struct ixgbe_adapter *)dev->data->dev_private;
5991
5992         ns = rte_timespec_to_ns(ts);
5993         /* Set the timecounters to a new value. */
5994         adapter->systime_tc.nsec = ns;
5995         adapter->rx_tstamp_tc.nsec = ns;
5996         adapter->tx_tstamp_tc.nsec = ns;
5997
5998         return 0;
5999 }
6000
6001 static int
6002 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6003 {
6004         uint64_t ns, systime_cycles;
6005         struct ixgbe_adapter *adapter =
6006                         (struct ixgbe_adapter *)dev->data->dev_private;
6007
6008         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6009         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6010         *ts = rte_ns_to_timespec(ns);
6011
6012         return 0;
6013 }
6014
6015 static int
6016 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6017 {
6018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6019         uint32_t tsync_ctl;
6020         uint32_t tsauxc;
6021
6022         /* Stop the timesync system time. */
6023         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6024         /* Reset the timesync system time value. */
6025         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6026         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6027
6028         /* Enable system time for platforms where it isn't on by default. */
6029         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6030         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6031         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6032
6033         ixgbe_start_timecounters(dev);
6034
6035         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6036         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6037                         (ETHER_TYPE_1588 |
6038                          IXGBE_ETQF_FILTER_EN |
6039                          IXGBE_ETQF_1588));
6040
6041         /* Enable timestamping of received PTP packets. */
6042         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6043         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6044         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6045
6046         /* Enable timestamping of transmitted PTP packets. */
6047         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6048         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6049         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6050
6051         IXGBE_WRITE_FLUSH(hw);
6052
6053         return 0;
6054 }
6055
6056 static int
6057 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6058 {
6059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6060         uint32_t tsync_ctl;
6061
6062         /* Disable timestamping of transmitted PTP packets. */
6063         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6064         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6065         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6066
6067         /* Disable timestamping of received PTP packets. */
6068         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6069         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6070         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6071
6072         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6073         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6074
6075         /* Stop incrementating the System Time registers. */
6076         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6077
6078         return 0;
6079 }
6080
6081 static int
6082 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6083                                  struct timespec *timestamp,
6084                                  uint32_t flags __rte_unused)
6085 {
6086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6087         struct ixgbe_adapter *adapter =
6088                 (struct ixgbe_adapter *)dev->data->dev_private;
6089         uint32_t tsync_rxctl;
6090         uint64_t rx_tstamp_cycles;
6091         uint64_t ns;
6092
6093         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6094         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6095                 return -EINVAL;
6096
6097         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6098         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6099         *timestamp = rte_ns_to_timespec(ns);
6100
6101         return  0;
6102 }
6103
6104 static int
6105 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6106                                  struct timespec *timestamp)
6107 {
6108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6109         struct ixgbe_adapter *adapter =
6110                 (struct ixgbe_adapter *)dev->data->dev_private;
6111         uint32_t tsync_txctl;
6112         uint64_t tx_tstamp_cycles;
6113         uint64_t ns;
6114
6115         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6116         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6117                 return -EINVAL;
6118
6119         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6120         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6121         *timestamp = rte_ns_to_timespec(ns);
6122
6123         return 0;
6124 }
6125
6126 static int
6127 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6128 {
6129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6130         int count = 0;
6131         int g_ind = 0;
6132         const struct reg_info *reg_group;
6133         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6134                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6135
6136         while ((reg_group = reg_set[g_ind++]))
6137                 count += ixgbe_regs_group_count(reg_group);
6138
6139         return count;
6140 }
6141
6142 static int
6143 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6144 {
6145         int count = 0;
6146         int g_ind = 0;
6147         const struct reg_info *reg_group;
6148
6149         while ((reg_group = ixgbevf_regs[g_ind++]))
6150                 count += ixgbe_regs_group_count(reg_group);
6151
6152         return count;
6153 }
6154
6155 static int
6156 ixgbe_get_regs(struct rte_eth_dev *dev,
6157               struct rte_dev_reg_info *regs)
6158 {
6159         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6160         uint32_t *data = regs->data;
6161         int g_ind = 0;
6162         int count = 0;
6163         const struct reg_info *reg_group;
6164         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6165                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6166
6167         /* Support only full register dump */
6168         if ((regs->length == 0) ||
6169             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6170                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6171                         hw->device_id;
6172                 while ((reg_group = reg_set[g_ind++]))
6173                         count += ixgbe_read_regs_group(dev, &data[count],
6174                                 reg_group);
6175                 return 0;
6176         }
6177
6178         return -ENOTSUP;
6179 }
6180
6181 static int
6182 ixgbevf_get_regs(struct rte_eth_dev *dev,
6183                 struct rte_dev_reg_info *regs)
6184 {
6185         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6186         uint32_t *data = regs->data;
6187         int g_ind = 0;
6188         int count = 0;
6189         const struct reg_info *reg_group;
6190
6191         /* Support only full register dump */
6192         if ((regs->length == 0) ||
6193             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6194                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6195                         hw->device_id;
6196                 while ((reg_group = ixgbevf_regs[g_ind++]))
6197                         count += ixgbe_read_regs_group(dev, &data[count],
6198                                                       reg_group);
6199                 return 0;
6200         }
6201
6202         return -ENOTSUP;
6203 }
6204
6205 static int
6206 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6207 {
6208         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6209
6210         /* Return unit is byte count */
6211         return hw->eeprom.word_size * 2;
6212 }
6213
6214 static int
6215 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6216                 struct rte_dev_eeprom_info *in_eeprom)
6217 {
6218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6219         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6220         uint16_t *data = in_eeprom->data;
6221         int first, length;
6222
6223         first = in_eeprom->offset >> 1;
6224         length = in_eeprom->length >> 1;
6225         if ((first > hw->eeprom.word_size) ||
6226             ((first + length) > hw->eeprom.word_size))
6227                 return -EINVAL;
6228
6229         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6230
6231         return eeprom->ops.read_buffer(hw, first, length, data);
6232 }
6233
6234 static int
6235 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6236                 struct rte_dev_eeprom_info *in_eeprom)
6237 {
6238         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6239         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6240         uint16_t *data = in_eeprom->data;
6241         int first, length;
6242
6243         first = in_eeprom->offset >> 1;
6244         length = in_eeprom->length >> 1;
6245         if ((first > hw->eeprom.word_size) ||
6246             ((first + length) > hw->eeprom.word_size))
6247                 return -EINVAL;
6248
6249         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6250
6251         return eeprom->ops.write_buffer(hw,  first, length, data);
6252 }
6253
6254 uint16_t
6255 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6256         switch (mac_type) {
6257         case ixgbe_mac_X550:
6258         case ixgbe_mac_X550EM_x:
6259         case ixgbe_mac_X550EM_a:
6260                 return ETH_RSS_RETA_SIZE_512;
6261         case ixgbe_mac_X550_vf:
6262         case ixgbe_mac_X550EM_x_vf:
6263         case ixgbe_mac_X550EM_a_vf:
6264                 return ETH_RSS_RETA_SIZE_64;
6265         default:
6266                 return ETH_RSS_RETA_SIZE_128;
6267         }
6268 }
6269
6270 uint32_t
6271 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6272         switch (mac_type) {
6273         case ixgbe_mac_X550:
6274         case ixgbe_mac_X550EM_x:
6275         case ixgbe_mac_X550EM_a:
6276                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6277                         return IXGBE_RETA(reta_idx >> 2);
6278                 else
6279                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6280         case ixgbe_mac_X550_vf:
6281         case ixgbe_mac_X550EM_x_vf:
6282         case ixgbe_mac_X550EM_a_vf:
6283                 return IXGBE_VFRETA(reta_idx >> 2);
6284         default:
6285                 return IXGBE_RETA(reta_idx >> 2);
6286         }
6287 }
6288
6289 uint32_t
6290 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6291         switch (mac_type) {
6292         case ixgbe_mac_X550_vf:
6293         case ixgbe_mac_X550EM_x_vf:
6294         case ixgbe_mac_X550EM_a_vf:
6295                 return IXGBE_VFMRQC;
6296         default:
6297                 return IXGBE_MRQC;
6298         }
6299 }
6300
6301 uint32_t
6302 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6303         switch (mac_type) {
6304         case ixgbe_mac_X550_vf:
6305         case ixgbe_mac_X550EM_x_vf:
6306         case ixgbe_mac_X550EM_a_vf:
6307                 return IXGBE_VFRSSRK(i);
6308         default:
6309                 return IXGBE_RSSRK(i);
6310         }
6311 }
6312
6313 bool
6314 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6315         switch (mac_type) {
6316         case ixgbe_mac_82599_vf:
6317         case ixgbe_mac_X540_vf:
6318                 return 0;
6319         default:
6320                 return 1;
6321         }
6322 }
6323
6324 static int
6325 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6326                         struct rte_eth_dcb_info *dcb_info)
6327 {
6328         struct ixgbe_dcb_config *dcb_config =
6329                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6330         struct ixgbe_dcb_tc_config *tc;
6331         uint8_t i, j;
6332
6333         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6334                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6335         else
6336                 dcb_info->nb_tcs = 1;
6337
6338         if (dcb_config->vt_mode) { /* vt is enabled*/
6339                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6340                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6341                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6342                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6343                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6344                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6345                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6346                                                 i * dcb_info->nb_tcs + j;
6347                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6348                                 dcb_info->tc_queue.tc_txq[i][j].base =
6349                                                 i * dcb_info->nb_tcs + j;
6350                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6351                         }
6352                 }
6353         } else { /* vt is disabled*/
6354                 struct rte_eth_dcb_rx_conf *rx_conf =
6355                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6356                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6357                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6358                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6359                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6360                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6361                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6362                         }
6363                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6364                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6365                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6366                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6367                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6368                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6369                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6370                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6371                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6372                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6373                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6374                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6375                         }
6376                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6377                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6378                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6379                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6380                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6381                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6382                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6383                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6384                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6385                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6386                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6387                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6388                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6389                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6390                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6391                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6392                 }
6393         }
6394         for (i = 0; i < dcb_info->nb_tcs; i++) {
6395                 tc = &dcb_config->tc_config[i];
6396                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6397         }
6398         return 0;
6399 }
6400
6401 /* Update e-tag ether type */
6402 static int
6403 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6404                             uint16_t ether_type)
6405 {
6406         uint32_t etag_etype;
6407
6408         if (hw->mac.type != ixgbe_mac_X550 &&
6409             hw->mac.type != ixgbe_mac_X550EM_x &&
6410             hw->mac.type != ixgbe_mac_X550EM_a) {
6411                 return -ENOTSUP;
6412         }
6413
6414         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6415         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6416         etag_etype |= ether_type;
6417         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6418         IXGBE_WRITE_FLUSH(hw);
6419
6420         return 0;
6421 }
6422
6423 /* Config l2 tunnel ether type */
6424 static int
6425 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6426                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6427 {
6428         int ret = 0;
6429         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6430
6431         if (l2_tunnel == NULL)
6432                 return -EINVAL;
6433
6434         switch (l2_tunnel->l2_tunnel_type) {
6435         case RTE_L2_TUNNEL_TYPE_E_TAG:
6436                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6437                 break;
6438         default:
6439                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6440                 ret = -EINVAL;
6441                 break;
6442         }
6443
6444         return ret;
6445 }
6446
6447 /* Enable e-tag tunnel */
6448 static int
6449 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6450 {
6451         uint32_t etag_etype;
6452
6453         if (hw->mac.type != ixgbe_mac_X550 &&
6454             hw->mac.type != ixgbe_mac_X550EM_x &&
6455             hw->mac.type != ixgbe_mac_X550EM_a) {
6456                 return -ENOTSUP;
6457         }
6458
6459         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6460         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6461         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6462         IXGBE_WRITE_FLUSH(hw);
6463
6464         return 0;
6465 }
6466
6467 /* Enable l2 tunnel */
6468 static int
6469 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6470                            enum rte_eth_tunnel_type l2_tunnel_type)
6471 {
6472         int ret = 0;
6473         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6474
6475         switch (l2_tunnel_type) {
6476         case RTE_L2_TUNNEL_TYPE_E_TAG:
6477                 ret = ixgbe_e_tag_enable(hw);
6478                 break;
6479         default:
6480                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6481                 ret = -EINVAL;
6482                 break;
6483         }
6484
6485         return ret;
6486 }
6487
6488 /* Disable e-tag tunnel */
6489 static int
6490 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6491 {
6492         uint32_t etag_etype;
6493
6494         if (hw->mac.type != ixgbe_mac_X550 &&
6495             hw->mac.type != ixgbe_mac_X550EM_x &&
6496             hw->mac.type != ixgbe_mac_X550EM_a) {
6497                 return -ENOTSUP;
6498         }
6499
6500         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6501         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6502         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6503         IXGBE_WRITE_FLUSH(hw);
6504
6505         return 0;
6506 }
6507
6508 /* Disable l2 tunnel */
6509 static int
6510 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6511                             enum rte_eth_tunnel_type l2_tunnel_type)
6512 {
6513         int ret = 0;
6514         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6515
6516         switch (l2_tunnel_type) {
6517         case RTE_L2_TUNNEL_TYPE_E_TAG:
6518                 ret = ixgbe_e_tag_disable(hw);
6519                 break;
6520         default:
6521                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6522                 ret = -EINVAL;
6523                 break;
6524         }
6525
6526         return ret;
6527 }
6528
6529 static int
6530 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6531                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6532 {
6533         int ret = 0;
6534         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6535         uint32_t i, rar_entries;
6536         uint32_t rar_low, rar_high;
6537
6538         if (hw->mac.type != ixgbe_mac_X550 &&
6539             hw->mac.type != ixgbe_mac_X550EM_x &&
6540             hw->mac.type != ixgbe_mac_X550EM_a) {
6541                 return -ENOTSUP;
6542         }
6543
6544         rar_entries = ixgbe_get_num_rx_addrs(hw);
6545
6546         for (i = 1; i < rar_entries; i++) {
6547                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6548                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6549                 if ((rar_high & IXGBE_RAH_AV) &&
6550                     (rar_high & IXGBE_RAH_ADTYPE) &&
6551                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6552                      l2_tunnel->tunnel_id)) {
6553                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6554                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6555
6556                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6557
6558                         return ret;
6559                 }
6560         }
6561
6562         return ret;
6563 }
6564
6565 static int
6566 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6567                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6568 {
6569         int ret = 0;
6570         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6571         uint32_t i, rar_entries;
6572         uint32_t rar_low, rar_high;
6573
6574         if (hw->mac.type != ixgbe_mac_X550 &&
6575             hw->mac.type != ixgbe_mac_X550EM_x &&
6576             hw->mac.type != ixgbe_mac_X550EM_a) {
6577                 return -ENOTSUP;
6578         }
6579
6580         /* One entry for one tunnel. Try to remove potential existing entry. */
6581         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6582
6583         rar_entries = ixgbe_get_num_rx_addrs(hw);
6584
6585         for (i = 1; i < rar_entries; i++) {
6586                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6587                 if (rar_high & IXGBE_RAH_AV) {
6588                         continue;
6589                 } else {
6590                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6591                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6592                         rar_low = l2_tunnel->tunnel_id;
6593
6594                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6595                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6596
6597                         return ret;
6598                 }
6599         }
6600
6601         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6602                      " Please remove a rule before adding a new one.");
6603         return -EINVAL;
6604 }
6605
6606 /* Add l2 tunnel filter */
6607 static int
6608 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6609                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6610 {
6611         int ret = 0;
6612
6613         switch (l2_tunnel->l2_tunnel_type) {
6614         case RTE_L2_TUNNEL_TYPE_E_TAG:
6615                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6616                 break;
6617         default:
6618                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6619                 ret = -EINVAL;
6620                 break;
6621         }
6622
6623         return ret;
6624 }
6625
6626 /* Delete l2 tunnel filter */
6627 static int
6628 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6629                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6630 {
6631         int ret = 0;
6632
6633         switch (l2_tunnel->l2_tunnel_type) {
6634         case RTE_L2_TUNNEL_TYPE_E_TAG:
6635                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6636                 break;
6637         default:
6638                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6639                 ret = -EINVAL;
6640                 break;
6641         }
6642
6643         return ret;
6644 }
6645
6646 /**
6647  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6648  * @dev: pointer to rte_eth_dev structure
6649  * @filter_op:operation will be taken.
6650  * @arg: a pointer to specific structure corresponding to the filter_op
6651  */
6652 static int
6653 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6654                                   enum rte_filter_op filter_op,
6655                                   void *arg)
6656 {
6657         int ret = 0;
6658
6659         if (filter_op == RTE_ETH_FILTER_NOP)
6660                 return 0;
6661
6662         if (arg == NULL) {
6663                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6664                             filter_op);
6665                 return -EINVAL;
6666         }
6667
6668         switch (filter_op) {
6669         case RTE_ETH_FILTER_ADD:
6670                 ret = ixgbe_dev_l2_tunnel_filter_add
6671                         (dev,
6672                          (struct rte_eth_l2_tunnel_conf *)arg);
6673                 break;
6674         case RTE_ETH_FILTER_DELETE:
6675                 ret = ixgbe_dev_l2_tunnel_filter_del
6676                         (dev,
6677                          (struct rte_eth_l2_tunnel_conf *)arg);
6678                 break;
6679         default:
6680                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6681                 ret = -EINVAL;
6682                 break;
6683         }
6684         return ret;
6685 }
6686
6687 static int
6688 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6689 {
6690         int ret = 0;
6691         uint32_t ctrl;
6692         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6693
6694         if (hw->mac.type != ixgbe_mac_X550 &&
6695             hw->mac.type != ixgbe_mac_X550EM_x &&
6696             hw->mac.type != ixgbe_mac_X550EM_a) {
6697                 return -ENOTSUP;
6698         }
6699
6700         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6701         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6702         if (en)
6703                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6704         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6705
6706         return ret;
6707 }
6708
6709 /* Enable l2 tunnel forwarding */
6710 static int
6711 ixgbe_dev_l2_tunnel_forwarding_enable
6712         (struct rte_eth_dev *dev,
6713          enum rte_eth_tunnel_type l2_tunnel_type)
6714 {
6715         int ret = 0;
6716
6717         switch (l2_tunnel_type) {
6718         case RTE_L2_TUNNEL_TYPE_E_TAG:
6719                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6720                 break;
6721         default:
6722                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6723                 ret = -EINVAL;
6724                 break;
6725         }
6726
6727         return ret;
6728 }
6729
6730 /* Disable l2 tunnel forwarding */
6731 static int
6732 ixgbe_dev_l2_tunnel_forwarding_disable
6733         (struct rte_eth_dev *dev,
6734          enum rte_eth_tunnel_type l2_tunnel_type)
6735 {
6736         int ret = 0;
6737
6738         switch (l2_tunnel_type) {
6739         case RTE_L2_TUNNEL_TYPE_E_TAG:
6740                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6741                 break;
6742         default:
6743                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6744                 ret = -EINVAL;
6745                 break;
6746         }
6747
6748         return ret;
6749 }
6750
6751 static int
6752 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6753                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6754                              bool en)
6755 {
6756         int ret = 0;
6757         uint32_t vmtir, vmvir;
6758         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6759
6760         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6761                 PMD_DRV_LOG(ERR,
6762                             "VF id %u should be less than %u",
6763                             l2_tunnel->vf_id,
6764                             dev->pci_dev->max_vfs);
6765                 return -EINVAL;
6766         }
6767
6768         if (hw->mac.type != ixgbe_mac_X550 &&
6769             hw->mac.type != ixgbe_mac_X550EM_x &&
6770             hw->mac.type != ixgbe_mac_X550EM_a) {
6771                 return -ENOTSUP;
6772         }
6773
6774         if (en)
6775                 vmtir = l2_tunnel->tunnel_id;
6776         else
6777                 vmtir = 0;
6778
6779         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6780
6781         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6782         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6783         if (en)
6784                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6785         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6786
6787         return ret;
6788 }
6789
6790 /* Enable l2 tunnel tag insertion */
6791 static int
6792 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6793                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6794 {
6795         int ret = 0;
6796
6797         switch (l2_tunnel->l2_tunnel_type) {
6798         case RTE_L2_TUNNEL_TYPE_E_TAG:
6799                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6800                 break;
6801         default:
6802                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6803                 ret = -EINVAL;
6804                 break;
6805         }
6806
6807         return ret;
6808 }
6809
6810 /* Disable l2 tunnel tag insertion */
6811 static int
6812 ixgbe_dev_l2_tunnel_insertion_disable
6813         (struct rte_eth_dev *dev,
6814          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6815 {
6816         int ret = 0;
6817
6818         switch (l2_tunnel->l2_tunnel_type) {
6819         case RTE_L2_TUNNEL_TYPE_E_TAG:
6820                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6821                 break;
6822         default:
6823                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6824                 ret = -EINVAL;
6825                 break;
6826         }
6827
6828         return ret;
6829 }
6830
6831 static int
6832 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6833                              bool en)
6834 {
6835         int ret = 0;
6836         uint32_t qde;
6837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6838
6839         if (hw->mac.type != ixgbe_mac_X550 &&
6840             hw->mac.type != ixgbe_mac_X550EM_x &&
6841             hw->mac.type != ixgbe_mac_X550EM_a) {
6842                 return -ENOTSUP;
6843         }
6844
6845         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6846         if (en)
6847                 qde |= IXGBE_QDE_STRIP_TAG;
6848         else
6849                 qde &= ~IXGBE_QDE_STRIP_TAG;
6850         qde &= ~IXGBE_QDE_READ;
6851         qde |= IXGBE_QDE_WRITE;
6852         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6853
6854         return ret;
6855 }
6856
6857 /* Enable l2 tunnel tag stripping */
6858 static int
6859 ixgbe_dev_l2_tunnel_stripping_enable
6860         (struct rte_eth_dev *dev,
6861          enum rte_eth_tunnel_type l2_tunnel_type)
6862 {
6863         int ret = 0;
6864
6865         switch (l2_tunnel_type) {
6866         case RTE_L2_TUNNEL_TYPE_E_TAG:
6867                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6868                 break;
6869         default:
6870                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6871                 ret = -EINVAL;
6872                 break;
6873         }
6874
6875         return ret;
6876 }
6877
6878 /* Disable l2 tunnel tag stripping */
6879 static int
6880 ixgbe_dev_l2_tunnel_stripping_disable
6881         (struct rte_eth_dev *dev,
6882          enum rte_eth_tunnel_type l2_tunnel_type)
6883 {
6884         int ret = 0;
6885
6886         switch (l2_tunnel_type) {
6887         case RTE_L2_TUNNEL_TYPE_E_TAG:
6888                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6889                 break;
6890         default:
6891                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6892                 ret = -EINVAL;
6893                 break;
6894         }
6895
6896         return ret;
6897 }
6898
6899 /* Enable/disable l2 tunnel offload functions */
6900 static int
6901 ixgbe_dev_l2_tunnel_offload_set
6902         (struct rte_eth_dev *dev,
6903          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6904          uint32_t mask,
6905          uint8_t en)
6906 {
6907         int ret = 0;
6908
6909         if (l2_tunnel == NULL)
6910                 return -EINVAL;
6911
6912         ret = -EINVAL;
6913         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6914                 if (en)
6915                         ret = ixgbe_dev_l2_tunnel_enable(
6916                                 dev,
6917                                 l2_tunnel->l2_tunnel_type);
6918                 else
6919                         ret = ixgbe_dev_l2_tunnel_disable(
6920                                 dev,
6921                                 l2_tunnel->l2_tunnel_type);
6922         }
6923
6924         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6925                 if (en)
6926                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6927                                 dev,
6928                                 l2_tunnel);
6929                 else
6930                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6931                                 dev,
6932                                 l2_tunnel);
6933         }
6934
6935         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6936                 if (en)
6937                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6938                                 dev,
6939                                 l2_tunnel->l2_tunnel_type);
6940                 else
6941                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6942                                 dev,
6943                                 l2_tunnel->l2_tunnel_type);
6944         }
6945
6946         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6947                 if (en)
6948                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6949                                 dev,
6950                                 l2_tunnel->l2_tunnel_type);
6951                 else
6952                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6953                                 dev,
6954                                 l2_tunnel->l2_tunnel_type);
6955         }
6956
6957         return ret;
6958 }
6959
6960 static int
6961 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6962                         uint16_t port)
6963 {
6964         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6965         IXGBE_WRITE_FLUSH(hw);
6966
6967         return 0;
6968 }
6969
6970 /* There's only one register for VxLAN UDP port.
6971  * So, we cannot add several ports. Will update it.
6972  */
6973 static int
6974 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6975                      uint16_t port)
6976 {
6977         if (port == 0) {
6978                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6979                 return -EINVAL;
6980         }
6981
6982         return ixgbe_update_vxlan_port(hw, port);
6983 }
6984
6985 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6986  * UDP port, it must have a value.
6987  * So, will reset it to the original value 0.
6988  */
6989 static int
6990 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6991                      uint16_t port)
6992 {
6993         uint16_t cur_port;
6994
6995         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6996
6997         if (cur_port != port) {
6998                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6999                 return -EINVAL;
7000         }
7001
7002         return ixgbe_update_vxlan_port(hw, 0);
7003 }
7004
7005 /* Add UDP tunneling port */
7006 static int
7007 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7008                               struct rte_eth_udp_tunnel *udp_tunnel)
7009 {
7010         int ret = 0;
7011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7012
7013         if (hw->mac.type != ixgbe_mac_X550 &&
7014             hw->mac.type != ixgbe_mac_X550EM_x &&
7015             hw->mac.type != ixgbe_mac_X550EM_a) {
7016                 return -ENOTSUP;
7017         }
7018
7019         if (udp_tunnel == NULL)
7020                 return -EINVAL;
7021
7022         switch (udp_tunnel->prot_type) {
7023         case RTE_TUNNEL_TYPE_VXLAN:
7024                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7025                 break;
7026
7027         case RTE_TUNNEL_TYPE_GENEVE:
7028         case RTE_TUNNEL_TYPE_TEREDO:
7029                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7030                 ret = -EINVAL;
7031                 break;
7032
7033         default:
7034                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7035                 ret = -EINVAL;
7036                 break;
7037         }
7038
7039         return ret;
7040 }
7041
7042 /* Remove UDP tunneling port */
7043 static int
7044 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7045                               struct rte_eth_udp_tunnel *udp_tunnel)
7046 {
7047         int ret = 0;
7048         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7049
7050         if (hw->mac.type != ixgbe_mac_X550 &&
7051             hw->mac.type != ixgbe_mac_X550EM_x &&
7052             hw->mac.type != ixgbe_mac_X550EM_a) {
7053                 return -ENOTSUP;
7054         }
7055
7056         if (udp_tunnel == NULL)
7057                 return -EINVAL;
7058
7059         switch (udp_tunnel->prot_type) {
7060         case RTE_TUNNEL_TYPE_VXLAN:
7061                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7062                 break;
7063         case RTE_TUNNEL_TYPE_GENEVE:
7064         case RTE_TUNNEL_TYPE_TEREDO:
7065                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7066                 ret = -EINVAL;
7067                 break;
7068         default:
7069                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7070                 ret = -EINVAL;
7071                 break;
7072         }
7073
7074         return ret;
7075 }
7076
7077 /* ixgbevf_update_xcast_mode - Update Multicast mode
7078  * @hw: pointer to the HW structure
7079  * @netdev: pointer to net device structure
7080  * @xcast_mode: new multicast mode
7081  *
7082  * Updates the Multicast Mode of VF.
7083  */
7084 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7085                                      int xcast_mode)
7086 {
7087         struct ixgbe_mbx_info *mbx = &hw->mbx;
7088         u32 msgbuf[2];
7089         s32 err;
7090
7091         switch (hw->api_version) {
7092         case ixgbe_mbox_api_12:
7093                 break;
7094         default:
7095                 return -EOPNOTSUPP;
7096         }
7097
7098         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7099         msgbuf[1] = xcast_mode;
7100
7101         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7102         if (err)
7103                 return err;
7104
7105         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7106         if (err)
7107                 return err;
7108
7109         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7110         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7111                 return -EPERM;
7112
7113         return 0;
7114 }
7115
7116 static void
7117 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7118 {
7119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7120
7121         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7122 }
7123
7124 static void
7125 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7126 {
7127         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7128
7129         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7130 }
7131
7132 static struct rte_driver rte_ixgbe_driver = {
7133         .type = PMD_PDEV,
7134         .init = rte_ixgbe_pmd_init,
7135 };
7136
7137 static struct rte_driver rte_ixgbevf_driver = {
7138         .type = PMD_PDEV,
7139         .init = rte_ixgbevf_pmd_init,
7140 };
7141
7142 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7143 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);