drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <ethdev_driver.h>
  31 #include <ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIB_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 304                         struct ixgbe_5tuple_filter *filter);
 305 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 306                         struct ixgbe_5tuple_filter *filter);
 307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 308                      enum rte_filter_type filter_type,
 309                      enum rte_filter_op filter_op,
 310                      void *arg);
 311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 312
 313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 314                                       struct rte_ether_addr *mc_addr_set,
 315                                       uint32_t nb_mc_addr);
 316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 317                                    struct rte_eth_dcb_info *dcb_info);
 318
 319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 320 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 321                             struct rte_dev_reg_info *regs);
 322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327
 328 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 329                                  struct rte_eth_dev_module_info *modinfo);
 330 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 331                                    struct rte_dev_eeprom_info *info);
 332
 333 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 334 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 335                                 struct rte_dev_reg_info *regs);
 336
 337 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 339 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp,
 341                                             uint32_t flags);
 342 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 343                                             struct timespec *timestamp);
 344 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 345 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 346                                    struct timespec *timestamp);
 347 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 348                                    const struct timespec *timestamp);
 349 static void ixgbevf_dev_interrupt_handler(void *param);
 350
 351 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 352                                          struct rte_eth_udp_tunnel *udp_tunnel);
 353 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 354                                          struct rte_eth_udp_tunnel *udp_tunnel);
 355 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 356 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 357 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 358
 359 /*
 360  * Define VF Stats MACRO for Non "cleared on read" register
 361  */
 362 #define UPDATE_VF_STAT(reg, last, cur)                          \
 363 {                                                               \
 364         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 365         cur += (latest - last) & UINT_MAX;                      \
 366         last = latest;                                          \
 367 }
 368
 369 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 370 {                                                                \
 371         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 372         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 373         u64 latest = ((new_msb << 32) | new_lsb);                \
 374         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 375         last = latest;                                           \
 376 }
 377
 378 #define IXGBE_SET_HWSTRIP(h, q) do {\
 379                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 380                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 381                 (h)->bitmap[idx] |= 1 << bit;\
 382         } while (0)
 383
 384 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 385                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 386                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 387                 (h)->bitmap[idx] &= ~(1 << bit);\
 388         } while (0)
 389
 390 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 391                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 392                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 393                 (r) = (h)->bitmap[idx] >> bit & 1;\
 394         } while (0)
 395
 396 /*
 397  * The set of PCI devices this driver supports
 398  */
 399 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 400         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 401         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 402         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 403         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 404         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 405         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 406         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 407         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 408         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 448 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 450 #endif
 451         { .vendor_id = 0, /* sentinel */ },
 452 };
 453
 454 /*
 455  * The set of PCI devices this driver supports (for 82599 VF)
 456  */
 457 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 468         { .vendor_id = 0, /* sentinel */ },
 469 };
 470
 471 static const struct rte_eth_desc_lim rx_desc_lim = {
 472         .nb_max = IXGBE_MAX_RING_DESC,
 473         .nb_min = IXGBE_MIN_RING_DESC,
 474         .nb_align = IXGBE_RXD_ALIGN,
 475 };
 476
 477 static const struct rte_eth_desc_lim tx_desc_lim = {
 478         .nb_max = IXGBE_MAX_RING_DESC,
 479         .nb_min = IXGBE_MIN_RING_DESC,
 480         .nb_align = IXGBE_TXD_ALIGN,
 481         .nb_seg_max = IXGBE_TX_MAX_SEG,
 482         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 483 };
 484
 485 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 486         .dev_configure        = ixgbe_dev_configure,
 487         .dev_start            = ixgbe_dev_start,
 488         .dev_stop             = ixgbe_dev_stop,
 489         .dev_set_link_up    = ixgbe_dev_set_link_up,
 490         .dev_set_link_down  = ixgbe_dev_set_link_down,
 491         .dev_close            = ixgbe_dev_close,
 492         .dev_reset            = ixgbe_dev_reset,
 493         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 494         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 495         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 496         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 497         .link_update          = ixgbe_dev_link_update,
 498         .stats_get            = ixgbe_dev_stats_get,
 499         .xstats_get           = ixgbe_dev_xstats_get,
 500         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 501         .stats_reset          = ixgbe_dev_stats_reset,
 502         .xstats_reset         = ixgbe_dev_xstats_reset,
 503         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 504         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 505         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 506         .fw_version_get       = ixgbe_fw_version_get,
 507         .dev_infos_get        = ixgbe_dev_info_get,
 508         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 509         .mtu_set              = ixgbe_dev_mtu_set,
 510         .vlan_filter_set      = ixgbe_vlan_filter_set,
 511         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 512         .vlan_offload_set     = ixgbe_vlan_offload_set,
 513         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 514         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 515         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 516         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 517         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 518         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 519         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 520         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 521         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 522         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 523         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 524         .dev_led_on           = ixgbe_dev_led_on,
 525         .dev_led_off          = ixgbe_dev_led_off,
 526         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 527         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 528         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 529         .mac_addr_add         = ixgbe_add_rar,
 530         .mac_addr_remove      = ixgbe_remove_rar,
 531         .mac_addr_set         = ixgbe_set_default_mac_addr,
 532         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 533         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 534         .mirror_rule_set      = ixgbe_mirror_rule_set,
 535         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 536         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 537         .reta_update          = ixgbe_dev_rss_reta_update,
 538         .reta_query           = ixgbe_dev_rss_reta_query,
 539         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 540         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 541         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 542         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 543         .rxq_info_get         = ixgbe_rxq_info_get,
 544         .txq_info_get         = ixgbe_txq_info_get,
 545         .timesync_enable      = ixgbe_timesync_enable,
 546         .timesync_disable     = ixgbe_timesync_disable,
 547         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 548         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 549         .get_reg              = ixgbe_get_regs,
 550         .get_eeprom_length    = ixgbe_get_eeprom_length,
 551         .get_eeprom           = ixgbe_get_eeprom,
 552         .set_eeprom           = ixgbe_set_eeprom,
 553         .get_module_info      = ixgbe_get_module_info,
 554         .get_module_eeprom    = ixgbe_get_module_eeprom,
 555         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 556         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 557         .timesync_read_time   = ixgbe_timesync_read_time,
 558         .timesync_write_time  = ixgbe_timesync_write_time,
 559         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 560         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 561         .tm_ops_get           = ixgbe_tm_ops_get,
 562         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 563         .get_monitor_addr     = ixgbe_get_monitor_addr,
 564 };
 565
 566 /*
 567  * dev_ops for virtual function, bare necessities for basic vf
 568  * operation have been implemented
 569  */
 570 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 571         .dev_configure        = ixgbevf_dev_configure,
 572         .dev_start            = ixgbevf_dev_start,
 573         .dev_stop             = ixgbevf_dev_stop,
 574         .link_update          = ixgbevf_dev_link_update,
 575         .stats_get            = ixgbevf_dev_stats_get,
 576         .xstats_get           = ixgbevf_dev_xstats_get,
 577         .stats_reset          = ixgbevf_dev_stats_reset,
 578         .xstats_reset         = ixgbevf_dev_stats_reset,
 579         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 580         .dev_close            = ixgbevf_dev_close,
 581         .dev_reset            = ixgbevf_dev_reset,
 582         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 583         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 584         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 585         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 586         .dev_infos_get        = ixgbevf_dev_info_get,
 587         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 588         .mtu_set              = ixgbevf_dev_set_mtu,
 589         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 590         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 591         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 592         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 593         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 594         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 595         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 596         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 597         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 598         .mac_addr_add         = ixgbevf_add_mac_addr,
 599         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 600         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 601         .rxq_info_get         = ixgbe_rxq_info_get,
 602         .txq_info_get         = ixgbe_txq_info_get,
 603         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 604         .get_reg              = ixgbevf_get_regs,
 605         .reta_update          = ixgbe_dev_rss_reta_update,
 606         .reta_query           = ixgbe_dev_rss_reta_query,
 607         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 608         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 609         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 610 };
 611
 612 /* store statistics names and its offset in stats structure */
 613 struct rte_ixgbe_xstats_name_off {
 614         char name[RTE_ETH_XSTATS_NAME_SIZE];
 615         unsigned offset;
 616 };
 617
 618 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 619         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 620         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 621         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 622         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 623         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 624         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 625         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 626         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 627         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 628         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 629         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 630         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 631         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 632         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 633         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 634                 prc1023)},
 635         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 636                 prc1522)},
 637         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 638         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 639         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 640         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 641         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 642         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 643         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 644         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 645         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 646         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 647         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 648         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 649         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 650         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 651         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 652         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 653         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 654                 ptc1023)},
 655         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 656                 ptc1522)},
 657         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 658         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 659         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 660         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 661
 662         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 663                 fdirustat_add)},
 664         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 665                 fdirustat_remove)},
 666         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 667                 fdirfstat_fadd)},
 668         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 669                 fdirfstat_fremove)},
 670         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 671                 fdirmatch)},
 672         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 673                 fdirmiss)},
 674
 675         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 676         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 677         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 678                 fclast)},
 679         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 680         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 681         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 682         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 683         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 684                 fcoe_noddp)},
 685         {"rx_fcoe_no_direct_data_placement_ext_buff",
 686                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 687
 688         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 689                 lxontxc)},
 690         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 691                 lxonrxc)},
 692         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 693                 lxofftxc)},
 694         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 695                 lxoffrxc)},
 696         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 697 };
 698
 699 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 700                            sizeof(rte_ixgbe_stats_strings[0]))
 701
 702 /* MACsec statistics */
 703 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 704         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 705                 out_pkts_untagged)},
 706         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 707                 out_pkts_encrypted)},
 708         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 709                 out_pkts_protected)},
 710         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 711                 out_octets_encrypted)},
 712         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 713                 out_octets_protected)},
 714         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 715                 in_pkts_untagged)},
 716         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 717                 in_pkts_badtag)},
 718         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 719                 in_pkts_nosci)},
 720         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 721                 in_pkts_unknownsci)},
 722         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 723                 in_octets_decrypted)},
 724         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 725                 in_octets_validated)},
 726         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_unchecked)},
 728         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_delayed)},
 730         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_late)},
 732         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_ok)},
 734         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 735                 in_pkts_invalid)},
 736         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 737                 in_pkts_notvalid)},
 738         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_unusedsa)},
 740         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_notusingsa)},
 742 };
 743
 744 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 745                            sizeof(rte_ixgbe_macsec_strings[0]))
 746
 747 /* Per-queue statistics */
 748 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 749         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 750         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 751         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 752         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 753 };
 754
 755 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 756                            sizeof(rte_ixgbe_rxq_strings[0]))
 757 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 758
 759 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 760         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 761         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 762         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 763                 pxon2offc)},
 764 };
 765
 766 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 767                            sizeof(rte_ixgbe_txq_strings[0]))
 768 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 769
 770 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 771         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 772 };
 773
 774 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 775                 sizeof(rte_ixgbevf_stats_strings[0]))
 776
 777 /*
 778  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 779  */
 780 static inline int
 781 ixgbe_is_sfp(struct ixgbe_hw *hw)
 782 {
 783         switch (hw->phy.type) {
 784         case ixgbe_phy_sfp_avago:
 785         case ixgbe_phy_sfp_ftl:
 786         case ixgbe_phy_sfp_intel:
 787         case ixgbe_phy_sfp_unknown:
 788         case ixgbe_phy_sfp_passive_tyco:
 789         case ixgbe_phy_sfp_passive_unknown:
 790                 return 1;
 791         default:
 792                 return 0;
 793         }
 794 }
 795
 796 static inline int32_t
 797 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 798 {
 799         uint32_t ctrl_ext;
 800         int32_t status;
 801
 802         status = ixgbe_reset_hw(hw);
 803
 804         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 805         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 806         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 807         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 808         IXGBE_WRITE_FLUSH(hw);
 809
 810         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 811                 status = IXGBE_SUCCESS;
 812         return status;
 813 }
 814
 815 static inline void
 816 ixgbe_enable_intr(struct rte_eth_dev *dev)
 817 {
 818         struct ixgbe_interrupt *intr =
 819                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 820         struct ixgbe_hw *hw =
 821                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 822
 823         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 824         IXGBE_WRITE_FLUSH(hw);
 825 }
 826
 827 /*
 828  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 829  */
 830 static void
 831 ixgbe_disable_intr(struct ixgbe_hw *hw)
 832 {
 833         PMD_INIT_FUNC_TRACE();
 834
 835         if (hw->mac.type == ixgbe_mac_82598EB) {
 836                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 837         } else {
 838                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 839                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 840                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 841         }
 842         IXGBE_WRITE_FLUSH(hw);
 843 }
 844
 845 /*
 846  * This function resets queue statistics mapping registers.
 847  * From Niantic datasheet, Initialization of Statistics section:
 848  * "...if software requires the queue counters, the RQSMR and TQSM registers
 849  * must be re-programmed following a device reset.
 850  */
 851 static void
 852 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 853 {
 854         uint32_t i;
 855
 856         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 857                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 858                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 859         }
 860 }
 861
 862
 863 static int
 864 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 865                                   uint16_t queue_id,
 866                                   uint8_t stat_idx,
 867                                   uint8_t is_rx)
 868 {
 869 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 870 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 871 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 872
 873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 874         struct ixgbe_stat_mapping_registers *stat_mappings =
 875                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 876         uint32_t qsmr_mask = 0;
 877         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 878         uint32_t q_map;
 879         uint8_t n, offset;
 880
 881         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 882                 (hw->mac.type != ixgbe_mac_X540) &&
 883                 (hw->mac.type != ixgbe_mac_X550) &&
 884                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 885                 (hw->mac.type != ixgbe_mac_X550EM_a))
 886                 return -ENOSYS;
 887
 888         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 889                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 890                      queue_id, stat_idx);
 891
 892         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 893         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 894                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 895                 return -EIO;
 896         }
 897         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 898
 899         /* Now clear any previous stat_idx set */
 900         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 901         if (!is_rx)
 902                 stat_mappings->tqsm[n] &= ~clearing_mask;
 903         else
 904                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 905
 906         q_map = (uint32_t)stat_idx;
 907         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 908         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 909         if (!is_rx)
 910                 stat_mappings->tqsm[n] |= qsmr_mask;
 911         else
 912                 stat_mappings->rqsmr[n] |= qsmr_mask;
 913
 914         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 915                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 916                      queue_id, stat_idx);
 917         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 918                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 919
 920         /* Now write the mapping in the appropriate register */
 921         if (is_rx) {
 922                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 923                              stat_mappings->rqsmr[n], n);
 924                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 925         } else {
 926                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 927                              stat_mappings->tqsm[n], n);
 928                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 929         }
 930         return 0;
 931 }
 932
 933 static void
 934 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 935 {
 936         struct ixgbe_stat_mapping_registers *stat_mappings =
 937                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 939         int i;
 940
 941         /* write whatever was in stat mapping table to the NIC */
 942         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 943                 /* rx */
 944                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 945
 946                 /* tx */
 947                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 948         }
 949 }
 950
 951 static void
 952 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 953 {
 954         uint8_t i;
 955         struct ixgbe_dcb_tc_config *tc;
 956         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 957
 958         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 959         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 960         for (i = 0; i < dcb_max_tc; i++) {
 961                 tc = &dcb_config->tc_config[i];
 962                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 963                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 964                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 965                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 966                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 967                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 968                 tc->pfc = ixgbe_dcb_pfc_disabled;
 969         }
 970
 971         /* Initialize default user to priority mapping, UPx->TC0 */
 972         tc = &dcb_config->tc_config[0];
 973         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 974         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 975         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 976                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 977                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 978         }
 979         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 980         dcb_config->pfc_mode_enable = false;
 981         dcb_config->vt_mode = true;
 982         dcb_config->round_robin_enable = false;
 983         /* support all DCB capabilities in 82599 */
 984         dcb_config->support.capabilities = 0xFF;
 985
 986         /*we only support 4 Tcs for X540, X550 */
 987         if (hw->mac.type == ixgbe_mac_X540 ||
 988                 hw->mac.type == ixgbe_mac_X550 ||
 989                 hw->mac.type == ixgbe_mac_X550EM_x ||
 990                 hw->mac.type == ixgbe_mac_X550EM_a) {
 991                 dcb_config->num_tcs.pg_tcs = 4;
 992                 dcb_config->num_tcs.pfc_tcs = 4;
 993         }
 994 }
 995
 996 /*
 997  * Ensure that all locks are released before first NVM or PHY access
 998  */
 999 static void
1000 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1001 {
1002         uint16_t mask;
1003
1004         /*
1005          * Phy lock should not fail in this early stage. If this is the case,
1006          * it is due to an improper exit of the application.
1007          * So force the release of the faulty lock. Release of common lock
1008          * is done automatically by swfw_sync function.
1009          */
1010         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1011         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1012                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1013         }
1014         ixgbe_release_swfw_semaphore(hw, mask);
1015
1016         /*
1017          * These ones are more tricky since they are common to all ports; but
1018          * swfw_sync retries last long enough (1s) to be almost sure that if
1019          * lock can not be taken it is due to an improper lock of the
1020          * semaphore.
1021          */
1022         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1023         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1024                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1025         }
1026         ixgbe_release_swfw_semaphore(hw, mask);
1027 }
1028
1029 /*
1030  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1031  * It returns 0 on success.
1032  */
1033 static int
1034 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1035 {
1036         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1037         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1038         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1039         struct ixgbe_hw *hw =
1040                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1041         struct ixgbe_vfta *shadow_vfta =
1042                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1043         struct ixgbe_hwstrip *hwstrip =
1044                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1045         struct ixgbe_dcb_config *dcb_config =
1046                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1047         struct ixgbe_filter_info *filter_info =
1048                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1049         struct ixgbe_bw_conf *bw_conf =
1050                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1051         uint32_t ctrl_ext;
1052         uint16_t csum;
1053         int diag, i, ret;
1054
1055         PMD_INIT_FUNC_TRACE();
1056
1057         ixgbe_dev_macsec_setting_reset(eth_dev);
1058
1059         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1060         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1061         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1062         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1063         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1064         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1065         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1066         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1067
1068         /*
1069          * For secondary processes, we don't initialise any further as primary
1070          * has already done this work. Only check we don't need a different
1071          * RX and TX function.
1072          */
1073         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1074                 struct ixgbe_tx_queue *txq;
1075                 /* TX queue function in primary, set by last queue initialized
1076                  * Tx queue may not initialized by primary process
1077                  */
1078                 if (eth_dev->data->tx_queues) {
1079                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1080                         ixgbe_set_tx_function(eth_dev, txq);
1081                 } else {
1082                         /* Use default TX function if we get here */
1083                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1084                                      "Using default TX function.");
1085                 }
1086
1087                 ixgbe_set_rx_function(eth_dev);
1088
1089                 return 0;
1090         }
1091
1092         rte_atomic32_clear(&ad->link_thread_running);
1093         rte_eth_copy_pci_info(eth_dev, pci_dev);
1094         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1095
1096         /* Vendor and Device ID need to be set before init of shared code */
1097         hw->device_id = pci_dev->id.device_id;
1098         hw->vendor_id = pci_dev->id.vendor_id;
1099         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1100         hw->allow_unsupported_sfp = 1;
1101
1102         /* Initialize the shared code (base driver) */
1103 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1104         diag = ixgbe_bypass_init_shared_code(hw);
1105 #else
1106         diag = ixgbe_init_shared_code(hw);
1107 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1108
1109         if (diag != IXGBE_SUCCESS) {
1110                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1111                 return -EIO;
1112         }
1113
1114         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1115                 PMD_INIT_LOG(ERR, "\nERROR: "
1116                         "Firmware recovery mode detected. Limiting functionality.\n"
1117                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1118                         "User Guide for details on firmware recovery mode.");
1119                 return -EIO;
1120         }
1121
1122         /* pick up the PCI bus settings for reporting later */
1123         ixgbe_get_bus_info(hw);
1124
1125         /* Unlock any pending hardware semaphore */
1126         ixgbe_swfw_lock_reset(hw);
1127
1128 #ifdef RTE_LIB_SECURITY
1129         /* Initialize security_ctx only for primary process*/
1130         if (ixgbe_ipsec_ctx_create(eth_dev))
1131                 return -ENOMEM;
1132 #endif
1133
1134         /* Initialize DCB configuration*/
1135         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1136         ixgbe_dcb_init(hw, dcb_config);
1137         /* Get Hardware Flow Control setting */
1138         hw->fc.requested_mode = ixgbe_fc_none;
1139         hw->fc.current_mode = ixgbe_fc_none;
1140         hw->fc.pause_time = IXGBE_FC_PAUSE;
1141         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1142                 hw->fc.low_water[i] = IXGBE_FC_LO;
1143                 hw->fc.high_water[i] = IXGBE_FC_HI;
1144         }
1145         hw->fc.send_xon = 1;
1146
1147         /* Make sure we have a good EEPROM before we read from it */
1148         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1149         if (diag != IXGBE_SUCCESS) {
1150                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1151                 return -EIO;
1152         }
1153
1154 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1155         diag = ixgbe_bypass_init_hw(hw);
1156 #else
1157         diag = ixgbe_init_hw(hw);
1158 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1159
1160         /*
1161          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1162          * is called too soon after the kernel driver unbinding/binding occurs.
1163          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1164          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1165          * also called. See ixgbe_identify_phy_82599(). The reason for the
1166          * failure is not known, and only occuts when virtualisation features
1167          * are disabled in the bios. A delay of 100ms  was found to be enough by
1168          * trial-and-error, and is doubled to be safe.
1169          */
1170         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1171                 rte_delay_ms(200);
1172                 diag = ixgbe_init_hw(hw);
1173         }
1174
1175         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1176                 diag = IXGBE_SUCCESS;
1177
1178         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1179                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1180                              "LOM.  Please be aware there may be issues associated "
1181                              "with your hardware.");
1182                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1183                              "please contact your Intel or hardware representative "
1184                              "who provided you with this hardware.");
1185         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1186                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1187         if (diag) {
1188                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1189                 return -EIO;
1190         }
1191
1192         /* Reset the hw statistics */
1193         ixgbe_dev_stats_reset(eth_dev);
1194
1195         /* disable interrupt */
1196         ixgbe_disable_intr(hw);
1197
1198         /* reset mappings for queue statistics hw counters*/
1199         ixgbe_reset_qstat_mappings(hw);
1200
1201         /* Allocate memory for storing MAC addresses */
1202         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1203                                                hw->mac.num_rar_entries, 0);
1204         if (eth_dev->data->mac_addrs == NULL) {
1205                 PMD_INIT_LOG(ERR,
1206                              "Failed to allocate %u bytes needed to store "
1207                              "MAC addresses",
1208                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1209                 return -ENOMEM;
1210         }
1211         /* Copy the permanent MAC address */
1212         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1213                         &eth_dev->data->mac_addrs[0]);
1214
1215         /* Allocate memory for storing hash filter MAC addresses */
1216         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1217                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1218         if (eth_dev->data->hash_mac_addrs == NULL) {
1219                 PMD_INIT_LOG(ERR,
1220                              "Failed to allocate %d bytes needed to store MAC addresses",
1221                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1222                 return -ENOMEM;
1223         }
1224
1225         /* initialize the vfta */
1226         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1227
1228         /* initialize the hw strip bitmap*/
1229         memset(hwstrip, 0, sizeof(*hwstrip));
1230
1231         /* initialize PF if max_vfs not zero */
1232         ret = ixgbe_pf_host_init(eth_dev);
1233         if (ret) {
1234                 rte_free(eth_dev->data->mac_addrs);
1235                 eth_dev->data->mac_addrs = NULL;
1236                 rte_free(eth_dev->data->hash_mac_addrs);
1237                 eth_dev->data->hash_mac_addrs = NULL;
1238                 return ret;
1239         }
1240
1241         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1242         /* let hardware know driver is loaded */
1243         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1244         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1245         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1246         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1247         IXGBE_WRITE_FLUSH(hw);
1248
1249         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1250                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1251                              (int) hw->mac.type, (int) hw->phy.type,
1252                              (int) hw->phy.sfp_type);
1253         else
1254                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1255                              (int) hw->mac.type, (int) hw->phy.type);
1256
1257         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1258                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1259                      pci_dev->id.device_id);
1260
1261         rte_intr_callback_register(intr_handle,
1262                                    ixgbe_dev_interrupt_handler, eth_dev);
1263
1264         /* enable uio/vfio intr/eventfd mapping */
1265         rte_intr_enable(intr_handle);
1266
1267         /* enable support intr */
1268         ixgbe_enable_intr(eth_dev);
1269
1270         /* initialize filter info */
1271         memset(filter_info, 0,
1272                sizeof(struct ixgbe_filter_info));
1273
1274         /* initialize 5tuple filter list */
1275         TAILQ_INIT(&filter_info->fivetuple_list);
1276
1277         /* initialize flow director filter list & hash */
1278         ixgbe_fdir_filter_init(eth_dev);
1279
1280         /* initialize l2 tunnel filter list & hash */
1281         ixgbe_l2_tn_filter_init(eth_dev);
1282
1283         /* initialize flow filter lists */
1284         ixgbe_filterlist_init();
1285
1286         /* initialize bandwidth configuration info */
1287         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1288
1289         /* initialize Traffic Manager configuration */
1290         ixgbe_tm_conf_init(eth_dev);
1291
1292         return 0;
1293 }
1294
1295 static int
1296 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1297 {
1298         PMD_INIT_FUNC_TRACE();
1299
1300         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1301                 return 0;
1302
1303         ixgbe_dev_close(eth_dev);
1304
1305         return 0;
1306 }
1307
1308 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1309 {
1310         struct ixgbe_filter_info *filter_info =
1311                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1312         struct ixgbe_5tuple_filter *p_5tuple;
1313
1314         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1315                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1316                              p_5tuple,
1317                              entries);
1318                 rte_free(p_5tuple);
1319         }
1320         memset(filter_info->fivetuple_mask, 0,
1321                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1322
1323         return 0;
1324 }
1325
1326 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1327 {
1328         struct ixgbe_hw_fdir_info *fdir_info =
1329                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1330         struct ixgbe_fdir_filter *fdir_filter;
1331
1332                 if (fdir_info->hash_map)
1333                 rte_free(fdir_info->hash_map);
1334         if (fdir_info->hash_handle)
1335                 rte_hash_free(fdir_info->hash_handle);
1336
1337         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1338                 TAILQ_REMOVE(&fdir_info->fdir_list,
1339                              fdir_filter,
1340                              entries);
1341                 rte_free(fdir_filter);
1342         }
1343
1344         return 0;
1345 }
1346
1347 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1348 {
1349         struct ixgbe_l2_tn_info *l2_tn_info =
1350                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1351         struct ixgbe_l2_tn_filter *l2_tn_filter;
1352
1353         if (l2_tn_info->hash_map)
1354                 rte_free(l2_tn_info->hash_map);
1355         if (l2_tn_info->hash_handle)
1356                 rte_hash_free(l2_tn_info->hash_handle);
1357
1358         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1359                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1360                              l2_tn_filter,
1361                              entries);
1362                 rte_free(l2_tn_filter);
1363         }
1364
1365         return 0;
1366 }
1367
1368 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1369 {
1370         struct ixgbe_hw_fdir_info *fdir_info =
1371                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1372         char fdir_hash_name[RTE_HASH_NAMESIZE];
1373         struct rte_hash_parameters fdir_hash_params = {
1374                 .name = fdir_hash_name,
1375                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1376                 .key_len = sizeof(union ixgbe_atr_input),
1377                 .hash_func = rte_hash_crc,
1378                 .hash_func_init_val = 0,
1379                 .socket_id = rte_socket_id(),
1380         };
1381
1382         TAILQ_INIT(&fdir_info->fdir_list);
1383         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1384                  "fdir_%s", eth_dev->device->name);
1385         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1386         if (!fdir_info->hash_handle) {
1387                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1388                 return -EINVAL;
1389         }
1390         fdir_info->hash_map = rte_zmalloc("ixgbe",
1391                                           sizeof(struct ixgbe_fdir_filter *) *
1392                                           IXGBE_MAX_FDIR_FILTER_NUM,
1393                                           0);
1394         if (!fdir_info->hash_map) {
1395                 PMD_INIT_LOG(ERR,
1396                              "Failed to allocate memory for fdir hash map!");
1397                 return -ENOMEM;
1398         }
1399         fdir_info->mask_added = FALSE;
1400
1401         return 0;
1402 }
1403
1404 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1405 {
1406         struct ixgbe_l2_tn_info *l2_tn_info =
1407                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1408         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1409         struct rte_hash_parameters l2_tn_hash_params = {
1410                 .name = l2_tn_hash_name,
1411                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1412                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1413                 .hash_func = rte_hash_crc,
1414                 .hash_func_init_val = 0,
1415                 .socket_id = rte_socket_id(),
1416         };
1417
1418         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1419         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1420                  "l2_tn_%s", eth_dev->device->name);
1421         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1422         if (!l2_tn_info->hash_handle) {
1423                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1424                 return -EINVAL;
1425         }
1426         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1427                                    sizeof(struct ixgbe_l2_tn_filter *) *
1428                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1429                                    0);
1430         if (!l2_tn_info->hash_map) {
1431                 PMD_INIT_LOG(ERR,
1432                         "Failed to allocate memory for L2 TN hash map!");
1433                 return -ENOMEM;
1434         }
1435         l2_tn_info->e_tag_en = FALSE;
1436         l2_tn_info->e_tag_fwd_en = FALSE;
1437         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1438
1439         return 0;
1440 }
1441 /*
1442  * Negotiate mailbox API version with the PF.
1443  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1444  * Then we try to negotiate starting with the most recent one.
1445  * If all negotiation attempts fail, then we will proceed with
1446  * the default one (ixgbe_mbox_api_10).
1447  */
1448 static void
1449 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1450 {
1451         int32_t i;
1452
1453         /* start with highest supported, proceed down */
1454         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1455                 ixgbe_mbox_api_13,
1456                 ixgbe_mbox_api_12,
1457                 ixgbe_mbox_api_11,
1458                 ixgbe_mbox_api_10,
1459         };
1460
1461         for (i = 0;
1462                         i != RTE_DIM(sup_ver) &&
1463                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1464                         i++)
1465                 ;
1466 }
1467
1468 static void
1469 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1470 {
1471         uint64_t random;
1472
1473         /* Set Organizationally Unique Identifier (OUI) prefix. */
1474         mac_addr->addr_bytes[0] = 0x00;
1475         mac_addr->addr_bytes[1] = 0x09;
1476         mac_addr->addr_bytes[2] = 0xC0;
1477         /* Force indication of locally assigned MAC address. */
1478         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1479         /* Generate the last 3 bytes of the MAC address with a random number. */
1480         random = rte_rand();
1481         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1482 }
1483
1484 static int
1485 devarg_handle_int(__rte_unused const char *key, const char *value,
1486                   void *extra_args)
1487 {
1488         uint16_t *n = extra_args;
1489
1490         if (value == NULL || extra_args == NULL)
1491                 return -EINVAL;
1492
1493         *n = (uint16_t)strtoul(value, NULL, 0);
1494         if (*n == USHRT_MAX && errno == ERANGE)
1495                 return -1;
1496
1497         return 0;
1498 }
1499
1500 static void
1501 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1502                       struct rte_devargs *devargs)
1503 {
1504         struct rte_kvargs *kvlist;
1505         uint16_t pflink_fullchk;
1506
1507         if (devargs == NULL)
1508                 return;
1509
1510         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1511         if (kvlist == NULL)
1512                 return;
1513
1514         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1515             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1516                                devarg_handle_int, &pflink_fullchk) == 0 &&
1517             pflink_fullchk == 1)
1518                 adapter->pflink_fullchk = 1;
1519
1520         rte_kvargs_free(kvlist);
1521 }
1522
1523 /*
1524  * Virtual Function device init
1525  */
1526 static int
1527 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1528 {
1529         int diag;
1530         uint32_t tc, tcs;
1531         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1532         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1533         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1534         struct ixgbe_hw *hw =
1535                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1536         struct ixgbe_vfta *shadow_vfta =
1537                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1538         struct ixgbe_hwstrip *hwstrip =
1539                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1540         struct rte_ether_addr *perm_addr =
1541                 (struct rte_ether_addr *)hw->mac.perm_addr;
1542
1543         PMD_INIT_FUNC_TRACE();
1544
1545         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1546         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1547         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1548         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1549         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1550         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1551
1552         /* for secondary processes, we don't initialise any further as primary
1553          * has already done this work. Only check we don't need a different
1554          * RX function
1555          */
1556         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1557                 struct ixgbe_tx_queue *txq;
1558                 /* TX queue function in primary, set by last queue initialized
1559                  * Tx queue may not initialized by primary process
1560                  */
1561                 if (eth_dev->data->tx_queues) {
1562                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1563                         ixgbe_set_tx_function(eth_dev, txq);
1564                 } else {
1565                         /* Use default TX function if we get here */
1566                         PMD_INIT_LOG(NOTICE,
1567                                      "No TX queues configured yet. Using default TX function.");
1568                 }
1569
1570                 ixgbe_set_rx_function(eth_dev);
1571
1572                 return 0;
1573         }
1574
1575         rte_atomic32_clear(&ad->link_thread_running);
1576         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1577                               pci_dev->device.devargs);
1578
1579         rte_eth_copy_pci_info(eth_dev, pci_dev);
1580         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1581
1582         hw->device_id = pci_dev->id.device_id;
1583         hw->vendor_id = pci_dev->id.vendor_id;
1584         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1585
1586         /* initialize the vfta */
1587         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1588
1589         /* initialize the hw strip bitmap*/
1590         memset(hwstrip, 0, sizeof(*hwstrip));
1591
1592         /* Initialize the shared code (base driver) */
1593         diag = ixgbe_init_shared_code(hw);
1594         if (diag != IXGBE_SUCCESS) {
1595                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1596                 return -EIO;
1597         }
1598
1599         /* init_mailbox_params */
1600         hw->mbx.ops.init_params(hw);
1601
1602         /* Reset the hw statistics */
1603         ixgbevf_dev_stats_reset(eth_dev);
1604
1605         /* Disable the interrupts for VF */
1606         ixgbevf_intr_disable(eth_dev);
1607
1608         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1609         diag = hw->mac.ops.reset_hw(hw);
1610
1611         /*
1612          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1613          * the underlying PF driver has not assigned a MAC address to the VF.
1614          * In this case, assign a random MAC address.
1615          */
1616         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1617                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1618                 /*
1619                  * This error code will be propagated to the app by
1620                  * rte_eth_dev_reset, so use a public error code rather than
1621                  * the internal-only IXGBE_ERR_RESET_FAILED
1622                  */
1623                 return -EAGAIN;
1624         }
1625
1626         /* negotiate mailbox API version to use with the PF. */
1627         ixgbevf_negotiate_api(hw);
1628
1629         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1630         ixgbevf_get_queues(hw, &tcs, &tc);
1631
1632         /* Allocate memory for storing MAC addresses */
1633         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1634                                                hw->mac.num_rar_entries, 0);
1635         if (eth_dev->data->mac_addrs == NULL) {
1636                 PMD_INIT_LOG(ERR,
1637                              "Failed to allocate %u bytes needed to store "
1638                              "MAC addresses",
1639                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1640                 return -ENOMEM;
1641         }
1642
1643         /* Generate a random MAC address, if none was assigned by PF. */
1644         if (rte_is_zero_ether_addr(perm_addr)) {
1645                 generate_random_mac_addr(perm_addr);
1646                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1647                 if (diag) {
1648                         rte_free(eth_dev->data->mac_addrs);
1649                         eth_dev->data->mac_addrs = NULL;
1650                         return diag;
1651                 }
1652                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1653                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1654                              "%02x:%02x:%02x:%02x:%02x:%02x",
1655                              perm_addr->addr_bytes[0],
1656                              perm_addr->addr_bytes[1],
1657                              perm_addr->addr_bytes[2],
1658                              perm_addr->addr_bytes[3],
1659                              perm_addr->addr_bytes[4],
1660                              perm_addr->addr_bytes[5]);
1661         }
1662
1663         /* Copy the permanent MAC address */
1664         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1665
1666         /* reset the hardware with the new settings */
1667         diag = hw->mac.ops.start_hw(hw);
1668         switch (diag) {
1669         case  0:
1670                 break;
1671
1672         default:
1673                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1674                 return -EIO;
1675         }
1676
1677         rte_intr_callback_register(intr_handle,
1678                                    ixgbevf_dev_interrupt_handler, eth_dev);
1679         rte_intr_enable(intr_handle);
1680         ixgbevf_intr_enable(eth_dev);
1681
1682         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1683                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1684                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1685
1686         return 0;
1687 }
1688
1689 /* Virtual Function device uninit */
1690
1691 static int
1692 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1693 {
1694         PMD_INIT_FUNC_TRACE();
1695
1696         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1697                 return 0;
1698
1699         ixgbevf_dev_close(eth_dev);
1700
1701         return 0;
1702 }
1703
1704 static int
1705 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1706                 struct rte_pci_device *pci_dev)
1707 {
1708         char name[RTE_ETH_NAME_MAX_LEN];
1709         struct rte_eth_dev *pf_ethdev;
1710         struct rte_eth_devargs eth_da;
1711         int i, retval;
1712
1713         if (pci_dev->device.devargs) {
1714                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1715                                 &eth_da);
1716                 if (retval)
1717                         return retval;
1718         } else
1719                 memset(&eth_da, 0, sizeof(eth_da));
1720
1721         if (eth_da.nb_representor_ports > 0 &&
1722             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
1723                 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
1724                             pci_dev->device.devargs->args);
1725                 return -ENOTSUP;
1726         }
1727
1728         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1729                 sizeof(struct ixgbe_adapter),
1730                 eth_dev_pci_specific_init, pci_dev,
1731                 eth_ixgbe_dev_init, NULL);
1732
1733         if (retval || eth_da.nb_representor_ports < 1)
1734                 return retval;
1735
1736         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1737         if (pf_ethdev == NULL)
1738                 return -ENODEV;
1739
1740         /* probe VF representor ports */
1741         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1742                 struct ixgbe_vf_info *vfinfo;
1743                 struct ixgbe_vf_representor representor;
1744
1745                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1746                         pf_ethdev->data->dev_private);
1747                 if (vfinfo == NULL) {
1748                         PMD_DRV_LOG(ERR,
1749                                 "no virtual functions supported by PF");
1750                         break;
1751                 }
1752
1753                 representor.vf_id = eth_da.representor_ports[i];
1754                 representor.switch_domain_id = vfinfo->switch_domain_id;
1755                 representor.pf_ethdev = pf_ethdev;
1756
1757                 /* representor port net_bdf_port */
1758                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1759                         pci_dev->device.name,
1760                         eth_da.representor_ports[i]);
1761
1762                 retval = rte_eth_dev_create(&pci_dev->device, name,
1763                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1764                         ixgbe_vf_representor_init, &representor);
1765
1766                 if (retval)
1767                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1768                                 "representor %s.", name);
1769         }
1770
1771         return 0;
1772 }
1773
1774 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1775 {
1776         struct rte_eth_dev *ethdev;
1777
1778         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1779         if (!ethdev)
1780                 return 0;
1781
1782         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1783                 return rte_eth_dev_pci_generic_remove(pci_dev,
1784                                         ixgbe_vf_representor_uninit);
1785         else
1786                 return rte_eth_dev_pci_generic_remove(pci_dev,
1787                                                 eth_ixgbe_dev_uninit);
1788 }
1789
1790 static struct rte_pci_driver rte_ixgbe_pmd = {
1791         .id_table = pci_id_ixgbe_map,
1792         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1793         .probe = eth_ixgbe_pci_probe,
1794         .remove = eth_ixgbe_pci_remove,
1795 };
1796
1797 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1798         struct rte_pci_device *pci_dev)
1799 {
1800         return rte_eth_dev_pci_generic_probe(pci_dev,
1801                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1802 }
1803
1804 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1805 {
1806         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1807 }
1808
1809 /*
1810  * virtual function driver struct
1811  */
1812 static struct rte_pci_driver rte_ixgbevf_pmd = {
1813         .id_table = pci_id_ixgbevf_map,
1814         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1815         .probe = eth_ixgbevf_pci_probe,
1816         .remove = eth_ixgbevf_pci_remove,
1817 };
1818
1819 static int
1820 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1821 {
1822         struct ixgbe_hw *hw =
1823                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1824         struct ixgbe_vfta *shadow_vfta =
1825                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1826         uint32_t vfta;
1827         uint32_t vid_idx;
1828         uint32_t vid_bit;
1829
1830         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1831         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1832         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1833         if (on)
1834                 vfta |= vid_bit;
1835         else
1836                 vfta &= ~vid_bit;
1837         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1838
1839         /* update local VFTA copy */
1840         shadow_vfta->vfta[vid_idx] = vfta;
1841
1842         return 0;
1843 }
1844
1845 static void
1846 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1847 {
1848         if (on)
1849                 ixgbe_vlan_hw_strip_enable(dev, queue);
1850         else
1851                 ixgbe_vlan_hw_strip_disable(dev, queue);
1852 }
1853
1854 static int
1855 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1856                     enum rte_vlan_type vlan_type,
1857                     uint16_t tpid)
1858 {
1859         struct ixgbe_hw *hw =
1860                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1861         int ret = 0;
1862         uint32_t reg;
1863         uint32_t qinq;
1864
1865         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1866         qinq &= IXGBE_DMATXCTL_GDV;
1867
1868         switch (vlan_type) {
1869         case ETH_VLAN_TYPE_INNER:
1870                 if (qinq) {
1871                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1872                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1873                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1874                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1875                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1876                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1877                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1878                 } else {
1879                         ret = -ENOTSUP;
1880                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1881                                     " by single VLAN");
1882                 }
1883                 break;
1884         case ETH_VLAN_TYPE_OUTER:
1885                 if (qinq) {
1886                         /* Only the high 16-bits is valid */
1887                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1888                                         IXGBE_EXVET_VET_EXT_SHIFT);
1889                 } else {
1890                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1891                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1892                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1893                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1894                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1895                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1896                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1897                 }
1898
1899                 break;
1900         default:
1901                 ret = -EINVAL;
1902                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1903                 break;
1904         }
1905
1906         return ret;
1907 }
1908
1909 void
1910 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1911 {
1912         struct ixgbe_hw *hw =
1913                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1914         uint32_t vlnctrl;
1915
1916         PMD_INIT_FUNC_TRACE();
1917
1918         /* Filter Table Disable */
1919         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1920         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1921
1922         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1923 }
1924
1925 void
1926 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1927 {
1928         struct ixgbe_hw *hw =
1929                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         struct ixgbe_vfta *shadow_vfta =
1931                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1932         uint32_t vlnctrl;
1933         uint16_t i;
1934
1935         PMD_INIT_FUNC_TRACE();
1936
1937         /* Filter Table Enable */
1938         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1939         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1940         vlnctrl |= IXGBE_VLNCTRL_VFE;
1941
1942         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1943
1944         /* write whatever is in local vfta copy */
1945         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1946                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1947 }
1948
1949 static void
1950 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1951 {
1952         struct ixgbe_hwstrip *hwstrip =
1953                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1954         struct ixgbe_rx_queue *rxq;
1955
1956         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1957                 return;
1958
1959         if (on)
1960                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1961         else
1962                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1963
1964         if (queue >= dev->data->nb_rx_queues)
1965                 return;
1966
1967         rxq = dev->data->rx_queues[queue];
1968
1969         if (on) {
1970                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1971                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1972         } else {
1973                 rxq->vlan_flags = PKT_RX_VLAN;
1974                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1975         }
1976 }
1977
1978 static void
1979 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1980 {
1981         struct ixgbe_hw *hw =
1982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983         uint32_t ctrl;
1984
1985         PMD_INIT_FUNC_TRACE();
1986
1987         if (hw->mac.type == ixgbe_mac_82598EB) {
1988                 /* No queue level support */
1989                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1990                 return;
1991         }
1992
1993         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1994         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1995         ctrl &= ~IXGBE_RXDCTL_VME;
1996         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1997
1998         /* record those setting for HW strip per queue */
1999         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2000 }
2001
2002 static void
2003 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2004 {
2005         struct ixgbe_hw *hw =
2006                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2007         uint32_t ctrl;
2008
2009         PMD_INIT_FUNC_TRACE();
2010
2011         if (hw->mac.type == ixgbe_mac_82598EB) {
2012                 /* No queue level supported */
2013                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2014                 return;
2015         }
2016
2017         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2018         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2019         ctrl |= IXGBE_RXDCTL_VME;
2020         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2021
2022         /* record those setting for HW strip per queue */
2023         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2024 }
2025
2026 static void
2027 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2028 {
2029         struct ixgbe_hw *hw =
2030                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031         uint32_t ctrl;
2032
2033         PMD_INIT_FUNC_TRACE();
2034
2035         /* DMATXCTRL: Geric Double VLAN Disable */
2036         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2037         ctrl &= ~IXGBE_DMATXCTL_GDV;
2038         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2039
2040         /* CTRL_EXT: Global Double VLAN Disable */
2041         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2042         ctrl &= ~IXGBE_EXTENDED_VLAN;
2043         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2044
2045 }
2046
2047 static void
2048 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2049 {
2050         struct ixgbe_hw *hw =
2051                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052         uint32_t ctrl;
2053
2054         PMD_INIT_FUNC_TRACE();
2055
2056         /* DMATXCTRL: Geric Double VLAN Enable */
2057         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2058         ctrl |= IXGBE_DMATXCTL_GDV;
2059         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2060
2061         /* CTRL_EXT: Global Double VLAN Enable */
2062         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2063         ctrl |= IXGBE_EXTENDED_VLAN;
2064         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2065
2066         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2067         if (hw->mac.type == ixgbe_mac_X550 ||
2068             hw->mac.type == ixgbe_mac_X550EM_x ||
2069             hw->mac.type == ixgbe_mac_X550EM_a) {
2070                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2071                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2072                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2073         }
2074
2075         /*
2076          * VET EXT field in the EXVET register = 0x8100 by default
2077          * So no need to change. Same to VT field of DMATXCTL register
2078          */
2079 }
2080
2081 void
2082 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2083 {
2084         struct ixgbe_hw *hw =
2085                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2086         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2087         uint32_t ctrl;
2088         uint16_t i;
2089         struct ixgbe_rx_queue *rxq;
2090         bool on;
2091
2092         PMD_INIT_FUNC_TRACE();
2093
2094         if (hw->mac.type == ixgbe_mac_82598EB) {
2095                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2096                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2097                         ctrl |= IXGBE_VLNCTRL_VME;
2098                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2099                 } else {
2100                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2101                         ctrl &= ~IXGBE_VLNCTRL_VME;
2102                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2103                 }
2104         } else {
2105                 /*
2106                  * Other 10G NIC, the VLAN strip can be setup
2107                  * per queue in RXDCTL
2108                  */
2109                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2110                         rxq = dev->data->rx_queues[i];
2111                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2112                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2113                                 ctrl |= IXGBE_RXDCTL_VME;
2114                                 on = TRUE;
2115                         } else {
2116                                 ctrl &= ~IXGBE_RXDCTL_VME;
2117                                 on = FALSE;
2118                         }
2119                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2120
2121                         /* record those setting for HW strip per queue */
2122                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2123                 }
2124         }
2125 }
2126
2127 static void
2128 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2129 {
2130         uint16_t i;
2131         struct rte_eth_rxmode *rxmode;
2132         struct ixgbe_rx_queue *rxq;
2133
2134         if (mask & ETH_VLAN_STRIP_MASK) {
2135                 rxmode = &dev->data->dev_conf.rxmode;
2136                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2137                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2138                                 rxq = dev->data->rx_queues[i];
2139                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2140                         }
2141                 else
2142                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2143                                 rxq = dev->data->rx_queues[i];
2144                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2145                         }
2146         }
2147 }
2148
2149 static int
2150 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2151 {
2152         struct rte_eth_rxmode *rxmode;
2153         rxmode = &dev->data->dev_conf.rxmode;
2154
2155         if (mask & ETH_VLAN_STRIP_MASK) {
2156                 ixgbe_vlan_hw_strip_config(dev);
2157         }
2158
2159         if (mask & ETH_VLAN_FILTER_MASK) {
2160                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2161                         ixgbe_vlan_hw_filter_enable(dev);
2162                 else
2163                         ixgbe_vlan_hw_filter_disable(dev);
2164         }
2165
2166         if (mask & ETH_VLAN_EXTEND_MASK) {
2167                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2168                         ixgbe_vlan_hw_extend_enable(dev);
2169                 else
2170                         ixgbe_vlan_hw_extend_disable(dev);
2171         }
2172
2173         return 0;
2174 }
2175
2176 static int
2177 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2178 {
2179         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2180
2181         ixgbe_vlan_offload_config(dev, mask);
2182
2183         return 0;
2184 }
2185
2186 static void
2187 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2188 {
2189         struct ixgbe_hw *hw =
2190                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2191         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2192         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2193
2194         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2195         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2196 }
2197
2198 static int
2199 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2200 {
2201         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2202
2203         switch (nb_rx_q) {
2204         case 1:
2205         case 2:
2206                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2207                 break;
2208         case 4:
2209                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2210                 break;
2211         default:
2212                 return -EINVAL;
2213         }
2214
2215         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2216                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2217         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2218                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2219         return 0;
2220 }
2221
2222 static int
2223 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2224 {
2225         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2226         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2228         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2229
2230         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2231                 /* check multi-queue mode */
2232                 switch (dev_conf->rxmode.mq_mode) {
2233                 case ETH_MQ_RX_VMDQ_DCB:
2234                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2235                         break;
2236                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2237                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2238                         PMD_INIT_LOG(ERR, "SRIOV active,"
2239                                         " unsupported mq_mode rx %d.",
2240                                         dev_conf->rxmode.mq_mode);
2241                         return -EINVAL;
2242                 case ETH_MQ_RX_RSS:
2243                 case ETH_MQ_RX_VMDQ_RSS:
2244                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2245                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2246                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2247                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2248                                                 " invalid queue number"
2249                                                 " for VMDQ RSS, allowed"
2250                                                 " value are 1, 2 or 4.");
2251                                         return -EINVAL;
2252                                 }
2253                         break;
2254                 case ETH_MQ_RX_VMDQ_ONLY:
2255                 case ETH_MQ_RX_NONE:
2256                         /* if nothing mq mode configure, use default scheme */
2257                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2258                         break;
2259                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2260                         /* SRIOV only works in VMDq enable mode */
2261                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2262                                         " wrong mq_mode rx %d.",
2263                                         dev_conf->rxmode.mq_mode);
2264                         return -EINVAL;
2265                 }
2266
2267                 switch (dev_conf->txmode.mq_mode) {
2268                 case ETH_MQ_TX_VMDQ_DCB:
2269                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2270                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2271                         break;
2272                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2273                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2274                         break;
2275                 }
2276
2277                 /* check valid queue number */
2278                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2279                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2280                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2281                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2282                                         " must be less than or equal to %d.",
2283                                         nb_rx_q, nb_tx_q,
2284                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2285                         return -EINVAL;
2286                 }
2287         } else {
2288                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2289                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2290                                           " not supported.");
2291                         return -EINVAL;
2292                 }
2293                 /* check configuration for vmdb+dcb mode */
2294                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2295                         const struct rte_eth_vmdq_dcb_conf *conf;
2296
2297                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2298                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2299                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2300                                 return -EINVAL;
2301                         }
2302                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2303                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2304                                conf->nb_queue_pools == ETH_32_POOLS)) {
2305                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2306                                                 " nb_queue_pools must be %d or %d.",
2307                                                 ETH_16_POOLS, ETH_32_POOLS);
2308                                 return -EINVAL;
2309                         }
2310                 }
2311                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2312                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2313
2314                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2315                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2316                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2317                                 return -EINVAL;
2318                         }
2319                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2320                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2321                                conf->nb_queue_pools == ETH_32_POOLS)) {
2322                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2323                                                 " nb_queue_pools != %d and"
2324                                                 " nb_queue_pools != %d.",
2325                                                 ETH_16_POOLS, ETH_32_POOLS);
2326                                 return -EINVAL;
2327                         }
2328                 }
2329
2330                 /* For DCB mode check our configuration before we go further */
2331                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2332                         const struct rte_eth_dcb_rx_conf *conf;
2333
2334                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2335                         if (!(conf->nb_tcs == ETH_4_TCS ||
2336                                conf->nb_tcs == ETH_8_TCS)) {
2337                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2338                                                 " and nb_tcs != %d.",
2339                                                 ETH_4_TCS, ETH_8_TCS);
2340                                 return -EINVAL;
2341                         }
2342                 }
2343
2344                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2345                         const struct rte_eth_dcb_tx_conf *conf;
2346
2347                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2348                         if (!(conf->nb_tcs == ETH_4_TCS ||
2349                                conf->nb_tcs == ETH_8_TCS)) {
2350                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2351                                                 " and nb_tcs != %d.",
2352                                                 ETH_4_TCS, ETH_8_TCS);
2353                                 return -EINVAL;
2354                         }
2355                 }
2356
2357                 /*
2358                  * When DCB/VT is off, maximum number of queues changes,
2359                  * except for 82598EB, which remains constant.
2360                  */
2361                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2362                                 hw->mac.type != ixgbe_mac_82598EB) {
2363                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2364                                 PMD_INIT_LOG(ERR,
2365                                              "Neither VT nor DCB are enabled, "
2366                                              "nb_tx_q > %d.",
2367                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2368                                 return -EINVAL;
2369                         }
2370                 }
2371         }
2372         return 0;
2373 }
2374
2375 static int
2376 ixgbe_dev_configure(struct rte_eth_dev *dev)
2377 {
2378         struct ixgbe_interrupt *intr =
2379                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2380         struct ixgbe_adapter *adapter = dev->data->dev_private;
2381         int ret;
2382
2383         PMD_INIT_FUNC_TRACE();
2384
2385         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2386                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2387
2388         /* multipe queue mode checking */
2389         ret  = ixgbe_check_mq_mode(dev);
2390         if (ret != 0) {
2391                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2392                             ret);
2393                 return ret;
2394         }
2395
2396         /* set flag to update link status after init */
2397         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2398
2399         /*
2400          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2401          * allocation or vector Rx preconditions we will reset it.
2402          */
2403         adapter->rx_bulk_alloc_allowed = true;
2404         adapter->rx_vec_allowed = true;
2405
2406         return 0;
2407 }
2408
2409 static void
2410 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2411 {
2412         struct ixgbe_hw *hw =
2413                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414         struct ixgbe_interrupt *intr =
2415                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2416         uint32_t gpie;
2417
2418         /* only set up it on X550EM_X */
2419         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2420                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2421                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2422                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2423                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2424                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2425         }
2426 }
2427
2428 int
2429 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2430                         uint16_t tx_rate, uint64_t q_msk)
2431 {
2432         struct ixgbe_hw *hw;
2433         struct ixgbe_vf_info *vfinfo;
2434         struct rte_eth_link link;
2435         uint8_t  nb_q_per_pool;
2436         uint32_t queue_stride;
2437         uint32_t queue_idx, idx = 0, vf_idx;
2438         uint32_t queue_end;
2439         uint16_t total_rate = 0;
2440         struct rte_pci_device *pci_dev;
2441         int ret;
2442
2443         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2444         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2445         if (ret < 0)
2446                 return ret;
2447
2448         if (vf >= pci_dev->max_vfs)
2449                 return -EINVAL;
2450
2451         if (tx_rate > link.link_speed)
2452                 return -EINVAL;
2453
2454         if (q_msk == 0)
2455                 return 0;
2456
2457         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2458         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2459         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2460         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2461         queue_idx = vf * queue_stride;
2462         queue_end = queue_idx + nb_q_per_pool - 1;
2463         if (queue_end >= hw->mac.max_tx_queues)
2464                 return -EINVAL;
2465
2466         if (vfinfo) {
2467                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2468                         if (vf_idx == vf)
2469                                 continue;
2470                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2471                                 idx++)
2472                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2473                 }
2474         } else {
2475                 return -EINVAL;
2476         }
2477
2478         /* Store tx_rate for this vf. */
2479         for (idx = 0; idx < nb_q_per_pool; idx++) {
2480                 if (((uint64_t)0x1 << idx) & q_msk) {
2481                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2482                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2483                         total_rate += tx_rate;
2484                 }
2485         }
2486
2487         if (total_rate > dev->data->dev_link.link_speed) {
2488                 /* Reset stored TX rate of the VF if it causes exceed
2489                  * link speed.
2490                  */
2491                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2492                 return -EINVAL;
2493         }
2494
2495         /* Set RTTBCNRC of each queue/pool for vf X  */
2496         for (; queue_idx <= queue_end; queue_idx++) {
2497                 if (0x1 & q_msk)
2498                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2499                 q_msk = q_msk >> 1;
2500         }
2501
2502         return 0;
2503 }
2504
2505 static int
2506 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2507 {
2508         struct ixgbe_adapter *adapter = dev->data->dev_private;
2509         int err;
2510         uint32_t mflcn;
2511
2512         ixgbe_setup_fc(hw);
2513
2514         err = ixgbe_fc_enable(hw);
2515
2516         /* Not negotiated is not an error case */
2517         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2518                 /*
2519                  *check if we want to forward MAC frames - driver doesn't
2520                  *have native capability to do that,
2521                  *so we'll write the registers ourselves
2522                  */
2523
2524                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2525
2526                 /* set or clear MFLCN.PMCF bit depending on configuration */
2527                 if (adapter->mac_ctrl_frame_fwd != 0)
2528                         mflcn |= IXGBE_MFLCN_PMCF;
2529                 else
2530                         mflcn &= ~IXGBE_MFLCN_PMCF;
2531
2532                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2533                 IXGBE_WRITE_FLUSH(hw);
2534
2535                 return 0;
2536         }
2537         return err;
2538 }
2539
2540 /*
2541  * Configure device link speed and setup link.
2542  * It returns 0 on success.
2543  */
2544 static int
2545 ixgbe_dev_start(struct rte_eth_dev *dev)
2546 {
2547         struct ixgbe_hw *hw =
2548                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549         struct ixgbe_vf_info *vfinfo =
2550                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2551         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2552         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2553         uint32_t intr_vector = 0;
2554         int err;
2555         bool link_up = false, negotiate = 0;
2556         uint32_t speed = 0;
2557         uint32_t allowed_speeds = 0;
2558         int mask = 0;
2559         int status;
2560         uint16_t vf, idx;
2561         uint32_t *link_speeds;
2562         struct ixgbe_tm_conf *tm_conf =
2563                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2564         struct ixgbe_macsec_setting *macsec_setting =
2565                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2566
2567         PMD_INIT_FUNC_TRACE();
2568
2569         /* Stop the link setup handler before resetting the HW. */
2570         ixgbe_dev_wait_setup_link_complete(dev, 0);
2571
2572         /* disable uio/vfio intr/eventfd mapping */
2573         rte_intr_disable(intr_handle);
2574
2575         /* stop adapter */
2576         hw->adapter_stopped = 0;
2577         ixgbe_stop_adapter(hw);
2578
2579         /* reinitialize adapter
2580          * this calls reset and start
2581          */
2582         status = ixgbe_pf_reset_hw(hw);
2583         if (status != 0)
2584                 return -1;
2585         hw->mac.ops.start_hw(hw);
2586         hw->mac.get_link_status = true;
2587
2588         /* configure PF module if SRIOV enabled */
2589         ixgbe_pf_host_configure(dev);
2590
2591         ixgbe_dev_phy_intr_setup(dev);
2592
2593         /* check and configure queue intr-vector mapping */
2594         if ((rte_intr_cap_multiple(intr_handle) ||
2595              !RTE_ETH_DEV_SRIOV(dev).active) &&
2596             dev->data->dev_conf.intr_conf.rxq != 0) {
2597                 intr_vector = dev->data->nb_rx_queues;
2598                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2599                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2600                                         IXGBE_MAX_INTR_QUEUE_NUM);
2601                         return -ENOTSUP;
2602                 }
2603                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2604                         return -1;
2605         }
2606
2607         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2608                 intr_handle->intr_vec =
2609                         rte_zmalloc("intr_vec",
2610                                     dev->data->nb_rx_queues * sizeof(int), 0);
2611                 if (intr_handle->intr_vec == NULL) {
2612                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2613                                      " intr_vec", dev->data->nb_rx_queues);
2614                         return -ENOMEM;
2615                 }
2616         }
2617
2618         /* confiugre msix for sleep until rx interrupt */
2619         ixgbe_configure_msix(dev);
2620
2621         /* initialize transmission unit */
2622         ixgbe_dev_tx_init(dev);
2623
2624         /* This can fail when allocating mbufs for descriptor rings */
2625         err = ixgbe_dev_rx_init(dev);
2626         if (err) {
2627                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2628                 goto error;
2629         }
2630
2631         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2632                 ETH_VLAN_EXTEND_MASK;
2633         err = ixgbe_vlan_offload_config(dev, mask);
2634         if (err) {
2635                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2636                 goto error;
2637         }
2638
2639         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2640                 /* Enable vlan filtering for VMDq */
2641                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2642         }
2643
2644         /* Configure DCB hw */
2645         ixgbe_configure_dcb(dev);
2646
2647         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2648                 err = ixgbe_fdir_configure(dev);
2649                 if (err)
2650                         goto error;
2651         }
2652
2653         /* Restore vf rate limit */
2654         if (vfinfo != NULL) {
2655                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2656                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2657                                 if (vfinfo[vf].tx_rate[idx] != 0)
2658                                         ixgbe_set_vf_rate_limit(
2659                                                 dev, vf,
2660                                                 vfinfo[vf].tx_rate[idx],
2661                                                 1 << idx);
2662         }
2663
2664         ixgbe_restore_statistics_mapping(dev);
2665
2666         err = ixgbe_flow_ctrl_enable(dev, hw);
2667         if (err < 0) {
2668                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2669                 goto error;
2670         }
2671
2672         err = ixgbe_dev_rxtx_start(dev);
2673         if (err < 0) {
2674                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2675                 goto error;
2676         }
2677
2678         /* Skip link setup if loopback mode is enabled. */
2679         if (dev->data->dev_conf.lpbk_mode != 0) {
2680                 err = ixgbe_check_supported_loopback_mode(dev);
2681                 if (err < 0) {
2682                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2683                         goto error;
2684                 } else {
2685                         goto skip_link_setup;
2686                 }
2687         }
2688
2689         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2690                 err = hw->mac.ops.setup_sfp(hw);
2691                 if (err)
2692                         goto error;
2693         }
2694
2695         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2696                 /* Turn on the copper */
2697                 ixgbe_set_phy_power(hw, true);
2698         } else {
2699                 /* Turn on the laser */
2700                 ixgbe_enable_tx_laser(hw);
2701         }
2702
2703         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2704         if (err)
2705                 goto error;
2706         dev->data->dev_link.link_status = link_up;
2707
2708         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2709         if (err)
2710                 goto error;
2711
2712         switch (hw->mac.type) {
2713         case ixgbe_mac_X550:
2714         case ixgbe_mac_X550EM_x:
2715         case ixgbe_mac_X550EM_a:
2716                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2717                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2718                         ETH_LINK_SPEED_10G;
2719                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2720                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2721                         allowed_speeds = ETH_LINK_SPEED_10M |
2722                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2723                 break;
2724         default:
2725                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2726                         ETH_LINK_SPEED_10G;
2727         }
2728
2729         link_speeds = &dev->data->dev_conf.link_speeds;
2730
2731         /* Ignore autoneg flag bit and check the validity of
2732          * link_speed
2733          */
2734         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2735                 PMD_INIT_LOG(ERR, "Invalid link setting");
2736                 goto error;
2737         }
2738
2739         speed = 0x0;
2740         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2741                 switch (hw->mac.type) {
2742                 case ixgbe_mac_82598EB:
2743                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2744                         break;
2745                 case ixgbe_mac_82599EB:
2746                 case ixgbe_mac_X540:
2747                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2748                         break;
2749                 case ixgbe_mac_X550:
2750                 case ixgbe_mac_X550EM_x:
2751                 case ixgbe_mac_X550EM_a:
2752                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2753                         break;
2754                 default:
2755                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2756                 }
2757         } else {
2758                 if (*link_speeds & ETH_LINK_SPEED_10G)
2759                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2760                 if (*link_speeds & ETH_LINK_SPEED_5G)
2761                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2762                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2763                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2764                 if (*link_speeds & ETH_LINK_SPEED_1G)
2765                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2766                 if (*link_speeds & ETH_LINK_SPEED_100M)
2767                         speed |= IXGBE_LINK_SPEED_100_FULL;
2768                 if (*link_speeds & ETH_LINK_SPEED_10M)
2769                         speed |= IXGBE_LINK_SPEED_10_FULL;
2770         }
2771
2772         err = ixgbe_setup_link(hw, speed, link_up);
2773         if (err)
2774                 goto error;
2775
2776 skip_link_setup:
2777
2778         if (rte_intr_allow_others(intr_handle)) {
2779                 /* check if lsc interrupt is enabled */
2780                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2781                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2782                 else
2783                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2784                 ixgbe_dev_macsec_interrupt_setup(dev);
2785         } else {
2786                 rte_intr_callback_unregister(intr_handle,
2787                                              ixgbe_dev_interrupt_handler, dev);
2788                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2789                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2790                                      " no intr multiplex");
2791         }
2792
2793         /* check if rxq interrupt is enabled */
2794         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2795             rte_intr_dp_is_en(intr_handle))
2796                 ixgbe_dev_rxq_interrupt_setup(dev);
2797
2798         /* enable uio/vfio intr/eventfd mapping */
2799         rte_intr_enable(intr_handle);
2800
2801         /* resume enabled intr since hw reset */
2802         ixgbe_enable_intr(dev);
2803         ixgbe_l2_tunnel_conf(dev);
2804         ixgbe_filter_restore(dev);
2805
2806         if (tm_conf->root && !tm_conf->committed)
2807                 PMD_DRV_LOG(WARNING,
2808                             "please call hierarchy_commit() "
2809                             "before starting the port");
2810
2811         /* wait for the controller to acquire link */
2812         err = ixgbe_wait_for_link_up(hw);
2813         if (err)
2814                 goto error;
2815
2816         /*
2817          * Update link status right before return, because it may
2818          * start link configuration process in a separate thread.
2819          */
2820         ixgbe_dev_link_update(dev, 0);
2821
2822         /* setup the macsec setting register */
2823         if (macsec_setting->offload_en)
2824                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2825
2826         return 0;
2827
2828 error:
2829         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2830         ixgbe_dev_clear_queues(dev);
2831         return -EIO;
2832 }
2833
2834 /*
2835  * Stop device: disable rx and tx functions to allow for reconfiguring.
2836  */
2837 static int
2838 ixgbe_dev_stop(struct rte_eth_dev *dev)
2839 {
2840         struct rte_eth_link link;
2841         struct ixgbe_adapter *adapter = dev->data->dev_private;
2842         struct ixgbe_hw *hw =
2843                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844         struct ixgbe_vf_info *vfinfo =
2845                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2846         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2847         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2848         int vf;
2849         struct ixgbe_tm_conf *tm_conf =
2850                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2851
2852         if (hw->adapter_stopped)
2853                 return 0;
2854
2855         PMD_INIT_FUNC_TRACE();
2856
2857         ixgbe_dev_wait_setup_link_complete(dev, 0);
2858
2859         /* disable interrupts */
2860         ixgbe_disable_intr(hw);
2861
2862         /* reset the NIC */
2863         ixgbe_pf_reset_hw(hw);
2864         hw->adapter_stopped = 0;
2865
2866         /* stop adapter */
2867         ixgbe_stop_adapter(hw);
2868
2869         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2870                 vfinfo[vf].clear_to_send = false;
2871
2872         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2873                 /* Turn off the copper */
2874                 ixgbe_set_phy_power(hw, false);
2875         } else {
2876                 /* Turn off the laser */
2877                 ixgbe_disable_tx_laser(hw);
2878         }
2879
2880         ixgbe_dev_clear_queues(dev);
2881
2882         /* Clear stored conf */
2883         dev->data->scattered_rx = 0;
2884         dev->data->lro = 0;
2885
2886         /* Clear recorded link status */
2887         memset(&link, 0, sizeof(link));
2888         rte_eth_linkstatus_set(dev, &link);
2889
2890         if (!rte_intr_allow_others(intr_handle))
2891                 /* resume to the default handler */
2892                 rte_intr_callback_register(intr_handle,
2893                                            ixgbe_dev_interrupt_handler,
2894                                            (void *)dev);
2895
2896         /* Clean datapath event and queue/vec mapping */
2897         rte_intr_efd_disable(intr_handle);
2898         if (intr_handle->intr_vec != NULL) {
2899                 rte_free(intr_handle->intr_vec);
2900                 intr_handle->intr_vec = NULL;
2901         }
2902
2903         /* reset hierarchy commit */
2904         tm_conf->committed = false;
2905
2906         adapter->rss_reta_updated = 0;
2907
2908         hw->adapter_stopped = true;
2909         dev->data->dev_started = 0;
2910
2911         return 0;
2912 }
2913
2914 /*
2915  * Set device link up: enable tx.
2916  */
2917 static int
2918 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2919 {
2920         struct ixgbe_hw *hw =
2921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2922         if (hw->mac.type == ixgbe_mac_82599EB) {
2923 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2924                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2925                         /* Not suported in bypass mode */
2926                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2927                                      "by device id 0x%x", hw->device_id);
2928                         return -ENOTSUP;
2929                 }
2930 #endif
2931         }
2932
2933         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2934                 /* Turn on the copper */
2935                 ixgbe_set_phy_power(hw, true);
2936         } else {
2937                 /* Turn on the laser */
2938                 ixgbe_enable_tx_laser(hw);
2939                 ixgbe_dev_link_update(dev, 0);
2940         }
2941
2942         return 0;
2943 }
2944
2945 /*
2946  * Set device link down: disable tx.
2947  */
2948 static int
2949 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2950 {
2951         struct ixgbe_hw *hw =
2952                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2953         if (hw->mac.type == ixgbe_mac_82599EB) {
2954 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2955                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2956                         /* Not suported in bypass mode */
2957                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2958                                      "by device id 0x%x", hw->device_id);
2959                         return -ENOTSUP;
2960                 }
2961 #endif
2962         }
2963
2964         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2965                 /* Turn off the copper */
2966                 ixgbe_set_phy_power(hw, false);
2967         } else {
2968                 /* Turn off the laser */
2969                 ixgbe_disable_tx_laser(hw);
2970                 ixgbe_dev_link_update(dev, 0);
2971         }
2972
2973         return 0;
2974 }
2975
2976 /*
2977  * Reset and stop device.
2978  */
2979 static int
2980 ixgbe_dev_close(struct rte_eth_dev *dev)
2981 {
2982         struct ixgbe_hw *hw =
2983                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2984         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2985         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2986         int retries = 0;
2987         int ret;
2988
2989         PMD_INIT_FUNC_TRACE();
2990         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2991                 return 0;
2992
2993         ixgbe_pf_reset_hw(hw);
2994
2995         ret = ixgbe_dev_stop(dev);
2996
2997         ixgbe_dev_free_queues(dev);
2998
2999         ixgbe_disable_pcie_master(hw);
3000
3001         /* reprogram the RAR[0] in case user changed it. */
3002         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3003
3004         /* Unlock any pending hardware semaphore */
3005         ixgbe_swfw_lock_reset(hw);
3006
3007         /* disable uio intr before callback unregister */
3008         rte_intr_disable(intr_handle);
3009
3010         do {
3011                 ret = rte_intr_callback_unregister(intr_handle,
3012                                 ixgbe_dev_interrupt_handler, dev);
3013                 if (ret >= 0 || ret == -ENOENT) {
3014                         break;
3015                 } else if (ret != -EAGAIN) {
3016                         PMD_INIT_LOG(ERR,
3017                                 "intr callback unregister failed: %d",
3018                                 ret);
3019                 }
3020                 rte_delay_ms(100);
3021         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3022
3023         /* cancel the delay handler before remove dev */
3024         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3025
3026         /* uninitialize PF if max_vfs not zero */
3027         ixgbe_pf_host_uninit(dev);
3028
3029         /* remove all the fdir filters & hash */
3030         ixgbe_fdir_filter_uninit(dev);
3031
3032         /* remove all the L2 tunnel filters & hash */
3033         ixgbe_l2_tn_filter_uninit(dev);
3034
3035         /* Remove all ntuple filters of the device */
3036         ixgbe_ntuple_filter_uninit(dev);
3037
3038         /* clear all the filters list */
3039         ixgbe_filterlist_flush();
3040
3041         /* Remove all Traffic Manager configuration */
3042         ixgbe_tm_conf_uninit(dev);
3043
3044 #ifdef RTE_LIB_SECURITY
3045         rte_free(dev->security_ctx);
3046 #endif
3047
3048         return ret;
3049 }
3050
3051 /*
3052  * Reset PF device.
3053  */
3054 static int
3055 ixgbe_dev_reset(struct rte_eth_dev *dev)
3056 {
3057         int ret;
3058
3059         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3060          * its VF to make them align with it. The detailed notification
3061          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3062          * To avoid unexpected behavior in VF, currently reset of PF with
3063          * SR-IOV activation is not supported. It might be supported later.
3064          */
3065         if (dev->data->sriov.active)
3066                 return -ENOTSUP;
3067
3068         ret = eth_ixgbe_dev_uninit(dev);
3069         if (ret)
3070                 return ret;
3071
3072         ret = eth_ixgbe_dev_init(dev, NULL);
3073
3074         return ret;
3075 }
3076
3077 static void
3078 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3079                            struct ixgbe_hw_stats *hw_stats,
3080                            struct ixgbe_macsec_stats *macsec_stats,
3081                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3082                            uint64_t *total_qprc, uint64_t *total_qprdc)
3083 {
3084         uint32_t bprc, lxon, lxoff, total;
3085         uint32_t delta_gprc = 0;
3086         unsigned i;
3087         /* Workaround for RX byte count not including CRC bytes when CRC
3088          * strip is enabled. CRC bytes are removed from counters when crc_strip
3089          * is disabled.
3090          */
3091         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3092                         IXGBE_HLREG0_RXCRCSTRP);
3093
3094         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3095         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3096         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3097         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3098
3099         for (i = 0; i < 8; i++) {
3100                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3101
3102                 /* global total per queue */
3103                 hw_stats->mpc[i] += mp;
3104                 /* Running comprehensive total for stats display */
3105                 *total_missed_rx += hw_stats->mpc[i];
3106                 if (hw->mac.type == ixgbe_mac_82598EB) {
3107                         hw_stats->rnbc[i] +=
3108                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3109                         hw_stats->pxonrxc[i] +=
3110                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3111                         hw_stats->pxoffrxc[i] +=
3112                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3113                 } else {
3114                         hw_stats->pxonrxc[i] +=
3115                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3116                         hw_stats->pxoffrxc[i] +=
3117                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3118                         hw_stats->pxon2offc[i] +=
3119                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3120                 }
3121                 hw_stats->pxontxc[i] +=
3122                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3123                 hw_stats->pxofftxc[i] +=
3124                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3125         }
3126         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3127                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3128                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3129                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3130
3131                 delta_gprc += delta_qprc;
3132
3133                 hw_stats->qprc[i] += delta_qprc;
3134                 hw_stats->qptc[i] += delta_qptc;
3135
3136                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3137                 hw_stats->qbrc[i] +=
3138                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3139                 if (crc_strip == 0)
3140                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3141
3142                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3143                 hw_stats->qbtc[i] +=
3144                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3145
3146                 hw_stats->qprdc[i] += delta_qprdc;
3147                 *total_qprdc += hw_stats->qprdc[i];
3148
3149                 *total_qprc += hw_stats->qprc[i];
3150                 *total_qbrc += hw_stats->qbrc[i];
3151         }
3152         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3153         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3154         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3155
3156         /*
3157          * An errata states that gprc actually counts good + missed packets:
3158          * Workaround to set gprc to summated queue packet receives
3159          */
3160         hw_stats->gprc = *total_qprc;
3161
3162         if (hw->mac.type != ixgbe_mac_82598EB) {
3163                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3164                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3165                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3166                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3167                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3168                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3169                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3170                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3171         } else {
3172                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3173                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3174                 /* 82598 only has a counter in the high register */
3175                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3176                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3177                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3178         }
3179         uint64_t old_tpr = hw_stats->tpr;
3180
3181         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3182         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3183
3184         if (crc_strip == 0)
3185                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3186
3187         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3188         hw_stats->gptc += delta_gptc;
3189         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3190         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3191
3192         /*
3193          * Workaround: mprc hardware is incorrectly counting
3194          * broadcasts, so for now we subtract those.
3195          */
3196         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3197         hw_stats->bprc += bprc;
3198         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3199         if (hw->mac.type == ixgbe_mac_82598EB)
3200                 hw_stats->mprc -= bprc;
3201
3202         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3203         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3204         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3205         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3206         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3207         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3208
3209         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3210         hw_stats->lxontxc += lxon;
3211         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3212         hw_stats->lxofftxc += lxoff;
3213         total = lxon + lxoff;
3214
3215         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3216         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3217         hw_stats->gptc -= total;
3218         hw_stats->mptc -= total;
3219         hw_stats->ptc64 -= total;
3220         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3221
3222         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3223         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3224         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3225         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3226         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3227         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3228         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3229         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3230         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3231         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3232         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3233         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3234         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3235         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3236         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3237         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3238         /* Only read FCOE on 82599 */
3239         if (hw->mac.type != ixgbe_mac_82598EB) {
3240                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3241                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3242                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3243                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3244                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3245         }
3246
3247         /* Flow Director Stats registers */
3248         if (hw->mac.type != ixgbe_mac_82598EB) {
3249                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3250                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3251                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3252                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3253                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3254                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3255                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3256                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3257                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3258                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3259         }
3260         /* MACsec Stats registers */
3261         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3262         macsec_stats->out_pkts_encrypted +=
3263                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3264         macsec_stats->out_pkts_protected +=
3265                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3266         macsec_stats->out_octets_encrypted +=
3267                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3268         macsec_stats->out_octets_protected +=
3269                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3270         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3271         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3272         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3273         macsec_stats->in_pkts_unknownsci +=
3274                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3275         macsec_stats->in_octets_decrypted +=
3276                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3277         macsec_stats->in_octets_validated +=
3278                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3279         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3280         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3281         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3282         for (i = 0; i < 2; i++) {
3283                 macsec_stats->in_pkts_ok +=
3284                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3285                 macsec_stats->in_pkts_invalid +=
3286                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3287                 macsec_stats->in_pkts_notvalid +=
3288                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3289         }
3290         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3291         macsec_stats->in_pkts_notusingsa +=
3292                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3293 }
3294
3295 /*
3296  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3297  */
3298 static int
3299 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3300 {
3301         struct ixgbe_hw *hw =
3302                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3303         struct ixgbe_hw_stats *hw_stats =
3304                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3305         struct ixgbe_macsec_stats *macsec_stats =
3306                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3307                                 dev->data->dev_private);
3308         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3309         unsigned i;
3310
3311         total_missed_rx = 0;
3312         total_qbrc = 0;
3313         total_qprc = 0;
3314         total_qprdc = 0;
3315
3316         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3317                         &total_qbrc, &total_qprc, &total_qprdc);
3318
3319         if (stats == NULL)
3320                 return -EINVAL;
3321
3322         /* Fill out the rte_eth_stats statistics structure */
3323         stats->ipackets = total_qprc;
3324         stats->ibytes = total_qbrc;
3325         stats->opackets = hw_stats->gptc;
3326         stats->obytes = hw_stats->gotc;
3327
3328         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3329                 stats->q_ipackets[i] = hw_stats->qprc[i];
3330                 stats->q_opackets[i] = hw_stats->qptc[i];
3331                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3332                 stats->q_obytes[i] = hw_stats->qbtc[i];
3333                 stats->q_errors[i] = hw_stats->qprdc[i];
3334         }
3335
3336         /* Rx Errors */
3337         stats->imissed  = total_missed_rx;
3338         stats->ierrors  = hw_stats->crcerrs +
3339                           hw_stats->mspdc +
3340                           hw_stats->rlec +
3341                           hw_stats->ruc +
3342                           hw_stats->roc +
3343                           hw_stats->illerrc +
3344                           hw_stats->errbc +
3345                           hw_stats->rfc +
3346                           hw_stats->fccrc +
3347                           hw_stats->fclast;
3348
3349         /* Tx Errors */
3350         stats->oerrors  = 0;
3351         return 0;
3352 }
3353
3354 static int
3355 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3356 {
3357         struct ixgbe_hw_stats *stats =
3358                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3359
3360         /* HW registers are cleared on read */
3361         ixgbe_dev_stats_get(dev, NULL);
3362
3363         /* Reset software totals */
3364         memset(stats, 0, sizeof(*stats));
3365
3366         return 0;
3367 }
3368
3369 /* This function calculates the number of xstats based on the current config */
3370 static unsigned
3371 ixgbe_xstats_calc_num(void) {
3372         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3373                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3374                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3375 }
3376
3377 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3378         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3379 {
3380         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3381         unsigned stat, i, count;
3382
3383         if (xstats_names != NULL) {
3384                 count = 0;
3385
3386                 /* Note: limit >= cnt_stats checked upstream
3387                  * in rte_eth_xstats_names()
3388                  */
3389
3390                 /* Extended stats from ixgbe_hw_stats */
3391                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3392                         strlcpy(xstats_names[count].name,
3393                                 rte_ixgbe_stats_strings[i].name,
3394                                 sizeof(xstats_names[count].name));
3395                         count++;
3396                 }
3397
3398                 /* MACsec Stats */
3399                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3400                         strlcpy(xstats_names[count].name,
3401                                 rte_ixgbe_macsec_strings[i].name,
3402                                 sizeof(xstats_names[count].name));
3403                         count++;
3404                 }
3405
3406                 /* RX Priority Stats */
3407                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3408                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3409                                 snprintf(xstats_names[count].name,
3410                                         sizeof(xstats_names[count].name),
3411                                         "rx_priority%u_%s", i,
3412                                         rte_ixgbe_rxq_strings[stat].name);
3413                                 count++;
3414                         }
3415                 }
3416
3417                 /* TX Priority Stats */
3418                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3419                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3420                                 snprintf(xstats_names[count].name,
3421                                         sizeof(xstats_names[count].name),
3422                                         "tx_priority%u_%s", i,
3423                                         rte_ixgbe_txq_strings[stat].name);
3424                                 count++;
3425                         }
3426                 }
3427         }
3428         return cnt_stats;
3429 }
3430
3431 static int ixgbe_dev_xstats_get_names_by_id(
3432         struct rte_eth_dev *dev,
3433         struct rte_eth_xstat_name *xstats_names,
3434         const uint64_t *ids,
3435         unsigned int limit)
3436 {
3437         if (!ids) {
3438                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3439                 unsigned int stat, i, count;
3440
3441                 if (xstats_names != NULL) {
3442                         count = 0;
3443
3444                         /* Note: limit >= cnt_stats checked upstream
3445                          * in rte_eth_xstats_names()
3446                          */
3447
3448                         /* Extended stats from ixgbe_hw_stats */
3449                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3450                                 strlcpy(xstats_names[count].name,
3451                                         rte_ixgbe_stats_strings[i].name,
3452                                         sizeof(xstats_names[count].name));
3453                                 count++;
3454                         }
3455
3456                         /* MACsec Stats */
3457                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3458                                 strlcpy(xstats_names[count].name,
3459                                         rte_ixgbe_macsec_strings[i].name,
3460                                         sizeof(xstats_names[count].name));
3461                                 count++;
3462                         }
3463
3464                         /* RX Priority Stats */
3465                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3466                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3467                                         snprintf(xstats_names[count].name,
3468                                             sizeof(xstats_names[count].name),
3469                                             "rx_priority%u_%s", i,
3470                                             rte_ixgbe_rxq_strings[stat].name);
3471                                         count++;
3472                                 }
3473                         }
3474
3475                         /* TX Priority Stats */
3476                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3477                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3478                                         snprintf(xstats_names[count].name,
3479                                             sizeof(xstats_names[count].name),
3480                                             "tx_priority%u_%s", i,
3481                                             rte_ixgbe_txq_strings[stat].name);
3482                                         count++;
3483                                 }
3484                         }
3485                 }
3486                 return cnt_stats;
3487         }
3488
3489         uint16_t i;
3490         uint16_t size = ixgbe_xstats_calc_num();
3491         struct rte_eth_xstat_name xstats_names_copy[size];
3492
3493         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3494                         size);
3495
3496         for (i = 0; i < limit; i++) {
3497                 if (ids[i] >= size) {
3498                         PMD_INIT_LOG(ERR, "id value isn't valid");
3499                         return -1;
3500                 }
3501                 strcpy(xstats_names[i].name,
3502                                 xstats_names_copy[ids[i]].name);
3503         }
3504         return limit;
3505 }
3506
3507 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3508         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3509 {
3510         unsigned i;
3511
3512         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3513                 return -ENOMEM;
3514
3515         if (xstats_names != NULL)
3516                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3517                         strlcpy(xstats_names[i].name,
3518                                 rte_ixgbevf_stats_strings[i].name,
3519                                 sizeof(xstats_names[i].name));
3520         return IXGBEVF_NB_XSTATS;
3521 }
3522
3523 static int
3524 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3525                                          unsigned n)
3526 {
3527         struct ixgbe_hw *hw =
3528                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3529         struct ixgbe_hw_stats *hw_stats =
3530                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3531         struct ixgbe_macsec_stats *macsec_stats =
3532                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3533                                 dev->data->dev_private);
3534         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3535         unsigned i, stat, count = 0;
3536
3537         count = ixgbe_xstats_calc_num();
3538
3539         if (n < count)
3540                 return count;
3541
3542         total_missed_rx = 0;
3543         total_qbrc = 0;
3544         total_qprc = 0;
3545         total_qprdc = 0;
3546
3547         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3548                         &total_qbrc, &total_qprc, &total_qprdc);
3549
3550         /* If this is a reset xstats is NULL, and we have cleared the
3551          * registers by reading them.
3552          */
3553         if (!xstats)
3554                 return 0;
3555
3556         /* Extended stats from ixgbe_hw_stats */
3557         count = 0;
3558         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3559                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3560                                 rte_ixgbe_stats_strings[i].offset);
3561                 xstats[count].id = count;
3562                 count++;
3563         }
3564
3565         /* MACsec Stats */
3566         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3567                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3568                                 rte_ixgbe_macsec_strings[i].offset);
3569                 xstats[count].id = count;
3570                 count++;
3571         }
3572
3573         /* RX Priority Stats */
3574         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3575                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3576                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3577                                         rte_ixgbe_rxq_strings[stat].offset +
3578                                         (sizeof(uint64_t) * i));
3579                         xstats[count].id = count;
3580                         count++;
3581                 }
3582         }
3583
3584         /* TX Priority Stats */
3585         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3586                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3587                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3588                                         rte_ixgbe_txq_strings[stat].offset +
3589                                         (sizeof(uint64_t) * i));
3590                         xstats[count].id = count;
3591                         count++;
3592                 }
3593         }
3594         return count;
3595 }
3596
3597 static int
3598 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3599                 uint64_t *values, unsigned int n)
3600 {
3601         if (!ids) {
3602                 struct ixgbe_hw *hw =
3603                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3604                 struct ixgbe_hw_stats *hw_stats =
3605                                 IXGBE_DEV_PRIVATE_TO_STATS(
3606                                                 dev->data->dev_private);
3607                 struct ixgbe_macsec_stats *macsec_stats =
3608                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3609                                         dev->data->dev_private);
3610                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3611                 unsigned int i, stat, count = 0;
3612
3613                 count = ixgbe_xstats_calc_num();
3614
3615                 if (!ids && n < count)
3616                         return count;
3617
3618                 total_missed_rx = 0;
3619                 total_qbrc = 0;
3620                 total_qprc = 0;
3621                 total_qprdc = 0;
3622
3623                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3624                                 &total_missed_rx, &total_qbrc, &total_qprc,
3625                                 &total_qprdc);
3626
3627                 /* If this is a reset xstats is NULL, and we have cleared the
3628                  * registers by reading them.
3629                  */
3630                 if (!ids && !values)
3631                         return 0;
3632
3633                 /* Extended stats from ixgbe_hw_stats */
3634                 count = 0;
3635                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3636                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3637                                         rte_ixgbe_stats_strings[i].offset);
3638                         count++;
3639                 }
3640
3641                 /* MACsec Stats */
3642                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3643                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3644                                         rte_ixgbe_macsec_strings[i].offset);
3645                         count++;
3646                 }
3647
3648                 /* RX Priority Stats */
3649                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3650                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3651                                 values[count] =
3652                                         *(uint64_t *)(((char *)hw_stats) +
3653                                         rte_ixgbe_rxq_strings[stat].offset +
3654                                         (sizeof(uint64_t) * i));
3655                                 count++;
3656                         }
3657                 }
3658
3659                 /* TX Priority Stats */
3660                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3661                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3662                                 values[count] =
3663                                         *(uint64_t *)(((char *)hw_stats) +
3664                                         rte_ixgbe_txq_strings[stat].offset +
3665                                         (sizeof(uint64_t) * i));
3666                                 count++;
3667                         }
3668                 }
3669                 return count;
3670         }
3671
3672         uint16_t i;
3673         uint16_t size = ixgbe_xstats_calc_num();
3674         uint64_t values_copy[size];
3675
3676         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3677
3678         for (i = 0; i < n; i++) {
3679                 if (ids[i] >= size) {
3680                         PMD_INIT_LOG(ERR, "id value isn't valid");
3681                         return -1;
3682                 }
3683                 values[i] = values_copy[ids[i]];
3684         }
3685         return n;
3686 }
3687
3688 static int
3689 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3690 {
3691         struct ixgbe_hw_stats *stats =
3692                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3693         struct ixgbe_macsec_stats *macsec_stats =
3694                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3695                                 dev->data->dev_private);
3696
3697         unsigned count = ixgbe_xstats_calc_num();
3698
3699         /* HW registers are cleared on read */
3700         ixgbe_dev_xstats_get(dev, NULL, count);
3701
3702         /* Reset software totals */
3703         memset(stats, 0, sizeof(*stats));
3704         memset(macsec_stats, 0, sizeof(*macsec_stats));
3705
3706         return 0;
3707 }
3708
3709 static void
3710 ixgbevf_update_stats(struct rte_eth_dev *dev)
3711 {
3712         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3713         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3714                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3715
3716         /* Good Rx packet, include VF loopback */
3717         UPDATE_VF_STAT(IXGBE_VFGPRC,
3718             hw_stats->last_vfgprc, hw_stats->vfgprc);
3719
3720         /* Good Rx octets, include VF loopback */
3721         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3722             hw_stats->last_vfgorc, hw_stats->vfgorc);
3723
3724         /* Good Tx packet, include VF loopback */
3725         UPDATE_VF_STAT(IXGBE_VFGPTC,
3726             hw_stats->last_vfgptc, hw_stats->vfgptc);
3727
3728         /* Good Tx octets, include VF loopback */
3729         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3730             hw_stats->last_vfgotc, hw_stats->vfgotc);
3731
3732         /* Rx Multicst Packet */
3733         UPDATE_VF_STAT(IXGBE_VFMPRC,
3734             hw_stats->last_vfmprc, hw_stats->vfmprc);
3735 }
3736
3737 static int
3738 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3739                        unsigned n)
3740 {
3741         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3742                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3743         unsigned i;
3744
3745         if (n < IXGBEVF_NB_XSTATS)
3746                 return IXGBEVF_NB_XSTATS;
3747
3748         ixgbevf_update_stats(dev);
3749
3750         if (!xstats)
3751                 return 0;
3752
3753         /* Extended stats */
3754         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3755                 xstats[i].id = i;
3756                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3757                         rte_ixgbevf_stats_strings[i].offset);
3758         }
3759
3760         return IXGBEVF_NB_XSTATS;
3761 }
3762
3763 static int
3764 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3765 {
3766         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3767                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3768
3769         ixgbevf_update_stats(dev);
3770
3771         if (stats == NULL)
3772                 return -EINVAL;
3773
3774         stats->ipackets = hw_stats->vfgprc;
3775         stats->ibytes = hw_stats->vfgorc;
3776         stats->opackets = hw_stats->vfgptc;
3777         stats->obytes = hw_stats->vfgotc;
3778         return 0;
3779 }
3780
3781 static int
3782 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3783 {
3784         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3785                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3786
3787         /* Sync HW register to the last stats */
3788         ixgbevf_dev_stats_get(dev, NULL);
3789
3790         /* reset HW current stats*/
3791         hw_stats->vfgprc = 0;
3792         hw_stats->vfgorc = 0;
3793         hw_stats->vfgptc = 0;
3794         hw_stats->vfgotc = 0;
3795
3796         return 0;
3797 }
3798
3799 static int
3800 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3801 {
3802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3803         u16 eeprom_verh, eeprom_verl;
3804         u32 etrack_id;
3805         int ret;
3806
3807         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3808         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3809
3810         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3811         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3812
3813         ret += 1; /* add the size of '\0' */
3814         if (fw_size < (u32)ret)
3815                 return ret;
3816         else
3817                 return 0;
3818 }
3819
3820 static int
3821 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3822 {
3823         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3824         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3825         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3826
3827         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3828         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3829         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3830                 /*
3831                  * When DCB/VT is off, maximum number of queues changes,
3832                  * except for 82598EB, which remains constant.
3833                  */
3834                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3835                                 hw->mac.type != ixgbe_mac_82598EB)
3836                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3837         }
3838         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3839         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3840         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3841         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3842         dev_info->max_vfs = pci_dev->max_vfs;
3843         if (hw->mac.type == ixgbe_mac_82598EB)
3844                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3845         else
3846                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3847         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3848         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3849         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3850         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3851         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3852                                      dev_info->rx_queue_offload_capa);
3853         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3854         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3855
3856         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3857                 .rx_thresh = {
3858                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3859                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3860                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3861                 },
3862                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3863                 .rx_drop_en = 0,
3864                 .offloads = 0,
3865         };
3866
3867         dev_info->default_txconf = (struct rte_eth_txconf) {
3868                 .tx_thresh = {
3869                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3870                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3871                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3872                 },
3873                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3874                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3875                 .offloads = 0,
3876         };
3877
3878         dev_info->rx_desc_lim = rx_desc_lim;
3879         dev_info->tx_desc_lim = tx_desc_lim;
3880
3881         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3882         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3883         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3884
3885         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3886         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3887                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3888                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3889                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3890
3891         if (hw->mac.type == ixgbe_mac_X540 ||
3892             hw->mac.type == ixgbe_mac_X540_vf ||
3893             hw->mac.type == ixgbe_mac_X550 ||
3894             hw->mac.type == ixgbe_mac_X550_vf) {
3895                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3896         }
3897         if (hw->mac.type == ixgbe_mac_X550) {
3898                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3899                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3900         }
3901
3902         /* Driver-preferred Rx/Tx parameters */
3903         dev_info->default_rxportconf.burst_size = 32;
3904         dev_info->default_txportconf.burst_size = 32;
3905         dev_info->default_rxportconf.nb_queues = 1;
3906         dev_info->default_txportconf.nb_queues = 1;
3907         dev_info->default_rxportconf.ring_size = 256;
3908         dev_info->default_txportconf.ring_size = 256;
3909
3910         return 0;
3911 }
3912
3913 static const uint32_t *
3914 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3915 {
3916         static const uint32_t ptypes[] = {
3917                 /* For non-vec functions,
3918                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3919                  * for vec functions,
3920                  * refers to _recv_raw_pkts_vec().
3921                  */
3922                 RTE_PTYPE_L2_ETHER,
3923                 RTE_PTYPE_L3_IPV4,
3924                 RTE_PTYPE_L3_IPV4_EXT,
3925                 RTE_PTYPE_L3_IPV6,
3926                 RTE_PTYPE_L3_IPV6_EXT,
3927                 RTE_PTYPE_L4_SCTP,
3928                 RTE_PTYPE_L4_TCP,
3929                 RTE_PTYPE_L4_UDP,
3930                 RTE_PTYPE_TUNNEL_IP,
3931                 RTE_PTYPE_INNER_L3_IPV6,
3932                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3933                 RTE_PTYPE_INNER_L4_TCP,
3934                 RTE_PTYPE_INNER_L4_UDP,
3935                 RTE_PTYPE_UNKNOWN
3936         };
3937
3938         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3939             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3940             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3941             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3942                 return ptypes;
3943
3944 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3945         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3946             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3947                 return ptypes;
3948 #endif
3949         return NULL;
3950 }
3951
3952 static int
3953 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3954                      struct rte_eth_dev_info *dev_info)
3955 {
3956         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3958
3959         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3960         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3961         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3962         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3963         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3964         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3965         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3966         dev_info->max_vfs = pci_dev->max_vfs;
3967         if (hw->mac.type == ixgbe_mac_82598EB)
3968                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3969         else
3970                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3971         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3972         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3973                                      dev_info->rx_queue_offload_capa);
3974         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3975         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3976         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3977         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3978         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3979
3980         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3981                 .rx_thresh = {
3982                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3983                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3984                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3985                 },
3986                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3987                 .rx_drop_en = 0,
3988                 .offloads = 0,
3989         };
3990
3991         dev_info->default_txconf = (struct rte_eth_txconf) {
3992                 .tx_thresh = {
3993                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3994                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3995                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3996                 },
3997                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3998                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3999                 .offloads = 0,
4000         };
4001
4002         dev_info->rx_desc_lim = rx_desc_lim;
4003         dev_info->tx_desc_lim = tx_desc_lim;
4004
4005         return 0;
4006 }
4007
4008 static int
4009 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4010                    bool *link_up, int wait_to_complete)
4011 {
4012         struct ixgbe_adapter *adapter = container_of(hw,
4013                                                      struct ixgbe_adapter, hw);
4014         struct ixgbe_mbx_info *mbx = &hw->mbx;
4015         struct ixgbe_mac_info *mac = &hw->mac;
4016         uint32_t links_reg, in_msg;
4017         int ret_val = 0;
4018
4019         /* If we were hit with a reset drop the link */
4020         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4021                 mac->get_link_status = true;
4022
4023         if (!mac->get_link_status)
4024                 goto out;
4025
4026         /* if link status is down no point in checking to see if pf is up */
4027         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4028         if (!(links_reg & IXGBE_LINKS_UP))
4029                 goto out;
4030
4031         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4032          * before the link status is correct
4033          */
4034         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4035                 int i;
4036
4037                 for (i = 0; i < 5; i++) {
4038                         rte_delay_us(100);
4039                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4040
4041                         if (!(links_reg & IXGBE_LINKS_UP))
4042                                 goto out;
4043                 }
4044         }
4045
4046         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4047         case IXGBE_LINKS_SPEED_10G_82599:
4048                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4049                 if (hw->mac.type >= ixgbe_mac_X550) {
4050                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4051                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4052                 }
4053                 break;
4054         case IXGBE_LINKS_SPEED_1G_82599:
4055                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4056                 break;
4057         case IXGBE_LINKS_SPEED_100_82599:
4058                 *speed = IXGBE_LINK_SPEED_100_FULL;
4059                 if (hw->mac.type == ixgbe_mac_X550) {
4060                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4061                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4062                 }
4063                 break;
4064         case IXGBE_LINKS_SPEED_10_X550EM_A:
4065                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4066                 /* Since Reserved in older MAC's */
4067                 if (hw->mac.type >= ixgbe_mac_X550)
4068                         *speed = IXGBE_LINK_SPEED_10_FULL;
4069                 break;
4070         default:
4071                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4072         }
4073
4074         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4075                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4076                         mac->get_link_status = true;
4077                 else
4078                         mac->get_link_status = false;
4079
4080                 goto out;
4081         }
4082
4083         /* if the read failed it could just be a mailbox collision, best wait
4084          * until we are called again and don't report an error
4085          */
4086         if (mbx->ops.read(hw, &in_msg, 1, 0))
4087                 goto out;
4088
4089         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4090                 /* msg is not CTS and is NACK we must have lost CTS status */
4091                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4092                         mac->get_link_status = false;
4093                 goto out;
4094         }
4095
4096         /* the pf is talking, if we timed out in the past we reinit */
4097         if (!mbx->timeout) {
4098                 ret_val = -1;
4099                 goto out;
4100         }
4101
4102         /* if we passed all the tests above then the link is up and we no
4103          * longer need to check for link
4104          */
4105         mac->get_link_status = false;
4106
4107 out:
4108         *link_up = !mac->get_link_status;
4109         return ret_val;
4110 }
4111
4112 /*
4113  * If @timeout_ms was 0, it means that it will not return until link complete.
4114  * It returns 1 on complete, return 0 on timeout.
4115  */
4116 static int
4117 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4118 {
4119 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4120         struct ixgbe_adapter *ad = dev->data->dev_private;
4121         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4122
4123         while (rte_atomic32_read(&ad->link_thread_running)) {
4124                 msec_delay(1);
4125                 timeout--;
4126
4127                 if (timeout_ms) {
4128                         if (!timeout)
4129                                 return 0;
4130                 } else if (!timeout) {
4131                         /* It will not return until link complete */
4132                         timeout = WARNING_TIMEOUT;
4133                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4134                 }
4135         }
4136
4137         return 1;
4138 }
4139
4140 static void *
4141 ixgbe_dev_setup_link_thread_handler(void *param)
4142 {
4143         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4144         struct ixgbe_adapter *ad = dev->data->dev_private;
4145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4146         struct ixgbe_interrupt *intr =
4147                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4148         u32 speed;
4149         bool autoneg = false;
4150
4151         pthread_detach(pthread_self());
4152         speed = hw->phy.autoneg_advertised;
4153         if (!speed)
4154                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4155
4156         ixgbe_setup_link(hw, speed, true);
4157
4158         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4159         rte_atomic32_clear(&ad->link_thread_running);
4160         return NULL;
4161 }
4162
4163 /*
4164  * In freebsd environment, nic_uio drivers do not support interrupts,
4165  * rte_intr_callback_register() will fail to register interrupts.
4166  * We can not make link status to change from down to up by interrupt
4167  * callback. So we need to wait for the controller to acquire link
4168  * when ports start.
4169  * It returns 0 on link up.
4170  */
4171 static int
4172 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4173 {
4174 #ifdef RTE_EXEC_ENV_FREEBSD
4175         int err, i;
4176         bool link_up = false;
4177         uint32_t speed = 0;
4178         const int nb_iter = 25;
4179
4180         for (i = 0; i < nb_iter; i++) {
4181                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4182                 if (err)
4183                         return err;
4184                 if (link_up)
4185                         return 0;
4186                 msec_delay(200);
4187         }
4188
4189         return 0;
4190 #else
4191         RTE_SET_USED(hw);
4192         return 0;
4193 #endif
4194 }
4195
4196 /* return 0 means link status changed, -1 means not changed */
4197 int
4198 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4199                             int wait_to_complete, int vf)
4200 {
4201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202         struct ixgbe_adapter *ad = dev->data->dev_private;
4203         struct rte_eth_link link;
4204         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4205         struct ixgbe_interrupt *intr =
4206                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4207         bool link_up;
4208         int diag;
4209         int wait = 1;
4210         u32 esdp_reg;
4211
4212         memset(&link, 0, sizeof(link));
4213         link.link_status = ETH_LINK_DOWN;
4214         link.link_speed = ETH_SPEED_NUM_NONE;
4215         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4216         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4217                         ETH_LINK_SPEED_FIXED);
4218
4219         hw->mac.get_link_status = true;
4220
4221         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4222                 return rte_eth_linkstatus_set(dev, &link);
4223
4224         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4225         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4226                 wait = 0;
4227
4228 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4229 #ifdef RTE_EXEC_ENV_FREEBSD
4230         wait = 1;
4231 #endif
4232
4233         if (vf)
4234                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4235         else
4236                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4237
4238         if (diag != 0) {
4239                 link.link_speed = ETH_SPEED_NUM_100M;
4240                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4241                 return rte_eth_linkstatus_set(dev, &link);
4242         }
4243
4244         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4245                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4246                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4247                         link_up = 0;
4248         }
4249
4250         if (link_up == 0) {
4251                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4252                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4253                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4254                                 /* To avoid race condition between threads, set
4255                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4256                                  * when there is no link thread running.
4257                                  */
4258                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4259                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4260                                         "ixgbe-link-handler",
4261                                         NULL,
4262                                         ixgbe_dev_setup_link_thread_handler,
4263                                         dev) < 0) {
4264                                         PMD_DRV_LOG(ERR,
4265                                                 "Create link thread failed!");
4266                                         rte_atomic32_clear(&ad->link_thread_running);
4267                                 }
4268                         } else {
4269                                 PMD_DRV_LOG(ERR,
4270                                         "Other link thread is running now!");
4271                         }
4272                 }
4273                 return rte_eth_linkstatus_set(dev, &link);
4274         }
4275
4276         link.link_status = ETH_LINK_UP;
4277         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4278
4279         switch (link_speed) {
4280         default:
4281         case IXGBE_LINK_SPEED_UNKNOWN:
4282                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4283                 break;
4284
4285         case IXGBE_LINK_SPEED_10_FULL:
4286                 link.link_speed = ETH_SPEED_NUM_10M;
4287                 break;
4288
4289         case IXGBE_LINK_SPEED_100_FULL:
4290                 link.link_speed = ETH_SPEED_NUM_100M;
4291                 break;
4292
4293         case IXGBE_LINK_SPEED_1GB_FULL:
4294                 link.link_speed = ETH_SPEED_NUM_1G;
4295                 break;
4296
4297         case IXGBE_LINK_SPEED_2_5GB_FULL:
4298                 link.link_speed = ETH_SPEED_NUM_2_5G;
4299                 break;
4300
4301         case IXGBE_LINK_SPEED_5GB_FULL:
4302                 link.link_speed = ETH_SPEED_NUM_5G;
4303                 break;
4304
4305         case IXGBE_LINK_SPEED_10GB_FULL:
4306                 link.link_speed = ETH_SPEED_NUM_10G;
4307                 break;
4308         }
4309
4310         return rte_eth_linkstatus_set(dev, &link);
4311 }
4312
4313 static int
4314 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4315 {
4316         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4317 }
4318
4319 static int
4320 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4321 {
4322         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4323 }
4324
4325 static int
4326 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4327 {
4328         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4329         uint32_t fctrl;
4330
4331         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4332         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4333         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4334
4335         return 0;
4336 }
4337
4338 static int
4339 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4340 {
4341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342         uint32_t fctrl;
4343
4344         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4345         fctrl &= (~IXGBE_FCTRL_UPE);
4346         if (dev->data->all_multicast == 1)
4347                 fctrl |= IXGBE_FCTRL_MPE;
4348         else
4349                 fctrl &= (~IXGBE_FCTRL_MPE);
4350         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4351
4352         return 0;
4353 }
4354
4355 static int
4356 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4357 {
4358         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4359         uint32_t fctrl;
4360
4361         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4362         fctrl |= IXGBE_FCTRL_MPE;
4363         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4364
4365         return 0;
4366 }
4367
4368 static int
4369 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4370 {
4371         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4372         uint32_t fctrl;
4373
4374         if (dev->data->promiscuous == 1)
4375                 return 0; /* must remain in all_multicast mode */
4376
4377         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4378         fctrl &= (~IXGBE_FCTRL_MPE);
4379         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4380
4381         return 0;
4382 }
4383
4384 /**
4385  * It clears the interrupt causes and enables the interrupt.
4386  * It will be called once only during nic initialized.
4387  *
4388  * @param dev
4389  *  Pointer to struct rte_eth_dev.
4390  * @param on
4391  *  Enable or Disable.
4392  *
4393  * @return
4394  *  - On success, zero.
4395  *  - On failure, a negative value.
4396  */
4397 static int
4398 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4399 {
4400         struct ixgbe_interrupt *intr =
4401                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4402
4403         ixgbe_dev_link_status_print(dev);
4404         if (on)
4405                 intr->mask |= IXGBE_EICR_LSC;
4406         else
4407                 intr->mask &= ~IXGBE_EICR_LSC;
4408
4409         return 0;
4410 }
4411
4412 /**
4413  * It clears the interrupt causes and enables the interrupt.
4414  * It will be called once only during nic initialized.
4415  *
4416  * @param dev
4417  *  Pointer to struct rte_eth_dev.
4418  *
4419  * @return
4420  *  - On success, zero.
4421  *  - On failure, a negative value.
4422  */
4423 static int
4424 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4425 {
4426         struct ixgbe_interrupt *intr =
4427                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4428
4429         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4430
4431         return 0;
4432 }
4433
4434 /**
4435  * It clears the interrupt causes and enables the interrupt.
4436  * It will be called once only during nic initialized.
4437  *
4438  * @param dev
4439  *  Pointer to struct rte_eth_dev.
4440  *
4441  * @return
4442  *  - On success, zero.
4443  *  - On failure, a negative value.
4444  */
4445 static int
4446 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4447 {
4448         struct ixgbe_interrupt *intr =
4449                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4450
4451         intr->mask |= IXGBE_EICR_LINKSEC;
4452
4453         return 0;
4454 }
4455
4456 /*
4457  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4458  *
4459  * @param dev
4460  *  Pointer to struct rte_eth_dev.
4461  *
4462  * @return
4463  *  - On success, zero.
4464  *  - On failure, a negative value.
4465  */
4466 static int
4467 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4468 {
4469         uint32_t eicr;
4470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4471         struct ixgbe_interrupt *intr =
4472                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4473
4474         /* clear all cause mask */
4475         ixgbe_disable_intr(hw);
4476
4477         /* read-on-clear nic registers here */
4478         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4479         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4480
4481         intr->flags = 0;
4482
4483         /* set flag for async link update */
4484         if (eicr & IXGBE_EICR_LSC)
4485                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4486
4487         if (eicr & IXGBE_EICR_MAILBOX)
4488                 intr->flags |= IXGBE_FLAG_MAILBOX;
4489
4490         if (eicr & IXGBE_EICR_LINKSEC)
4491                 intr->flags |= IXGBE_FLAG_MACSEC;
4492
4493         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4494             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4495             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4496                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4497
4498         return 0;
4499 }
4500
4501 /**
4502  * It gets and then prints the link status.
4503  *
4504  * @param dev
4505  *  Pointer to struct rte_eth_dev.
4506  *
4507  * @return
4508  *  - On success, zero.
4509  *  - On failure, a negative value.
4510  */
4511 static void
4512 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4513 {
4514         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4515         struct rte_eth_link link;
4516
4517         rte_eth_linkstatus_get(dev, &link);
4518
4519         if (link.link_status) {
4520                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4521                                         (int)(dev->data->port_id),
4522                                         (unsigned)link.link_speed,
4523                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4524                                         "full-duplex" : "half-duplex");
4525         } else {
4526                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4527                                 (int)(dev->data->port_id));
4528         }
4529         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4530                                 pci_dev->addr.domain,
4531                                 pci_dev->addr.bus,
4532                                 pci_dev->addr.devid,
4533                                 pci_dev->addr.function);
4534 }
4535
4536 /*
4537  * It executes link_update after knowing an interrupt occurred.
4538  *
4539  * @param dev
4540  *  Pointer to struct rte_eth_dev.
4541  *
4542  * @return
4543  *  - On success, zero.
4544  *  - On failure, a negative value.
4545  */
4546 static int
4547 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4548 {
4549         struct ixgbe_interrupt *intr =
4550                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4551         int64_t timeout;
4552         struct ixgbe_hw *hw =
4553                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4554
4555         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4556
4557         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4558                 ixgbe_pf_mbx_process(dev);
4559                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4560         }
4561
4562         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4563                 ixgbe_handle_lasi(hw);
4564                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4565         }
4566
4567         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4568                 struct rte_eth_link link;
4569
4570                 /* get the link status before link update, for predicting later */
4571                 rte_eth_linkstatus_get(dev, &link);
4572
4573                 ixgbe_dev_link_update(dev, 0);
4574
4575                 /* likely to up */
4576                 if (!link.link_status)
4577                         /* handle it 1 sec later, wait it being stable */
4578                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4579                 /* likely to down */
4580                 else
4581                         /* handle it 4 sec later, wait it being stable */
4582                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4583
4584                 ixgbe_dev_link_status_print(dev);
4585                 if (rte_eal_alarm_set(timeout * 1000,
4586                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4587                         PMD_DRV_LOG(ERR, "Error setting alarm");
4588                 else {
4589                         /* remember original mask */
4590                         intr->mask_original = intr->mask;
4591                         /* only disable lsc interrupt */
4592                         intr->mask &= ~IXGBE_EIMS_LSC;
4593                 }
4594         }
4595
4596         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4597         ixgbe_enable_intr(dev);
4598
4599         return 0;
4600 }
4601
4602 /**
4603  * Interrupt handler which shall be registered for alarm callback for delayed
4604  * handling specific interrupt to wait for the stable nic state. As the
4605  * NIC interrupt state is not stable for ixgbe after link is just down,
4606  * it needs to wait 4 seconds to get the stable status.
4607  *
4608  * @param handle
4609  *  Pointer to interrupt handle.
4610  * @param param
4611  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4612  *
4613  * @return
4614  *  void
4615  */
4616 static void
4617 ixgbe_dev_interrupt_delayed_handler(void *param)
4618 {
4619         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4620         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4621         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4622         struct ixgbe_interrupt *intr =
4623                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4624         struct ixgbe_hw *hw =
4625                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4626         uint32_t eicr;
4627
4628         ixgbe_disable_intr(hw);
4629
4630         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4631         if (eicr & IXGBE_EICR_MAILBOX)
4632                 ixgbe_pf_mbx_process(dev);
4633
4634         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4635                 ixgbe_handle_lasi(hw);
4636                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4637         }
4638
4639         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4640                 ixgbe_dev_link_update(dev, 0);
4641                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4642                 ixgbe_dev_link_status_print(dev);
4643                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4644         }
4645
4646         if (intr->flags & IXGBE_FLAG_MACSEC) {
4647                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4648                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4649         }
4650
4651         /* restore original mask */
4652         intr->mask = intr->mask_original;
4653         intr->mask_original = 0;
4654
4655         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4656         ixgbe_enable_intr(dev);
4657         rte_intr_ack(intr_handle);
4658 }
4659
4660 /**
4661  * Interrupt handler triggered by NIC  for handling
4662  * specific interrupt.
4663  *
4664  * @param handle
4665  *  Pointer to interrupt handle.
4666  * @param param
4667  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4668  *
4669  * @return
4670  *  void
4671  */
4672 static void
4673 ixgbe_dev_interrupt_handler(void *param)
4674 {
4675         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4676
4677         ixgbe_dev_interrupt_get_status(dev);
4678         ixgbe_dev_interrupt_action(dev);
4679 }
4680
4681 static int
4682 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4683 {
4684         struct ixgbe_hw *hw;
4685
4686         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4687         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4688 }
4689
4690 static int
4691 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4692 {
4693         struct ixgbe_hw *hw;
4694
4695         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4696         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4697 }
4698
4699 static int
4700 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4701 {
4702         struct ixgbe_hw *hw;
4703         uint32_t mflcn_reg;
4704         uint32_t fccfg_reg;
4705         int rx_pause;
4706         int tx_pause;
4707
4708         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4709
4710         fc_conf->pause_time = hw->fc.pause_time;
4711         fc_conf->high_water = hw->fc.high_water[0];
4712         fc_conf->low_water = hw->fc.low_water[0];
4713         fc_conf->send_xon = hw->fc.send_xon;
4714         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4715
4716         /*
4717          * Return rx_pause status according to actual setting of
4718          * MFLCN register.
4719          */
4720         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4721         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4722                 fc_conf->mac_ctrl_frame_fwd = 1;
4723         else
4724                 fc_conf->mac_ctrl_frame_fwd = 0;
4725
4726         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4727                 rx_pause = 1;
4728         else
4729                 rx_pause = 0;
4730
4731         /*
4732          * Return tx_pause status according to actual setting of
4733          * FCCFG register.
4734          */
4735         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4736         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4737                 tx_pause = 1;
4738         else
4739                 tx_pause = 0;
4740
4741         if (rx_pause && tx_pause)
4742                 fc_conf->mode = RTE_FC_FULL;
4743         else if (rx_pause)
4744                 fc_conf->mode = RTE_FC_RX_PAUSE;
4745         else if (tx_pause)
4746                 fc_conf->mode = RTE_FC_TX_PAUSE;
4747         else
4748                 fc_conf->mode = RTE_FC_NONE;
4749
4750         return 0;
4751 }
4752
4753 static int
4754 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4755 {
4756         struct ixgbe_hw *hw;
4757         struct ixgbe_adapter *adapter = dev->data->dev_private;
4758         int err;
4759         uint32_t rx_buf_size;
4760         uint32_t max_high_water;
4761         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4762                 ixgbe_fc_none,
4763                 ixgbe_fc_rx_pause,
4764                 ixgbe_fc_tx_pause,
4765                 ixgbe_fc_full
4766         };
4767
4768         PMD_INIT_FUNC_TRACE();
4769
4770         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4771         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4772         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4773
4774         /*
4775          * At least reserve one Ethernet frame for watermark
4776          * high_water/low_water in kilo bytes for ixgbe
4777          */
4778         max_high_water = (rx_buf_size -
4779                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4780         if ((fc_conf->high_water > max_high_water) ||
4781                 (fc_conf->high_water < fc_conf->low_water)) {
4782                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4783                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4784                 return -EINVAL;
4785         }
4786
4787         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4788         hw->fc.pause_time     = fc_conf->pause_time;
4789         hw->fc.high_water[0]  = fc_conf->high_water;
4790         hw->fc.low_water[0]   = fc_conf->low_water;
4791         hw->fc.send_xon       = fc_conf->send_xon;
4792         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4793         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4794
4795         err = ixgbe_flow_ctrl_enable(dev, hw);
4796         if (err < 0) {
4797                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4798                 return -EIO;
4799         }
4800         return err;
4801 }
4802
4803 /**
4804  *  ixgbe_pfc_enable_generic - Enable flow control
4805  *  @hw: pointer to hardware structure
4806  *  @tc_num: traffic class number
4807  *  Enable flow control according to the current settings.
4808  */
4809 static int
4810 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4811 {
4812         int ret_val = 0;
4813         uint32_t mflcn_reg, fccfg_reg;
4814         uint32_t reg;
4815         uint32_t fcrtl, fcrth;
4816         uint8_t i;
4817         uint8_t nb_rx_en;
4818
4819         /* Validate the water mark configuration */
4820         if (!hw->fc.pause_time) {
4821                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4822                 goto out;
4823         }
4824
4825         /* Low water mark of zero causes XOFF floods */
4826         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4827                  /* High/Low water can not be 0 */
4828                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4829                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4830                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4831                         goto out;
4832                 }
4833
4834                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4835                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4836                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4837                         goto out;
4838                 }
4839         }
4840         /* Negotiate the fc mode to use */
4841         ixgbe_fc_autoneg(hw);
4842
4843         /* Disable any previous flow control settings */
4844         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4845         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4846
4847         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4848         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4849
4850         switch (hw->fc.current_mode) {
4851         case ixgbe_fc_none:
4852                 /*
4853                  * If the count of enabled RX Priority Flow control >1,
4854                  * and the TX pause can not be disabled
4855                  */
4856                 nb_rx_en = 0;
4857                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4858                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4859                         if (reg & IXGBE_FCRTH_FCEN)
4860                                 nb_rx_en++;
4861                 }
4862                 if (nb_rx_en > 1)
4863                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4864                 break;
4865         case ixgbe_fc_rx_pause:
4866                 /*
4867                  * Rx Flow control is enabled and Tx Flow control is
4868                  * disabled by software override. Since there really
4869                  * isn't a way to advertise that we are capable of RX
4870                  * Pause ONLY, we will advertise that we support both
4871                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4872                  * disable the adapter's ability to send PAUSE frames.
4873                  */
4874                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4875                 /*
4876                  * If the count of enabled RX Priority Flow control >1,
4877                  * and the TX pause can not be disabled
4878                  */
4879                 nb_rx_en = 0;
4880                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4881                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4882                         if (reg & IXGBE_FCRTH_FCEN)
4883                                 nb_rx_en++;
4884                 }
4885                 if (nb_rx_en > 1)
4886                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4887                 break;
4888         case ixgbe_fc_tx_pause:
4889                 /*
4890                  * Tx Flow control is enabled, and Rx Flow control is
4891                  * disabled by software override.
4892                  */
4893                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4894                 break;
4895         case ixgbe_fc_full:
4896                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4897                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4898                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4899                 break;
4900         default:
4901                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4902                 ret_val = IXGBE_ERR_CONFIG;
4903                 goto out;
4904         }
4905
4906         /* Set 802.3x based flow control settings. */
4907         mflcn_reg |= IXGBE_MFLCN_DPF;
4908         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4909         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4910
4911         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4912         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4913                 hw->fc.high_water[tc_num]) {
4914                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4915                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4916                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4917         } else {
4918                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4919                 /*
4920                  * In order to prevent Tx hangs when the internal Tx
4921                  * switch is enabled we must set the high water mark
4922                  * to the maximum FCRTH value.  This allows the Tx
4923                  * switch to function even under heavy Rx workloads.
4924                  */
4925                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4926         }
4927         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4928
4929         /* Configure pause time (2 TCs per register) */
4930         reg = hw->fc.pause_time * 0x00010001;
4931         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4932                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4933
4934         /* Configure flow control refresh threshold value */
4935         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4936
4937 out:
4938         return ret_val;
4939 }
4940
4941 static int
4942 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4943 {
4944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4945         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4946
4947         if (hw->mac.type != ixgbe_mac_82598EB) {
4948                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4949         }
4950         return ret_val;
4951 }
4952
4953 static int
4954 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4955 {
4956         int err;
4957         uint32_t rx_buf_size;
4958         uint32_t max_high_water;
4959         uint8_t tc_num;
4960         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4961         struct ixgbe_hw *hw =
4962                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4963         struct ixgbe_dcb_config *dcb_config =
4964                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4965
4966         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4967                 ixgbe_fc_none,
4968                 ixgbe_fc_rx_pause,
4969                 ixgbe_fc_tx_pause,
4970                 ixgbe_fc_full
4971         };
4972
4973         PMD_INIT_FUNC_TRACE();
4974
4975         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4976         tc_num = map[pfc_conf->priority];
4977         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4978         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4979         /*
4980          * At least reserve one Ethernet frame for watermark
4981          * high_water/low_water in kilo bytes for ixgbe
4982          */
4983         max_high_water = (rx_buf_size -
4984                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4985         if ((pfc_conf->fc.high_water > max_high_water) ||
4986             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4987                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4988                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4989                 return -EINVAL;
4990         }
4991
4992         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4993         hw->fc.pause_time = pfc_conf->fc.pause_time;
4994         hw->fc.send_xon = pfc_conf->fc.send_xon;
4995         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4996         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4997
4998         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4999
5000         /* Not negotiated is not an error case */
5001         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5002                 return 0;
5003
5004         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5005         return -EIO;
5006 }
5007
5008 static int
5009 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5010                           struct rte_eth_rss_reta_entry64 *reta_conf,
5011                           uint16_t reta_size)
5012 {
5013         uint16_t i, sp_reta_size;
5014         uint8_t j, mask;
5015         uint32_t reta, r;
5016         uint16_t idx, shift;
5017         struct ixgbe_adapter *adapter = dev->data->dev_private;
5018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5019         uint32_t reta_reg;
5020
5021         PMD_INIT_FUNC_TRACE();
5022
5023         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5024                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5025                         "NIC.");
5026                 return -ENOTSUP;
5027         }
5028
5029         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5030         if (reta_size != sp_reta_size) {
5031                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5032                         "(%d) doesn't match the number hardware can supported "
5033                         "(%d)", reta_size, sp_reta_size);
5034                 return -EINVAL;
5035         }
5036
5037         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5038                 idx = i / RTE_RETA_GROUP_SIZE;
5039                 shift = i % RTE_RETA_GROUP_SIZE;
5040                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5041                                                 IXGBE_4_BIT_MASK);
5042                 if (!mask)
5043                         continue;
5044                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5045                 if (mask == IXGBE_4_BIT_MASK)
5046                         r = 0;
5047                 else
5048                         r = IXGBE_READ_REG(hw, reta_reg);
5049                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5050                         if (mask & (0x1 << j))
5051                                 reta |= reta_conf[idx].reta[shift + j] <<
5052                                                         (CHAR_BIT * j);
5053                         else
5054                                 reta |= r & (IXGBE_8_BIT_MASK <<
5055                                                 (CHAR_BIT * j));
5056                 }
5057                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5058         }
5059         adapter->rss_reta_updated = 1;
5060
5061         return 0;
5062 }
5063
5064 static int
5065 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5066                          struct rte_eth_rss_reta_entry64 *reta_conf,
5067                          uint16_t reta_size)
5068 {
5069         uint16_t i, sp_reta_size;
5070         uint8_t j, mask;
5071         uint32_t reta;
5072         uint16_t idx, shift;
5073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5074         uint32_t reta_reg;
5075
5076         PMD_INIT_FUNC_TRACE();
5077         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5078         if (reta_size != sp_reta_size) {
5079                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5080                         "(%d) doesn't match the number hardware can supported "
5081                         "(%d)", reta_size, sp_reta_size);
5082                 return -EINVAL;
5083         }
5084
5085         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5086                 idx = i / RTE_RETA_GROUP_SIZE;
5087                 shift = i % RTE_RETA_GROUP_SIZE;
5088                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5089                                                 IXGBE_4_BIT_MASK);
5090                 if (!mask)
5091                         continue;
5092
5093                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5094                 reta = IXGBE_READ_REG(hw, reta_reg);
5095                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5096                         if (mask & (0x1 << j))
5097                                 reta_conf[idx].reta[shift + j] =
5098                                         ((reta >> (CHAR_BIT * j)) &
5099                                                 IXGBE_8_BIT_MASK);
5100                 }
5101         }
5102
5103         return 0;
5104 }
5105
5106 static int
5107 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5108                                 uint32_t index, uint32_t pool)
5109 {
5110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5111         uint32_t enable_addr = 1;
5112
5113         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5114                              pool, enable_addr);
5115 }
5116
5117 static void
5118 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5119 {
5120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5121
5122         ixgbe_clear_rar(hw, index);
5123 }
5124
5125 static int
5126 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5127 {
5128         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5129
5130         ixgbe_remove_rar(dev, 0);
5131         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5132
5133         return 0;
5134 }
5135
5136 static bool
5137 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5138 {
5139         if (strcmp(dev->device->driver->name, drv->driver.name))
5140                 return false;
5141
5142         return true;
5143 }
5144
5145 bool
5146 is_ixgbe_supported(struct rte_eth_dev *dev)
5147 {
5148         return is_device_supported(dev, &rte_ixgbe_pmd);
5149 }
5150
5151 static int
5152 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5153 {
5154         uint32_t hlreg0;
5155         uint32_t maxfrs;
5156         struct ixgbe_hw *hw;
5157         struct rte_eth_dev_info dev_info;
5158         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5159         struct rte_eth_dev_data *dev_data = dev->data;
5160         int ret;
5161
5162         ret = ixgbe_dev_info_get(dev, &dev_info);
5163         if (ret != 0)
5164                 return ret;
5165
5166         /* check that mtu is within the allowed range */
5167         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5168                 return -EINVAL;
5169
5170         /* If device is started, refuse mtu that requires the support of
5171          * scattered packets when this feature has not been enabled before.
5172          */
5173         if (dev_data->dev_started && !dev_data->scattered_rx &&
5174             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5175              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5176                 PMD_INIT_LOG(ERR, "Stop port first.");
5177                 return -EINVAL;
5178         }
5179
5180         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5181         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5182
5183         /* switch to jumbo mode if needed */
5184         if (frame_size > IXGBE_ETH_MAX_LEN) {
5185                 dev->data->dev_conf.rxmode.offloads |=
5186                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5187                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5188         } else {
5189                 dev->data->dev_conf.rxmode.offloads &=
5190                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5191                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5192         }
5193         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5194
5195         /* update max frame size */
5196         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5197
5198         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5199         maxfrs &= 0x0000FFFF;
5200         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5201         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5202
5203         return 0;
5204 }
5205
5206 /*
5207  * Virtual Function operations
5208  */
5209 static void
5210 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5211 {
5212         struct ixgbe_interrupt *intr =
5213                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5214         struct ixgbe_hw *hw =
5215                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5216
5217         PMD_INIT_FUNC_TRACE();
5218
5219         /* Clear interrupt mask to stop from interrupts being generated */
5220         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5221
5222         IXGBE_WRITE_FLUSH(hw);
5223
5224         /* Clear mask value. */
5225         intr->mask = 0;
5226 }
5227
5228 static void
5229 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5230 {
5231         struct ixgbe_interrupt *intr =
5232                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5233         struct ixgbe_hw *hw =
5234                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5235
5236         PMD_INIT_FUNC_TRACE();
5237
5238         /* VF enable interrupt autoclean */
5239         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5240         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5241         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5242
5243         IXGBE_WRITE_FLUSH(hw);
5244
5245         /* Save IXGBE_VTEIMS value to mask. */
5246         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5247 }
5248
5249 static int
5250 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5251 {
5252         struct rte_eth_conf *conf = &dev->data->dev_conf;
5253         struct ixgbe_adapter *adapter = dev->data->dev_private;
5254
5255         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5256                      dev->data->port_id);
5257
5258         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5259                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5260
5261         /*
5262          * VF has no ability to enable/disable HW CRC
5263          * Keep the persistent behavior the same as Host PF
5264          */
5265 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5266         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5267                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5268                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5269         }
5270 #else
5271         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5272                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5273                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5274         }
5275 #endif
5276
5277         /*
5278          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5279          * allocation or vector Rx preconditions we will reset it.
5280          */
5281         adapter->rx_bulk_alloc_allowed = true;
5282         adapter->rx_vec_allowed = true;
5283
5284         return 0;
5285 }
5286
5287 static int
5288 ixgbevf_dev_start(struct rte_eth_dev *dev)
5289 {
5290         struct ixgbe_hw *hw =
5291                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5292         uint32_t intr_vector = 0;
5293         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5294         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5295
5296         int err, mask = 0;
5297
5298         PMD_INIT_FUNC_TRACE();
5299
5300         /* Stop the link setup handler before resetting the HW. */
5301         ixgbe_dev_wait_setup_link_complete(dev, 0);
5302
5303         err = hw->mac.ops.reset_hw(hw);
5304
5305         /**
5306          * In this case, reuses the MAC address assigned by VF
5307          * initialization.
5308          */
5309         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5310                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5311                 return err;
5312         }
5313
5314         hw->mac.get_link_status = true;
5315
5316         /* negotiate mailbox API version to use with the PF. */
5317         ixgbevf_negotiate_api(hw);
5318
5319         ixgbevf_dev_tx_init(dev);
5320
5321         /* This can fail when allocating mbufs for descriptor rings */
5322         err = ixgbevf_dev_rx_init(dev);
5323         if (err) {
5324                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5325                 ixgbe_dev_clear_queues(dev);
5326                 return err;
5327         }
5328
5329         /* Set vfta */
5330         ixgbevf_set_vfta_all(dev, 1);
5331
5332         /* Set HW strip */
5333         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5334                 ETH_VLAN_EXTEND_MASK;
5335         err = ixgbevf_vlan_offload_config(dev, mask);
5336         if (err) {
5337                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5338                 ixgbe_dev_clear_queues(dev);
5339                 return err;
5340         }
5341
5342         ixgbevf_dev_rxtx_start(dev);
5343
5344         /* check and configure queue intr-vector mapping */
5345         if (rte_intr_cap_multiple(intr_handle) &&
5346             dev->data->dev_conf.intr_conf.rxq) {
5347                 /* According to datasheet, only vector 0/1/2 can be used,
5348                  * now only one vector is used for Rx queue
5349                  */
5350                 intr_vector = 1;
5351                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5352                         return -1;
5353         }
5354
5355         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5356                 intr_handle->intr_vec =
5357                         rte_zmalloc("intr_vec",
5358                                     dev->data->nb_rx_queues * sizeof(int), 0);
5359                 if (intr_handle->intr_vec == NULL) {
5360                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5361                                      " intr_vec", dev->data->nb_rx_queues);
5362                         return -ENOMEM;
5363                 }
5364         }
5365         ixgbevf_configure_msix(dev);
5366
5367         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5368          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5369          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5370          * is not cleared, it will fail when following rte_intr_enable( ) tries
5371          * to map Rx queue interrupt to other VFIO vectors.
5372          * So clear uio/vfio intr/evevnfd first to avoid failure.
5373          */
5374         rte_intr_disable(intr_handle);
5375
5376         rte_intr_enable(intr_handle);
5377
5378         /* Re-enable interrupt for VF */
5379         ixgbevf_intr_enable(dev);
5380
5381         /*
5382          * Update link status right before return, because it may
5383          * start link configuration process in a separate thread.
5384          */
5385         ixgbevf_dev_link_update(dev, 0);
5386
5387         hw->adapter_stopped = false;
5388
5389         return 0;
5390 }
5391
5392 static int
5393 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5394 {
5395         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5396         struct ixgbe_adapter *adapter = dev->data->dev_private;
5397         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5398         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5399
5400         if (hw->adapter_stopped)
5401                 return 0;
5402
5403         PMD_INIT_FUNC_TRACE();
5404
5405         ixgbe_dev_wait_setup_link_complete(dev, 0);
5406
5407         ixgbevf_intr_disable(dev);
5408
5409         dev->data->dev_started = 0;
5410         hw->adapter_stopped = 1;
5411         ixgbe_stop_adapter(hw);
5412
5413         /*
5414           * Clear what we set, but we still keep shadow_vfta to
5415           * restore after device starts
5416           */
5417         ixgbevf_set_vfta_all(dev, 0);
5418
5419         /* Clear stored conf */
5420         dev->data->scattered_rx = 0;
5421
5422         ixgbe_dev_clear_queues(dev);
5423
5424         /* Clean datapath event and queue/vec mapping */
5425         rte_intr_efd_disable(intr_handle);
5426         if (intr_handle->intr_vec != NULL) {
5427                 rte_free(intr_handle->intr_vec);
5428                 intr_handle->intr_vec = NULL;
5429         }
5430
5431         adapter->rss_reta_updated = 0;
5432
5433         return 0;
5434 }
5435
5436 static int
5437 ixgbevf_dev_close(struct rte_eth_dev *dev)
5438 {
5439         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5440         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5441         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5442         int ret;
5443
5444         PMD_INIT_FUNC_TRACE();
5445         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5446                 return 0;
5447
5448         ixgbe_reset_hw(hw);
5449
5450         ret = ixgbevf_dev_stop(dev);
5451
5452         ixgbe_dev_free_queues(dev);
5453
5454         /**
5455          * Remove the VF MAC address ro ensure
5456          * that the VF traffic goes to the PF
5457          * after stop, close and detach of the VF
5458          **/
5459         ixgbevf_remove_mac_addr(dev, 0);
5460
5461         rte_intr_disable(intr_handle);
5462         rte_intr_callback_unregister(intr_handle,
5463                                      ixgbevf_dev_interrupt_handler, dev);
5464
5465         return ret;
5466 }
5467
5468 /*
5469  * Reset VF device
5470  */
5471 static int
5472 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5473 {
5474         int ret;
5475
5476         ret = eth_ixgbevf_dev_uninit(dev);
5477         if (ret)
5478                 return ret;
5479
5480         ret = eth_ixgbevf_dev_init(dev);
5481
5482         return ret;
5483 }
5484
5485 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5486 {
5487         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5488         struct ixgbe_vfta *shadow_vfta =
5489                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5490         int i = 0, j = 0, vfta = 0, mask = 1;
5491
5492         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5493                 vfta = shadow_vfta->vfta[i];
5494                 if (vfta) {
5495                         mask = 1;
5496                         for (j = 0; j < 32; j++) {
5497                                 if (vfta & mask)
5498                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5499                                                        on, false);
5500                                 mask <<= 1;
5501                         }
5502                 }
5503         }
5504
5505 }
5506
5507 static int
5508 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5509 {
5510         struct ixgbe_hw *hw =
5511                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5512         struct ixgbe_vfta *shadow_vfta =
5513                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5514         uint32_t vid_idx = 0;
5515         uint32_t vid_bit = 0;
5516         int ret = 0;
5517
5518         PMD_INIT_FUNC_TRACE();
5519
5520         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5521         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5522         if (ret) {
5523                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5524                 return ret;
5525         }
5526         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5527         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5528
5529         /* Save what we set and retore it after device reset */
5530         if (on)
5531                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5532         else
5533                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5534
5535         return 0;
5536 }
5537
5538 static void
5539 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5540 {
5541         struct ixgbe_hw *hw =
5542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5543         uint32_t ctrl;
5544
5545         PMD_INIT_FUNC_TRACE();
5546
5547         if (queue >= hw->mac.max_rx_queues)
5548                 return;
5549
5550         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5551         if (on)
5552                 ctrl |= IXGBE_RXDCTL_VME;
5553         else
5554                 ctrl &= ~IXGBE_RXDCTL_VME;
5555         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5556
5557         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5558 }
5559
5560 static int
5561 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5562 {
5563         struct ixgbe_rx_queue *rxq;
5564         uint16_t i;
5565         int on = 0;
5566
5567         /* VF function only support hw strip feature, others are not support */
5568         if (mask & ETH_VLAN_STRIP_MASK) {
5569                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5570                         rxq = dev->data->rx_queues[i];
5571                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5572                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5573                 }
5574         }
5575
5576         return 0;
5577 }
5578
5579 static int
5580 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5581 {
5582         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5583
5584         ixgbevf_vlan_offload_config(dev, mask);
5585
5586         return 0;
5587 }
5588
5589 int
5590 ixgbe_vt_check(struct ixgbe_hw *hw)
5591 {
5592         uint32_t reg_val;
5593
5594         /* if Virtualization Technology is enabled */
5595         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5596         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5597                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5598                 return -1;
5599         }
5600
5601         return 0;
5602 }
5603
5604 static uint32_t
5605 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5606 {
5607         uint32_t vector = 0;
5608
5609         switch (hw->mac.mc_filter_type) {
5610         case 0:   /* use bits [47:36] of the address */
5611                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5612                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5613                 break;
5614         case 1:   /* use bits [46:35] of the address */
5615                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5616                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5617                 break;
5618         case 2:   /* use bits [45:34] of the address */
5619                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5620                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5621                 break;
5622         case 3:   /* use bits [43:32] of the address */
5623                 vector = ((uc_addr->addr_bytes[4]) |
5624                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5625                 break;
5626         default:  /* Invalid mc_filter_type */
5627                 break;
5628         }
5629
5630         /* vector can only be 12-bits or boundary will be exceeded */
5631         vector &= 0xFFF;
5632         return vector;
5633 }
5634
5635 static int
5636 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5637                         struct rte_ether_addr *mac_addr, uint8_t on)
5638 {
5639         uint32_t vector;
5640         uint32_t uta_idx;
5641         uint32_t reg_val;
5642         uint32_t uta_shift;
5643         uint32_t rc;
5644         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5645         const uint32_t ixgbe_uta_bit_shift = 5;
5646         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5647         const uint32_t bit1 = 0x1;
5648
5649         struct ixgbe_hw *hw =
5650                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5651         struct ixgbe_uta_info *uta_info =
5652                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5653
5654         /* The UTA table only exists on 82599 hardware and newer */
5655         if (hw->mac.type < ixgbe_mac_82599EB)
5656                 return -ENOTSUP;
5657
5658         vector = ixgbe_uta_vector(hw, mac_addr);
5659         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5660         uta_shift = vector & ixgbe_uta_bit_mask;
5661
5662         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5663         if (rc == on)
5664                 return 0;
5665
5666         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5667         if (on) {
5668                 uta_info->uta_in_use++;
5669                 reg_val |= (bit1 << uta_shift);
5670                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5671         } else {
5672                 uta_info->uta_in_use--;
5673                 reg_val &= ~(bit1 << uta_shift);
5674                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5675         }
5676
5677         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5678
5679         if (uta_info->uta_in_use > 0)
5680                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5681                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5682         else
5683                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5684
5685         return 0;
5686 }
5687
5688 static int
5689 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5690 {
5691         int i;
5692         struct ixgbe_hw *hw =
5693                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5694         struct ixgbe_uta_info *uta_info =
5695                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5696
5697         /* The UTA table only exists on 82599 hardware and newer */
5698         if (hw->mac.type < ixgbe_mac_82599EB)
5699                 return -ENOTSUP;
5700
5701         if (on) {
5702                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5703                         uta_info->uta_shadow[i] = ~0;
5704                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5705                 }
5706         } else {
5707                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5708                         uta_info->uta_shadow[i] = 0;
5709                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5710                 }
5711         }
5712         return 0;
5713
5714 }
5715
5716 uint32_t
5717 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5718 {
5719         uint32_t new_val = orig_val;
5720
5721         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5722                 new_val |= IXGBE_VMOLR_AUPE;
5723         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5724                 new_val |= IXGBE_VMOLR_ROMPE;
5725         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5726                 new_val |= IXGBE_VMOLR_ROPE;
5727         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5728                 new_val |= IXGBE_VMOLR_BAM;
5729         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5730                 new_val |= IXGBE_VMOLR_MPE;
5731
5732         return new_val;
5733 }
5734
5735 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5736 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5737 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5738 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5739 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5740         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5741         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5742
5743 static int
5744 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5745                       struct rte_eth_mirror_conf *mirror_conf,
5746                       uint8_t rule_id, uint8_t on)
5747 {
5748         uint32_t mr_ctl, vlvf;
5749         uint32_t mp_lsb = 0;
5750         uint32_t mv_msb = 0;
5751         uint32_t mv_lsb = 0;
5752         uint32_t mp_msb = 0;
5753         uint8_t i = 0;
5754         int reg_index = 0;
5755         uint64_t vlan_mask = 0;
5756
5757         const uint8_t pool_mask_offset = 32;
5758         const uint8_t vlan_mask_offset = 32;
5759         const uint8_t dst_pool_offset = 8;
5760         const uint8_t rule_mr_offset  = 4;
5761         const uint8_t mirror_rule_mask = 0x0F;
5762
5763         struct ixgbe_mirror_info *mr_info =
5764                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5765         struct ixgbe_hw *hw =
5766                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5767         uint8_t mirror_type = 0;
5768
5769         if (ixgbe_vt_check(hw) < 0)
5770                 return -ENOTSUP;
5771
5772         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5773                 return -EINVAL;
5774
5775         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5776                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5777                             mirror_conf->rule_type);
5778                 return -EINVAL;
5779         }
5780
5781         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5782                 mirror_type |= IXGBE_MRCTL_VLME;
5783                 /* Check if vlan id is valid and find conresponding VLAN ID
5784                  * index in VLVF
5785                  */
5786                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5787                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5788                                 /* search vlan id related pool vlan filter
5789                                  * index
5790                                  */
5791                                 reg_index = ixgbe_find_vlvf_slot(
5792                                                 hw,
5793                                                 mirror_conf->vlan.vlan_id[i],
5794                                                 false);
5795                                 if (reg_index < 0)
5796                                         return -EINVAL;
5797                                 vlvf = IXGBE_READ_REG(hw,
5798                                                       IXGBE_VLVF(reg_index));
5799                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5800                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5801                                       mirror_conf->vlan.vlan_id[i]))
5802                                         vlan_mask |= (1ULL << reg_index);
5803                                 else
5804                                         return -EINVAL;
5805                         }
5806                 }
5807
5808                 if (on) {
5809                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5810                         mv_msb = vlan_mask >> vlan_mask_offset;
5811
5812                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5813                                                 mirror_conf->vlan.vlan_mask;
5814                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5815                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5816                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5817                                                 mirror_conf->vlan.vlan_id[i];
5818                         }
5819                 } else {
5820                         mv_lsb = 0;
5821                         mv_msb = 0;
5822                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5823                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5824                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5825                 }
5826         }
5827
5828         /**
5829          * if enable pool mirror, write related pool mask register,if disable
5830          * pool mirror, clear PFMRVM register
5831          */
5832         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5833                 mirror_type |= IXGBE_MRCTL_VPME;
5834                 if (on) {
5835                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5836                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5837                         mr_info->mr_conf[rule_id].pool_mask =
5838                                         mirror_conf->pool_mask;
5839
5840                 } else {
5841                         mp_lsb = 0;
5842                         mp_msb = 0;
5843                         mr_info->mr_conf[rule_id].pool_mask = 0;
5844                 }
5845         }
5846         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5847                 mirror_type |= IXGBE_MRCTL_UPME;
5848         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5849                 mirror_type |= IXGBE_MRCTL_DPME;
5850
5851         /* read  mirror control register and recalculate it */
5852         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5853
5854         if (on) {
5855                 mr_ctl |= mirror_type;
5856                 mr_ctl &= mirror_rule_mask;
5857                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5858         } else {
5859                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5860         }
5861
5862         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5863         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5864
5865         /* write mirrror control  register */
5866         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5867
5868         /* write pool mirrror control  register */
5869         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5870                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5871                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5872                                 mp_msb);
5873         }
5874         /* write VLAN mirrror control  register */
5875         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5876                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5877                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5878                                 mv_msb);
5879         }
5880
5881         return 0;
5882 }
5883
5884 static int
5885 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5886 {
5887         int mr_ctl = 0;
5888         uint32_t lsb_val = 0;
5889         uint32_t msb_val = 0;
5890         const uint8_t rule_mr_offset = 4;
5891
5892         struct ixgbe_hw *hw =
5893                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5894         struct ixgbe_mirror_info *mr_info =
5895                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5896
5897         if (ixgbe_vt_check(hw) < 0)
5898                 return -ENOTSUP;
5899
5900         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5901                 return -EINVAL;
5902
5903         memset(&mr_info->mr_conf[rule_id], 0,
5904                sizeof(struct rte_eth_mirror_conf));
5905
5906         /* clear PFVMCTL register */
5907         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5908
5909         /* clear pool mask register */
5910         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5911         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5912
5913         /* clear vlan mask register */
5914         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5915         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5916
5917         return 0;
5918 }
5919
5920 static int
5921 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5922 {
5923         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5924         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5925         struct ixgbe_interrupt *intr =
5926                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5927         struct ixgbe_hw *hw =
5928                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5929         uint32_t vec = IXGBE_MISC_VEC_ID;
5930
5931         if (rte_intr_allow_others(intr_handle))
5932                 vec = IXGBE_RX_VEC_START;
5933         intr->mask |= (1 << vec);
5934         RTE_SET_USED(queue_id);
5935         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5936
5937         rte_intr_ack(intr_handle);
5938
5939         return 0;
5940 }
5941
5942 static int
5943 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5944 {
5945         struct ixgbe_interrupt *intr =
5946                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5947         struct ixgbe_hw *hw =
5948                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5949         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5950         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5951         uint32_t vec = IXGBE_MISC_VEC_ID;
5952
5953         if (rte_intr_allow_others(intr_handle))
5954                 vec = IXGBE_RX_VEC_START;
5955         intr->mask &= ~(1 << vec);
5956         RTE_SET_USED(queue_id);
5957         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5958
5959         return 0;
5960 }
5961
5962 static int
5963 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5964 {
5965         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5966         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5967         uint32_t mask;
5968         struct ixgbe_hw *hw =
5969                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5970         struct ixgbe_interrupt *intr =
5971                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5972
5973         if (queue_id < 16) {
5974                 ixgbe_disable_intr(hw);
5975                 intr->mask |= (1 << queue_id);
5976                 ixgbe_enable_intr(dev);
5977         } else if (queue_id < 32) {
5978                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5979                 mask &= (1 << queue_id);
5980                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5981         } else if (queue_id < 64) {
5982                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5983                 mask &= (1 << (queue_id - 32));
5984                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5985         }
5986         rte_intr_ack(intr_handle);
5987
5988         return 0;
5989 }
5990
5991 static int
5992 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5993 {
5994         uint32_t mask;
5995         struct ixgbe_hw *hw =
5996                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5997         struct ixgbe_interrupt *intr =
5998                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5999
6000         if (queue_id < 16) {
6001                 ixgbe_disable_intr(hw);
6002                 intr->mask &= ~(1 << queue_id);
6003                 ixgbe_enable_intr(dev);
6004         } else if (queue_id < 32) {
6005                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6006                 mask &= ~(1 << queue_id);
6007                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6008         } else if (queue_id < 64) {
6009                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6010                 mask &= ~(1 << (queue_id - 32));
6011                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6012         }
6013
6014         return 0;
6015 }
6016
6017 static void
6018 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6019                      uint8_t queue, uint8_t msix_vector)
6020 {
6021         uint32_t tmp, idx;
6022
6023         if (direction == -1) {
6024                 /* other causes */
6025                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6026                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6027                 tmp &= ~0xFF;
6028                 tmp |= msix_vector;
6029                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6030         } else {
6031                 /* rx or tx cause */
6032                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6033                 idx = ((16 * (queue & 1)) + (8 * direction));
6034                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6035                 tmp &= ~(0xFF << idx);
6036                 tmp |= (msix_vector << idx);
6037                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6038         }
6039 }
6040
6041 /**
6042  * set the IVAR registers, mapping interrupt causes to vectors
6043  * @param hw
6044  *  pointer to ixgbe_hw struct
6045  * @direction
6046  *  0 for Rx, 1 for Tx, -1 for other causes
6047  * @queue
6048  *  queue to map the corresponding interrupt to
6049  * @msix_vector
6050  *  the vector to map to the corresponding queue
6051  */
6052 static void
6053 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6054                    uint8_t queue, uint8_t msix_vector)
6055 {
6056         uint32_t tmp, idx;
6057
6058         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6059         if (hw->mac.type == ixgbe_mac_82598EB) {
6060                 if (direction == -1)
6061                         direction = 0;
6062                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6063                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6064                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6065                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6066                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6067         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6068                         (hw->mac.type == ixgbe_mac_X540) ||
6069                         (hw->mac.type == ixgbe_mac_X550) ||
6070                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6071                 if (direction == -1) {
6072                         /* other causes */
6073                         idx = ((queue & 1) * 8);
6074                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6075                         tmp &= ~(0xFF << idx);
6076                         tmp |= (msix_vector << idx);
6077                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6078                 } else {
6079                         /* rx or tx causes */
6080                         idx = ((16 * (queue & 1)) + (8 * direction));
6081                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6082                         tmp &= ~(0xFF << idx);
6083                         tmp |= (msix_vector << idx);
6084                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6085                 }
6086         }
6087 }
6088
6089 static void
6090 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6091 {
6092         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6093         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6094         struct ixgbe_hw *hw =
6095                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6096         uint32_t q_idx;
6097         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6098         uint32_t base = IXGBE_MISC_VEC_ID;
6099
6100         /* Configure VF other cause ivar */
6101         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6102
6103         /* won't configure msix register if no mapping is done
6104          * between intr vector and event fd.
6105          */
6106         if (!rte_intr_dp_is_en(intr_handle))
6107                 return;
6108
6109         if (rte_intr_allow_others(intr_handle)) {
6110                 base = IXGBE_RX_VEC_START;
6111                 vector_idx = IXGBE_RX_VEC_START;
6112         }
6113
6114         /* Configure all RX queues of VF */
6115         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6116                 /* Force all queue use vector 0,
6117                  * as IXGBE_VF_MAXMSIVECOTR = 1
6118                  */
6119                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6120                 intr_handle->intr_vec[q_idx] = vector_idx;
6121                 if (vector_idx < base + intr_handle->nb_efd - 1)
6122                         vector_idx++;
6123         }
6124
6125         /* As RX queue setting above show, all queues use the vector 0.
6126          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6127          */
6128         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6129                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6130                         | IXGBE_EITR_CNT_WDIS);
6131 }
6132
6133 /**
6134  * Sets up the hardware to properly generate MSI-X interrupts
6135  * @hw
6136  *  board private structure
6137  */
6138 static void
6139 ixgbe_configure_msix(struct rte_eth_dev *dev)
6140 {
6141         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6142         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6143         struct ixgbe_hw *hw =
6144                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6145         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6146         uint32_t vec = IXGBE_MISC_VEC_ID;
6147         uint32_t mask;
6148         uint32_t gpie;
6149
6150         /* won't configure msix register if no mapping is done
6151          * between intr vector and event fd
6152          * but if misx has been enabled already, need to configure
6153          * auto clean, auto mask and throttling.
6154          */
6155         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6156         if (!rte_intr_dp_is_en(intr_handle) &&
6157             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6158                 return;
6159
6160         if (rte_intr_allow_others(intr_handle))
6161                 vec = base = IXGBE_RX_VEC_START;
6162
6163         /* setup GPIE for MSI-x mode */
6164         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6165         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6166                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6167         /* auto clearing and auto setting corresponding bits in EIMS
6168          * when MSI-X interrupt is triggered
6169          */
6170         if (hw->mac.type == ixgbe_mac_82598EB) {
6171                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6172         } else {
6173                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6174                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6175         }
6176         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6177
6178         /* Populate the IVAR table and set the ITR values to the
6179          * corresponding register.
6180          */
6181         if (rte_intr_dp_is_en(intr_handle)) {
6182                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6183                         queue_id++) {
6184                         /* by default, 1:1 mapping */
6185                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6186                         intr_handle->intr_vec[queue_id] = vec;
6187                         if (vec < base + intr_handle->nb_efd - 1)
6188                                 vec++;
6189                 }
6190
6191                 switch (hw->mac.type) {
6192                 case ixgbe_mac_82598EB:
6193                         ixgbe_set_ivar_map(hw, -1,
6194                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6195                                            IXGBE_MISC_VEC_ID);
6196                         break;
6197                 case ixgbe_mac_82599EB:
6198                 case ixgbe_mac_X540:
6199                 case ixgbe_mac_X550:
6200                 case ixgbe_mac_X550EM_x:
6201                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6202                         break;
6203                 default:
6204                         break;
6205                 }
6206         }
6207         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6208                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6209                         | IXGBE_EITR_CNT_WDIS);
6210
6211         /* set up to autoclear timer, and the vectors */
6212         mask = IXGBE_EIMS_ENABLE_MASK;
6213         mask &= ~(IXGBE_EIMS_OTHER |
6214                   IXGBE_EIMS_MAILBOX |
6215                   IXGBE_EIMS_LSC);
6216
6217         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6218 }
6219
6220 int
6221 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6222                            uint16_t queue_idx, uint16_t tx_rate)
6223 {
6224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6225         struct rte_eth_rxmode *rxmode;
6226         uint32_t rf_dec, rf_int;
6227         uint32_t bcnrc_val;
6228         uint16_t link_speed = dev->data->dev_link.link_speed;
6229
6230         if (queue_idx >= hw->mac.max_tx_queues)
6231                 return -EINVAL;
6232
6233         if (tx_rate != 0) {
6234                 /* Calculate the rate factor values to set */
6235                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6236                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6237                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6238
6239                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6240                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6241                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6242                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6243         } else {
6244                 bcnrc_val = 0;
6245         }
6246
6247         rxmode = &dev->data->dev_conf.rxmode;
6248         /*
6249          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6250          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6251          * set as 0x4.
6252          */
6253         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6254             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6255                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6256                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6257         else
6258                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6259                         IXGBE_MMW_SIZE_DEFAULT);
6260
6261         /* Set RTTBCNRC of queue X */
6262         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6263         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6264         IXGBE_WRITE_FLUSH(hw);
6265
6266         return 0;
6267 }
6268
6269 static int
6270 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6271                      __rte_unused uint32_t index,
6272                      __rte_unused uint32_t pool)
6273 {
6274         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6275         int diag;
6276
6277         /*
6278          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6279          * operation. Trap this case to avoid exhausting the [very limited]
6280          * set of PF resources used to store VF MAC addresses.
6281          */
6282         if (memcmp(hw->mac.perm_addr, mac_addr,
6283                         sizeof(struct rte_ether_addr)) == 0)
6284                 return -1;
6285         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6286         if (diag != 0)
6287                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6288                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6289                             mac_addr->addr_bytes[0],
6290                             mac_addr->addr_bytes[1],
6291                             mac_addr->addr_bytes[2],
6292                             mac_addr->addr_bytes[3],
6293                             mac_addr->addr_bytes[4],
6294                             mac_addr->addr_bytes[5],
6295                             diag);
6296         return diag;
6297 }
6298
6299 static void
6300 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6301 {
6302         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6303         struct rte_ether_addr *perm_addr =
6304                 (struct rte_ether_addr *)hw->mac.perm_addr;
6305         struct rte_ether_addr *mac_addr;
6306         uint32_t i;
6307         int diag;
6308
6309         /*
6310          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6311          * not support the deletion of a given MAC address.
6312          * Instead, it imposes to delete all MAC addresses, then to add again
6313          * all MAC addresses with the exception of the one to be deleted.
6314          */
6315         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6316
6317         /*
6318          * Add again all MAC addresses, with the exception of the deleted one
6319          * and of the permanent MAC address.
6320          */
6321         for (i = 0, mac_addr = dev->data->mac_addrs;
6322              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6323                 /* Skip the deleted MAC address */
6324                 if (i == index)
6325                         continue;
6326                 /* Skip NULL MAC addresses */
6327                 if (rte_is_zero_ether_addr(mac_addr))
6328                         continue;
6329                 /* Skip the permanent MAC address */
6330                 if (memcmp(perm_addr, mac_addr,
6331                                 sizeof(struct rte_ether_addr)) == 0)
6332                         continue;
6333                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6334                 if (diag != 0)
6335                         PMD_DRV_LOG(ERR,
6336                                     "Adding again MAC address "
6337                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6338                                     "diag=%d",
6339                                     mac_addr->addr_bytes[0],
6340                                     mac_addr->addr_bytes[1],
6341                                     mac_addr->addr_bytes[2],
6342                                     mac_addr->addr_bytes[3],
6343                                     mac_addr->addr_bytes[4],
6344                                     mac_addr->addr_bytes[5],
6345                                     diag);
6346         }
6347 }
6348
6349 static int
6350 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6351                         struct rte_ether_addr *addr)
6352 {
6353         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6354
6355         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6356
6357         return 0;
6358 }
6359
6360 int
6361 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6362                         struct rte_eth_syn_filter *filter,
6363                         bool add)
6364 {
6365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6366         struct ixgbe_filter_info *filter_info =
6367                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6368         uint32_t syn_info;
6369         uint32_t synqf;
6370
6371         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6372                 return -EINVAL;
6373
6374         syn_info = filter_info->syn_info;
6375
6376         if (add) {
6377                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6378                         return -EINVAL;
6379                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6380                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6381
6382                 if (filter->hig_pri)
6383                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6384                 else
6385                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6386         } else {
6387                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6388                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6389                         return -ENOENT;
6390                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6391         }
6392
6393         filter_info->syn_info = synqf;
6394         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6395         IXGBE_WRITE_FLUSH(hw);
6396         return 0;
6397 }
6398
6399
6400 static inline enum ixgbe_5tuple_protocol
6401 convert_protocol_type(uint8_t protocol_value)
6402 {
6403         if (protocol_value == IPPROTO_TCP)
6404                 return IXGBE_FILTER_PROTOCOL_TCP;
6405         else if (protocol_value == IPPROTO_UDP)
6406                 return IXGBE_FILTER_PROTOCOL_UDP;
6407         else if (protocol_value == IPPROTO_SCTP)
6408                 return IXGBE_FILTER_PROTOCOL_SCTP;
6409         else
6410                 return IXGBE_FILTER_PROTOCOL_NONE;
6411 }
6412
6413 /* inject a 5-tuple filter to HW */
6414 static inline void
6415 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6416                            struct ixgbe_5tuple_filter *filter)
6417 {
6418         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6419         int i;
6420         uint32_t ftqf, sdpqf;
6421         uint32_t l34timir = 0;
6422         uint8_t mask = 0xff;
6423
6424         i = filter->index;
6425
6426         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6427                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6428         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6429
6430         ftqf = (uint32_t)(filter->filter_info.proto &
6431                 IXGBE_FTQF_PROTOCOL_MASK);
6432         ftqf |= (uint32_t)((filter->filter_info.priority &
6433                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6434         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6435                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6436         if (filter->filter_info.dst_ip_mask == 0)
6437                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6438         if (filter->filter_info.src_port_mask == 0)
6439                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6440         if (filter->filter_info.dst_port_mask == 0)
6441                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6442         if (filter->filter_info.proto_mask == 0)
6443                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6444         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6445         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6446         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6447
6448         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6449         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6450         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6451         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6452
6453         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6454         l34timir |= (uint32_t)(filter->queue <<
6455                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6456         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6457 }
6458
6459 /*
6460  * add a 5tuple filter
6461  *
6462  * @param
6463  * dev: Pointer to struct rte_eth_dev.
6464  * index: the index the filter allocates.
6465  * filter: ponter to the filter that will be added.
6466  * rx_queue: the queue id the filter assigned to.
6467  *
6468  * @return
6469  *    - On success, zero.
6470  *    - On failure, a negative value.
6471  */
6472 static int
6473 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6474                         struct ixgbe_5tuple_filter *filter)
6475 {
6476         struct ixgbe_filter_info *filter_info =
6477                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6478         int i, idx, shift;
6479
6480         /*
6481          * look for an unused 5tuple filter index,
6482          * and insert the filter to list.
6483          */
6484         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6485                 idx = i / (sizeof(uint32_t) * NBBY);
6486                 shift = i % (sizeof(uint32_t) * NBBY);
6487                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6488                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6489                         filter->index = i;
6490                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6491                                           filter,
6492                                           entries);
6493                         break;
6494                 }
6495         }
6496         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6497                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6498                 return -ENOSYS;
6499         }
6500
6501         ixgbe_inject_5tuple_filter(dev, filter);
6502
6503         return 0;
6504 }
6505
6506 /*
6507  * remove a 5tuple filter
6508  *
6509  * @param
6510  * dev: Pointer to struct rte_eth_dev.
6511  * filter: the pointer of the filter will be removed.
6512  */
6513 static void
6514 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6515                         struct ixgbe_5tuple_filter *filter)
6516 {
6517         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6518         struct ixgbe_filter_info *filter_info =
6519                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6520         uint16_t index = filter->index;
6521
6522         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6523                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6524         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6525         rte_free(filter);
6526
6527         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6528         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6529         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6530         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6531         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6532 }
6533
6534 static int
6535 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6536 {
6537         struct ixgbe_hw *hw;
6538         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6539         struct rte_eth_dev_data *dev_data = dev->data;
6540
6541         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6542
6543         if (mtu < RTE_ETHER_MIN_MTU ||
6544                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6545                 return -EINVAL;
6546
6547         /* If device is started, refuse mtu that requires the support of
6548          * scattered packets when this feature has not been enabled before.
6549          */
6550         if (dev_data->dev_started && !dev_data->scattered_rx &&
6551             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6552              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6553                 PMD_INIT_LOG(ERR, "Stop port first.");
6554                 return -EINVAL;
6555         }
6556
6557         /*
6558          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6559          * request of the version 2.0 of the mailbox API.
6560          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6561          * of the mailbox API.
6562          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6563          * prior to 3.11.33 which contains the following change:
6564          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6565          */
6566         if (ixgbevf_rlpml_set_vf(hw, max_frame))
6567                 return -EINVAL;
6568
6569         /* update max frame size */
6570         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6571         return 0;
6572 }
6573
6574 static inline struct ixgbe_5tuple_filter *
6575 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6576                         struct ixgbe_5tuple_filter_info *key)
6577 {
6578         struct ixgbe_5tuple_filter *it;
6579
6580         TAILQ_FOREACH(it, filter_list, entries) {
6581                 if (memcmp(key, &it->filter_info,
6582                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6583                         return it;
6584                 }
6585         }
6586         return NULL;
6587 }
6588
6589 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6590 static inline int
6591 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6592                         struct ixgbe_5tuple_filter_info *filter_info)
6593 {
6594         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6595                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6596                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6597                 return -EINVAL;
6598
6599         switch (filter->dst_ip_mask) {
6600         case UINT32_MAX:
6601                 filter_info->dst_ip_mask = 0;
6602                 filter_info->dst_ip = filter->dst_ip;
6603                 break;
6604         case 0:
6605                 filter_info->dst_ip_mask = 1;
6606                 break;
6607         default:
6608                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6609                 return -EINVAL;
6610         }
6611
6612         switch (filter->src_ip_mask) {
6613         case UINT32_MAX:
6614                 filter_info->src_ip_mask = 0;
6615                 filter_info->src_ip = filter->src_ip;
6616                 break;
6617         case 0:
6618                 filter_info->src_ip_mask = 1;
6619                 break;
6620         default:
6621                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6622                 return -EINVAL;
6623         }
6624
6625         switch (filter->dst_port_mask) {
6626         case UINT16_MAX:
6627                 filter_info->dst_port_mask = 0;
6628                 filter_info->dst_port = filter->dst_port;
6629                 break;
6630         case 0:
6631                 filter_info->dst_port_mask = 1;
6632                 break;
6633         default:
6634                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6635                 return -EINVAL;
6636         }
6637
6638         switch (filter->src_port_mask) {
6639         case UINT16_MAX:
6640                 filter_info->src_port_mask = 0;
6641                 filter_info->src_port = filter->src_port;
6642                 break;
6643         case 0:
6644                 filter_info->src_port_mask = 1;
6645                 break;
6646         default:
6647                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6648                 return -EINVAL;
6649         }
6650
6651         switch (filter->proto_mask) {
6652         case UINT8_MAX:
6653                 filter_info->proto_mask = 0;
6654                 filter_info->proto =
6655                         convert_protocol_type(filter->proto);
6656                 break;
6657         case 0:
6658                 filter_info->proto_mask = 1;
6659                 break;
6660         default:
6661                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6662                 return -EINVAL;
6663         }
6664
6665         filter_info->priority = (uint8_t)filter->priority;
6666         return 0;
6667 }
6668
6669 /*
6670  * add or delete a ntuple filter
6671  *
6672  * @param
6673  * dev: Pointer to struct rte_eth_dev.
6674  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6675  * add: if true, add filter, if false, remove filter
6676  *
6677  * @return
6678  *    - On success, zero.
6679  *    - On failure, a negative value.
6680  */
6681 int
6682 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6683                         struct rte_eth_ntuple_filter *ntuple_filter,
6684                         bool add)
6685 {
6686         struct ixgbe_filter_info *filter_info =
6687                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6688         struct ixgbe_5tuple_filter_info filter_5tuple;
6689         struct ixgbe_5tuple_filter *filter;
6690         int ret;
6691
6692         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6693                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6694                 return -EINVAL;
6695         }
6696
6697         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6698         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6699         if (ret < 0)
6700                 return ret;
6701
6702         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6703                                          &filter_5tuple);
6704         if (filter != NULL && add) {
6705                 PMD_DRV_LOG(ERR, "filter exists.");
6706                 return -EEXIST;
6707         }
6708         if (filter == NULL && !add) {
6709                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6710                 return -ENOENT;
6711         }
6712
6713         if (add) {
6714                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6715                                 sizeof(struct ixgbe_5tuple_filter), 0);
6716                 if (filter == NULL)
6717                         return -ENOMEM;
6718                 rte_memcpy(&filter->filter_info,
6719                                  &filter_5tuple,
6720                                  sizeof(struct ixgbe_5tuple_filter_info));
6721                 filter->queue = ntuple_filter->queue;
6722                 ret = ixgbe_add_5tuple_filter(dev, filter);
6723                 if (ret < 0) {
6724                         rte_free(filter);
6725                         return ret;
6726                 }
6727         } else
6728                 ixgbe_remove_5tuple_filter(dev, filter);
6729
6730         return 0;
6731 }
6732
6733 int
6734 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6735                         struct rte_eth_ethertype_filter *filter,
6736                         bool add)
6737 {
6738         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6739         struct ixgbe_filter_info *filter_info =
6740                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6741         uint32_t etqf = 0;
6742         uint32_t etqs = 0;
6743         int ret;
6744         struct ixgbe_ethertype_filter ethertype_filter;
6745
6746         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6747                 return -EINVAL;
6748
6749         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6750                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6751                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6752                         " ethertype filter.", filter->ether_type);
6753                 return -EINVAL;
6754         }
6755
6756         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6757                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6758                 return -EINVAL;
6759         }
6760         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6761                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6762                 return -EINVAL;
6763         }
6764
6765         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6766         if (ret >= 0 && add) {
6767                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6768                             filter->ether_type);
6769                 return -EEXIST;
6770         }
6771         if (ret < 0 && !add) {
6772                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6773                             filter->ether_type);
6774                 return -ENOENT;
6775         }
6776
6777         if (add) {
6778                 etqf = IXGBE_ETQF_FILTER_EN;
6779                 etqf |= (uint32_t)filter->ether_type;
6780                 etqs |= (uint32_t)((filter->queue <<
6781                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6782                                     IXGBE_ETQS_RX_QUEUE);
6783                 etqs |= IXGBE_ETQS_QUEUE_EN;
6784
6785                 ethertype_filter.ethertype = filter->ether_type;
6786                 ethertype_filter.etqf = etqf;
6787                 ethertype_filter.etqs = etqs;
6788                 ethertype_filter.conf = FALSE;
6789                 ret = ixgbe_ethertype_filter_insert(filter_info,
6790                                                     &ethertype_filter);
6791                 if (ret < 0) {
6792                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6793                         return -ENOSPC;
6794                 }
6795         } else {
6796                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6797                 if (ret < 0)
6798                         return -ENOSYS;
6799         }
6800         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6801         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6802         IXGBE_WRITE_FLUSH(hw);
6803
6804         return 0;
6805 }
6806
6807 static int
6808 ixgbe_dev_filter_ctrl(__rte_unused struct rte_eth_dev *dev,
6809                      enum rte_filter_type filter_type,
6810                      enum rte_filter_op filter_op,
6811                      void *arg)
6812 {
6813         int ret = 0;
6814
6815         switch (filter_type) {
6816         case RTE_ETH_FILTER_GENERIC:
6817                 if (filter_op != RTE_ETH_FILTER_GET)
6818                         return -EINVAL;
6819                 *(const void **)arg = &ixgbe_flow_ops;
6820                 break;
6821         default:
6822                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6823                                                         filter_type);
6824                 ret = -EINVAL;
6825                 break;
6826         }
6827
6828         return ret;
6829 }
6830
6831 static u8 *
6832 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6833                         u8 **mc_addr_ptr, u32 *vmdq)
6834 {
6835         u8 *mc_addr;
6836
6837         *vmdq = 0;
6838         mc_addr = *mc_addr_ptr;
6839         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6840         return mc_addr;
6841 }
6842
6843 static int
6844 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6845                           struct rte_ether_addr *mc_addr_set,
6846                           uint32_t nb_mc_addr)
6847 {
6848         struct ixgbe_hw *hw;
6849         u8 *mc_addr_list;
6850
6851         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6852         mc_addr_list = (u8 *)mc_addr_set;
6853         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6854                                          ixgbe_dev_addr_list_itr, TRUE);
6855 }
6856
6857 static uint64_t
6858 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6859 {
6860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6861         uint64_t systime_cycles;
6862
6863         switch (hw->mac.type) {
6864         case ixgbe_mac_X550:
6865         case ixgbe_mac_X550EM_x:
6866         case ixgbe_mac_X550EM_a:
6867                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6868                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6869                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6870                                 * NSEC_PER_SEC;
6871                 break;
6872         default:
6873                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6874                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6875                                 << 32;
6876         }
6877
6878         return systime_cycles;
6879 }
6880
6881 static uint64_t
6882 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6883 {
6884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6885         uint64_t rx_tstamp_cycles;
6886
6887         switch (hw->mac.type) {
6888         case ixgbe_mac_X550:
6889         case ixgbe_mac_X550EM_x:
6890         case ixgbe_mac_X550EM_a:
6891                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6892                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6893                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6894                                 * NSEC_PER_SEC;
6895                 break;
6896         default:
6897                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6898                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6899                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6900                                 << 32;
6901         }
6902
6903         return rx_tstamp_cycles;
6904 }
6905
6906 static uint64_t
6907 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6908 {
6909         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6910         uint64_t tx_tstamp_cycles;
6911
6912         switch (hw->mac.type) {
6913         case ixgbe_mac_X550:
6914         case ixgbe_mac_X550EM_x:
6915         case ixgbe_mac_X550EM_a:
6916                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6917                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6918                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6919                                 * NSEC_PER_SEC;
6920                 break;
6921         default:
6922                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6923                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6924                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6925                                 << 32;
6926         }
6927
6928         return tx_tstamp_cycles;
6929 }
6930
6931 static void
6932 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6933 {
6934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6935         struct ixgbe_adapter *adapter = dev->data->dev_private;
6936         struct rte_eth_link link;
6937         uint32_t incval = 0;
6938         uint32_t shift = 0;
6939
6940         /* Get current link speed. */
6941         ixgbe_dev_link_update(dev, 1);
6942         rte_eth_linkstatus_get(dev, &link);
6943
6944         switch (link.link_speed) {
6945         case ETH_SPEED_NUM_100M:
6946                 incval = IXGBE_INCVAL_100;
6947                 shift = IXGBE_INCVAL_SHIFT_100;
6948                 break;
6949         case ETH_SPEED_NUM_1G:
6950                 incval = IXGBE_INCVAL_1GB;
6951                 shift = IXGBE_INCVAL_SHIFT_1GB;
6952                 break;
6953         case ETH_SPEED_NUM_10G:
6954         default:
6955                 incval = IXGBE_INCVAL_10GB;
6956                 shift = IXGBE_INCVAL_SHIFT_10GB;
6957                 break;
6958         }
6959
6960         switch (hw->mac.type) {
6961         case ixgbe_mac_X550:
6962         case ixgbe_mac_X550EM_x:
6963         case ixgbe_mac_X550EM_a:
6964                 /* Independent of link speed. */
6965                 incval = 1;
6966                 /* Cycles read will be interpreted as ns. */
6967                 shift = 0;
6968                 /* Fall-through */
6969         case ixgbe_mac_X540:
6970                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6971                 break;
6972         case ixgbe_mac_82599EB:
6973                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6974                 shift -= IXGBE_INCVAL_SHIFT_82599;
6975                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6976                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6977                 break;
6978         default:
6979                 /* Not supported. */
6980                 return;
6981         }
6982
6983         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6984         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6985         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6986
6987         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6988         adapter->systime_tc.cc_shift = shift;
6989         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6990
6991         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6992         adapter->rx_tstamp_tc.cc_shift = shift;
6993         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6994
6995         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6996         adapter->tx_tstamp_tc.cc_shift = shift;
6997         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6998 }
6999
7000 static int
7001 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7002 {
7003         struct ixgbe_adapter *adapter = dev->data->dev_private;
7004
7005         adapter->systime_tc.nsec += delta;
7006         adapter->rx_tstamp_tc.nsec += delta;
7007         adapter->tx_tstamp_tc.nsec += delta;
7008
7009         return 0;
7010 }
7011
7012 static int
7013 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7014 {
7015         uint64_t ns;
7016         struct ixgbe_adapter *adapter = dev->data->dev_private;
7017
7018         ns = rte_timespec_to_ns(ts);
7019         /* Set the timecounters to a new value. */
7020         adapter->systime_tc.nsec = ns;
7021         adapter->rx_tstamp_tc.nsec = ns;
7022         adapter->tx_tstamp_tc.nsec = ns;
7023
7024         return 0;
7025 }
7026
7027 static int
7028 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7029 {
7030         uint64_t ns, systime_cycles;
7031         struct ixgbe_adapter *adapter = dev->data->dev_private;
7032
7033         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7034         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7035         *ts = rte_ns_to_timespec(ns);
7036
7037         return 0;
7038 }
7039
7040 static int
7041 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7042 {
7043         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7044         uint32_t tsync_ctl;
7045         uint32_t tsauxc;
7046
7047         /* Stop the timesync system time. */
7048         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7049         /* Reset the timesync system time value. */
7050         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7051         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7052
7053         /* Enable system time for platforms where it isn't on by default. */
7054         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7055         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7056         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7057
7058         ixgbe_start_timecounters(dev);
7059
7060         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7061         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7062                         (RTE_ETHER_TYPE_1588 |
7063                          IXGBE_ETQF_FILTER_EN |
7064                          IXGBE_ETQF_1588));
7065
7066         /* Enable timestamping of received PTP packets. */
7067         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7068         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7069         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7070
7071         /* Enable timestamping of transmitted PTP packets. */
7072         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7073         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7074         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7075
7076         IXGBE_WRITE_FLUSH(hw);
7077
7078         return 0;
7079 }
7080
7081 static int
7082 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7083 {
7084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7085         uint32_t tsync_ctl;
7086
7087         /* Disable timestamping of transmitted PTP packets. */
7088         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7089         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7090         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7091
7092         /* Disable timestamping of received PTP packets. */
7093         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7094         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7095         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7096
7097         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7098         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7099
7100         /* Stop incrementating the System Time registers. */
7101         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7102
7103         return 0;
7104 }
7105
7106 static int
7107 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7108                                  struct timespec *timestamp,
7109                                  uint32_t flags __rte_unused)
7110 {
7111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7112         struct ixgbe_adapter *adapter = dev->data->dev_private;
7113         uint32_t tsync_rxctl;
7114         uint64_t rx_tstamp_cycles;
7115         uint64_t ns;
7116
7117         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7118         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7119                 return -EINVAL;
7120
7121         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7122         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7123         *timestamp = rte_ns_to_timespec(ns);
7124
7125         return  0;
7126 }
7127
7128 static int
7129 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7130                                  struct timespec *timestamp)
7131 {
7132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7133         struct ixgbe_adapter *adapter = dev->data->dev_private;
7134         uint32_t tsync_txctl;
7135         uint64_t tx_tstamp_cycles;
7136         uint64_t ns;
7137
7138         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7139         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7140                 return -EINVAL;
7141
7142         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7143         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7144         *timestamp = rte_ns_to_timespec(ns);
7145
7146         return 0;
7147 }
7148
7149 static int
7150 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7151 {
7152         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7153         int count = 0;
7154         int g_ind = 0;
7155         const struct reg_info *reg_group;
7156         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7157                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7158
7159         while ((reg_group = reg_set[g_ind++]))
7160                 count += ixgbe_regs_group_count(reg_group);
7161
7162         return count;
7163 }
7164
7165 static int
7166 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7167 {
7168         int count = 0;
7169         int g_ind = 0;
7170         const struct reg_info *reg_group;
7171
7172         while ((reg_group = ixgbevf_regs[g_ind++]))
7173                 count += ixgbe_regs_group_count(reg_group);
7174
7175         return count;
7176 }
7177
7178 static int
7179 ixgbe_get_regs(struct rte_eth_dev *dev,
7180               struct rte_dev_reg_info *regs)
7181 {
7182         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7183         uint32_t *data = regs->data;
7184         int g_ind = 0;
7185         int count = 0;
7186         const struct reg_info *reg_group;
7187         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7188                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7189
7190         if (data == NULL) {
7191                 regs->length = ixgbe_get_reg_length(dev);
7192                 regs->width = sizeof(uint32_t);
7193                 return 0;
7194         }
7195
7196         /* Support only full register dump */
7197         if ((regs->length == 0) ||
7198             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7199                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7200                         hw->device_id;
7201                 while ((reg_group = reg_set[g_ind++]))
7202                         count += ixgbe_read_regs_group(dev, &data[count],
7203                                 reg_group);
7204                 return 0;
7205         }
7206
7207         return -ENOTSUP;
7208 }
7209
7210 static int
7211 ixgbevf_get_regs(struct rte_eth_dev *dev,
7212                 struct rte_dev_reg_info *regs)
7213 {
7214         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7215         uint32_t *data = regs->data;
7216         int g_ind = 0;
7217         int count = 0;
7218         const struct reg_info *reg_group;
7219
7220         if (data == NULL) {
7221                 regs->length = ixgbevf_get_reg_length(dev);
7222                 regs->width = sizeof(uint32_t);
7223                 return 0;
7224         }
7225
7226         /* Support only full register dump */
7227         if ((regs->length == 0) ||
7228             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7229                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7230                         hw->device_id;
7231                 while ((reg_group = ixgbevf_regs[g_ind++]))
7232                         count += ixgbe_read_regs_group(dev, &data[count],
7233                                                       reg_group);
7234                 return 0;
7235         }
7236
7237         return -ENOTSUP;
7238 }
7239
7240 static int
7241 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7242 {
7243         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7244
7245         /* Return unit is byte count */
7246         return hw->eeprom.word_size * 2;
7247 }
7248
7249 static int
7250 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7251                 struct rte_dev_eeprom_info *in_eeprom)
7252 {
7253         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7254         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7255         uint16_t *data = in_eeprom->data;
7256         int first, length;
7257
7258         first = in_eeprom->offset >> 1;
7259         length = in_eeprom->length >> 1;
7260         if ((first > hw->eeprom.word_size) ||
7261             ((first + length) > hw->eeprom.word_size))
7262                 return -EINVAL;
7263
7264         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7265
7266         return eeprom->ops.read_buffer(hw, first, length, data);
7267 }
7268
7269 static int
7270 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7271                 struct rte_dev_eeprom_info *in_eeprom)
7272 {
7273         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7274         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7275         uint16_t *data = in_eeprom->data;
7276         int first, length;
7277
7278         first = in_eeprom->offset >> 1;
7279         length = in_eeprom->length >> 1;
7280         if ((first > hw->eeprom.word_size) ||
7281             ((first + length) > hw->eeprom.word_size))
7282                 return -EINVAL;
7283
7284         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7285
7286         return eeprom->ops.write_buffer(hw,  first, length, data);
7287 }
7288
7289 static int
7290 ixgbe_get_module_info(struct rte_eth_dev *dev,
7291                       struct rte_eth_dev_module_info *modinfo)
7292 {
7293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7294         uint32_t status;
7295         uint8_t sff8472_rev, addr_mode;
7296         bool page_swap = false;
7297
7298         /* Check whether we support SFF-8472 or not */
7299         status = hw->phy.ops.read_i2c_eeprom(hw,
7300                                              IXGBE_SFF_SFF_8472_COMP,
7301                                              &sff8472_rev);
7302         if (status != 0)
7303                 return -EIO;
7304
7305         /* addressing mode is not supported */
7306         status = hw->phy.ops.read_i2c_eeprom(hw,
7307                                              IXGBE_SFF_SFF_8472_SWAP,
7308                                              &addr_mode);
7309         if (status != 0)
7310                 return -EIO;
7311
7312         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7313                 PMD_DRV_LOG(ERR,
7314                             "Address change required to access page 0xA2, "
7315                             "but not supported. Please report the module "
7316                             "type to the driver maintainers.");
7317                 page_swap = true;
7318         }
7319
7320         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7321                 /* We have a SFP, but it does not support SFF-8472 */
7322                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7323                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7324         } else {
7325                 /* We have a SFP which supports a revision of SFF-8472. */
7326                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7327                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7328         }
7329
7330         return 0;
7331 }
7332
7333 static int
7334 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7335                         struct rte_dev_eeprom_info *info)
7336 {
7337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7338         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7339         uint8_t databyte = 0xFF;
7340         uint8_t *data = info->data;
7341         uint32_t i = 0;
7342
7343         if (info->length == 0)
7344                 return -EINVAL;
7345
7346         for (i = info->offset; i < info->offset + info->length; i++) {
7347                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7348                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7349                 else
7350                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7351
7352                 if (status != 0)
7353                         return -EIO;
7354
7355                 data[i - info->offset] = databyte;
7356         }
7357
7358         return 0;
7359 }
7360
7361 uint16_t
7362 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7363         switch (mac_type) {
7364         case ixgbe_mac_X550:
7365         case ixgbe_mac_X550EM_x:
7366         case ixgbe_mac_X550EM_a:
7367                 return ETH_RSS_RETA_SIZE_512;
7368         case ixgbe_mac_X550_vf:
7369         case ixgbe_mac_X550EM_x_vf:
7370         case ixgbe_mac_X550EM_a_vf:
7371                 return ETH_RSS_RETA_SIZE_64;
7372         case ixgbe_mac_X540_vf:
7373         case ixgbe_mac_82599_vf:
7374                 return 0;
7375         default:
7376                 return ETH_RSS_RETA_SIZE_128;
7377         }
7378 }
7379
7380 uint32_t
7381 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7382         switch (mac_type) {
7383         case ixgbe_mac_X550:
7384         case ixgbe_mac_X550EM_x:
7385         case ixgbe_mac_X550EM_a:
7386                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7387                         return IXGBE_RETA(reta_idx >> 2);
7388                 else
7389                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7390         case ixgbe_mac_X550_vf:
7391         case ixgbe_mac_X550EM_x_vf:
7392         case ixgbe_mac_X550EM_a_vf:
7393                 return IXGBE_VFRETA(reta_idx >> 2);
7394         default:
7395                 return IXGBE_RETA(reta_idx >> 2);
7396         }
7397 }
7398
7399 uint32_t
7400 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7401         switch (mac_type) {
7402         case ixgbe_mac_X550_vf:
7403         case ixgbe_mac_X550EM_x_vf:
7404         case ixgbe_mac_X550EM_a_vf:
7405                 return IXGBE_VFMRQC;
7406         default:
7407                 return IXGBE_MRQC;
7408         }
7409 }
7410
7411 uint32_t
7412 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7413         switch (mac_type) {
7414         case ixgbe_mac_X550_vf:
7415         case ixgbe_mac_X550EM_x_vf:
7416         case ixgbe_mac_X550EM_a_vf:
7417                 return IXGBE_VFRSSRK(i);
7418         default:
7419                 return IXGBE_RSSRK(i);
7420         }
7421 }
7422
7423 bool
7424 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7425         switch (mac_type) {
7426         case ixgbe_mac_82599_vf:
7427         case ixgbe_mac_X540_vf:
7428                 return 0;
7429         default:
7430                 return 1;
7431         }
7432 }
7433
7434 static int
7435 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7436                         struct rte_eth_dcb_info *dcb_info)
7437 {
7438         struct ixgbe_dcb_config *dcb_config =
7439                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7440         struct ixgbe_dcb_tc_config *tc;
7441         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7442         uint8_t nb_tcs;
7443         uint8_t i, j;
7444
7445         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7446                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7447         else
7448                 dcb_info->nb_tcs = 1;
7449
7450         tc_queue = &dcb_info->tc_queue;
7451         nb_tcs = dcb_info->nb_tcs;
7452
7453         if (dcb_config->vt_mode) { /* vt is enabled*/
7454                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7455                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7456                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7457                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7458                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7459                         for (j = 0; j < nb_tcs; j++) {
7460                                 tc_queue->tc_rxq[0][j].base = j;
7461                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7462                                 tc_queue->tc_txq[0][j].base = j;
7463                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7464                         }
7465                 } else {
7466                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7467                                 for (j = 0; j < nb_tcs; j++) {
7468                                         tc_queue->tc_rxq[i][j].base =
7469                                                 i * nb_tcs + j;
7470                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7471                                         tc_queue->tc_txq[i][j].base =
7472                                                 i * nb_tcs + j;
7473                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7474                                 }
7475                         }
7476                 }
7477         } else { /* vt is disabled*/
7478                 struct rte_eth_dcb_rx_conf *rx_conf =
7479                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7480                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7481                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7482                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7483                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7484                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7485                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7486                         }
7487                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7488                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7489                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7490                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7491                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7492                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7493                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7494                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7495                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7496                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7497                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7498                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7499                         }
7500                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7501                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7502                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7503                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7504                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7505                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7506                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7507                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7508                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7509                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7510                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7511                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7512                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7513                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7514                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7515                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7516                 }
7517         }
7518         for (i = 0; i < dcb_info->nb_tcs; i++) {
7519                 tc = &dcb_config->tc_config[i];
7520                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7521         }
7522         return 0;
7523 }
7524
7525 /* Update e-tag ether type */
7526 static int
7527 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7528                             uint16_t ether_type)
7529 {
7530         uint32_t etag_etype;
7531
7532         if (hw->mac.type != ixgbe_mac_X550 &&
7533             hw->mac.type != ixgbe_mac_X550EM_x &&
7534             hw->mac.type != ixgbe_mac_X550EM_a) {
7535                 return -ENOTSUP;
7536         }
7537
7538         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7539         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7540         etag_etype |= ether_type;
7541         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7542         IXGBE_WRITE_FLUSH(hw);
7543
7544         return 0;
7545 }
7546
7547 /* Enable e-tag tunnel */
7548 static int
7549 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7550 {
7551         uint32_t etag_etype;
7552
7553         if (hw->mac.type != ixgbe_mac_X550 &&
7554             hw->mac.type != ixgbe_mac_X550EM_x &&
7555             hw->mac.type != ixgbe_mac_X550EM_a) {
7556                 return -ENOTSUP;
7557         }
7558
7559         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7560         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7561         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7562         IXGBE_WRITE_FLUSH(hw);
7563
7564         return 0;
7565 }
7566
7567 static int
7568 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7569                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7570 {
7571         int ret = 0;
7572         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7573         uint32_t i, rar_entries;
7574         uint32_t rar_low, rar_high;
7575
7576         if (hw->mac.type != ixgbe_mac_X550 &&
7577             hw->mac.type != ixgbe_mac_X550EM_x &&
7578             hw->mac.type != ixgbe_mac_X550EM_a) {
7579                 return -ENOTSUP;
7580         }
7581
7582         rar_entries = ixgbe_get_num_rx_addrs(hw);
7583
7584         for (i = 1; i < rar_entries; i++) {
7585                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7586                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7587                 if ((rar_high & IXGBE_RAH_AV) &&
7588                     (rar_high & IXGBE_RAH_ADTYPE) &&
7589                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7590                      l2_tunnel->tunnel_id)) {
7591                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7592                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7593
7594                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7595
7596                         return ret;
7597                 }
7598         }
7599
7600         return ret;
7601 }
7602
7603 static int
7604 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7605                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7606 {
7607         int ret = 0;
7608         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7609         uint32_t i, rar_entries;
7610         uint32_t rar_low, rar_high;
7611
7612         if (hw->mac.type != ixgbe_mac_X550 &&
7613             hw->mac.type != ixgbe_mac_X550EM_x &&
7614             hw->mac.type != ixgbe_mac_X550EM_a) {
7615                 return -ENOTSUP;
7616         }
7617
7618         /* One entry for one tunnel. Try to remove potential existing entry. */
7619         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7620
7621         rar_entries = ixgbe_get_num_rx_addrs(hw);
7622
7623         for (i = 1; i < rar_entries; i++) {
7624                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7625                 if (rar_high & IXGBE_RAH_AV) {
7626                         continue;
7627                 } else {
7628                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7629                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7630                         rar_low = l2_tunnel->tunnel_id;
7631
7632                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7633                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7634
7635                         return ret;
7636                 }
7637         }
7638
7639         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7640                      " Please remove a rule before adding a new one.");
7641         return -EINVAL;
7642 }
7643
7644 static inline struct ixgbe_l2_tn_filter *
7645 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7646                           struct ixgbe_l2_tn_key *key)
7647 {
7648         int ret;
7649
7650         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7651         if (ret < 0)
7652                 return NULL;
7653
7654         return l2_tn_info->hash_map[ret];
7655 }
7656
7657 static inline int
7658 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7659                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7660 {
7661         int ret;
7662
7663         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7664                                &l2_tn_filter->key);
7665
7666         if (ret < 0) {
7667                 PMD_DRV_LOG(ERR,
7668                             "Failed to insert L2 tunnel filter"
7669                             " to hash table %d!",
7670                             ret);
7671                 return ret;
7672         }
7673
7674         l2_tn_info->hash_map[ret] = l2_tn_filter;
7675
7676         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7677
7678         return 0;
7679 }
7680
7681 static inline int
7682 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7683                           struct ixgbe_l2_tn_key *key)
7684 {
7685         int ret;
7686         struct ixgbe_l2_tn_filter *l2_tn_filter;
7687
7688         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7689
7690         if (ret < 0) {
7691                 PMD_DRV_LOG(ERR,
7692                             "No such L2 tunnel filter to delete %d!",
7693                             ret);
7694                 return ret;
7695         }
7696
7697         l2_tn_filter = l2_tn_info->hash_map[ret];
7698         l2_tn_info->hash_map[ret] = NULL;
7699
7700         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7701         rte_free(l2_tn_filter);
7702
7703         return 0;
7704 }
7705
7706 /* Add l2 tunnel filter */
7707 int
7708 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7709                                struct ixgbe_l2_tunnel_conf *l2_tunnel,
7710                                bool restore)
7711 {
7712         int ret;
7713         struct ixgbe_l2_tn_info *l2_tn_info =
7714                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7715         struct ixgbe_l2_tn_key key;
7716         struct ixgbe_l2_tn_filter *node;
7717
7718         if (!restore) {
7719                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7720                 key.tn_id = l2_tunnel->tunnel_id;
7721
7722                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7723
7724                 if (node) {
7725                         PMD_DRV_LOG(ERR,
7726                                     "The L2 tunnel filter already exists!");
7727                         return -EINVAL;
7728                 }
7729
7730                 node = rte_zmalloc("ixgbe_l2_tn",
7731                                    sizeof(struct ixgbe_l2_tn_filter),
7732                                    0);
7733                 if (!node)
7734                         return -ENOMEM;
7735
7736                 rte_memcpy(&node->key,
7737                                  &key,
7738                                  sizeof(struct ixgbe_l2_tn_key));
7739                 node->pool = l2_tunnel->pool;
7740                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7741                 if (ret < 0) {
7742                         rte_free(node);
7743                         return ret;
7744                 }
7745         }
7746
7747         switch (l2_tunnel->l2_tunnel_type) {
7748         case RTE_L2_TUNNEL_TYPE_E_TAG:
7749                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7750                 break;
7751         default:
7752                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7753                 ret = -EINVAL;
7754                 break;
7755         }
7756
7757         if ((!restore) && (ret < 0))
7758                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7759
7760         return ret;
7761 }
7762
7763 /* Delete l2 tunnel filter */
7764 int
7765 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7766                                struct ixgbe_l2_tunnel_conf *l2_tunnel)
7767 {
7768         int ret;
7769         struct ixgbe_l2_tn_info *l2_tn_info =
7770                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7771         struct ixgbe_l2_tn_key key;
7772
7773         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7774         key.tn_id = l2_tunnel->tunnel_id;
7775         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7776         if (ret < 0)
7777                 return ret;
7778
7779         switch (l2_tunnel->l2_tunnel_type) {
7780         case RTE_L2_TUNNEL_TYPE_E_TAG:
7781                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7782                 break;
7783         default:
7784                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7785                 ret = -EINVAL;
7786                 break;
7787         }
7788
7789         return ret;
7790 }
7791
7792 static int
7793 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7794 {
7795         int ret = 0;
7796         uint32_t ctrl;
7797         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7798
7799         if (hw->mac.type != ixgbe_mac_X550 &&
7800             hw->mac.type != ixgbe_mac_X550EM_x &&
7801             hw->mac.type != ixgbe_mac_X550EM_a) {
7802                 return -ENOTSUP;
7803         }
7804
7805         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7806         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7807         if (en)
7808                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7809         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7810
7811         return ret;
7812 }
7813
7814 static int
7815 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7816                         uint16_t port)
7817 {
7818         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7819         IXGBE_WRITE_FLUSH(hw);
7820
7821         return 0;
7822 }
7823
7824 /* There's only one register for VxLAN UDP port.
7825  * So, we cannot add several ports. Will update it.
7826  */
7827 static int
7828 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7829                      uint16_t port)
7830 {
7831         if (port == 0) {
7832                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7833                 return -EINVAL;
7834         }
7835
7836         return ixgbe_update_vxlan_port(hw, port);
7837 }
7838
7839 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7840  * UDP port, it must have a value.
7841  * So, will reset it to the original value 0.
7842  */
7843 static int
7844 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7845                      uint16_t port)
7846 {
7847         uint16_t cur_port;
7848
7849         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7850
7851         if (cur_port != port) {
7852                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7853                 return -EINVAL;
7854         }
7855
7856         return ixgbe_update_vxlan_port(hw, 0);
7857 }
7858
7859 /* Add UDP tunneling port */
7860 static int
7861 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7862                               struct rte_eth_udp_tunnel *udp_tunnel)
7863 {
7864         int ret = 0;
7865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7866
7867         if (hw->mac.type != ixgbe_mac_X550 &&
7868             hw->mac.type != ixgbe_mac_X550EM_x &&
7869             hw->mac.type != ixgbe_mac_X550EM_a) {
7870                 return -ENOTSUP;
7871         }
7872
7873         if (udp_tunnel == NULL)
7874                 return -EINVAL;
7875
7876         switch (udp_tunnel->prot_type) {
7877         case RTE_TUNNEL_TYPE_VXLAN:
7878                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7879                 break;
7880
7881         case RTE_TUNNEL_TYPE_GENEVE:
7882         case RTE_TUNNEL_TYPE_TEREDO:
7883                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7884                 ret = -EINVAL;
7885                 break;
7886
7887         default:
7888                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7889                 ret = -EINVAL;
7890                 break;
7891         }
7892
7893         return ret;
7894 }
7895
7896 /* Remove UDP tunneling port */
7897 static int
7898 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7899                               struct rte_eth_udp_tunnel *udp_tunnel)
7900 {
7901         int ret = 0;
7902         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7903
7904         if (hw->mac.type != ixgbe_mac_X550 &&
7905             hw->mac.type != ixgbe_mac_X550EM_x &&
7906             hw->mac.type != ixgbe_mac_X550EM_a) {
7907                 return -ENOTSUP;
7908         }
7909
7910         if (udp_tunnel == NULL)
7911                 return -EINVAL;
7912
7913         switch (udp_tunnel->prot_type) {
7914         case RTE_TUNNEL_TYPE_VXLAN:
7915                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7916                 break;
7917         case RTE_TUNNEL_TYPE_GENEVE:
7918         case RTE_TUNNEL_TYPE_TEREDO:
7919                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7920                 ret = -EINVAL;
7921                 break;
7922         default:
7923                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7924                 ret = -EINVAL;
7925                 break;
7926         }
7927
7928         return ret;
7929 }
7930
7931 static int
7932 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
7933 {
7934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7935         int ret;
7936
7937         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
7938         case IXGBE_SUCCESS:
7939                 ret = 0;
7940                 break;
7941         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7942                 ret = -ENOTSUP;
7943                 break;
7944         default:
7945                 ret = -EAGAIN;
7946                 break;
7947         }
7948
7949         return ret;
7950 }
7951
7952 static int
7953 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
7954 {
7955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7956         int ret;
7957
7958         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
7959         case IXGBE_SUCCESS:
7960                 ret = 0;
7961                 break;
7962         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7963                 ret = -ENOTSUP;
7964                 break;
7965         default:
7966                 ret = -EAGAIN;
7967                 break;
7968         }
7969
7970         return ret;
7971 }
7972
7973 static int
7974 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7975 {
7976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7977         int ret;
7978         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
7979
7980         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
7981         case IXGBE_SUCCESS:
7982                 ret = 0;
7983                 break;
7984         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7985                 ret = -ENOTSUP;
7986                 break;
7987         default:
7988                 ret = -EAGAIN;
7989                 break;
7990         }
7991
7992         return ret;
7993 }
7994
7995 static int
7996 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7997 {
7998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7999         int ret;
8000
8001         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8002         case IXGBE_SUCCESS:
8003                 ret = 0;
8004                 break;
8005         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8006                 ret = -ENOTSUP;
8007                 break;
8008         default:
8009                 ret = -EAGAIN;
8010                 break;
8011         }
8012
8013         return ret;
8014 }
8015
8016 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8017 {
8018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8019         u32 in_msg = 0;
8020
8021         /* peek the message first */
8022         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8023
8024         /* PF reset VF event */
8025         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8026                 /* dummy mbx read to ack pf */
8027                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8028                         return;
8029                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8030                                              NULL);
8031         }
8032 }
8033
8034 static int
8035 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8036 {
8037         uint32_t eicr;
8038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8039         struct ixgbe_interrupt *intr =
8040                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8041         ixgbevf_intr_disable(dev);
8042
8043         /* read-on-clear nic registers here */
8044         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8045         intr->flags = 0;
8046
8047         /* only one misc vector supported - mailbox */
8048         eicr &= IXGBE_VTEICR_MASK;
8049         if (eicr == IXGBE_MISC_VEC_ID)
8050                 intr->flags |= IXGBE_FLAG_MAILBOX;
8051
8052         return 0;
8053 }
8054
8055 static int
8056 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8057 {
8058         struct ixgbe_interrupt *intr =
8059                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8060
8061         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8062                 ixgbevf_mbx_process(dev);
8063                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8064         }
8065
8066         ixgbevf_intr_enable(dev);
8067
8068         return 0;
8069 }
8070
8071 static void
8072 ixgbevf_dev_interrupt_handler(void *param)
8073 {
8074         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8075
8076         ixgbevf_dev_interrupt_get_status(dev);
8077         ixgbevf_dev_interrupt_action(dev);
8078 }
8079
8080 /**
8081  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8082  *  @hw: pointer to hardware structure
8083  *
8084  *  Stops the transmit data path and waits for the HW to internally empty
8085  *  the Tx security block
8086  **/
8087 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8088 {
8089 #define IXGBE_MAX_SECTX_POLL 40
8090
8091         int i;
8092         int sectxreg;
8093
8094         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8095         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8096         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8097         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8098                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8099                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8100                         break;
8101                 /* Use interrupt-safe sleep just in case */
8102                 usec_delay(1000);
8103         }
8104
8105         /* For informational purposes only */
8106         if (i >= IXGBE_MAX_SECTX_POLL)
8107                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8108                          "path fully disabled.  Continuing with init.");
8109
8110         return IXGBE_SUCCESS;
8111 }
8112
8113 /**
8114  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8115  *  @hw: pointer to hardware structure
8116  *
8117  *  Enables the transmit data path.
8118  **/
8119 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8120 {
8121         uint32_t sectxreg;
8122
8123         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8124         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8125         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8126         IXGBE_WRITE_FLUSH(hw);
8127
8128         return IXGBE_SUCCESS;
8129 }
8130
8131 /* restore n-tuple filter */
8132 static inline void
8133 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8134 {
8135         struct ixgbe_filter_info *filter_info =
8136                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8137         struct ixgbe_5tuple_filter *node;
8138
8139         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8140                 ixgbe_inject_5tuple_filter(dev, node);
8141         }
8142 }
8143
8144 /* restore ethernet type filter */
8145 static inline void
8146 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8147 {
8148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8149         struct ixgbe_filter_info *filter_info =
8150                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8151         int i;
8152
8153         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8154                 if (filter_info->ethertype_mask & (1 << i)) {
8155                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8156                                         filter_info->ethertype_filters[i].etqf);
8157                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8158                                         filter_info->ethertype_filters[i].etqs);
8159                         IXGBE_WRITE_FLUSH(hw);
8160                 }
8161         }
8162 }
8163
8164 /* restore SYN filter */
8165 static inline void
8166 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8167 {
8168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8169         struct ixgbe_filter_info *filter_info =
8170                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8171         uint32_t synqf;
8172
8173         synqf = filter_info->syn_info;
8174
8175         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8176                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8177                 IXGBE_WRITE_FLUSH(hw);
8178         }
8179 }
8180
8181 /* restore L2 tunnel filter */
8182 static inline void
8183 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8184 {
8185         struct ixgbe_l2_tn_info *l2_tn_info =
8186                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8187         struct ixgbe_l2_tn_filter *node;
8188         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8189
8190         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8191                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8192                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8193                 l2_tn_conf.pool           = node->pool;
8194                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8195         }
8196 }
8197
8198 /* restore rss filter */
8199 static inline void
8200 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8201 {
8202         struct ixgbe_filter_info *filter_info =
8203                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8204
8205         if (filter_info->rss_info.conf.queue_num)
8206                 ixgbe_config_rss_filter(dev,
8207                         &filter_info->rss_info, TRUE);
8208 }
8209
8210 static int
8211 ixgbe_filter_restore(struct rte_eth_dev *dev)
8212 {
8213         ixgbe_ntuple_filter_restore(dev);
8214         ixgbe_ethertype_filter_restore(dev);
8215         ixgbe_syn_filter_restore(dev);
8216         ixgbe_fdir_filter_restore(dev);
8217         ixgbe_l2_tn_filter_restore(dev);
8218         ixgbe_rss_filter_restore(dev);
8219
8220         return 0;
8221 }
8222
8223 static void
8224 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8225 {
8226         struct ixgbe_l2_tn_info *l2_tn_info =
8227                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8228         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8229
8230         if (l2_tn_info->e_tag_en)
8231                 (void)ixgbe_e_tag_enable(hw);
8232
8233         if (l2_tn_info->e_tag_fwd_en)
8234                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8235
8236         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8237 }
8238
8239 /* remove all the n-tuple filters */
8240 void
8241 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8242 {
8243         struct ixgbe_filter_info *filter_info =
8244                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8245         struct ixgbe_5tuple_filter *p_5tuple;
8246
8247         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8248                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8249 }
8250
8251 /* remove all the ether type filters */
8252 void
8253 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8254 {
8255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8256         struct ixgbe_filter_info *filter_info =
8257                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8258         int i;
8259
8260         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8261                 if (filter_info->ethertype_mask & (1 << i) &&
8262                     !filter_info->ethertype_filters[i].conf) {
8263                         (void)ixgbe_ethertype_filter_remove(filter_info,
8264                                                             (uint8_t)i);
8265                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8266                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8267                         IXGBE_WRITE_FLUSH(hw);
8268                 }
8269         }
8270 }
8271
8272 /* remove the SYN filter */
8273 void
8274 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8275 {
8276         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8277         struct ixgbe_filter_info *filter_info =
8278                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8279
8280         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8281                 filter_info->syn_info = 0;
8282
8283                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8284                 IXGBE_WRITE_FLUSH(hw);
8285         }
8286 }
8287
8288 /* remove all the L2 tunnel filters */
8289 int
8290 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8291 {
8292         struct ixgbe_l2_tn_info *l2_tn_info =
8293                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8294         struct ixgbe_l2_tn_filter *l2_tn_filter;
8295         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8296         int ret = 0;
8297
8298         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8299                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8300                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8301                 l2_tn_conf.pool           = l2_tn_filter->pool;
8302                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8303                 if (ret < 0)
8304                         return ret;
8305         }
8306
8307         return 0;
8308 }
8309
8310 void
8311 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8312                                 struct ixgbe_macsec_setting *macsec_setting)
8313 {
8314         struct ixgbe_macsec_setting *macsec =
8315                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8316
8317         macsec->offload_en = macsec_setting->offload_en;
8318         macsec->encrypt_en = macsec_setting->encrypt_en;
8319         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8320 }
8321
8322 void
8323 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8324 {
8325         struct ixgbe_macsec_setting *macsec =
8326                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8327
8328         macsec->offload_en = 0;
8329         macsec->encrypt_en = 0;
8330         macsec->replayprotect_en = 0;
8331 }
8332
8333 void
8334 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8335                                 struct ixgbe_macsec_setting *macsec_setting)
8336 {
8337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8338         uint32_t ctrl;
8339         uint8_t en = macsec_setting->encrypt_en;
8340         uint8_t rp = macsec_setting->replayprotect_en;
8341
8342         /**
8343          * Workaround:
8344          * As no ixgbe_disable_sec_rx_path equivalent is
8345          * implemented for tx in the base code, and we are
8346          * not allowed to modify the base code in DPDK, so
8347          * just call the hand-written one directly for now.
8348          * The hardware support has been checked by
8349          * ixgbe_disable_sec_rx_path().
8350          */
8351         ixgbe_disable_sec_tx_path_generic(hw);
8352
8353         /* Enable Ethernet CRC (required by MACsec offload) */
8354         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8355         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8356         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8357
8358         /* Enable the TX and RX crypto engines */
8359         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8360         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8361         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8362
8363         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8364         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8365         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8366
8367         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8368         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8369         ctrl |= 0x3;
8370         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8371
8372         /* Enable SA lookup */
8373         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8374         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8375         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8376                      IXGBE_LSECTXCTRL_AUTH;
8377         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8378         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8379         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8380         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8381
8382         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8383         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8384         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8385         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8386         if (rp)
8387                 ctrl |= IXGBE_LSECRXCTRL_RP;
8388         else
8389                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8390         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8391
8392         /* Start the data paths */
8393         ixgbe_enable_sec_rx_path(hw);
8394         /**
8395          * Workaround:
8396          * As no ixgbe_enable_sec_rx_path equivalent is
8397          * implemented for tx in the base code, and we are
8398          * not allowed to modify the base code in DPDK, so
8399          * just call the hand-written one directly for now.
8400          */
8401         ixgbe_enable_sec_tx_path_generic(hw);
8402 }
8403
8404 void
8405 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8406 {
8407         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8408         uint32_t ctrl;
8409
8410         /**
8411          * Workaround:
8412          * As no ixgbe_disable_sec_rx_path equivalent is
8413          * implemented for tx in the base code, and we are
8414          * not allowed to modify the base code in DPDK, so
8415          * just call the hand-written one directly for now.
8416          * The hardware support has been checked by
8417          * ixgbe_disable_sec_rx_path().
8418          */
8419         ixgbe_disable_sec_tx_path_generic(hw);
8420
8421         /* Disable the TX and RX crypto engines */
8422         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8423         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8424         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8425
8426         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8427         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8428         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8429
8430         /* Disable SA lookup */
8431         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8432         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8433         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8434         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8435
8436         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8437         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8438         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8439         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8440
8441         /* Start the data paths */
8442         ixgbe_enable_sec_rx_path(hw);
8443         /**
8444          * Workaround:
8445          * As no ixgbe_enable_sec_rx_path equivalent is
8446          * implemented for tx in the base code, and we are
8447          * not allowed to modify the base code in DPDK, so
8448          * just call the hand-written one directly for now.
8449          */
8450         ixgbe_enable_sec_tx_path_generic(hw);
8451 }
8452
8453 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8454 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8455 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8456 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8457 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8458 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8459 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8460                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8461
8462 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
8463 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
8464
8465 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
8466 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
8467 #endif
8468 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
8469 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
8470 #endif
8471 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
8472 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
8473 #endif