1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_kvargs.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_hash_crc.h>
36 #ifdef RTE_LIB_SECURITY
37 #include <rte_security_driver.h>
40 #include "ixgbe_logs.h"
41 #include "base/ixgbe_api.h"
42 #include "base/ixgbe_vf.h"
43 #include "base/ixgbe_common.h"
44 #include "ixgbe_ethdev.h"
45 #include "ixgbe_bypass.h"
46 #include "ixgbe_rxtx.h"
47 #include "base/ixgbe_type.h"
48 #include "base/ixgbe_phy.h"
49 #include "ixgbe_regs.h"
52 * High threshold controlling when to start sending XOFF frames. Must be at
53 * least 8 bytes less than receive packet buffer size. This value is in units
56 #define IXGBE_FC_HI 0x80
59 * Low threshold controlling when to start sending XON frames. This value is
60 * in units of 1024 bytes.
62 #define IXGBE_FC_LO 0x40
64 /* Timer value included in XOFF frames. */
65 #define IXGBE_FC_PAUSE 0x680
67 /*Default value of Max Rx Queue*/
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
74 #define IXGBE_MMW_SIZE_DEFAULT 0x4
75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
79 * Default values for RX/TX configuration
81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
82 #define IXGBE_DEFAULT_RX_PTHRESH 8
83 #define IXGBE_DEFAULT_RX_HTHRESH 8
84 #define IXGBE_DEFAULT_RX_WTHRESH 0
86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
87 #define IXGBE_DEFAULT_TX_PTHRESH 32
88 #define IXGBE_DEFAULT_TX_HTHRESH 0
89 #define IXGBE_DEFAULT_TX_WTHRESH 0
90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
95 #define IXGBE_8_BIT_WIDTH CHAR_BIT
96 #define IXGBE_8_BIT_MASK UINT8_MAX
98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
102 /* Additional timesync values. */
103 #define NSEC_PER_SEC 1000000000L
104 #define IXGBE_INCVAL_10GB 0x66666666
105 #define IXGBE_INCVAL_1GB 0x40000000
106 #define IXGBE_INCVAL_100 0x50000000
107 #define IXGBE_INCVAL_SHIFT_10GB 28
108 #define IXGBE_INCVAL_SHIFT_1GB 24
109 #define IXGBE_INCVAL_SHIFT_100 21
110 #define IXGBE_INCVAL_SHIFT_82599 7
111 #define IXGBE_INCPER_SHIFT_82599 24
113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
117 #define IXGBE_ETAG_ETYPE 0x00005084
118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
120 #define IXGBE_RAH_ADTYPE 0x40000000
121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
125 #define IXGBE_QDE_STRIP_TAG 0x00000004
126 #define IXGBE_VTEICR_MASK 0x07
128 #define IXGBE_EXVET_VET_EXT_SHIFT 16
129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk"
133 static const char * const ixgbevf_valid_arguments[] = {
134 IXGBEVF_DEVARG_PFLINK_FULLCHK,
138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
157 int wait_to_complete);
158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
166 uint64_t *values, unsigned int n);
167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names, unsigned limit);
174 static int ixgbe_dev_xstats_get_names_by_id(
175 struct rte_eth_dev *dev,
176 struct rte_eth_xstat_name *xstats_names,
179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_fc_conf *fc_conf);
216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
217 struct rte_eth_pfc_conf *pfc_conf);
218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
222 struct rte_eth_rss_reta_entry64 *reta_conf,
224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
230 static void ixgbe_dev_interrupt_handler(void *param);
231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
234 uint32_t timeout_ms);
236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
237 struct rte_ether_addr *mac_addr,
238 uint32_t index, uint32_t pool);
239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
241 struct rte_ether_addr *mac_addr);
242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
243 static bool is_device_supported(struct rte_eth_dev *dev,
244 struct rte_pci_driver *drv);
246 /* For Virtual Function support */
247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
250 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
252 int wait_to_complete);
253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
255 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
262 uint16_t vlan_id, int on);
263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
264 uint16_t queue, int on);
265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
273 uint8_t queue, uint8_t msix_vector);
274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
280 /* For Eth VMDQ APIs support */
281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
282 rte_ether_addr * mac_addr, uint8_t on);
283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
285 struct rte_eth_mirror_conf *mirror_conf,
286 uint8_t rule_id, uint8_t on);
287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
294 uint8_t queue, uint8_t msix_vector);
295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
298 struct rte_ether_addr *mac_addr,
299 uint32_t index, uint32_t pool);
300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
302 struct rte_ether_addr *mac_addr);
303 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
304 struct ixgbe_5tuple_filter *filter);
305 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
306 struct ixgbe_5tuple_filter *filter);
307 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
308 enum rte_filter_op filter_op,
310 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
311 struct rte_eth_ntuple_filter *filter);
312 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
313 enum rte_filter_type filter_type,
314 enum rte_filter_op filter_op,
316 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
318 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
319 struct rte_ether_addr *mc_addr_set,
320 uint32_t nb_mc_addr);
321 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
322 struct rte_eth_dcb_info *dcb_info);
324 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
325 static int ixgbe_get_regs(struct rte_eth_dev *dev,
326 struct rte_dev_reg_info *regs);
327 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
328 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
329 struct rte_dev_eeprom_info *eeprom);
330 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
331 struct rte_dev_eeprom_info *eeprom);
333 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
334 struct rte_eth_dev_module_info *modinfo);
335 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
336 struct rte_dev_eeprom_info *info);
338 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
339 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
340 struct rte_dev_reg_info *regs);
342 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
343 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
344 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
345 struct timespec *timestamp,
347 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
348 struct timespec *timestamp);
349 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
350 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
351 struct timespec *timestamp);
352 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
353 const struct timespec *timestamp);
354 static void ixgbevf_dev_interrupt_handler(void *param);
356 static int ixgbe_dev_l2_tunnel_eth_type_conf
357 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
358 static int ixgbe_dev_l2_tunnel_offload_set
359 (struct rte_eth_dev *dev,
360 struct rte_eth_l2_tunnel_conf *l2_tunnel,
363 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
364 enum rte_filter_op filter_op,
367 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
368 struct rte_eth_udp_tunnel *udp_tunnel);
369 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
370 struct rte_eth_udp_tunnel *udp_tunnel);
371 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
372 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
373 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
376 * Define VF Stats MACRO for Non "cleared on read" register
378 #define UPDATE_VF_STAT(reg, last, cur) \
380 uint32_t latest = IXGBE_READ_REG(hw, reg); \
381 cur += (latest - last) & UINT_MAX; \
385 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
387 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
388 u64 new_msb = IXGBE_READ_REG(hw, msb); \
389 u64 latest = ((new_msb << 32) | new_lsb); \
390 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
394 #define IXGBE_SET_HWSTRIP(h, q) do {\
395 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
396 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
397 (h)->bitmap[idx] |= 1 << bit;\
400 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
401 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
402 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
403 (h)->bitmap[idx] &= ~(1 << bit);\
406 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
407 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
408 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
409 (r) = (h)->bitmap[idx] >> bit & 1;\
413 * The set of PCI devices this driver supports
415 static const struct rte_pci_id pci_id_ixgbe_map[] = {
416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
464 #ifdef RTE_LIBRTE_IXGBE_BYPASS
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
467 { .vendor_id = 0, /* sentinel */ },
471 * The set of PCI devices this driver supports (for 82599 VF)
473 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
484 { .vendor_id = 0, /* sentinel */ },
487 static const struct rte_eth_desc_lim rx_desc_lim = {
488 .nb_max = IXGBE_MAX_RING_DESC,
489 .nb_min = IXGBE_MIN_RING_DESC,
490 .nb_align = IXGBE_RXD_ALIGN,
493 static const struct rte_eth_desc_lim tx_desc_lim = {
494 .nb_max = IXGBE_MAX_RING_DESC,
495 .nb_min = IXGBE_MIN_RING_DESC,
496 .nb_align = IXGBE_TXD_ALIGN,
497 .nb_seg_max = IXGBE_TX_MAX_SEG,
498 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
501 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
502 .dev_configure = ixgbe_dev_configure,
503 .dev_start = ixgbe_dev_start,
504 .dev_stop = ixgbe_dev_stop,
505 .dev_set_link_up = ixgbe_dev_set_link_up,
506 .dev_set_link_down = ixgbe_dev_set_link_down,
507 .dev_close = ixgbe_dev_close,
508 .dev_reset = ixgbe_dev_reset,
509 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
510 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
511 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
512 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
513 .link_update = ixgbe_dev_link_update,
514 .stats_get = ixgbe_dev_stats_get,
515 .xstats_get = ixgbe_dev_xstats_get,
516 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
517 .stats_reset = ixgbe_dev_stats_reset,
518 .xstats_reset = ixgbe_dev_xstats_reset,
519 .xstats_get_names = ixgbe_dev_xstats_get_names,
520 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
521 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
522 .fw_version_get = ixgbe_fw_version_get,
523 .dev_infos_get = ixgbe_dev_info_get,
524 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
525 .mtu_set = ixgbe_dev_mtu_set,
526 .vlan_filter_set = ixgbe_vlan_filter_set,
527 .vlan_tpid_set = ixgbe_vlan_tpid_set,
528 .vlan_offload_set = ixgbe_vlan_offload_set,
529 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
530 .rx_queue_start = ixgbe_dev_rx_queue_start,
531 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
532 .tx_queue_start = ixgbe_dev_tx_queue_start,
533 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
534 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
535 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
536 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
537 .rx_queue_release = ixgbe_dev_rx_queue_release,
538 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
539 .tx_queue_release = ixgbe_dev_tx_queue_release,
540 .dev_led_on = ixgbe_dev_led_on,
541 .dev_led_off = ixgbe_dev_led_off,
542 .flow_ctrl_get = ixgbe_flow_ctrl_get,
543 .flow_ctrl_set = ixgbe_flow_ctrl_set,
544 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
545 .mac_addr_add = ixgbe_add_rar,
546 .mac_addr_remove = ixgbe_remove_rar,
547 .mac_addr_set = ixgbe_set_default_mac_addr,
548 .uc_hash_table_set = ixgbe_uc_hash_table_set,
549 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
550 .mirror_rule_set = ixgbe_mirror_rule_set,
551 .mirror_rule_reset = ixgbe_mirror_rule_reset,
552 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
553 .reta_update = ixgbe_dev_rss_reta_update,
554 .reta_query = ixgbe_dev_rss_reta_query,
555 .rss_hash_update = ixgbe_dev_rss_hash_update,
556 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
557 .filter_ctrl = ixgbe_dev_filter_ctrl,
558 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
559 .rxq_info_get = ixgbe_rxq_info_get,
560 .txq_info_get = ixgbe_txq_info_get,
561 .timesync_enable = ixgbe_timesync_enable,
562 .timesync_disable = ixgbe_timesync_disable,
563 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
564 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
565 .get_reg = ixgbe_get_regs,
566 .get_eeprom_length = ixgbe_get_eeprom_length,
567 .get_eeprom = ixgbe_get_eeprom,
568 .set_eeprom = ixgbe_set_eeprom,
569 .get_module_info = ixgbe_get_module_info,
570 .get_module_eeprom = ixgbe_get_module_eeprom,
571 .get_dcb_info = ixgbe_dev_get_dcb_info,
572 .timesync_adjust_time = ixgbe_timesync_adjust_time,
573 .timesync_read_time = ixgbe_timesync_read_time,
574 .timesync_write_time = ixgbe_timesync_write_time,
575 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
576 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
577 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
578 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
579 .tm_ops_get = ixgbe_tm_ops_get,
580 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
584 * dev_ops for virtual function, bare necessities for basic vf
585 * operation have been implemented
587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
588 .dev_configure = ixgbevf_dev_configure,
589 .dev_start = ixgbevf_dev_start,
590 .dev_stop = ixgbevf_dev_stop,
591 .link_update = ixgbevf_dev_link_update,
592 .stats_get = ixgbevf_dev_stats_get,
593 .xstats_get = ixgbevf_dev_xstats_get,
594 .stats_reset = ixgbevf_dev_stats_reset,
595 .xstats_reset = ixgbevf_dev_stats_reset,
596 .xstats_get_names = ixgbevf_dev_xstats_get_names,
597 .dev_close = ixgbevf_dev_close,
598 .dev_reset = ixgbevf_dev_reset,
599 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
600 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
601 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
602 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
603 .dev_infos_get = ixgbevf_dev_info_get,
604 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
605 .mtu_set = ixgbevf_dev_set_mtu,
606 .vlan_filter_set = ixgbevf_vlan_filter_set,
607 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
608 .vlan_offload_set = ixgbevf_vlan_offload_set,
609 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
610 .rx_queue_release = ixgbe_dev_rx_queue_release,
611 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
612 .tx_queue_release = ixgbe_dev_tx_queue_release,
613 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
614 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
615 .mac_addr_add = ixgbevf_add_mac_addr,
616 .mac_addr_remove = ixgbevf_remove_mac_addr,
617 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
618 .rxq_info_get = ixgbe_rxq_info_get,
619 .txq_info_get = ixgbe_txq_info_get,
620 .mac_addr_set = ixgbevf_set_default_mac_addr,
621 .get_reg = ixgbevf_get_regs,
622 .reta_update = ixgbe_dev_rss_reta_update,
623 .reta_query = ixgbe_dev_rss_reta_query,
624 .rss_hash_update = ixgbe_dev_rss_hash_update,
625 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
626 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
629 /* store statistics names and its offset in stats structure */
630 struct rte_ixgbe_xstats_name_off {
631 char name[RTE_ETH_XSTATS_NAME_SIZE];
635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
636 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
637 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
638 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
639 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
640 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
641 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
642 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
643 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
644 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
645 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
646 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
647 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
648 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
649 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
650 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
652 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
654 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
655 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
656 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
657 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
658 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
659 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
660 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
661 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
662 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
663 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
664 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
665 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
666 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
667 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
668 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
669 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
670 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
672 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
674 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
675 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
676 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
677 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
679 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
681 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
683 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
685 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
687 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
689 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
692 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
693 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
694 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
696 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
697 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
698 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
699 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
700 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
702 {"rx_fcoe_no_direct_data_placement_ext_buff",
703 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
705 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
707 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
709 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
711 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
713 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
717 sizeof(rte_ixgbe_stats_strings[0]))
719 /* MACsec statistics */
720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
721 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
723 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
724 out_pkts_encrypted)},
725 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
726 out_pkts_protected)},
727 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
728 out_octets_encrypted)},
729 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
730 out_octets_protected)},
731 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
733 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
735 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
737 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
738 in_pkts_unknownsci)},
739 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
740 in_octets_decrypted)},
741 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
742 in_octets_validated)},
743 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
745 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
747 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
749 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
751 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
753 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
755 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
757 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
758 in_pkts_notusingsa)},
761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
762 sizeof(rte_ixgbe_macsec_strings[0]))
764 /* Per-queue statistics */
765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
766 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
767 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
768 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
769 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
773 sizeof(rte_ixgbe_rxq_strings[0]))
774 #define IXGBE_NB_RXQ_PRIO_VALUES 8
776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
777 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
778 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
779 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
784 sizeof(rte_ixgbe_txq_strings[0]))
785 #define IXGBE_NB_TXQ_PRIO_VALUES 8
787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
788 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
792 sizeof(rte_ixgbevf_stats_strings[0]))
795 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
798 ixgbe_is_sfp(struct ixgbe_hw *hw)
800 switch (hw->phy.type) {
801 case ixgbe_phy_sfp_avago:
802 case ixgbe_phy_sfp_ftl:
803 case ixgbe_phy_sfp_intel:
804 case ixgbe_phy_sfp_unknown:
805 case ixgbe_phy_sfp_passive_tyco:
806 case ixgbe_phy_sfp_passive_unknown:
813 static inline int32_t
814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
819 status = ixgbe_reset_hw(hw);
821 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
822 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
823 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
824 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
825 IXGBE_WRITE_FLUSH(hw);
827 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
828 status = IXGBE_SUCCESS;
833 ixgbe_enable_intr(struct rte_eth_dev *dev)
835 struct ixgbe_interrupt *intr =
836 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
837 struct ixgbe_hw *hw =
838 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
840 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
841 IXGBE_WRITE_FLUSH(hw);
845 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
848 ixgbe_disable_intr(struct ixgbe_hw *hw)
850 PMD_INIT_FUNC_TRACE();
852 if (hw->mac.type == ixgbe_mac_82598EB) {
853 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
855 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
856 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
857 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
859 IXGBE_WRITE_FLUSH(hw);
863 * This function resets queue statistics mapping registers.
864 * From Niantic datasheet, Initialization of Statistics section:
865 * "...if software requires the queue counters, the RQSMR and TQSM registers
866 * must be re-programmed following a device reset.
869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
873 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
874 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
875 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
887 #define NB_QMAP_FIELDS_PER_QSM_REG 4
888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
890 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
891 struct ixgbe_stat_mapping_registers *stat_mappings =
892 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
893 uint32_t qsmr_mask = 0;
894 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
898 if ((hw->mac.type != ixgbe_mac_82599EB) &&
899 (hw->mac.type != ixgbe_mac_X540) &&
900 (hw->mac.type != ixgbe_mac_X550) &&
901 (hw->mac.type != ixgbe_mac_X550EM_x) &&
902 (hw->mac.type != ixgbe_mac_X550EM_a))
905 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
906 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
909 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
910 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
911 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
914 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
916 /* Now clear any previous stat_idx set */
917 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
919 stat_mappings->tqsm[n] &= ~clearing_mask;
921 stat_mappings->rqsmr[n] &= ~clearing_mask;
923 q_map = (uint32_t)stat_idx;
924 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
925 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
927 stat_mappings->tqsm[n] |= qsmr_mask;
929 stat_mappings->rqsmr[n] |= qsmr_mask;
931 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
932 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
934 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
935 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
937 /* Now write the mapping in the appropriate register */
939 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
940 stat_mappings->rqsmr[n], n);
941 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
943 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
944 stat_mappings->tqsm[n], n);
945 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
953 struct ixgbe_stat_mapping_registers *stat_mappings =
954 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
955 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
958 /* write whatever was in stat mapping table to the NIC */
959 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
961 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
964 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
972 struct ixgbe_dcb_tc_config *tc;
973 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
975 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
976 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
977 for (i = 0; i < dcb_max_tc; i++) {
978 tc = &dcb_config->tc_config[i];
979 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
980 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
981 (uint8_t)(100/dcb_max_tc + (i & 1));
982 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
983 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
984 (uint8_t)(100/dcb_max_tc + (i & 1));
985 tc->pfc = ixgbe_dcb_pfc_disabled;
988 /* Initialize default user to priority mapping, UPx->TC0 */
989 tc = &dcb_config->tc_config[0];
990 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
991 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
992 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
993 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
994 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
996 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
997 dcb_config->pfc_mode_enable = false;
998 dcb_config->vt_mode = true;
999 dcb_config->round_robin_enable = false;
1000 /* support all DCB capabilities in 82599 */
1001 dcb_config->support.capabilities = 0xFF;
1003 /*we only support 4 Tcs for X540, X550 */
1004 if (hw->mac.type == ixgbe_mac_X540 ||
1005 hw->mac.type == ixgbe_mac_X550 ||
1006 hw->mac.type == ixgbe_mac_X550EM_x ||
1007 hw->mac.type == ixgbe_mac_X550EM_a) {
1008 dcb_config->num_tcs.pg_tcs = 4;
1009 dcb_config->num_tcs.pfc_tcs = 4;
1014 * Ensure that all locks are released before first NVM or PHY access
1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1022 * Phy lock should not fail in this early stage. If this is the case,
1023 * it is due to an improper exit of the application.
1024 * So force the release of the faulty lock. Release of common lock
1025 * is done automatically by swfw_sync function.
1027 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1028 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1029 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1031 ixgbe_release_swfw_semaphore(hw, mask);
1034 * These ones are more tricky since they are common to all ports; but
1035 * swfw_sync retries last long enough (1s) to be almost sure that if
1036 * lock can not be taken it is due to an improper lock of the
1039 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1040 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1041 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1043 ixgbe_release_swfw_semaphore(hw, mask);
1047 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1048 * It returns 0 on success.
1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1053 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1054 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1055 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1056 struct ixgbe_hw *hw =
1057 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1058 struct ixgbe_vfta *shadow_vfta =
1059 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1060 struct ixgbe_hwstrip *hwstrip =
1061 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1062 struct ixgbe_dcb_config *dcb_config =
1063 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1064 struct ixgbe_filter_info *filter_info =
1065 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1066 struct ixgbe_bw_conf *bw_conf =
1067 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1072 PMD_INIT_FUNC_TRACE();
1074 ixgbe_dev_macsec_setting_reset(eth_dev);
1076 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1077 eth_dev->rx_queue_count = ixgbe_dev_rx_queue_count;
1078 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done;
1079 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1080 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1081 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1082 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1083 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1086 * For secondary processes, we don't initialise any further as primary
1087 * has already done this work. Only check we don't need a different
1088 * RX and TX function.
1090 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1091 struct ixgbe_tx_queue *txq;
1092 /* TX queue function in primary, set by last queue initialized
1093 * Tx queue may not initialized by primary process
1095 if (eth_dev->data->tx_queues) {
1096 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1097 ixgbe_set_tx_function(eth_dev, txq);
1099 /* Use default TX function if we get here */
1100 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1101 "Using default TX function.");
1104 ixgbe_set_rx_function(eth_dev);
1109 rte_atomic32_clear(&ad->link_thread_running);
1110 rte_eth_copy_pci_info(eth_dev, pci_dev);
1111 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1113 /* Vendor and Device ID need to be set before init of shared code */
1114 hw->device_id = pci_dev->id.device_id;
1115 hw->vendor_id = pci_dev->id.vendor_id;
1116 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1117 hw->allow_unsupported_sfp = 1;
1119 /* Initialize the shared code (base driver) */
1120 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1121 diag = ixgbe_bypass_init_shared_code(hw);
1123 diag = ixgbe_init_shared_code(hw);
1124 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1126 if (diag != IXGBE_SUCCESS) {
1127 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1131 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1132 PMD_INIT_LOG(ERR, "\nERROR: "
1133 "Firmware recovery mode detected. Limiting functionality.\n"
1134 "Refer to the Intel(R) Ethernet Adapters and Devices "
1135 "User Guide for details on firmware recovery mode.");
1139 /* pick up the PCI bus settings for reporting later */
1140 ixgbe_get_bus_info(hw);
1142 /* Unlock any pending hardware semaphore */
1143 ixgbe_swfw_lock_reset(hw);
1145 #ifdef RTE_LIB_SECURITY
1146 /* Initialize security_ctx only for primary process*/
1147 if (ixgbe_ipsec_ctx_create(eth_dev))
1151 /* Initialize DCB configuration*/
1152 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1153 ixgbe_dcb_init(hw, dcb_config);
1154 /* Get Hardware Flow Control setting */
1155 hw->fc.requested_mode = ixgbe_fc_none;
1156 hw->fc.current_mode = ixgbe_fc_none;
1157 hw->fc.pause_time = IXGBE_FC_PAUSE;
1158 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1159 hw->fc.low_water[i] = IXGBE_FC_LO;
1160 hw->fc.high_water[i] = IXGBE_FC_HI;
1162 hw->fc.send_xon = 1;
1164 /* Make sure we have a good EEPROM before we read from it */
1165 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1166 if (diag != IXGBE_SUCCESS) {
1167 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1171 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1172 diag = ixgbe_bypass_init_hw(hw);
1174 diag = ixgbe_init_hw(hw);
1175 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1178 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1179 * is called too soon after the kernel driver unbinding/binding occurs.
1180 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1181 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1182 * also called. See ixgbe_identify_phy_82599(). The reason for the
1183 * failure is not known, and only occuts when virtualisation features
1184 * are disabled in the bios. A delay of 100ms was found to be enough by
1185 * trial-and-error, and is doubled to be safe.
1187 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1189 diag = ixgbe_init_hw(hw);
1192 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1193 diag = IXGBE_SUCCESS;
1195 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1196 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1197 "LOM. Please be aware there may be issues associated "
1198 "with your hardware.");
1199 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1200 "please contact your Intel or hardware representative "
1201 "who provided you with this hardware.");
1202 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1203 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1205 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1209 /* Reset the hw statistics */
1210 ixgbe_dev_stats_reset(eth_dev);
1212 /* disable interrupt */
1213 ixgbe_disable_intr(hw);
1215 /* reset mappings for queue statistics hw counters*/
1216 ixgbe_reset_qstat_mappings(hw);
1218 /* Allocate memory for storing MAC addresses */
1219 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1220 hw->mac.num_rar_entries, 0);
1221 if (eth_dev->data->mac_addrs == NULL) {
1223 "Failed to allocate %u bytes needed to store "
1225 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1228 /* Copy the permanent MAC address */
1229 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1230 ð_dev->data->mac_addrs[0]);
1232 /* Allocate memory for storing hash filter MAC addresses */
1233 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1234 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1235 if (eth_dev->data->hash_mac_addrs == NULL) {
1237 "Failed to allocate %d bytes needed to store MAC addresses",
1238 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1242 /* initialize the vfta */
1243 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1245 /* initialize the hw strip bitmap*/
1246 memset(hwstrip, 0, sizeof(*hwstrip));
1248 /* initialize PF if max_vfs not zero */
1249 ret = ixgbe_pf_host_init(eth_dev);
1251 rte_free(eth_dev->data->mac_addrs);
1252 eth_dev->data->mac_addrs = NULL;
1253 rte_free(eth_dev->data->hash_mac_addrs);
1254 eth_dev->data->hash_mac_addrs = NULL;
1258 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1259 /* let hardware know driver is loaded */
1260 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1261 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1262 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1263 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1264 IXGBE_WRITE_FLUSH(hw);
1266 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1267 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1268 (int) hw->mac.type, (int) hw->phy.type,
1269 (int) hw->phy.sfp_type);
1271 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1272 (int) hw->mac.type, (int) hw->phy.type);
1274 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1275 eth_dev->data->port_id, pci_dev->id.vendor_id,
1276 pci_dev->id.device_id);
1278 rte_intr_callback_register(intr_handle,
1279 ixgbe_dev_interrupt_handler, eth_dev);
1281 /* enable uio/vfio intr/eventfd mapping */
1282 rte_intr_enable(intr_handle);
1284 /* enable support intr */
1285 ixgbe_enable_intr(eth_dev);
1287 /* initialize filter info */
1288 memset(filter_info, 0,
1289 sizeof(struct ixgbe_filter_info));
1291 /* initialize 5tuple filter list */
1292 TAILQ_INIT(&filter_info->fivetuple_list);
1294 /* initialize flow director filter list & hash */
1295 ixgbe_fdir_filter_init(eth_dev);
1297 /* initialize l2 tunnel filter list & hash */
1298 ixgbe_l2_tn_filter_init(eth_dev);
1300 /* initialize flow filter lists */
1301 ixgbe_filterlist_init();
1303 /* initialize bandwidth configuration info */
1304 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1306 /* initialize Traffic Manager configuration */
1307 ixgbe_tm_conf_init(eth_dev);
1313 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1315 PMD_INIT_FUNC_TRACE();
1317 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1320 ixgbe_dev_close(eth_dev);
1325 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1327 struct ixgbe_filter_info *filter_info =
1328 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1329 struct ixgbe_5tuple_filter *p_5tuple;
1331 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1332 TAILQ_REMOVE(&filter_info->fivetuple_list,
1337 memset(filter_info->fivetuple_mask, 0,
1338 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1343 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1345 struct ixgbe_hw_fdir_info *fdir_info =
1346 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1347 struct ixgbe_fdir_filter *fdir_filter;
1349 if (fdir_info->hash_map)
1350 rte_free(fdir_info->hash_map);
1351 if (fdir_info->hash_handle)
1352 rte_hash_free(fdir_info->hash_handle);
1354 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1355 TAILQ_REMOVE(&fdir_info->fdir_list,
1358 rte_free(fdir_filter);
1364 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1366 struct ixgbe_l2_tn_info *l2_tn_info =
1367 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1368 struct ixgbe_l2_tn_filter *l2_tn_filter;
1370 if (l2_tn_info->hash_map)
1371 rte_free(l2_tn_info->hash_map);
1372 if (l2_tn_info->hash_handle)
1373 rte_hash_free(l2_tn_info->hash_handle);
1375 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1376 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1379 rte_free(l2_tn_filter);
1385 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1387 struct ixgbe_hw_fdir_info *fdir_info =
1388 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1389 char fdir_hash_name[RTE_HASH_NAMESIZE];
1390 struct rte_hash_parameters fdir_hash_params = {
1391 .name = fdir_hash_name,
1392 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1393 .key_len = sizeof(union ixgbe_atr_input),
1394 .hash_func = rte_hash_crc,
1395 .hash_func_init_val = 0,
1396 .socket_id = rte_socket_id(),
1399 TAILQ_INIT(&fdir_info->fdir_list);
1400 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1401 "fdir_%s", eth_dev->device->name);
1402 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1403 if (!fdir_info->hash_handle) {
1404 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1407 fdir_info->hash_map = rte_zmalloc("ixgbe",
1408 sizeof(struct ixgbe_fdir_filter *) *
1409 IXGBE_MAX_FDIR_FILTER_NUM,
1411 if (!fdir_info->hash_map) {
1413 "Failed to allocate memory for fdir hash map!");
1416 fdir_info->mask_added = FALSE;
1421 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1423 struct ixgbe_l2_tn_info *l2_tn_info =
1424 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1425 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1426 struct rte_hash_parameters l2_tn_hash_params = {
1427 .name = l2_tn_hash_name,
1428 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1429 .key_len = sizeof(struct ixgbe_l2_tn_key),
1430 .hash_func = rte_hash_crc,
1431 .hash_func_init_val = 0,
1432 .socket_id = rte_socket_id(),
1435 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1436 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1437 "l2_tn_%s", eth_dev->device->name);
1438 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1439 if (!l2_tn_info->hash_handle) {
1440 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1443 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1444 sizeof(struct ixgbe_l2_tn_filter *) *
1445 IXGBE_MAX_L2_TN_FILTER_NUM,
1447 if (!l2_tn_info->hash_map) {
1449 "Failed to allocate memory for L2 TN hash map!");
1452 l2_tn_info->e_tag_en = FALSE;
1453 l2_tn_info->e_tag_fwd_en = FALSE;
1454 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1459 * Negotiate mailbox API version with the PF.
1460 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1461 * Then we try to negotiate starting with the most recent one.
1462 * If all negotiation attempts fail, then we will proceed with
1463 * the default one (ixgbe_mbox_api_10).
1466 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1470 /* start with highest supported, proceed down */
1471 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1479 i != RTE_DIM(sup_ver) &&
1480 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1486 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1490 /* Set Organizationally Unique Identifier (OUI) prefix. */
1491 mac_addr->addr_bytes[0] = 0x00;
1492 mac_addr->addr_bytes[1] = 0x09;
1493 mac_addr->addr_bytes[2] = 0xC0;
1494 /* Force indication of locally assigned MAC address. */
1495 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1496 /* Generate the last 3 bytes of the MAC address with a random number. */
1497 random = rte_rand();
1498 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1502 devarg_handle_int(__rte_unused const char *key, const char *value,
1505 uint16_t *n = extra_args;
1507 if (value == NULL || extra_args == NULL)
1510 *n = (uint16_t)strtoul(value, NULL, 0);
1511 if (*n == USHRT_MAX && errno == ERANGE)
1518 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1519 struct rte_devargs *devargs)
1521 struct rte_kvargs *kvlist;
1522 uint16_t pflink_fullchk;
1524 if (devargs == NULL)
1527 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1531 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1532 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1533 devarg_handle_int, &pflink_fullchk) == 0 &&
1534 pflink_fullchk == 1)
1535 adapter->pflink_fullchk = 1;
1537 rte_kvargs_free(kvlist);
1541 * Virtual Function device init
1544 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1548 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1549 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1550 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1551 struct ixgbe_hw *hw =
1552 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1553 struct ixgbe_vfta *shadow_vfta =
1554 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1555 struct ixgbe_hwstrip *hwstrip =
1556 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1557 struct rte_ether_addr *perm_addr =
1558 (struct rte_ether_addr *)hw->mac.perm_addr;
1560 PMD_INIT_FUNC_TRACE();
1562 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1563 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done;
1564 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1565 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1566 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1567 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1569 /* for secondary processes, we don't initialise any further as primary
1570 * has already done this work. Only check we don't need a different
1573 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1574 struct ixgbe_tx_queue *txq;
1575 /* TX queue function in primary, set by last queue initialized
1576 * Tx queue may not initialized by primary process
1578 if (eth_dev->data->tx_queues) {
1579 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1580 ixgbe_set_tx_function(eth_dev, txq);
1582 /* Use default TX function if we get here */
1583 PMD_INIT_LOG(NOTICE,
1584 "No TX queues configured yet. Using default TX function.");
1587 ixgbe_set_rx_function(eth_dev);
1592 rte_atomic32_clear(&ad->link_thread_running);
1593 ixgbevf_parse_devargs(eth_dev->data->dev_private,
1594 pci_dev->device.devargs);
1596 rte_eth_copy_pci_info(eth_dev, pci_dev);
1597 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1599 hw->device_id = pci_dev->id.device_id;
1600 hw->vendor_id = pci_dev->id.vendor_id;
1601 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1603 /* initialize the vfta */
1604 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1606 /* initialize the hw strip bitmap*/
1607 memset(hwstrip, 0, sizeof(*hwstrip));
1609 /* Initialize the shared code (base driver) */
1610 diag = ixgbe_init_shared_code(hw);
1611 if (diag != IXGBE_SUCCESS) {
1612 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1616 /* init_mailbox_params */
1617 hw->mbx.ops.init_params(hw);
1619 /* Reset the hw statistics */
1620 ixgbevf_dev_stats_reset(eth_dev);
1622 /* Disable the interrupts for VF */
1623 ixgbevf_intr_disable(eth_dev);
1625 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1626 diag = hw->mac.ops.reset_hw(hw);
1629 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1630 * the underlying PF driver has not assigned a MAC address to the VF.
1631 * In this case, assign a random MAC address.
1633 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1634 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1636 * This error code will be propagated to the app by
1637 * rte_eth_dev_reset, so use a public error code rather than
1638 * the internal-only IXGBE_ERR_RESET_FAILED
1643 /* negotiate mailbox API version to use with the PF. */
1644 ixgbevf_negotiate_api(hw);
1646 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1647 ixgbevf_get_queues(hw, &tcs, &tc);
1649 /* Allocate memory for storing MAC addresses */
1650 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1651 hw->mac.num_rar_entries, 0);
1652 if (eth_dev->data->mac_addrs == NULL) {
1654 "Failed to allocate %u bytes needed to store "
1656 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1660 /* Generate a random MAC address, if none was assigned by PF. */
1661 if (rte_is_zero_ether_addr(perm_addr)) {
1662 generate_random_mac_addr(perm_addr);
1663 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1665 rte_free(eth_dev->data->mac_addrs);
1666 eth_dev->data->mac_addrs = NULL;
1669 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1670 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1671 "%02x:%02x:%02x:%02x:%02x:%02x",
1672 perm_addr->addr_bytes[0],
1673 perm_addr->addr_bytes[1],
1674 perm_addr->addr_bytes[2],
1675 perm_addr->addr_bytes[3],
1676 perm_addr->addr_bytes[4],
1677 perm_addr->addr_bytes[5]);
1680 /* Copy the permanent MAC address */
1681 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1683 /* reset the hardware with the new settings */
1684 diag = hw->mac.ops.start_hw(hw);
1690 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1694 rte_intr_callback_register(intr_handle,
1695 ixgbevf_dev_interrupt_handler, eth_dev);
1696 rte_intr_enable(intr_handle);
1697 ixgbevf_intr_enable(eth_dev);
1699 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1700 eth_dev->data->port_id, pci_dev->id.vendor_id,
1701 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1706 /* Virtual Function device uninit */
1709 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1711 PMD_INIT_FUNC_TRACE();
1713 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1716 ixgbevf_dev_close(eth_dev);
1722 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1723 struct rte_pci_device *pci_dev)
1725 char name[RTE_ETH_NAME_MAX_LEN];
1726 struct rte_eth_dev *pf_ethdev;
1727 struct rte_eth_devargs eth_da;
1730 if (pci_dev->device.devargs) {
1731 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1736 memset(ð_da, 0, sizeof(eth_da));
1738 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1739 sizeof(struct ixgbe_adapter),
1740 eth_dev_pci_specific_init, pci_dev,
1741 eth_ixgbe_dev_init, NULL);
1743 if (retval || eth_da.nb_representor_ports < 1)
1746 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1747 if (pf_ethdev == NULL)
1750 /* probe VF representor ports */
1751 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1752 struct ixgbe_vf_info *vfinfo;
1753 struct ixgbe_vf_representor representor;
1755 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1756 pf_ethdev->data->dev_private);
1757 if (vfinfo == NULL) {
1759 "no virtual functions supported by PF");
1763 representor.vf_id = eth_da.representor_ports[i];
1764 representor.switch_domain_id = vfinfo->switch_domain_id;
1765 representor.pf_ethdev = pf_ethdev;
1767 /* representor port net_bdf_port */
1768 snprintf(name, sizeof(name), "net_%s_representor_%d",
1769 pci_dev->device.name,
1770 eth_da.representor_ports[i]);
1772 retval = rte_eth_dev_create(&pci_dev->device, name,
1773 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1774 ixgbe_vf_representor_init, &representor);
1777 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1778 "representor %s.", name);
1784 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1786 struct rte_eth_dev *ethdev;
1788 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1792 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1793 return rte_eth_dev_pci_generic_remove(pci_dev,
1794 ixgbe_vf_representor_uninit);
1796 return rte_eth_dev_pci_generic_remove(pci_dev,
1797 eth_ixgbe_dev_uninit);
1800 static struct rte_pci_driver rte_ixgbe_pmd = {
1801 .id_table = pci_id_ixgbe_map,
1802 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1803 .probe = eth_ixgbe_pci_probe,
1804 .remove = eth_ixgbe_pci_remove,
1807 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1808 struct rte_pci_device *pci_dev)
1810 return rte_eth_dev_pci_generic_probe(pci_dev,
1811 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1814 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1816 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1820 * virtual function driver struct
1822 static struct rte_pci_driver rte_ixgbevf_pmd = {
1823 .id_table = pci_id_ixgbevf_map,
1824 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1825 .probe = eth_ixgbevf_pci_probe,
1826 .remove = eth_ixgbevf_pci_remove,
1830 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1832 struct ixgbe_hw *hw =
1833 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1834 struct ixgbe_vfta *shadow_vfta =
1835 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1840 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1841 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1842 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1847 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1849 /* update local VFTA copy */
1850 shadow_vfta->vfta[vid_idx] = vfta;
1856 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1859 ixgbe_vlan_hw_strip_enable(dev, queue);
1861 ixgbe_vlan_hw_strip_disable(dev, queue);
1865 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1866 enum rte_vlan_type vlan_type,
1869 struct ixgbe_hw *hw =
1870 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1875 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1876 qinq &= IXGBE_DMATXCTL_GDV;
1878 switch (vlan_type) {
1879 case ETH_VLAN_TYPE_INNER:
1881 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1882 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1883 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1884 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1885 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1886 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1887 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1890 PMD_DRV_LOG(ERR, "Inner type is not supported"
1894 case ETH_VLAN_TYPE_OUTER:
1896 /* Only the high 16-bits is valid */
1897 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1898 IXGBE_EXVET_VET_EXT_SHIFT);
1900 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1901 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1902 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1903 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1904 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1905 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1906 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1912 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1920 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1922 struct ixgbe_hw *hw =
1923 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926 PMD_INIT_FUNC_TRACE();
1928 /* Filter Table Disable */
1929 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1930 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1932 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1936 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1938 struct ixgbe_hw *hw =
1939 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940 struct ixgbe_vfta *shadow_vfta =
1941 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1945 PMD_INIT_FUNC_TRACE();
1947 /* Filter Table Enable */
1948 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1949 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1950 vlnctrl |= IXGBE_VLNCTRL_VFE;
1952 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1954 /* write whatever is in local vfta copy */
1955 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1956 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1960 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1962 struct ixgbe_hwstrip *hwstrip =
1963 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1964 struct ixgbe_rx_queue *rxq;
1966 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1970 IXGBE_SET_HWSTRIP(hwstrip, queue);
1972 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1974 if (queue >= dev->data->nb_rx_queues)
1977 rxq = dev->data->rx_queues[queue];
1980 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1981 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1983 rxq->vlan_flags = PKT_RX_VLAN;
1984 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1989 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1991 struct ixgbe_hw *hw =
1992 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1995 PMD_INIT_FUNC_TRACE();
1997 if (hw->mac.type == ixgbe_mac_82598EB) {
1998 /* No queue level support */
1999 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2003 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2004 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2005 ctrl &= ~IXGBE_RXDCTL_VME;
2006 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2008 /* record those setting for HW strip per queue */
2009 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2013 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2015 struct ixgbe_hw *hw =
2016 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2019 PMD_INIT_FUNC_TRACE();
2021 if (hw->mac.type == ixgbe_mac_82598EB) {
2022 /* No queue level supported */
2023 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2027 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2028 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2029 ctrl |= IXGBE_RXDCTL_VME;
2030 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2032 /* record those setting for HW strip per queue */
2033 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2037 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2039 struct ixgbe_hw *hw =
2040 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2043 PMD_INIT_FUNC_TRACE();
2045 /* DMATXCTRL: Geric Double VLAN Disable */
2046 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2047 ctrl &= ~IXGBE_DMATXCTL_GDV;
2048 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2050 /* CTRL_EXT: Global Double VLAN Disable */
2051 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2052 ctrl &= ~IXGBE_EXTENDED_VLAN;
2053 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2058 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2060 struct ixgbe_hw *hw =
2061 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2064 PMD_INIT_FUNC_TRACE();
2066 /* DMATXCTRL: Geric Double VLAN Enable */
2067 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2068 ctrl |= IXGBE_DMATXCTL_GDV;
2069 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2071 /* CTRL_EXT: Global Double VLAN Enable */
2072 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2073 ctrl |= IXGBE_EXTENDED_VLAN;
2074 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2076 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2077 if (hw->mac.type == ixgbe_mac_X550 ||
2078 hw->mac.type == ixgbe_mac_X550EM_x ||
2079 hw->mac.type == ixgbe_mac_X550EM_a) {
2080 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2081 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2082 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2086 * VET EXT field in the EXVET register = 0x8100 by default
2087 * So no need to change. Same to VT field of DMATXCTL register
2092 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2094 struct ixgbe_hw *hw =
2095 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2099 struct ixgbe_rx_queue *rxq;
2102 PMD_INIT_FUNC_TRACE();
2104 if (hw->mac.type == ixgbe_mac_82598EB) {
2105 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2106 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2107 ctrl |= IXGBE_VLNCTRL_VME;
2108 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2110 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2111 ctrl &= ~IXGBE_VLNCTRL_VME;
2112 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2116 * Other 10G NIC, the VLAN strip can be setup
2117 * per queue in RXDCTL
2119 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2120 rxq = dev->data->rx_queues[i];
2121 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2122 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2123 ctrl |= IXGBE_RXDCTL_VME;
2126 ctrl &= ~IXGBE_RXDCTL_VME;
2129 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2131 /* record those setting for HW strip per queue */
2132 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2138 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2141 struct rte_eth_rxmode *rxmode;
2142 struct ixgbe_rx_queue *rxq;
2144 if (mask & ETH_VLAN_STRIP_MASK) {
2145 rxmode = &dev->data->dev_conf.rxmode;
2146 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2147 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2148 rxq = dev->data->rx_queues[i];
2149 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2152 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2153 rxq = dev->data->rx_queues[i];
2154 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2160 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2162 struct rte_eth_rxmode *rxmode;
2163 rxmode = &dev->data->dev_conf.rxmode;
2165 if (mask & ETH_VLAN_STRIP_MASK) {
2166 ixgbe_vlan_hw_strip_config(dev);
2169 if (mask & ETH_VLAN_FILTER_MASK) {
2170 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2171 ixgbe_vlan_hw_filter_enable(dev);
2173 ixgbe_vlan_hw_filter_disable(dev);
2176 if (mask & ETH_VLAN_EXTEND_MASK) {
2177 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2178 ixgbe_vlan_hw_extend_enable(dev);
2180 ixgbe_vlan_hw_extend_disable(dev);
2187 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2189 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2191 ixgbe_vlan_offload_config(dev, mask);
2197 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2199 struct ixgbe_hw *hw =
2200 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2202 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2204 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2205 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2209 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2211 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2216 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2219 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2225 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2226 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2227 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2228 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2233 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2235 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2236 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2238 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2240 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2241 /* check multi-queue mode */
2242 switch (dev_conf->rxmode.mq_mode) {
2243 case ETH_MQ_RX_VMDQ_DCB:
2244 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2246 case ETH_MQ_RX_VMDQ_DCB_RSS:
2247 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2248 PMD_INIT_LOG(ERR, "SRIOV active,"
2249 " unsupported mq_mode rx %d.",
2250 dev_conf->rxmode.mq_mode);
2253 case ETH_MQ_RX_VMDQ_RSS:
2254 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2255 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2256 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2257 PMD_INIT_LOG(ERR, "SRIOV is active,"
2258 " invalid queue number"
2259 " for VMDQ RSS, allowed"
2260 " value are 1, 2 or 4.");
2264 case ETH_MQ_RX_VMDQ_ONLY:
2265 case ETH_MQ_RX_NONE:
2266 /* if nothing mq mode configure, use default scheme */
2267 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2269 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2270 /* SRIOV only works in VMDq enable mode */
2271 PMD_INIT_LOG(ERR, "SRIOV is active,"
2272 " wrong mq_mode rx %d.",
2273 dev_conf->rxmode.mq_mode);
2277 switch (dev_conf->txmode.mq_mode) {
2278 case ETH_MQ_TX_VMDQ_DCB:
2279 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2280 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2282 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2283 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2287 /* check valid queue number */
2288 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2289 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2290 PMD_INIT_LOG(ERR, "SRIOV is active,"
2291 " nb_rx_q=%d nb_tx_q=%d queue number"
2292 " must be less than or equal to %d.",
2294 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2298 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2299 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2303 /* check configuration for vmdb+dcb mode */
2304 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2305 const struct rte_eth_vmdq_dcb_conf *conf;
2307 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2308 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2309 IXGBE_VMDQ_DCB_NB_QUEUES);
2312 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2313 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2314 conf->nb_queue_pools == ETH_32_POOLS)) {
2315 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2316 " nb_queue_pools must be %d or %d.",
2317 ETH_16_POOLS, ETH_32_POOLS);
2321 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2322 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2324 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2325 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2326 IXGBE_VMDQ_DCB_NB_QUEUES);
2329 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2330 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2331 conf->nb_queue_pools == ETH_32_POOLS)) {
2332 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2333 " nb_queue_pools != %d and"
2334 " nb_queue_pools != %d.",
2335 ETH_16_POOLS, ETH_32_POOLS);
2340 /* For DCB mode check our configuration before we go further */
2341 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2342 const struct rte_eth_dcb_rx_conf *conf;
2344 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2345 if (!(conf->nb_tcs == ETH_4_TCS ||
2346 conf->nb_tcs == ETH_8_TCS)) {
2347 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2348 " and nb_tcs != %d.",
2349 ETH_4_TCS, ETH_8_TCS);
2354 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2355 const struct rte_eth_dcb_tx_conf *conf;
2357 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2358 if (!(conf->nb_tcs == ETH_4_TCS ||
2359 conf->nb_tcs == ETH_8_TCS)) {
2360 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2361 " and nb_tcs != %d.",
2362 ETH_4_TCS, ETH_8_TCS);
2368 * When DCB/VT is off, maximum number of queues changes,
2369 * except for 82598EB, which remains constant.
2371 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2372 hw->mac.type != ixgbe_mac_82598EB) {
2373 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2375 "Neither VT nor DCB are enabled, "
2377 IXGBE_NONE_MODE_TX_NB_QUEUES);
2386 ixgbe_dev_configure(struct rte_eth_dev *dev)
2388 struct ixgbe_interrupt *intr =
2389 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2390 struct ixgbe_adapter *adapter = dev->data->dev_private;
2393 PMD_INIT_FUNC_TRACE();
2395 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2396 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2398 /* multipe queue mode checking */
2399 ret = ixgbe_check_mq_mode(dev);
2401 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2406 /* set flag to update link status after init */
2407 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2410 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2411 * allocation or vector Rx preconditions we will reset it.
2413 adapter->rx_bulk_alloc_allowed = true;
2414 adapter->rx_vec_allowed = true;
2420 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2422 struct ixgbe_hw *hw =
2423 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2424 struct ixgbe_interrupt *intr =
2425 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2428 /* only set up it on X550EM_X */
2429 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2430 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2431 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2432 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2433 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2434 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2439 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2440 uint16_t tx_rate, uint64_t q_msk)
2442 struct ixgbe_hw *hw;
2443 struct ixgbe_vf_info *vfinfo;
2444 struct rte_eth_link link;
2445 uint8_t nb_q_per_pool;
2446 uint32_t queue_stride;
2447 uint32_t queue_idx, idx = 0, vf_idx;
2449 uint16_t total_rate = 0;
2450 struct rte_pci_device *pci_dev;
2453 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2454 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2458 if (vf >= pci_dev->max_vfs)
2461 if (tx_rate > link.link_speed)
2467 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2468 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2469 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2470 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2471 queue_idx = vf * queue_stride;
2472 queue_end = queue_idx + nb_q_per_pool - 1;
2473 if (queue_end >= hw->mac.max_tx_queues)
2477 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2480 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2482 total_rate += vfinfo[vf_idx].tx_rate[idx];
2488 /* Store tx_rate for this vf. */
2489 for (idx = 0; idx < nb_q_per_pool; idx++) {
2490 if (((uint64_t)0x1 << idx) & q_msk) {
2491 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2492 vfinfo[vf].tx_rate[idx] = tx_rate;
2493 total_rate += tx_rate;
2497 if (total_rate > dev->data->dev_link.link_speed) {
2498 /* Reset stored TX rate of the VF if it causes exceed
2501 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2505 /* Set RTTBCNRC of each queue/pool for vf X */
2506 for (; queue_idx <= queue_end; queue_idx++) {
2508 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2516 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2518 struct ixgbe_adapter *adapter = dev->data->dev_private;
2524 err = ixgbe_fc_enable(hw);
2526 /* Not negotiated is not an error case */
2527 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2529 *check if we want to forward MAC frames - driver doesn't
2530 *have native capability to do that,
2531 *so we'll write the registers ourselves
2534 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2536 /* set or clear MFLCN.PMCF bit depending on configuration */
2537 if (adapter->mac_ctrl_frame_fwd != 0)
2538 mflcn |= IXGBE_MFLCN_PMCF;
2540 mflcn &= ~IXGBE_MFLCN_PMCF;
2542 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2543 IXGBE_WRITE_FLUSH(hw);
2551 * Configure device link speed and setup link.
2552 * It returns 0 on success.
2555 ixgbe_dev_start(struct rte_eth_dev *dev)
2557 struct ixgbe_hw *hw =
2558 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2559 struct ixgbe_vf_info *vfinfo =
2560 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2561 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2562 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2563 uint32_t intr_vector = 0;
2565 bool link_up = false, negotiate = 0;
2567 uint32_t allowed_speeds = 0;
2571 uint32_t *link_speeds;
2572 struct ixgbe_tm_conf *tm_conf =
2573 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2574 struct ixgbe_macsec_setting *macsec_setting =
2575 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2577 PMD_INIT_FUNC_TRACE();
2579 /* Stop the link setup handler before resetting the HW. */
2580 ixgbe_dev_wait_setup_link_complete(dev, 0);
2582 /* disable uio/vfio intr/eventfd mapping */
2583 rte_intr_disable(intr_handle);
2586 hw->adapter_stopped = 0;
2587 ixgbe_stop_adapter(hw);
2589 /* reinitialize adapter
2590 * this calls reset and start
2592 status = ixgbe_pf_reset_hw(hw);
2595 hw->mac.ops.start_hw(hw);
2596 hw->mac.get_link_status = true;
2598 /* configure PF module if SRIOV enabled */
2599 ixgbe_pf_host_configure(dev);
2601 ixgbe_dev_phy_intr_setup(dev);
2603 /* check and configure queue intr-vector mapping */
2604 if ((rte_intr_cap_multiple(intr_handle) ||
2605 !RTE_ETH_DEV_SRIOV(dev).active) &&
2606 dev->data->dev_conf.intr_conf.rxq != 0) {
2607 intr_vector = dev->data->nb_rx_queues;
2608 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2609 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2610 IXGBE_MAX_INTR_QUEUE_NUM);
2613 if (rte_intr_efd_enable(intr_handle, intr_vector))
2617 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2618 intr_handle->intr_vec =
2619 rte_zmalloc("intr_vec",
2620 dev->data->nb_rx_queues * sizeof(int), 0);
2621 if (intr_handle->intr_vec == NULL) {
2622 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2623 " intr_vec", dev->data->nb_rx_queues);
2628 /* confiugre msix for sleep until rx interrupt */
2629 ixgbe_configure_msix(dev);
2631 /* initialize transmission unit */
2632 ixgbe_dev_tx_init(dev);
2634 /* This can fail when allocating mbufs for descriptor rings */
2635 err = ixgbe_dev_rx_init(dev);
2637 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2641 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2642 ETH_VLAN_EXTEND_MASK;
2643 err = ixgbe_vlan_offload_config(dev, mask);
2645 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2649 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2650 /* Enable vlan filtering for VMDq */
2651 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2654 /* Configure DCB hw */
2655 ixgbe_configure_dcb(dev);
2657 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2658 err = ixgbe_fdir_configure(dev);
2663 /* Restore vf rate limit */
2664 if (vfinfo != NULL) {
2665 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2666 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2667 if (vfinfo[vf].tx_rate[idx] != 0)
2668 ixgbe_set_vf_rate_limit(
2670 vfinfo[vf].tx_rate[idx],
2674 ixgbe_restore_statistics_mapping(dev);
2676 err = ixgbe_flow_ctrl_enable(dev, hw);
2678 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2682 err = ixgbe_dev_rxtx_start(dev);
2684 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2688 /* Skip link setup if loopback mode is enabled. */
2689 if (dev->data->dev_conf.lpbk_mode != 0) {
2690 err = ixgbe_check_supported_loopback_mode(dev);
2692 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2695 goto skip_link_setup;
2699 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2700 err = hw->mac.ops.setup_sfp(hw);
2705 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2706 /* Turn on the copper */
2707 ixgbe_set_phy_power(hw, true);
2709 /* Turn on the laser */
2710 ixgbe_enable_tx_laser(hw);
2713 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2716 dev->data->dev_link.link_status = link_up;
2718 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2722 switch (hw->mac.type) {
2723 case ixgbe_mac_X550:
2724 case ixgbe_mac_X550EM_x:
2725 case ixgbe_mac_X550EM_a:
2726 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2727 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2729 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2730 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2731 allowed_speeds = ETH_LINK_SPEED_10M |
2732 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2735 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2739 link_speeds = &dev->data->dev_conf.link_speeds;
2741 /* Ignore autoneg flag bit and check the validity ofÂ
2744 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2745 PMD_INIT_LOG(ERR, "Invalid link setting");
2750 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2751 switch (hw->mac.type) {
2752 case ixgbe_mac_82598EB:
2753 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2755 case ixgbe_mac_82599EB:
2756 case ixgbe_mac_X540:
2757 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2759 case ixgbe_mac_X550:
2760 case ixgbe_mac_X550EM_x:
2761 case ixgbe_mac_X550EM_a:
2762 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2765 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2768 if (*link_speeds & ETH_LINK_SPEED_10G)
2769 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2770 if (*link_speeds & ETH_LINK_SPEED_5G)
2771 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2772 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2773 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2774 if (*link_speeds & ETH_LINK_SPEED_1G)
2775 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2776 if (*link_speeds & ETH_LINK_SPEED_100M)
2777 speed |= IXGBE_LINK_SPEED_100_FULL;
2778 if (*link_speeds & ETH_LINK_SPEED_10M)
2779 speed |= IXGBE_LINK_SPEED_10_FULL;
2782 err = ixgbe_setup_link(hw, speed, link_up);
2788 if (rte_intr_allow_others(intr_handle)) {
2789 /* check if lsc interrupt is enabled */
2790 if (dev->data->dev_conf.intr_conf.lsc != 0)
2791 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2793 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2794 ixgbe_dev_macsec_interrupt_setup(dev);
2796 rte_intr_callback_unregister(intr_handle,
2797 ixgbe_dev_interrupt_handler, dev);
2798 if (dev->data->dev_conf.intr_conf.lsc != 0)
2799 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2800 " no intr multiplex");
2803 /* check if rxq interrupt is enabled */
2804 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2805 rte_intr_dp_is_en(intr_handle))
2806 ixgbe_dev_rxq_interrupt_setup(dev);
2808 /* enable uio/vfio intr/eventfd mapping */
2809 rte_intr_enable(intr_handle);
2811 /* resume enabled intr since hw reset */
2812 ixgbe_enable_intr(dev);
2813 ixgbe_l2_tunnel_conf(dev);
2814 ixgbe_filter_restore(dev);
2816 if (tm_conf->root && !tm_conf->committed)
2817 PMD_DRV_LOG(WARNING,
2818 "please call hierarchy_commit() "
2819 "before starting the port");
2821 /* wait for the controller to acquire link */
2822 err = ixgbe_wait_for_link_up(hw);
2827 * Update link status right before return, because it may
2828 * start link configuration process in a separate thread.
2830 ixgbe_dev_link_update(dev, 0);
2832 /* setup the macsec setting register */
2833 if (macsec_setting->offload_en)
2834 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2839 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2840 ixgbe_dev_clear_queues(dev);
2845 * Stop device: disable rx and tx functions to allow for reconfiguring.
2848 ixgbe_dev_stop(struct rte_eth_dev *dev)
2850 struct rte_eth_link link;
2851 struct ixgbe_adapter *adapter = dev->data->dev_private;
2852 struct ixgbe_hw *hw =
2853 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854 struct ixgbe_vf_info *vfinfo =
2855 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2856 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2857 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2859 struct ixgbe_tm_conf *tm_conf =
2860 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2862 if (hw->adapter_stopped)
2865 PMD_INIT_FUNC_TRACE();
2867 ixgbe_dev_wait_setup_link_complete(dev, 0);
2869 /* disable interrupts */
2870 ixgbe_disable_intr(hw);
2873 ixgbe_pf_reset_hw(hw);
2874 hw->adapter_stopped = 0;
2877 ixgbe_stop_adapter(hw);
2879 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2880 vfinfo[vf].clear_to_send = false;
2882 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2883 /* Turn off the copper */
2884 ixgbe_set_phy_power(hw, false);
2886 /* Turn off the laser */
2887 ixgbe_disable_tx_laser(hw);
2890 ixgbe_dev_clear_queues(dev);
2892 /* Clear stored conf */
2893 dev->data->scattered_rx = 0;
2896 /* Clear recorded link status */
2897 memset(&link, 0, sizeof(link));
2898 rte_eth_linkstatus_set(dev, &link);
2900 if (!rte_intr_allow_others(intr_handle))
2901 /* resume to the default handler */
2902 rte_intr_callback_register(intr_handle,
2903 ixgbe_dev_interrupt_handler,
2906 /* Clean datapath event and queue/vec mapping */
2907 rte_intr_efd_disable(intr_handle);
2908 if (intr_handle->intr_vec != NULL) {
2909 rte_free(intr_handle->intr_vec);
2910 intr_handle->intr_vec = NULL;
2913 /* reset hierarchy commit */
2914 tm_conf->committed = false;
2916 adapter->rss_reta_updated = 0;
2918 hw->adapter_stopped = true;
2919 dev->data->dev_started = 0;
2925 * Set device link up: enable tx.
2928 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2930 struct ixgbe_hw *hw =
2931 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2932 if (hw->mac.type == ixgbe_mac_82599EB) {
2933 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2934 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2935 /* Not suported in bypass mode */
2936 PMD_INIT_LOG(ERR, "Set link up is not supported "
2937 "by device id 0x%x", hw->device_id);
2943 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2944 /* Turn on the copper */
2945 ixgbe_set_phy_power(hw, true);
2947 /* Turn on the laser */
2948 ixgbe_enable_tx_laser(hw);
2949 ixgbe_dev_link_update(dev, 0);
2956 * Set device link down: disable tx.
2959 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2961 struct ixgbe_hw *hw =
2962 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2963 if (hw->mac.type == ixgbe_mac_82599EB) {
2964 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2965 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2966 /* Not suported in bypass mode */
2967 PMD_INIT_LOG(ERR, "Set link down is not supported "
2968 "by device id 0x%x", hw->device_id);
2974 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2975 /* Turn off the copper */
2976 ixgbe_set_phy_power(hw, false);
2978 /* Turn off the laser */
2979 ixgbe_disable_tx_laser(hw);
2980 ixgbe_dev_link_update(dev, 0);
2987 * Reset and stop device.
2990 ixgbe_dev_close(struct rte_eth_dev *dev)
2992 struct ixgbe_hw *hw =
2993 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2994 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2995 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2999 PMD_INIT_FUNC_TRACE();
3000 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3003 ixgbe_pf_reset_hw(hw);
3005 ret = ixgbe_dev_stop(dev);
3007 ixgbe_dev_free_queues(dev);
3009 ixgbe_disable_pcie_master(hw);
3011 /* reprogram the RAR[0] in case user changed it. */
3012 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3014 /* Unlock any pending hardware semaphore */
3015 ixgbe_swfw_lock_reset(hw);
3017 /* disable uio intr before callback unregister */
3018 rte_intr_disable(intr_handle);
3021 ret = rte_intr_callback_unregister(intr_handle,
3022 ixgbe_dev_interrupt_handler, dev);
3023 if (ret >= 0 || ret == -ENOENT) {
3025 } else if (ret != -EAGAIN) {
3027 "intr callback unregister failed: %d",
3031 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3033 /* cancel the delay handler before remove dev */
3034 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3036 /* uninitialize PF if max_vfs not zero */
3037 ixgbe_pf_host_uninit(dev);
3039 /* remove all the fdir filters & hash */
3040 ixgbe_fdir_filter_uninit(dev);
3042 /* remove all the L2 tunnel filters & hash */
3043 ixgbe_l2_tn_filter_uninit(dev);
3045 /* Remove all ntuple filters of the device */
3046 ixgbe_ntuple_filter_uninit(dev);
3048 /* clear all the filters list */
3049 ixgbe_filterlist_flush();
3051 /* Remove all Traffic Manager configuration */
3052 ixgbe_tm_conf_uninit(dev);
3054 #ifdef RTE_LIB_SECURITY
3055 rte_free(dev->security_ctx);
3065 ixgbe_dev_reset(struct rte_eth_dev *dev)
3069 /* When a DPDK PMD PF begin to reset PF port, it should notify all
3070 * its VF to make them align with it. The detailed notification
3071 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3072 * To avoid unexpected behavior in VF, currently reset of PF with
3073 * SR-IOV activation is not supported. It might be supported later.
3075 if (dev->data->sriov.active)
3078 ret = eth_ixgbe_dev_uninit(dev);
3082 ret = eth_ixgbe_dev_init(dev, NULL);
3088 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3089 struct ixgbe_hw_stats *hw_stats,
3090 struct ixgbe_macsec_stats *macsec_stats,
3091 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3092 uint64_t *total_qprc, uint64_t *total_qprdc)
3094 uint32_t bprc, lxon, lxoff, total;
3095 uint32_t delta_gprc = 0;
3097 /* Workaround for RX byte count not including CRC bytes when CRC
3098 * strip is enabled. CRC bytes are removed from counters when crc_strip
3101 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3102 IXGBE_HLREG0_RXCRCSTRP);
3104 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3105 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3106 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3107 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3109 for (i = 0; i < 8; i++) {
3110 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3112 /* global total per queue */
3113 hw_stats->mpc[i] += mp;
3114 /* Running comprehensive total for stats display */
3115 *total_missed_rx += hw_stats->mpc[i];
3116 if (hw->mac.type == ixgbe_mac_82598EB) {
3117 hw_stats->rnbc[i] +=
3118 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3119 hw_stats->pxonrxc[i] +=
3120 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3121 hw_stats->pxoffrxc[i] +=
3122 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3124 hw_stats->pxonrxc[i] +=
3125 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3126 hw_stats->pxoffrxc[i] +=
3127 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3128 hw_stats->pxon2offc[i] +=
3129 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3131 hw_stats->pxontxc[i] +=
3132 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3133 hw_stats->pxofftxc[i] +=
3134 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3136 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3137 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3138 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3139 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3141 delta_gprc += delta_qprc;
3143 hw_stats->qprc[i] += delta_qprc;
3144 hw_stats->qptc[i] += delta_qptc;
3146 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3147 hw_stats->qbrc[i] +=
3148 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3150 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3152 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3153 hw_stats->qbtc[i] +=
3154 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3156 hw_stats->qprdc[i] += delta_qprdc;
3157 *total_qprdc += hw_stats->qprdc[i];
3159 *total_qprc += hw_stats->qprc[i];
3160 *total_qbrc += hw_stats->qbrc[i];
3162 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3163 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3164 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3167 * An errata states that gprc actually counts good + missed packets:
3168 * Workaround to set gprc to summated queue packet receives
3170 hw_stats->gprc = *total_qprc;
3172 if (hw->mac.type != ixgbe_mac_82598EB) {
3173 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3174 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3175 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3176 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3177 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3178 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3179 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3180 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3182 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3183 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3184 /* 82598 only has a counter in the high register */
3185 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3186 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3187 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3189 uint64_t old_tpr = hw_stats->tpr;
3191 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3192 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3195 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3197 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3198 hw_stats->gptc += delta_gptc;
3199 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3200 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3203 * Workaround: mprc hardware is incorrectly counting
3204 * broadcasts, so for now we subtract those.
3206 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3207 hw_stats->bprc += bprc;
3208 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3209 if (hw->mac.type == ixgbe_mac_82598EB)
3210 hw_stats->mprc -= bprc;
3212 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3213 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3214 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3215 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3216 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3217 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3219 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3220 hw_stats->lxontxc += lxon;
3221 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3222 hw_stats->lxofftxc += lxoff;
3223 total = lxon + lxoff;
3225 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3226 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3227 hw_stats->gptc -= total;
3228 hw_stats->mptc -= total;
3229 hw_stats->ptc64 -= total;
3230 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3232 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3233 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3234 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3235 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3236 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3237 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3238 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3239 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3240 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3241 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3242 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3243 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3244 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3245 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3246 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3247 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3248 /* Only read FCOE on 82599 */
3249 if (hw->mac.type != ixgbe_mac_82598EB) {
3250 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3251 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3252 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3253 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3254 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3257 /* Flow Director Stats registers */
3258 if (hw->mac.type != ixgbe_mac_82598EB) {
3259 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3260 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3261 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3262 IXGBE_FDIRUSTAT) & 0xFFFF;
3263 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3264 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3265 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3266 IXGBE_FDIRFSTAT) & 0xFFFF;
3267 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3268 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3270 /* MACsec Stats registers */
3271 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3272 macsec_stats->out_pkts_encrypted +=
3273 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3274 macsec_stats->out_pkts_protected +=
3275 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3276 macsec_stats->out_octets_encrypted +=
3277 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3278 macsec_stats->out_octets_protected +=
3279 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3280 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3281 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3282 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3283 macsec_stats->in_pkts_unknownsci +=
3284 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3285 macsec_stats->in_octets_decrypted +=
3286 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3287 macsec_stats->in_octets_validated +=
3288 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3289 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3290 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3291 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3292 for (i = 0; i < 2; i++) {
3293 macsec_stats->in_pkts_ok +=
3294 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3295 macsec_stats->in_pkts_invalid +=
3296 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3297 macsec_stats->in_pkts_notvalid +=
3298 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3300 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3301 macsec_stats->in_pkts_notusingsa +=
3302 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3306 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3309 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3311 struct ixgbe_hw *hw =
3312 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313 struct ixgbe_hw_stats *hw_stats =
3314 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3315 struct ixgbe_macsec_stats *macsec_stats =
3316 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3317 dev->data->dev_private);
3318 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3321 total_missed_rx = 0;
3326 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3327 &total_qbrc, &total_qprc, &total_qprdc);
3332 /* Fill out the rte_eth_stats statistics structure */
3333 stats->ipackets = total_qprc;
3334 stats->ibytes = total_qbrc;
3335 stats->opackets = hw_stats->gptc;
3336 stats->obytes = hw_stats->gotc;
3338 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3339 stats->q_ipackets[i] = hw_stats->qprc[i];
3340 stats->q_opackets[i] = hw_stats->qptc[i];
3341 stats->q_ibytes[i] = hw_stats->qbrc[i];
3342 stats->q_obytes[i] = hw_stats->qbtc[i];
3343 stats->q_errors[i] = hw_stats->qprdc[i];
3347 stats->imissed = total_missed_rx;
3348 stats->ierrors = hw_stats->crcerrs +
3365 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3367 struct ixgbe_hw_stats *stats =
3368 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3370 /* HW registers are cleared on read */
3371 ixgbe_dev_stats_get(dev, NULL);
3373 /* Reset software totals */
3374 memset(stats, 0, sizeof(*stats));
3379 /* This function calculates the number of xstats based on the current config */
3381 ixgbe_xstats_calc_num(void) {
3382 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3383 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3384 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3387 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3388 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3390 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3391 unsigned stat, i, count;
3393 if (xstats_names != NULL) {
3396 /* Note: limit >= cnt_stats checked upstream
3397 * in rte_eth_xstats_names()
3400 /* Extended stats from ixgbe_hw_stats */
3401 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3402 strlcpy(xstats_names[count].name,
3403 rte_ixgbe_stats_strings[i].name,
3404 sizeof(xstats_names[count].name));
3409 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3410 strlcpy(xstats_names[count].name,
3411 rte_ixgbe_macsec_strings[i].name,
3412 sizeof(xstats_names[count].name));
3416 /* RX Priority Stats */
3417 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3418 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3419 snprintf(xstats_names[count].name,
3420 sizeof(xstats_names[count].name),
3421 "rx_priority%u_%s", i,
3422 rte_ixgbe_rxq_strings[stat].name);
3427 /* TX Priority Stats */
3428 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3429 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3430 snprintf(xstats_names[count].name,
3431 sizeof(xstats_names[count].name),
3432 "tx_priority%u_%s", i,
3433 rte_ixgbe_txq_strings[stat].name);
3441 static int ixgbe_dev_xstats_get_names_by_id(
3442 struct rte_eth_dev *dev,
3443 struct rte_eth_xstat_name *xstats_names,
3444 const uint64_t *ids,
3448 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3449 unsigned int stat, i, count;
3451 if (xstats_names != NULL) {
3454 /* Note: limit >= cnt_stats checked upstream
3455 * in rte_eth_xstats_names()
3458 /* Extended stats from ixgbe_hw_stats */
3459 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3460 strlcpy(xstats_names[count].name,
3461 rte_ixgbe_stats_strings[i].name,
3462 sizeof(xstats_names[count].name));
3467 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3468 strlcpy(xstats_names[count].name,
3469 rte_ixgbe_macsec_strings[i].name,
3470 sizeof(xstats_names[count].name));
3474 /* RX Priority Stats */
3475 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3476 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3477 snprintf(xstats_names[count].name,
3478 sizeof(xstats_names[count].name),
3479 "rx_priority%u_%s", i,
3480 rte_ixgbe_rxq_strings[stat].name);
3485 /* TX Priority Stats */
3486 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3487 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3488 snprintf(xstats_names[count].name,
3489 sizeof(xstats_names[count].name),
3490 "tx_priority%u_%s", i,
3491 rte_ixgbe_txq_strings[stat].name);
3500 uint16_t size = ixgbe_xstats_calc_num();
3501 struct rte_eth_xstat_name xstats_names_copy[size];
3503 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3506 for (i = 0; i < limit; i++) {
3507 if (ids[i] >= size) {
3508 PMD_INIT_LOG(ERR, "id value isn't valid");
3511 strcpy(xstats_names[i].name,
3512 xstats_names_copy[ids[i]].name);
3517 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3518 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3522 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3525 if (xstats_names != NULL)
3526 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3527 strlcpy(xstats_names[i].name,
3528 rte_ixgbevf_stats_strings[i].name,
3529 sizeof(xstats_names[i].name));
3530 return IXGBEVF_NB_XSTATS;
3534 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3537 struct ixgbe_hw *hw =
3538 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3539 struct ixgbe_hw_stats *hw_stats =
3540 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3541 struct ixgbe_macsec_stats *macsec_stats =
3542 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3543 dev->data->dev_private);
3544 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3545 unsigned i, stat, count = 0;
3547 count = ixgbe_xstats_calc_num();
3552 total_missed_rx = 0;
3557 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3558 &total_qbrc, &total_qprc, &total_qprdc);
3560 /* If this is a reset xstats is NULL, and we have cleared the
3561 * registers by reading them.
3566 /* Extended stats from ixgbe_hw_stats */
3568 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3569 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3570 rte_ixgbe_stats_strings[i].offset);
3571 xstats[count].id = count;
3576 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3577 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3578 rte_ixgbe_macsec_strings[i].offset);
3579 xstats[count].id = count;
3583 /* RX Priority Stats */
3584 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3585 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3586 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3587 rte_ixgbe_rxq_strings[stat].offset +
3588 (sizeof(uint64_t) * i));
3589 xstats[count].id = count;
3594 /* TX Priority Stats */
3595 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3596 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3597 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3598 rte_ixgbe_txq_strings[stat].offset +
3599 (sizeof(uint64_t) * i));
3600 xstats[count].id = count;
3608 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3609 uint64_t *values, unsigned int n)
3612 struct ixgbe_hw *hw =
3613 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3614 struct ixgbe_hw_stats *hw_stats =
3615 IXGBE_DEV_PRIVATE_TO_STATS(
3616 dev->data->dev_private);
3617 struct ixgbe_macsec_stats *macsec_stats =
3618 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3619 dev->data->dev_private);
3620 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3621 unsigned int i, stat, count = 0;
3623 count = ixgbe_xstats_calc_num();
3625 if (!ids && n < count)
3628 total_missed_rx = 0;
3633 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3634 &total_missed_rx, &total_qbrc, &total_qprc,
3637 /* If this is a reset xstats is NULL, and we have cleared the
3638 * registers by reading them.
3640 if (!ids && !values)
3643 /* Extended stats from ixgbe_hw_stats */
3645 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3646 values[count] = *(uint64_t *)(((char *)hw_stats) +
3647 rte_ixgbe_stats_strings[i].offset);
3652 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3653 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3654 rte_ixgbe_macsec_strings[i].offset);
3658 /* RX Priority Stats */
3659 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3660 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3662 *(uint64_t *)(((char *)hw_stats) +
3663 rte_ixgbe_rxq_strings[stat].offset +
3664 (sizeof(uint64_t) * i));
3669 /* TX Priority Stats */
3670 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3671 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3673 *(uint64_t *)(((char *)hw_stats) +
3674 rte_ixgbe_txq_strings[stat].offset +
3675 (sizeof(uint64_t) * i));
3683 uint16_t size = ixgbe_xstats_calc_num();
3684 uint64_t values_copy[size];
3686 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3688 for (i = 0; i < n; i++) {
3689 if (ids[i] >= size) {
3690 PMD_INIT_LOG(ERR, "id value isn't valid");
3693 values[i] = values_copy[ids[i]];
3699 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3701 struct ixgbe_hw_stats *stats =
3702 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3703 struct ixgbe_macsec_stats *macsec_stats =
3704 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3705 dev->data->dev_private);
3707 unsigned count = ixgbe_xstats_calc_num();
3709 /* HW registers are cleared on read */
3710 ixgbe_dev_xstats_get(dev, NULL, count);
3712 /* Reset software totals */
3713 memset(stats, 0, sizeof(*stats));
3714 memset(macsec_stats, 0, sizeof(*macsec_stats));
3720 ixgbevf_update_stats(struct rte_eth_dev *dev)
3722 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3723 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3724 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3726 /* Good Rx packet, include VF loopback */
3727 UPDATE_VF_STAT(IXGBE_VFGPRC,
3728 hw_stats->last_vfgprc, hw_stats->vfgprc);
3730 /* Good Rx octets, include VF loopback */
3731 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3732 hw_stats->last_vfgorc, hw_stats->vfgorc);
3734 /* Good Tx packet, include VF loopback */
3735 UPDATE_VF_STAT(IXGBE_VFGPTC,
3736 hw_stats->last_vfgptc, hw_stats->vfgptc);
3738 /* Good Tx octets, include VF loopback */
3739 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3740 hw_stats->last_vfgotc, hw_stats->vfgotc);
3742 /* Rx Multicst Packet */
3743 UPDATE_VF_STAT(IXGBE_VFMPRC,
3744 hw_stats->last_vfmprc, hw_stats->vfmprc);
3748 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3751 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3752 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3755 if (n < IXGBEVF_NB_XSTATS)
3756 return IXGBEVF_NB_XSTATS;
3758 ixgbevf_update_stats(dev);
3763 /* Extended stats */
3764 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3766 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3767 rte_ixgbevf_stats_strings[i].offset);
3770 return IXGBEVF_NB_XSTATS;
3774 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3776 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3777 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3779 ixgbevf_update_stats(dev);
3784 stats->ipackets = hw_stats->vfgprc;
3785 stats->ibytes = hw_stats->vfgorc;
3786 stats->opackets = hw_stats->vfgptc;
3787 stats->obytes = hw_stats->vfgotc;
3792 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3794 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3795 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3797 /* Sync HW register to the last stats */
3798 ixgbevf_dev_stats_get(dev, NULL);
3800 /* reset HW current stats*/
3801 hw_stats->vfgprc = 0;
3802 hw_stats->vfgorc = 0;
3803 hw_stats->vfgptc = 0;
3804 hw_stats->vfgotc = 0;
3810 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3812 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3813 u16 eeprom_verh, eeprom_verl;
3817 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3818 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3820 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3821 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3823 ret += 1; /* add the size of '\0' */
3824 if (fw_size < (u32)ret)
3831 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3833 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3834 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3835 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3837 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3838 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3839 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3841 * When DCB/VT is off, maximum number of queues changes,
3842 * except for 82598EB, which remains constant.
3844 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3845 hw->mac.type != ixgbe_mac_82598EB)
3846 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3848 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3849 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3850 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3851 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3852 dev_info->max_vfs = pci_dev->max_vfs;
3853 if (hw->mac.type == ixgbe_mac_82598EB)
3854 dev_info->max_vmdq_pools = ETH_16_POOLS;
3856 dev_info->max_vmdq_pools = ETH_64_POOLS;
3857 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3858 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3859 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3860 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3861 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3862 dev_info->rx_queue_offload_capa);
3863 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3864 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3866 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3868 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3869 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3870 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3872 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3877 dev_info->default_txconf = (struct rte_eth_txconf) {
3879 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3880 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3881 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3883 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3884 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3888 dev_info->rx_desc_lim = rx_desc_lim;
3889 dev_info->tx_desc_lim = tx_desc_lim;
3891 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3892 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3893 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3895 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3896 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3897 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3898 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3899 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3901 if (hw->mac.type == ixgbe_mac_X540 ||
3902 hw->mac.type == ixgbe_mac_X540_vf ||
3903 hw->mac.type == ixgbe_mac_X550 ||
3904 hw->mac.type == ixgbe_mac_X550_vf) {
3905 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3907 if (hw->mac.type == ixgbe_mac_X550) {
3908 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3909 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3912 /* Driver-preferred Rx/Tx parameters */
3913 dev_info->default_rxportconf.burst_size = 32;
3914 dev_info->default_txportconf.burst_size = 32;
3915 dev_info->default_rxportconf.nb_queues = 1;
3916 dev_info->default_txportconf.nb_queues = 1;
3917 dev_info->default_rxportconf.ring_size = 256;
3918 dev_info->default_txportconf.ring_size = 256;
3923 static const uint32_t *
3924 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3926 static const uint32_t ptypes[] = {
3927 /* For non-vec functions,
3928 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3929 * for vec functions,
3930 * refers to _recv_raw_pkts_vec().
3934 RTE_PTYPE_L3_IPV4_EXT,
3936 RTE_PTYPE_L3_IPV6_EXT,
3940 RTE_PTYPE_TUNNEL_IP,
3941 RTE_PTYPE_INNER_L3_IPV6,
3942 RTE_PTYPE_INNER_L3_IPV6_EXT,
3943 RTE_PTYPE_INNER_L4_TCP,
3944 RTE_PTYPE_INNER_L4_UDP,
3948 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3949 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3950 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3951 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3954 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3955 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3956 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3963 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3964 struct rte_eth_dev_info *dev_info)
3966 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3967 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3969 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3970 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3971 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3972 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3973 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3974 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3975 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3976 dev_info->max_vfs = pci_dev->max_vfs;
3977 if (hw->mac.type == ixgbe_mac_82598EB)
3978 dev_info->max_vmdq_pools = ETH_16_POOLS;
3980 dev_info->max_vmdq_pools = ETH_64_POOLS;
3981 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3982 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3983 dev_info->rx_queue_offload_capa);
3984 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3985 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3986 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3987 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3988 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3990 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3992 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3993 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3994 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3996 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4001 dev_info->default_txconf = (struct rte_eth_txconf) {
4003 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4004 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4005 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4007 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4008 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4012 dev_info->rx_desc_lim = rx_desc_lim;
4013 dev_info->tx_desc_lim = tx_desc_lim;
4019 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4020 bool *link_up, int wait_to_complete)
4022 struct ixgbe_adapter *adapter = container_of(hw,
4023 struct ixgbe_adapter, hw);
4024 struct ixgbe_mbx_info *mbx = &hw->mbx;
4025 struct ixgbe_mac_info *mac = &hw->mac;
4026 uint32_t links_reg, in_msg;
4029 /* If we were hit with a reset drop the link */
4030 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4031 mac->get_link_status = true;
4033 if (!mac->get_link_status)
4036 /* if link status is down no point in checking to see if pf is up */
4037 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4038 if (!(links_reg & IXGBE_LINKS_UP))
4041 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4042 * before the link status is correct
4044 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4047 for (i = 0; i < 5; i++) {
4049 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4051 if (!(links_reg & IXGBE_LINKS_UP))
4056 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4057 case IXGBE_LINKS_SPEED_10G_82599:
4058 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4059 if (hw->mac.type >= ixgbe_mac_X550) {
4060 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4061 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4064 case IXGBE_LINKS_SPEED_1G_82599:
4065 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4067 case IXGBE_LINKS_SPEED_100_82599:
4068 *speed = IXGBE_LINK_SPEED_100_FULL;
4069 if (hw->mac.type == ixgbe_mac_X550) {
4070 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4071 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4074 case IXGBE_LINKS_SPEED_10_X550EM_A:
4075 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4076 /* Since Reserved in older MAC's */
4077 if (hw->mac.type >= ixgbe_mac_X550)
4078 *speed = IXGBE_LINK_SPEED_10_FULL;
4081 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4084 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4085 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4086 mac->get_link_status = true;
4088 mac->get_link_status = false;
4093 /* if the read failed it could just be a mailbox collision, best wait
4094 * until we are called again and don't report an error
4096 if (mbx->ops.read(hw, &in_msg, 1, 0))
4099 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4100 /* msg is not CTS and is NACK we must have lost CTS status */
4101 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4102 mac->get_link_status = false;
4106 /* the pf is talking, if we timed out in the past we reinit */
4107 if (!mbx->timeout) {
4112 /* if we passed all the tests above then the link is up and we no
4113 * longer need to check for link
4115 mac->get_link_status = false;
4118 *link_up = !mac->get_link_status;
4123 * If @timeout_ms was 0, it means that it will not return until link complete.
4124 * It returns 1 on complete, return 0 on timeout.
4127 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4129 #define WARNING_TIMEOUT 9000 /* 9s in total */
4130 struct ixgbe_adapter *ad = dev->data->dev_private;
4131 uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4133 while (rte_atomic32_read(&ad->link_thread_running)) {
4140 } else if (!timeout) {
4141 /* It will not return until link complete */
4142 timeout = WARNING_TIMEOUT;
4143 PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4151 ixgbe_dev_setup_link_thread_handler(void *param)
4153 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4154 struct ixgbe_adapter *ad = dev->data->dev_private;
4155 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4156 struct ixgbe_interrupt *intr =
4157 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4159 bool autoneg = false;
4161 pthread_detach(pthread_self());
4162 speed = hw->phy.autoneg_advertised;
4164 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4166 ixgbe_setup_link(hw, speed, true);
4168 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4169 rte_atomic32_clear(&ad->link_thread_running);
4174 * In freebsd environment, nic_uio drivers do not support interrupts,
4175 * rte_intr_callback_register() will fail to register interrupts.
4176 * We can not make link status to change from down to up by interrupt
4177 * callback. So we need to wait for the controller to acquire link
4179 * It returns 0 on link up.
4182 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4184 #ifdef RTE_EXEC_ENV_FREEBSD
4186 bool link_up = false;
4188 const int nb_iter = 25;
4190 for (i = 0; i < nb_iter; i++) {
4191 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4206 /* return 0 means link status changed, -1 means not changed */
4208 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4209 int wait_to_complete, int vf)
4211 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4212 struct ixgbe_adapter *ad = dev->data->dev_private;
4213 struct rte_eth_link link;
4214 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4215 struct ixgbe_interrupt *intr =
4216 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4222 memset(&link, 0, sizeof(link));
4223 link.link_status = ETH_LINK_DOWN;
4224 link.link_speed = ETH_SPEED_NUM_NONE;
4225 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4226 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4227 ETH_LINK_SPEED_FIXED);
4229 hw->mac.get_link_status = true;
4231 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4232 return rte_eth_linkstatus_set(dev, &link);
4234 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4235 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4238 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4239 #ifdef RTE_EXEC_ENV_FREEBSD
4244 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4246 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4249 link.link_speed = ETH_SPEED_NUM_100M;
4250 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4251 return rte_eth_linkstatus_set(dev, &link);
4254 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4255 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4256 if ((esdp_reg & IXGBE_ESDP_SDP3))
4261 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4262 ixgbe_dev_wait_setup_link_complete(dev, 0);
4263 if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4264 /* To avoid race condition between threads, set
4265 * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4266 * when there is no link thread running.
4268 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4269 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4270 "ixgbe-link-handler",
4272 ixgbe_dev_setup_link_thread_handler,
4275 "Create link thread failed!");
4276 rte_atomic32_clear(&ad->link_thread_running);
4280 "Other link thread is running now!");
4283 return rte_eth_linkstatus_set(dev, &link);
4286 link.link_status = ETH_LINK_UP;
4287 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4289 switch (link_speed) {
4291 case IXGBE_LINK_SPEED_UNKNOWN:
4292 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4295 case IXGBE_LINK_SPEED_10_FULL:
4296 link.link_speed = ETH_SPEED_NUM_10M;
4299 case IXGBE_LINK_SPEED_100_FULL:
4300 link.link_speed = ETH_SPEED_NUM_100M;
4303 case IXGBE_LINK_SPEED_1GB_FULL:
4304 link.link_speed = ETH_SPEED_NUM_1G;
4307 case IXGBE_LINK_SPEED_2_5GB_FULL:
4308 link.link_speed = ETH_SPEED_NUM_2_5G;
4311 case IXGBE_LINK_SPEED_5GB_FULL:
4312 link.link_speed = ETH_SPEED_NUM_5G;
4315 case IXGBE_LINK_SPEED_10GB_FULL:
4316 link.link_speed = ETH_SPEED_NUM_10G;
4320 return rte_eth_linkstatus_set(dev, &link);
4324 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4326 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4330 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4332 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4336 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4338 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4341 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4342 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4343 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4349 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4351 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4354 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4355 fctrl &= (~IXGBE_FCTRL_UPE);
4356 if (dev->data->all_multicast == 1)
4357 fctrl |= IXGBE_FCTRL_MPE;
4359 fctrl &= (~IXGBE_FCTRL_MPE);
4360 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4366 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4368 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4371 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4372 fctrl |= IXGBE_FCTRL_MPE;
4373 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4379 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4381 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4384 if (dev->data->promiscuous == 1)
4385 return 0; /* must remain in all_multicast mode */
4387 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4388 fctrl &= (~IXGBE_FCTRL_MPE);
4389 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4395 * It clears the interrupt causes and enables the interrupt.
4396 * It will be called once only during nic initialized.
4399 * Pointer to struct rte_eth_dev.
4401 * Enable or Disable.
4404 * - On success, zero.
4405 * - On failure, a negative value.
4408 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4410 struct ixgbe_interrupt *intr =
4411 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4413 ixgbe_dev_link_status_print(dev);
4415 intr->mask |= IXGBE_EICR_LSC;
4417 intr->mask &= ~IXGBE_EICR_LSC;
4423 * It clears the interrupt causes and enables the interrupt.
4424 * It will be called once only during nic initialized.
4427 * Pointer to struct rte_eth_dev.
4430 * - On success, zero.
4431 * - On failure, a negative value.
4434 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4436 struct ixgbe_interrupt *intr =
4437 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4439 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4445 * It clears the interrupt causes and enables the interrupt.
4446 * It will be called once only during nic initialized.
4449 * Pointer to struct rte_eth_dev.
4452 * - On success, zero.
4453 * - On failure, a negative value.
4456 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4458 struct ixgbe_interrupt *intr =
4459 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4461 intr->mask |= IXGBE_EICR_LINKSEC;
4467 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4470 * Pointer to struct rte_eth_dev.
4473 * - On success, zero.
4474 * - On failure, a negative value.
4477 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4480 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481 struct ixgbe_interrupt *intr =
4482 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4484 /* clear all cause mask */
4485 ixgbe_disable_intr(hw);
4487 /* read-on-clear nic registers here */
4488 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4489 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4493 /* set flag for async link update */
4494 if (eicr & IXGBE_EICR_LSC)
4495 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4497 if (eicr & IXGBE_EICR_MAILBOX)
4498 intr->flags |= IXGBE_FLAG_MAILBOX;
4500 if (eicr & IXGBE_EICR_LINKSEC)
4501 intr->flags |= IXGBE_FLAG_MACSEC;
4503 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4504 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4505 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4506 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4512 * It gets and then prints the link status.
4515 * Pointer to struct rte_eth_dev.
4518 * - On success, zero.
4519 * - On failure, a negative value.
4522 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4524 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4525 struct rte_eth_link link;
4527 rte_eth_linkstatus_get(dev, &link);
4529 if (link.link_status) {
4530 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4531 (int)(dev->data->port_id),
4532 (unsigned)link.link_speed,
4533 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4534 "full-duplex" : "half-duplex");
4536 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4537 (int)(dev->data->port_id));
4539 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4540 pci_dev->addr.domain,
4542 pci_dev->addr.devid,
4543 pci_dev->addr.function);
4547 * It executes link_update after knowing an interrupt occurred.
4550 * Pointer to struct rte_eth_dev.
4553 * - On success, zero.
4554 * - On failure, a negative value.
4557 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4559 struct ixgbe_interrupt *intr =
4560 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4562 struct ixgbe_hw *hw =
4563 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4565 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4567 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4568 ixgbe_pf_mbx_process(dev);
4569 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4572 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4573 ixgbe_handle_lasi(hw);
4574 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4577 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4578 struct rte_eth_link link;
4580 /* get the link status before link update, for predicting later */
4581 rte_eth_linkstatus_get(dev, &link);
4583 ixgbe_dev_link_update(dev, 0);
4586 if (!link.link_status)
4587 /* handle it 1 sec later, wait it being stable */
4588 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4589 /* likely to down */
4591 /* handle it 4 sec later, wait it being stable */
4592 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4594 ixgbe_dev_link_status_print(dev);
4595 if (rte_eal_alarm_set(timeout * 1000,
4596 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4597 PMD_DRV_LOG(ERR, "Error setting alarm");
4599 /* remember original mask */
4600 intr->mask_original = intr->mask;
4601 /* only disable lsc interrupt */
4602 intr->mask &= ~IXGBE_EIMS_LSC;
4606 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4607 ixgbe_enable_intr(dev);
4613 * Interrupt handler which shall be registered for alarm callback for delayed
4614 * handling specific interrupt to wait for the stable nic state. As the
4615 * NIC interrupt state is not stable for ixgbe after link is just down,
4616 * it needs to wait 4 seconds to get the stable status.
4619 * Pointer to interrupt handle.
4621 * The address of parameter (struct rte_eth_dev *) regsitered before.
4627 ixgbe_dev_interrupt_delayed_handler(void *param)
4629 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4630 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4631 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4632 struct ixgbe_interrupt *intr =
4633 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4634 struct ixgbe_hw *hw =
4635 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4638 ixgbe_disable_intr(hw);
4640 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4641 if (eicr & IXGBE_EICR_MAILBOX)
4642 ixgbe_pf_mbx_process(dev);
4644 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4645 ixgbe_handle_lasi(hw);
4646 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4649 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4650 ixgbe_dev_link_update(dev, 0);
4651 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4652 ixgbe_dev_link_status_print(dev);
4653 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4656 if (intr->flags & IXGBE_FLAG_MACSEC) {
4657 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4658 intr->flags &= ~IXGBE_FLAG_MACSEC;
4661 /* restore original mask */
4662 intr->mask = intr->mask_original;
4663 intr->mask_original = 0;
4665 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4666 ixgbe_enable_intr(dev);
4667 rte_intr_ack(intr_handle);
4671 * Interrupt handler triggered by NIC for handling
4672 * specific interrupt.
4675 * Pointer to interrupt handle.
4677 * The address of parameter (struct rte_eth_dev *) regsitered before.
4683 ixgbe_dev_interrupt_handler(void *param)
4685 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4687 ixgbe_dev_interrupt_get_status(dev);
4688 ixgbe_dev_interrupt_action(dev);
4692 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4694 struct ixgbe_hw *hw;
4696 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4697 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4701 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4703 struct ixgbe_hw *hw;
4705 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4706 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4710 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4712 struct ixgbe_hw *hw;
4718 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4720 fc_conf->pause_time = hw->fc.pause_time;
4721 fc_conf->high_water = hw->fc.high_water[0];
4722 fc_conf->low_water = hw->fc.low_water[0];
4723 fc_conf->send_xon = hw->fc.send_xon;
4724 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4727 * Return rx_pause status according to actual setting of
4730 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4731 if (mflcn_reg & IXGBE_MFLCN_PMCF)
4732 fc_conf->mac_ctrl_frame_fwd = 1;
4734 fc_conf->mac_ctrl_frame_fwd = 0;
4736 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4742 * Return tx_pause status according to actual setting of
4745 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4746 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4751 if (rx_pause && tx_pause)
4752 fc_conf->mode = RTE_FC_FULL;
4754 fc_conf->mode = RTE_FC_RX_PAUSE;
4756 fc_conf->mode = RTE_FC_TX_PAUSE;
4758 fc_conf->mode = RTE_FC_NONE;
4764 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4766 struct ixgbe_hw *hw;
4767 struct ixgbe_adapter *adapter = dev->data->dev_private;
4769 uint32_t rx_buf_size;
4770 uint32_t max_high_water;
4771 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4778 PMD_INIT_FUNC_TRACE();
4780 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4781 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4782 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4785 * At least reserve one Ethernet frame for watermark
4786 * high_water/low_water in kilo bytes for ixgbe
4788 max_high_water = (rx_buf_size -
4789 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4790 if ((fc_conf->high_water > max_high_water) ||
4791 (fc_conf->high_water < fc_conf->low_water)) {
4792 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4793 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4797 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4798 hw->fc.pause_time = fc_conf->pause_time;
4799 hw->fc.high_water[0] = fc_conf->high_water;
4800 hw->fc.low_water[0] = fc_conf->low_water;
4801 hw->fc.send_xon = fc_conf->send_xon;
4802 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4803 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4805 err = ixgbe_flow_ctrl_enable(dev, hw);
4807 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4814 * ixgbe_pfc_enable_generic - Enable flow control
4815 * @hw: pointer to hardware structure
4816 * @tc_num: traffic class number
4817 * Enable flow control according to the current settings.
4820 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4823 uint32_t mflcn_reg, fccfg_reg;
4825 uint32_t fcrtl, fcrth;
4829 /* Validate the water mark configuration */
4830 if (!hw->fc.pause_time) {
4831 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4835 /* Low water mark of zero causes XOFF floods */
4836 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4837 /* High/Low water can not be 0 */
4838 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4839 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4840 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4844 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4845 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4846 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4850 /* Negotiate the fc mode to use */
4851 ixgbe_fc_autoneg(hw);
4853 /* Disable any previous flow control settings */
4854 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4855 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4857 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4858 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4860 switch (hw->fc.current_mode) {
4863 * If the count of enabled RX Priority Flow control >1,
4864 * and the TX pause can not be disabled
4867 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4868 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4869 if (reg & IXGBE_FCRTH_FCEN)
4873 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4875 case ixgbe_fc_rx_pause:
4877 * Rx Flow control is enabled and Tx Flow control is
4878 * disabled by software override. Since there really
4879 * isn't a way to advertise that we are capable of RX
4880 * Pause ONLY, we will advertise that we support both
4881 * symmetric and asymmetric Rx PAUSE. Later, we will
4882 * disable the adapter's ability to send PAUSE frames.
4884 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4886 * If the count of enabled RX Priority Flow control >1,
4887 * and the TX pause can not be disabled
4890 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4891 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4892 if (reg & IXGBE_FCRTH_FCEN)
4896 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4898 case ixgbe_fc_tx_pause:
4900 * Tx Flow control is enabled, and Rx Flow control is
4901 * disabled by software override.
4903 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4906 /* Flow control (both Rx and Tx) is enabled by SW override. */
4907 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4908 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4911 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4912 ret_val = IXGBE_ERR_CONFIG;
4916 /* Set 802.3x based flow control settings. */
4917 mflcn_reg |= IXGBE_MFLCN_DPF;
4918 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4919 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4921 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4922 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4923 hw->fc.high_water[tc_num]) {
4924 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4925 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4926 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4928 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4930 * In order to prevent Tx hangs when the internal Tx
4931 * switch is enabled we must set the high water mark
4932 * to the maximum FCRTH value. This allows the Tx
4933 * switch to function even under heavy Rx workloads.
4935 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4937 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4939 /* Configure pause time (2 TCs per register) */
4940 reg = hw->fc.pause_time * 0x00010001;
4941 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4942 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4944 /* Configure flow control refresh threshold value */
4945 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4952 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4954 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4957 if (hw->mac.type != ixgbe_mac_82598EB) {
4958 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4964 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4967 uint32_t rx_buf_size;
4968 uint32_t max_high_water;
4970 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4971 struct ixgbe_hw *hw =
4972 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4973 struct ixgbe_dcb_config *dcb_config =
4974 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4976 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4983 PMD_INIT_FUNC_TRACE();
4985 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4986 tc_num = map[pfc_conf->priority];
4987 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4988 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4990 * At least reserve one Ethernet frame for watermark
4991 * high_water/low_water in kilo bytes for ixgbe
4993 max_high_water = (rx_buf_size -
4994 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4995 if ((pfc_conf->fc.high_water > max_high_water) ||
4996 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4997 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4998 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5002 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5003 hw->fc.pause_time = pfc_conf->fc.pause_time;
5004 hw->fc.send_xon = pfc_conf->fc.send_xon;
5005 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
5006 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5008 err = ixgbe_dcb_pfc_enable(dev, tc_num);
5010 /* Not negotiated is not an error case */
5011 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5014 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5019 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5020 struct rte_eth_rss_reta_entry64 *reta_conf,
5023 uint16_t i, sp_reta_size;
5026 uint16_t idx, shift;
5027 struct ixgbe_adapter *adapter = dev->data->dev_private;
5028 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5031 PMD_INIT_FUNC_TRACE();
5033 if (!ixgbe_rss_update_sp(hw->mac.type)) {
5034 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5039 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5040 if (reta_size != sp_reta_size) {
5041 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5042 "(%d) doesn't match the number hardware can supported "
5043 "(%d)", reta_size, sp_reta_size);
5047 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5048 idx = i / RTE_RETA_GROUP_SIZE;
5049 shift = i % RTE_RETA_GROUP_SIZE;
5050 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5054 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5055 if (mask == IXGBE_4_BIT_MASK)
5058 r = IXGBE_READ_REG(hw, reta_reg);
5059 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5060 if (mask & (0x1 << j))
5061 reta |= reta_conf[idx].reta[shift + j] <<
5064 reta |= r & (IXGBE_8_BIT_MASK <<
5067 IXGBE_WRITE_REG(hw, reta_reg, reta);
5069 adapter->rss_reta_updated = 1;
5075 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5076 struct rte_eth_rss_reta_entry64 *reta_conf,
5079 uint16_t i, sp_reta_size;
5082 uint16_t idx, shift;
5083 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5086 PMD_INIT_FUNC_TRACE();
5087 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5088 if (reta_size != sp_reta_size) {
5089 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5090 "(%d) doesn't match the number hardware can supported "
5091 "(%d)", reta_size, sp_reta_size);
5095 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5096 idx = i / RTE_RETA_GROUP_SIZE;
5097 shift = i % RTE_RETA_GROUP_SIZE;
5098 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5103 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5104 reta = IXGBE_READ_REG(hw, reta_reg);
5105 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5106 if (mask & (0x1 << j))
5107 reta_conf[idx].reta[shift + j] =
5108 ((reta >> (CHAR_BIT * j)) &
5117 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5118 uint32_t index, uint32_t pool)
5120 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5121 uint32_t enable_addr = 1;
5123 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5128 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5130 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5132 ixgbe_clear_rar(hw, index);
5136 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5138 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5140 ixgbe_remove_rar(dev, 0);
5141 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5147 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5149 if (strcmp(dev->device->driver->name, drv->driver.name))
5156 is_ixgbe_supported(struct rte_eth_dev *dev)
5158 return is_device_supported(dev, &rte_ixgbe_pmd);
5162 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5166 struct ixgbe_hw *hw;
5167 struct rte_eth_dev_info dev_info;
5168 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5169 struct rte_eth_dev_data *dev_data = dev->data;
5172 ret = ixgbe_dev_info_get(dev, &dev_info);
5176 /* check that mtu is within the allowed range */
5177 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5180 /* If device is started, refuse mtu that requires the support of
5181 * scattered packets when this feature has not been enabled before.
5183 if (dev_data->dev_started && !dev_data->scattered_rx &&
5184 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5185 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5186 PMD_INIT_LOG(ERR, "Stop port first.");
5190 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5191 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5193 /* switch to jumbo mode if needed */
5194 if (frame_size > RTE_ETHER_MAX_LEN) {
5195 dev->data->dev_conf.rxmode.offloads |=
5196 DEV_RX_OFFLOAD_JUMBO_FRAME;
5197 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5199 dev->data->dev_conf.rxmode.offloads &=
5200 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5201 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5203 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5205 /* update max frame size */
5206 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5208 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5209 maxfrs &= 0x0000FFFF;
5210 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5211 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5217 * Virtual Function operations
5220 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5222 struct ixgbe_interrupt *intr =
5223 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5224 struct ixgbe_hw *hw =
5225 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5227 PMD_INIT_FUNC_TRACE();
5229 /* Clear interrupt mask to stop from interrupts being generated */
5230 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5232 IXGBE_WRITE_FLUSH(hw);
5234 /* Clear mask value. */
5239 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5241 struct ixgbe_interrupt *intr =
5242 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5243 struct ixgbe_hw *hw =
5244 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5246 PMD_INIT_FUNC_TRACE();
5248 /* VF enable interrupt autoclean */
5249 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5250 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5251 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5253 IXGBE_WRITE_FLUSH(hw);
5255 /* Save IXGBE_VTEIMS value to mask. */
5256 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5260 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5262 struct rte_eth_conf *conf = &dev->data->dev_conf;
5263 struct ixgbe_adapter *adapter = dev->data->dev_private;
5265 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5266 dev->data->port_id);
5268 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5269 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5272 * VF has no ability to enable/disable HW CRC
5273 * Keep the persistent behavior the same as Host PF
5275 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5276 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5277 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5278 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5281 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5282 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5283 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5288 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5289 * allocation or vector Rx preconditions we will reset it.
5291 adapter->rx_bulk_alloc_allowed = true;
5292 adapter->rx_vec_allowed = true;
5298 ixgbevf_dev_start(struct rte_eth_dev *dev)
5300 struct ixgbe_hw *hw =
5301 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5302 uint32_t intr_vector = 0;
5303 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5304 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5308 PMD_INIT_FUNC_TRACE();
5310 /* Stop the link setup handler before resetting the HW. */
5311 ixgbe_dev_wait_setup_link_complete(dev, 0);
5313 err = hw->mac.ops.reset_hw(hw);
5316 * In this case, reuses the MAC address assigned by VF
5319 if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5320 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5324 hw->mac.get_link_status = true;
5326 /* negotiate mailbox API version to use with the PF. */
5327 ixgbevf_negotiate_api(hw);
5329 ixgbevf_dev_tx_init(dev);
5331 /* This can fail when allocating mbufs for descriptor rings */
5332 err = ixgbevf_dev_rx_init(dev);
5334 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5335 ixgbe_dev_clear_queues(dev);
5340 ixgbevf_set_vfta_all(dev, 1);
5343 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5344 ETH_VLAN_EXTEND_MASK;
5345 err = ixgbevf_vlan_offload_config(dev, mask);
5347 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5348 ixgbe_dev_clear_queues(dev);
5352 ixgbevf_dev_rxtx_start(dev);
5354 /* check and configure queue intr-vector mapping */
5355 if (rte_intr_cap_multiple(intr_handle) &&
5356 dev->data->dev_conf.intr_conf.rxq) {
5357 /* According to datasheet, only vector 0/1/2 can be used,
5358 * now only one vector is used for Rx queue
5361 if (rte_intr_efd_enable(intr_handle, intr_vector))
5365 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5366 intr_handle->intr_vec =
5367 rte_zmalloc("intr_vec",
5368 dev->data->nb_rx_queues * sizeof(int), 0);
5369 if (intr_handle->intr_vec == NULL) {
5370 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5371 " intr_vec", dev->data->nb_rx_queues);
5375 ixgbevf_configure_msix(dev);
5377 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5378 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5379 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5380 * is not cleared, it will fail when following rte_intr_enable( ) tries
5381 * to map Rx queue interrupt to other VFIO vectors.
5382 * So clear uio/vfio intr/evevnfd first to avoid failure.
5384 rte_intr_disable(intr_handle);
5386 rte_intr_enable(intr_handle);
5388 /* Re-enable interrupt for VF */
5389 ixgbevf_intr_enable(dev);
5392 * Update link status right before return, because it may
5393 * start link configuration process in a separate thread.
5395 ixgbevf_dev_link_update(dev, 0);
5397 hw->adapter_stopped = false;
5403 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5405 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5406 struct ixgbe_adapter *adapter = dev->data->dev_private;
5407 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5408 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5410 if (hw->adapter_stopped)
5413 PMD_INIT_FUNC_TRACE();
5415 ixgbe_dev_wait_setup_link_complete(dev, 0);
5417 ixgbevf_intr_disable(dev);
5419 dev->data->dev_started = 0;
5420 hw->adapter_stopped = 1;
5421 ixgbe_stop_adapter(hw);
5424 * Clear what we set, but we still keep shadow_vfta to
5425 * restore after device starts
5427 ixgbevf_set_vfta_all(dev, 0);
5429 /* Clear stored conf */
5430 dev->data->scattered_rx = 0;
5432 ixgbe_dev_clear_queues(dev);
5434 /* Clean datapath event and queue/vec mapping */
5435 rte_intr_efd_disable(intr_handle);
5436 if (intr_handle->intr_vec != NULL) {
5437 rte_free(intr_handle->intr_vec);
5438 intr_handle->intr_vec = NULL;
5441 adapter->rss_reta_updated = 0;
5447 ixgbevf_dev_close(struct rte_eth_dev *dev)
5449 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5450 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5451 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5454 PMD_INIT_FUNC_TRACE();
5455 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5460 ret = ixgbevf_dev_stop(dev);
5462 ixgbe_dev_free_queues(dev);
5465 * Remove the VF MAC address ro ensure
5466 * that the VF traffic goes to the PF
5467 * after stop, close and detach of the VF
5469 ixgbevf_remove_mac_addr(dev, 0);
5471 rte_intr_disable(intr_handle);
5472 rte_intr_callback_unregister(intr_handle,
5473 ixgbevf_dev_interrupt_handler, dev);
5482 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5486 ret = eth_ixgbevf_dev_uninit(dev);
5490 ret = eth_ixgbevf_dev_init(dev);
5495 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5497 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5498 struct ixgbe_vfta *shadow_vfta =
5499 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5500 int i = 0, j = 0, vfta = 0, mask = 1;
5502 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5503 vfta = shadow_vfta->vfta[i];
5506 for (j = 0; j < 32; j++) {
5508 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5518 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5520 struct ixgbe_hw *hw =
5521 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5522 struct ixgbe_vfta *shadow_vfta =
5523 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5524 uint32_t vid_idx = 0;
5525 uint32_t vid_bit = 0;
5528 PMD_INIT_FUNC_TRACE();
5530 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5531 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5533 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5536 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5537 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5539 /* Save what we set and retore it after device reset */
5541 shadow_vfta->vfta[vid_idx] |= vid_bit;
5543 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5549 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5551 struct ixgbe_hw *hw =
5552 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5555 PMD_INIT_FUNC_TRACE();
5557 if (queue >= hw->mac.max_rx_queues)
5560 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5562 ctrl |= IXGBE_RXDCTL_VME;
5564 ctrl &= ~IXGBE_RXDCTL_VME;
5565 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5567 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5571 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5573 struct ixgbe_rx_queue *rxq;
5577 /* VF function only support hw strip feature, others are not support */
5578 if (mask & ETH_VLAN_STRIP_MASK) {
5579 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5580 rxq = dev->data->rx_queues[i];
5581 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5582 ixgbevf_vlan_strip_queue_set(dev, i, on);
5590 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5592 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5594 ixgbevf_vlan_offload_config(dev, mask);
5600 ixgbe_vt_check(struct ixgbe_hw *hw)
5604 /* if Virtualization Technology is enabled */
5605 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5606 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5607 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5615 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5617 uint32_t vector = 0;
5619 switch (hw->mac.mc_filter_type) {
5620 case 0: /* use bits [47:36] of the address */
5621 vector = ((uc_addr->addr_bytes[4] >> 4) |
5622 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5624 case 1: /* use bits [46:35] of the address */
5625 vector = ((uc_addr->addr_bytes[4] >> 3) |
5626 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5628 case 2: /* use bits [45:34] of the address */
5629 vector = ((uc_addr->addr_bytes[4] >> 2) |
5630 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5632 case 3: /* use bits [43:32] of the address */
5633 vector = ((uc_addr->addr_bytes[4]) |
5634 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5636 default: /* Invalid mc_filter_type */
5640 /* vector can only be 12-bits or boundary will be exceeded */
5646 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5647 struct rte_ether_addr *mac_addr, uint8_t on)
5654 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5655 const uint32_t ixgbe_uta_bit_shift = 5;
5656 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5657 const uint32_t bit1 = 0x1;
5659 struct ixgbe_hw *hw =
5660 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5661 struct ixgbe_uta_info *uta_info =
5662 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5664 /* The UTA table only exists on 82599 hardware and newer */
5665 if (hw->mac.type < ixgbe_mac_82599EB)
5668 vector = ixgbe_uta_vector(hw, mac_addr);
5669 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5670 uta_shift = vector & ixgbe_uta_bit_mask;
5672 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5676 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5678 uta_info->uta_in_use++;
5679 reg_val |= (bit1 << uta_shift);
5680 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5682 uta_info->uta_in_use--;
5683 reg_val &= ~(bit1 << uta_shift);
5684 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5687 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5689 if (uta_info->uta_in_use > 0)
5690 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5691 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5693 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5699 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5702 struct ixgbe_hw *hw =
5703 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5704 struct ixgbe_uta_info *uta_info =
5705 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5707 /* The UTA table only exists on 82599 hardware and newer */
5708 if (hw->mac.type < ixgbe_mac_82599EB)
5712 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5713 uta_info->uta_shadow[i] = ~0;
5714 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5717 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5718 uta_info->uta_shadow[i] = 0;
5719 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5727 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5729 uint32_t new_val = orig_val;
5731 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5732 new_val |= IXGBE_VMOLR_AUPE;
5733 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5734 new_val |= IXGBE_VMOLR_ROMPE;
5735 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5736 new_val |= IXGBE_VMOLR_ROPE;
5737 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5738 new_val |= IXGBE_VMOLR_BAM;
5739 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5740 new_val |= IXGBE_VMOLR_MPE;
5745 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5746 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5747 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5748 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5749 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5750 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5751 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5754 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5755 struct rte_eth_mirror_conf *mirror_conf,
5756 uint8_t rule_id, uint8_t on)
5758 uint32_t mr_ctl, vlvf;
5759 uint32_t mp_lsb = 0;
5760 uint32_t mv_msb = 0;
5761 uint32_t mv_lsb = 0;
5762 uint32_t mp_msb = 0;
5765 uint64_t vlan_mask = 0;
5767 const uint8_t pool_mask_offset = 32;
5768 const uint8_t vlan_mask_offset = 32;
5769 const uint8_t dst_pool_offset = 8;
5770 const uint8_t rule_mr_offset = 4;
5771 const uint8_t mirror_rule_mask = 0x0F;
5773 struct ixgbe_mirror_info *mr_info =
5774 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5775 struct ixgbe_hw *hw =
5776 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5777 uint8_t mirror_type = 0;
5779 if (ixgbe_vt_check(hw) < 0)
5782 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5785 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5786 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5787 mirror_conf->rule_type);
5791 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5792 mirror_type |= IXGBE_MRCTL_VLME;
5793 /* Check if vlan id is valid and find conresponding VLAN ID
5796 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5797 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5798 /* search vlan id related pool vlan filter
5801 reg_index = ixgbe_find_vlvf_slot(
5803 mirror_conf->vlan.vlan_id[i],
5807 vlvf = IXGBE_READ_REG(hw,
5808 IXGBE_VLVF(reg_index));
5809 if ((vlvf & IXGBE_VLVF_VIEN) &&
5810 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5811 mirror_conf->vlan.vlan_id[i]))
5812 vlan_mask |= (1ULL << reg_index);
5819 mv_lsb = vlan_mask & 0xFFFFFFFF;
5820 mv_msb = vlan_mask >> vlan_mask_offset;
5822 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5823 mirror_conf->vlan.vlan_mask;
5824 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5825 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5826 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5827 mirror_conf->vlan.vlan_id[i];
5832 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5833 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5834 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5839 * if enable pool mirror, write related pool mask register,if disable
5840 * pool mirror, clear PFMRVM register
5842 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5843 mirror_type |= IXGBE_MRCTL_VPME;
5845 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5846 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5847 mr_info->mr_conf[rule_id].pool_mask =
5848 mirror_conf->pool_mask;
5853 mr_info->mr_conf[rule_id].pool_mask = 0;
5856 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5857 mirror_type |= IXGBE_MRCTL_UPME;
5858 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5859 mirror_type |= IXGBE_MRCTL_DPME;
5861 /* read mirror control register and recalculate it */
5862 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5865 mr_ctl |= mirror_type;
5866 mr_ctl &= mirror_rule_mask;
5867 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5869 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5872 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5873 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5875 /* write mirrror control register */
5876 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5878 /* write pool mirrror control register */
5879 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5880 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5881 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5884 /* write VLAN mirrror control register */
5885 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5886 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5887 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5895 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5898 uint32_t lsb_val = 0;
5899 uint32_t msb_val = 0;
5900 const uint8_t rule_mr_offset = 4;
5902 struct ixgbe_hw *hw =
5903 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5904 struct ixgbe_mirror_info *mr_info =
5905 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5907 if (ixgbe_vt_check(hw) < 0)
5910 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5913 memset(&mr_info->mr_conf[rule_id], 0,
5914 sizeof(struct rte_eth_mirror_conf));
5916 /* clear PFVMCTL register */
5917 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5919 /* clear pool mask register */
5920 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5921 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5923 /* clear vlan mask register */
5924 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5925 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5931 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5933 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5934 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5935 struct ixgbe_interrupt *intr =
5936 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5937 struct ixgbe_hw *hw =
5938 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5939 uint32_t vec = IXGBE_MISC_VEC_ID;
5941 if (rte_intr_allow_others(intr_handle))
5942 vec = IXGBE_RX_VEC_START;
5943 intr->mask |= (1 << vec);
5944 RTE_SET_USED(queue_id);
5945 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5947 rte_intr_ack(intr_handle);
5953 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5955 struct ixgbe_interrupt *intr =
5956 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5957 struct ixgbe_hw *hw =
5958 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5959 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5960 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5961 uint32_t vec = IXGBE_MISC_VEC_ID;
5963 if (rte_intr_allow_others(intr_handle))
5964 vec = IXGBE_RX_VEC_START;
5965 intr->mask &= ~(1 << vec);
5966 RTE_SET_USED(queue_id);
5967 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5973 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5975 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5976 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5978 struct ixgbe_hw *hw =
5979 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5980 struct ixgbe_interrupt *intr =
5981 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5983 if (queue_id < 16) {
5984 ixgbe_disable_intr(hw);
5985 intr->mask |= (1 << queue_id);
5986 ixgbe_enable_intr(dev);
5987 } else if (queue_id < 32) {
5988 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5989 mask &= (1 << queue_id);
5990 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5991 } else if (queue_id < 64) {
5992 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5993 mask &= (1 << (queue_id - 32));
5994 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5996 rte_intr_ack(intr_handle);
6002 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6005 struct ixgbe_hw *hw =
6006 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6007 struct ixgbe_interrupt *intr =
6008 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6010 if (queue_id < 16) {
6011 ixgbe_disable_intr(hw);
6012 intr->mask &= ~(1 << queue_id);
6013 ixgbe_enable_intr(dev);
6014 } else if (queue_id < 32) {
6015 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6016 mask &= ~(1 << queue_id);
6017 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6018 } else if (queue_id < 64) {
6019 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6020 mask &= ~(1 << (queue_id - 32));
6021 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6028 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6029 uint8_t queue, uint8_t msix_vector)
6033 if (direction == -1) {
6035 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6036 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6039 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6041 /* rx or tx cause */
6042 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6043 idx = ((16 * (queue & 1)) + (8 * direction));
6044 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6045 tmp &= ~(0xFF << idx);
6046 tmp |= (msix_vector << idx);
6047 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6052 * set the IVAR registers, mapping interrupt causes to vectors
6054 * pointer to ixgbe_hw struct
6056 * 0 for Rx, 1 for Tx, -1 for other causes
6058 * queue to map the corresponding interrupt to
6060 * the vector to map to the corresponding queue
6063 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6064 uint8_t queue, uint8_t msix_vector)
6068 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6069 if (hw->mac.type == ixgbe_mac_82598EB) {
6070 if (direction == -1)
6072 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6073 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6074 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6075 tmp |= (msix_vector << (8 * (queue & 0x3)));
6076 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6077 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6078 (hw->mac.type == ixgbe_mac_X540) ||
6079 (hw->mac.type == ixgbe_mac_X550) ||
6080 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6081 if (direction == -1) {
6083 idx = ((queue & 1) * 8);
6084 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6085 tmp &= ~(0xFF << idx);
6086 tmp |= (msix_vector << idx);
6087 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6089 /* rx or tx causes */
6090 idx = ((16 * (queue & 1)) + (8 * direction));
6091 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6092 tmp &= ~(0xFF << idx);
6093 tmp |= (msix_vector << idx);
6094 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6100 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6102 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6103 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6104 struct ixgbe_hw *hw =
6105 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6107 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6108 uint32_t base = IXGBE_MISC_VEC_ID;
6110 /* Configure VF other cause ivar */
6111 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6113 /* won't configure msix register if no mapping is done
6114 * between intr vector and event fd.
6116 if (!rte_intr_dp_is_en(intr_handle))
6119 if (rte_intr_allow_others(intr_handle)) {
6120 base = IXGBE_RX_VEC_START;
6121 vector_idx = IXGBE_RX_VEC_START;
6124 /* Configure all RX queues of VF */
6125 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6126 /* Force all queue use vector 0,
6127 * as IXGBE_VF_MAXMSIVECOTR = 1
6129 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6130 intr_handle->intr_vec[q_idx] = vector_idx;
6131 if (vector_idx < base + intr_handle->nb_efd - 1)
6135 /* As RX queue setting above show, all queues use the vector 0.
6136 * Set only the ITR value of IXGBE_MISC_VEC_ID.
6138 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6139 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6140 | IXGBE_EITR_CNT_WDIS);
6144 * Sets up the hardware to properly generate MSI-X interrupts
6146 * board private structure
6149 ixgbe_configure_msix(struct rte_eth_dev *dev)
6151 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6152 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6153 struct ixgbe_hw *hw =
6154 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6155 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6156 uint32_t vec = IXGBE_MISC_VEC_ID;
6160 /* won't configure msix register if no mapping is done
6161 * between intr vector and event fd
6162 * but if misx has been enabled already, need to configure
6163 * auto clean, auto mask and throttling.
6165 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6166 if (!rte_intr_dp_is_en(intr_handle) &&
6167 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6170 if (rte_intr_allow_others(intr_handle))
6171 vec = base = IXGBE_RX_VEC_START;
6173 /* setup GPIE for MSI-x mode */
6174 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6175 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6176 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6177 /* auto clearing and auto setting corresponding bits in EIMS
6178 * when MSI-X interrupt is triggered
6180 if (hw->mac.type == ixgbe_mac_82598EB) {
6181 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6183 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6184 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6186 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6188 /* Populate the IVAR table and set the ITR values to the
6189 * corresponding register.
6191 if (rte_intr_dp_is_en(intr_handle)) {
6192 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6194 /* by default, 1:1 mapping */
6195 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6196 intr_handle->intr_vec[queue_id] = vec;
6197 if (vec < base + intr_handle->nb_efd - 1)
6201 switch (hw->mac.type) {
6202 case ixgbe_mac_82598EB:
6203 ixgbe_set_ivar_map(hw, -1,
6204 IXGBE_IVAR_OTHER_CAUSES_INDEX,
6207 case ixgbe_mac_82599EB:
6208 case ixgbe_mac_X540:
6209 case ixgbe_mac_X550:
6210 case ixgbe_mac_X550EM_x:
6211 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6217 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6218 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6219 | IXGBE_EITR_CNT_WDIS);
6221 /* set up to autoclear timer, and the vectors */
6222 mask = IXGBE_EIMS_ENABLE_MASK;
6223 mask &= ~(IXGBE_EIMS_OTHER |
6224 IXGBE_EIMS_MAILBOX |
6227 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6231 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6232 uint16_t queue_idx, uint16_t tx_rate)
6234 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6235 struct rte_eth_rxmode *rxmode;
6236 uint32_t rf_dec, rf_int;
6238 uint16_t link_speed = dev->data->dev_link.link_speed;
6240 if (queue_idx >= hw->mac.max_tx_queues)
6244 /* Calculate the rate factor values to set */
6245 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6246 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6247 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6249 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6250 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6251 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6252 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6257 rxmode = &dev->data->dev_conf.rxmode;
6259 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6260 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6263 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6264 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6265 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6266 IXGBE_MMW_SIZE_JUMBO_FRAME);
6268 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6269 IXGBE_MMW_SIZE_DEFAULT);
6271 /* Set RTTBCNRC of queue X */
6272 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6273 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6274 IXGBE_WRITE_FLUSH(hw);
6280 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6281 __rte_unused uint32_t index,
6282 __rte_unused uint32_t pool)
6284 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6288 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6289 * operation. Trap this case to avoid exhausting the [very limited]
6290 * set of PF resources used to store VF MAC addresses.
6292 if (memcmp(hw->mac.perm_addr, mac_addr,
6293 sizeof(struct rte_ether_addr)) == 0)
6295 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6297 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6298 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6299 mac_addr->addr_bytes[0],
6300 mac_addr->addr_bytes[1],
6301 mac_addr->addr_bytes[2],
6302 mac_addr->addr_bytes[3],
6303 mac_addr->addr_bytes[4],
6304 mac_addr->addr_bytes[5],
6310 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6312 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6313 struct rte_ether_addr *perm_addr =
6314 (struct rte_ether_addr *)hw->mac.perm_addr;
6315 struct rte_ether_addr *mac_addr;
6320 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6321 * not support the deletion of a given MAC address.
6322 * Instead, it imposes to delete all MAC addresses, then to add again
6323 * all MAC addresses with the exception of the one to be deleted.
6325 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6328 * Add again all MAC addresses, with the exception of the deleted one
6329 * and of the permanent MAC address.
6331 for (i = 0, mac_addr = dev->data->mac_addrs;
6332 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6333 /* Skip the deleted MAC address */
6336 /* Skip NULL MAC addresses */
6337 if (rte_is_zero_ether_addr(mac_addr))
6339 /* Skip the permanent MAC address */
6340 if (memcmp(perm_addr, mac_addr,
6341 sizeof(struct rte_ether_addr)) == 0)
6343 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6346 "Adding again MAC address "
6347 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6349 mac_addr->addr_bytes[0],
6350 mac_addr->addr_bytes[1],
6351 mac_addr->addr_bytes[2],
6352 mac_addr->addr_bytes[3],
6353 mac_addr->addr_bytes[4],
6354 mac_addr->addr_bytes[5],
6360 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6361 struct rte_ether_addr *addr)
6363 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6365 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6371 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6372 struct rte_eth_syn_filter *filter,
6375 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6376 struct ixgbe_filter_info *filter_info =
6377 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6381 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6384 syn_info = filter_info->syn_info;
6387 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6389 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6390 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6392 if (filter->hig_pri)
6393 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6395 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6397 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6398 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6400 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6403 filter_info->syn_info = synqf;
6404 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6405 IXGBE_WRITE_FLUSH(hw);
6410 static inline enum ixgbe_5tuple_protocol
6411 convert_protocol_type(uint8_t protocol_value)
6413 if (protocol_value == IPPROTO_TCP)
6414 return IXGBE_FILTER_PROTOCOL_TCP;
6415 else if (protocol_value == IPPROTO_UDP)
6416 return IXGBE_FILTER_PROTOCOL_UDP;
6417 else if (protocol_value == IPPROTO_SCTP)
6418 return IXGBE_FILTER_PROTOCOL_SCTP;
6420 return IXGBE_FILTER_PROTOCOL_NONE;
6423 /* inject a 5-tuple filter to HW */
6425 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6426 struct ixgbe_5tuple_filter *filter)
6428 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6430 uint32_t ftqf, sdpqf;
6431 uint32_t l34timir = 0;
6432 uint8_t mask = 0xff;
6436 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6437 IXGBE_SDPQF_DSTPORT_SHIFT);
6438 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6440 ftqf = (uint32_t)(filter->filter_info.proto &
6441 IXGBE_FTQF_PROTOCOL_MASK);
6442 ftqf |= (uint32_t)((filter->filter_info.priority &
6443 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6444 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6445 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6446 if (filter->filter_info.dst_ip_mask == 0)
6447 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6448 if (filter->filter_info.src_port_mask == 0)
6449 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6450 if (filter->filter_info.dst_port_mask == 0)
6451 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6452 if (filter->filter_info.proto_mask == 0)
6453 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6454 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6455 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6456 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6458 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6459 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6460 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6461 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6463 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6464 l34timir |= (uint32_t)(filter->queue <<
6465 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6466 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6470 * add a 5tuple filter
6473 * dev: Pointer to struct rte_eth_dev.
6474 * index: the index the filter allocates.
6475 * filter: ponter to the filter that will be added.
6476 * rx_queue: the queue id the filter assigned to.
6479 * - On success, zero.
6480 * - On failure, a negative value.
6483 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6484 struct ixgbe_5tuple_filter *filter)
6486 struct ixgbe_filter_info *filter_info =
6487 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6491 * look for an unused 5tuple filter index,
6492 * and insert the filter to list.
6494 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6495 idx = i / (sizeof(uint32_t) * NBBY);
6496 shift = i % (sizeof(uint32_t) * NBBY);
6497 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6498 filter_info->fivetuple_mask[idx] |= 1 << shift;
6500 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6506 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6507 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6511 ixgbe_inject_5tuple_filter(dev, filter);
6517 * remove a 5tuple filter
6520 * dev: Pointer to struct rte_eth_dev.
6521 * filter: the pointer of the filter will be removed.
6524 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6525 struct ixgbe_5tuple_filter *filter)
6527 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6528 struct ixgbe_filter_info *filter_info =
6529 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6530 uint16_t index = filter->index;
6532 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6533 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6534 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6537 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6538 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6539 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6540 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6541 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6545 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6547 struct ixgbe_hw *hw;
6548 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6549 struct rte_eth_dev_data *dev_data = dev->data;
6551 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6553 if (mtu < RTE_ETHER_MIN_MTU ||
6554 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6557 /* If device is started, refuse mtu that requires the support of
6558 * scattered packets when this feature has not been enabled before.
6560 if (dev_data->dev_started && !dev_data->scattered_rx &&
6561 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6562 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6563 PMD_INIT_LOG(ERR, "Stop port first.");
6568 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6569 * request of the version 2.0 of the mailbox API.
6570 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6571 * of the mailbox API.
6572 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6573 * prior to 3.11.33 which contains the following change:
6574 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6576 ixgbevf_rlpml_set_vf(hw, max_frame);
6578 /* update max frame size */
6579 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6583 static inline struct ixgbe_5tuple_filter *
6584 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6585 struct ixgbe_5tuple_filter_info *key)
6587 struct ixgbe_5tuple_filter *it;
6589 TAILQ_FOREACH(it, filter_list, entries) {
6590 if (memcmp(key, &it->filter_info,
6591 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6598 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6600 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6601 struct ixgbe_5tuple_filter_info *filter_info)
6603 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6604 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6605 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6608 switch (filter->dst_ip_mask) {
6610 filter_info->dst_ip_mask = 0;
6611 filter_info->dst_ip = filter->dst_ip;
6614 filter_info->dst_ip_mask = 1;
6617 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6621 switch (filter->src_ip_mask) {
6623 filter_info->src_ip_mask = 0;
6624 filter_info->src_ip = filter->src_ip;
6627 filter_info->src_ip_mask = 1;
6630 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6634 switch (filter->dst_port_mask) {
6636 filter_info->dst_port_mask = 0;
6637 filter_info->dst_port = filter->dst_port;
6640 filter_info->dst_port_mask = 1;
6643 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6647 switch (filter->src_port_mask) {
6649 filter_info->src_port_mask = 0;
6650 filter_info->src_port = filter->src_port;
6653 filter_info->src_port_mask = 1;
6656 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6660 switch (filter->proto_mask) {
6662 filter_info->proto_mask = 0;
6663 filter_info->proto =
6664 convert_protocol_type(filter->proto);
6667 filter_info->proto_mask = 1;
6670 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6674 filter_info->priority = (uint8_t)filter->priority;
6679 * add or delete a ntuple filter
6682 * dev: Pointer to struct rte_eth_dev.
6683 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6684 * add: if true, add filter, if false, remove filter
6687 * - On success, zero.
6688 * - On failure, a negative value.
6691 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6692 struct rte_eth_ntuple_filter *ntuple_filter,
6695 struct ixgbe_filter_info *filter_info =
6696 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6697 struct ixgbe_5tuple_filter_info filter_5tuple;
6698 struct ixgbe_5tuple_filter *filter;
6701 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6702 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6706 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6707 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6711 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6713 if (filter != NULL && add) {
6714 PMD_DRV_LOG(ERR, "filter exists.");
6717 if (filter == NULL && !add) {
6718 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6723 filter = rte_zmalloc("ixgbe_5tuple_filter",
6724 sizeof(struct ixgbe_5tuple_filter), 0);
6727 rte_memcpy(&filter->filter_info,
6729 sizeof(struct ixgbe_5tuple_filter_info));
6730 filter->queue = ntuple_filter->queue;
6731 ret = ixgbe_add_5tuple_filter(dev, filter);
6737 ixgbe_remove_5tuple_filter(dev, filter);
6743 * get a ntuple filter
6746 * dev: Pointer to struct rte_eth_dev.
6747 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6750 * - On success, zero.
6751 * - On failure, a negative value.
6754 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6755 struct rte_eth_ntuple_filter *ntuple_filter)
6757 struct ixgbe_filter_info *filter_info =
6758 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6759 struct ixgbe_5tuple_filter_info filter_5tuple;
6760 struct ixgbe_5tuple_filter *filter;
6763 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6764 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6768 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6769 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6773 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6775 if (filter == NULL) {
6776 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6779 ntuple_filter->queue = filter->queue;
6784 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6785 * @dev: pointer to rte_eth_dev structure
6786 * @filter_op:operation will be taken.
6787 * @arg: a pointer to specific structure corresponding to the filter_op
6790 * - On success, zero.
6791 * - On failure, a negative value.
6794 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6795 enum rte_filter_op filter_op,
6798 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6801 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6803 if (filter_op == RTE_ETH_FILTER_NOP)
6807 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6812 switch (filter_op) {
6813 case RTE_ETH_FILTER_ADD:
6814 ret = ixgbe_add_del_ntuple_filter(dev,
6815 (struct rte_eth_ntuple_filter *)arg,
6818 case RTE_ETH_FILTER_DELETE:
6819 ret = ixgbe_add_del_ntuple_filter(dev,
6820 (struct rte_eth_ntuple_filter *)arg,
6823 case RTE_ETH_FILTER_GET:
6824 ret = ixgbe_get_ntuple_filter(dev,
6825 (struct rte_eth_ntuple_filter *)arg);
6828 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6836 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6837 struct rte_eth_ethertype_filter *filter,
6840 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6841 struct ixgbe_filter_info *filter_info =
6842 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6846 struct ixgbe_ethertype_filter ethertype_filter;
6848 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6851 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6852 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6853 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6854 " ethertype filter.", filter->ether_type);
6858 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6859 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6862 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6863 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6867 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6868 if (ret >= 0 && add) {
6869 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6870 filter->ether_type);
6873 if (ret < 0 && !add) {
6874 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6875 filter->ether_type);
6880 etqf = IXGBE_ETQF_FILTER_EN;
6881 etqf |= (uint32_t)filter->ether_type;
6882 etqs |= (uint32_t)((filter->queue <<
6883 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6884 IXGBE_ETQS_RX_QUEUE);
6885 etqs |= IXGBE_ETQS_QUEUE_EN;
6887 ethertype_filter.ethertype = filter->ether_type;
6888 ethertype_filter.etqf = etqf;
6889 ethertype_filter.etqs = etqs;
6890 ethertype_filter.conf = FALSE;
6891 ret = ixgbe_ethertype_filter_insert(filter_info,
6894 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6898 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6902 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6903 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6904 IXGBE_WRITE_FLUSH(hw);
6910 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6911 enum rte_filter_type filter_type,
6912 enum rte_filter_op filter_op,
6917 switch (filter_type) {
6918 case RTE_ETH_FILTER_NTUPLE:
6919 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6921 case RTE_ETH_FILTER_FDIR:
6922 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6924 case RTE_ETH_FILTER_L2_TUNNEL:
6925 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6927 case RTE_ETH_FILTER_GENERIC:
6928 if (filter_op != RTE_ETH_FILTER_GET)
6930 *(const void **)arg = &ixgbe_flow_ops;
6933 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6943 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6944 u8 **mc_addr_ptr, u32 *vmdq)
6949 mc_addr = *mc_addr_ptr;
6950 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6955 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6956 struct rte_ether_addr *mc_addr_set,
6957 uint32_t nb_mc_addr)
6959 struct ixgbe_hw *hw;
6962 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6963 mc_addr_list = (u8 *)mc_addr_set;
6964 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6965 ixgbe_dev_addr_list_itr, TRUE);
6969 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6971 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6972 uint64_t systime_cycles;
6974 switch (hw->mac.type) {
6975 case ixgbe_mac_X550:
6976 case ixgbe_mac_X550EM_x:
6977 case ixgbe_mac_X550EM_a:
6978 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6979 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6980 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6984 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6985 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6989 return systime_cycles;
6993 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6995 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6996 uint64_t rx_tstamp_cycles;
6998 switch (hw->mac.type) {
6999 case ixgbe_mac_X550:
7000 case ixgbe_mac_X550EM_x:
7001 case ixgbe_mac_X550EM_a:
7002 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7003 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7004 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7008 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7009 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7010 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7014 return rx_tstamp_cycles;
7018 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7020 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7021 uint64_t tx_tstamp_cycles;
7023 switch (hw->mac.type) {
7024 case ixgbe_mac_X550:
7025 case ixgbe_mac_X550EM_x:
7026 case ixgbe_mac_X550EM_a:
7027 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7028 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7029 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7033 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7034 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7035 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7039 return tx_tstamp_cycles;
7043 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7045 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7046 struct ixgbe_adapter *adapter = dev->data->dev_private;
7047 struct rte_eth_link link;
7048 uint32_t incval = 0;
7051 /* Get current link speed. */
7052 ixgbe_dev_link_update(dev, 1);
7053 rte_eth_linkstatus_get(dev, &link);
7055 switch (link.link_speed) {
7056 case ETH_SPEED_NUM_100M:
7057 incval = IXGBE_INCVAL_100;
7058 shift = IXGBE_INCVAL_SHIFT_100;
7060 case ETH_SPEED_NUM_1G:
7061 incval = IXGBE_INCVAL_1GB;
7062 shift = IXGBE_INCVAL_SHIFT_1GB;
7064 case ETH_SPEED_NUM_10G:
7066 incval = IXGBE_INCVAL_10GB;
7067 shift = IXGBE_INCVAL_SHIFT_10GB;
7071 switch (hw->mac.type) {
7072 case ixgbe_mac_X550:
7073 case ixgbe_mac_X550EM_x:
7074 case ixgbe_mac_X550EM_a:
7075 /* Independent of link speed. */
7077 /* Cycles read will be interpreted as ns. */
7080 case ixgbe_mac_X540:
7081 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7083 case ixgbe_mac_82599EB:
7084 incval >>= IXGBE_INCVAL_SHIFT_82599;
7085 shift -= IXGBE_INCVAL_SHIFT_82599;
7086 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7087 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7090 /* Not supported. */
7094 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7095 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7096 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7098 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7099 adapter->systime_tc.cc_shift = shift;
7100 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7102 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7103 adapter->rx_tstamp_tc.cc_shift = shift;
7104 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7106 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7107 adapter->tx_tstamp_tc.cc_shift = shift;
7108 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7112 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7114 struct ixgbe_adapter *adapter = dev->data->dev_private;
7116 adapter->systime_tc.nsec += delta;
7117 adapter->rx_tstamp_tc.nsec += delta;
7118 adapter->tx_tstamp_tc.nsec += delta;
7124 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7127 struct ixgbe_adapter *adapter = dev->data->dev_private;
7129 ns = rte_timespec_to_ns(ts);
7130 /* Set the timecounters to a new value. */
7131 adapter->systime_tc.nsec = ns;
7132 adapter->rx_tstamp_tc.nsec = ns;
7133 adapter->tx_tstamp_tc.nsec = ns;
7139 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7141 uint64_t ns, systime_cycles;
7142 struct ixgbe_adapter *adapter = dev->data->dev_private;
7144 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7145 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7146 *ts = rte_ns_to_timespec(ns);
7152 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7154 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7158 /* Stop the timesync system time. */
7159 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7160 /* Reset the timesync system time value. */
7161 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7162 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7164 /* Enable system time for platforms where it isn't on by default. */
7165 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7166 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7167 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7169 ixgbe_start_timecounters(dev);
7171 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7172 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7173 (RTE_ETHER_TYPE_1588 |
7174 IXGBE_ETQF_FILTER_EN |
7177 /* Enable timestamping of received PTP packets. */
7178 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7179 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7180 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7182 /* Enable timestamping of transmitted PTP packets. */
7183 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7184 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7185 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7187 IXGBE_WRITE_FLUSH(hw);
7193 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7195 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7198 /* Disable timestamping of transmitted PTP packets. */
7199 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7200 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7201 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7203 /* Disable timestamping of received PTP packets. */
7204 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7205 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7206 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7208 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7209 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7211 /* Stop incrementating the System Time registers. */
7212 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7218 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7219 struct timespec *timestamp,
7220 uint32_t flags __rte_unused)
7222 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7223 struct ixgbe_adapter *adapter = dev->data->dev_private;
7224 uint32_t tsync_rxctl;
7225 uint64_t rx_tstamp_cycles;
7228 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7229 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7232 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7233 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7234 *timestamp = rte_ns_to_timespec(ns);
7240 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7241 struct timespec *timestamp)
7243 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7244 struct ixgbe_adapter *adapter = dev->data->dev_private;
7245 uint32_t tsync_txctl;
7246 uint64_t tx_tstamp_cycles;
7249 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7250 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7253 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7254 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7255 *timestamp = rte_ns_to_timespec(ns);
7261 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7263 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7266 const struct reg_info *reg_group;
7267 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7268 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7270 while ((reg_group = reg_set[g_ind++]))
7271 count += ixgbe_regs_group_count(reg_group);
7277 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7281 const struct reg_info *reg_group;
7283 while ((reg_group = ixgbevf_regs[g_ind++]))
7284 count += ixgbe_regs_group_count(reg_group);
7290 ixgbe_get_regs(struct rte_eth_dev *dev,
7291 struct rte_dev_reg_info *regs)
7293 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7294 uint32_t *data = regs->data;
7297 const struct reg_info *reg_group;
7298 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7299 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7302 regs->length = ixgbe_get_reg_length(dev);
7303 regs->width = sizeof(uint32_t);
7307 /* Support only full register dump */
7308 if ((regs->length == 0) ||
7309 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7310 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7312 while ((reg_group = reg_set[g_ind++]))
7313 count += ixgbe_read_regs_group(dev, &data[count],
7322 ixgbevf_get_regs(struct rte_eth_dev *dev,
7323 struct rte_dev_reg_info *regs)
7325 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7326 uint32_t *data = regs->data;
7329 const struct reg_info *reg_group;
7332 regs->length = ixgbevf_get_reg_length(dev);
7333 regs->width = sizeof(uint32_t);
7337 /* Support only full register dump */
7338 if ((regs->length == 0) ||
7339 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7340 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7342 while ((reg_group = ixgbevf_regs[g_ind++]))
7343 count += ixgbe_read_regs_group(dev, &data[count],
7352 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7354 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7356 /* Return unit is byte count */
7357 return hw->eeprom.word_size * 2;
7361 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7362 struct rte_dev_eeprom_info *in_eeprom)
7364 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7365 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7366 uint16_t *data = in_eeprom->data;
7369 first = in_eeprom->offset >> 1;
7370 length = in_eeprom->length >> 1;
7371 if ((first > hw->eeprom.word_size) ||
7372 ((first + length) > hw->eeprom.word_size))
7375 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7377 return eeprom->ops.read_buffer(hw, first, length, data);
7381 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7382 struct rte_dev_eeprom_info *in_eeprom)
7384 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7385 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7386 uint16_t *data = in_eeprom->data;
7389 first = in_eeprom->offset >> 1;
7390 length = in_eeprom->length >> 1;
7391 if ((first > hw->eeprom.word_size) ||
7392 ((first + length) > hw->eeprom.word_size))
7395 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7397 return eeprom->ops.write_buffer(hw, first, length, data);
7401 ixgbe_get_module_info(struct rte_eth_dev *dev,
7402 struct rte_eth_dev_module_info *modinfo)
7404 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7406 uint8_t sff8472_rev, addr_mode;
7407 bool page_swap = false;
7409 /* Check whether we support SFF-8472 or not */
7410 status = hw->phy.ops.read_i2c_eeprom(hw,
7411 IXGBE_SFF_SFF_8472_COMP,
7416 /* addressing mode is not supported */
7417 status = hw->phy.ops.read_i2c_eeprom(hw,
7418 IXGBE_SFF_SFF_8472_SWAP,
7423 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7425 "Address change required to access page 0xA2, "
7426 "but not supported. Please report the module "
7427 "type to the driver maintainers.");
7431 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7432 /* We have a SFP, but it does not support SFF-8472 */
7433 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7434 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7436 /* We have a SFP which supports a revision of SFF-8472. */
7437 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7438 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7445 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7446 struct rte_dev_eeprom_info *info)
7448 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7449 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7450 uint8_t databyte = 0xFF;
7451 uint8_t *data = info->data;
7454 if (info->length == 0)
7457 for (i = info->offset; i < info->offset + info->length; i++) {
7458 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7459 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7461 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7466 data[i - info->offset] = databyte;
7473 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7475 case ixgbe_mac_X550:
7476 case ixgbe_mac_X550EM_x:
7477 case ixgbe_mac_X550EM_a:
7478 return ETH_RSS_RETA_SIZE_512;
7479 case ixgbe_mac_X550_vf:
7480 case ixgbe_mac_X550EM_x_vf:
7481 case ixgbe_mac_X550EM_a_vf:
7482 return ETH_RSS_RETA_SIZE_64;
7483 case ixgbe_mac_X540_vf:
7484 case ixgbe_mac_82599_vf:
7487 return ETH_RSS_RETA_SIZE_128;
7492 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7494 case ixgbe_mac_X550:
7495 case ixgbe_mac_X550EM_x:
7496 case ixgbe_mac_X550EM_a:
7497 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7498 return IXGBE_RETA(reta_idx >> 2);
7500 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7501 case ixgbe_mac_X550_vf:
7502 case ixgbe_mac_X550EM_x_vf:
7503 case ixgbe_mac_X550EM_a_vf:
7504 return IXGBE_VFRETA(reta_idx >> 2);
7506 return IXGBE_RETA(reta_idx >> 2);
7511 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7513 case ixgbe_mac_X550_vf:
7514 case ixgbe_mac_X550EM_x_vf:
7515 case ixgbe_mac_X550EM_a_vf:
7516 return IXGBE_VFMRQC;
7523 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7525 case ixgbe_mac_X550_vf:
7526 case ixgbe_mac_X550EM_x_vf:
7527 case ixgbe_mac_X550EM_a_vf:
7528 return IXGBE_VFRSSRK(i);
7530 return IXGBE_RSSRK(i);
7535 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7537 case ixgbe_mac_82599_vf:
7538 case ixgbe_mac_X540_vf:
7546 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7547 struct rte_eth_dcb_info *dcb_info)
7549 struct ixgbe_dcb_config *dcb_config =
7550 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7551 struct ixgbe_dcb_tc_config *tc;
7552 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7556 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7557 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7559 dcb_info->nb_tcs = 1;
7561 tc_queue = &dcb_info->tc_queue;
7562 nb_tcs = dcb_info->nb_tcs;
7564 if (dcb_config->vt_mode) { /* vt is enabled*/
7565 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7566 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7567 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7568 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7569 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7570 for (j = 0; j < nb_tcs; j++) {
7571 tc_queue->tc_rxq[0][j].base = j;
7572 tc_queue->tc_rxq[0][j].nb_queue = 1;
7573 tc_queue->tc_txq[0][j].base = j;
7574 tc_queue->tc_txq[0][j].nb_queue = 1;
7577 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7578 for (j = 0; j < nb_tcs; j++) {
7579 tc_queue->tc_rxq[i][j].base =
7581 tc_queue->tc_rxq[i][j].nb_queue = 1;
7582 tc_queue->tc_txq[i][j].base =
7584 tc_queue->tc_txq[i][j].nb_queue = 1;
7588 } else { /* vt is disabled*/
7589 struct rte_eth_dcb_rx_conf *rx_conf =
7590 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7591 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7592 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7593 if (dcb_info->nb_tcs == ETH_4_TCS) {
7594 for (i = 0; i < dcb_info->nb_tcs; i++) {
7595 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7596 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7598 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7599 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7600 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7601 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7602 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7603 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7604 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7605 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7606 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7607 for (i = 0; i < dcb_info->nb_tcs; i++) {
7608 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7609 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7611 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7612 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7613 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7614 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7615 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7616 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7617 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7618 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7619 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7620 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7621 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7622 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7623 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7624 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7625 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7626 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7629 for (i = 0; i < dcb_info->nb_tcs; i++) {
7630 tc = &dcb_config->tc_config[i];
7631 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7636 /* Update e-tag ether type */
7638 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7639 uint16_t ether_type)
7641 uint32_t etag_etype;
7643 if (hw->mac.type != ixgbe_mac_X550 &&
7644 hw->mac.type != ixgbe_mac_X550EM_x &&
7645 hw->mac.type != ixgbe_mac_X550EM_a) {
7649 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7650 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7651 etag_etype |= ether_type;
7652 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7653 IXGBE_WRITE_FLUSH(hw);
7658 /* Config l2 tunnel ether type */
7660 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7661 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7664 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7665 struct ixgbe_l2_tn_info *l2_tn_info =
7666 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7668 if (l2_tunnel == NULL)
7671 switch (l2_tunnel->l2_tunnel_type) {
7672 case RTE_L2_TUNNEL_TYPE_E_TAG:
7673 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7674 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7677 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7685 /* Enable e-tag tunnel */
7687 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7689 uint32_t etag_etype;
7691 if (hw->mac.type != ixgbe_mac_X550 &&
7692 hw->mac.type != ixgbe_mac_X550EM_x &&
7693 hw->mac.type != ixgbe_mac_X550EM_a) {
7697 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7698 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7699 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7700 IXGBE_WRITE_FLUSH(hw);
7705 /* Enable l2 tunnel */
7707 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7708 enum rte_eth_tunnel_type l2_tunnel_type)
7711 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7712 struct ixgbe_l2_tn_info *l2_tn_info =
7713 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7715 switch (l2_tunnel_type) {
7716 case RTE_L2_TUNNEL_TYPE_E_TAG:
7717 l2_tn_info->e_tag_en = TRUE;
7718 ret = ixgbe_e_tag_enable(hw);
7721 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7729 /* Disable e-tag tunnel */
7731 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7733 uint32_t etag_etype;
7735 if (hw->mac.type != ixgbe_mac_X550 &&
7736 hw->mac.type != ixgbe_mac_X550EM_x &&
7737 hw->mac.type != ixgbe_mac_X550EM_a) {
7741 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7742 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7743 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7744 IXGBE_WRITE_FLUSH(hw);
7749 /* Disable l2 tunnel */
7751 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7752 enum rte_eth_tunnel_type l2_tunnel_type)
7755 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7756 struct ixgbe_l2_tn_info *l2_tn_info =
7757 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7759 switch (l2_tunnel_type) {
7760 case RTE_L2_TUNNEL_TYPE_E_TAG:
7761 l2_tn_info->e_tag_en = FALSE;
7762 ret = ixgbe_e_tag_disable(hw);
7765 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7774 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7775 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7778 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7779 uint32_t i, rar_entries;
7780 uint32_t rar_low, rar_high;
7782 if (hw->mac.type != ixgbe_mac_X550 &&
7783 hw->mac.type != ixgbe_mac_X550EM_x &&
7784 hw->mac.type != ixgbe_mac_X550EM_a) {
7788 rar_entries = ixgbe_get_num_rx_addrs(hw);
7790 for (i = 1; i < rar_entries; i++) {
7791 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7792 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7793 if ((rar_high & IXGBE_RAH_AV) &&
7794 (rar_high & IXGBE_RAH_ADTYPE) &&
7795 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7796 l2_tunnel->tunnel_id)) {
7797 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7798 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7800 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7810 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7811 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7814 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7815 uint32_t i, rar_entries;
7816 uint32_t rar_low, rar_high;
7818 if (hw->mac.type != ixgbe_mac_X550 &&
7819 hw->mac.type != ixgbe_mac_X550EM_x &&
7820 hw->mac.type != ixgbe_mac_X550EM_a) {
7824 /* One entry for one tunnel. Try to remove potential existing entry. */
7825 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7827 rar_entries = ixgbe_get_num_rx_addrs(hw);
7829 for (i = 1; i < rar_entries; i++) {
7830 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7831 if (rar_high & IXGBE_RAH_AV) {
7834 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7835 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7836 rar_low = l2_tunnel->tunnel_id;
7838 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7839 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7845 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7846 " Please remove a rule before adding a new one.");
7850 static inline struct ixgbe_l2_tn_filter *
7851 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7852 struct ixgbe_l2_tn_key *key)
7856 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7860 return l2_tn_info->hash_map[ret];
7864 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7865 struct ixgbe_l2_tn_filter *l2_tn_filter)
7869 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7870 &l2_tn_filter->key);
7874 "Failed to insert L2 tunnel filter"
7875 " to hash table %d!",
7880 l2_tn_info->hash_map[ret] = l2_tn_filter;
7882 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7888 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7889 struct ixgbe_l2_tn_key *key)
7892 struct ixgbe_l2_tn_filter *l2_tn_filter;
7894 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7898 "No such L2 tunnel filter to delete %d!",
7903 l2_tn_filter = l2_tn_info->hash_map[ret];
7904 l2_tn_info->hash_map[ret] = NULL;
7906 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7907 rte_free(l2_tn_filter);
7912 /* Add l2 tunnel filter */
7914 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7915 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7919 struct ixgbe_l2_tn_info *l2_tn_info =
7920 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7921 struct ixgbe_l2_tn_key key;
7922 struct ixgbe_l2_tn_filter *node;
7925 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7926 key.tn_id = l2_tunnel->tunnel_id;
7928 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7932 "The L2 tunnel filter already exists!");
7936 node = rte_zmalloc("ixgbe_l2_tn",
7937 sizeof(struct ixgbe_l2_tn_filter),
7942 rte_memcpy(&node->key,
7944 sizeof(struct ixgbe_l2_tn_key));
7945 node->pool = l2_tunnel->pool;
7946 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7953 switch (l2_tunnel->l2_tunnel_type) {
7954 case RTE_L2_TUNNEL_TYPE_E_TAG:
7955 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7958 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7963 if ((!restore) && (ret < 0))
7964 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7969 /* Delete l2 tunnel filter */
7971 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7972 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7975 struct ixgbe_l2_tn_info *l2_tn_info =
7976 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7977 struct ixgbe_l2_tn_key key;
7979 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7980 key.tn_id = l2_tunnel->tunnel_id;
7981 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7985 switch (l2_tunnel->l2_tunnel_type) {
7986 case RTE_L2_TUNNEL_TYPE_E_TAG:
7987 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7990 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7999 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8000 * @dev: pointer to rte_eth_dev structure
8001 * @filter_op:operation will be taken.
8002 * @arg: a pointer to specific structure corresponding to the filter_op
8005 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8006 enum rte_filter_op filter_op,
8011 if (filter_op == RTE_ETH_FILTER_NOP)
8015 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8020 switch (filter_op) {
8021 case RTE_ETH_FILTER_ADD:
8022 ret = ixgbe_dev_l2_tunnel_filter_add
8024 (struct rte_eth_l2_tunnel_conf *)arg,
8027 case RTE_ETH_FILTER_DELETE:
8028 ret = ixgbe_dev_l2_tunnel_filter_del
8030 (struct rte_eth_l2_tunnel_conf *)arg);
8033 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8041 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8045 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8047 if (hw->mac.type != ixgbe_mac_X550 &&
8048 hw->mac.type != ixgbe_mac_X550EM_x &&
8049 hw->mac.type != ixgbe_mac_X550EM_a) {
8053 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8054 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8056 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8057 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8062 /* Enable l2 tunnel forwarding */
8064 ixgbe_dev_l2_tunnel_forwarding_enable
8065 (struct rte_eth_dev *dev,
8066 enum rte_eth_tunnel_type l2_tunnel_type)
8068 struct ixgbe_l2_tn_info *l2_tn_info =
8069 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8072 switch (l2_tunnel_type) {
8073 case RTE_L2_TUNNEL_TYPE_E_TAG:
8074 l2_tn_info->e_tag_fwd_en = TRUE;
8075 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8078 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8086 /* Disable l2 tunnel forwarding */
8088 ixgbe_dev_l2_tunnel_forwarding_disable
8089 (struct rte_eth_dev *dev,
8090 enum rte_eth_tunnel_type l2_tunnel_type)
8092 struct ixgbe_l2_tn_info *l2_tn_info =
8093 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8096 switch (l2_tunnel_type) {
8097 case RTE_L2_TUNNEL_TYPE_E_TAG:
8098 l2_tn_info->e_tag_fwd_en = FALSE;
8099 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8102 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8111 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8112 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8115 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8117 uint32_t vmtir, vmvir;
8118 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8120 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8122 "VF id %u should be less than %u",
8128 if (hw->mac.type != ixgbe_mac_X550 &&
8129 hw->mac.type != ixgbe_mac_X550EM_x &&
8130 hw->mac.type != ixgbe_mac_X550EM_a) {
8135 vmtir = l2_tunnel->tunnel_id;
8139 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8141 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8142 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8144 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8145 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8150 /* Enable l2 tunnel tag insertion */
8152 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8153 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8157 switch (l2_tunnel->l2_tunnel_type) {
8158 case RTE_L2_TUNNEL_TYPE_E_TAG:
8159 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8162 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8170 /* Disable l2 tunnel tag insertion */
8172 ixgbe_dev_l2_tunnel_insertion_disable
8173 (struct rte_eth_dev *dev,
8174 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8178 switch (l2_tunnel->l2_tunnel_type) {
8179 case RTE_L2_TUNNEL_TYPE_E_TAG:
8180 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8183 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8192 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8197 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8199 if (hw->mac.type != ixgbe_mac_X550 &&
8200 hw->mac.type != ixgbe_mac_X550EM_x &&
8201 hw->mac.type != ixgbe_mac_X550EM_a) {
8205 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8207 qde |= IXGBE_QDE_STRIP_TAG;
8209 qde &= ~IXGBE_QDE_STRIP_TAG;
8210 qde &= ~IXGBE_QDE_READ;
8211 qde |= IXGBE_QDE_WRITE;
8212 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8217 /* Enable l2 tunnel tag stripping */
8219 ixgbe_dev_l2_tunnel_stripping_enable
8220 (struct rte_eth_dev *dev,
8221 enum rte_eth_tunnel_type l2_tunnel_type)
8225 switch (l2_tunnel_type) {
8226 case RTE_L2_TUNNEL_TYPE_E_TAG:
8227 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8230 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8238 /* Disable l2 tunnel tag stripping */
8240 ixgbe_dev_l2_tunnel_stripping_disable
8241 (struct rte_eth_dev *dev,
8242 enum rte_eth_tunnel_type l2_tunnel_type)
8246 switch (l2_tunnel_type) {
8247 case RTE_L2_TUNNEL_TYPE_E_TAG:
8248 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8251 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8259 /* Enable/disable l2 tunnel offload functions */
8261 ixgbe_dev_l2_tunnel_offload_set
8262 (struct rte_eth_dev *dev,
8263 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8269 if (l2_tunnel == NULL)
8273 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8275 ret = ixgbe_dev_l2_tunnel_enable(
8277 l2_tunnel->l2_tunnel_type);
8279 ret = ixgbe_dev_l2_tunnel_disable(
8281 l2_tunnel->l2_tunnel_type);
8284 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8286 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8290 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8295 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8297 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8299 l2_tunnel->l2_tunnel_type);
8301 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8303 l2_tunnel->l2_tunnel_type);
8306 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8308 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8310 l2_tunnel->l2_tunnel_type);
8312 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8314 l2_tunnel->l2_tunnel_type);
8321 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8324 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8325 IXGBE_WRITE_FLUSH(hw);
8330 /* There's only one register for VxLAN UDP port.
8331 * So, we cannot add several ports. Will update it.
8334 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8338 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8342 return ixgbe_update_vxlan_port(hw, port);
8345 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8346 * UDP port, it must have a value.
8347 * So, will reset it to the original value 0.
8350 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8355 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8357 if (cur_port != port) {
8358 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8362 return ixgbe_update_vxlan_port(hw, 0);
8365 /* Add UDP tunneling port */
8367 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8368 struct rte_eth_udp_tunnel *udp_tunnel)
8371 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8373 if (hw->mac.type != ixgbe_mac_X550 &&
8374 hw->mac.type != ixgbe_mac_X550EM_x &&
8375 hw->mac.type != ixgbe_mac_X550EM_a) {
8379 if (udp_tunnel == NULL)
8382 switch (udp_tunnel->prot_type) {
8383 case RTE_TUNNEL_TYPE_VXLAN:
8384 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8387 case RTE_TUNNEL_TYPE_GENEVE:
8388 case RTE_TUNNEL_TYPE_TEREDO:
8389 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8394 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8402 /* Remove UDP tunneling port */
8404 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8405 struct rte_eth_udp_tunnel *udp_tunnel)
8408 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8410 if (hw->mac.type != ixgbe_mac_X550 &&
8411 hw->mac.type != ixgbe_mac_X550EM_x &&
8412 hw->mac.type != ixgbe_mac_X550EM_a) {
8416 if (udp_tunnel == NULL)
8419 switch (udp_tunnel->prot_type) {
8420 case RTE_TUNNEL_TYPE_VXLAN:
8421 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8423 case RTE_TUNNEL_TYPE_GENEVE:
8424 case RTE_TUNNEL_TYPE_TEREDO:
8425 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8429 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8438 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8440 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8443 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8447 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8459 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8461 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8464 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8468 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8480 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8482 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8484 int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8486 switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8490 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8502 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8504 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8507 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8511 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8522 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8524 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8527 /* peek the message first */
8528 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8530 /* PF reset VF event */
8531 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8532 /* dummy mbx read to ack pf */
8533 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8535 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8541 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8544 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8545 struct ixgbe_interrupt *intr =
8546 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8547 ixgbevf_intr_disable(dev);
8549 /* read-on-clear nic registers here */
8550 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8553 /* only one misc vector supported - mailbox */
8554 eicr &= IXGBE_VTEICR_MASK;
8555 if (eicr == IXGBE_MISC_VEC_ID)
8556 intr->flags |= IXGBE_FLAG_MAILBOX;
8562 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8564 struct ixgbe_interrupt *intr =
8565 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8567 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8568 ixgbevf_mbx_process(dev);
8569 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8572 ixgbevf_intr_enable(dev);
8578 ixgbevf_dev_interrupt_handler(void *param)
8580 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8582 ixgbevf_dev_interrupt_get_status(dev);
8583 ixgbevf_dev_interrupt_action(dev);
8587 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8588 * @hw: pointer to hardware structure
8590 * Stops the transmit data path and waits for the HW to internally empty
8591 * the Tx security block
8593 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8595 #define IXGBE_MAX_SECTX_POLL 40
8600 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8601 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8602 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8603 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8604 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8605 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8607 /* Use interrupt-safe sleep just in case */
8611 /* For informational purposes only */
8612 if (i >= IXGBE_MAX_SECTX_POLL)
8613 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8614 "path fully disabled. Continuing with init.");
8616 return IXGBE_SUCCESS;
8620 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8621 * @hw: pointer to hardware structure
8623 * Enables the transmit data path.
8625 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8629 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8630 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8631 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8632 IXGBE_WRITE_FLUSH(hw);
8634 return IXGBE_SUCCESS;
8637 /* restore n-tuple filter */
8639 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8641 struct ixgbe_filter_info *filter_info =
8642 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8643 struct ixgbe_5tuple_filter *node;
8645 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8646 ixgbe_inject_5tuple_filter(dev, node);
8650 /* restore ethernet type filter */
8652 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8654 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8655 struct ixgbe_filter_info *filter_info =
8656 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8659 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8660 if (filter_info->ethertype_mask & (1 << i)) {
8661 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8662 filter_info->ethertype_filters[i].etqf);
8663 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8664 filter_info->ethertype_filters[i].etqs);
8665 IXGBE_WRITE_FLUSH(hw);
8670 /* restore SYN filter */
8672 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8674 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8675 struct ixgbe_filter_info *filter_info =
8676 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8679 synqf = filter_info->syn_info;
8681 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8682 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8683 IXGBE_WRITE_FLUSH(hw);
8687 /* restore L2 tunnel filter */
8689 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8691 struct ixgbe_l2_tn_info *l2_tn_info =
8692 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8693 struct ixgbe_l2_tn_filter *node;
8694 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8696 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8697 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8698 l2_tn_conf.tunnel_id = node->key.tn_id;
8699 l2_tn_conf.pool = node->pool;
8700 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8704 /* restore rss filter */
8706 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8708 struct ixgbe_filter_info *filter_info =
8709 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8711 if (filter_info->rss_info.conf.queue_num)
8712 ixgbe_config_rss_filter(dev,
8713 &filter_info->rss_info, TRUE);
8717 ixgbe_filter_restore(struct rte_eth_dev *dev)
8719 ixgbe_ntuple_filter_restore(dev);
8720 ixgbe_ethertype_filter_restore(dev);
8721 ixgbe_syn_filter_restore(dev);
8722 ixgbe_fdir_filter_restore(dev);
8723 ixgbe_l2_tn_filter_restore(dev);
8724 ixgbe_rss_filter_restore(dev);
8730 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8732 struct ixgbe_l2_tn_info *l2_tn_info =
8733 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8734 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8736 if (l2_tn_info->e_tag_en)
8737 (void)ixgbe_e_tag_enable(hw);
8739 if (l2_tn_info->e_tag_fwd_en)
8740 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8742 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8745 /* remove all the n-tuple filters */
8747 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8749 struct ixgbe_filter_info *filter_info =
8750 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8751 struct ixgbe_5tuple_filter *p_5tuple;
8753 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8754 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8757 /* remove all the ether type filters */
8759 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8761 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8762 struct ixgbe_filter_info *filter_info =
8763 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8766 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8767 if (filter_info->ethertype_mask & (1 << i) &&
8768 !filter_info->ethertype_filters[i].conf) {
8769 (void)ixgbe_ethertype_filter_remove(filter_info,
8771 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8772 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8773 IXGBE_WRITE_FLUSH(hw);
8778 /* remove the SYN filter */
8780 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8782 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8783 struct ixgbe_filter_info *filter_info =
8784 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8786 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8787 filter_info->syn_info = 0;
8789 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8790 IXGBE_WRITE_FLUSH(hw);
8794 /* remove all the L2 tunnel filters */
8796 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8798 struct ixgbe_l2_tn_info *l2_tn_info =
8799 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8800 struct ixgbe_l2_tn_filter *l2_tn_filter;
8801 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8804 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8805 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8806 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8807 l2_tn_conf.pool = l2_tn_filter->pool;
8808 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8817 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8818 struct ixgbe_macsec_setting *macsec_setting)
8820 struct ixgbe_macsec_setting *macsec =
8821 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8823 macsec->offload_en = macsec_setting->offload_en;
8824 macsec->encrypt_en = macsec_setting->encrypt_en;
8825 macsec->replayprotect_en = macsec_setting->replayprotect_en;
8829 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8831 struct ixgbe_macsec_setting *macsec =
8832 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8834 macsec->offload_en = 0;
8835 macsec->encrypt_en = 0;
8836 macsec->replayprotect_en = 0;
8840 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8841 struct ixgbe_macsec_setting *macsec_setting)
8843 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8845 uint8_t en = macsec_setting->encrypt_en;
8846 uint8_t rp = macsec_setting->replayprotect_en;
8850 * As no ixgbe_disable_sec_rx_path equivalent is
8851 * implemented for tx in the base code, and we are
8852 * not allowed to modify the base code in DPDK, so
8853 * just call the hand-written one directly for now.
8854 * The hardware support has been checked by
8855 * ixgbe_disable_sec_rx_path().
8857 ixgbe_disable_sec_tx_path_generic(hw);
8859 /* Enable Ethernet CRC (required by MACsec offload) */
8860 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8861 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8862 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8864 /* Enable the TX and RX crypto engines */
8865 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8866 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8867 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8869 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8870 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8871 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8873 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8874 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8876 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8878 /* Enable SA lookup */
8879 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8880 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8881 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8882 IXGBE_LSECTXCTRL_AUTH;
8883 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8884 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8885 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8886 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8888 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8889 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8890 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8891 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8893 ctrl |= IXGBE_LSECRXCTRL_RP;
8895 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8896 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8898 /* Start the data paths */
8899 ixgbe_enable_sec_rx_path(hw);
8902 * As no ixgbe_enable_sec_rx_path equivalent is
8903 * implemented for tx in the base code, and we are
8904 * not allowed to modify the base code in DPDK, so
8905 * just call the hand-written one directly for now.
8907 ixgbe_enable_sec_tx_path_generic(hw);
8911 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8913 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8918 * As no ixgbe_disable_sec_rx_path equivalent is
8919 * implemented for tx in the base code, and we are
8920 * not allowed to modify the base code in DPDK, so
8921 * just call the hand-written one directly for now.
8922 * The hardware support has been checked by
8923 * ixgbe_disable_sec_rx_path().
8925 ixgbe_disable_sec_tx_path_generic(hw);
8927 /* Disable the TX and RX crypto engines */
8928 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8929 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8930 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8932 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8933 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8934 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8936 /* Disable SA lookup */
8937 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8938 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8939 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8940 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8942 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8943 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8944 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8945 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8947 /* Start the data paths */
8948 ixgbe_enable_sec_rx_path(hw);
8951 * As no ixgbe_enable_sec_rx_path equivalent is
8952 * implemented for tx in the base code, and we are
8953 * not allowed to modify the base code in DPDK, so
8954 * just call the hand-written one directly for now.
8956 ixgbe_enable_sec_tx_path_generic(hw);
8959 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8960 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8961 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8962 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8963 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8964 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8965 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8966 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8968 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
8969 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
8971 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
8972 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
8974 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
8975 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
8977 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
8978 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);