1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_kvargs.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_hash_crc.h>
36 #ifdef RTE_LIB_SECURITY
37 #include <rte_security_driver.h>
40 #include "ixgbe_logs.h"
41 #include "base/ixgbe_api.h"
42 #include "base/ixgbe_vf.h"
43 #include "base/ixgbe_common.h"
44 #include "ixgbe_ethdev.h"
45 #include "ixgbe_bypass.h"
46 #include "ixgbe_rxtx.h"
47 #include "base/ixgbe_type.h"
48 #include "base/ixgbe_phy.h"
49 #include "ixgbe_regs.h"
52 * High threshold controlling when to start sending XOFF frames. Must be at
53 * least 8 bytes less than receive packet buffer size. This value is in units
56 #define IXGBE_FC_HI 0x80
59 * Low threshold controlling when to start sending XON frames. This value is
60 * in units of 1024 bytes.
62 #define IXGBE_FC_LO 0x40
64 /* Timer value included in XOFF frames. */
65 #define IXGBE_FC_PAUSE 0x680
67 /*Default value of Max Rx Queue*/
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
74 #define IXGBE_MMW_SIZE_DEFAULT 0x4
75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
79 * Default values for RX/TX configuration
81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
82 #define IXGBE_DEFAULT_RX_PTHRESH 8
83 #define IXGBE_DEFAULT_RX_HTHRESH 8
84 #define IXGBE_DEFAULT_RX_WTHRESH 0
86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
87 #define IXGBE_DEFAULT_TX_PTHRESH 32
88 #define IXGBE_DEFAULT_TX_HTHRESH 0
89 #define IXGBE_DEFAULT_TX_WTHRESH 0
90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
95 #define IXGBE_8_BIT_WIDTH CHAR_BIT
96 #define IXGBE_8_BIT_MASK UINT8_MAX
98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
102 /* Additional timesync values. */
103 #define NSEC_PER_SEC 1000000000L
104 #define IXGBE_INCVAL_10GB 0x66666666
105 #define IXGBE_INCVAL_1GB 0x40000000
106 #define IXGBE_INCVAL_100 0x50000000
107 #define IXGBE_INCVAL_SHIFT_10GB 28
108 #define IXGBE_INCVAL_SHIFT_1GB 24
109 #define IXGBE_INCVAL_SHIFT_100 21
110 #define IXGBE_INCVAL_SHIFT_82599 7
111 #define IXGBE_INCPER_SHIFT_82599 24
113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
117 #define IXGBE_ETAG_ETYPE 0x00005084
118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
120 #define IXGBE_RAH_ADTYPE 0x40000000
121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
125 #define IXGBE_QDE_STRIP_TAG 0x00000004
126 #define IXGBE_VTEICR_MASK 0x07
128 #define IXGBE_EXVET_VET_EXT_SHIFT 16
129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk"
133 static const char * const ixgbevf_valid_arguments[] = {
134 IXGBEVF_DEVARG_PFLINK_FULLCHK,
138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
157 int wait_to_complete);
158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
166 uint64_t *values, unsigned int n);
167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names, unsigned limit);
174 static int ixgbe_dev_xstats_get_names_by_id(
175 struct rte_eth_dev *dev,
176 struct rte_eth_xstat_name *xstats_names,
179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_fc_conf *fc_conf);
216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
217 struct rte_eth_pfc_conf *pfc_conf);
218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
222 struct rte_eth_rss_reta_entry64 *reta_conf,
224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
230 static void ixgbe_dev_interrupt_handler(void *param);
231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
234 uint32_t timeout_ms);
236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
237 struct rte_ether_addr *mac_addr,
238 uint32_t index, uint32_t pool);
239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
241 struct rte_ether_addr *mac_addr);
242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
243 static bool is_device_supported(struct rte_eth_dev *dev,
244 struct rte_pci_driver *drv);
246 /* For Virtual Function support */
247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
250 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
252 int wait_to_complete);
253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
255 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
262 uint16_t vlan_id, int on);
263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
264 uint16_t queue, int on);
265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
273 uint8_t queue, uint8_t msix_vector);
274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
280 /* For Eth VMDQ APIs support */
281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
282 rte_ether_addr * mac_addr, uint8_t on);
283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
285 struct rte_eth_mirror_conf *mirror_conf,
286 uint8_t rule_id, uint8_t on);
287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
294 uint8_t queue, uint8_t msix_vector);
295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
298 struct rte_ether_addr *mac_addr,
299 uint32_t index, uint32_t pool);
300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
302 struct rte_ether_addr *mac_addr);
303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
304 struct rte_eth_syn_filter *filter);
305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
306 enum rte_filter_op filter_op,
308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
309 struct ixgbe_5tuple_filter *filter);
310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
311 struct ixgbe_5tuple_filter *filter);
312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
313 enum rte_filter_op filter_op,
315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
316 struct rte_eth_ntuple_filter *filter);
317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
318 enum rte_filter_op filter_op,
320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
321 struct rte_eth_ethertype_filter *filter);
322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
323 enum rte_filter_type filter_type,
324 enum rte_filter_op filter_op,
326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
329 struct rte_ether_addr *mc_addr_set,
330 uint32_t nb_mc_addr);
331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
332 struct rte_eth_dcb_info *dcb_info);
334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
336 struct rte_dev_reg_info *regs);
337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
339 struct rte_dev_eeprom_info *eeprom);
340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
341 struct rte_dev_eeprom_info *eeprom);
343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
344 struct rte_eth_dev_module_info *modinfo);
345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
346 struct rte_dev_eeprom_info *info);
348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
350 struct rte_dev_reg_info *regs);
352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
355 struct timespec *timestamp,
357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
358 struct timespec *timestamp);
359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
361 struct timespec *timestamp);
362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
363 const struct timespec *timestamp);
364 static void ixgbevf_dev_interrupt_handler(void *param);
366 static int ixgbe_dev_l2_tunnel_eth_type_conf
367 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
368 static int ixgbe_dev_l2_tunnel_offload_set
369 (struct rte_eth_dev *dev,
370 struct rte_eth_l2_tunnel_conf *l2_tunnel,
373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
374 enum rte_filter_op filter_op,
377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
378 struct rte_eth_udp_tunnel *udp_tunnel);
379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
380 struct rte_eth_udp_tunnel *udp_tunnel);
381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
386 * Define VF Stats MACRO for Non "cleared on read" register
388 #define UPDATE_VF_STAT(reg, last, cur) \
390 uint32_t latest = IXGBE_READ_REG(hw, reg); \
391 cur += (latest - last) & UINT_MAX; \
395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
397 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
398 u64 new_msb = IXGBE_READ_REG(hw, msb); \
399 u64 latest = ((new_msb << 32) | new_lsb); \
400 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
404 #define IXGBE_SET_HWSTRIP(h, q) do {\
405 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
406 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
407 (h)->bitmap[idx] |= 1 << bit;\
410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
411 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
412 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
413 (h)->bitmap[idx] &= ~(1 << bit);\
416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
417 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
418 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
419 (r) = (h)->bitmap[idx] >> bit & 1;\
423 * The set of PCI devices this driver supports
425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
477 { .vendor_id = 0, /* sentinel */ },
481 * The set of PCI devices this driver supports (for 82599 VF)
483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
494 { .vendor_id = 0, /* sentinel */ },
497 static const struct rte_eth_desc_lim rx_desc_lim = {
498 .nb_max = IXGBE_MAX_RING_DESC,
499 .nb_min = IXGBE_MIN_RING_DESC,
500 .nb_align = IXGBE_RXD_ALIGN,
503 static const struct rte_eth_desc_lim tx_desc_lim = {
504 .nb_max = IXGBE_MAX_RING_DESC,
505 .nb_min = IXGBE_MIN_RING_DESC,
506 .nb_align = IXGBE_TXD_ALIGN,
507 .nb_seg_max = IXGBE_TX_MAX_SEG,
508 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
512 .dev_configure = ixgbe_dev_configure,
513 .dev_start = ixgbe_dev_start,
514 .dev_stop = ixgbe_dev_stop,
515 .dev_set_link_up = ixgbe_dev_set_link_up,
516 .dev_set_link_down = ixgbe_dev_set_link_down,
517 .dev_close = ixgbe_dev_close,
518 .dev_reset = ixgbe_dev_reset,
519 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
520 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
521 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
522 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
523 .link_update = ixgbe_dev_link_update,
524 .stats_get = ixgbe_dev_stats_get,
525 .xstats_get = ixgbe_dev_xstats_get,
526 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
527 .stats_reset = ixgbe_dev_stats_reset,
528 .xstats_reset = ixgbe_dev_xstats_reset,
529 .xstats_get_names = ixgbe_dev_xstats_get_names,
530 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
531 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
532 .fw_version_get = ixgbe_fw_version_get,
533 .dev_infos_get = ixgbe_dev_info_get,
534 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
535 .mtu_set = ixgbe_dev_mtu_set,
536 .vlan_filter_set = ixgbe_vlan_filter_set,
537 .vlan_tpid_set = ixgbe_vlan_tpid_set,
538 .vlan_offload_set = ixgbe_vlan_offload_set,
539 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
540 .rx_queue_start = ixgbe_dev_rx_queue_start,
541 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
542 .tx_queue_start = ixgbe_dev_tx_queue_start,
543 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
544 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
545 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
546 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
547 .rx_queue_release = ixgbe_dev_rx_queue_release,
548 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
549 .tx_queue_release = ixgbe_dev_tx_queue_release,
550 .dev_led_on = ixgbe_dev_led_on,
551 .dev_led_off = ixgbe_dev_led_off,
552 .flow_ctrl_get = ixgbe_flow_ctrl_get,
553 .flow_ctrl_set = ixgbe_flow_ctrl_set,
554 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
555 .mac_addr_add = ixgbe_add_rar,
556 .mac_addr_remove = ixgbe_remove_rar,
557 .mac_addr_set = ixgbe_set_default_mac_addr,
558 .uc_hash_table_set = ixgbe_uc_hash_table_set,
559 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
560 .mirror_rule_set = ixgbe_mirror_rule_set,
561 .mirror_rule_reset = ixgbe_mirror_rule_reset,
562 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
563 .reta_update = ixgbe_dev_rss_reta_update,
564 .reta_query = ixgbe_dev_rss_reta_query,
565 .rss_hash_update = ixgbe_dev_rss_hash_update,
566 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
567 .filter_ctrl = ixgbe_dev_filter_ctrl,
568 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
569 .rxq_info_get = ixgbe_rxq_info_get,
570 .txq_info_get = ixgbe_txq_info_get,
571 .timesync_enable = ixgbe_timesync_enable,
572 .timesync_disable = ixgbe_timesync_disable,
573 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
574 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
575 .get_reg = ixgbe_get_regs,
576 .get_eeprom_length = ixgbe_get_eeprom_length,
577 .get_eeprom = ixgbe_get_eeprom,
578 .set_eeprom = ixgbe_set_eeprom,
579 .get_module_info = ixgbe_get_module_info,
580 .get_module_eeprom = ixgbe_get_module_eeprom,
581 .get_dcb_info = ixgbe_dev_get_dcb_info,
582 .timesync_adjust_time = ixgbe_timesync_adjust_time,
583 .timesync_read_time = ixgbe_timesync_read_time,
584 .timesync_write_time = ixgbe_timesync_write_time,
585 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
586 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
587 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
588 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
589 .tm_ops_get = ixgbe_tm_ops_get,
590 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
594 * dev_ops for virtual function, bare necessities for basic vf
595 * operation have been implemented
597 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
598 .dev_configure = ixgbevf_dev_configure,
599 .dev_start = ixgbevf_dev_start,
600 .dev_stop = ixgbevf_dev_stop,
601 .link_update = ixgbevf_dev_link_update,
602 .stats_get = ixgbevf_dev_stats_get,
603 .xstats_get = ixgbevf_dev_xstats_get,
604 .stats_reset = ixgbevf_dev_stats_reset,
605 .xstats_reset = ixgbevf_dev_stats_reset,
606 .xstats_get_names = ixgbevf_dev_xstats_get_names,
607 .dev_close = ixgbevf_dev_close,
608 .dev_reset = ixgbevf_dev_reset,
609 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
610 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
611 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
612 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
613 .dev_infos_get = ixgbevf_dev_info_get,
614 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
615 .mtu_set = ixgbevf_dev_set_mtu,
616 .vlan_filter_set = ixgbevf_vlan_filter_set,
617 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
618 .vlan_offload_set = ixgbevf_vlan_offload_set,
619 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
620 .rx_queue_release = ixgbe_dev_rx_queue_release,
621 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
622 .tx_queue_release = ixgbe_dev_tx_queue_release,
623 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
624 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
625 .mac_addr_add = ixgbevf_add_mac_addr,
626 .mac_addr_remove = ixgbevf_remove_mac_addr,
627 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
628 .rxq_info_get = ixgbe_rxq_info_get,
629 .txq_info_get = ixgbe_txq_info_get,
630 .mac_addr_set = ixgbevf_set_default_mac_addr,
631 .get_reg = ixgbevf_get_regs,
632 .reta_update = ixgbe_dev_rss_reta_update,
633 .reta_query = ixgbe_dev_rss_reta_query,
634 .rss_hash_update = ixgbe_dev_rss_hash_update,
635 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
636 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
639 /* store statistics names and its offset in stats structure */
640 struct rte_ixgbe_xstats_name_off {
641 char name[RTE_ETH_XSTATS_NAME_SIZE];
645 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
646 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
647 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
648 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
649 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
650 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
651 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
652 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
653 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
654 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
655 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
656 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
657 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
658 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
659 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
660 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
662 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
664 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
665 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
666 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
667 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
668 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
669 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
670 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
671 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
672 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
673 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
674 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
675 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
676 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
677 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
678 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
679 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
680 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
682 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
684 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
685 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
686 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
687 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
689 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
691 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
693 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
695 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
697 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
699 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
702 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
703 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
704 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
706 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
707 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
708 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
709 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
710 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
712 {"rx_fcoe_no_direct_data_placement_ext_buff",
713 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
715 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
717 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
719 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
721 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
723 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
726 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
727 sizeof(rte_ixgbe_stats_strings[0]))
729 /* MACsec statistics */
730 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
731 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
733 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
734 out_pkts_encrypted)},
735 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
736 out_pkts_protected)},
737 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
738 out_octets_encrypted)},
739 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
740 out_octets_protected)},
741 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
743 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
745 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
747 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
748 in_pkts_unknownsci)},
749 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
750 in_octets_decrypted)},
751 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
752 in_octets_validated)},
753 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
755 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
757 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
759 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
761 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
763 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
765 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
768 in_pkts_notusingsa)},
771 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
772 sizeof(rte_ixgbe_macsec_strings[0]))
774 /* Per-queue statistics */
775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
776 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
777 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
778 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
779 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
782 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
783 sizeof(rte_ixgbe_rxq_strings[0]))
784 #define IXGBE_NB_RXQ_PRIO_VALUES 8
786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
787 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
788 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
789 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
793 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
794 sizeof(rte_ixgbe_txq_strings[0]))
795 #define IXGBE_NB_TXQ_PRIO_VALUES 8
797 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
798 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
801 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
802 sizeof(rte_ixgbevf_stats_strings[0]))
805 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
808 ixgbe_is_sfp(struct ixgbe_hw *hw)
810 switch (hw->phy.type) {
811 case ixgbe_phy_sfp_avago:
812 case ixgbe_phy_sfp_ftl:
813 case ixgbe_phy_sfp_intel:
814 case ixgbe_phy_sfp_unknown:
815 case ixgbe_phy_sfp_passive_tyco:
816 case ixgbe_phy_sfp_passive_unknown:
823 static inline int32_t
824 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
829 status = ixgbe_reset_hw(hw);
831 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
832 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
833 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
834 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
835 IXGBE_WRITE_FLUSH(hw);
837 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
838 status = IXGBE_SUCCESS;
843 ixgbe_enable_intr(struct rte_eth_dev *dev)
845 struct ixgbe_interrupt *intr =
846 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
847 struct ixgbe_hw *hw =
848 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
850 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
851 IXGBE_WRITE_FLUSH(hw);
855 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
858 ixgbe_disable_intr(struct ixgbe_hw *hw)
860 PMD_INIT_FUNC_TRACE();
862 if (hw->mac.type == ixgbe_mac_82598EB) {
863 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
865 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
866 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
867 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
869 IXGBE_WRITE_FLUSH(hw);
873 * This function resets queue statistics mapping registers.
874 * From Niantic datasheet, Initialization of Statistics section:
875 * "...if software requires the queue counters, the RQSMR and TQSM registers
876 * must be re-programmed following a device reset.
879 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
883 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
884 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
885 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
891 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
896 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
897 #define NB_QMAP_FIELDS_PER_QSM_REG 4
898 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
900 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
901 struct ixgbe_stat_mapping_registers *stat_mappings =
902 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
903 uint32_t qsmr_mask = 0;
904 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
908 if ((hw->mac.type != ixgbe_mac_82599EB) &&
909 (hw->mac.type != ixgbe_mac_X540) &&
910 (hw->mac.type != ixgbe_mac_X550) &&
911 (hw->mac.type != ixgbe_mac_X550EM_x) &&
912 (hw->mac.type != ixgbe_mac_X550EM_a))
915 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
916 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
919 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
920 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
921 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
924 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
926 /* Now clear any previous stat_idx set */
927 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
929 stat_mappings->tqsm[n] &= ~clearing_mask;
931 stat_mappings->rqsmr[n] &= ~clearing_mask;
933 q_map = (uint32_t)stat_idx;
934 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
935 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
937 stat_mappings->tqsm[n] |= qsmr_mask;
939 stat_mappings->rqsmr[n] |= qsmr_mask;
941 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
942 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
944 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
945 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
947 /* Now write the mapping in the appropriate register */
949 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
950 stat_mappings->rqsmr[n], n);
951 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
953 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
954 stat_mappings->tqsm[n], n);
955 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
961 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
963 struct ixgbe_stat_mapping_registers *stat_mappings =
964 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
965 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
968 /* write whatever was in stat mapping table to the NIC */
969 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
971 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
974 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
979 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
982 struct ixgbe_dcb_tc_config *tc;
983 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
985 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
986 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
987 for (i = 0; i < dcb_max_tc; i++) {
988 tc = &dcb_config->tc_config[i];
989 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
990 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
991 (uint8_t)(100/dcb_max_tc + (i & 1));
992 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
993 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
994 (uint8_t)(100/dcb_max_tc + (i & 1));
995 tc->pfc = ixgbe_dcb_pfc_disabled;
998 /* Initialize default user to priority mapping, UPx->TC0 */
999 tc = &dcb_config->tc_config[0];
1000 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1001 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1002 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1003 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1004 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1006 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1007 dcb_config->pfc_mode_enable = false;
1008 dcb_config->vt_mode = true;
1009 dcb_config->round_robin_enable = false;
1010 /* support all DCB capabilities in 82599 */
1011 dcb_config->support.capabilities = 0xFF;
1013 /*we only support 4 Tcs for X540, X550 */
1014 if (hw->mac.type == ixgbe_mac_X540 ||
1015 hw->mac.type == ixgbe_mac_X550 ||
1016 hw->mac.type == ixgbe_mac_X550EM_x ||
1017 hw->mac.type == ixgbe_mac_X550EM_a) {
1018 dcb_config->num_tcs.pg_tcs = 4;
1019 dcb_config->num_tcs.pfc_tcs = 4;
1024 * Ensure that all locks are released before first NVM or PHY access
1027 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1032 * Phy lock should not fail in this early stage. If this is the case,
1033 * it is due to an improper exit of the application.
1034 * So force the release of the faulty lock. Release of common lock
1035 * is done automatically by swfw_sync function.
1037 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1038 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1039 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1041 ixgbe_release_swfw_semaphore(hw, mask);
1044 * These ones are more tricky since they are common to all ports; but
1045 * swfw_sync retries last long enough (1s) to be almost sure that if
1046 * lock can not be taken it is due to an improper lock of the
1049 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1050 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1051 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1053 ixgbe_release_swfw_semaphore(hw, mask);
1057 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1058 * It returns 0 on success.
1061 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1063 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1064 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1065 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1066 struct ixgbe_hw *hw =
1067 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1068 struct ixgbe_vfta *shadow_vfta =
1069 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1070 struct ixgbe_hwstrip *hwstrip =
1071 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1072 struct ixgbe_dcb_config *dcb_config =
1073 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1074 struct ixgbe_filter_info *filter_info =
1075 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1076 struct ixgbe_bw_conf *bw_conf =
1077 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1082 PMD_INIT_FUNC_TRACE();
1084 ixgbe_dev_macsec_setting_reset(eth_dev);
1086 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1087 eth_dev->rx_queue_count = ixgbe_dev_rx_queue_count;
1088 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done;
1089 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1090 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1091 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1092 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1093 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1096 * For secondary processes, we don't initialise any further as primary
1097 * has already done this work. Only check we don't need a different
1098 * RX and TX function.
1100 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1101 struct ixgbe_tx_queue *txq;
1102 /* TX queue function in primary, set by last queue initialized
1103 * Tx queue may not initialized by primary process
1105 if (eth_dev->data->tx_queues) {
1106 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1107 ixgbe_set_tx_function(eth_dev, txq);
1109 /* Use default TX function if we get here */
1110 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1111 "Using default TX function.");
1114 ixgbe_set_rx_function(eth_dev);
1119 rte_atomic32_clear(&ad->link_thread_running);
1120 rte_eth_copy_pci_info(eth_dev, pci_dev);
1121 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1123 /* Vendor and Device ID need to be set before init of shared code */
1124 hw->device_id = pci_dev->id.device_id;
1125 hw->vendor_id = pci_dev->id.vendor_id;
1126 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1127 hw->allow_unsupported_sfp = 1;
1129 /* Initialize the shared code (base driver) */
1130 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1131 diag = ixgbe_bypass_init_shared_code(hw);
1133 diag = ixgbe_init_shared_code(hw);
1134 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1136 if (diag != IXGBE_SUCCESS) {
1137 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1141 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1142 PMD_INIT_LOG(ERR, "\nERROR: "
1143 "Firmware recovery mode detected. Limiting functionality.\n"
1144 "Refer to the Intel(R) Ethernet Adapters and Devices "
1145 "User Guide for details on firmware recovery mode.");
1149 /* pick up the PCI bus settings for reporting later */
1150 ixgbe_get_bus_info(hw);
1152 /* Unlock any pending hardware semaphore */
1153 ixgbe_swfw_lock_reset(hw);
1155 #ifdef RTE_LIB_SECURITY
1156 /* Initialize security_ctx only for primary process*/
1157 if (ixgbe_ipsec_ctx_create(eth_dev))
1161 /* Initialize DCB configuration*/
1162 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1163 ixgbe_dcb_init(hw, dcb_config);
1164 /* Get Hardware Flow Control setting */
1165 hw->fc.requested_mode = ixgbe_fc_none;
1166 hw->fc.current_mode = ixgbe_fc_none;
1167 hw->fc.pause_time = IXGBE_FC_PAUSE;
1168 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1169 hw->fc.low_water[i] = IXGBE_FC_LO;
1170 hw->fc.high_water[i] = IXGBE_FC_HI;
1172 hw->fc.send_xon = 1;
1174 /* Make sure we have a good EEPROM before we read from it */
1175 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1176 if (diag != IXGBE_SUCCESS) {
1177 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1181 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1182 diag = ixgbe_bypass_init_hw(hw);
1184 diag = ixgbe_init_hw(hw);
1185 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1188 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1189 * is called too soon after the kernel driver unbinding/binding occurs.
1190 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1191 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1192 * also called. See ixgbe_identify_phy_82599(). The reason for the
1193 * failure is not known, and only occuts when virtualisation features
1194 * are disabled in the bios. A delay of 100ms was found to be enough by
1195 * trial-and-error, and is doubled to be safe.
1197 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1199 diag = ixgbe_init_hw(hw);
1202 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1203 diag = IXGBE_SUCCESS;
1205 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1206 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1207 "LOM. Please be aware there may be issues associated "
1208 "with your hardware.");
1209 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1210 "please contact your Intel or hardware representative "
1211 "who provided you with this hardware.");
1212 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1213 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1215 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1219 /* Reset the hw statistics */
1220 ixgbe_dev_stats_reset(eth_dev);
1222 /* disable interrupt */
1223 ixgbe_disable_intr(hw);
1225 /* reset mappings for queue statistics hw counters*/
1226 ixgbe_reset_qstat_mappings(hw);
1228 /* Allocate memory for storing MAC addresses */
1229 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1230 hw->mac.num_rar_entries, 0);
1231 if (eth_dev->data->mac_addrs == NULL) {
1233 "Failed to allocate %u bytes needed to store "
1235 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1238 /* Copy the permanent MAC address */
1239 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1240 ð_dev->data->mac_addrs[0]);
1242 /* Allocate memory for storing hash filter MAC addresses */
1243 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1244 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1245 if (eth_dev->data->hash_mac_addrs == NULL) {
1247 "Failed to allocate %d bytes needed to store MAC addresses",
1248 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1252 /* initialize the vfta */
1253 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1255 /* initialize the hw strip bitmap*/
1256 memset(hwstrip, 0, sizeof(*hwstrip));
1258 /* initialize PF if max_vfs not zero */
1259 ret = ixgbe_pf_host_init(eth_dev);
1261 rte_free(eth_dev->data->mac_addrs);
1262 eth_dev->data->mac_addrs = NULL;
1263 rte_free(eth_dev->data->hash_mac_addrs);
1264 eth_dev->data->hash_mac_addrs = NULL;
1268 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1269 /* let hardware know driver is loaded */
1270 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1271 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1272 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1273 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1274 IXGBE_WRITE_FLUSH(hw);
1276 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1277 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1278 (int) hw->mac.type, (int) hw->phy.type,
1279 (int) hw->phy.sfp_type);
1281 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1282 (int) hw->mac.type, (int) hw->phy.type);
1284 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1285 eth_dev->data->port_id, pci_dev->id.vendor_id,
1286 pci_dev->id.device_id);
1288 rte_intr_callback_register(intr_handle,
1289 ixgbe_dev_interrupt_handler, eth_dev);
1291 /* enable uio/vfio intr/eventfd mapping */
1292 rte_intr_enable(intr_handle);
1294 /* enable support intr */
1295 ixgbe_enable_intr(eth_dev);
1297 /* initialize filter info */
1298 memset(filter_info, 0,
1299 sizeof(struct ixgbe_filter_info));
1301 /* initialize 5tuple filter list */
1302 TAILQ_INIT(&filter_info->fivetuple_list);
1304 /* initialize flow director filter list & hash */
1305 ixgbe_fdir_filter_init(eth_dev);
1307 /* initialize l2 tunnel filter list & hash */
1308 ixgbe_l2_tn_filter_init(eth_dev);
1310 /* initialize flow filter lists */
1311 ixgbe_filterlist_init();
1313 /* initialize bandwidth configuration info */
1314 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1316 /* initialize Traffic Manager configuration */
1317 ixgbe_tm_conf_init(eth_dev);
1323 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1325 PMD_INIT_FUNC_TRACE();
1327 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1330 ixgbe_dev_close(eth_dev);
1335 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1337 struct ixgbe_filter_info *filter_info =
1338 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1339 struct ixgbe_5tuple_filter *p_5tuple;
1341 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1342 TAILQ_REMOVE(&filter_info->fivetuple_list,
1347 memset(filter_info->fivetuple_mask, 0,
1348 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1353 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1355 struct ixgbe_hw_fdir_info *fdir_info =
1356 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1357 struct ixgbe_fdir_filter *fdir_filter;
1359 if (fdir_info->hash_map)
1360 rte_free(fdir_info->hash_map);
1361 if (fdir_info->hash_handle)
1362 rte_hash_free(fdir_info->hash_handle);
1364 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1365 TAILQ_REMOVE(&fdir_info->fdir_list,
1368 rte_free(fdir_filter);
1374 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1376 struct ixgbe_l2_tn_info *l2_tn_info =
1377 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1378 struct ixgbe_l2_tn_filter *l2_tn_filter;
1380 if (l2_tn_info->hash_map)
1381 rte_free(l2_tn_info->hash_map);
1382 if (l2_tn_info->hash_handle)
1383 rte_hash_free(l2_tn_info->hash_handle);
1385 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1386 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1389 rte_free(l2_tn_filter);
1395 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1397 struct ixgbe_hw_fdir_info *fdir_info =
1398 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1399 char fdir_hash_name[RTE_HASH_NAMESIZE];
1400 struct rte_hash_parameters fdir_hash_params = {
1401 .name = fdir_hash_name,
1402 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1403 .key_len = sizeof(union ixgbe_atr_input),
1404 .hash_func = rte_hash_crc,
1405 .hash_func_init_val = 0,
1406 .socket_id = rte_socket_id(),
1409 TAILQ_INIT(&fdir_info->fdir_list);
1410 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1411 "fdir_%s", eth_dev->device->name);
1412 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1413 if (!fdir_info->hash_handle) {
1414 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1417 fdir_info->hash_map = rte_zmalloc("ixgbe",
1418 sizeof(struct ixgbe_fdir_filter *) *
1419 IXGBE_MAX_FDIR_FILTER_NUM,
1421 if (!fdir_info->hash_map) {
1423 "Failed to allocate memory for fdir hash map!");
1426 fdir_info->mask_added = FALSE;
1431 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1433 struct ixgbe_l2_tn_info *l2_tn_info =
1434 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1435 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1436 struct rte_hash_parameters l2_tn_hash_params = {
1437 .name = l2_tn_hash_name,
1438 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1439 .key_len = sizeof(struct ixgbe_l2_tn_key),
1440 .hash_func = rte_hash_crc,
1441 .hash_func_init_val = 0,
1442 .socket_id = rte_socket_id(),
1445 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1446 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1447 "l2_tn_%s", eth_dev->device->name);
1448 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1449 if (!l2_tn_info->hash_handle) {
1450 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1453 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1454 sizeof(struct ixgbe_l2_tn_filter *) *
1455 IXGBE_MAX_L2_TN_FILTER_NUM,
1457 if (!l2_tn_info->hash_map) {
1459 "Failed to allocate memory for L2 TN hash map!");
1462 l2_tn_info->e_tag_en = FALSE;
1463 l2_tn_info->e_tag_fwd_en = FALSE;
1464 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1469 * Negotiate mailbox API version with the PF.
1470 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1471 * Then we try to negotiate starting with the most recent one.
1472 * If all negotiation attempts fail, then we will proceed with
1473 * the default one (ixgbe_mbox_api_10).
1476 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1480 /* start with highest supported, proceed down */
1481 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1489 i != RTE_DIM(sup_ver) &&
1490 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1496 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1500 /* Set Organizationally Unique Identifier (OUI) prefix. */
1501 mac_addr->addr_bytes[0] = 0x00;
1502 mac_addr->addr_bytes[1] = 0x09;
1503 mac_addr->addr_bytes[2] = 0xC0;
1504 /* Force indication of locally assigned MAC address. */
1505 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1506 /* Generate the last 3 bytes of the MAC address with a random number. */
1507 random = rte_rand();
1508 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1512 devarg_handle_int(__rte_unused const char *key, const char *value,
1515 uint16_t *n = extra_args;
1517 if (value == NULL || extra_args == NULL)
1520 *n = (uint16_t)strtoul(value, NULL, 0);
1521 if (*n == USHRT_MAX && errno == ERANGE)
1528 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1529 struct rte_devargs *devargs)
1531 struct rte_kvargs *kvlist;
1532 uint16_t pflink_fullchk;
1534 if (devargs == NULL)
1537 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1541 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1542 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1543 devarg_handle_int, &pflink_fullchk) == 0 &&
1544 pflink_fullchk == 1)
1545 adapter->pflink_fullchk = 1;
1547 rte_kvargs_free(kvlist);
1551 * Virtual Function device init
1554 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1558 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1559 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1560 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1561 struct ixgbe_hw *hw =
1562 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1563 struct ixgbe_vfta *shadow_vfta =
1564 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1565 struct ixgbe_hwstrip *hwstrip =
1566 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1567 struct rte_ether_addr *perm_addr =
1568 (struct rte_ether_addr *)hw->mac.perm_addr;
1570 PMD_INIT_FUNC_TRACE();
1572 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1573 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done;
1574 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1575 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1576 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1577 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1579 /* for secondary processes, we don't initialise any further as primary
1580 * has already done this work. Only check we don't need a different
1583 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1584 struct ixgbe_tx_queue *txq;
1585 /* TX queue function in primary, set by last queue initialized
1586 * Tx queue may not initialized by primary process
1588 if (eth_dev->data->tx_queues) {
1589 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1590 ixgbe_set_tx_function(eth_dev, txq);
1592 /* Use default TX function if we get here */
1593 PMD_INIT_LOG(NOTICE,
1594 "No TX queues configured yet. Using default TX function.");
1597 ixgbe_set_rx_function(eth_dev);
1602 rte_atomic32_clear(&ad->link_thread_running);
1603 ixgbevf_parse_devargs(eth_dev->data->dev_private,
1604 pci_dev->device.devargs);
1606 rte_eth_copy_pci_info(eth_dev, pci_dev);
1607 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1609 hw->device_id = pci_dev->id.device_id;
1610 hw->vendor_id = pci_dev->id.vendor_id;
1611 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1613 /* initialize the vfta */
1614 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1616 /* initialize the hw strip bitmap*/
1617 memset(hwstrip, 0, sizeof(*hwstrip));
1619 /* Initialize the shared code (base driver) */
1620 diag = ixgbe_init_shared_code(hw);
1621 if (diag != IXGBE_SUCCESS) {
1622 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1626 /* init_mailbox_params */
1627 hw->mbx.ops.init_params(hw);
1629 /* Reset the hw statistics */
1630 ixgbevf_dev_stats_reset(eth_dev);
1632 /* Disable the interrupts for VF */
1633 ixgbevf_intr_disable(eth_dev);
1635 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1636 diag = hw->mac.ops.reset_hw(hw);
1639 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1640 * the underlying PF driver has not assigned a MAC address to the VF.
1641 * In this case, assign a random MAC address.
1643 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1644 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1646 * This error code will be propagated to the app by
1647 * rte_eth_dev_reset, so use a public error code rather than
1648 * the internal-only IXGBE_ERR_RESET_FAILED
1653 /* negotiate mailbox API version to use with the PF. */
1654 ixgbevf_negotiate_api(hw);
1656 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1657 ixgbevf_get_queues(hw, &tcs, &tc);
1659 /* Allocate memory for storing MAC addresses */
1660 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1661 hw->mac.num_rar_entries, 0);
1662 if (eth_dev->data->mac_addrs == NULL) {
1664 "Failed to allocate %u bytes needed to store "
1666 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1670 /* Generate a random MAC address, if none was assigned by PF. */
1671 if (rte_is_zero_ether_addr(perm_addr)) {
1672 generate_random_mac_addr(perm_addr);
1673 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1675 rte_free(eth_dev->data->mac_addrs);
1676 eth_dev->data->mac_addrs = NULL;
1679 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1680 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1681 "%02x:%02x:%02x:%02x:%02x:%02x",
1682 perm_addr->addr_bytes[0],
1683 perm_addr->addr_bytes[1],
1684 perm_addr->addr_bytes[2],
1685 perm_addr->addr_bytes[3],
1686 perm_addr->addr_bytes[4],
1687 perm_addr->addr_bytes[5]);
1690 /* Copy the permanent MAC address */
1691 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1693 /* reset the hardware with the new settings */
1694 diag = hw->mac.ops.start_hw(hw);
1700 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1704 rte_intr_callback_register(intr_handle,
1705 ixgbevf_dev_interrupt_handler, eth_dev);
1706 rte_intr_enable(intr_handle);
1707 ixgbevf_intr_enable(eth_dev);
1709 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1710 eth_dev->data->port_id, pci_dev->id.vendor_id,
1711 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1716 /* Virtual Function device uninit */
1719 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1721 PMD_INIT_FUNC_TRACE();
1723 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1726 ixgbevf_dev_close(eth_dev);
1732 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1733 struct rte_pci_device *pci_dev)
1735 char name[RTE_ETH_NAME_MAX_LEN];
1736 struct rte_eth_dev *pf_ethdev;
1737 struct rte_eth_devargs eth_da;
1740 if (pci_dev->device.devargs) {
1741 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1746 memset(ð_da, 0, sizeof(eth_da));
1748 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1749 sizeof(struct ixgbe_adapter),
1750 eth_dev_pci_specific_init, pci_dev,
1751 eth_ixgbe_dev_init, NULL);
1753 if (retval || eth_da.nb_representor_ports < 1)
1756 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1757 if (pf_ethdev == NULL)
1760 /* probe VF representor ports */
1761 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1762 struct ixgbe_vf_info *vfinfo;
1763 struct ixgbe_vf_representor representor;
1765 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1766 pf_ethdev->data->dev_private);
1767 if (vfinfo == NULL) {
1769 "no virtual functions supported by PF");
1773 representor.vf_id = eth_da.representor_ports[i];
1774 representor.switch_domain_id = vfinfo->switch_domain_id;
1775 representor.pf_ethdev = pf_ethdev;
1777 /* representor port net_bdf_port */
1778 snprintf(name, sizeof(name), "net_%s_representor_%d",
1779 pci_dev->device.name,
1780 eth_da.representor_ports[i]);
1782 retval = rte_eth_dev_create(&pci_dev->device, name,
1783 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1784 ixgbe_vf_representor_init, &representor);
1787 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1788 "representor %s.", name);
1794 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1796 struct rte_eth_dev *ethdev;
1798 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1802 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1803 return rte_eth_dev_pci_generic_remove(pci_dev,
1804 ixgbe_vf_representor_uninit);
1806 return rte_eth_dev_pci_generic_remove(pci_dev,
1807 eth_ixgbe_dev_uninit);
1810 static struct rte_pci_driver rte_ixgbe_pmd = {
1811 .id_table = pci_id_ixgbe_map,
1812 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1813 .probe = eth_ixgbe_pci_probe,
1814 .remove = eth_ixgbe_pci_remove,
1817 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1818 struct rte_pci_device *pci_dev)
1820 return rte_eth_dev_pci_generic_probe(pci_dev,
1821 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1824 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1826 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1830 * virtual function driver struct
1832 static struct rte_pci_driver rte_ixgbevf_pmd = {
1833 .id_table = pci_id_ixgbevf_map,
1834 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1835 .probe = eth_ixgbevf_pci_probe,
1836 .remove = eth_ixgbevf_pci_remove,
1840 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1842 struct ixgbe_hw *hw =
1843 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1844 struct ixgbe_vfta *shadow_vfta =
1845 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1850 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1851 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1852 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1857 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1859 /* update local VFTA copy */
1860 shadow_vfta->vfta[vid_idx] = vfta;
1866 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1869 ixgbe_vlan_hw_strip_enable(dev, queue);
1871 ixgbe_vlan_hw_strip_disable(dev, queue);
1875 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1876 enum rte_vlan_type vlan_type,
1879 struct ixgbe_hw *hw =
1880 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1885 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886 qinq &= IXGBE_DMATXCTL_GDV;
1888 switch (vlan_type) {
1889 case ETH_VLAN_TYPE_INNER:
1891 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1892 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1893 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1894 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1895 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1896 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1897 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1900 PMD_DRV_LOG(ERR, "Inner type is not supported"
1904 case ETH_VLAN_TYPE_OUTER:
1906 /* Only the high 16-bits is valid */
1907 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1908 IXGBE_EXVET_VET_EXT_SHIFT);
1910 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1911 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1912 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1913 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1914 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1915 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1916 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1922 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1930 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1932 struct ixgbe_hw *hw =
1933 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1936 PMD_INIT_FUNC_TRACE();
1938 /* Filter Table Disable */
1939 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1940 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1942 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1946 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1948 struct ixgbe_hw *hw =
1949 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950 struct ixgbe_vfta *shadow_vfta =
1951 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1955 PMD_INIT_FUNC_TRACE();
1957 /* Filter Table Enable */
1958 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1959 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1960 vlnctrl |= IXGBE_VLNCTRL_VFE;
1962 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1964 /* write whatever is in local vfta copy */
1965 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1966 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1970 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1972 struct ixgbe_hwstrip *hwstrip =
1973 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1974 struct ixgbe_rx_queue *rxq;
1976 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1980 IXGBE_SET_HWSTRIP(hwstrip, queue);
1982 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1984 if (queue >= dev->data->nb_rx_queues)
1987 rxq = dev->data->rx_queues[queue];
1990 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1991 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1993 rxq->vlan_flags = PKT_RX_VLAN;
1994 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1999 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2001 struct ixgbe_hw *hw =
2002 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005 PMD_INIT_FUNC_TRACE();
2007 if (hw->mac.type == ixgbe_mac_82598EB) {
2008 /* No queue level support */
2009 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2013 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2014 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2015 ctrl &= ~IXGBE_RXDCTL_VME;
2016 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2018 /* record those setting for HW strip per queue */
2019 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2023 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2025 struct ixgbe_hw *hw =
2026 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029 PMD_INIT_FUNC_TRACE();
2031 if (hw->mac.type == ixgbe_mac_82598EB) {
2032 /* No queue level supported */
2033 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2037 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2038 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2039 ctrl |= IXGBE_RXDCTL_VME;
2040 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2042 /* record those setting for HW strip per queue */
2043 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2047 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2049 struct ixgbe_hw *hw =
2050 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 PMD_INIT_FUNC_TRACE();
2055 /* DMATXCTRL: Geric Double VLAN Disable */
2056 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2057 ctrl &= ~IXGBE_DMATXCTL_GDV;
2058 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2060 /* CTRL_EXT: Global Double VLAN Disable */
2061 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2062 ctrl &= ~IXGBE_EXTENDED_VLAN;
2063 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2068 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2070 struct ixgbe_hw *hw =
2071 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2074 PMD_INIT_FUNC_TRACE();
2076 /* DMATXCTRL: Geric Double VLAN Enable */
2077 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2078 ctrl |= IXGBE_DMATXCTL_GDV;
2079 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2081 /* CTRL_EXT: Global Double VLAN Enable */
2082 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2083 ctrl |= IXGBE_EXTENDED_VLAN;
2084 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2086 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2087 if (hw->mac.type == ixgbe_mac_X550 ||
2088 hw->mac.type == ixgbe_mac_X550EM_x ||
2089 hw->mac.type == ixgbe_mac_X550EM_a) {
2090 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2091 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2092 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2096 * VET EXT field in the EXVET register = 0x8100 by default
2097 * So no need to change. Same to VT field of DMATXCTL register
2102 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2104 struct ixgbe_hw *hw =
2105 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2109 struct ixgbe_rx_queue *rxq;
2112 PMD_INIT_FUNC_TRACE();
2114 if (hw->mac.type == ixgbe_mac_82598EB) {
2115 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2116 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2117 ctrl |= IXGBE_VLNCTRL_VME;
2118 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2120 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2121 ctrl &= ~IXGBE_VLNCTRL_VME;
2122 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2126 * Other 10G NIC, the VLAN strip can be setup
2127 * per queue in RXDCTL
2129 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2130 rxq = dev->data->rx_queues[i];
2131 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2132 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2133 ctrl |= IXGBE_RXDCTL_VME;
2136 ctrl &= ~IXGBE_RXDCTL_VME;
2139 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2141 /* record those setting for HW strip per queue */
2142 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2148 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2151 struct rte_eth_rxmode *rxmode;
2152 struct ixgbe_rx_queue *rxq;
2154 if (mask & ETH_VLAN_STRIP_MASK) {
2155 rxmode = &dev->data->dev_conf.rxmode;
2156 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2157 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2158 rxq = dev->data->rx_queues[i];
2159 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2162 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2163 rxq = dev->data->rx_queues[i];
2164 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2170 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2172 struct rte_eth_rxmode *rxmode;
2173 rxmode = &dev->data->dev_conf.rxmode;
2175 if (mask & ETH_VLAN_STRIP_MASK) {
2176 ixgbe_vlan_hw_strip_config(dev);
2179 if (mask & ETH_VLAN_FILTER_MASK) {
2180 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2181 ixgbe_vlan_hw_filter_enable(dev);
2183 ixgbe_vlan_hw_filter_disable(dev);
2186 if (mask & ETH_VLAN_EXTEND_MASK) {
2187 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2188 ixgbe_vlan_hw_extend_enable(dev);
2190 ixgbe_vlan_hw_extend_disable(dev);
2197 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2199 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2201 ixgbe_vlan_offload_config(dev, mask);
2207 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2209 struct ixgbe_hw *hw =
2210 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2211 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2212 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2214 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2215 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2219 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2221 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2226 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2229 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2235 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2236 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2237 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2238 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2243 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2245 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2246 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2248 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2250 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2251 /* check multi-queue mode */
2252 switch (dev_conf->rxmode.mq_mode) {
2253 case ETH_MQ_RX_VMDQ_DCB:
2254 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2256 case ETH_MQ_RX_VMDQ_DCB_RSS:
2257 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2258 PMD_INIT_LOG(ERR, "SRIOV active,"
2259 " unsupported mq_mode rx %d.",
2260 dev_conf->rxmode.mq_mode);
2263 case ETH_MQ_RX_VMDQ_RSS:
2264 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2265 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2266 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2267 PMD_INIT_LOG(ERR, "SRIOV is active,"
2268 " invalid queue number"
2269 " for VMDQ RSS, allowed"
2270 " value are 1, 2 or 4.");
2274 case ETH_MQ_RX_VMDQ_ONLY:
2275 case ETH_MQ_RX_NONE:
2276 /* if nothing mq mode configure, use default scheme */
2277 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2279 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2280 /* SRIOV only works in VMDq enable mode */
2281 PMD_INIT_LOG(ERR, "SRIOV is active,"
2282 " wrong mq_mode rx %d.",
2283 dev_conf->rxmode.mq_mode);
2287 switch (dev_conf->txmode.mq_mode) {
2288 case ETH_MQ_TX_VMDQ_DCB:
2289 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2290 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2292 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2293 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2297 /* check valid queue number */
2298 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2299 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2300 PMD_INIT_LOG(ERR, "SRIOV is active,"
2301 " nb_rx_q=%d nb_tx_q=%d queue number"
2302 " must be less than or equal to %d.",
2304 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2308 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2309 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2313 /* check configuration for vmdb+dcb mode */
2314 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2315 const struct rte_eth_vmdq_dcb_conf *conf;
2317 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2318 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2319 IXGBE_VMDQ_DCB_NB_QUEUES);
2322 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2323 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2324 conf->nb_queue_pools == ETH_32_POOLS)) {
2325 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2326 " nb_queue_pools must be %d or %d.",
2327 ETH_16_POOLS, ETH_32_POOLS);
2331 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2332 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2334 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2335 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2336 IXGBE_VMDQ_DCB_NB_QUEUES);
2339 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2340 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2341 conf->nb_queue_pools == ETH_32_POOLS)) {
2342 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2343 " nb_queue_pools != %d and"
2344 " nb_queue_pools != %d.",
2345 ETH_16_POOLS, ETH_32_POOLS);
2350 /* For DCB mode check our configuration before we go further */
2351 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2352 const struct rte_eth_dcb_rx_conf *conf;
2354 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2355 if (!(conf->nb_tcs == ETH_4_TCS ||
2356 conf->nb_tcs == ETH_8_TCS)) {
2357 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2358 " and nb_tcs != %d.",
2359 ETH_4_TCS, ETH_8_TCS);
2364 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2365 const struct rte_eth_dcb_tx_conf *conf;
2367 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2368 if (!(conf->nb_tcs == ETH_4_TCS ||
2369 conf->nb_tcs == ETH_8_TCS)) {
2370 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2371 " and nb_tcs != %d.",
2372 ETH_4_TCS, ETH_8_TCS);
2378 * When DCB/VT is off, maximum number of queues changes,
2379 * except for 82598EB, which remains constant.
2381 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2382 hw->mac.type != ixgbe_mac_82598EB) {
2383 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2385 "Neither VT nor DCB are enabled, "
2387 IXGBE_NONE_MODE_TX_NB_QUEUES);
2396 ixgbe_dev_configure(struct rte_eth_dev *dev)
2398 struct ixgbe_interrupt *intr =
2399 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2400 struct ixgbe_adapter *adapter = dev->data->dev_private;
2403 PMD_INIT_FUNC_TRACE();
2405 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2406 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2408 /* multipe queue mode checking */
2409 ret = ixgbe_check_mq_mode(dev);
2411 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2416 /* set flag to update link status after init */
2417 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2420 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2421 * allocation or vector Rx preconditions we will reset it.
2423 adapter->rx_bulk_alloc_allowed = true;
2424 adapter->rx_vec_allowed = true;
2430 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2432 struct ixgbe_hw *hw =
2433 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2434 struct ixgbe_interrupt *intr =
2435 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2438 /* only set up it on X550EM_X */
2439 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2440 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2441 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2442 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2443 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2444 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2449 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2450 uint16_t tx_rate, uint64_t q_msk)
2452 struct ixgbe_hw *hw;
2453 struct ixgbe_vf_info *vfinfo;
2454 struct rte_eth_link link;
2455 uint8_t nb_q_per_pool;
2456 uint32_t queue_stride;
2457 uint32_t queue_idx, idx = 0, vf_idx;
2459 uint16_t total_rate = 0;
2460 struct rte_pci_device *pci_dev;
2463 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2464 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2468 if (vf >= pci_dev->max_vfs)
2471 if (tx_rate > link.link_speed)
2477 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2478 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2479 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2480 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2481 queue_idx = vf * queue_stride;
2482 queue_end = queue_idx + nb_q_per_pool - 1;
2483 if (queue_end >= hw->mac.max_tx_queues)
2487 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2490 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2492 total_rate += vfinfo[vf_idx].tx_rate[idx];
2498 /* Store tx_rate for this vf. */
2499 for (idx = 0; idx < nb_q_per_pool; idx++) {
2500 if (((uint64_t)0x1 << idx) & q_msk) {
2501 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2502 vfinfo[vf].tx_rate[idx] = tx_rate;
2503 total_rate += tx_rate;
2507 if (total_rate > dev->data->dev_link.link_speed) {
2508 /* Reset stored TX rate of the VF if it causes exceed
2511 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2515 /* Set RTTBCNRC of each queue/pool for vf X */
2516 for (; queue_idx <= queue_end; queue_idx++) {
2518 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2526 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2528 struct ixgbe_adapter *adapter = dev->data->dev_private;
2534 err = ixgbe_fc_enable(hw);
2536 /* Not negotiated is not an error case */
2537 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2539 *check if we want to forward MAC frames - driver doesn't
2540 *have native capability to do that,
2541 *so we'll write the registers ourselves
2544 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2546 /* set or clear MFLCN.PMCF bit depending on configuration */
2547 if (adapter->mac_ctrl_frame_fwd != 0)
2548 mflcn |= IXGBE_MFLCN_PMCF;
2550 mflcn &= ~IXGBE_MFLCN_PMCF;
2552 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2553 IXGBE_WRITE_FLUSH(hw);
2561 * Configure device link speed and setup link.
2562 * It returns 0 on success.
2565 ixgbe_dev_start(struct rte_eth_dev *dev)
2567 struct ixgbe_hw *hw =
2568 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569 struct ixgbe_vf_info *vfinfo =
2570 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2571 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2572 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2573 uint32_t intr_vector = 0;
2575 bool link_up = false, negotiate = 0;
2577 uint32_t allowed_speeds = 0;
2581 uint32_t *link_speeds;
2582 struct ixgbe_tm_conf *tm_conf =
2583 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2584 struct ixgbe_macsec_setting *macsec_setting =
2585 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2587 PMD_INIT_FUNC_TRACE();
2589 /* Stop the link setup handler before resetting the HW. */
2590 ixgbe_dev_wait_setup_link_complete(dev, 0);
2592 /* disable uio/vfio intr/eventfd mapping */
2593 rte_intr_disable(intr_handle);
2596 hw->adapter_stopped = 0;
2597 ixgbe_stop_adapter(hw);
2599 /* reinitialize adapter
2600 * this calls reset and start
2602 status = ixgbe_pf_reset_hw(hw);
2605 hw->mac.ops.start_hw(hw);
2606 hw->mac.get_link_status = true;
2608 /* configure PF module if SRIOV enabled */
2609 ixgbe_pf_host_configure(dev);
2611 ixgbe_dev_phy_intr_setup(dev);
2613 /* check and configure queue intr-vector mapping */
2614 if ((rte_intr_cap_multiple(intr_handle) ||
2615 !RTE_ETH_DEV_SRIOV(dev).active) &&
2616 dev->data->dev_conf.intr_conf.rxq != 0) {
2617 intr_vector = dev->data->nb_rx_queues;
2618 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2619 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2620 IXGBE_MAX_INTR_QUEUE_NUM);
2623 if (rte_intr_efd_enable(intr_handle, intr_vector))
2627 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2628 intr_handle->intr_vec =
2629 rte_zmalloc("intr_vec",
2630 dev->data->nb_rx_queues * sizeof(int), 0);
2631 if (intr_handle->intr_vec == NULL) {
2632 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2633 " intr_vec", dev->data->nb_rx_queues);
2638 /* confiugre msix for sleep until rx interrupt */
2639 ixgbe_configure_msix(dev);
2641 /* initialize transmission unit */
2642 ixgbe_dev_tx_init(dev);
2644 /* This can fail when allocating mbufs for descriptor rings */
2645 err = ixgbe_dev_rx_init(dev);
2647 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2651 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2652 ETH_VLAN_EXTEND_MASK;
2653 err = ixgbe_vlan_offload_config(dev, mask);
2655 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2659 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2660 /* Enable vlan filtering for VMDq */
2661 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2664 /* Configure DCB hw */
2665 ixgbe_configure_dcb(dev);
2667 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2668 err = ixgbe_fdir_configure(dev);
2673 /* Restore vf rate limit */
2674 if (vfinfo != NULL) {
2675 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2676 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2677 if (vfinfo[vf].tx_rate[idx] != 0)
2678 ixgbe_set_vf_rate_limit(
2680 vfinfo[vf].tx_rate[idx],
2684 ixgbe_restore_statistics_mapping(dev);
2686 err = ixgbe_flow_ctrl_enable(dev, hw);
2688 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2692 err = ixgbe_dev_rxtx_start(dev);
2694 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2698 /* Skip link setup if loopback mode is enabled. */
2699 if (dev->data->dev_conf.lpbk_mode != 0) {
2700 err = ixgbe_check_supported_loopback_mode(dev);
2702 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2705 goto skip_link_setup;
2709 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2710 err = hw->mac.ops.setup_sfp(hw);
2715 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2716 /* Turn on the copper */
2717 ixgbe_set_phy_power(hw, true);
2719 /* Turn on the laser */
2720 ixgbe_enable_tx_laser(hw);
2723 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2726 dev->data->dev_link.link_status = link_up;
2728 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2732 switch (hw->mac.type) {
2733 case ixgbe_mac_X550:
2734 case ixgbe_mac_X550EM_x:
2735 case ixgbe_mac_X550EM_a:
2736 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2737 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2739 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2740 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2741 allowed_speeds = ETH_LINK_SPEED_10M |
2742 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2745 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2749 link_speeds = &dev->data->dev_conf.link_speeds;
2751 /* Ignore autoneg flag bit and check the validity ofÂ
2754 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2755 PMD_INIT_LOG(ERR, "Invalid link setting");
2760 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2761 switch (hw->mac.type) {
2762 case ixgbe_mac_82598EB:
2763 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2765 case ixgbe_mac_82599EB:
2766 case ixgbe_mac_X540:
2767 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2769 case ixgbe_mac_X550:
2770 case ixgbe_mac_X550EM_x:
2771 case ixgbe_mac_X550EM_a:
2772 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2775 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2778 if (*link_speeds & ETH_LINK_SPEED_10G)
2779 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2780 if (*link_speeds & ETH_LINK_SPEED_5G)
2781 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2782 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2783 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2784 if (*link_speeds & ETH_LINK_SPEED_1G)
2785 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2786 if (*link_speeds & ETH_LINK_SPEED_100M)
2787 speed |= IXGBE_LINK_SPEED_100_FULL;
2788 if (*link_speeds & ETH_LINK_SPEED_10M)
2789 speed |= IXGBE_LINK_SPEED_10_FULL;
2792 err = ixgbe_setup_link(hw, speed, link_up);
2798 if (rte_intr_allow_others(intr_handle)) {
2799 /* check if lsc interrupt is enabled */
2800 if (dev->data->dev_conf.intr_conf.lsc != 0)
2801 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2803 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2804 ixgbe_dev_macsec_interrupt_setup(dev);
2806 rte_intr_callback_unregister(intr_handle,
2807 ixgbe_dev_interrupt_handler, dev);
2808 if (dev->data->dev_conf.intr_conf.lsc != 0)
2809 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2810 " no intr multiplex");
2813 /* check if rxq interrupt is enabled */
2814 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2815 rte_intr_dp_is_en(intr_handle))
2816 ixgbe_dev_rxq_interrupt_setup(dev);
2818 /* enable uio/vfio intr/eventfd mapping */
2819 rte_intr_enable(intr_handle);
2821 /* resume enabled intr since hw reset */
2822 ixgbe_enable_intr(dev);
2823 ixgbe_l2_tunnel_conf(dev);
2824 ixgbe_filter_restore(dev);
2826 if (tm_conf->root && !tm_conf->committed)
2827 PMD_DRV_LOG(WARNING,
2828 "please call hierarchy_commit() "
2829 "before starting the port");
2831 /* wait for the controller to acquire link */
2832 err = ixgbe_wait_for_link_up(hw);
2837 * Update link status right before return, because it may
2838 * start link configuration process in a separate thread.
2840 ixgbe_dev_link_update(dev, 0);
2842 /* setup the macsec setting register */
2843 if (macsec_setting->offload_en)
2844 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2849 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2850 ixgbe_dev_clear_queues(dev);
2855 * Stop device: disable rx and tx functions to allow for reconfiguring.
2858 ixgbe_dev_stop(struct rte_eth_dev *dev)
2860 struct rte_eth_link link;
2861 struct ixgbe_adapter *adapter = dev->data->dev_private;
2862 struct ixgbe_hw *hw =
2863 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2864 struct ixgbe_vf_info *vfinfo =
2865 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2866 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2867 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2869 struct ixgbe_tm_conf *tm_conf =
2870 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2872 if (hw->adapter_stopped)
2875 PMD_INIT_FUNC_TRACE();
2877 ixgbe_dev_wait_setup_link_complete(dev, 0);
2879 /* disable interrupts */
2880 ixgbe_disable_intr(hw);
2883 ixgbe_pf_reset_hw(hw);
2884 hw->adapter_stopped = 0;
2887 ixgbe_stop_adapter(hw);
2889 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2890 vfinfo[vf].clear_to_send = false;
2892 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2893 /* Turn off the copper */
2894 ixgbe_set_phy_power(hw, false);
2896 /* Turn off the laser */
2897 ixgbe_disable_tx_laser(hw);
2900 ixgbe_dev_clear_queues(dev);
2902 /* Clear stored conf */
2903 dev->data->scattered_rx = 0;
2906 /* Clear recorded link status */
2907 memset(&link, 0, sizeof(link));
2908 rte_eth_linkstatus_set(dev, &link);
2910 if (!rte_intr_allow_others(intr_handle))
2911 /* resume to the default handler */
2912 rte_intr_callback_register(intr_handle,
2913 ixgbe_dev_interrupt_handler,
2916 /* Clean datapath event and queue/vec mapping */
2917 rte_intr_efd_disable(intr_handle);
2918 if (intr_handle->intr_vec != NULL) {
2919 rte_free(intr_handle->intr_vec);
2920 intr_handle->intr_vec = NULL;
2923 /* reset hierarchy commit */
2924 tm_conf->committed = false;
2926 adapter->rss_reta_updated = 0;
2928 hw->adapter_stopped = true;
2929 dev->data->dev_started = 0;
2935 * Set device link up: enable tx.
2938 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2940 struct ixgbe_hw *hw =
2941 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2942 if (hw->mac.type == ixgbe_mac_82599EB) {
2943 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2944 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2945 /* Not suported in bypass mode */
2946 PMD_INIT_LOG(ERR, "Set link up is not supported "
2947 "by device id 0x%x", hw->device_id);
2953 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2954 /* Turn on the copper */
2955 ixgbe_set_phy_power(hw, true);
2957 /* Turn on the laser */
2958 ixgbe_enable_tx_laser(hw);
2959 ixgbe_dev_link_update(dev, 0);
2966 * Set device link down: disable tx.
2969 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2971 struct ixgbe_hw *hw =
2972 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2973 if (hw->mac.type == ixgbe_mac_82599EB) {
2974 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2975 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2976 /* Not suported in bypass mode */
2977 PMD_INIT_LOG(ERR, "Set link down is not supported "
2978 "by device id 0x%x", hw->device_id);
2984 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2985 /* Turn off the copper */
2986 ixgbe_set_phy_power(hw, false);
2988 /* Turn off the laser */
2989 ixgbe_disable_tx_laser(hw);
2990 ixgbe_dev_link_update(dev, 0);
2997 * Reset and stop device.
3000 ixgbe_dev_close(struct rte_eth_dev *dev)
3002 struct ixgbe_hw *hw =
3003 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3005 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3009 PMD_INIT_FUNC_TRACE();
3010 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3013 ixgbe_pf_reset_hw(hw);
3015 ret = ixgbe_dev_stop(dev);
3017 ixgbe_dev_free_queues(dev);
3019 ixgbe_disable_pcie_master(hw);
3021 /* reprogram the RAR[0] in case user changed it. */
3022 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3024 /* Unlock any pending hardware semaphore */
3025 ixgbe_swfw_lock_reset(hw);
3027 /* disable uio intr before callback unregister */
3028 rte_intr_disable(intr_handle);
3031 ret = rte_intr_callback_unregister(intr_handle,
3032 ixgbe_dev_interrupt_handler, dev);
3033 if (ret >= 0 || ret == -ENOENT) {
3035 } else if (ret != -EAGAIN) {
3037 "intr callback unregister failed: %d",
3041 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3043 /* cancel the delay handler before remove dev */
3044 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3046 /* uninitialize PF if max_vfs not zero */
3047 ixgbe_pf_host_uninit(dev);
3049 /* remove all the fdir filters & hash */
3050 ixgbe_fdir_filter_uninit(dev);
3052 /* remove all the L2 tunnel filters & hash */
3053 ixgbe_l2_tn_filter_uninit(dev);
3055 /* Remove all ntuple filters of the device */
3056 ixgbe_ntuple_filter_uninit(dev);
3058 /* clear all the filters list */
3059 ixgbe_filterlist_flush();
3061 /* Remove all Traffic Manager configuration */
3062 ixgbe_tm_conf_uninit(dev);
3064 #ifdef RTE_LIB_SECURITY
3065 rte_free(dev->security_ctx);
3075 ixgbe_dev_reset(struct rte_eth_dev *dev)
3079 /* When a DPDK PMD PF begin to reset PF port, it should notify all
3080 * its VF to make them align with it. The detailed notification
3081 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3082 * To avoid unexpected behavior in VF, currently reset of PF with
3083 * SR-IOV activation is not supported. It might be supported later.
3085 if (dev->data->sriov.active)
3088 ret = eth_ixgbe_dev_uninit(dev);
3092 ret = eth_ixgbe_dev_init(dev, NULL);
3098 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3099 struct ixgbe_hw_stats *hw_stats,
3100 struct ixgbe_macsec_stats *macsec_stats,
3101 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3102 uint64_t *total_qprc, uint64_t *total_qprdc)
3104 uint32_t bprc, lxon, lxoff, total;
3105 uint32_t delta_gprc = 0;
3107 /* Workaround for RX byte count not including CRC bytes when CRC
3108 * strip is enabled. CRC bytes are removed from counters when crc_strip
3111 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3112 IXGBE_HLREG0_RXCRCSTRP);
3114 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3115 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3116 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3117 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3119 for (i = 0; i < 8; i++) {
3120 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3122 /* global total per queue */
3123 hw_stats->mpc[i] += mp;
3124 /* Running comprehensive total for stats display */
3125 *total_missed_rx += hw_stats->mpc[i];
3126 if (hw->mac.type == ixgbe_mac_82598EB) {
3127 hw_stats->rnbc[i] +=
3128 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3129 hw_stats->pxonrxc[i] +=
3130 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3131 hw_stats->pxoffrxc[i] +=
3132 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3134 hw_stats->pxonrxc[i] +=
3135 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3136 hw_stats->pxoffrxc[i] +=
3137 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3138 hw_stats->pxon2offc[i] +=
3139 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3141 hw_stats->pxontxc[i] +=
3142 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3143 hw_stats->pxofftxc[i] +=
3144 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3146 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3147 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3148 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3149 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3151 delta_gprc += delta_qprc;
3153 hw_stats->qprc[i] += delta_qprc;
3154 hw_stats->qptc[i] += delta_qptc;
3156 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3157 hw_stats->qbrc[i] +=
3158 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3160 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3162 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3163 hw_stats->qbtc[i] +=
3164 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3166 hw_stats->qprdc[i] += delta_qprdc;
3167 *total_qprdc += hw_stats->qprdc[i];
3169 *total_qprc += hw_stats->qprc[i];
3170 *total_qbrc += hw_stats->qbrc[i];
3172 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3173 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3174 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3177 * An errata states that gprc actually counts good + missed packets:
3178 * Workaround to set gprc to summated queue packet receives
3180 hw_stats->gprc = *total_qprc;
3182 if (hw->mac.type != ixgbe_mac_82598EB) {
3183 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3184 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3185 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3186 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3187 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3188 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3189 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3190 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3192 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3193 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3194 /* 82598 only has a counter in the high register */
3195 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3196 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3197 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3199 uint64_t old_tpr = hw_stats->tpr;
3201 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3202 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3205 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3207 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3208 hw_stats->gptc += delta_gptc;
3209 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3210 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3213 * Workaround: mprc hardware is incorrectly counting
3214 * broadcasts, so for now we subtract those.
3216 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3217 hw_stats->bprc += bprc;
3218 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3219 if (hw->mac.type == ixgbe_mac_82598EB)
3220 hw_stats->mprc -= bprc;
3222 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3223 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3224 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3225 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3226 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3227 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3229 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3230 hw_stats->lxontxc += lxon;
3231 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3232 hw_stats->lxofftxc += lxoff;
3233 total = lxon + lxoff;
3235 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3236 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3237 hw_stats->gptc -= total;
3238 hw_stats->mptc -= total;
3239 hw_stats->ptc64 -= total;
3240 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3242 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3243 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3244 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3245 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3246 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3247 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3248 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3249 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3250 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3251 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3252 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3253 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3254 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3255 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3256 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3257 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3258 /* Only read FCOE on 82599 */
3259 if (hw->mac.type != ixgbe_mac_82598EB) {
3260 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3261 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3262 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3263 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3264 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3267 /* Flow Director Stats registers */
3268 if (hw->mac.type != ixgbe_mac_82598EB) {
3269 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3270 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3271 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3272 IXGBE_FDIRUSTAT) & 0xFFFF;
3273 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3274 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3275 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3276 IXGBE_FDIRFSTAT) & 0xFFFF;
3277 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3278 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3280 /* MACsec Stats registers */
3281 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3282 macsec_stats->out_pkts_encrypted +=
3283 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3284 macsec_stats->out_pkts_protected +=
3285 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3286 macsec_stats->out_octets_encrypted +=
3287 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3288 macsec_stats->out_octets_protected +=
3289 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3290 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3291 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3292 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3293 macsec_stats->in_pkts_unknownsci +=
3294 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3295 macsec_stats->in_octets_decrypted +=
3296 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3297 macsec_stats->in_octets_validated +=
3298 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3299 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3300 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3301 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3302 for (i = 0; i < 2; i++) {
3303 macsec_stats->in_pkts_ok +=
3304 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3305 macsec_stats->in_pkts_invalid +=
3306 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3307 macsec_stats->in_pkts_notvalid +=
3308 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3310 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3311 macsec_stats->in_pkts_notusingsa +=
3312 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3316 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3319 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3321 struct ixgbe_hw *hw =
3322 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3323 struct ixgbe_hw_stats *hw_stats =
3324 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3325 struct ixgbe_macsec_stats *macsec_stats =
3326 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3327 dev->data->dev_private);
3328 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3331 total_missed_rx = 0;
3336 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3337 &total_qbrc, &total_qprc, &total_qprdc);
3342 /* Fill out the rte_eth_stats statistics structure */
3343 stats->ipackets = total_qprc;
3344 stats->ibytes = total_qbrc;
3345 stats->opackets = hw_stats->gptc;
3346 stats->obytes = hw_stats->gotc;
3348 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3349 stats->q_ipackets[i] = hw_stats->qprc[i];
3350 stats->q_opackets[i] = hw_stats->qptc[i];
3351 stats->q_ibytes[i] = hw_stats->qbrc[i];
3352 stats->q_obytes[i] = hw_stats->qbtc[i];
3353 stats->q_errors[i] = hw_stats->qprdc[i];
3357 stats->imissed = total_missed_rx;
3358 stats->ierrors = hw_stats->crcerrs +
3375 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3377 struct ixgbe_hw_stats *stats =
3378 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3380 /* HW registers are cleared on read */
3381 ixgbe_dev_stats_get(dev, NULL);
3383 /* Reset software totals */
3384 memset(stats, 0, sizeof(*stats));
3389 /* This function calculates the number of xstats based on the current config */
3391 ixgbe_xstats_calc_num(void) {
3392 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3393 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3394 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3397 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3398 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3400 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3401 unsigned stat, i, count;
3403 if (xstats_names != NULL) {
3406 /* Note: limit >= cnt_stats checked upstream
3407 * in rte_eth_xstats_names()
3410 /* Extended stats from ixgbe_hw_stats */
3411 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3412 strlcpy(xstats_names[count].name,
3413 rte_ixgbe_stats_strings[i].name,
3414 sizeof(xstats_names[count].name));
3419 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3420 strlcpy(xstats_names[count].name,
3421 rte_ixgbe_macsec_strings[i].name,
3422 sizeof(xstats_names[count].name));
3426 /* RX Priority Stats */
3427 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3428 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3429 snprintf(xstats_names[count].name,
3430 sizeof(xstats_names[count].name),
3431 "rx_priority%u_%s", i,
3432 rte_ixgbe_rxq_strings[stat].name);
3437 /* TX Priority Stats */
3438 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3439 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3440 snprintf(xstats_names[count].name,
3441 sizeof(xstats_names[count].name),
3442 "tx_priority%u_%s", i,
3443 rte_ixgbe_txq_strings[stat].name);
3451 static int ixgbe_dev_xstats_get_names_by_id(
3452 struct rte_eth_dev *dev,
3453 struct rte_eth_xstat_name *xstats_names,
3454 const uint64_t *ids,
3458 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3459 unsigned int stat, i, count;
3461 if (xstats_names != NULL) {
3464 /* Note: limit >= cnt_stats checked upstream
3465 * in rte_eth_xstats_names()
3468 /* Extended stats from ixgbe_hw_stats */
3469 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3470 strlcpy(xstats_names[count].name,
3471 rte_ixgbe_stats_strings[i].name,
3472 sizeof(xstats_names[count].name));
3477 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3478 strlcpy(xstats_names[count].name,
3479 rte_ixgbe_macsec_strings[i].name,
3480 sizeof(xstats_names[count].name));
3484 /* RX Priority Stats */
3485 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3486 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3487 snprintf(xstats_names[count].name,
3488 sizeof(xstats_names[count].name),
3489 "rx_priority%u_%s", i,
3490 rte_ixgbe_rxq_strings[stat].name);
3495 /* TX Priority Stats */
3496 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3497 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3498 snprintf(xstats_names[count].name,
3499 sizeof(xstats_names[count].name),
3500 "tx_priority%u_%s", i,
3501 rte_ixgbe_txq_strings[stat].name);
3510 uint16_t size = ixgbe_xstats_calc_num();
3511 struct rte_eth_xstat_name xstats_names_copy[size];
3513 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3516 for (i = 0; i < limit; i++) {
3517 if (ids[i] >= size) {
3518 PMD_INIT_LOG(ERR, "id value isn't valid");
3521 strcpy(xstats_names[i].name,
3522 xstats_names_copy[ids[i]].name);
3527 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3528 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3532 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3535 if (xstats_names != NULL)
3536 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3537 strlcpy(xstats_names[i].name,
3538 rte_ixgbevf_stats_strings[i].name,
3539 sizeof(xstats_names[i].name));
3540 return IXGBEVF_NB_XSTATS;
3544 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3547 struct ixgbe_hw *hw =
3548 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3549 struct ixgbe_hw_stats *hw_stats =
3550 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3551 struct ixgbe_macsec_stats *macsec_stats =
3552 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3553 dev->data->dev_private);
3554 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3555 unsigned i, stat, count = 0;
3557 count = ixgbe_xstats_calc_num();
3562 total_missed_rx = 0;
3567 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3568 &total_qbrc, &total_qprc, &total_qprdc);
3570 /* If this is a reset xstats is NULL, and we have cleared the
3571 * registers by reading them.
3576 /* Extended stats from ixgbe_hw_stats */
3578 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3579 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3580 rte_ixgbe_stats_strings[i].offset);
3581 xstats[count].id = count;
3586 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3587 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3588 rte_ixgbe_macsec_strings[i].offset);
3589 xstats[count].id = count;
3593 /* RX Priority Stats */
3594 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3595 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3596 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3597 rte_ixgbe_rxq_strings[stat].offset +
3598 (sizeof(uint64_t) * i));
3599 xstats[count].id = count;
3604 /* TX Priority Stats */
3605 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3606 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3607 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3608 rte_ixgbe_txq_strings[stat].offset +
3609 (sizeof(uint64_t) * i));
3610 xstats[count].id = count;
3618 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3619 uint64_t *values, unsigned int n)
3622 struct ixgbe_hw *hw =
3623 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3624 struct ixgbe_hw_stats *hw_stats =
3625 IXGBE_DEV_PRIVATE_TO_STATS(
3626 dev->data->dev_private);
3627 struct ixgbe_macsec_stats *macsec_stats =
3628 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3629 dev->data->dev_private);
3630 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3631 unsigned int i, stat, count = 0;
3633 count = ixgbe_xstats_calc_num();
3635 if (!ids && n < count)
3638 total_missed_rx = 0;
3643 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3644 &total_missed_rx, &total_qbrc, &total_qprc,
3647 /* If this is a reset xstats is NULL, and we have cleared the
3648 * registers by reading them.
3650 if (!ids && !values)
3653 /* Extended stats from ixgbe_hw_stats */
3655 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3656 values[count] = *(uint64_t *)(((char *)hw_stats) +
3657 rte_ixgbe_stats_strings[i].offset);
3662 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3663 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3664 rte_ixgbe_macsec_strings[i].offset);
3668 /* RX Priority Stats */
3669 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3670 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3672 *(uint64_t *)(((char *)hw_stats) +
3673 rte_ixgbe_rxq_strings[stat].offset +
3674 (sizeof(uint64_t) * i));
3679 /* TX Priority Stats */
3680 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3681 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3683 *(uint64_t *)(((char *)hw_stats) +
3684 rte_ixgbe_txq_strings[stat].offset +
3685 (sizeof(uint64_t) * i));
3693 uint16_t size = ixgbe_xstats_calc_num();
3694 uint64_t values_copy[size];
3696 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3698 for (i = 0; i < n; i++) {
3699 if (ids[i] >= size) {
3700 PMD_INIT_LOG(ERR, "id value isn't valid");
3703 values[i] = values_copy[ids[i]];
3709 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3711 struct ixgbe_hw_stats *stats =
3712 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3713 struct ixgbe_macsec_stats *macsec_stats =
3714 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3715 dev->data->dev_private);
3717 unsigned count = ixgbe_xstats_calc_num();
3719 /* HW registers are cleared on read */
3720 ixgbe_dev_xstats_get(dev, NULL, count);
3722 /* Reset software totals */
3723 memset(stats, 0, sizeof(*stats));
3724 memset(macsec_stats, 0, sizeof(*macsec_stats));
3730 ixgbevf_update_stats(struct rte_eth_dev *dev)
3732 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3733 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3734 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3736 /* Good Rx packet, include VF loopback */
3737 UPDATE_VF_STAT(IXGBE_VFGPRC,
3738 hw_stats->last_vfgprc, hw_stats->vfgprc);
3740 /* Good Rx octets, include VF loopback */
3741 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3742 hw_stats->last_vfgorc, hw_stats->vfgorc);
3744 /* Good Tx packet, include VF loopback */
3745 UPDATE_VF_STAT(IXGBE_VFGPTC,
3746 hw_stats->last_vfgptc, hw_stats->vfgptc);
3748 /* Good Tx octets, include VF loopback */
3749 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3750 hw_stats->last_vfgotc, hw_stats->vfgotc);
3752 /* Rx Multicst Packet */
3753 UPDATE_VF_STAT(IXGBE_VFMPRC,
3754 hw_stats->last_vfmprc, hw_stats->vfmprc);
3758 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3761 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3762 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3765 if (n < IXGBEVF_NB_XSTATS)
3766 return IXGBEVF_NB_XSTATS;
3768 ixgbevf_update_stats(dev);
3773 /* Extended stats */
3774 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3776 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3777 rte_ixgbevf_stats_strings[i].offset);
3780 return IXGBEVF_NB_XSTATS;
3784 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3786 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3787 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3789 ixgbevf_update_stats(dev);
3794 stats->ipackets = hw_stats->vfgprc;
3795 stats->ibytes = hw_stats->vfgorc;
3796 stats->opackets = hw_stats->vfgptc;
3797 stats->obytes = hw_stats->vfgotc;
3802 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3804 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3805 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3807 /* Sync HW register to the last stats */
3808 ixgbevf_dev_stats_get(dev, NULL);
3810 /* reset HW current stats*/
3811 hw_stats->vfgprc = 0;
3812 hw_stats->vfgorc = 0;
3813 hw_stats->vfgptc = 0;
3814 hw_stats->vfgotc = 0;
3820 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3822 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3823 u16 eeprom_verh, eeprom_verl;
3827 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3828 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3830 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3831 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3833 ret += 1; /* add the size of '\0' */
3834 if (fw_size < (u32)ret)
3841 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3843 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3844 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3845 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3847 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3848 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3849 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3851 * When DCB/VT is off, maximum number of queues changes,
3852 * except for 82598EB, which remains constant.
3854 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3855 hw->mac.type != ixgbe_mac_82598EB)
3856 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3858 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3859 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3860 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3861 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3862 dev_info->max_vfs = pci_dev->max_vfs;
3863 if (hw->mac.type == ixgbe_mac_82598EB)
3864 dev_info->max_vmdq_pools = ETH_16_POOLS;
3866 dev_info->max_vmdq_pools = ETH_64_POOLS;
3867 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3868 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3869 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3870 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3871 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3872 dev_info->rx_queue_offload_capa);
3873 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3874 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3876 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3878 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3879 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3880 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3882 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3887 dev_info->default_txconf = (struct rte_eth_txconf) {
3889 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3890 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3891 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3893 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3894 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3898 dev_info->rx_desc_lim = rx_desc_lim;
3899 dev_info->tx_desc_lim = tx_desc_lim;
3901 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3902 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3903 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3905 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3906 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3907 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3908 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3909 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3911 if (hw->mac.type == ixgbe_mac_X540 ||
3912 hw->mac.type == ixgbe_mac_X540_vf ||
3913 hw->mac.type == ixgbe_mac_X550 ||
3914 hw->mac.type == ixgbe_mac_X550_vf) {
3915 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3917 if (hw->mac.type == ixgbe_mac_X550) {
3918 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3919 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3922 /* Driver-preferred Rx/Tx parameters */
3923 dev_info->default_rxportconf.burst_size = 32;
3924 dev_info->default_txportconf.burst_size = 32;
3925 dev_info->default_rxportconf.nb_queues = 1;
3926 dev_info->default_txportconf.nb_queues = 1;
3927 dev_info->default_rxportconf.ring_size = 256;
3928 dev_info->default_txportconf.ring_size = 256;
3933 static const uint32_t *
3934 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3936 static const uint32_t ptypes[] = {
3937 /* For non-vec functions,
3938 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3939 * for vec functions,
3940 * refers to _recv_raw_pkts_vec().
3944 RTE_PTYPE_L3_IPV4_EXT,
3946 RTE_PTYPE_L3_IPV6_EXT,
3950 RTE_PTYPE_TUNNEL_IP,
3951 RTE_PTYPE_INNER_L3_IPV6,
3952 RTE_PTYPE_INNER_L3_IPV6_EXT,
3953 RTE_PTYPE_INNER_L4_TCP,
3954 RTE_PTYPE_INNER_L4_UDP,
3958 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3959 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3960 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3961 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3964 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3965 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3966 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3973 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3974 struct rte_eth_dev_info *dev_info)
3976 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3977 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3979 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3980 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3981 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3982 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3983 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3984 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3985 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3986 dev_info->max_vfs = pci_dev->max_vfs;
3987 if (hw->mac.type == ixgbe_mac_82598EB)
3988 dev_info->max_vmdq_pools = ETH_16_POOLS;
3990 dev_info->max_vmdq_pools = ETH_64_POOLS;
3991 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3992 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3993 dev_info->rx_queue_offload_capa);
3994 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3995 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3996 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3997 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3998 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
4000 dev_info->default_rxconf = (struct rte_eth_rxconf) {
4002 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
4003 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
4004 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
4006 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4011 dev_info->default_txconf = (struct rte_eth_txconf) {
4013 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4014 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4015 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4017 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4018 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4022 dev_info->rx_desc_lim = rx_desc_lim;
4023 dev_info->tx_desc_lim = tx_desc_lim;
4029 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4030 bool *link_up, int wait_to_complete)
4032 struct ixgbe_adapter *adapter = container_of(hw,
4033 struct ixgbe_adapter, hw);
4034 struct ixgbe_mbx_info *mbx = &hw->mbx;
4035 struct ixgbe_mac_info *mac = &hw->mac;
4036 uint32_t links_reg, in_msg;
4039 /* If we were hit with a reset drop the link */
4040 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4041 mac->get_link_status = true;
4043 if (!mac->get_link_status)
4046 /* if link status is down no point in checking to see if pf is up */
4047 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4048 if (!(links_reg & IXGBE_LINKS_UP))
4051 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4052 * before the link status is correct
4054 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4057 for (i = 0; i < 5; i++) {
4059 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4061 if (!(links_reg & IXGBE_LINKS_UP))
4066 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4067 case IXGBE_LINKS_SPEED_10G_82599:
4068 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4069 if (hw->mac.type >= ixgbe_mac_X550) {
4070 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4071 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4074 case IXGBE_LINKS_SPEED_1G_82599:
4075 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4077 case IXGBE_LINKS_SPEED_100_82599:
4078 *speed = IXGBE_LINK_SPEED_100_FULL;
4079 if (hw->mac.type == ixgbe_mac_X550) {
4080 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4081 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4084 case IXGBE_LINKS_SPEED_10_X550EM_A:
4085 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4086 /* Since Reserved in older MAC's */
4087 if (hw->mac.type >= ixgbe_mac_X550)
4088 *speed = IXGBE_LINK_SPEED_10_FULL;
4091 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4094 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4095 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4096 mac->get_link_status = true;
4098 mac->get_link_status = false;
4103 /* if the read failed it could just be a mailbox collision, best wait
4104 * until we are called again and don't report an error
4106 if (mbx->ops.read(hw, &in_msg, 1, 0))
4109 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4110 /* msg is not CTS and is NACK we must have lost CTS status */
4111 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4112 mac->get_link_status = false;
4116 /* the pf is talking, if we timed out in the past we reinit */
4117 if (!mbx->timeout) {
4122 /* if we passed all the tests above then the link is up and we no
4123 * longer need to check for link
4125 mac->get_link_status = false;
4128 *link_up = !mac->get_link_status;
4133 * If @timeout_ms was 0, it means that it will not return until link complete.
4134 * It returns 1 on complete, return 0 on timeout.
4137 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4139 #define WARNING_TIMEOUT 9000 /* 9s in total */
4140 struct ixgbe_adapter *ad = dev->data->dev_private;
4141 uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4143 while (rte_atomic32_read(&ad->link_thread_running)) {
4150 } else if (!timeout) {
4151 /* It will not return until link complete */
4152 timeout = WARNING_TIMEOUT;
4153 PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4161 ixgbe_dev_setup_link_thread_handler(void *param)
4163 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4164 struct ixgbe_adapter *ad = dev->data->dev_private;
4165 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4166 struct ixgbe_interrupt *intr =
4167 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4169 bool autoneg = false;
4171 pthread_detach(pthread_self());
4172 speed = hw->phy.autoneg_advertised;
4174 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4176 ixgbe_setup_link(hw, speed, true);
4178 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4179 rte_atomic32_clear(&ad->link_thread_running);
4184 * In freebsd environment, nic_uio drivers do not support interrupts,
4185 * rte_intr_callback_register() will fail to register interrupts.
4186 * We can not make link status to change from down to up by interrupt
4187 * callback. So we need to wait for the controller to acquire link
4189 * It returns 0 on link up.
4192 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4194 #ifdef RTE_EXEC_ENV_FREEBSD
4196 bool link_up = false;
4198 const int nb_iter = 25;
4200 for (i = 0; i < nb_iter; i++) {
4201 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4216 /* return 0 means link status changed, -1 means not changed */
4218 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4219 int wait_to_complete, int vf)
4221 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4222 struct ixgbe_adapter *ad = dev->data->dev_private;
4223 struct rte_eth_link link;
4224 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4225 struct ixgbe_interrupt *intr =
4226 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4232 memset(&link, 0, sizeof(link));
4233 link.link_status = ETH_LINK_DOWN;
4234 link.link_speed = ETH_SPEED_NUM_NONE;
4235 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4236 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4237 ETH_LINK_SPEED_FIXED);
4239 hw->mac.get_link_status = true;
4241 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4242 return rte_eth_linkstatus_set(dev, &link);
4244 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4245 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4248 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4249 #ifdef RTE_EXEC_ENV_FREEBSD
4254 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4256 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4259 link.link_speed = ETH_SPEED_NUM_100M;
4260 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4261 return rte_eth_linkstatus_set(dev, &link);
4264 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4265 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4266 if ((esdp_reg & IXGBE_ESDP_SDP3))
4271 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4272 ixgbe_dev_wait_setup_link_complete(dev, 0);
4273 if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4274 /* To avoid race condition between threads, set
4275 * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4276 * when there is no link thread running.
4278 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4279 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4280 "ixgbe-link-handler",
4282 ixgbe_dev_setup_link_thread_handler,
4285 "Create link thread failed!");
4286 rte_atomic32_clear(&ad->link_thread_running);
4290 "Other link thread is running now!");
4293 return rte_eth_linkstatus_set(dev, &link);
4296 link.link_status = ETH_LINK_UP;
4297 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4299 switch (link_speed) {
4301 case IXGBE_LINK_SPEED_UNKNOWN:
4302 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4305 case IXGBE_LINK_SPEED_10_FULL:
4306 link.link_speed = ETH_SPEED_NUM_10M;
4309 case IXGBE_LINK_SPEED_100_FULL:
4310 link.link_speed = ETH_SPEED_NUM_100M;
4313 case IXGBE_LINK_SPEED_1GB_FULL:
4314 link.link_speed = ETH_SPEED_NUM_1G;
4317 case IXGBE_LINK_SPEED_2_5GB_FULL:
4318 link.link_speed = ETH_SPEED_NUM_2_5G;
4321 case IXGBE_LINK_SPEED_5GB_FULL:
4322 link.link_speed = ETH_SPEED_NUM_5G;
4325 case IXGBE_LINK_SPEED_10GB_FULL:
4326 link.link_speed = ETH_SPEED_NUM_10G;
4330 return rte_eth_linkstatus_set(dev, &link);
4334 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4336 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4340 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4342 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4346 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4348 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4352 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4353 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4359 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4361 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4364 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4365 fctrl &= (~IXGBE_FCTRL_UPE);
4366 if (dev->data->all_multicast == 1)
4367 fctrl |= IXGBE_FCTRL_MPE;
4369 fctrl &= (~IXGBE_FCTRL_MPE);
4370 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4376 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4378 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4381 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4382 fctrl |= IXGBE_FCTRL_MPE;
4383 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4389 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4391 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4394 if (dev->data->promiscuous == 1)
4395 return 0; /* must remain in all_multicast mode */
4397 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4398 fctrl &= (~IXGBE_FCTRL_MPE);
4399 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4405 * It clears the interrupt causes and enables the interrupt.
4406 * It will be called once only during nic initialized.
4409 * Pointer to struct rte_eth_dev.
4411 * Enable or Disable.
4414 * - On success, zero.
4415 * - On failure, a negative value.
4418 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4420 struct ixgbe_interrupt *intr =
4421 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4423 ixgbe_dev_link_status_print(dev);
4425 intr->mask |= IXGBE_EICR_LSC;
4427 intr->mask &= ~IXGBE_EICR_LSC;
4433 * It clears the interrupt causes and enables the interrupt.
4434 * It will be called once only during nic initialized.
4437 * Pointer to struct rte_eth_dev.
4440 * - On success, zero.
4441 * - On failure, a negative value.
4444 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4446 struct ixgbe_interrupt *intr =
4447 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4449 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4455 * It clears the interrupt causes and enables the interrupt.
4456 * It will be called once only during nic initialized.
4459 * Pointer to struct rte_eth_dev.
4462 * - On success, zero.
4463 * - On failure, a negative value.
4466 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4468 struct ixgbe_interrupt *intr =
4469 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4471 intr->mask |= IXGBE_EICR_LINKSEC;
4477 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4480 * Pointer to struct rte_eth_dev.
4483 * - On success, zero.
4484 * - On failure, a negative value.
4487 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4490 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4491 struct ixgbe_interrupt *intr =
4492 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4494 /* clear all cause mask */
4495 ixgbe_disable_intr(hw);
4497 /* read-on-clear nic registers here */
4498 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4499 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4503 /* set flag for async link update */
4504 if (eicr & IXGBE_EICR_LSC)
4505 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4507 if (eicr & IXGBE_EICR_MAILBOX)
4508 intr->flags |= IXGBE_FLAG_MAILBOX;
4510 if (eicr & IXGBE_EICR_LINKSEC)
4511 intr->flags |= IXGBE_FLAG_MACSEC;
4513 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4514 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4515 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4516 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4522 * It gets and then prints the link status.
4525 * Pointer to struct rte_eth_dev.
4528 * - On success, zero.
4529 * - On failure, a negative value.
4532 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4534 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4535 struct rte_eth_link link;
4537 rte_eth_linkstatus_get(dev, &link);
4539 if (link.link_status) {
4540 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4541 (int)(dev->data->port_id),
4542 (unsigned)link.link_speed,
4543 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4544 "full-duplex" : "half-duplex");
4546 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4547 (int)(dev->data->port_id));
4549 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4550 pci_dev->addr.domain,
4552 pci_dev->addr.devid,
4553 pci_dev->addr.function);
4557 * It executes link_update after knowing an interrupt occurred.
4560 * Pointer to struct rte_eth_dev.
4563 * - On success, zero.
4564 * - On failure, a negative value.
4567 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4569 struct ixgbe_interrupt *intr =
4570 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4572 struct ixgbe_hw *hw =
4573 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4575 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4577 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4578 ixgbe_pf_mbx_process(dev);
4579 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4582 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4583 ixgbe_handle_lasi(hw);
4584 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4587 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4588 struct rte_eth_link link;
4590 /* get the link status before link update, for predicting later */
4591 rte_eth_linkstatus_get(dev, &link);
4593 ixgbe_dev_link_update(dev, 0);
4596 if (!link.link_status)
4597 /* handle it 1 sec later, wait it being stable */
4598 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4599 /* likely to down */
4601 /* handle it 4 sec later, wait it being stable */
4602 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4604 ixgbe_dev_link_status_print(dev);
4605 if (rte_eal_alarm_set(timeout * 1000,
4606 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4607 PMD_DRV_LOG(ERR, "Error setting alarm");
4609 /* remember original mask */
4610 intr->mask_original = intr->mask;
4611 /* only disable lsc interrupt */
4612 intr->mask &= ~IXGBE_EIMS_LSC;
4616 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4617 ixgbe_enable_intr(dev);
4623 * Interrupt handler which shall be registered for alarm callback for delayed
4624 * handling specific interrupt to wait for the stable nic state. As the
4625 * NIC interrupt state is not stable for ixgbe after link is just down,
4626 * it needs to wait 4 seconds to get the stable status.
4629 * Pointer to interrupt handle.
4631 * The address of parameter (struct rte_eth_dev *) regsitered before.
4637 ixgbe_dev_interrupt_delayed_handler(void *param)
4639 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4640 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4641 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4642 struct ixgbe_interrupt *intr =
4643 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4644 struct ixgbe_hw *hw =
4645 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4648 ixgbe_disable_intr(hw);
4650 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4651 if (eicr & IXGBE_EICR_MAILBOX)
4652 ixgbe_pf_mbx_process(dev);
4654 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4655 ixgbe_handle_lasi(hw);
4656 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4659 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4660 ixgbe_dev_link_update(dev, 0);
4661 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4662 ixgbe_dev_link_status_print(dev);
4663 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4666 if (intr->flags & IXGBE_FLAG_MACSEC) {
4667 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4668 intr->flags &= ~IXGBE_FLAG_MACSEC;
4671 /* restore original mask */
4672 intr->mask = intr->mask_original;
4673 intr->mask_original = 0;
4675 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4676 ixgbe_enable_intr(dev);
4677 rte_intr_ack(intr_handle);
4681 * Interrupt handler triggered by NIC for handling
4682 * specific interrupt.
4685 * Pointer to interrupt handle.
4687 * The address of parameter (struct rte_eth_dev *) regsitered before.
4693 ixgbe_dev_interrupt_handler(void *param)
4695 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4697 ixgbe_dev_interrupt_get_status(dev);
4698 ixgbe_dev_interrupt_action(dev);
4702 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4704 struct ixgbe_hw *hw;
4706 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4707 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4711 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4713 struct ixgbe_hw *hw;
4715 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4716 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4720 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4722 struct ixgbe_hw *hw;
4728 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4730 fc_conf->pause_time = hw->fc.pause_time;
4731 fc_conf->high_water = hw->fc.high_water[0];
4732 fc_conf->low_water = hw->fc.low_water[0];
4733 fc_conf->send_xon = hw->fc.send_xon;
4734 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4737 * Return rx_pause status according to actual setting of
4740 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4741 if (mflcn_reg & IXGBE_MFLCN_PMCF)
4742 fc_conf->mac_ctrl_frame_fwd = 1;
4744 fc_conf->mac_ctrl_frame_fwd = 0;
4746 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4752 * Return tx_pause status according to actual setting of
4755 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4756 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4761 if (rx_pause && tx_pause)
4762 fc_conf->mode = RTE_FC_FULL;
4764 fc_conf->mode = RTE_FC_RX_PAUSE;
4766 fc_conf->mode = RTE_FC_TX_PAUSE;
4768 fc_conf->mode = RTE_FC_NONE;
4774 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4776 struct ixgbe_hw *hw;
4777 struct ixgbe_adapter *adapter = dev->data->dev_private;
4779 uint32_t rx_buf_size;
4780 uint32_t max_high_water;
4781 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4788 PMD_INIT_FUNC_TRACE();
4790 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4791 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4792 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4795 * At least reserve one Ethernet frame for watermark
4796 * high_water/low_water in kilo bytes for ixgbe
4798 max_high_water = (rx_buf_size -
4799 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4800 if ((fc_conf->high_water > max_high_water) ||
4801 (fc_conf->high_water < fc_conf->low_water)) {
4802 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4803 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4807 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4808 hw->fc.pause_time = fc_conf->pause_time;
4809 hw->fc.high_water[0] = fc_conf->high_water;
4810 hw->fc.low_water[0] = fc_conf->low_water;
4811 hw->fc.send_xon = fc_conf->send_xon;
4812 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4813 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4815 err = ixgbe_flow_ctrl_enable(dev, hw);
4817 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4824 * ixgbe_pfc_enable_generic - Enable flow control
4825 * @hw: pointer to hardware structure
4826 * @tc_num: traffic class number
4827 * Enable flow control according to the current settings.
4830 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4833 uint32_t mflcn_reg, fccfg_reg;
4835 uint32_t fcrtl, fcrth;
4839 /* Validate the water mark configuration */
4840 if (!hw->fc.pause_time) {
4841 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4845 /* Low water mark of zero causes XOFF floods */
4846 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4847 /* High/Low water can not be 0 */
4848 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4849 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4850 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4854 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4855 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4856 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4860 /* Negotiate the fc mode to use */
4861 ixgbe_fc_autoneg(hw);
4863 /* Disable any previous flow control settings */
4864 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4865 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4867 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4868 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4870 switch (hw->fc.current_mode) {
4873 * If the count of enabled RX Priority Flow control >1,
4874 * and the TX pause can not be disabled
4877 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4878 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4879 if (reg & IXGBE_FCRTH_FCEN)
4883 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4885 case ixgbe_fc_rx_pause:
4887 * Rx Flow control is enabled and Tx Flow control is
4888 * disabled by software override. Since there really
4889 * isn't a way to advertise that we are capable of RX
4890 * Pause ONLY, we will advertise that we support both
4891 * symmetric and asymmetric Rx PAUSE. Later, we will
4892 * disable the adapter's ability to send PAUSE frames.
4894 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4896 * If the count of enabled RX Priority Flow control >1,
4897 * and the TX pause can not be disabled
4900 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4901 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4902 if (reg & IXGBE_FCRTH_FCEN)
4906 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4908 case ixgbe_fc_tx_pause:
4910 * Tx Flow control is enabled, and Rx Flow control is
4911 * disabled by software override.
4913 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4916 /* Flow control (both Rx and Tx) is enabled by SW override. */
4917 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4918 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4921 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4922 ret_val = IXGBE_ERR_CONFIG;
4926 /* Set 802.3x based flow control settings. */
4927 mflcn_reg |= IXGBE_MFLCN_DPF;
4928 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4929 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4931 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4932 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4933 hw->fc.high_water[tc_num]) {
4934 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4935 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4936 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4938 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4940 * In order to prevent Tx hangs when the internal Tx
4941 * switch is enabled we must set the high water mark
4942 * to the maximum FCRTH value. This allows the Tx
4943 * switch to function even under heavy Rx workloads.
4945 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4947 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4949 /* Configure pause time (2 TCs per register) */
4950 reg = hw->fc.pause_time * 0x00010001;
4951 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4952 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4954 /* Configure flow control refresh threshold value */
4955 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4962 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4964 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4965 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4967 if (hw->mac.type != ixgbe_mac_82598EB) {
4968 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4974 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4977 uint32_t rx_buf_size;
4978 uint32_t max_high_water;
4980 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4981 struct ixgbe_hw *hw =
4982 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4983 struct ixgbe_dcb_config *dcb_config =
4984 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4986 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4993 PMD_INIT_FUNC_TRACE();
4995 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4996 tc_num = map[pfc_conf->priority];
4997 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4998 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
5000 * At least reserve one Ethernet frame for watermark
5001 * high_water/low_water in kilo bytes for ixgbe
5003 max_high_water = (rx_buf_size -
5004 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
5005 if ((pfc_conf->fc.high_water > max_high_water) ||
5006 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5007 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5008 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5012 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5013 hw->fc.pause_time = pfc_conf->fc.pause_time;
5014 hw->fc.send_xon = pfc_conf->fc.send_xon;
5015 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
5016 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5018 err = ixgbe_dcb_pfc_enable(dev, tc_num);
5020 /* Not negotiated is not an error case */
5021 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5024 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5029 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5030 struct rte_eth_rss_reta_entry64 *reta_conf,
5033 uint16_t i, sp_reta_size;
5036 uint16_t idx, shift;
5037 struct ixgbe_adapter *adapter = dev->data->dev_private;
5038 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5041 PMD_INIT_FUNC_TRACE();
5043 if (!ixgbe_rss_update_sp(hw->mac.type)) {
5044 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5049 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5050 if (reta_size != sp_reta_size) {
5051 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5052 "(%d) doesn't match the number hardware can supported "
5053 "(%d)", reta_size, sp_reta_size);
5057 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5058 idx = i / RTE_RETA_GROUP_SIZE;
5059 shift = i % RTE_RETA_GROUP_SIZE;
5060 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5064 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5065 if (mask == IXGBE_4_BIT_MASK)
5068 r = IXGBE_READ_REG(hw, reta_reg);
5069 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5070 if (mask & (0x1 << j))
5071 reta |= reta_conf[idx].reta[shift + j] <<
5074 reta |= r & (IXGBE_8_BIT_MASK <<
5077 IXGBE_WRITE_REG(hw, reta_reg, reta);
5079 adapter->rss_reta_updated = 1;
5085 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5086 struct rte_eth_rss_reta_entry64 *reta_conf,
5089 uint16_t i, sp_reta_size;
5092 uint16_t idx, shift;
5093 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5096 PMD_INIT_FUNC_TRACE();
5097 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5098 if (reta_size != sp_reta_size) {
5099 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5100 "(%d) doesn't match the number hardware can supported "
5101 "(%d)", reta_size, sp_reta_size);
5105 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5106 idx = i / RTE_RETA_GROUP_SIZE;
5107 shift = i % RTE_RETA_GROUP_SIZE;
5108 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5113 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5114 reta = IXGBE_READ_REG(hw, reta_reg);
5115 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5116 if (mask & (0x1 << j))
5117 reta_conf[idx].reta[shift + j] =
5118 ((reta >> (CHAR_BIT * j)) &
5127 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5128 uint32_t index, uint32_t pool)
5130 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131 uint32_t enable_addr = 1;
5133 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5138 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5140 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5142 ixgbe_clear_rar(hw, index);
5146 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5148 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5150 ixgbe_remove_rar(dev, 0);
5151 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5157 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5159 if (strcmp(dev->device->driver->name, drv->driver.name))
5166 is_ixgbe_supported(struct rte_eth_dev *dev)
5168 return is_device_supported(dev, &rte_ixgbe_pmd);
5172 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5176 struct ixgbe_hw *hw;
5177 struct rte_eth_dev_info dev_info;
5178 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5179 struct rte_eth_dev_data *dev_data = dev->data;
5182 ret = ixgbe_dev_info_get(dev, &dev_info);
5186 /* check that mtu is within the allowed range */
5187 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5190 /* If device is started, refuse mtu that requires the support of
5191 * scattered packets when this feature has not been enabled before.
5193 if (dev_data->dev_started && !dev_data->scattered_rx &&
5194 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5195 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5196 PMD_INIT_LOG(ERR, "Stop port first.");
5200 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5203 /* switch to jumbo mode if needed */
5204 if (frame_size > RTE_ETHER_MAX_LEN) {
5205 dev->data->dev_conf.rxmode.offloads |=
5206 DEV_RX_OFFLOAD_JUMBO_FRAME;
5207 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5209 dev->data->dev_conf.rxmode.offloads &=
5210 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5211 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5213 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5215 /* update max frame size */
5216 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5218 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5219 maxfrs &= 0x0000FFFF;
5220 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5221 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5227 * Virtual Function operations
5230 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5232 struct ixgbe_interrupt *intr =
5233 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5234 struct ixgbe_hw *hw =
5235 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5237 PMD_INIT_FUNC_TRACE();
5239 /* Clear interrupt mask to stop from interrupts being generated */
5240 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5242 IXGBE_WRITE_FLUSH(hw);
5244 /* Clear mask value. */
5249 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5251 struct ixgbe_interrupt *intr =
5252 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5253 struct ixgbe_hw *hw =
5254 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5256 PMD_INIT_FUNC_TRACE();
5258 /* VF enable interrupt autoclean */
5259 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5260 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5261 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5263 IXGBE_WRITE_FLUSH(hw);
5265 /* Save IXGBE_VTEIMS value to mask. */
5266 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5270 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5272 struct rte_eth_conf *conf = &dev->data->dev_conf;
5273 struct ixgbe_adapter *adapter = dev->data->dev_private;
5275 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5276 dev->data->port_id);
5278 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5279 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5282 * VF has no ability to enable/disable HW CRC
5283 * Keep the persistent behavior the same as Host PF
5285 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5286 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5287 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5288 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5291 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5292 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5293 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5298 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5299 * allocation or vector Rx preconditions we will reset it.
5301 adapter->rx_bulk_alloc_allowed = true;
5302 adapter->rx_vec_allowed = true;
5308 ixgbevf_dev_start(struct rte_eth_dev *dev)
5310 struct ixgbe_hw *hw =
5311 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5312 uint32_t intr_vector = 0;
5313 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5314 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5318 PMD_INIT_FUNC_TRACE();
5320 /* Stop the link setup handler before resetting the HW. */
5321 ixgbe_dev_wait_setup_link_complete(dev, 0);
5323 err = hw->mac.ops.reset_hw(hw);
5326 * In this case, reuses the MAC address assigned by VF
5329 if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5330 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5334 hw->mac.get_link_status = true;
5336 /* negotiate mailbox API version to use with the PF. */
5337 ixgbevf_negotiate_api(hw);
5339 ixgbevf_dev_tx_init(dev);
5341 /* This can fail when allocating mbufs for descriptor rings */
5342 err = ixgbevf_dev_rx_init(dev);
5344 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5345 ixgbe_dev_clear_queues(dev);
5350 ixgbevf_set_vfta_all(dev, 1);
5353 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5354 ETH_VLAN_EXTEND_MASK;
5355 err = ixgbevf_vlan_offload_config(dev, mask);
5357 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5358 ixgbe_dev_clear_queues(dev);
5362 ixgbevf_dev_rxtx_start(dev);
5364 /* check and configure queue intr-vector mapping */
5365 if (rte_intr_cap_multiple(intr_handle) &&
5366 dev->data->dev_conf.intr_conf.rxq) {
5367 /* According to datasheet, only vector 0/1/2 can be used,
5368 * now only one vector is used for Rx queue
5371 if (rte_intr_efd_enable(intr_handle, intr_vector))
5375 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5376 intr_handle->intr_vec =
5377 rte_zmalloc("intr_vec",
5378 dev->data->nb_rx_queues * sizeof(int), 0);
5379 if (intr_handle->intr_vec == NULL) {
5380 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5381 " intr_vec", dev->data->nb_rx_queues);
5385 ixgbevf_configure_msix(dev);
5387 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5388 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5389 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5390 * is not cleared, it will fail when following rte_intr_enable( ) tries
5391 * to map Rx queue interrupt to other VFIO vectors.
5392 * So clear uio/vfio intr/evevnfd first to avoid failure.
5394 rte_intr_disable(intr_handle);
5396 rte_intr_enable(intr_handle);
5398 /* Re-enable interrupt for VF */
5399 ixgbevf_intr_enable(dev);
5402 * Update link status right before return, because it may
5403 * start link configuration process in a separate thread.
5405 ixgbevf_dev_link_update(dev, 0);
5407 hw->adapter_stopped = false;
5413 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5415 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5416 struct ixgbe_adapter *adapter = dev->data->dev_private;
5417 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5418 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5420 if (hw->adapter_stopped)
5423 PMD_INIT_FUNC_TRACE();
5425 ixgbe_dev_wait_setup_link_complete(dev, 0);
5427 ixgbevf_intr_disable(dev);
5429 dev->data->dev_started = 0;
5430 hw->adapter_stopped = 1;
5431 ixgbe_stop_adapter(hw);
5434 * Clear what we set, but we still keep shadow_vfta to
5435 * restore after device starts
5437 ixgbevf_set_vfta_all(dev, 0);
5439 /* Clear stored conf */
5440 dev->data->scattered_rx = 0;
5442 ixgbe_dev_clear_queues(dev);
5444 /* Clean datapath event and queue/vec mapping */
5445 rte_intr_efd_disable(intr_handle);
5446 if (intr_handle->intr_vec != NULL) {
5447 rte_free(intr_handle->intr_vec);
5448 intr_handle->intr_vec = NULL;
5451 adapter->rss_reta_updated = 0;
5457 ixgbevf_dev_close(struct rte_eth_dev *dev)
5459 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5460 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5461 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5464 PMD_INIT_FUNC_TRACE();
5465 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5470 ret = ixgbevf_dev_stop(dev);
5472 ixgbe_dev_free_queues(dev);
5475 * Remove the VF MAC address ro ensure
5476 * that the VF traffic goes to the PF
5477 * after stop, close and detach of the VF
5479 ixgbevf_remove_mac_addr(dev, 0);
5481 rte_intr_disable(intr_handle);
5482 rte_intr_callback_unregister(intr_handle,
5483 ixgbevf_dev_interrupt_handler, dev);
5492 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5496 ret = eth_ixgbevf_dev_uninit(dev);
5500 ret = eth_ixgbevf_dev_init(dev);
5505 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5507 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5508 struct ixgbe_vfta *shadow_vfta =
5509 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5510 int i = 0, j = 0, vfta = 0, mask = 1;
5512 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5513 vfta = shadow_vfta->vfta[i];
5516 for (j = 0; j < 32; j++) {
5518 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5528 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5530 struct ixgbe_hw *hw =
5531 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5532 struct ixgbe_vfta *shadow_vfta =
5533 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5534 uint32_t vid_idx = 0;
5535 uint32_t vid_bit = 0;
5538 PMD_INIT_FUNC_TRACE();
5540 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5541 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5543 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5546 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5547 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5549 /* Save what we set and retore it after device reset */
5551 shadow_vfta->vfta[vid_idx] |= vid_bit;
5553 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5559 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5561 struct ixgbe_hw *hw =
5562 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5565 PMD_INIT_FUNC_TRACE();
5567 if (queue >= hw->mac.max_rx_queues)
5570 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5572 ctrl |= IXGBE_RXDCTL_VME;
5574 ctrl &= ~IXGBE_RXDCTL_VME;
5575 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5577 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5581 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5583 struct ixgbe_rx_queue *rxq;
5587 /* VF function only support hw strip feature, others are not support */
5588 if (mask & ETH_VLAN_STRIP_MASK) {
5589 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5590 rxq = dev->data->rx_queues[i];
5591 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5592 ixgbevf_vlan_strip_queue_set(dev, i, on);
5600 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5602 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5604 ixgbevf_vlan_offload_config(dev, mask);
5610 ixgbe_vt_check(struct ixgbe_hw *hw)
5614 /* if Virtualization Technology is enabled */
5615 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5616 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5617 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5625 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5627 uint32_t vector = 0;
5629 switch (hw->mac.mc_filter_type) {
5630 case 0: /* use bits [47:36] of the address */
5631 vector = ((uc_addr->addr_bytes[4] >> 4) |
5632 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5634 case 1: /* use bits [46:35] of the address */
5635 vector = ((uc_addr->addr_bytes[4] >> 3) |
5636 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5638 case 2: /* use bits [45:34] of the address */
5639 vector = ((uc_addr->addr_bytes[4] >> 2) |
5640 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5642 case 3: /* use bits [43:32] of the address */
5643 vector = ((uc_addr->addr_bytes[4]) |
5644 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5646 default: /* Invalid mc_filter_type */
5650 /* vector can only be 12-bits or boundary will be exceeded */
5656 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5657 struct rte_ether_addr *mac_addr, uint8_t on)
5664 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5665 const uint32_t ixgbe_uta_bit_shift = 5;
5666 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5667 const uint32_t bit1 = 0x1;
5669 struct ixgbe_hw *hw =
5670 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5671 struct ixgbe_uta_info *uta_info =
5672 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5674 /* The UTA table only exists on 82599 hardware and newer */
5675 if (hw->mac.type < ixgbe_mac_82599EB)
5678 vector = ixgbe_uta_vector(hw, mac_addr);
5679 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5680 uta_shift = vector & ixgbe_uta_bit_mask;
5682 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5686 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5688 uta_info->uta_in_use++;
5689 reg_val |= (bit1 << uta_shift);
5690 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5692 uta_info->uta_in_use--;
5693 reg_val &= ~(bit1 << uta_shift);
5694 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5697 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5699 if (uta_info->uta_in_use > 0)
5700 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5701 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5703 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5709 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5712 struct ixgbe_hw *hw =
5713 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5714 struct ixgbe_uta_info *uta_info =
5715 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5717 /* The UTA table only exists on 82599 hardware and newer */
5718 if (hw->mac.type < ixgbe_mac_82599EB)
5722 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5723 uta_info->uta_shadow[i] = ~0;
5724 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5727 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5728 uta_info->uta_shadow[i] = 0;
5729 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5737 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5739 uint32_t new_val = orig_val;
5741 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5742 new_val |= IXGBE_VMOLR_AUPE;
5743 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5744 new_val |= IXGBE_VMOLR_ROMPE;
5745 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5746 new_val |= IXGBE_VMOLR_ROPE;
5747 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5748 new_val |= IXGBE_VMOLR_BAM;
5749 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5750 new_val |= IXGBE_VMOLR_MPE;
5755 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5756 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5757 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5758 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5759 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5760 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5761 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5764 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5765 struct rte_eth_mirror_conf *mirror_conf,
5766 uint8_t rule_id, uint8_t on)
5768 uint32_t mr_ctl, vlvf;
5769 uint32_t mp_lsb = 0;
5770 uint32_t mv_msb = 0;
5771 uint32_t mv_lsb = 0;
5772 uint32_t mp_msb = 0;
5775 uint64_t vlan_mask = 0;
5777 const uint8_t pool_mask_offset = 32;
5778 const uint8_t vlan_mask_offset = 32;
5779 const uint8_t dst_pool_offset = 8;
5780 const uint8_t rule_mr_offset = 4;
5781 const uint8_t mirror_rule_mask = 0x0F;
5783 struct ixgbe_mirror_info *mr_info =
5784 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5785 struct ixgbe_hw *hw =
5786 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5787 uint8_t mirror_type = 0;
5789 if (ixgbe_vt_check(hw) < 0)
5792 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5795 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5796 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5797 mirror_conf->rule_type);
5801 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5802 mirror_type |= IXGBE_MRCTL_VLME;
5803 /* Check if vlan id is valid and find conresponding VLAN ID
5806 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5807 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5808 /* search vlan id related pool vlan filter
5811 reg_index = ixgbe_find_vlvf_slot(
5813 mirror_conf->vlan.vlan_id[i],
5817 vlvf = IXGBE_READ_REG(hw,
5818 IXGBE_VLVF(reg_index));
5819 if ((vlvf & IXGBE_VLVF_VIEN) &&
5820 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5821 mirror_conf->vlan.vlan_id[i]))
5822 vlan_mask |= (1ULL << reg_index);
5829 mv_lsb = vlan_mask & 0xFFFFFFFF;
5830 mv_msb = vlan_mask >> vlan_mask_offset;
5832 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5833 mirror_conf->vlan.vlan_mask;
5834 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5835 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5836 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5837 mirror_conf->vlan.vlan_id[i];
5842 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5843 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5844 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5849 * if enable pool mirror, write related pool mask register,if disable
5850 * pool mirror, clear PFMRVM register
5852 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5853 mirror_type |= IXGBE_MRCTL_VPME;
5855 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5856 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5857 mr_info->mr_conf[rule_id].pool_mask =
5858 mirror_conf->pool_mask;
5863 mr_info->mr_conf[rule_id].pool_mask = 0;
5866 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5867 mirror_type |= IXGBE_MRCTL_UPME;
5868 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5869 mirror_type |= IXGBE_MRCTL_DPME;
5871 /* read mirror control register and recalculate it */
5872 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5875 mr_ctl |= mirror_type;
5876 mr_ctl &= mirror_rule_mask;
5877 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5879 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5882 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5883 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5885 /* write mirrror control register */
5886 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5888 /* write pool mirrror control register */
5889 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5890 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5891 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5894 /* write VLAN mirrror control register */
5895 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5896 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5897 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5905 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5908 uint32_t lsb_val = 0;
5909 uint32_t msb_val = 0;
5910 const uint8_t rule_mr_offset = 4;
5912 struct ixgbe_hw *hw =
5913 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5914 struct ixgbe_mirror_info *mr_info =
5915 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5917 if (ixgbe_vt_check(hw) < 0)
5920 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5923 memset(&mr_info->mr_conf[rule_id], 0,
5924 sizeof(struct rte_eth_mirror_conf));
5926 /* clear PFVMCTL register */
5927 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5929 /* clear pool mask register */
5930 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5931 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5933 /* clear vlan mask register */
5934 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5935 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5941 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5943 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5944 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5945 struct ixgbe_interrupt *intr =
5946 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5947 struct ixgbe_hw *hw =
5948 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5949 uint32_t vec = IXGBE_MISC_VEC_ID;
5951 if (rte_intr_allow_others(intr_handle))
5952 vec = IXGBE_RX_VEC_START;
5953 intr->mask |= (1 << vec);
5954 RTE_SET_USED(queue_id);
5955 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5957 rte_intr_ack(intr_handle);
5963 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5965 struct ixgbe_interrupt *intr =
5966 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5967 struct ixgbe_hw *hw =
5968 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5969 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5970 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5971 uint32_t vec = IXGBE_MISC_VEC_ID;
5973 if (rte_intr_allow_others(intr_handle))
5974 vec = IXGBE_RX_VEC_START;
5975 intr->mask &= ~(1 << vec);
5976 RTE_SET_USED(queue_id);
5977 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5983 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5985 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5986 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5988 struct ixgbe_hw *hw =
5989 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5990 struct ixgbe_interrupt *intr =
5991 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5993 if (queue_id < 16) {
5994 ixgbe_disable_intr(hw);
5995 intr->mask |= (1 << queue_id);
5996 ixgbe_enable_intr(dev);
5997 } else if (queue_id < 32) {
5998 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5999 mask &= (1 << queue_id);
6000 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6001 } else if (queue_id < 64) {
6002 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6003 mask &= (1 << (queue_id - 32));
6004 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6006 rte_intr_ack(intr_handle);
6012 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6015 struct ixgbe_hw *hw =
6016 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6017 struct ixgbe_interrupt *intr =
6018 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6020 if (queue_id < 16) {
6021 ixgbe_disable_intr(hw);
6022 intr->mask &= ~(1 << queue_id);
6023 ixgbe_enable_intr(dev);
6024 } else if (queue_id < 32) {
6025 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6026 mask &= ~(1 << queue_id);
6027 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6028 } else if (queue_id < 64) {
6029 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6030 mask &= ~(1 << (queue_id - 32));
6031 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6038 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6039 uint8_t queue, uint8_t msix_vector)
6043 if (direction == -1) {
6045 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6046 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6049 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6051 /* rx or tx cause */
6052 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6053 idx = ((16 * (queue & 1)) + (8 * direction));
6054 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6055 tmp &= ~(0xFF << idx);
6056 tmp |= (msix_vector << idx);
6057 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6062 * set the IVAR registers, mapping interrupt causes to vectors
6064 * pointer to ixgbe_hw struct
6066 * 0 for Rx, 1 for Tx, -1 for other causes
6068 * queue to map the corresponding interrupt to
6070 * the vector to map to the corresponding queue
6073 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6074 uint8_t queue, uint8_t msix_vector)
6078 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6079 if (hw->mac.type == ixgbe_mac_82598EB) {
6080 if (direction == -1)
6082 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6083 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6084 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6085 tmp |= (msix_vector << (8 * (queue & 0x3)));
6086 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6087 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6088 (hw->mac.type == ixgbe_mac_X540) ||
6089 (hw->mac.type == ixgbe_mac_X550) ||
6090 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6091 if (direction == -1) {
6093 idx = ((queue & 1) * 8);
6094 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6095 tmp &= ~(0xFF << idx);
6096 tmp |= (msix_vector << idx);
6097 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6099 /* rx or tx causes */
6100 idx = ((16 * (queue & 1)) + (8 * direction));
6101 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6102 tmp &= ~(0xFF << idx);
6103 tmp |= (msix_vector << idx);
6104 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6110 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6112 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6113 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6114 struct ixgbe_hw *hw =
6115 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6117 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6118 uint32_t base = IXGBE_MISC_VEC_ID;
6120 /* Configure VF other cause ivar */
6121 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6123 /* won't configure msix register if no mapping is done
6124 * between intr vector and event fd.
6126 if (!rte_intr_dp_is_en(intr_handle))
6129 if (rte_intr_allow_others(intr_handle)) {
6130 base = IXGBE_RX_VEC_START;
6131 vector_idx = IXGBE_RX_VEC_START;
6134 /* Configure all RX queues of VF */
6135 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6136 /* Force all queue use vector 0,
6137 * as IXGBE_VF_MAXMSIVECOTR = 1
6139 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6140 intr_handle->intr_vec[q_idx] = vector_idx;
6141 if (vector_idx < base + intr_handle->nb_efd - 1)
6145 /* As RX queue setting above show, all queues use the vector 0.
6146 * Set only the ITR value of IXGBE_MISC_VEC_ID.
6148 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6149 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6150 | IXGBE_EITR_CNT_WDIS);
6154 * Sets up the hardware to properly generate MSI-X interrupts
6156 * board private structure
6159 ixgbe_configure_msix(struct rte_eth_dev *dev)
6161 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6162 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6163 struct ixgbe_hw *hw =
6164 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6165 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6166 uint32_t vec = IXGBE_MISC_VEC_ID;
6170 /* won't configure msix register if no mapping is done
6171 * between intr vector and event fd
6172 * but if misx has been enabled already, need to configure
6173 * auto clean, auto mask and throttling.
6175 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6176 if (!rte_intr_dp_is_en(intr_handle) &&
6177 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6180 if (rte_intr_allow_others(intr_handle))
6181 vec = base = IXGBE_RX_VEC_START;
6183 /* setup GPIE for MSI-x mode */
6184 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6185 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6186 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6187 /* auto clearing and auto setting corresponding bits in EIMS
6188 * when MSI-X interrupt is triggered
6190 if (hw->mac.type == ixgbe_mac_82598EB) {
6191 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6193 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6194 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6196 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6198 /* Populate the IVAR table and set the ITR values to the
6199 * corresponding register.
6201 if (rte_intr_dp_is_en(intr_handle)) {
6202 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6204 /* by default, 1:1 mapping */
6205 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6206 intr_handle->intr_vec[queue_id] = vec;
6207 if (vec < base + intr_handle->nb_efd - 1)
6211 switch (hw->mac.type) {
6212 case ixgbe_mac_82598EB:
6213 ixgbe_set_ivar_map(hw, -1,
6214 IXGBE_IVAR_OTHER_CAUSES_INDEX,
6217 case ixgbe_mac_82599EB:
6218 case ixgbe_mac_X540:
6219 case ixgbe_mac_X550:
6220 case ixgbe_mac_X550EM_x:
6221 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6227 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6228 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6229 | IXGBE_EITR_CNT_WDIS);
6231 /* set up to autoclear timer, and the vectors */
6232 mask = IXGBE_EIMS_ENABLE_MASK;
6233 mask &= ~(IXGBE_EIMS_OTHER |
6234 IXGBE_EIMS_MAILBOX |
6237 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6241 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6242 uint16_t queue_idx, uint16_t tx_rate)
6244 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6245 struct rte_eth_rxmode *rxmode;
6246 uint32_t rf_dec, rf_int;
6248 uint16_t link_speed = dev->data->dev_link.link_speed;
6250 if (queue_idx >= hw->mac.max_tx_queues)
6254 /* Calculate the rate factor values to set */
6255 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6256 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6257 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6259 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6260 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6261 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6262 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6267 rxmode = &dev->data->dev_conf.rxmode;
6269 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6270 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6273 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6274 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6275 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6276 IXGBE_MMW_SIZE_JUMBO_FRAME);
6278 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6279 IXGBE_MMW_SIZE_DEFAULT);
6281 /* Set RTTBCNRC of queue X */
6282 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6283 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6284 IXGBE_WRITE_FLUSH(hw);
6290 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6291 __rte_unused uint32_t index,
6292 __rte_unused uint32_t pool)
6294 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6298 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6299 * operation. Trap this case to avoid exhausting the [very limited]
6300 * set of PF resources used to store VF MAC addresses.
6302 if (memcmp(hw->mac.perm_addr, mac_addr,
6303 sizeof(struct rte_ether_addr)) == 0)
6305 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6307 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6308 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6309 mac_addr->addr_bytes[0],
6310 mac_addr->addr_bytes[1],
6311 mac_addr->addr_bytes[2],
6312 mac_addr->addr_bytes[3],
6313 mac_addr->addr_bytes[4],
6314 mac_addr->addr_bytes[5],
6320 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6322 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6323 struct rte_ether_addr *perm_addr =
6324 (struct rte_ether_addr *)hw->mac.perm_addr;
6325 struct rte_ether_addr *mac_addr;
6330 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6331 * not support the deletion of a given MAC address.
6332 * Instead, it imposes to delete all MAC addresses, then to add again
6333 * all MAC addresses with the exception of the one to be deleted.
6335 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6338 * Add again all MAC addresses, with the exception of the deleted one
6339 * and of the permanent MAC address.
6341 for (i = 0, mac_addr = dev->data->mac_addrs;
6342 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6343 /* Skip the deleted MAC address */
6346 /* Skip NULL MAC addresses */
6347 if (rte_is_zero_ether_addr(mac_addr))
6349 /* Skip the permanent MAC address */
6350 if (memcmp(perm_addr, mac_addr,
6351 sizeof(struct rte_ether_addr)) == 0)
6353 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6356 "Adding again MAC address "
6357 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6359 mac_addr->addr_bytes[0],
6360 mac_addr->addr_bytes[1],
6361 mac_addr->addr_bytes[2],
6362 mac_addr->addr_bytes[3],
6363 mac_addr->addr_bytes[4],
6364 mac_addr->addr_bytes[5],
6370 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6371 struct rte_ether_addr *addr)
6373 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6375 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6381 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6382 struct rte_eth_syn_filter *filter,
6385 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6386 struct ixgbe_filter_info *filter_info =
6387 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6391 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6394 syn_info = filter_info->syn_info;
6397 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6399 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6400 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6402 if (filter->hig_pri)
6403 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6405 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6407 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6408 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6410 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6413 filter_info->syn_info = synqf;
6414 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6415 IXGBE_WRITE_FLUSH(hw);
6420 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6421 struct rte_eth_syn_filter *filter)
6423 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6424 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6426 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6427 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6428 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6435 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6436 enum rte_filter_op filter_op,
6439 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6442 MAC_TYPE_FILTER_SUP(hw->mac.type);
6444 if (filter_op == RTE_ETH_FILTER_NOP)
6448 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6453 switch (filter_op) {
6454 case RTE_ETH_FILTER_ADD:
6455 ret = ixgbe_syn_filter_set(dev,
6456 (struct rte_eth_syn_filter *)arg,
6459 case RTE_ETH_FILTER_DELETE:
6460 ret = ixgbe_syn_filter_set(dev,
6461 (struct rte_eth_syn_filter *)arg,
6464 case RTE_ETH_FILTER_GET:
6465 ret = ixgbe_syn_filter_get(dev,
6466 (struct rte_eth_syn_filter *)arg);
6469 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6478 static inline enum ixgbe_5tuple_protocol
6479 convert_protocol_type(uint8_t protocol_value)
6481 if (protocol_value == IPPROTO_TCP)
6482 return IXGBE_FILTER_PROTOCOL_TCP;
6483 else if (protocol_value == IPPROTO_UDP)
6484 return IXGBE_FILTER_PROTOCOL_UDP;
6485 else if (protocol_value == IPPROTO_SCTP)
6486 return IXGBE_FILTER_PROTOCOL_SCTP;
6488 return IXGBE_FILTER_PROTOCOL_NONE;
6491 /* inject a 5-tuple filter to HW */
6493 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6494 struct ixgbe_5tuple_filter *filter)
6496 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6498 uint32_t ftqf, sdpqf;
6499 uint32_t l34timir = 0;
6500 uint8_t mask = 0xff;
6504 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6505 IXGBE_SDPQF_DSTPORT_SHIFT);
6506 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6508 ftqf = (uint32_t)(filter->filter_info.proto &
6509 IXGBE_FTQF_PROTOCOL_MASK);
6510 ftqf |= (uint32_t)((filter->filter_info.priority &
6511 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6512 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6513 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6514 if (filter->filter_info.dst_ip_mask == 0)
6515 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6516 if (filter->filter_info.src_port_mask == 0)
6517 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6518 if (filter->filter_info.dst_port_mask == 0)
6519 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6520 if (filter->filter_info.proto_mask == 0)
6521 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6522 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6523 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6524 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6526 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6527 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6528 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6529 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6531 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6532 l34timir |= (uint32_t)(filter->queue <<
6533 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6534 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6538 * add a 5tuple filter
6541 * dev: Pointer to struct rte_eth_dev.
6542 * index: the index the filter allocates.
6543 * filter: ponter to the filter that will be added.
6544 * rx_queue: the queue id the filter assigned to.
6547 * - On success, zero.
6548 * - On failure, a negative value.
6551 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6552 struct ixgbe_5tuple_filter *filter)
6554 struct ixgbe_filter_info *filter_info =
6555 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6559 * look for an unused 5tuple filter index,
6560 * and insert the filter to list.
6562 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6563 idx = i / (sizeof(uint32_t) * NBBY);
6564 shift = i % (sizeof(uint32_t) * NBBY);
6565 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6566 filter_info->fivetuple_mask[idx] |= 1 << shift;
6568 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6574 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6575 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6579 ixgbe_inject_5tuple_filter(dev, filter);
6585 * remove a 5tuple filter
6588 * dev: Pointer to struct rte_eth_dev.
6589 * filter: the pointer of the filter will be removed.
6592 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6593 struct ixgbe_5tuple_filter *filter)
6595 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6596 struct ixgbe_filter_info *filter_info =
6597 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6598 uint16_t index = filter->index;
6600 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6601 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6602 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6605 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6606 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6607 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6608 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6609 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6613 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6615 struct ixgbe_hw *hw;
6616 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6617 struct rte_eth_dev_data *dev_data = dev->data;
6619 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6621 if (mtu < RTE_ETHER_MIN_MTU ||
6622 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6625 /* If device is started, refuse mtu that requires the support of
6626 * scattered packets when this feature has not been enabled before.
6628 if (dev_data->dev_started && !dev_data->scattered_rx &&
6629 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6630 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6631 PMD_INIT_LOG(ERR, "Stop port first.");
6636 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6637 * request of the version 2.0 of the mailbox API.
6638 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6639 * of the mailbox API.
6640 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6641 * prior to 3.11.33 which contains the following change:
6642 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6644 ixgbevf_rlpml_set_vf(hw, max_frame);
6646 /* update max frame size */
6647 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6651 static inline struct ixgbe_5tuple_filter *
6652 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6653 struct ixgbe_5tuple_filter_info *key)
6655 struct ixgbe_5tuple_filter *it;
6657 TAILQ_FOREACH(it, filter_list, entries) {
6658 if (memcmp(key, &it->filter_info,
6659 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6666 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6668 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6669 struct ixgbe_5tuple_filter_info *filter_info)
6671 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6672 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6673 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6676 switch (filter->dst_ip_mask) {
6678 filter_info->dst_ip_mask = 0;
6679 filter_info->dst_ip = filter->dst_ip;
6682 filter_info->dst_ip_mask = 1;
6685 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6689 switch (filter->src_ip_mask) {
6691 filter_info->src_ip_mask = 0;
6692 filter_info->src_ip = filter->src_ip;
6695 filter_info->src_ip_mask = 1;
6698 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6702 switch (filter->dst_port_mask) {
6704 filter_info->dst_port_mask = 0;
6705 filter_info->dst_port = filter->dst_port;
6708 filter_info->dst_port_mask = 1;
6711 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6715 switch (filter->src_port_mask) {
6717 filter_info->src_port_mask = 0;
6718 filter_info->src_port = filter->src_port;
6721 filter_info->src_port_mask = 1;
6724 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6728 switch (filter->proto_mask) {
6730 filter_info->proto_mask = 0;
6731 filter_info->proto =
6732 convert_protocol_type(filter->proto);
6735 filter_info->proto_mask = 1;
6738 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6742 filter_info->priority = (uint8_t)filter->priority;
6747 * add or delete a ntuple filter
6750 * dev: Pointer to struct rte_eth_dev.
6751 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6752 * add: if true, add filter, if false, remove filter
6755 * - On success, zero.
6756 * - On failure, a negative value.
6759 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6760 struct rte_eth_ntuple_filter *ntuple_filter,
6763 struct ixgbe_filter_info *filter_info =
6764 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6765 struct ixgbe_5tuple_filter_info filter_5tuple;
6766 struct ixgbe_5tuple_filter *filter;
6769 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6770 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6774 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6775 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6779 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6781 if (filter != NULL && add) {
6782 PMD_DRV_LOG(ERR, "filter exists.");
6785 if (filter == NULL && !add) {
6786 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6791 filter = rte_zmalloc("ixgbe_5tuple_filter",
6792 sizeof(struct ixgbe_5tuple_filter), 0);
6795 rte_memcpy(&filter->filter_info,
6797 sizeof(struct ixgbe_5tuple_filter_info));
6798 filter->queue = ntuple_filter->queue;
6799 ret = ixgbe_add_5tuple_filter(dev, filter);
6805 ixgbe_remove_5tuple_filter(dev, filter);
6811 * get a ntuple filter
6814 * dev: Pointer to struct rte_eth_dev.
6815 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6818 * - On success, zero.
6819 * - On failure, a negative value.
6822 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6823 struct rte_eth_ntuple_filter *ntuple_filter)
6825 struct ixgbe_filter_info *filter_info =
6826 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6827 struct ixgbe_5tuple_filter_info filter_5tuple;
6828 struct ixgbe_5tuple_filter *filter;
6831 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6832 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6836 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6837 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6841 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6843 if (filter == NULL) {
6844 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6847 ntuple_filter->queue = filter->queue;
6852 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6853 * @dev: pointer to rte_eth_dev structure
6854 * @filter_op:operation will be taken.
6855 * @arg: a pointer to specific structure corresponding to the filter_op
6858 * - On success, zero.
6859 * - On failure, a negative value.
6862 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6863 enum rte_filter_op filter_op,
6866 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6869 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6871 if (filter_op == RTE_ETH_FILTER_NOP)
6875 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6880 switch (filter_op) {
6881 case RTE_ETH_FILTER_ADD:
6882 ret = ixgbe_add_del_ntuple_filter(dev,
6883 (struct rte_eth_ntuple_filter *)arg,
6886 case RTE_ETH_FILTER_DELETE:
6887 ret = ixgbe_add_del_ntuple_filter(dev,
6888 (struct rte_eth_ntuple_filter *)arg,
6891 case RTE_ETH_FILTER_GET:
6892 ret = ixgbe_get_ntuple_filter(dev,
6893 (struct rte_eth_ntuple_filter *)arg);
6896 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6904 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6905 struct rte_eth_ethertype_filter *filter,
6908 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6909 struct ixgbe_filter_info *filter_info =
6910 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6914 struct ixgbe_ethertype_filter ethertype_filter;
6916 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6919 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6920 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6921 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6922 " ethertype filter.", filter->ether_type);
6926 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6927 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6930 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6931 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6935 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6936 if (ret >= 0 && add) {
6937 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6938 filter->ether_type);
6941 if (ret < 0 && !add) {
6942 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6943 filter->ether_type);
6948 etqf = IXGBE_ETQF_FILTER_EN;
6949 etqf |= (uint32_t)filter->ether_type;
6950 etqs |= (uint32_t)((filter->queue <<
6951 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6952 IXGBE_ETQS_RX_QUEUE);
6953 etqs |= IXGBE_ETQS_QUEUE_EN;
6955 ethertype_filter.ethertype = filter->ether_type;
6956 ethertype_filter.etqf = etqf;
6957 ethertype_filter.etqs = etqs;
6958 ethertype_filter.conf = FALSE;
6959 ret = ixgbe_ethertype_filter_insert(filter_info,
6962 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6966 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6970 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6971 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6972 IXGBE_WRITE_FLUSH(hw);
6978 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6979 struct rte_eth_ethertype_filter *filter)
6981 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6982 struct ixgbe_filter_info *filter_info =
6983 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6984 uint32_t etqf, etqs;
6987 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6989 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6990 filter->ether_type);
6994 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6995 if (etqf & IXGBE_ETQF_FILTER_EN) {
6996 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6997 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6999 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
7000 IXGBE_ETQS_RX_QUEUE_SHIFT;
7007 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
7008 * @dev: pointer to rte_eth_dev structure
7009 * @filter_op:operation will be taken.
7010 * @arg: a pointer to specific structure corresponding to the filter_op
7013 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7014 enum rte_filter_op filter_op,
7017 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7020 MAC_TYPE_FILTER_SUP(hw->mac.type);
7022 if (filter_op == RTE_ETH_FILTER_NOP)
7026 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7031 switch (filter_op) {
7032 case RTE_ETH_FILTER_ADD:
7033 ret = ixgbe_add_del_ethertype_filter(dev,
7034 (struct rte_eth_ethertype_filter *)arg,
7037 case RTE_ETH_FILTER_DELETE:
7038 ret = ixgbe_add_del_ethertype_filter(dev,
7039 (struct rte_eth_ethertype_filter *)arg,
7042 case RTE_ETH_FILTER_GET:
7043 ret = ixgbe_get_ethertype_filter(dev,
7044 (struct rte_eth_ethertype_filter *)arg);
7047 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7055 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7056 enum rte_filter_type filter_type,
7057 enum rte_filter_op filter_op,
7062 switch (filter_type) {
7063 case RTE_ETH_FILTER_NTUPLE:
7064 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7066 case RTE_ETH_FILTER_ETHERTYPE:
7067 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7069 case RTE_ETH_FILTER_SYN:
7070 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7072 case RTE_ETH_FILTER_FDIR:
7073 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7075 case RTE_ETH_FILTER_L2_TUNNEL:
7076 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7078 case RTE_ETH_FILTER_GENERIC:
7079 if (filter_op != RTE_ETH_FILTER_GET)
7081 *(const void **)arg = &ixgbe_flow_ops;
7084 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7094 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7095 u8 **mc_addr_ptr, u32 *vmdq)
7100 mc_addr = *mc_addr_ptr;
7101 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7106 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7107 struct rte_ether_addr *mc_addr_set,
7108 uint32_t nb_mc_addr)
7110 struct ixgbe_hw *hw;
7113 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7114 mc_addr_list = (u8 *)mc_addr_set;
7115 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7116 ixgbe_dev_addr_list_itr, TRUE);
7120 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7122 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7123 uint64_t systime_cycles;
7125 switch (hw->mac.type) {
7126 case ixgbe_mac_X550:
7127 case ixgbe_mac_X550EM_x:
7128 case ixgbe_mac_X550EM_a:
7129 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7130 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7131 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7135 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7136 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7140 return systime_cycles;
7144 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7146 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7147 uint64_t rx_tstamp_cycles;
7149 switch (hw->mac.type) {
7150 case ixgbe_mac_X550:
7151 case ixgbe_mac_X550EM_x:
7152 case ixgbe_mac_X550EM_a:
7153 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7154 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7155 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7159 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7160 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7161 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7165 return rx_tstamp_cycles;
7169 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7171 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7172 uint64_t tx_tstamp_cycles;
7174 switch (hw->mac.type) {
7175 case ixgbe_mac_X550:
7176 case ixgbe_mac_X550EM_x:
7177 case ixgbe_mac_X550EM_a:
7178 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7179 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7180 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7184 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7185 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7186 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7190 return tx_tstamp_cycles;
7194 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7196 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7197 struct ixgbe_adapter *adapter = dev->data->dev_private;
7198 struct rte_eth_link link;
7199 uint32_t incval = 0;
7202 /* Get current link speed. */
7203 ixgbe_dev_link_update(dev, 1);
7204 rte_eth_linkstatus_get(dev, &link);
7206 switch (link.link_speed) {
7207 case ETH_SPEED_NUM_100M:
7208 incval = IXGBE_INCVAL_100;
7209 shift = IXGBE_INCVAL_SHIFT_100;
7211 case ETH_SPEED_NUM_1G:
7212 incval = IXGBE_INCVAL_1GB;
7213 shift = IXGBE_INCVAL_SHIFT_1GB;
7215 case ETH_SPEED_NUM_10G:
7217 incval = IXGBE_INCVAL_10GB;
7218 shift = IXGBE_INCVAL_SHIFT_10GB;
7222 switch (hw->mac.type) {
7223 case ixgbe_mac_X550:
7224 case ixgbe_mac_X550EM_x:
7225 case ixgbe_mac_X550EM_a:
7226 /* Independent of link speed. */
7228 /* Cycles read will be interpreted as ns. */
7231 case ixgbe_mac_X540:
7232 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7234 case ixgbe_mac_82599EB:
7235 incval >>= IXGBE_INCVAL_SHIFT_82599;
7236 shift -= IXGBE_INCVAL_SHIFT_82599;
7237 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7238 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7241 /* Not supported. */
7245 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7246 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7247 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7249 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7250 adapter->systime_tc.cc_shift = shift;
7251 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7253 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7254 adapter->rx_tstamp_tc.cc_shift = shift;
7255 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7257 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7258 adapter->tx_tstamp_tc.cc_shift = shift;
7259 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7263 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7265 struct ixgbe_adapter *adapter = dev->data->dev_private;
7267 adapter->systime_tc.nsec += delta;
7268 adapter->rx_tstamp_tc.nsec += delta;
7269 adapter->tx_tstamp_tc.nsec += delta;
7275 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7278 struct ixgbe_adapter *adapter = dev->data->dev_private;
7280 ns = rte_timespec_to_ns(ts);
7281 /* Set the timecounters to a new value. */
7282 adapter->systime_tc.nsec = ns;
7283 adapter->rx_tstamp_tc.nsec = ns;
7284 adapter->tx_tstamp_tc.nsec = ns;
7290 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7292 uint64_t ns, systime_cycles;
7293 struct ixgbe_adapter *adapter = dev->data->dev_private;
7295 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7296 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7297 *ts = rte_ns_to_timespec(ns);
7303 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7305 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7309 /* Stop the timesync system time. */
7310 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7311 /* Reset the timesync system time value. */
7312 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7313 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7315 /* Enable system time for platforms where it isn't on by default. */
7316 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7317 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7318 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7320 ixgbe_start_timecounters(dev);
7322 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7323 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7324 (RTE_ETHER_TYPE_1588 |
7325 IXGBE_ETQF_FILTER_EN |
7328 /* Enable timestamping of received PTP packets. */
7329 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7330 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7331 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7333 /* Enable timestamping of transmitted PTP packets. */
7334 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7335 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7336 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7338 IXGBE_WRITE_FLUSH(hw);
7344 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7346 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7349 /* Disable timestamping of transmitted PTP packets. */
7350 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7351 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7352 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7354 /* Disable timestamping of received PTP packets. */
7355 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7356 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7357 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7359 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7360 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7362 /* Stop incrementating the System Time registers. */
7363 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7369 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7370 struct timespec *timestamp,
7371 uint32_t flags __rte_unused)
7373 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7374 struct ixgbe_adapter *adapter = dev->data->dev_private;
7375 uint32_t tsync_rxctl;
7376 uint64_t rx_tstamp_cycles;
7379 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7380 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7383 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7384 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7385 *timestamp = rte_ns_to_timespec(ns);
7391 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7392 struct timespec *timestamp)
7394 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7395 struct ixgbe_adapter *adapter = dev->data->dev_private;
7396 uint32_t tsync_txctl;
7397 uint64_t tx_tstamp_cycles;
7400 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7401 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7404 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7405 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7406 *timestamp = rte_ns_to_timespec(ns);
7412 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7414 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7417 const struct reg_info *reg_group;
7418 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7419 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7421 while ((reg_group = reg_set[g_ind++]))
7422 count += ixgbe_regs_group_count(reg_group);
7428 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7432 const struct reg_info *reg_group;
7434 while ((reg_group = ixgbevf_regs[g_ind++]))
7435 count += ixgbe_regs_group_count(reg_group);
7441 ixgbe_get_regs(struct rte_eth_dev *dev,
7442 struct rte_dev_reg_info *regs)
7444 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7445 uint32_t *data = regs->data;
7448 const struct reg_info *reg_group;
7449 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7450 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7453 regs->length = ixgbe_get_reg_length(dev);
7454 regs->width = sizeof(uint32_t);
7458 /* Support only full register dump */
7459 if ((regs->length == 0) ||
7460 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7461 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7463 while ((reg_group = reg_set[g_ind++]))
7464 count += ixgbe_read_regs_group(dev, &data[count],
7473 ixgbevf_get_regs(struct rte_eth_dev *dev,
7474 struct rte_dev_reg_info *regs)
7476 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7477 uint32_t *data = regs->data;
7480 const struct reg_info *reg_group;
7483 regs->length = ixgbevf_get_reg_length(dev);
7484 regs->width = sizeof(uint32_t);
7488 /* Support only full register dump */
7489 if ((regs->length == 0) ||
7490 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7491 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7493 while ((reg_group = ixgbevf_regs[g_ind++]))
7494 count += ixgbe_read_regs_group(dev, &data[count],
7503 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7505 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7507 /* Return unit is byte count */
7508 return hw->eeprom.word_size * 2;
7512 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7513 struct rte_dev_eeprom_info *in_eeprom)
7515 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7516 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7517 uint16_t *data = in_eeprom->data;
7520 first = in_eeprom->offset >> 1;
7521 length = in_eeprom->length >> 1;
7522 if ((first > hw->eeprom.word_size) ||
7523 ((first + length) > hw->eeprom.word_size))
7526 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7528 return eeprom->ops.read_buffer(hw, first, length, data);
7532 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7533 struct rte_dev_eeprom_info *in_eeprom)
7535 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7536 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7537 uint16_t *data = in_eeprom->data;
7540 first = in_eeprom->offset >> 1;
7541 length = in_eeprom->length >> 1;
7542 if ((first > hw->eeprom.word_size) ||
7543 ((first + length) > hw->eeprom.word_size))
7546 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7548 return eeprom->ops.write_buffer(hw, first, length, data);
7552 ixgbe_get_module_info(struct rte_eth_dev *dev,
7553 struct rte_eth_dev_module_info *modinfo)
7555 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7557 uint8_t sff8472_rev, addr_mode;
7558 bool page_swap = false;
7560 /* Check whether we support SFF-8472 or not */
7561 status = hw->phy.ops.read_i2c_eeprom(hw,
7562 IXGBE_SFF_SFF_8472_COMP,
7567 /* addressing mode is not supported */
7568 status = hw->phy.ops.read_i2c_eeprom(hw,
7569 IXGBE_SFF_SFF_8472_SWAP,
7574 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7576 "Address change required to access page 0xA2, "
7577 "but not supported. Please report the module "
7578 "type to the driver maintainers.");
7582 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7583 /* We have a SFP, but it does not support SFF-8472 */
7584 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7585 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7587 /* We have a SFP which supports a revision of SFF-8472. */
7588 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7589 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7596 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7597 struct rte_dev_eeprom_info *info)
7599 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7600 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7601 uint8_t databyte = 0xFF;
7602 uint8_t *data = info->data;
7605 if (info->length == 0)
7608 for (i = info->offset; i < info->offset + info->length; i++) {
7609 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7610 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7612 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7617 data[i - info->offset] = databyte;
7624 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7626 case ixgbe_mac_X550:
7627 case ixgbe_mac_X550EM_x:
7628 case ixgbe_mac_X550EM_a:
7629 return ETH_RSS_RETA_SIZE_512;
7630 case ixgbe_mac_X550_vf:
7631 case ixgbe_mac_X550EM_x_vf:
7632 case ixgbe_mac_X550EM_a_vf:
7633 return ETH_RSS_RETA_SIZE_64;
7634 case ixgbe_mac_X540_vf:
7635 case ixgbe_mac_82599_vf:
7638 return ETH_RSS_RETA_SIZE_128;
7643 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7645 case ixgbe_mac_X550:
7646 case ixgbe_mac_X550EM_x:
7647 case ixgbe_mac_X550EM_a:
7648 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7649 return IXGBE_RETA(reta_idx >> 2);
7651 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7652 case ixgbe_mac_X550_vf:
7653 case ixgbe_mac_X550EM_x_vf:
7654 case ixgbe_mac_X550EM_a_vf:
7655 return IXGBE_VFRETA(reta_idx >> 2);
7657 return IXGBE_RETA(reta_idx >> 2);
7662 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7664 case ixgbe_mac_X550_vf:
7665 case ixgbe_mac_X550EM_x_vf:
7666 case ixgbe_mac_X550EM_a_vf:
7667 return IXGBE_VFMRQC;
7674 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7676 case ixgbe_mac_X550_vf:
7677 case ixgbe_mac_X550EM_x_vf:
7678 case ixgbe_mac_X550EM_a_vf:
7679 return IXGBE_VFRSSRK(i);
7681 return IXGBE_RSSRK(i);
7686 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7688 case ixgbe_mac_82599_vf:
7689 case ixgbe_mac_X540_vf:
7697 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7698 struct rte_eth_dcb_info *dcb_info)
7700 struct ixgbe_dcb_config *dcb_config =
7701 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7702 struct ixgbe_dcb_tc_config *tc;
7703 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7707 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7708 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7710 dcb_info->nb_tcs = 1;
7712 tc_queue = &dcb_info->tc_queue;
7713 nb_tcs = dcb_info->nb_tcs;
7715 if (dcb_config->vt_mode) { /* vt is enabled*/
7716 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7717 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7718 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7719 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7720 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7721 for (j = 0; j < nb_tcs; j++) {
7722 tc_queue->tc_rxq[0][j].base = j;
7723 tc_queue->tc_rxq[0][j].nb_queue = 1;
7724 tc_queue->tc_txq[0][j].base = j;
7725 tc_queue->tc_txq[0][j].nb_queue = 1;
7728 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7729 for (j = 0; j < nb_tcs; j++) {
7730 tc_queue->tc_rxq[i][j].base =
7732 tc_queue->tc_rxq[i][j].nb_queue = 1;
7733 tc_queue->tc_txq[i][j].base =
7735 tc_queue->tc_txq[i][j].nb_queue = 1;
7739 } else { /* vt is disabled*/
7740 struct rte_eth_dcb_rx_conf *rx_conf =
7741 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7742 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7743 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7744 if (dcb_info->nb_tcs == ETH_4_TCS) {
7745 for (i = 0; i < dcb_info->nb_tcs; i++) {
7746 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7747 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7749 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7750 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7751 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7752 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7753 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7754 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7755 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7756 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7757 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7758 for (i = 0; i < dcb_info->nb_tcs; i++) {
7759 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7760 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7762 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7763 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7764 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7765 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7766 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7767 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7768 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7769 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7770 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7771 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7772 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7773 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7774 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7775 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7776 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7777 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7780 for (i = 0; i < dcb_info->nb_tcs; i++) {
7781 tc = &dcb_config->tc_config[i];
7782 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7787 /* Update e-tag ether type */
7789 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7790 uint16_t ether_type)
7792 uint32_t etag_etype;
7794 if (hw->mac.type != ixgbe_mac_X550 &&
7795 hw->mac.type != ixgbe_mac_X550EM_x &&
7796 hw->mac.type != ixgbe_mac_X550EM_a) {
7800 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7801 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7802 etag_etype |= ether_type;
7803 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7804 IXGBE_WRITE_FLUSH(hw);
7809 /* Config l2 tunnel ether type */
7811 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7812 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7815 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7816 struct ixgbe_l2_tn_info *l2_tn_info =
7817 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7819 if (l2_tunnel == NULL)
7822 switch (l2_tunnel->l2_tunnel_type) {
7823 case RTE_L2_TUNNEL_TYPE_E_TAG:
7824 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7825 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7828 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7836 /* Enable e-tag tunnel */
7838 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7840 uint32_t etag_etype;
7842 if (hw->mac.type != ixgbe_mac_X550 &&
7843 hw->mac.type != ixgbe_mac_X550EM_x &&
7844 hw->mac.type != ixgbe_mac_X550EM_a) {
7848 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7849 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7850 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7851 IXGBE_WRITE_FLUSH(hw);
7856 /* Enable l2 tunnel */
7858 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7859 enum rte_eth_tunnel_type l2_tunnel_type)
7862 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7863 struct ixgbe_l2_tn_info *l2_tn_info =
7864 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7866 switch (l2_tunnel_type) {
7867 case RTE_L2_TUNNEL_TYPE_E_TAG:
7868 l2_tn_info->e_tag_en = TRUE;
7869 ret = ixgbe_e_tag_enable(hw);
7872 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7880 /* Disable e-tag tunnel */
7882 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7884 uint32_t etag_etype;
7886 if (hw->mac.type != ixgbe_mac_X550 &&
7887 hw->mac.type != ixgbe_mac_X550EM_x &&
7888 hw->mac.type != ixgbe_mac_X550EM_a) {
7892 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7893 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7894 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7895 IXGBE_WRITE_FLUSH(hw);
7900 /* Disable l2 tunnel */
7902 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7903 enum rte_eth_tunnel_type l2_tunnel_type)
7906 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7907 struct ixgbe_l2_tn_info *l2_tn_info =
7908 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7910 switch (l2_tunnel_type) {
7911 case RTE_L2_TUNNEL_TYPE_E_TAG:
7912 l2_tn_info->e_tag_en = FALSE;
7913 ret = ixgbe_e_tag_disable(hw);
7916 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7925 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7926 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7929 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7930 uint32_t i, rar_entries;
7931 uint32_t rar_low, rar_high;
7933 if (hw->mac.type != ixgbe_mac_X550 &&
7934 hw->mac.type != ixgbe_mac_X550EM_x &&
7935 hw->mac.type != ixgbe_mac_X550EM_a) {
7939 rar_entries = ixgbe_get_num_rx_addrs(hw);
7941 for (i = 1; i < rar_entries; i++) {
7942 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7943 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7944 if ((rar_high & IXGBE_RAH_AV) &&
7945 (rar_high & IXGBE_RAH_ADTYPE) &&
7946 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7947 l2_tunnel->tunnel_id)) {
7948 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7949 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7951 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7961 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7962 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7965 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7966 uint32_t i, rar_entries;
7967 uint32_t rar_low, rar_high;
7969 if (hw->mac.type != ixgbe_mac_X550 &&
7970 hw->mac.type != ixgbe_mac_X550EM_x &&
7971 hw->mac.type != ixgbe_mac_X550EM_a) {
7975 /* One entry for one tunnel. Try to remove potential existing entry. */
7976 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7978 rar_entries = ixgbe_get_num_rx_addrs(hw);
7980 for (i = 1; i < rar_entries; i++) {
7981 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7982 if (rar_high & IXGBE_RAH_AV) {
7985 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7986 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7987 rar_low = l2_tunnel->tunnel_id;
7989 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7990 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7996 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7997 " Please remove a rule before adding a new one.");
8001 static inline struct ixgbe_l2_tn_filter *
8002 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
8003 struct ixgbe_l2_tn_key *key)
8007 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
8011 return l2_tn_info->hash_map[ret];
8015 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8016 struct ixgbe_l2_tn_filter *l2_tn_filter)
8020 ret = rte_hash_add_key(l2_tn_info->hash_handle,
8021 &l2_tn_filter->key);
8025 "Failed to insert L2 tunnel filter"
8026 " to hash table %d!",
8031 l2_tn_info->hash_map[ret] = l2_tn_filter;
8033 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8039 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8040 struct ixgbe_l2_tn_key *key)
8043 struct ixgbe_l2_tn_filter *l2_tn_filter;
8045 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8049 "No such L2 tunnel filter to delete %d!",
8054 l2_tn_filter = l2_tn_info->hash_map[ret];
8055 l2_tn_info->hash_map[ret] = NULL;
8057 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8058 rte_free(l2_tn_filter);
8063 /* Add l2 tunnel filter */
8065 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8066 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8070 struct ixgbe_l2_tn_info *l2_tn_info =
8071 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8072 struct ixgbe_l2_tn_key key;
8073 struct ixgbe_l2_tn_filter *node;
8076 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8077 key.tn_id = l2_tunnel->tunnel_id;
8079 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8083 "The L2 tunnel filter already exists!");
8087 node = rte_zmalloc("ixgbe_l2_tn",
8088 sizeof(struct ixgbe_l2_tn_filter),
8093 rte_memcpy(&node->key,
8095 sizeof(struct ixgbe_l2_tn_key));
8096 node->pool = l2_tunnel->pool;
8097 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8104 switch (l2_tunnel->l2_tunnel_type) {
8105 case RTE_L2_TUNNEL_TYPE_E_TAG:
8106 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8109 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8114 if ((!restore) && (ret < 0))
8115 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8120 /* Delete l2 tunnel filter */
8122 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8123 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8126 struct ixgbe_l2_tn_info *l2_tn_info =
8127 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8128 struct ixgbe_l2_tn_key key;
8130 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8131 key.tn_id = l2_tunnel->tunnel_id;
8132 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8136 switch (l2_tunnel->l2_tunnel_type) {
8137 case RTE_L2_TUNNEL_TYPE_E_TAG:
8138 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8141 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8150 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8151 * @dev: pointer to rte_eth_dev structure
8152 * @filter_op:operation will be taken.
8153 * @arg: a pointer to specific structure corresponding to the filter_op
8156 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8157 enum rte_filter_op filter_op,
8162 if (filter_op == RTE_ETH_FILTER_NOP)
8166 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8171 switch (filter_op) {
8172 case RTE_ETH_FILTER_ADD:
8173 ret = ixgbe_dev_l2_tunnel_filter_add
8175 (struct rte_eth_l2_tunnel_conf *)arg,
8178 case RTE_ETH_FILTER_DELETE:
8179 ret = ixgbe_dev_l2_tunnel_filter_del
8181 (struct rte_eth_l2_tunnel_conf *)arg);
8184 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8192 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8196 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8198 if (hw->mac.type != ixgbe_mac_X550 &&
8199 hw->mac.type != ixgbe_mac_X550EM_x &&
8200 hw->mac.type != ixgbe_mac_X550EM_a) {
8204 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8205 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8207 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8208 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8213 /* Enable l2 tunnel forwarding */
8215 ixgbe_dev_l2_tunnel_forwarding_enable
8216 (struct rte_eth_dev *dev,
8217 enum rte_eth_tunnel_type l2_tunnel_type)
8219 struct ixgbe_l2_tn_info *l2_tn_info =
8220 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8223 switch (l2_tunnel_type) {
8224 case RTE_L2_TUNNEL_TYPE_E_TAG:
8225 l2_tn_info->e_tag_fwd_en = TRUE;
8226 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8229 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8237 /* Disable l2 tunnel forwarding */
8239 ixgbe_dev_l2_tunnel_forwarding_disable
8240 (struct rte_eth_dev *dev,
8241 enum rte_eth_tunnel_type l2_tunnel_type)
8243 struct ixgbe_l2_tn_info *l2_tn_info =
8244 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8247 switch (l2_tunnel_type) {
8248 case RTE_L2_TUNNEL_TYPE_E_TAG:
8249 l2_tn_info->e_tag_fwd_en = FALSE;
8250 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8253 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8262 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8263 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8266 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8268 uint32_t vmtir, vmvir;
8269 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8271 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8273 "VF id %u should be less than %u",
8279 if (hw->mac.type != ixgbe_mac_X550 &&
8280 hw->mac.type != ixgbe_mac_X550EM_x &&
8281 hw->mac.type != ixgbe_mac_X550EM_a) {
8286 vmtir = l2_tunnel->tunnel_id;
8290 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8292 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8293 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8295 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8296 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8301 /* Enable l2 tunnel tag insertion */
8303 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8304 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8308 switch (l2_tunnel->l2_tunnel_type) {
8309 case RTE_L2_TUNNEL_TYPE_E_TAG:
8310 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8313 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8321 /* Disable l2 tunnel tag insertion */
8323 ixgbe_dev_l2_tunnel_insertion_disable
8324 (struct rte_eth_dev *dev,
8325 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8329 switch (l2_tunnel->l2_tunnel_type) {
8330 case RTE_L2_TUNNEL_TYPE_E_TAG:
8331 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8334 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8343 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8348 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8350 if (hw->mac.type != ixgbe_mac_X550 &&
8351 hw->mac.type != ixgbe_mac_X550EM_x &&
8352 hw->mac.type != ixgbe_mac_X550EM_a) {
8356 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8358 qde |= IXGBE_QDE_STRIP_TAG;
8360 qde &= ~IXGBE_QDE_STRIP_TAG;
8361 qde &= ~IXGBE_QDE_READ;
8362 qde |= IXGBE_QDE_WRITE;
8363 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8368 /* Enable l2 tunnel tag stripping */
8370 ixgbe_dev_l2_tunnel_stripping_enable
8371 (struct rte_eth_dev *dev,
8372 enum rte_eth_tunnel_type l2_tunnel_type)
8376 switch (l2_tunnel_type) {
8377 case RTE_L2_TUNNEL_TYPE_E_TAG:
8378 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8381 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8389 /* Disable l2 tunnel tag stripping */
8391 ixgbe_dev_l2_tunnel_stripping_disable
8392 (struct rte_eth_dev *dev,
8393 enum rte_eth_tunnel_type l2_tunnel_type)
8397 switch (l2_tunnel_type) {
8398 case RTE_L2_TUNNEL_TYPE_E_TAG:
8399 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8402 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8410 /* Enable/disable l2 tunnel offload functions */
8412 ixgbe_dev_l2_tunnel_offload_set
8413 (struct rte_eth_dev *dev,
8414 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8420 if (l2_tunnel == NULL)
8424 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8426 ret = ixgbe_dev_l2_tunnel_enable(
8428 l2_tunnel->l2_tunnel_type);
8430 ret = ixgbe_dev_l2_tunnel_disable(
8432 l2_tunnel->l2_tunnel_type);
8435 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8437 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8441 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8446 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8448 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8450 l2_tunnel->l2_tunnel_type);
8452 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8454 l2_tunnel->l2_tunnel_type);
8457 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8459 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8461 l2_tunnel->l2_tunnel_type);
8463 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8465 l2_tunnel->l2_tunnel_type);
8472 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8475 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8476 IXGBE_WRITE_FLUSH(hw);
8481 /* There's only one register for VxLAN UDP port.
8482 * So, we cannot add several ports. Will update it.
8485 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8489 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8493 return ixgbe_update_vxlan_port(hw, port);
8496 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8497 * UDP port, it must have a value.
8498 * So, will reset it to the original value 0.
8501 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8506 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8508 if (cur_port != port) {
8509 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8513 return ixgbe_update_vxlan_port(hw, 0);
8516 /* Add UDP tunneling port */
8518 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8519 struct rte_eth_udp_tunnel *udp_tunnel)
8522 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8524 if (hw->mac.type != ixgbe_mac_X550 &&
8525 hw->mac.type != ixgbe_mac_X550EM_x &&
8526 hw->mac.type != ixgbe_mac_X550EM_a) {
8530 if (udp_tunnel == NULL)
8533 switch (udp_tunnel->prot_type) {
8534 case RTE_TUNNEL_TYPE_VXLAN:
8535 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8538 case RTE_TUNNEL_TYPE_GENEVE:
8539 case RTE_TUNNEL_TYPE_TEREDO:
8540 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8545 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8553 /* Remove UDP tunneling port */
8555 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8556 struct rte_eth_udp_tunnel *udp_tunnel)
8559 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8561 if (hw->mac.type != ixgbe_mac_X550 &&
8562 hw->mac.type != ixgbe_mac_X550EM_x &&
8563 hw->mac.type != ixgbe_mac_X550EM_a) {
8567 if (udp_tunnel == NULL)
8570 switch (udp_tunnel->prot_type) {
8571 case RTE_TUNNEL_TYPE_VXLAN:
8572 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8574 case RTE_TUNNEL_TYPE_GENEVE:
8575 case RTE_TUNNEL_TYPE_TEREDO:
8576 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8580 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8589 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8591 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8594 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8598 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8610 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8612 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8615 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8619 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8631 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8633 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8635 int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8637 switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8641 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8653 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8655 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8658 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8662 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8673 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8675 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8678 /* peek the message first */
8679 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8681 /* PF reset VF event */
8682 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8683 /* dummy mbx read to ack pf */
8684 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8686 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8692 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8695 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8696 struct ixgbe_interrupt *intr =
8697 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8698 ixgbevf_intr_disable(dev);
8700 /* read-on-clear nic registers here */
8701 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8704 /* only one misc vector supported - mailbox */
8705 eicr &= IXGBE_VTEICR_MASK;
8706 if (eicr == IXGBE_MISC_VEC_ID)
8707 intr->flags |= IXGBE_FLAG_MAILBOX;
8713 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8715 struct ixgbe_interrupt *intr =
8716 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8718 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8719 ixgbevf_mbx_process(dev);
8720 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8723 ixgbevf_intr_enable(dev);
8729 ixgbevf_dev_interrupt_handler(void *param)
8731 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8733 ixgbevf_dev_interrupt_get_status(dev);
8734 ixgbevf_dev_interrupt_action(dev);
8738 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8739 * @hw: pointer to hardware structure
8741 * Stops the transmit data path and waits for the HW to internally empty
8742 * the Tx security block
8744 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8746 #define IXGBE_MAX_SECTX_POLL 40
8751 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8752 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8753 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8754 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8755 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8756 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8758 /* Use interrupt-safe sleep just in case */
8762 /* For informational purposes only */
8763 if (i >= IXGBE_MAX_SECTX_POLL)
8764 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8765 "path fully disabled. Continuing with init.");
8767 return IXGBE_SUCCESS;
8771 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8772 * @hw: pointer to hardware structure
8774 * Enables the transmit data path.
8776 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8780 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8781 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8782 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8783 IXGBE_WRITE_FLUSH(hw);
8785 return IXGBE_SUCCESS;
8788 /* restore n-tuple filter */
8790 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8792 struct ixgbe_filter_info *filter_info =
8793 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8794 struct ixgbe_5tuple_filter *node;
8796 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8797 ixgbe_inject_5tuple_filter(dev, node);
8801 /* restore ethernet type filter */
8803 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8805 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8806 struct ixgbe_filter_info *filter_info =
8807 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8810 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8811 if (filter_info->ethertype_mask & (1 << i)) {
8812 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8813 filter_info->ethertype_filters[i].etqf);
8814 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8815 filter_info->ethertype_filters[i].etqs);
8816 IXGBE_WRITE_FLUSH(hw);
8821 /* restore SYN filter */
8823 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8825 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8826 struct ixgbe_filter_info *filter_info =
8827 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8830 synqf = filter_info->syn_info;
8832 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8833 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8834 IXGBE_WRITE_FLUSH(hw);
8838 /* restore L2 tunnel filter */
8840 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8842 struct ixgbe_l2_tn_info *l2_tn_info =
8843 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8844 struct ixgbe_l2_tn_filter *node;
8845 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8847 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8848 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8849 l2_tn_conf.tunnel_id = node->key.tn_id;
8850 l2_tn_conf.pool = node->pool;
8851 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8855 /* restore rss filter */
8857 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8859 struct ixgbe_filter_info *filter_info =
8860 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8862 if (filter_info->rss_info.conf.queue_num)
8863 ixgbe_config_rss_filter(dev,
8864 &filter_info->rss_info, TRUE);
8868 ixgbe_filter_restore(struct rte_eth_dev *dev)
8870 ixgbe_ntuple_filter_restore(dev);
8871 ixgbe_ethertype_filter_restore(dev);
8872 ixgbe_syn_filter_restore(dev);
8873 ixgbe_fdir_filter_restore(dev);
8874 ixgbe_l2_tn_filter_restore(dev);
8875 ixgbe_rss_filter_restore(dev);
8881 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8883 struct ixgbe_l2_tn_info *l2_tn_info =
8884 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8885 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8887 if (l2_tn_info->e_tag_en)
8888 (void)ixgbe_e_tag_enable(hw);
8890 if (l2_tn_info->e_tag_fwd_en)
8891 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8893 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8896 /* remove all the n-tuple filters */
8898 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8900 struct ixgbe_filter_info *filter_info =
8901 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8902 struct ixgbe_5tuple_filter *p_5tuple;
8904 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8905 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8908 /* remove all the ether type filters */
8910 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8912 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8913 struct ixgbe_filter_info *filter_info =
8914 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8917 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8918 if (filter_info->ethertype_mask & (1 << i) &&
8919 !filter_info->ethertype_filters[i].conf) {
8920 (void)ixgbe_ethertype_filter_remove(filter_info,
8922 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8923 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8924 IXGBE_WRITE_FLUSH(hw);
8929 /* remove the SYN filter */
8931 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8933 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8934 struct ixgbe_filter_info *filter_info =
8935 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8937 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8938 filter_info->syn_info = 0;
8940 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8941 IXGBE_WRITE_FLUSH(hw);
8945 /* remove all the L2 tunnel filters */
8947 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8949 struct ixgbe_l2_tn_info *l2_tn_info =
8950 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8951 struct ixgbe_l2_tn_filter *l2_tn_filter;
8952 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8955 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8956 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8957 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8958 l2_tn_conf.pool = l2_tn_filter->pool;
8959 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8968 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8969 struct ixgbe_macsec_setting *macsec_setting)
8971 struct ixgbe_macsec_setting *macsec =
8972 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8974 macsec->offload_en = macsec_setting->offload_en;
8975 macsec->encrypt_en = macsec_setting->encrypt_en;
8976 macsec->replayprotect_en = macsec_setting->replayprotect_en;
8980 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8982 struct ixgbe_macsec_setting *macsec =
8983 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8985 macsec->offload_en = 0;
8986 macsec->encrypt_en = 0;
8987 macsec->replayprotect_en = 0;
8991 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8992 struct ixgbe_macsec_setting *macsec_setting)
8994 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8996 uint8_t en = macsec_setting->encrypt_en;
8997 uint8_t rp = macsec_setting->replayprotect_en;
9001 * As no ixgbe_disable_sec_rx_path equivalent is
9002 * implemented for tx in the base code, and we are
9003 * not allowed to modify the base code in DPDK, so
9004 * just call the hand-written one directly for now.
9005 * The hardware support has been checked by
9006 * ixgbe_disable_sec_rx_path().
9008 ixgbe_disable_sec_tx_path_generic(hw);
9010 /* Enable Ethernet CRC (required by MACsec offload) */
9011 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9012 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9013 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9015 /* Enable the TX and RX crypto engines */
9016 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9017 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9018 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9020 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9021 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9022 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9024 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9025 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9027 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9029 /* Enable SA lookup */
9030 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9031 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9032 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9033 IXGBE_LSECTXCTRL_AUTH;
9034 ctrl |= IXGBE_LSECTXCTRL_AISCI;
9035 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9036 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9037 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9039 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9040 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9041 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9042 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9044 ctrl |= IXGBE_LSECRXCTRL_RP;
9046 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9047 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9049 /* Start the data paths */
9050 ixgbe_enable_sec_rx_path(hw);
9053 * As no ixgbe_enable_sec_rx_path equivalent is
9054 * implemented for tx in the base code, and we are
9055 * not allowed to modify the base code in DPDK, so
9056 * just call the hand-written one directly for now.
9058 ixgbe_enable_sec_tx_path_generic(hw);
9062 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9064 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9069 * As no ixgbe_disable_sec_rx_path equivalent is
9070 * implemented for tx in the base code, and we are
9071 * not allowed to modify the base code in DPDK, so
9072 * just call the hand-written one directly for now.
9073 * The hardware support has been checked by
9074 * ixgbe_disable_sec_rx_path().
9076 ixgbe_disable_sec_tx_path_generic(hw);
9078 /* Disable the TX and RX crypto engines */
9079 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9080 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9081 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9083 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9084 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9085 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9087 /* Disable SA lookup */
9088 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9089 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9090 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9091 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9093 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9094 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9095 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9096 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9098 /* Start the data paths */
9099 ixgbe_enable_sec_rx_path(hw);
9102 * As no ixgbe_enable_sec_rx_path equivalent is
9103 * implemented for tx in the base code, and we are
9104 * not allowed to modify the base code in DPDK, so
9105 * just call the hand-written one directly for now.
9107 ixgbe_enable_sec_tx_path_generic(hw);
9110 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9111 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9112 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9113 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9114 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9115 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9116 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9117 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9119 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
9120 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
9122 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9123 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
9125 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9126 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
9128 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9129 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);