drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIB_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter);
 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 306                         enum rte_filter_op filter_op,
 307                         void *arg);
 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 311                         struct ixgbe_5tuple_filter *filter);
 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 313                                 enum rte_filter_op filter_op,
 314                                 void *arg);
 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter);
 317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 318                                 enum rte_filter_op filter_op,
 319                                 void *arg);
 320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 321                         struct rte_eth_ethertype_filter *filter);
 322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                      enum rte_filter_type filter_type,
 324                      enum rte_filter_op filter_op,
 325                      void *arg);
 326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 327
 328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 329                                       struct rte_ether_addr *mc_addr_set,
 330                                       uint32_t nb_mc_addr);
 331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                    struct rte_eth_dcb_info *dcb_info);
 333
 334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 336                             struct rte_dev_reg_info *regs);
 337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 341                                 struct rte_dev_eeprom_info *eeprom);
 342
 343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 344                                  struct rte_eth_dev_module_info *modinfo);
 345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 346                                    struct rte_dev_eeprom_info *info);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364 static void ixgbevf_dev_interrupt_handler(void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 384
 385 /*
 386  * Define VF Stats MACRO for Non "cleared on read" register
 387  */
 388 #define UPDATE_VF_STAT(reg, last, cur)                          \
 389 {                                                               \
 390         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 391         cur += (latest - last) & UINT_MAX;                      \
 392         last = latest;                                          \
 393 }
 394
 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 396 {                                                                \
 397         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 398         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 399         u64 latest = ((new_msb << 32) | new_lsb);                \
 400         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 401         last = latest;                                           \
 402 }
 403
 404 #define IXGBE_SET_HWSTRIP(h, q) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (h)->bitmap[idx] |= 1 << bit;\
 408         } while (0)
 409
 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] &= ~(1 << bit);\
 414         } while (0)
 415
 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (r) = (h)->bitmap[idx] >> bit & 1;\
 420         } while (0)
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 476 #endif
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 /*
 481  * The set of PCI devices this driver supports (for 82599 VF)
 482  */
 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 static const struct rte_eth_desc_lim rx_desc_lim = {
 498         .nb_max = IXGBE_MAX_RING_DESC,
 499         .nb_min = IXGBE_MIN_RING_DESC,
 500         .nb_align = IXGBE_RXD_ALIGN,
 501 };
 502
 503 static const struct rte_eth_desc_lim tx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_TXD_ALIGN,
 507         .nb_seg_max = IXGBE_TX_MAX_SEG,
 508         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 509 };
 510
 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 512         .dev_configure        = ixgbe_dev_configure,
 513         .dev_start            = ixgbe_dev_start,
 514         .dev_stop             = ixgbe_dev_stop,
 515         .dev_set_link_up    = ixgbe_dev_set_link_up,
 516         .dev_set_link_down  = ixgbe_dev_set_link_down,
 517         .dev_close            = ixgbe_dev_close,
 518         .dev_reset            = ixgbe_dev_reset,
 519         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 520         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 521         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 522         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 523         .link_update          = ixgbe_dev_link_update,
 524         .stats_get            = ixgbe_dev_stats_get,
 525         .xstats_get           = ixgbe_dev_xstats_get,
 526         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 527         .stats_reset          = ixgbe_dev_stats_reset,
 528         .xstats_reset         = ixgbe_dev_xstats_reset,
 529         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 530         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 531         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 532         .fw_version_get       = ixgbe_fw_version_get,
 533         .dev_infos_get        = ixgbe_dev_info_get,
 534         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 535         .mtu_set              = ixgbe_dev_mtu_set,
 536         .vlan_filter_set      = ixgbe_vlan_filter_set,
 537         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 538         .vlan_offload_set     = ixgbe_vlan_offload_set,
 539         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 540         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 541         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 542         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 543         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 544         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 545         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 546         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 547         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 548         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 549         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 550         .dev_led_on           = ixgbe_dev_led_on,
 551         .dev_led_off          = ixgbe_dev_led_off,
 552         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 553         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 554         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 555         .mac_addr_add         = ixgbe_add_rar,
 556         .mac_addr_remove      = ixgbe_remove_rar,
 557         .mac_addr_set         = ixgbe_set_default_mac_addr,
 558         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 559         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 560         .mirror_rule_set      = ixgbe_mirror_rule_set,
 561         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 562         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 563         .reta_update          = ixgbe_dev_rss_reta_update,
 564         .reta_query           = ixgbe_dev_rss_reta_query,
 565         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 566         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 567         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 568         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 569         .rxq_info_get         = ixgbe_rxq_info_get,
 570         .txq_info_get         = ixgbe_txq_info_get,
 571         .timesync_enable      = ixgbe_timesync_enable,
 572         .timesync_disable     = ixgbe_timesync_disable,
 573         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 574         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 575         .get_reg              = ixgbe_get_regs,
 576         .get_eeprom_length    = ixgbe_get_eeprom_length,
 577         .get_eeprom           = ixgbe_get_eeprom,
 578         .set_eeprom           = ixgbe_set_eeprom,
 579         .get_module_info      = ixgbe_get_module_info,
 580         .get_module_eeprom    = ixgbe_get_module_eeprom,
 581         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 582         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 583         .timesync_read_time   = ixgbe_timesync_read_time,
 584         .timesync_write_time  = ixgbe_timesync_write_time,
 585         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 586         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 587         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 588         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 589         .tm_ops_get           = ixgbe_tm_ops_get,
 590         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 591 };
 592
 593 /*
 594  * dev_ops for virtual function, bare necessities for basic vf
 595  * operation have been implemented
 596  */
 597 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 598         .dev_configure        = ixgbevf_dev_configure,
 599         .dev_start            = ixgbevf_dev_start,
 600         .dev_stop             = ixgbevf_dev_stop,
 601         .link_update          = ixgbevf_dev_link_update,
 602         .stats_get            = ixgbevf_dev_stats_get,
 603         .xstats_get           = ixgbevf_dev_xstats_get,
 604         .stats_reset          = ixgbevf_dev_stats_reset,
 605         .xstats_reset         = ixgbevf_dev_stats_reset,
 606         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 607         .dev_close            = ixgbevf_dev_close,
 608         .dev_reset            = ixgbevf_dev_reset,
 609         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 610         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 611         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 612         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 613         .dev_infos_get        = ixgbevf_dev_info_get,
 614         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 615         .mtu_set              = ixgbevf_dev_set_mtu,
 616         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 617         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 618         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 619         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 620         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 621         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 622         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 623         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 624         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 625         .mac_addr_add         = ixgbevf_add_mac_addr,
 626         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 627         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 628         .rxq_info_get         = ixgbe_rxq_info_get,
 629         .txq_info_get         = ixgbe_txq_info_get,
 630         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 631         .get_reg              = ixgbevf_get_regs,
 632         .reta_update          = ixgbe_dev_rss_reta_update,
 633         .reta_query           = ixgbe_dev_rss_reta_query,
 634         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 635         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 636         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 637 };
 638
 639 /* store statistics names and its offset in stats structure */
 640 struct rte_ixgbe_xstats_name_off {
 641         char name[RTE_ETH_XSTATS_NAME_SIZE];
 642         unsigned offset;
 643 };
 644
 645 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 646         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 647         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 648         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 649         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 650         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 651         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 652         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 653         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 654         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 655         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 656         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 657         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 658         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 659         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 660         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 661                 prc1023)},
 662         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 663                 prc1522)},
 664         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 665         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 666         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 667         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 668         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 669         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 670         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 671         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 672         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 673         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 674         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 675         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 676         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 677         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 678         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 679         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 680         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 681                 ptc1023)},
 682         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 683                 ptc1522)},
 684         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 685         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 686         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 687         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 688
 689         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirustat_add)},
 691         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 692                 fdirustat_remove)},
 693         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 694                 fdirfstat_fadd)},
 695         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 696                 fdirfstat_fremove)},
 697         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirmatch)},
 699         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 700                 fdirmiss)},
 701
 702         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 703         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 704         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 705                 fclast)},
 706         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 707         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 708         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 709         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 710         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 711                 fcoe_noddp)},
 712         {"rx_fcoe_no_direct_data_placement_ext_buff",
 713                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 714
 715         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 716                 lxontxc)},
 717         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 718                 lxonrxc)},
 719         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 720                 lxofftxc)},
 721         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 722                 lxoffrxc)},
 723         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 724 };
 725
 726 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 727                            sizeof(rte_ixgbe_stats_strings[0]))
 728
 729 /* MACsec statistics */
 730 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 731         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 out_pkts_untagged)},
 733         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 734                 out_pkts_encrypted)},
 735         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 736                 out_pkts_protected)},
 737         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 738                 out_octets_encrypted)},
 739         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 740                 out_octets_protected)},
 741         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_untagged)},
 743         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_badtag)},
 745         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_nosci)},
 747         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_unknownsci)},
 749         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 750                 in_octets_decrypted)},
 751         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 752                 in_octets_validated)},
 753         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_unchecked)},
 755         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_delayed)},
 757         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_late)},
 759         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_ok)},
 761         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_invalid)},
 763         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_notvalid)},
 765         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_unusedsa)},
 767         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_notusingsa)},
 769 };
 770
 771 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 772                            sizeof(rte_ixgbe_macsec_strings[0]))
 773
 774 /* Per-queue statistics */
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 776         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 777         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 778         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 779         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 780 };
 781
 782 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 783                            sizeof(rte_ixgbe_rxq_strings[0]))
 784 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 785
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 787         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 788         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 789         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 790                 pxon2offc)},
 791 };
 792
 793 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 794                            sizeof(rte_ixgbe_txq_strings[0]))
 795 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 796
 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 798         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 799 };
 800
 801 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 802                 sizeof(rte_ixgbevf_stats_strings[0]))
 803
 804 /*
 805  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 806  */
 807 static inline int
 808 ixgbe_is_sfp(struct ixgbe_hw *hw)
 809 {
 810         switch (hw->phy.type) {
 811         case ixgbe_phy_sfp_avago:
 812         case ixgbe_phy_sfp_ftl:
 813         case ixgbe_phy_sfp_intel:
 814         case ixgbe_phy_sfp_unknown:
 815         case ixgbe_phy_sfp_passive_tyco:
 816         case ixgbe_phy_sfp_passive_unknown:
 817                 return 1;
 818         default:
 819                 return 0;
 820         }
 821 }
 822
 823 static inline int32_t
 824 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 825 {
 826         uint32_t ctrl_ext;
 827         int32_t status;
 828
 829         status = ixgbe_reset_hw(hw);
 830
 831         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 832         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 833         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 834         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 835         IXGBE_WRITE_FLUSH(hw);
 836
 837         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 838                 status = IXGBE_SUCCESS;
 839         return status;
 840 }
 841
 842 static inline void
 843 ixgbe_enable_intr(struct rte_eth_dev *dev)
 844 {
 845         struct ixgbe_interrupt *intr =
 846                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 847         struct ixgbe_hw *hw =
 848                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 849
 850         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 851         IXGBE_WRITE_FLUSH(hw);
 852 }
 853
 854 /*
 855  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 856  */
 857 static void
 858 ixgbe_disable_intr(struct ixgbe_hw *hw)
 859 {
 860         PMD_INIT_FUNC_TRACE();
 861
 862         if (hw->mac.type == ixgbe_mac_82598EB) {
 863                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 864         } else {
 865                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 866                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 867                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 868         }
 869         IXGBE_WRITE_FLUSH(hw);
 870 }
 871
 872 /*
 873  * This function resets queue statistics mapping registers.
 874  * From Niantic datasheet, Initialization of Statistics section:
 875  * "...if software requires the queue counters, the RQSMR and TQSM registers
 876  * must be re-programmed following a device reset.
 877  */
 878 static void
 879 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 880 {
 881         uint32_t i;
 882
 883         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 884                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 885                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 886         }
 887 }
 888
 889
 890 static int
 891 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 892                                   uint16_t queue_id,
 893                                   uint8_t stat_idx,
 894                                   uint8_t is_rx)
 895 {
 896 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 897 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 898 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 899
 900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 901         struct ixgbe_stat_mapping_registers *stat_mappings =
 902                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 903         uint32_t qsmr_mask = 0;
 904         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 905         uint32_t q_map;
 906         uint8_t n, offset;
 907
 908         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 909                 (hw->mac.type != ixgbe_mac_X540) &&
 910                 (hw->mac.type != ixgbe_mac_X550) &&
 911                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 912                 (hw->mac.type != ixgbe_mac_X550EM_a))
 913                 return -ENOSYS;
 914
 915         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 916                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 917                      queue_id, stat_idx);
 918
 919         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 920         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 921                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 922                 return -EIO;
 923         }
 924         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 925
 926         /* Now clear any previous stat_idx set */
 927         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 928         if (!is_rx)
 929                 stat_mappings->tqsm[n] &= ~clearing_mask;
 930         else
 931                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 932
 933         q_map = (uint32_t)stat_idx;
 934         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 935         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 936         if (!is_rx)
 937                 stat_mappings->tqsm[n] |= qsmr_mask;
 938         else
 939                 stat_mappings->rqsmr[n] |= qsmr_mask;
 940
 941         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 942                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 943                      queue_id, stat_idx);
 944         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 945                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 946
 947         /* Now write the mapping in the appropriate register */
 948         if (is_rx) {
 949                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 950                              stat_mappings->rqsmr[n], n);
 951                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 952         } else {
 953                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 954                              stat_mappings->tqsm[n], n);
 955                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 956         }
 957         return 0;
 958 }
 959
 960 static void
 961 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 962 {
 963         struct ixgbe_stat_mapping_registers *stat_mappings =
 964                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 965         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         int i;
 967
 968         /* write whatever was in stat mapping table to the NIC */
 969         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 970                 /* rx */
 971                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 972
 973                 /* tx */
 974                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 975         }
 976 }
 977
 978 static void
 979 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 980 {
 981         uint8_t i;
 982         struct ixgbe_dcb_tc_config *tc;
 983         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 984
 985         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 986         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 987         for (i = 0; i < dcb_max_tc; i++) {
 988                 tc = &dcb_config->tc_config[i];
 989                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 990                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 991                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 992                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 993                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 994                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 995                 tc->pfc = ixgbe_dcb_pfc_disabled;
 996         }
 997
 998         /* Initialize default user to priority mapping, UPx->TC0 */
 999         tc = &dcb_config->tc_config[0];
1000         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1001         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1002         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1003                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1004                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1005         }
1006         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1007         dcb_config->pfc_mode_enable = false;
1008         dcb_config->vt_mode = true;
1009         dcb_config->round_robin_enable = false;
1010         /* support all DCB capabilities in 82599 */
1011         dcb_config->support.capabilities = 0xFF;
1012
1013         /*we only support 4 Tcs for X540, X550 */
1014         if (hw->mac.type == ixgbe_mac_X540 ||
1015                 hw->mac.type == ixgbe_mac_X550 ||
1016                 hw->mac.type == ixgbe_mac_X550EM_x ||
1017                 hw->mac.type == ixgbe_mac_X550EM_a) {
1018                 dcb_config->num_tcs.pg_tcs = 4;
1019                 dcb_config->num_tcs.pfc_tcs = 4;
1020         }
1021 }
1022
1023 /*
1024  * Ensure that all locks are released before first NVM or PHY access
1025  */
1026 static void
1027 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1028 {
1029         uint16_t mask;
1030
1031         /*
1032          * Phy lock should not fail in this early stage. If this is the case,
1033          * it is due to an improper exit of the application.
1034          * So force the release of the faulty lock. Release of common lock
1035          * is done automatically by swfw_sync function.
1036          */
1037         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1038         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1039                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1040         }
1041         ixgbe_release_swfw_semaphore(hw, mask);
1042
1043         /*
1044          * These ones are more tricky since they are common to all ports; but
1045          * swfw_sync retries last long enough (1s) to be almost sure that if
1046          * lock can not be taken it is due to an improper lock of the
1047          * semaphore.
1048          */
1049         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1050         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1051                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1052         }
1053         ixgbe_release_swfw_semaphore(hw, mask);
1054 }
1055
1056 /*
1057  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1058  * It returns 0 on success.
1059  */
1060 static int
1061 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1062 {
1063         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1064         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1065         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1066         struct ixgbe_hw *hw =
1067                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1068         struct ixgbe_vfta *shadow_vfta =
1069                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1070         struct ixgbe_hwstrip *hwstrip =
1071                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1072         struct ixgbe_dcb_config *dcb_config =
1073                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1074         struct ixgbe_filter_info *filter_info =
1075                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1076         struct ixgbe_bw_conf *bw_conf =
1077                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1078         uint32_t ctrl_ext;
1079         uint16_t csum;
1080         int diag, i, ret;
1081
1082         PMD_INIT_FUNC_TRACE();
1083
1084         ixgbe_dev_macsec_setting_reset(eth_dev);
1085
1086         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1087         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1088         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1089         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1090         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1091         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1092         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1093         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1094
1095         /*
1096          * For secondary processes, we don't initialise any further as primary
1097          * has already done this work. Only check we don't need a different
1098          * RX and TX function.
1099          */
1100         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1101                 struct ixgbe_tx_queue *txq;
1102                 /* TX queue function in primary, set by last queue initialized
1103                  * Tx queue may not initialized by primary process
1104                  */
1105                 if (eth_dev->data->tx_queues) {
1106                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1107                         ixgbe_set_tx_function(eth_dev, txq);
1108                 } else {
1109                         /* Use default TX function if we get here */
1110                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1111                                      "Using default TX function.");
1112                 }
1113
1114                 ixgbe_set_rx_function(eth_dev);
1115
1116                 return 0;
1117         }
1118
1119         rte_atomic32_clear(&ad->link_thread_running);
1120         rte_eth_copy_pci_info(eth_dev, pci_dev);
1121         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1122
1123         /* Vendor and Device ID need to be set before init of shared code */
1124         hw->device_id = pci_dev->id.device_id;
1125         hw->vendor_id = pci_dev->id.vendor_id;
1126         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1127         hw->allow_unsupported_sfp = 1;
1128
1129         /* Initialize the shared code (base driver) */
1130 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1131         diag = ixgbe_bypass_init_shared_code(hw);
1132 #else
1133         diag = ixgbe_init_shared_code(hw);
1134 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1135
1136         if (diag != IXGBE_SUCCESS) {
1137                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1138                 return -EIO;
1139         }
1140
1141         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1142                 PMD_INIT_LOG(ERR, "\nERROR: "
1143                         "Firmware recovery mode detected. Limiting functionality.\n"
1144                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1145                         "User Guide for details on firmware recovery mode.");
1146                 return -EIO;
1147         }
1148
1149         /* pick up the PCI bus settings for reporting later */
1150         ixgbe_get_bus_info(hw);
1151
1152         /* Unlock any pending hardware semaphore */
1153         ixgbe_swfw_lock_reset(hw);
1154
1155 #ifdef RTE_LIB_SECURITY
1156         /* Initialize security_ctx only for primary process*/
1157         if (ixgbe_ipsec_ctx_create(eth_dev))
1158                 return -ENOMEM;
1159 #endif
1160
1161         /* Initialize DCB configuration*/
1162         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1163         ixgbe_dcb_init(hw, dcb_config);
1164         /* Get Hardware Flow Control setting */
1165         hw->fc.requested_mode = ixgbe_fc_none;
1166         hw->fc.current_mode = ixgbe_fc_none;
1167         hw->fc.pause_time = IXGBE_FC_PAUSE;
1168         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1169                 hw->fc.low_water[i] = IXGBE_FC_LO;
1170                 hw->fc.high_water[i] = IXGBE_FC_HI;
1171         }
1172         hw->fc.send_xon = 1;
1173
1174         /* Make sure we have a good EEPROM before we read from it */
1175         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1176         if (diag != IXGBE_SUCCESS) {
1177                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1178                 return -EIO;
1179         }
1180
1181 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1182         diag = ixgbe_bypass_init_hw(hw);
1183 #else
1184         diag = ixgbe_init_hw(hw);
1185 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1186
1187         /*
1188          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1189          * is called too soon after the kernel driver unbinding/binding occurs.
1190          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1191          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1192          * also called. See ixgbe_identify_phy_82599(). The reason for the
1193          * failure is not known, and only occuts when virtualisation features
1194          * are disabled in the bios. A delay of 100ms  was found to be enough by
1195          * trial-and-error, and is doubled to be safe.
1196          */
1197         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1198                 rte_delay_ms(200);
1199                 diag = ixgbe_init_hw(hw);
1200         }
1201
1202         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1203                 diag = IXGBE_SUCCESS;
1204
1205         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1206                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1207                              "LOM.  Please be aware there may be issues associated "
1208                              "with your hardware.");
1209                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1210                              "please contact your Intel or hardware representative "
1211                              "who provided you with this hardware.");
1212         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1213                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1214         if (diag) {
1215                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1216                 return -EIO;
1217         }
1218
1219         /* Reset the hw statistics */
1220         ixgbe_dev_stats_reset(eth_dev);
1221
1222         /* disable interrupt */
1223         ixgbe_disable_intr(hw);
1224
1225         /* reset mappings for queue statistics hw counters*/
1226         ixgbe_reset_qstat_mappings(hw);
1227
1228         /* Allocate memory for storing MAC addresses */
1229         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1230                                                hw->mac.num_rar_entries, 0);
1231         if (eth_dev->data->mac_addrs == NULL) {
1232                 PMD_INIT_LOG(ERR,
1233                              "Failed to allocate %u bytes needed to store "
1234                              "MAC addresses",
1235                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1236                 return -ENOMEM;
1237         }
1238         /* Copy the permanent MAC address */
1239         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1240                         &eth_dev->data->mac_addrs[0]);
1241
1242         /* Allocate memory for storing hash filter MAC addresses */
1243         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1244                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1245         if (eth_dev->data->hash_mac_addrs == NULL) {
1246                 PMD_INIT_LOG(ERR,
1247                              "Failed to allocate %d bytes needed to store MAC addresses",
1248                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1249                 return -ENOMEM;
1250         }
1251
1252         /* initialize the vfta */
1253         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1254
1255         /* initialize the hw strip bitmap*/
1256         memset(hwstrip, 0, sizeof(*hwstrip));
1257
1258         /* initialize PF if max_vfs not zero */
1259         ret = ixgbe_pf_host_init(eth_dev);
1260         if (ret) {
1261                 rte_free(eth_dev->data->mac_addrs);
1262                 eth_dev->data->mac_addrs = NULL;
1263                 rte_free(eth_dev->data->hash_mac_addrs);
1264                 eth_dev->data->hash_mac_addrs = NULL;
1265                 return ret;
1266         }
1267
1268         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1269         /* let hardware know driver is loaded */
1270         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1271         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1272         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1273         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1274         IXGBE_WRITE_FLUSH(hw);
1275
1276         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1277                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1278                              (int) hw->mac.type, (int) hw->phy.type,
1279                              (int) hw->phy.sfp_type);
1280         else
1281                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1282                              (int) hw->mac.type, (int) hw->phy.type);
1283
1284         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1285                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1286                      pci_dev->id.device_id);
1287
1288         rte_intr_callback_register(intr_handle,
1289                                    ixgbe_dev_interrupt_handler, eth_dev);
1290
1291         /* enable uio/vfio intr/eventfd mapping */
1292         rte_intr_enable(intr_handle);
1293
1294         /* enable support intr */
1295         ixgbe_enable_intr(eth_dev);
1296
1297         /* initialize filter info */
1298         memset(filter_info, 0,
1299                sizeof(struct ixgbe_filter_info));
1300
1301         /* initialize 5tuple filter list */
1302         TAILQ_INIT(&filter_info->fivetuple_list);
1303
1304         /* initialize flow director filter list & hash */
1305         ixgbe_fdir_filter_init(eth_dev);
1306
1307         /* initialize l2 tunnel filter list & hash */
1308         ixgbe_l2_tn_filter_init(eth_dev);
1309
1310         /* initialize flow filter lists */
1311         ixgbe_filterlist_init();
1312
1313         /* initialize bandwidth configuration info */
1314         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1315
1316         /* initialize Traffic Manager configuration */
1317         ixgbe_tm_conf_init(eth_dev);
1318
1319         return 0;
1320 }
1321
1322 static int
1323 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1324 {
1325         PMD_INIT_FUNC_TRACE();
1326
1327         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1328                 return 0;
1329
1330         ixgbe_dev_close(eth_dev);
1331
1332         return 0;
1333 }
1334
1335 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1336 {
1337         struct ixgbe_filter_info *filter_info =
1338                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1339         struct ixgbe_5tuple_filter *p_5tuple;
1340
1341         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1342                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1343                              p_5tuple,
1344                              entries);
1345                 rte_free(p_5tuple);
1346         }
1347         memset(filter_info->fivetuple_mask, 0,
1348                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1349
1350         return 0;
1351 }
1352
1353 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1354 {
1355         struct ixgbe_hw_fdir_info *fdir_info =
1356                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1357         struct ixgbe_fdir_filter *fdir_filter;
1358
1359                 if (fdir_info->hash_map)
1360                 rte_free(fdir_info->hash_map);
1361         if (fdir_info->hash_handle)
1362                 rte_hash_free(fdir_info->hash_handle);
1363
1364         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1365                 TAILQ_REMOVE(&fdir_info->fdir_list,
1366                              fdir_filter,
1367                              entries);
1368                 rte_free(fdir_filter);
1369         }
1370
1371         return 0;
1372 }
1373
1374 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1375 {
1376         struct ixgbe_l2_tn_info *l2_tn_info =
1377                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1378         struct ixgbe_l2_tn_filter *l2_tn_filter;
1379
1380         if (l2_tn_info->hash_map)
1381                 rte_free(l2_tn_info->hash_map);
1382         if (l2_tn_info->hash_handle)
1383                 rte_hash_free(l2_tn_info->hash_handle);
1384
1385         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1386                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1387                              l2_tn_filter,
1388                              entries);
1389                 rte_free(l2_tn_filter);
1390         }
1391
1392         return 0;
1393 }
1394
1395 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1396 {
1397         struct ixgbe_hw_fdir_info *fdir_info =
1398                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1399         char fdir_hash_name[RTE_HASH_NAMESIZE];
1400         struct rte_hash_parameters fdir_hash_params = {
1401                 .name = fdir_hash_name,
1402                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1403                 .key_len = sizeof(union ixgbe_atr_input),
1404                 .hash_func = rte_hash_crc,
1405                 .hash_func_init_val = 0,
1406                 .socket_id = rte_socket_id(),
1407         };
1408
1409         TAILQ_INIT(&fdir_info->fdir_list);
1410         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1411                  "fdir_%s", eth_dev->device->name);
1412         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1413         if (!fdir_info->hash_handle) {
1414                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1415                 return -EINVAL;
1416         }
1417         fdir_info->hash_map = rte_zmalloc("ixgbe",
1418                                           sizeof(struct ixgbe_fdir_filter *) *
1419                                           IXGBE_MAX_FDIR_FILTER_NUM,
1420                                           0);
1421         if (!fdir_info->hash_map) {
1422                 PMD_INIT_LOG(ERR,
1423                              "Failed to allocate memory for fdir hash map!");
1424                 return -ENOMEM;
1425         }
1426         fdir_info->mask_added = FALSE;
1427
1428         return 0;
1429 }
1430
1431 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1432 {
1433         struct ixgbe_l2_tn_info *l2_tn_info =
1434                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1435         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1436         struct rte_hash_parameters l2_tn_hash_params = {
1437                 .name = l2_tn_hash_name,
1438                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1439                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1440                 .hash_func = rte_hash_crc,
1441                 .hash_func_init_val = 0,
1442                 .socket_id = rte_socket_id(),
1443         };
1444
1445         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1446         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1447                  "l2_tn_%s", eth_dev->device->name);
1448         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1449         if (!l2_tn_info->hash_handle) {
1450                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1451                 return -EINVAL;
1452         }
1453         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1454                                    sizeof(struct ixgbe_l2_tn_filter *) *
1455                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1456                                    0);
1457         if (!l2_tn_info->hash_map) {
1458                 PMD_INIT_LOG(ERR,
1459                         "Failed to allocate memory for L2 TN hash map!");
1460                 return -ENOMEM;
1461         }
1462         l2_tn_info->e_tag_en = FALSE;
1463         l2_tn_info->e_tag_fwd_en = FALSE;
1464         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1465
1466         return 0;
1467 }
1468 /*
1469  * Negotiate mailbox API version with the PF.
1470  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1471  * Then we try to negotiate starting with the most recent one.
1472  * If all negotiation attempts fail, then we will proceed with
1473  * the default one (ixgbe_mbox_api_10).
1474  */
1475 static void
1476 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1477 {
1478         int32_t i;
1479
1480         /* start with highest supported, proceed down */
1481         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1482                 ixgbe_mbox_api_13,
1483                 ixgbe_mbox_api_12,
1484                 ixgbe_mbox_api_11,
1485                 ixgbe_mbox_api_10,
1486         };
1487
1488         for (i = 0;
1489                         i != RTE_DIM(sup_ver) &&
1490                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1491                         i++)
1492                 ;
1493 }
1494
1495 static void
1496 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1497 {
1498         uint64_t random;
1499
1500         /* Set Organizationally Unique Identifier (OUI) prefix. */
1501         mac_addr->addr_bytes[0] = 0x00;
1502         mac_addr->addr_bytes[1] = 0x09;
1503         mac_addr->addr_bytes[2] = 0xC0;
1504         /* Force indication of locally assigned MAC address. */
1505         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1506         /* Generate the last 3 bytes of the MAC address with a random number. */
1507         random = rte_rand();
1508         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1509 }
1510
1511 static int
1512 devarg_handle_int(__rte_unused const char *key, const char *value,
1513                   void *extra_args)
1514 {
1515         uint16_t *n = extra_args;
1516
1517         if (value == NULL || extra_args == NULL)
1518                 return -EINVAL;
1519
1520         *n = (uint16_t)strtoul(value, NULL, 0);
1521         if (*n == USHRT_MAX && errno == ERANGE)
1522                 return -1;
1523
1524         return 0;
1525 }
1526
1527 static void
1528 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1529                       struct rte_devargs *devargs)
1530 {
1531         struct rte_kvargs *kvlist;
1532         uint16_t pflink_fullchk;
1533
1534         if (devargs == NULL)
1535                 return;
1536
1537         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1538         if (kvlist == NULL)
1539                 return;
1540
1541         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1542             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1543                                devarg_handle_int, &pflink_fullchk) == 0 &&
1544             pflink_fullchk == 1)
1545                 adapter->pflink_fullchk = 1;
1546
1547         rte_kvargs_free(kvlist);
1548 }
1549
1550 /*
1551  * Virtual Function device init
1552  */
1553 static int
1554 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1555 {
1556         int diag;
1557         uint32_t tc, tcs;
1558         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1559         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1560         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1561         struct ixgbe_hw *hw =
1562                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1563         struct ixgbe_vfta *shadow_vfta =
1564                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1565         struct ixgbe_hwstrip *hwstrip =
1566                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1567         struct rte_ether_addr *perm_addr =
1568                 (struct rte_ether_addr *)hw->mac.perm_addr;
1569
1570         PMD_INIT_FUNC_TRACE();
1571
1572         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1573         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1574         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1575         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1576         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1577         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1578
1579         /* for secondary processes, we don't initialise any further as primary
1580          * has already done this work. Only check we don't need a different
1581          * RX function
1582          */
1583         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1584                 struct ixgbe_tx_queue *txq;
1585                 /* TX queue function in primary, set by last queue initialized
1586                  * Tx queue may not initialized by primary process
1587                  */
1588                 if (eth_dev->data->tx_queues) {
1589                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1590                         ixgbe_set_tx_function(eth_dev, txq);
1591                 } else {
1592                         /* Use default TX function if we get here */
1593                         PMD_INIT_LOG(NOTICE,
1594                                      "No TX queues configured yet. Using default TX function.");
1595                 }
1596
1597                 ixgbe_set_rx_function(eth_dev);
1598
1599                 return 0;
1600         }
1601
1602         rte_atomic32_clear(&ad->link_thread_running);
1603         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1604                               pci_dev->device.devargs);
1605
1606         rte_eth_copy_pci_info(eth_dev, pci_dev);
1607         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1608
1609         hw->device_id = pci_dev->id.device_id;
1610         hw->vendor_id = pci_dev->id.vendor_id;
1611         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1612
1613         /* initialize the vfta */
1614         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1615
1616         /* initialize the hw strip bitmap*/
1617         memset(hwstrip, 0, sizeof(*hwstrip));
1618
1619         /* Initialize the shared code (base driver) */
1620         diag = ixgbe_init_shared_code(hw);
1621         if (diag != IXGBE_SUCCESS) {
1622                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1623                 return -EIO;
1624         }
1625
1626         /* init_mailbox_params */
1627         hw->mbx.ops.init_params(hw);
1628
1629         /* Reset the hw statistics */
1630         ixgbevf_dev_stats_reset(eth_dev);
1631
1632         /* Disable the interrupts for VF */
1633         ixgbevf_intr_disable(eth_dev);
1634
1635         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1636         diag = hw->mac.ops.reset_hw(hw);
1637
1638         /*
1639          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1640          * the underlying PF driver has not assigned a MAC address to the VF.
1641          * In this case, assign a random MAC address.
1642          */
1643         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1644                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1645                 /*
1646                  * This error code will be propagated to the app by
1647                  * rte_eth_dev_reset, so use a public error code rather than
1648                  * the internal-only IXGBE_ERR_RESET_FAILED
1649                  */
1650                 return -EAGAIN;
1651         }
1652
1653         /* negotiate mailbox API version to use with the PF. */
1654         ixgbevf_negotiate_api(hw);
1655
1656         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1657         ixgbevf_get_queues(hw, &tcs, &tc);
1658
1659         /* Allocate memory for storing MAC addresses */
1660         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1661                                                hw->mac.num_rar_entries, 0);
1662         if (eth_dev->data->mac_addrs == NULL) {
1663                 PMD_INIT_LOG(ERR,
1664                              "Failed to allocate %u bytes needed to store "
1665                              "MAC addresses",
1666                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1667                 return -ENOMEM;
1668         }
1669
1670         /* Generate a random MAC address, if none was assigned by PF. */
1671         if (rte_is_zero_ether_addr(perm_addr)) {
1672                 generate_random_mac_addr(perm_addr);
1673                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1674                 if (diag) {
1675                         rte_free(eth_dev->data->mac_addrs);
1676                         eth_dev->data->mac_addrs = NULL;
1677                         return diag;
1678                 }
1679                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1680                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1681                              "%02x:%02x:%02x:%02x:%02x:%02x",
1682                              perm_addr->addr_bytes[0],
1683                              perm_addr->addr_bytes[1],
1684                              perm_addr->addr_bytes[2],
1685                              perm_addr->addr_bytes[3],
1686                              perm_addr->addr_bytes[4],
1687                              perm_addr->addr_bytes[5]);
1688         }
1689
1690         /* Copy the permanent MAC address */
1691         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1692
1693         /* reset the hardware with the new settings */
1694         diag = hw->mac.ops.start_hw(hw);
1695         switch (diag) {
1696         case  0:
1697                 break;
1698
1699         default:
1700                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1701                 return -EIO;
1702         }
1703
1704         rte_intr_callback_register(intr_handle,
1705                                    ixgbevf_dev_interrupt_handler, eth_dev);
1706         rte_intr_enable(intr_handle);
1707         ixgbevf_intr_enable(eth_dev);
1708
1709         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1710                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1711                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1712
1713         return 0;
1714 }
1715
1716 /* Virtual Function device uninit */
1717
1718 static int
1719 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1720 {
1721         PMD_INIT_FUNC_TRACE();
1722
1723         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1724                 return 0;
1725
1726         ixgbevf_dev_close(eth_dev);
1727
1728         return 0;
1729 }
1730
1731 static int
1732 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1733                 struct rte_pci_device *pci_dev)
1734 {
1735         char name[RTE_ETH_NAME_MAX_LEN];
1736         struct rte_eth_dev *pf_ethdev;
1737         struct rte_eth_devargs eth_da;
1738         int i, retval;
1739
1740         if (pci_dev->device.devargs) {
1741                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1742                                 &eth_da);
1743                 if (retval)
1744                         return retval;
1745         } else
1746                 memset(&eth_da, 0, sizeof(eth_da));
1747
1748         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1749                 sizeof(struct ixgbe_adapter),
1750                 eth_dev_pci_specific_init, pci_dev,
1751                 eth_ixgbe_dev_init, NULL);
1752
1753         if (retval || eth_da.nb_representor_ports < 1)
1754                 return retval;
1755
1756         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1757         if (pf_ethdev == NULL)
1758                 return -ENODEV;
1759
1760         /* probe VF representor ports */
1761         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1762                 struct ixgbe_vf_info *vfinfo;
1763                 struct ixgbe_vf_representor representor;
1764
1765                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1766                         pf_ethdev->data->dev_private);
1767                 if (vfinfo == NULL) {
1768                         PMD_DRV_LOG(ERR,
1769                                 "no virtual functions supported by PF");
1770                         break;
1771                 }
1772
1773                 representor.vf_id = eth_da.representor_ports[i];
1774                 representor.switch_domain_id = vfinfo->switch_domain_id;
1775                 representor.pf_ethdev = pf_ethdev;
1776
1777                 /* representor port net_bdf_port */
1778                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1779                         pci_dev->device.name,
1780                         eth_da.representor_ports[i]);
1781
1782                 retval = rte_eth_dev_create(&pci_dev->device, name,
1783                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1784                         ixgbe_vf_representor_init, &representor);
1785
1786                 if (retval)
1787                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1788                                 "representor %s.", name);
1789         }
1790
1791         return 0;
1792 }
1793
1794 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1795 {
1796         struct rte_eth_dev *ethdev;
1797
1798         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1799         if (!ethdev)
1800                 return 0;
1801
1802         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1803                 return rte_eth_dev_pci_generic_remove(pci_dev,
1804                                         ixgbe_vf_representor_uninit);
1805         else
1806                 return rte_eth_dev_pci_generic_remove(pci_dev,
1807                                                 eth_ixgbe_dev_uninit);
1808 }
1809
1810 static struct rte_pci_driver rte_ixgbe_pmd = {
1811         .id_table = pci_id_ixgbe_map,
1812         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1813         .probe = eth_ixgbe_pci_probe,
1814         .remove = eth_ixgbe_pci_remove,
1815 };
1816
1817 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1818         struct rte_pci_device *pci_dev)
1819 {
1820         return rte_eth_dev_pci_generic_probe(pci_dev,
1821                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1822 }
1823
1824 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1825 {
1826         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1827 }
1828
1829 /*
1830  * virtual function driver struct
1831  */
1832 static struct rte_pci_driver rte_ixgbevf_pmd = {
1833         .id_table = pci_id_ixgbevf_map,
1834         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1835         .probe = eth_ixgbevf_pci_probe,
1836         .remove = eth_ixgbevf_pci_remove,
1837 };
1838
1839 static int
1840 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1841 {
1842         struct ixgbe_hw *hw =
1843                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1844         struct ixgbe_vfta *shadow_vfta =
1845                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1846         uint32_t vfta;
1847         uint32_t vid_idx;
1848         uint32_t vid_bit;
1849
1850         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1851         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1852         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1853         if (on)
1854                 vfta |= vid_bit;
1855         else
1856                 vfta &= ~vid_bit;
1857         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1858
1859         /* update local VFTA copy */
1860         shadow_vfta->vfta[vid_idx] = vfta;
1861
1862         return 0;
1863 }
1864
1865 static void
1866 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1867 {
1868         if (on)
1869                 ixgbe_vlan_hw_strip_enable(dev, queue);
1870         else
1871                 ixgbe_vlan_hw_strip_disable(dev, queue);
1872 }
1873
1874 static int
1875 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1876                     enum rte_vlan_type vlan_type,
1877                     uint16_t tpid)
1878 {
1879         struct ixgbe_hw *hw =
1880                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1881         int ret = 0;
1882         uint32_t reg;
1883         uint32_t qinq;
1884
1885         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886         qinq &= IXGBE_DMATXCTL_GDV;
1887
1888         switch (vlan_type) {
1889         case ETH_VLAN_TYPE_INNER:
1890                 if (qinq) {
1891                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1892                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1893                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1894                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1895                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1896                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1897                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1898                 } else {
1899                         ret = -ENOTSUP;
1900                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1901                                     " by single VLAN");
1902                 }
1903                 break;
1904         case ETH_VLAN_TYPE_OUTER:
1905                 if (qinq) {
1906                         /* Only the high 16-bits is valid */
1907                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1908                                         IXGBE_EXVET_VET_EXT_SHIFT);
1909                 } else {
1910                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1911                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1912                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1913                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1914                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1915                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1916                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1917                 }
1918
1919                 break;
1920         default:
1921                 ret = -EINVAL;
1922                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1923                 break;
1924         }
1925
1926         return ret;
1927 }
1928
1929 void
1930 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1931 {
1932         struct ixgbe_hw *hw =
1933                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934         uint32_t vlnctrl;
1935
1936         PMD_INIT_FUNC_TRACE();
1937
1938         /* Filter Table Disable */
1939         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1940         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1941
1942         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1943 }
1944
1945 void
1946 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1947 {
1948         struct ixgbe_hw *hw =
1949                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950         struct ixgbe_vfta *shadow_vfta =
1951                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1952         uint32_t vlnctrl;
1953         uint16_t i;
1954
1955         PMD_INIT_FUNC_TRACE();
1956
1957         /* Filter Table Enable */
1958         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1959         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1960         vlnctrl |= IXGBE_VLNCTRL_VFE;
1961
1962         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1963
1964         /* write whatever is in local vfta copy */
1965         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1966                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1967 }
1968
1969 static void
1970 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1971 {
1972         struct ixgbe_hwstrip *hwstrip =
1973                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1974         struct ixgbe_rx_queue *rxq;
1975
1976         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1977                 return;
1978
1979         if (on)
1980                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1981         else
1982                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1983
1984         if (queue >= dev->data->nb_rx_queues)
1985                 return;
1986
1987         rxq = dev->data->rx_queues[queue];
1988
1989         if (on) {
1990                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1991                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1992         } else {
1993                 rxq->vlan_flags = PKT_RX_VLAN;
1994                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1995         }
1996 }
1997
1998 static void
1999 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2000 {
2001         struct ixgbe_hw *hw =
2002                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2003         uint32_t ctrl;
2004
2005         PMD_INIT_FUNC_TRACE();
2006
2007         if (hw->mac.type == ixgbe_mac_82598EB) {
2008                 /* No queue level support */
2009                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2010                 return;
2011         }
2012
2013         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2014         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2015         ctrl &= ~IXGBE_RXDCTL_VME;
2016         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2017
2018         /* record those setting for HW strip per queue */
2019         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2020 }
2021
2022 static void
2023 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2024 {
2025         struct ixgbe_hw *hw =
2026                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2027         uint32_t ctrl;
2028
2029         PMD_INIT_FUNC_TRACE();
2030
2031         if (hw->mac.type == ixgbe_mac_82598EB) {
2032                 /* No queue level supported */
2033                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2034                 return;
2035         }
2036
2037         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2038         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2039         ctrl |= IXGBE_RXDCTL_VME;
2040         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2041
2042         /* record those setting for HW strip per queue */
2043         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2044 }
2045
2046 static void
2047 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2048 {
2049         struct ixgbe_hw *hw =
2050                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051         uint32_t ctrl;
2052
2053         PMD_INIT_FUNC_TRACE();
2054
2055         /* DMATXCTRL: Geric Double VLAN Disable */
2056         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2057         ctrl &= ~IXGBE_DMATXCTL_GDV;
2058         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2059
2060         /* CTRL_EXT: Global Double VLAN Disable */
2061         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2062         ctrl &= ~IXGBE_EXTENDED_VLAN;
2063         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2064
2065 }
2066
2067 static void
2068 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2069 {
2070         struct ixgbe_hw *hw =
2071                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2072         uint32_t ctrl;
2073
2074         PMD_INIT_FUNC_TRACE();
2075
2076         /* DMATXCTRL: Geric Double VLAN Enable */
2077         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2078         ctrl |= IXGBE_DMATXCTL_GDV;
2079         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2080
2081         /* CTRL_EXT: Global Double VLAN Enable */
2082         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2083         ctrl |= IXGBE_EXTENDED_VLAN;
2084         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2085
2086         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2087         if (hw->mac.type == ixgbe_mac_X550 ||
2088             hw->mac.type == ixgbe_mac_X550EM_x ||
2089             hw->mac.type == ixgbe_mac_X550EM_a) {
2090                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2091                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2092                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2093         }
2094
2095         /*
2096          * VET EXT field in the EXVET register = 0x8100 by default
2097          * So no need to change. Same to VT field of DMATXCTL register
2098          */
2099 }
2100
2101 void
2102 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2103 {
2104         struct ixgbe_hw *hw =
2105                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2107         uint32_t ctrl;
2108         uint16_t i;
2109         struct ixgbe_rx_queue *rxq;
2110         bool on;
2111
2112         PMD_INIT_FUNC_TRACE();
2113
2114         if (hw->mac.type == ixgbe_mac_82598EB) {
2115                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2116                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2117                         ctrl |= IXGBE_VLNCTRL_VME;
2118                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2119                 } else {
2120                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2121                         ctrl &= ~IXGBE_VLNCTRL_VME;
2122                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2123                 }
2124         } else {
2125                 /*
2126                  * Other 10G NIC, the VLAN strip can be setup
2127                  * per queue in RXDCTL
2128                  */
2129                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2130                         rxq = dev->data->rx_queues[i];
2131                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2132                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2133                                 ctrl |= IXGBE_RXDCTL_VME;
2134                                 on = TRUE;
2135                         } else {
2136                                 ctrl &= ~IXGBE_RXDCTL_VME;
2137                                 on = FALSE;
2138                         }
2139                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2140
2141                         /* record those setting for HW strip per queue */
2142                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2143                 }
2144         }
2145 }
2146
2147 static void
2148 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2149 {
2150         uint16_t i;
2151         struct rte_eth_rxmode *rxmode;
2152         struct ixgbe_rx_queue *rxq;
2153
2154         if (mask & ETH_VLAN_STRIP_MASK) {
2155                 rxmode = &dev->data->dev_conf.rxmode;
2156                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2157                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2158                                 rxq = dev->data->rx_queues[i];
2159                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2160                         }
2161                 else
2162                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2163                                 rxq = dev->data->rx_queues[i];
2164                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2165                         }
2166         }
2167 }
2168
2169 static int
2170 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2171 {
2172         struct rte_eth_rxmode *rxmode;
2173         rxmode = &dev->data->dev_conf.rxmode;
2174
2175         if (mask & ETH_VLAN_STRIP_MASK) {
2176                 ixgbe_vlan_hw_strip_config(dev);
2177         }
2178
2179         if (mask & ETH_VLAN_FILTER_MASK) {
2180                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2181                         ixgbe_vlan_hw_filter_enable(dev);
2182                 else
2183                         ixgbe_vlan_hw_filter_disable(dev);
2184         }
2185
2186         if (mask & ETH_VLAN_EXTEND_MASK) {
2187                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2188                         ixgbe_vlan_hw_extend_enable(dev);
2189                 else
2190                         ixgbe_vlan_hw_extend_disable(dev);
2191         }
2192
2193         return 0;
2194 }
2195
2196 static int
2197 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2198 {
2199         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2200
2201         ixgbe_vlan_offload_config(dev, mask);
2202
2203         return 0;
2204 }
2205
2206 static void
2207 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2208 {
2209         struct ixgbe_hw *hw =
2210                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2211         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2212         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2213
2214         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2215         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2216 }
2217
2218 static int
2219 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2220 {
2221         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2222
2223         switch (nb_rx_q) {
2224         case 1:
2225         case 2:
2226                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2227                 break;
2228         case 4:
2229                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2230                 break;
2231         default:
2232                 return -EINVAL;
2233         }
2234
2235         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2236                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2237         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2238                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2239         return 0;
2240 }
2241
2242 static int
2243 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2244 {
2245         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2246         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2248         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2249
2250         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2251                 /* check multi-queue mode */
2252                 switch (dev_conf->rxmode.mq_mode) {
2253                 case ETH_MQ_RX_VMDQ_DCB:
2254                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2255                         break;
2256                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2257                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2258                         PMD_INIT_LOG(ERR, "SRIOV active,"
2259                                         " unsupported mq_mode rx %d.",
2260                                         dev_conf->rxmode.mq_mode);
2261                         return -EINVAL;
2262                 case ETH_MQ_RX_RSS:
2263                 case ETH_MQ_RX_VMDQ_RSS:
2264                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2265                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2266                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2267                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2268                                                 " invalid queue number"
2269                                                 " for VMDQ RSS, allowed"
2270                                                 " value are 1, 2 or 4.");
2271                                         return -EINVAL;
2272                                 }
2273                         break;
2274                 case ETH_MQ_RX_VMDQ_ONLY:
2275                 case ETH_MQ_RX_NONE:
2276                         /* if nothing mq mode configure, use default scheme */
2277                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2278                         break;
2279                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2280                         /* SRIOV only works in VMDq enable mode */
2281                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2282                                         " wrong mq_mode rx %d.",
2283                                         dev_conf->rxmode.mq_mode);
2284                         return -EINVAL;
2285                 }
2286
2287                 switch (dev_conf->txmode.mq_mode) {
2288                 case ETH_MQ_TX_VMDQ_DCB:
2289                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2290                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2291                         break;
2292                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2293                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2294                         break;
2295                 }
2296
2297                 /* check valid queue number */
2298                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2299                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2300                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2301                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2302                                         " must be less than or equal to %d.",
2303                                         nb_rx_q, nb_tx_q,
2304                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2305                         return -EINVAL;
2306                 }
2307         } else {
2308                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2309                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2310                                           " not supported.");
2311                         return -EINVAL;
2312                 }
2313                 /* check configuration for vmdb+dcb mode */
2314                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2315                         const struct rte_eth_vmdq_dcb_conf *conf;
2316
2317                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2318                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2319                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2320                                 return -EINVAL;
2321                         }
2322                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2323                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2324                                conf->nb_queue_pools == ETH_32_POOLS)) {
2325                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2326                                                 " nb_queue_pools must be %d or %d.",
2327                                                 ETH_16_POOLS, ETH_32_POOLS);
2328                                 return -EINVAL;
2329                         }
2330                 }
2331                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2332                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2333
2334                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2335                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2336                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2337                                 return -EINVAL;
2338                         }
2339                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2340                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2341                                conf->nb_queue_pools == ETH_32_POOLS)) {
2342                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2343                                                 " nb_queue_pools != %d and"
2344                                                 " nb_queue_pools != %d.",
2345                                                 ETH_16_POOLS, ETH_32_POOLS);
2346                                 return -EINVAL;
2347                         }
2348                 }
2349
2350                 /* For DCB mode check our configuration before we go further */
2351                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2352                         const struct rte_eth_dcb_rx_conf *conf;
2353
2354                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2355                         if (!(conf->nb_tcs == ETH_4_TCS ||
2356                                conf->nb_tcs == ETH_8_TCS)) {
2357                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2358                                                 " and nb_tcs != %d.",
2359                                                 ETH_4_TCS, ETH_8_TCS);
2360                                 return -EINVAL;
2361                         }
2362                 }
2363
2364                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2365                         const struct rte_eth_dcb_tx_conf *conf;
2366
2367                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2368                         if (!(conf->nb_tcs == ETH_4_TCS ||
2369                                conf->nb_tcs == ETH_8_TCS)) {
2370                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2371                                                 " and nb_tcs != %d.",
2372                                                 ETH_4_TCS, ETH_8_TCS);
2373                                 return -EINVAL;
2374                         }
2375                 }
2376
2377                 /*
2378                  * When DCB/VT is off, maximum number of queues changes,
2379                  * except for 82598EB, which remains constant.
2380                  */
2381                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2382                                 hw->mac.type != ixgbe_mac_82598EB) {
2383                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2384                                 PMD_INIT_LOG(ERR,
2385                                              "Neither VT nor DCB are enabled, "
2386                                              "nb_tx_q > %d.",
2387                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2388                                 return -EINVAL;
2389                         }
2390                 }
2391         }
2392         return 0;
2393 }
2394
2395 static int
2396 ixgbe_dev_configure(struct rte_eth_dev *dev)
2397 {
2398         struct ixgbe_interrupt *intr =
2399                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2400         struct ixgbe_adapter *adapter = dev->data->dev_private;
2401         int ret;
2402
2403         PMD_INIT_FUNC_TRACE();
2404
2405         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2406                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2407
2408         /* multipe queue mode checking */
2409         ret  = ixgbe_check_mq_mode(dev);
2410         if (ret != 0) {
2411                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2412                             ret);
2413                 return ret;
2414         }
2415
2416         /* set flag to update link status after init */
2417         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2418
2419         /*
2420          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2421          * allocation or vector Rx preconditions we will reset it.
2422          */
2423         adapter->rx_bulk_alloc_allowed = true;
2424         adapter->rx_vec_allowed = true;
2425
2426         return 0;
2427 }
2428
2429 static void
2430 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2431 {
2432         struct ixgbe_hw *hw =
2433                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2434         struct ixgbe_interrupt *intr =
2435                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2436         uint32_t gpie;
2437
2438         /* only set up it on X550EM_X */
2439         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2440                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2441                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2442                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2443                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2444                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2445         }
2446 }
2447
2448 int
2449 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2450                         uint16_t tx_rate, uint64_t q_msk)
2451 {
2452         struct ixgbe_hw *hw;
2453         struct ixgbe_vf_info *vfinfo;
2454         struct rte_eth_link link;
2455         uint8_t  nb_q_per_pool;
2456         uint32_t queue_stride;
2457         uint32_t queue_idx, idx = 0, vf_idx;
2458         uint32_t queue_end;
2459         uint16_t total_rate = 0;
2460         struct rte_pci_device *pci_dev;
2461         int ret;
2462
2463         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2464         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2465         if (ret < 0)
2466                 return ret;
2467
2468         if (vf >= pci_dev->max_vfs)
2469                 return -EINVAL;
2470
2471         if (tx_rate > link.link_speed)
2472                 return -EINVAL;
2473
2474         if (q_msk == 0)
2475                 return 0;
2476
2477         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2478         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2479         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2480         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2481         queue_idx = vf * queue_stride;
2482         queue_end = queue_idx + nb_q_per_pool - 1;
2483         if (queue_end >= hw->mac.max_tx_queues)
2484                 return -EINVAL;
2485
2486         if (vfinfo) {
2487                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2488                         if (vf_idx == vf)
2489                                 continue;
2490                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2491                                 idx++)
2492                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2493                 }
2494         } else {
2495                 return -EINVAL;
2496         }
2497
2498         /* Store tx_rate for this vf. */
2499         for (idx = 0; idx < nb_q_per_pool; idx++) {
2500                 if (((uint64_t)0x1 << idx) & q_msk) {
2501                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2502                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2503                         total_rate += tx_rate;
2504                 }
2505         }
2506
2507         if (total_rate > dev->data->dev_link.link_speed) {
2508                 /* Reset stored TX rate of the VF if it causes exceed
2509                  * link speed.
2510                  */
2511                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2512                 return -EINVAL;
2513         }
2514
2515         /* Set RTTBCNRC of each queue/pool for vf X  */
2516         for (; queue_idx <= queue_end; queue_idx++) {
2517                 if (0x1 & q_msk)
2518                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2519                 q_msk = q_msk >> 1;
2520         }
2521
2522         return 0;
2523 }
2524
2525 static int
2526 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2527 {
2528         struct ixgbe_adapter *adapter = dev->data->dev_private;
2529         int err;
2530         uint32_t mflcn;
2531
2532         ixgbe_setup_fc(hw);
2533
2534         err = ixgbe_fc_enable(hw);
2535
2536         /* Not negotiated is not an error case */
2537         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2538                 /*
2539                  *check if we want to forward MAC frames - driver doesn't
2540                  *have native capability to do that,
2541                  *so we'll write the registers ourselves
2542                  */
2543
2544                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2545
2546                 /* set or clear MFLCN.PMCF bit depending on configuration */
2547                 if (adapter->mac_ctrl_frame_fwd != 0)
2548                         mflcn |= IXGBE_MFLCN_PMCF;
2549                 else
2550                         mflcn &= ~IXGBE_MFLCN_PMCF;
2551
2552                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2553                 IXGBE_WRITE_FLUSH(hw);
2554
2555                 return 0;
2556         }
2557         return err;
2558 }
2559
2560 /*
2561  * Configure device link speed and setup link.
2562  * It returns 0 on success.
2563  */
2564 static int
2565 ixgbe_dev_start(struct rte_eth_dev *dev)
2566 {
2567         struct ixgbe_hw *hw =
2568                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569         struct ixgbe_vf_info *vfinfo =
2570                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2571         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2572         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2573         uint32_t intr_vector = 0;
2574         int err;
2575         bool link_up = false, negotiate = 0;
2576         uint32_t speed = 0;
2577         uint32_t allowed_speeds = 0;
2578         int mask = 0;
2579         int status;
2580         uint16_t vf, idx;
2581         uint32_t *link_speeds;
2582         struct ixgbe_tm_conf *tm_conf =
2583                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2584         struct ixgbe_macsec_setting *macsec_setting =
2585                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2586
2587         PMD_INIT_FUNC_TRACE();
2588
2589         /* Stop the link setup handler before resetting the HW. */
2590         ixgbe_dev_wait_setup_link_complete(dev, 0);
2591
2592         /* disable uio/vfio intr/eventfd mapping */
2593         rte_intr_disable(intr_handle);
2594
2595         /* stop adapter */
2596         hw->adapter_stopped = 0;
2597         ixgbe_stop_adapter(hw);
2598
2599         /* reinitialize adapter
2600          * this calls reset and start
2601          */
2602         status = ixgbe_pf_reset_hw(hw);
2603         if (status != 0)
2604                 return -1;
2605         hw->mac.ops.start_hw(hw);
2606         hw->mac.get_link_status = true;
2607
2608         /* configure PF module if SRIOV enabled */
2609         ixgbe_pf_host_configure(dev);
2610
2611         ixgbe_dev_phy_intr_setup(dev);
2612
2613         /* check and configure queue intr-vector mapping */
2614         if ((rte_intr_cap_multiple(intr_handle) ||
2615              !RTE_ETH_DEV_SRIOV(dev).active) &&
2616             dev->data->dev_conf.intr_conf.rxq != 0) {
2617                 intr_vector = dev->data->nb_rx_queues;
2618                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2619                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2620                                         IXGBE_MAX_INTR_QUEUE_NUM);
2621                         return -ENOTSUP;
2622                 }
2623                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2624                         return -1;
2625         }
2626
2627         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2628                 intr_handle->intr_vec =
2629                         rte_zmalloc("intr_vec",
2630                                     dev->data->nb_rx_queues * sizeof(int), 0);
2631                 if (intr_handle->intr_vec == NULL) {
2632                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2633                                      " intr_vec", dev->data->nb_rx_queues);
2634                         return -ENOMEM;
2635                 }
2636         }
2637
2638         /* confiugre msix for sleep until rx interrupt */
2639         ixgbe_configure_msix(dev);
2640
2641         /* initialize transmission unit */
2642         ixgbe_dev_tx_init(dev);
2643
2644         /* This can fail when allocating mbufs for descriptor rings */
2645         err = ixgbe_dev_rx_init(dev);
2646         if (err) {
2647                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2648                 goto error;
2649         }
2650
2651         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2652                 ETH_VLAN_EXTEND_MASK;
2653         err = ixgbe_vlan_offload_config(dev, mask);
2654         if (err) {
2655                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2656                 goto error;
2657         }
2658
2659         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2660                 /* Enable vlan filtering for VMDq */
2661                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2662         }
2663
2664         /* Configure DCB hw */
2665         ixgbe_configure_dcb(dev);
2666
2667         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2668                 err = ixgbe_fdir_configure(dev);
2669                 if (err)
2670                         goto error;
2671         }
2672
2673         /* Restore vf rate limit */
2674         if (vfinfo != NULL) {
2675                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2676                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2677                                 if (vfinfo[vf].tx_rate[idx] != 0)
2678                                         ixgbe_set_vf_rate_limit(
2679                                                 dev, vf,
2680                                                 vfinfo[vf].tx_rate[idx],
2681                                                 1 << idx);
2682         }
2683
2684         ixgbe_restore_statistics_mapping(dev);
2685
2686         err = ixgbe_flow_ctrl_enable(dev, hw);
2687         if (err < 0) {
2688                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2689                 goto error;
2690         }
2691
2692         err = ixgbe_dev_rxtx_start(dev);
2693         if (err < 0) {
2694                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2695                 goto error;
2696         }
2697
2698         /* Skip link setup if loopback mode is enabled. */
2699         if (dev->data->dev_conf.lpbk_mode != 0) {
2700                 err = ixgbe_check_supported_loopback_mode(dev);
2701                 if (err < 0) {
2702                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2703                         goto error;
2704                 } else {
2705                         goto skip_link_setup;
2706                 }
2707         }
2708
2709         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2710                 err = hw->mac.ops.setup_sfp(hw);
2711                 if (err)
2712                         goto error;
2713         }
2714
2715         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2716                 /* Turn on the copper */
2717                 ixgbe_set_phy_power(hw, true);
2718         } else {
2719                 /* Turn on the laser */
2720                 ixgbe_enable_tx_laser(hw);
2721         }
2722
2723         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2724         if (err)
2725                 goto error;
2726         dev->data->dev_link.link_status = link_up;
2727
2728         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2729         if (err)
2730                 goto error;
2731
2732         switch (hw->mac.type) {
2733         case ixgbe_mac_X550:
2734         case ixgbe_mac_X550EM_x:
2735         case ixgbe_mac_X550EM_a:
2736                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2737                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2738                         ETH_LINK_SPEED_10G;
2739                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2740                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2741                         allowed_speeds = ETH_LINK_SPEED_10M |
2742                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2743                 break;
2744         default:
2745                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2746                         ETH_LINK_SPEED_10G;
2747         }
2748
2749         link_speeds = &dev->data->dev_conf.link_speeds;
2750
2751         /* Ignore autoneg flag bit and check the validity of
2752          * link_speed
2753          */
2754         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2755                 PMD_INIT_LOG(ERR, "Invalid link setting");
2756                 goto error;
2757         }
2758
2759         speed = 0x0;
2760         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2761                 switch (hw->mac.type) {
2762                 case ixgbe_mac_82598EB:
2763                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2764                         break;
2765                 case ixgbe_mac_82599EB:
2766                 case ixgbe_mac_X540:
2767                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2768                         break;
2769                 case ixgbe_mac_X550:
2770                 case ixgbe_mac_X550EM_x:
2771                 case ixgbe_mac_X550EM_a:
2772                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2773                         break;
2774                 default:
2775                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2776                 }
2777         } else {
2778                 if (*link_speeds & ETH_LINK_SPEED_10G)
2779                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2780                 if (*link_speeds & ETH_LINK_SPEED_5G)
2781                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2782                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2783                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2784                 if (*link_speeds & ETH_LINK_SPEED_1G)
2785                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2786                 if (*link_speeds & ETH_LINK_SPEED_100M)
2787                         speed |= IXGBE_LINK_SPEED_100_FULL;
2788                 if (*link_speeds & ETH_LINK_SPEED_10M)
2789                         speed |= IXGBE_LINK_SPEED_10_FULL;
2790         }
2791
2792         err = ixgbe_setup_link(hw, speed, link_up);
2793         if (err)
2794                 goto error;
2795
2796 skip_link_setup:
2797
2798         if (rte_intr_allow_others(intr_handle)) {
2799                 /* check if lsc interrupt is enabled */
2800                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2801                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2802                 else
2803                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2804                 ixgbe_dev_macsec_interrupt_setup(dev);
2805         } else {
2806                 rte_intr_callback_unregister(intr_handle,
2807                                              ixgbe_dev_interrupt_handler, dev);
2808                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2809                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2810                                      " no intr multiplex");
2811         }
2812
2813         /* check if rxq interrupt is enabled */
2814         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2815             rte_intr_dp_is_en(intr_handle))
2816                 ixgbe_dev_rxq_interrupt_setup(dev);
2817
2818         /* enable uio/vfio intr/eventfd mapping */
2819         rte_intr_enable(intr_handle);
2820
2821         /* resume enabled intr since hw reset */
2822         ixgbe_enable_intr(dev);
2823         ixgbe_l2_tunnel_conf(dev);
2824         ixgbe_filter_restore(dev);
2825
2826         if (tm_conf->root && !tm_conf->committed)
2827                 PMD_DRV_LOG(WARNING,
2828                             "please call hierarchy_commit() "
2829                             "before starting the port");
2830
2831         /* wait for the controller to acquire link */
2832         err = ixgbe_wait_for_link_up(hw);
2833         if (err)
2834                 goto error;
2835
2836         /*
2837          * Update link status right before return, because it may
2838          * start link configuration process in a separate thread.
2839          */
2840         ixgbe_dev_link_update(dev, 0);
2841
2842         /* setup the macsec setting register */
2843         if (macsec_setting->offload_en)
2844                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2845
2846         return 0;
2847
2848 error:
2849         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2850         ixgbe_dev_clear_queues(dev);
2851         return -EIO;
2852 }
2853
2854 /*
2855  * Stop device: disable rx and tx functions to allow for reconfiguring.
2856  */
2857 static int
2858 ixgbe_dev_stop(struct rte_eth_dev *dev)
2859 {
2860         struct rte_eth_link link;
2861         struct ixgbe_adapter *adapter = dev->data->dev_private;
2862         struct ixgbe_hw *hw =
2863                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2864         struct ixgbe_vf_info *vfinfo =
2865                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2866         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2867         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2868         int vf;
2869         struct ixgbe_tm_conf *tm_conf =
2870                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2871
2872         if (hw->adapter_stopped)
2873                 return 0;
2874
2875         PMD_INIT_FUNC_TRACE();
2876
2877         ixgbe_dev_wait_setup_link_complete(dev, 0);
2878
2879         /* disable interrupts */
2880         ixgbe_disable_intr(hw);
2881
2882         /* reset the NIC */
2883         ixgbe_pf_reset_hw(hw);
2884         hw->adapter_stopped = 0;
2885
2886         /* stop adapter */
2887         ixgbe_stop_adapter(hw);
2888
2889         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2890                 vfinfo[vf].clear_to_send = false;
2891
2892         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2893                 /* Turn off the copper */
2894                 ixgbe_set_phy_power(hw, false);
2895         } else {
2896                 /* Turn off the laser */
2897                 ixgbe_disable_tx_laser(hw);
2898         }
2899
2900         ixgbe_dev_clear_queues(dev);
2901
2902         /* Clear stored conf */
2903         dev->data->scattered_rx = 0;
2904         dev->data->lro = 0;
2905
2906         /* Clear recorded link status */
2907         memset(&link, 0, sizeof(link));
2908         rte_eth_linkstatus_set(dev, &link);
2909
2910         if (!rte_intr_allow_others(intr_handle))
2911                 /* resume to the default handler */
2912                 rte_intr_callback_register(intr_handle,
2913                                            ixgbe_dev_interrupt_handler,
2914                                            (void *)dev);
2915
2916         /* Clean datapath event and queue/vec mapping */
2917         rte_intr_efd_disable(intr_handle);
2918         if (intr_handle->intr_vec != NULL) {
2919                 rte_free(intr_handle->intr_vec);
2920                 intr_handle->intr_vec = NULL;
2921         }
2922
2923         /* reset hierarchy commit */
2924         tm_conf->committed = false;
2925
2926         adapter->rss_reta_updated = 0;
2927
2928         hw->adapter_stopped = true;
2929         dev->data->dev_started = 0;
2930
2931         return 0;
2932 }
2933
2934 /*
2935  * Set device link up: enable tx.
2936  */
2937 static int
2938 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2939 {
2940         struct ixgbe_hw *hw =
2941                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2942         if (hw->mac.type == ixgbe_mac_82599EB) {
2943 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2944                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2945                         /* Not suported in bypass mode */
2946                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2947                                      "by device id 0x%x", hw->device_id);
2948                         return -ENOTSUP;
2949                 }
2950 #endif
2951         }
2952
2953         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2954                 /* Turn on the copper */
2955                 ixgbe_set_phy_power(hw, true);
2956         } else {
2957                 /* Turn on the laser */
2958                 ixgbe_enable_tx_laser(hw);
2959                 ixgbe_dev_link_update(dev, 0);
2960         }
2961
2962         return 0;
2963 }
2964
2965 /*
2966  * Set device link down: disable tx.
2967  */
2968 static int
2969 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2970 {
2971         struct ixgbe_hw *hw =
2972                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2973         if (hw->mac.type == ixgbe_mac_82599EB) {
2974 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2975                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2976                         /* Not suported in bypass mode */
2977                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2978                                      "by device id 0x%x", hw->device_id);
2979                         return -ENOTSUP;
2980                 }
2981 #endif
2982         }
2983
2984         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2985                 /* Turn off the copper */
2986                 ixgbe_set_phy_power(hw, false);
2987         } else {
2988                 /* Turn off the laser */
2989                 ixgbe_disable_tx_laser(hw);
2990                 ixgbe_dev_link_update(dev, 0);
2991         }
2992
2993         return 0;
2994 }
2995
2996 /*
2997  * Reset and stop device.
2998  */
2999 static int
3000 ixgbe_dev_close(struct rte_eth_dev *dev)
3001 {
3002         struct ixgbe_hw *hw =
3003                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3005         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3006         int retries = 0;
3007         int ret;
3008
3009         PMD_INIT_FUNC_TRACE();
3010         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3011                 return 0;
3012
3013         ixgbe_pf_reset_hw(hw);
3014
3015         ret = ixgbe_dev_stop(dev);
3016
3017         ixgbe_dev_free_queues(dev);
3018
3019         ixgbe_disable_pcie_master(hw);
3020
3021         /* reprogram the RAR[0] in case user changed it. */
3022         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3023
3024         /* Unlock any pending hardware semaphore */
3025         ixgbe_swfw_lock_reset(hw);
3026
3027         /* disable uio intr before callback unregister */
3028         rte_intr_disable(intr_handle);
3029
3030         do {
3031                 ret = rte_intr_callback_unregister(intr_handle,
3032                                 ixgbe_dev_interrupt_handler, dev);
3033                 if (ret >= 0 || ret == -ENOENT) {
3034                         break;
3035                 } else if (ret != -EAGAIN) {
3036                         PMD_INIT_LOG(ERR,
3037                                 "intr callback unregister failed: %d",
3038                                 ret);
3039                 }
3040                 rte_delay_ms(100);
3041         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3042
3043         /* cancel the delay handler before remove dev */
3044         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3045
3046         /* uninitialize PF if max_vfs not zero */
3047         ixgbe_pf_host_uninit(dev);
3048
3049         /* remove all the fdir filters & hash */
3050         ixgbe_fdir_filter_uninit(dev);
3051
3052         /* remove all the L2 tunnel filters & hash */
3053         ixgbe_l2_tn_filter_uninit(dev);
3054
3055         /* Remove all ntuple filters of the device */
3056         ixgbe_ntuple_filter_uninit(dev);
3057
3058         /* clear all the filters list */
3059         ixgbe_filterlist_flush();
3060
3061         /* Remove all Traffic Manager configuration */
3062         ixgbe_tm_conf_uninit(dev);
3063
3064 #ifdef RTE_LIB_SECURITY
3065         rte_free(dev->security_ctx);
3066 #endif
3067
3068         return ret;
3069 }
3070
3071 /*
3072  * Reset PF device.
3073  */
3074 static int
3075 ixgbe_dev_reset(struct rte_eth_dev *dev)
3076 {
3077         int ret;
3078
3079         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3080          * its VF to make them align with it. The detailed notification
3081          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3082          * To avoid unexpected behavior in VF, currently reset of PF with
3083          * SR-IOV activation is not supported. It might be supported later.
3084          */
3085         if (dev->data->sriov.active)
3086                 return -ENOTSUP;
3087
3088         ret = eth_ixgbe_dev_uninit(dev);
3089         if (ret)
3090                 return ret;
3091
3092         ret = eth_ixgbe_dev_init(dev, NULL);
3093
3094         return ret;
3095 }
3096
3097 static void
3098 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3099                            struct ixgbe_hw_stats *hw_stats,
3100                            struct ixgbe_macsec_stats *macsec_stats,
3101                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3102                            uint64_t *total_qprc, uint64_t *total_qprdc)
3103 {
3104         uint32_t bprc, lxon, lxoff, total;
3105         uint32_t delta_gprc = 0;
3106         unsigned i;
3107         /* Workaround for RX byte count not including CRC bytes when CRC
3108          * strip is enabled. CRC bytes are removed from counters when crc_strip
3109          * is disabled.
3110          */
3111         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3112                         IXGBE_HLREG0_RXCRCSTRP);
3113
3114         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3115         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3116         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3117         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3118
3119         for (i = 0; i < 8; i++) {
3120                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3121
3122                 /* global total per queue */
3123                 hw_stats->mpc[i] += mp;
3124                 /* Running comprehensive total for stats display */
3125                 *total_missed_rx += hw_stats->mpc[i];
3126                 if (hw->mac.type == ixgbe_mac_82598EB) {
3127                         hw_stats->rnbc[i] +=
3128                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3129                         hw_stats->pxonrxc[i] +=
3130                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3131                         hw_stats->pxoffrxc[i] +=
3132                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3133                 } else {
3134                         hw_stats->pxonrxc[i] +=
3135                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3136                         hw_stats->pxoffrxc[i] +=
3137                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3138                         hw_stats->pxon2offc[i] +=
3139                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3140                 }
3141                 hw_stats->pxontxc[i] +=
3142                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3143                 hw_stats->pxofftxc[i] +=
3144                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3145         }
3146         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3147                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3148                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3149                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3150
3151                 delta_gprc += delta_qprc;
3152
3153                 hw_stats->qprc[i] += delta_qprc;
3154                 hw_stats->qptc[i] += delta_qptc;
3155
3156                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3157                 hw_stats->qbrc[i] +=
3158                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3159                 if (crc_strip == 0)
3160                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3161
3162                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3163                 hw_stats->qbtc[i] +=
3164                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3165
3166                 hw_stats->qprdc[i] += delta_qprdc;
3167                 *total_qprdc += hw_stats->qprdc[i];
3168
3169                 *total_qprc += hw_stats->qprc[i];
3170                 *total_qbrc += hw_stats->qbrc[i];
3171         }
3172         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3173         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3174         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3175
3176         /*
3177          * An errata states that gprc actually counts good + missed packets:
3178          * Workaround to set gprc to summated queue packet receives
3179          */
3180         hw_stats->gprc = *total_qprc;
3181
3182         if (hw->mac.type != ixgbe_mac_82598EB) {
3183                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3184                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3185                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3186                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3187                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3188                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3189                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3190                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3191         } else {
3192                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3193                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3194                 /* 82598 only has a counter in the high register */
3195                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3196                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3197                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3198         }
3199         uint64_t old_tpr = hw_stats->tpr;
3200
3201         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3202         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3203
3204         if (crc_strip == 0)
3205                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3206
3207         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3208         hw_stats->gptc += delta_gptc;
3209         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3210         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3211
3212         /*
3213          * Workaround: mprc hardware is incorrectly counting
3214          * broadcasts, so for now we subtract those.
3215          */
3216         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3217         hw_stats->bprc += bprc;
3218         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3219         if (hw->mac.type == ixgbe_mac_82598EB)
3220                 hw_stats->mprc -= bprc;
3221
3222         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3223         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3224         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3225         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3226         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3227         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3228
3229         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3230         hw_stats->lxontxc += lxon;
3231         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3232         hw_stats->lxofftxc += lxoff;
3233         total = lxon + lxoff;
3234
3235         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3236         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3237         hw_stats->gptc -= total;
3238         hw_stats->mptc -= total;
3239         hw_stats->ptc64 -= total;
3240         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3241
3242         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3243         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3244         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3245         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3246         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3247         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3248         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3249         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3250         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3251         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3252         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3253         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3254         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3255         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3256         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3257         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3258         /* Only read FCOE on 82599 */
3259         if (hw->mac.type != ixgbe_mac_82598EB) {
3260                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3261                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3262                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3263                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3264                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3265         }
3266
3267         /* Flow Director Stats registers */
3268         if (hw->mac.type != ixgbe_mac_82598EB) {
3269                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3270                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3271                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3272                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3273                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3274                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3275                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3276                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3277                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3278                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3279         }
3280         /* MACsec Stats registers */
3281         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3282         macsec_stats->out_pkts_encrypted +=
3283                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3284         macsec_stats->out_pkts_protected +=
3285                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3286         macsec_stats->out_octets_encrypted +=
3287                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3288         macsec_stats->out_octets_protected +=
3289                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3290         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3291         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3292         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3293         macsec_stats->in_pkts_unknownsci +=
3294                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3295         macsec_stats->in_octets_decrypted +=
3296                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3297         macsec_stats->in_octets_validated +=
3298                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3299         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3300         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3301         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3302         for (i = 0; i < 2; i++) {
3303                 macsec_stats->in_pkts_ok +=
3304                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3305                 macsec_stats->in_pkts_invalid +=
3306                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3307                 macsec_stats->in_pkts_notvalid +=
3308                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3309         }
3310         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3311         macsec_stats->in_pkts_notusingsa +=
3312                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3313 }
3314
3315 /*
3316  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3317  */
3318 static int
3319 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3320 {
3321         struct ixgbe_hw *hw =
3322                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3323         struct ixgbe_hw_stats *hw_stats =
3324                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3325         struct ixgbe_macsec_stats *macsec_stats =
3326                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3327                                 dev->data->dev_private);
3328         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3329         unsigned i;
3330
3331         total_missed_rx = 0;
3332         total_qbrc = 0;
3333         total_qprc = 0;
3334         total_qprdc = 0;
3335
3336         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3337                         &total_qbrc, &total_qprc, &total_qprdc);
3338
3339         if (stats == NULL)
3340                 return -EINVAL;
3341
3342         /* Fill out the rte_eth_stats statistics structure */
3343         stats->ipackets = total_qprc;
3344         stats->ibytes = total_qbrc;
3345         stats->opackets = hw_stats->gptc;
3346         stats->obytes = hw_stats->gotc;
3347
3348         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3349                 stats->q_ipackets[i] = hw_stats->qprc[i];
3350                 stats->q_opackets[i] = hw_stats->qptc[i];
3351                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3352                 stats->q_obytes[i] = hw_stats->qbtc[i];
3353                 stats->q_errors[i] = hw_stats->qprdc[i];
3354         }
3355
3356         /* Rx Errors */
3357         stats->imissed  = total_missed_rx;
3358         stats->ierrors  = hw_stats->crcerrs +
3359                           hw_stats->mspdc +
3360                           hw_stats->rlec +
3361                           hw_stats->ruc +
3362                           hw_stats->roc +
3363                           hw_stats->illerrc +
3364                           hw_stats->errbc +
3365                           hw_stats->rfc +
3366                           hw_stats->fccrc +
3367                           hw_stats->fclast;
3368
3369         /* Tx Errors */
3370         stats->oerrors  = 0;
3371         return 0;
3372 }
3373
3374 static int
3375 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3376 {
3377         struct ixgbe_hw_stats *stats =
3378                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3379
3380         /* HW registers are cleared on read */
3381         ixgbe_dev_stats_get(dev, NULL);
3382
3383         /* Reset software totals */
3384         memset(stats, 0, sizeof(*stats));
3385
3386         return 0;
3387 }
3388
3389 /* This function calculates the number of xstats based on the current config */
3390 static unsigned
3391 ixgbe_xstats_calc_num(void) {
3392         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3393                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3394                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3395 }
3396
3397 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3398         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3399 {
3400         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3401         unsigned stat, i, count;
3402
3403         if (xstats_names != NULL) {
3404                 count = 0;
3405
3406                 /* Note: limit >= cnt_stats checked upstream
3407                  * in rte_eth_xstats_names()
3408                  */
3409
3410                 /* Extended stats from ixgbe_hw_stats */
3411                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3412                         strlcpy(xstats_names[count].name,
3413                                 rte_ixgbe_stats_strings[i].name,
3414                                 sizeof(xstats_names[count].name));
3415                         count++;
3416                 }
3417
3418                 /* MACsec Stats */
3419                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3420                         strlcpy(xstats_names[count].name,
3421                                 rte_ixgbe_macsec_strings[i].name,
3422                                 sizeof(xstats_names[count].name));
3423                         count++;
3424                 }
3425
3426                 /* RX Priority Stats */
3427                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3428                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3429                                 snprintf(xstats_names[count].name,
3430                                         sizeof(xstats_names[count].name),
3431                                         "rx_priority%u_%s", i,
3432                                         rte_ixgbe_rxq_strings[stat].name);
3433                                 count++;
3434                         }
3435                 }
3436
3437                 /* TX Priority Stats */
3438                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3439                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3440                                 snprintf(xstats_names[count].name,
3441                                         sizeof(xstats_names[count].name),
3442                                         "tx_priority%u_%s", i,
3443                                         rte_ixgbe_txq_strings[stat].name);
3444                                 count++;
3445                         }
3446                 }
3447         }
3448         return cnt_stats;
3449 }
3450
3451 static int ixgbe_dev_xstats_get_names_by_id(
3452         struct rte_eth_dev *dev,
3453         struct rte_eth_xstat_name *xstats_names,
3454         const uint64_t *ids,
3455         unsigned int limit)
3456 {
3457         if (!ids) {
3458                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3459                 unsigned int stat, i, count;
3460
3461                 if (xstats_names != NULL) {
3462                         count = 0;
3463
3464                         /* Note: limit >= cnt_stats checked upstream
3465                          * in rte_eth_xstats_names()
3466                          */
3467
3468                         /* Extended stats from ixgbe_hw_stats */
3469                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3470                                 strlcpy(xstats_names[count].name,
3471                                         rte_ixgbe_stats_strings[i].name,
3472                                         sizeof(xstats_names[count].name));
3473                                 count++;
3474                         }
3475
3476                         /* MACsec Stats */
3477                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3478                                 strlcpy(xstats_names[count].name,
3479                                         rte_ixgbe_macsec_strings[i].name,
3480                                         sizeof(xstats_names[count].name));
3481                                 count++;
3482                         }
3483
3484                         /* RX Priority Stats */
3485                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3486                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3487                                         snprintf(xstats_names[count].name,
3488                                             sizeof(xstats_names[count].name),
3489                                             "rx_priority%u_%s", i,
3490                                             rte_ixgbe_rxq_strings[stat].name);
3491                                         count++;
3492                                 }
3493                         }
3494
3495                         /* TX Priority Stats */
3496                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3497                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3498                                         snprintf(xstats_names[count].name,
3499                                             sizeof(xstats_names[count].name),
3500                                             "tx_priority%u_%s", i,
3501                                             rte_ixgbe_txq_strings[stat].name);
3502                                         count++;
3503                                 }
3504                         }
3505                 }
3506                 return cnt_stats;
3507         }
3508
3509         uint16_t i;
3510         uint16_t size = ixgbe_xstats_calc_num();
3511         struct rte_eth_xstat_name xstats_names_copy[size];
3512
3513         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3514                         size);
3515
3516         for (i = 0; i < limit; i++) {
3517                 if (ids[i] >= size) {
3518                         PMD_INIT_LOG(ERR, "id value isn't valid");
3519                         return -1;
3520                 }
3521                 strcpy(xstats_names[i].name,
3522                                 xstats_names_copy[ids[i]].name);
3523         }
3524         return limit;
3525 }
3526
3527 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3528         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3529 {
3530         unsigned i;
3531
3532         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3533                 return -ENOMEM;
3534
3535         if (xstats_names != NULL)
3536                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3537                         strlcpy(xstats_names[i].name,
3538                                 rte_ixgbevf_stats_strings[i].name,
3539                                 sizeof(xstats_names[i].name));
3540         return IXGBEVF_NB_XSTATS;
3541 }
3542
3543 static int
3544 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3545                                          unsigned n)
3546 {
3547         struct ixgbe_hw *hw =
3548                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3549         struct ixgbe_hw_stats *hw_stats =
3550                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3551         struct ixgbe_macsec_stats *macsec_stats =
3552                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3553                                 dev->data->dev_private);
3554         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3555         unsigned i, stat, count = 0;
3556
3557         count = ixgbe_xstats_calc_num();
3558
3559         if (n < count)
3560                 return count;
3561
3562         total_missed_rx = 0;
3563         total_qbrc = 0;
3564         total_qprc = 0;
3565         total_qprdc = 0;
3566
3567         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3568                         &total_qbrc, &total_qprc, &total_qprdc);
3569
3570         /* If this is a reset xstats is NULL, and we have cleared the
3571          * registers by reading them.
3572          */
3573         if (!xstats)
3574                 return 0;
3575
3576         /* Extended stats from ixgbe_hw_stats */
3577         count = 0;
3578         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3579                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3580                                 rte_ixgbe_stats_strings[i].offset);
3581                 xstats[count].id = count;
3582                 count++;
3583         }
3584
3585         /* MACsec Stats */
3586         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3587                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3588                                 rte_ixgbe_macsec_strings[i].offset);
3589                 xstats[count].id = count;
3590                 count++;
3591         }
3592
3593         /* RX Priority Stats */
3594         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3595                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3596                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3597                                         rte_ixgbe_rxq_strings[stat].offset +
3598                                         (sizeof(uint64_t) * i));
3599                         xstats[count].id = count;
3600                         count++;
3601                 }
3602         }
3603
3604         /* TX Priority Stats */
3605         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3606                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3607                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3608                                         rte_ixgbe_txq_strings[stat].offset +
3609                                         (sizeof(uint64_t) * i));
3610                         xstats[count].id = count;
3611                         count++;
3612                 }
3613         }
3614         return count;
3615 }
3616
3617 static int
3618 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3619                 uint64_t *values, unsigned int n)
3620 {
3621         if (!ids) {
3622                 struct ixgbe_hw *hw =
3623                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3624                 struct ixgbe_hw_stats *hw_stats =
3625                                 IXGBE_DEV_PRIVATE_TO_STATS(
3626                                                 dev->data->dev_private);
3627                 struct ixgbe_macsec_stats *macsec_stats =
3628                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3629                                         dev->data->dev_private);
3630                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3631                 unsigned int i, stat, count = 0;
3632
3633                 count = ixgbe_xstats_calc_num();
3634
3635                 if (!ids && n < count)
3636                         return count;
3637
3638                 total_missed_rx = 0;
3639                 total_qbrc = 0;
3640                 total_qprc = 0;
3641                 total_qprdc = 0;
3642
3643                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3644                                 &total_missed_rx, &total_qbrc, &total_qprc,
3645                                 &total_qprdc);
3646
3647                 /* If this is a reset xstats is NULL, and we have cleared the
3648                  * registers by reading them.
3649                  */
3650                 if (!ids && !values)
3651                         return 0;
3652
3653                 /* Extended stats from ixgbe_hw_stats */
3654                 count = 0;
3655                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3656                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3657                                         rte_ixgbe_stats_strings[i].offset);
3658                         count++;
3659                 }
3660
3661                 /* MACsec Stats */
3662                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3663                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3664                                         rte_ixgbe_macsec_strings[i].offset);
3665                         count++;
3666                 }
3667
3668                 /* RX Priority Stats */
3669                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3670                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3671                                 values[count] =
3672                                         *(uint64_t *)(((char *)hw_stats) +
3673                                         rte_ixgbe_rxq_strings[stat].offset +
3674                                         (sizeof(uint64_t) * i));
3675                                 count++;
3676                         }
3677                 }
3678
3679                 /* TX Priority Stats */
3680                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3681                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3682                                 values[count] =
3683                                         *(uint64_t *)(((char *)hw_stats) +
3684                                         rte_ixgbe_txq_strings[stat].offset +
3685                                         (sizeof(uint64_t) * i));
3686                                 count++;
3687                         }
3688                 }
3689                 return count;
3690         }
3691
3692         uint16_t i;
3693         uint16_t size = ixgbe_xstats_calc_num();
3694         uint64_t values_copy[size];
3695
3696         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3697
3698         for (i = 0; i < n; i++) {
3699                 if (ids[i] >= size) {
3700                         PMD_INIT_LOG(ERR, "id value isn't valid");
3701                         return -1;
3702                 }
3703                 values[i] = values_copy[ids[i]];
3704         }
3705         return n;
3706 }
3707
3708 static int
3709 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3710 {
3711         struct ixgbe_hw_stats *stats =
3712                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3713         struct ixgbe_macsec_stats *macsec_stats =
3714                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3715                                 dev->data->dev_private);
3716
3717         unsigned count = ixgbe_xstats_calc_num();
3718
3719         /* HW registers are cleared on read */
3720         ixgbe_dev_xstats_get(dev, NULL, count);
3721
3722         /* Reset software totals */
3723         memset(stats, 0, sizeof(*stats));
3724         memset(macsec_stats, 0, sizeof(*macsec_stats));
3725
3726         return 0;
3727 }
3728
3729 static void
3730 ixgbevf_update_stats(struct rte_eth_dev *dev)
3731 {
3732         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3733         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3734                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3735
3736         /* Good Rx packet, include VF loopback */
3737         UPDATE_VF_STAT(IXGBE_VFGPRC,
3738             hw_stats->last_vfgprc, hw_stats->vfgprc);
3739
3740         /* Good Rx octets, include VF loopback */
3741         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3742             hw_stats->last_vfgorc, hw_stats->vfgorc);
3743
3744         /* Good Tx packet, include VF loopback */
3745         UPDATE_VF_STAT(IXGBE_VFGPTC,
3746             hw_stats->last_vfgptc, hw_stats->vfgptc);
3747
3748         /* Good Tx octets, include VF loopback */
3749         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3750             hw_stats->last_vfgotc, hw_stats->vfgotc);
3751
3752         /* Rx Multicst Packet */
3753         UPDATE_VF_STAT(IXGBE_VFMPRC,
3754             hw_stats->last_vfmprc, hw_stats->vfmprc);
3755 }
3756
3757 static int
3758 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3759                        unsigned n)
3760 {
3761         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3762                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3763         unsigned i;
3764
3765         if (n < IXGBEVF_NB_XSTATS)
3766                 return IXGBEVF_NB_XSTATS;
3767
3768         ixgbevf_update_stats(dev);
3769
3770         if (!xstats)
3771                 return 0;
3772
3773         /* Extended stats */
3774         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3775                 xstats[i].id = i;
3776                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3777                         rte_ixgbevf_stats_strings[i].offset);
3778         }
3779
3780         return IXGBEVF_NB_XSTATS;
3781 }
3782
3783 static int
3784 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3785 {
3786         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3787                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3788
3789         ixgbevf_update_stats(dev);
3790
3791         if (stats == NULL)
3792                 return -EINVAL;
3793
3794         stats->ipackets = hw_stats->vfgprc;
3795         stats->ibytes = hw_stats->vfgorc;
3796         stats->opackets = hw_stats->vfgptc;
3797         stats->obytes = hw_stats->vfgotc;
3798         return 0;
3799 }
3800
3801 static int
3802 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3803 {
3804         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3805                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3806
3807         /* Sync HW register to the last stats */
3808         ixgbevf_dev_stats_get(dev, NULL);
3809
3810         /* reset HW current stats*/
3811         hw_stats->vfgprc = 0;
3812         hw_stats->vfgorc = 0;
3813         hw_stats->vfgptc = 0;
3814         hw_stats->vfgotc = 0;
3815
3816         return 0;
3817 }
3818
3819 static int
3820 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3821 {
3822         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3823         u16 eeprom_verh, eeprom_verl;
3824         u32 etrack_id;
3825         int ret;
3826
3827         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3828         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3829
3830         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3831         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3832
3833         ret += 1; /* add the size of '\0' */
3834         if (fw_size < (u32)ret)
3835                 return ret;
3836         else
3837                 return 0;
3838 }
3839
3840 static int
3841 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3842 {
3843         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3845         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3846
3847         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3848         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3849         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3850                 /*
3851                  * When DCB/VT is off, maximum number of queues changes,
3852                  * except for 82598EB, which remains constant.
3853                  */
3854                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3855                                 hw->mac.type != ixgbe_mac_82598EB)
3856                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3857         }
3858         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3859         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3860         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3861         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3862         dev_info->max_vfs = pci_dev->max_vfs;
3863         if (hw->mac.type == ixgbe_mac_82598EB)
3864                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3865         else
3866                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3867         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3868         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3869         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3870         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3871         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3872                                      dev_info->rx_queue_offload_capa);
3873         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3874         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3875
3876         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3877                 .rx_thresh = {
3878                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3879                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3880                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3881                 },
3882                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3883                 .rx_drop_en = 0,
3884                 .offloads = 0,
3885         };
3886
3887         dev_info->default_txconf = (struct rte_eth_txconf) {
3888                 .tx_thresh = {
3889                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3890                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3891                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3892                 },
3893                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3894                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3895                 .offloads = 0,
3896         };
3897
3898         dev_info->rx_desc_lim = rx_desc_lim;
3899         dev_info->tx_desc_lim = tx_desc_lim;
3900
3901         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3902         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3903         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3904
3905         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3906         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3907                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3908                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3909                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3910
3911         if (hw->mac.type == ixgbe_mac_X540 ||
3912             hw->mac.type == ixgbe_mac_X540_vf ||
3913             hw->mac.type == ixgbe_mac_X550 ||
3914             hw->mac.type == ixgbe_mac_X550_vf) {
3915                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3916         }
3917         if (hw->mac.type == ixgbe_mac_X550) {
3918                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3919                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3920         }
3921
3922         /* Driver-preferred Rx/Tx parameters */
3923         dev_info->default_rxportconf.burst_size = 32;
3924         dev_info->default_txportconf.burst_size = 32;
3925         dev_info->default_rxportconf.nb_queues = 1;
3926         dev_info->default_txportconf.nb_queues = 1;
3927         dev_info->default_rxportconf.ring_size = 256;
3928         dev_info->default_txportconf.ring_size = 256;
3929
3930         return 0;
3931 }
3932
3933 static const uint32_t *
3934 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3935 {
3936         static const uint32_t ptypes[] = {
3937                 /* For non-vec functions,
3938                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3939                  * for vec functions,
3940                  * refers to _recv_raw_pkts_vec().
3941                  */
3942                 RTE_PTYPE_L2_ETHER,
3943                 RTE_PTYPE_L3_IPV4,
3944                 RTE_PTYPE_L3_IPV4_EXT,
3945                 RTE_PTYPE_L3_IPV6,
3946                 RTE_PTYPE_L3_IPV6_EXT,
3947                 RTE_PTYPE_L4_SCTP,
3948                 RTE_PTYPE_L4_TCP,
3949                 RTE_PTYPE_L4_UDP,
3950                 RTE_PTYPE_TUNNEL_IP,
3951                 RTE_PTYPE_INNER_L3_IPV6,
3952                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3953                 RTE_PTYPE_INNER_L4_TCP,
3954                 RTE_PTYPE_INNER_L4_UDP,
3955                 RTE_PTYPE_UNKNOWN
3956         };
3957
3958         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3959             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3960             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3961             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3962                 return ptypes;
3963
3964 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3965         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3966             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3967                 return ptypes;
3968 #endif
3969         return NULL;
3970 }
3971
3972 static int
3973 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3974                      struct rte_eth_dev_info *dev_info)
3975 {
3976         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3977         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3978
3979         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3980         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3981         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3982         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3983         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3984         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3985         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3986         dev_info->max_vfs = pci_dev->max_vfs;
3987         if (hw->mac.type == ixgbe_mac_82598EB)
3988                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3989         else
3990                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3991         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3992         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3993                                      dev_info->rx_queue_offload_capa);
3994         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3995         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3996         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3997         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3998         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3999
4000         dev_info->default_rxconf = (struct rte_eth_rxconf) {
4001                 .rx_thresh = {
4002                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
4003                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
4004                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
4005                 },
4006                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4007                 .rx_drop_en = 0,
4008                 .offloads = 0,
4009         };
4010
4011         dev_info->default_txconf = (struct rte_eth_txconf) {
4012                 .tx_thresh = {
4013                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4014                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4015                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4016                 },
4017                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4018                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4019                 .offloads = 0,
4020         };
4021
4022         dev_info->rx_desc_lim = rx_desc_lim;
4023         dev_info->tx_desc_lim = tx_desc_lim;
4024
4025         return 0;
4026 }
4027
4028 static int
4029 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4030                    bool *link_up, int wait_to_complete)
4031 {
4032         struct ixgbe_adapter *adapter = container_of(hw,
4033                                                      struct ixgbe_adapter, hw);
4034         struct ixgbe_mbx_info *mbx = &hw->mbx;
4035         struct ixgbe_mac_info *mac = &hw->mac;
4036         uint32_t links_reg, in_msg;
4037         int ret_val = 0;
4038
4039         /* If we were hit with a reset drop the link */
4040         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4041                 mac->get_link_status = true;
4042
4043         if (!mac->get_link_status)
4044                 goto out;
4045
4046         /* if link status is down no point in checking to see if pf is up */
4047         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4048         if (!(links_reg & IXGBE_LINKS_UP))
4049                 goto out;
4050
4051         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4052          * before the link status is correct
4053          */
4054         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4055                 int i;
4056
4057                 for (i = 0; i < 5; i++) {
4058                         rte_delay_us(100);
4059                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4060
4061                         if (!(links_reg & IXGBE_LINKS_UP))
4062                                 goto out;
4063                 }
4064         }
4065
4066         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4067         case IXGBE_LINKS_SPEED_10G_82599:
4068                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4069                 if (hw->mac.type >= ixgbe_mac_X550) {
4070                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4071                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4072                 }
4073                 break;
4074         case IXGBE_LINKS_SPEED_1G_82599:
4075                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4076                 break;
4077         case IXGBE_LINKS_SPEED_100_82599:
4078                 *speed = IXGBE_LINK_SPEED_100_FULL;
4079                 if (hw->mac.type == ixgbe_mac_X550) {
4080                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4081                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4082                 }
4083                 break;
4084         case IXGBE_LINKS_SPEED_10_X550EM_A:
4085                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4086                 /* Since Reserved in older MAC's */
4087                 if (hw->mac.type >= ixgbe_mac_X550)
4088                         *speed = IXGBE_LINK_SPEED_10_FULL;
4089                 break;
4090         default:
4091                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4092         }
4093
4094         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4095                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4096                         mac->get_link_status = true;
4097                 else
4098                         mac->get_link_status = false;
4099
4100                 goto out;
4101         }
4102
4103         /* if the read failed it could just be a mailbox collision, best wait
4104          * until we are called again and don't report an error
4105          */
4106         if (mbx->ops.read(hw, &in_msg, 1, 0))
4107                 goto out;
4108
4109         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4110                 /* msg is not CTS and is NACK we must have lost CTS status */
4111                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4112                         mac->get_link_status = false;
4113                 goto out;
4114         }
4115
4116         /* the pf is talking, if we timed out in the past we reinit */
4117         if (!mbx->timeout) {
4118                 ret_val = -1;
4119                 goto out;
4120         }
4121
4122         /* if we passed all the tests above then the link is up and we no
4123          * longer need to check for link
4124          */
4125         mac->get_link_status = false;
4126
4127 out:
4128         *link_up = !mac->get_link_status;
4129         return ret_val;
4130 }
4131
4132 /*
4133  * If @timeout_ms was 0, it means that it will not return until link complete.
4134  * It returns 1 on complete, return 0 on timeout.
4135  */
4136 static int
4137 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4138 {
4139 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4140         struct ixgbe_adapter *ad = dev->data->dev_private;
4141         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4142
4143         while (rte_atomic32_read(&ad->link_thread_running)) {
4144                 msec_delay(1);
4145                 timeout--;
4146
4147                 if (timeout_ms) {
4148                         if (!timeout)
4149                                 return 0;
4150                 } else if (!timeout) {
4151                         /* It will not return until link complete */
4152                         timeout = WARNING_TIMEOUT;
4153                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4154                 }
4155         }
4156
4157         return 1;
4158 }
4159
4160 static void *
4161 ixgbe_dev_setup_link_thread_handler(void *param)
4162 {
4163         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4164         struct ixgbe_adapter *ad = dev->data->dev_private;
4165         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4166         struct ixgbe_interrupt *intr =
4167                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4168         u32 speed;
4169         bool autoneg = false;
4170
4171         pthread_detach(pthread_self());
4172         speed = hw->phy.autoneg_advertised;
4173         if (!speed)
4174                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4175
4176         ixgbe_setup_link(hw, speed, true);
4177
4178         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4179         rte_atomic32_clear(&ad->link_thread_running);
4180         return NULL;
4181 }
4182
4183 /*
4184  * In freebsd environment, nic_uio drivers do not support interrupts,
4185  * rte_intr_callback_register() will fail to register interrupts.
4186  * We can not make link status to change from down to up by interrupt
4187  * callback. So we need to wait for the controller to acquire link
4188  * when ports start.
4189  * It returns 0 on link up.
4190  */
4191 static int
4192 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4193 {
4194 #ifdef RTE_EXEC_ENV_FREEBSD
4195         int err, i;
4196         bool link_up = false;
4197         uint32_t speed = 0;
4198         const int nb_iter = 25;
4199
4200         for (i = 0; i < nb_iter; i++) {
4201                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4202                 if (err)
4203                         return err;
4204                 if (link_up)
4205                         return 0;
4206                 msec_delay(200);
4207         }
4208
4209         return 0;
4210 #else
4211         RTE_SET_USED(hw);
4212         return 0;
4213 #endif
4214 }
4215
4216 /* return 0 means link status changed, -1 means not changed */
4217 int
4218 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4219                             int wait_to_complete, int vf)
4220 {
4221         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4222         struct ixgbe_adapter *ad = dev->data->dev_private;
4223         struct rte_eth_link link;
4224         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4225         struct ixgbe_interrupt *intr =
4226                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4227         bool link_up;
4228         int diag;
4229         int wait = 1;
4230         u32 esdp_reg;
4231
4232         memset(&link, 0, sizeof(link));
4233         link.link_status = ETH_LINK_DOWN;
4234         link.link_speed = ETH_SPEED_NUM_NONE;
4235         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4236         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4237                         ETH_LINK_SPEED_FIXED);
4238
4239         hw->mac.get_link_status = true;
4240
4241         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4242                 return rte_eth_linkstatus_set(dev, &link);
4243
4244         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4245         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4246                 wait = 0;
4247
4248 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4249 #ifdef RTE_EXEC_ENV_FREEBSD
4250         wait = 1;
4251 #endif
4252
4253         if (vf)
4254                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4255         else
4256                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4257
4258         if (diag != 0) {
4259                 link.link_speed = ETH_SPEED_NUM_100M;
4260                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4261                 return rte_eth_linkstatus_set(dev, &link);
4262         }
4263
4264         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4265                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4266                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4267                         link_up = 0;
4268         }
4269
4270         if (link_up == 0) {
4271                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4272                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4273                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4274                                 /* To avoid race condition between threads, set
4275                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4276                                  * when there is no link thread running.
4277                                  */
4278                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4279                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4280                                         "ixgbe-link-handler",
4281                                         NULL,
4282                                         ixgbe_dev_setup_link_thread_handler,
4283                                         dev) < 0) {
4284                                         PMD_DRV_LOG(ERR,
4285                                                 "Create link thread failed!");
4286                                         rte_atomic32_clear(&ad->link_thread_running);
4287                                 }
4288                         } else {
4289                                 PMD_DRV_LOG(ERR,
4290                                         "Other link thread is running now!");
4291                         }
4292                 }
4293                 return rte_eth_linkstatus_set(dev, &link);
4294         }
4295
4296         link.link_status = ETH_LINK_UP;
4297         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4298
4299         switch (link_speed) {
4300         default:
4301         case IXGBE_LINK_SPEED_UNKNOWN:
4302                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4303                 break;
4304
4305         case IXGBE_LINK_SPEED_10_FULL:
4306                 link.link_speed = ETH_SPEED_NUM_10M;
4307                 break;
4308
4309         case IXGBE_LINK_SPEED_100_FULL:
4310                 link.link_speed = ETH_SPEED_NUM_100M;
4311                 break;
4312
4313         case IXGBE_LINK_SPEED_1GB_FULL:
4314                 link.link_speed = ETH_SPEED_NUM_1G;
4315                 break;
4316
4317         case IXGBE_LINK_SPEED_2_5GB_FULL:
4318                 link.link_speed = ETH_SPEED_NUM_2_5G;
4319                 break;
4320
4321         case IXGBE_LINK_SPEED_5GB_FULL:
4322                 link.link_speed = ETH_SPEED_NUM_5G;
4323                 break;
4324
4325         case IXGBE_LINK_SPEED_10GB_FULL:
4326                 link.link_speed = ETH_SPEED_NUM_10G;
4327                 break;
4328         }
4329
4330         return rte_eth_linkstatus_set(dev, &link);
4331 }
4332
4333 static int
4334 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4335 {
4336         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4337 }
4338
4339 static int
4340 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4341 {
4342         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4343 }
4344
4345 static int
4346 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4347 {
4348         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4349         uint32_t fctrl;
4350
4351         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4352         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4353         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4354
4355         return 0;
4356 }
4357
4358 static int
4359 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4360 {
4361         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362         uint32_t fctrl;
4363
4364         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4365         fctrl &= (~IXGBE_FCTRL_UPE);
4366         if (dev->data->all_multicast == 1)
4367                 fctrl |= IXGBE_FCTRL_MPE;
4368         else
4369                 fctrl &= (~IXGBE_FCTRL_MPE);
4370         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4371
4372         return 0;
4373 }
4374
4375 static int
4376 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4377 {
4378         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4379         uint32_t fctrl;
4380
4381         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4382         fctrl |= IXGBE_FCTRL_MPE;
4383         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4384
4385         return 0;
4386 }
4387
4388 static int
4389 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4390 {
4391         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4392         uint32_t fctrl;
4393
4394         if (dev->data->promiscuous == 1)
4395                 return 0; /* must remain in all_multicast mode */
4396
4397         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4398         fctrl &= (~IXGBE_FCTRL_MPE);
4399         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4400
4401         return 0;
4402 }
4403
4404 /**
4405  * It clears the interrupt causes and enables the interrupt.
4406  * It will be called once only during nic initialized.
4407  *
4408  * @param dev
4409  *  Pointer to struct rte_eth_dev.
4410  * @param on
4411  *  Enable or Disable.
4412  *
4413  * @return
4414  *  - On success, zero.
4415  *  - On failure, a negative value.
4416  */
4417 static int
4418 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4419 {
4420         struct ixgbe_interrupt *intr =
4421                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4422
4423         ixgbe_dev_link_status_print(dev);
4424         if (on)
4425                 intr->mask |= IXGBE_EICR_LSC;
4426         else
4427                 intr->mask &= ~IXGBE_EICR_LSC;
4428
4429         return 0;
4430 }
4431
4432 /**
4433  * It clears the interrupt causes and enables the interrupt.
4434  * It will be called once only during nic initialized.
4435  *
4436  * @param dev
4437  *  Pointer to struct rte_eth_dev.
4438  *
4439  * @return
4440  *  - On success, zero.
4441  *  - On failure, a negative value.
4442  */
4443 static int
4444 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4445 {
4446         struct ixgbe_interrupt *intr =
4447                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4448
4449         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4450
4451         return 0;
4452 }
4453
4454 /**
4455  * It clears the interrupt causes and enables the interrupt.
4456  * It will be called once only during nic initialized.
4457  *
4458  * @param dev
4459  *  Pointer to struct rte_eth_dev.
4460  *
4461  * @return
4462  *  - On success, zero.
4463  *  - On failure, a negative value.
4464  */
4465 static int
4466 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4467 {
4468         struct ixgbe_interrupt *intr =
4469                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4470
4471         intr->mask |= IXGBE_EICR_LINKSEC;
4472
4473         return 0;
4474 }
4475
4476 /*
4477  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4478  *
4479  * @param dev
4480  *  Pointer to struct rte_eth_dev.
4481  *
4482  * @return
4483  *  - On success, zero.
4484  *  - On failure, a negative value.
4485  */
4486 static int
4487 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4488 {
4489         uint32_t eicr;
4490         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4491         struct ixgbe_interrupt *intr =
4492                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4493
4494         /* clear all cause mask */
4495         ixgbe_disable_intr(hw);
4496
4497         /* read-on-clear nic registers here */
4498         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4499         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4500
4501         intr->flags = 0;
4502
4503         /* set flag for async link update */
4504         if (eicr & IXGBE_EICR_LSC)
4505                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4506
4507         if (eicr & IXGBE_EICR_MAILBOX)
4508                 intr->flags |= IXGBE_FLAG_MAILBOX;
4509
4510         if (eicr & IXGBE_EICR_LINKSEC)
4511                 intr->flags |= IXGBE_FLAG_MACSEC;
4512
4513         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4514             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4515             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4516                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4517
4518         return 0;
4519 }
4520
4521 /**
4522  * It gets and then prints the link status.
4523  *
4524  * @param dev
4525  *  Pointer to struct rte_eth_dev.
4526  *
4527  * @return
4528  *  - On success, zero.
4529  *  - On failure, a negative value.
4530  */
4531 static void
4532 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4533 {
4534         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4535         struct rte_eth_link link;
4536
4537         rte_eth_linkstatus_get(dev, &link);
4538
4539         if (link.link_status) {
4540                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4541                                         (int)(dev->data->port_id),
4542                                         (unsigned)link.link_speed,
4543                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4544                                         "full-duplex" : "half-duplex");
4545         } else {
4546                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4547                                 (int)(dev->data->port_id));
4548         }
4549         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4550                                 pci_dev->addr.domain,
4551                                 pci_dev->addr.bus,
4552                                 pci_dev->addr.devid,
4553                                 pci_dev->addr.function);
4554 }
4555
4556 /*
4557  * It executes link_update after knowing an interrupt occurred.
4558  *
4559  * @param dev
4560  *  Pointer to struct rte_eth_dev.
4561  *
4562  * @return
4563  *  - On success, zero.
4564  *  - On failure, a negative value.
4565  */
4566 static int
4567 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4568 {
4569         struct ixgbe_interrupt *intr =
4570                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4571         int64_t timeout;
4572         struct ixgbe_hw *hw =
4573                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4574
4575         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4576
4577         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4578                 ixgbe_pf_mbx_process(dev);
4579                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4580         }
4581
4582         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4583                 ixgbe_handle_lasi(hw);
4584                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4585         }
4586
4587         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4588                 struct rte_eth_link link;
4589
4590                 /* get the link status before link update, for predicting later */
4591                 rte_eth_linkstatus_get(dev, &link);
4592
4593                 ixgbe_dev_link_update(dev, 0);
4594
4595                 /* likely to up */
4596                 if (!link.link_status)
4597                         /* handle it 1 sec later, wait it being stable */
4598                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4599                 /* likely to down */
4600                 else
4601                         /* handle it 4 sec later, wait it being stable */
4602                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4603
4604                 ixgbe_dev_link_status_print(dev);
4605                 if (rte_eal_alarm_set(timeout * 1000,
4606                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4607                         PMD_DRV_LOG(ERR, "Error setting alarm");
4608                 else {
4609                         /* remember original mask */
4610                         intr->mask_original = intr->mask;
4611                         /* only disable lsc interrupt */
4612                         intr->mask &= ~IXGBE_EIMS_LSC;
4613                 }
4614         }
4615
4616         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4617         ixgbe_enable_intr(dev);
4618
4619         return 0;
4620 }
4621
4622 /**
4623  * Interrupt handler which shall be registered for alarm callback for delayed
4624  * handling specific interrupt to wait for the stable nic state. As the
4625  * NIC interrupt state is not stable for ixgbe after link is just down,
4626  * it needs to wait 4 seconds to get the stable status.
4627  *
4628  * @param handle
4629  *  Pointer to interrupt handle.
4630  * @param param
4631  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4632  *
4633  * @return
4634  *  void
4635  */
4636 static void
4637 ixgbe_dev_interrupt_delayed_handler(void *param)
4638 {
4639         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4640         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4641         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4642         struct ixgbe_interrupt *intr =
4643                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4644         struct ixgbe_hw *hw =
4645                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4646         uint32_t eicr;
4647
4648         ixgbe_disable_intr(hw);
4649
4650         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4651         if (eicr & IXGBE_EICR_MAILBOX)
4652                 ixgbe_pf_mbx_process(dev);
4653
4654         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4655                 ixgbe_handle_lasi(hw);
4656                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4657         }
4658
4659         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4660                 ixgbe_dev_link_update(dev, 0);
4661                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4662                 ixgbe_dev_link_status_print(dev);
4663                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4664         }
4665
4666         if (intr->flags & IXGBE_FLAG_MACSEC) {
4667                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4668                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4669         }
4670
4671         /* restore original mask */
4672         intr->mask = intr->mask_original;
4673         intr->mask_original = 0;
4674
4675         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4676         ixgbe_enable_intr(dev);
4677         rte_intr_ack(intr_handle);
4678 }
4679
4680 /**
4681  * Interrupt handler triggered by NIC  for handling
4682  * specific interrupt.
4683  *
4684  * @param handle
4685  *  Pointer to interrupt handle.
4686  * @param param
4687  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4688  *
4689  * @return
4690  *  void
4691  */
4692 static void
4693 ixgbe_dev_interrupt_handler(void *param)
4694 {
4695         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4696
4697         ixgbe_dev_interrupt_get_status(dev);
4698         ixgbe_dev_interrupt_action(dev);
4699 }
4700
4701 static int
4702 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4703 {
4704         struct ixgbe_hw *hw;
4705
4706         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4707         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4708 }
4709
4710 static int
4711 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4712 {
4713         struct ixgbe_hw *hw;
4714
4715         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4716         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4717 }
4718
4719 static int
4720 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4721 {
4722         struct ixgbe_hw *hw;
4723         uint32_t mflcn_reg;
4724         uint32_t fccfg_reg;
4725         int rx_pause;
4726         int tx_pause;
4727
4728         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4729
4730         fc_conf->pause_time = hw->fc.pause_time;
4731         fc_conf->high_water = hw->fc.high_water[0];
4732         fc_conf->low_water = hw->fc.low_water[0];
4733         fc_conf->send_xon = hw->fc.send_xon;
4734         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4735
4736         /*
4737          * Return rx_pause status according to actual setting of
4738          * MFLCN register.
4739          */
4740         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4741         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4742                 fc_conf->mac_ctrl_frame_fwd = 1;
4743         else
4744                 fc_conf->mac_ctrl_frame_fwd = 0;
4745
4746         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4747                 rx_pause = 1;
4748         else
4749                 rx_pause = 0;
4750
4751         /*
4752          * Return tx_pause status according to actual setting of
4753          * FCCFG register.
4754          */
4755         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4756         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4757                 tx_pause = 1;
4758         else
4759                 tx_pause = 0;
4760
4761         if (rx_pause && tx_pause)
4762                 fc_conf->mode = RTE_FC_FULL;
4763         else if (rx_pause)
4764                 fc_conf->mode = RTE_FC_RX_PAUSE;
4765         else if (tx_pause)
4766                 fc_conf->mode = RTE_FC_TX_PAUSE;
4767         else
4768                 fc_conf->mode = RTE_FC_NONE;
4769
4770         return 0;
4771 }
4772
4773 static int
4774 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4775 {
4776         struct ixgbe_hw *hw;
4777         struct ixgbe_adapter *adapter = dev->data->dev_private;
4778         int err;
4779         uint32_t rx_buf_size;
4780         uint32_t max_high_water;
4781         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4782                 ixgbe_fc_none,
4783                 ixgbe_fc_rx_pause,
4784                 ixgbe_fc_tx_pause,
4785                 ixgbe_fc_full
4786         };
4787
4788         PMD_INIT_FUNC_TRACE();
4789
4790         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4791         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4792         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4793
4794         /*
4795          * At least reserve one Ethernet frame for watermark
4796          * high_water/low_water in kilo bytes for ixgbe
4797          */
4798         max_high_water = (rx_buf_size -
4799                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4800         if ((fc_conf->high_water > max_high_water) ||
4801                 (fc_conf->high_water < fc_conf->low_water)) {
4802                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4803                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4804                 return -EINVAL;
4805         }
4806
4807         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4808         hw->fc.pause_time     = fc_conf->pause_time;
4809         hw->fc.high_water[0]  = fc_conf->high_water;
4810         hw->fc.low_water[0]   = fc_conf->low_water;
4811         hw->fc.send_xon       = fc_conf->send_xon;
4812         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4813         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4814
4815         err = ixgbe_flow_ctrl_enable(dev, hw);
4816         if (err < 0) {
4817                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4818                 return -EIO;
4819         }
4820         return err;
4821 }
4822
4823 /**
4824  *  ixgbe_pfc_enable_generic - Enable flow control
4825  *  @hw: pointer to hardware structure
4826  *  @tc_num: traffic class number
4827  *  Enable flow control according to the current settings.
4828  */
4829 static int
4830 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4831 {
4832         int ret_val = 0;
4833         uint32_t mflcn_reg, fccfg_reg;
4834         uint32_t reg;
4835         uint32_t fcrtl, fcrth;
4836         uint8_t i;
4837         uint8_t nb_rx_en;
4838
4839         /* Validate the water mark configuration */
4840         if (!hw->fc.pause_time) {
4841                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4842                 goto out;
4843         }
4844
4845         /* Low water mark of zero causes XOFF floods */
4846         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4847                  /* High/Low water can not be 0 */
4848                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4849                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4850                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4851                         goto out;
4852                 }
4853
4854                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4855                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4856                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4857                         goto out;
4858                 }
4859         }
4860         /* Negotiate the fc mode to use */
4861         ixgbe_fc_autoneg(hw);
4862
4863         /* Disable any previous flow control settings */
4864         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4865         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4866
4867         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4868         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4869
4870         switch (hw->fc.current_mode) {
4871         case ixgbe_fc_none:
4872                 /*
4873                  * If the count of enabled RX Priority Flow control >1,
4874                  * and the TX pause can not be disabled
4875                  */
4876                 nb_rx_en = 0;
4877                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4878                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4879                         if (reg & IXGBE_FCRTH_FCEN)
4880                                 nb_rx_en++;
4881                 }
4882                 if (nb_rx_en > 1)
4883                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4884                 break;
4885         case ixgbe_fc_rx_pause:
4886                 /*
4887                  * Rx Flow control is enabled and Tx Flow control is
4888                  * disabled by software override. Since there really
4889                  * isn't a way to advertise that we are capable of RX
4890                  * Pause ONLY, we will advertise that we support both
4891                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4892                  * disable the adapter's ability to send PAUSE frames.
4893                  */
4894                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4895                 /*
4896                  * If the count of enabled RX Priority Flow control >1,
4897                  * and the TX pause can not be disabled
4898                  */
4899                 nb_rx_en = 0;
4900                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4901                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4902                         if (reg & IXGBE_FCRTH_FCEN)
4903                                 nb_rx_en++;
4904                 }
4905                 if (nb_rx_en > 1)
4906                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4907                 break;
4908         case ixgbe_fc_tx_pause:
4909                 /*
4910                  * Tx Flow control is enabled, and Rx Flow control is
4911                  * disabled by software override.
4912                  */
4913                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4914                 break;
4915         case ixgbe_fc_full:
4916                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4917                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4918                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4919                 break;
4920         default:
4921                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4922                 ret_val = IXGBE_ERR_CONFIG;
4923                 goto out;
4924         }
4925
4926         /* Set 802.3x based flow control settings. */
4927         mflcn_reg |= IXGBE_MFLCN_DPF;
4928         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4929         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4930
4931         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4932         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4933                 hw->fc.high_water[tc_num]) {
4934                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4935                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4936                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4937         } else {
4938                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4939                 /*
4940                  * In order to prevent Tx hangs when the internal Tx
4941                  * switch is enabled we must set the high water mark
4942                  * to the maximum FCRTH value.  This allows the Tx
4943                  * switch to function even under heavy Rx workloads.
4944                  */
4945                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4946         }
4947         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4948
4949         /* Configure pause time (2 TCs per register) */
4950         reg = hw->fc.pause_time * 0x00010001;
4951         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4952                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4953
4954         /* Configure flow control refresh threshold value */
4955         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4956
4957 out:
4958         return ret_val;
4959 }
4960
4961 static int
4962 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4963 {
4964         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4965         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4966
4967         if (hw->mac.type != ixgbe_mac_82598EB) {
4968                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4969         }
4970         return ret_val;
4971 }
4972
4973 static int
4974 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4975 {
4976         int err;
4977         uint32_t rx_buf_size;
4978         uint32_t max_high_water;
4979         uint8_t tc_num;
4980         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4981         struct ixgbe_hw *hw =
4982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4983         struct ixgbe_dcb_config *dcb_config =
4984                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4985
4986         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4987                 ixgbe_fc_none,
4988                 ixgbe_fc_rx_pause,
4989                 ixgbe_fc_tx_pause,
4990                 ixgbe_fc_full
4991         };
4992
4993         PMD_INIT_FUNC_TRACE();
4994
4995         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4996         tc_num = map[pfc_conf->priority];
4997         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4998         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4999         /*
5000          * At least reserve one Ethernet frame for watermark
5001          * high_water/low_water in kilo bytes for ixgbe
5002          */
5003         max_high_water = (rx_buf_size -
5004                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
5005         if ((pfc_conf->fc.high_water > max_high_water) ||
5006             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5007                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5008                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5009                 return -EINVAL;
5010         }
5011
5012         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5013         hw->fc.pause_time = pfc_conf->fc.pause_time;
5014         hw->fc.send_xon = pfc_conf->fc.send_xon;
5015         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5016         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5017
5018         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5019
5020         /* Not negotiated is not an error case */
5021         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5022                 return 0;
5023
5024         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5025         return -EIO;
5026 }
5027
5028 static int
5029 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5030                           struct rte_eth_rss_reta_entry64 *reta_conf,
5031                           uint16_t reta_size)
5032 {
5033         uint16_t i, sp_reta_size;
5034         uint8_t j, mask;
5035         uint32_t reta, r;
5036         uint16_t idx, shift;
5037         struct ixgbe_adapter *adapter = dev->data->dev_private;
5038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5039         uint32_t reta_reg;
5040
5041         PMD_INIT_FUNC_TRACE();
5042
5043         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5044                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5045                         "NIC.");
5046                 return -ENOTSUP;
5047         }
5048
5049         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5050         if (reta_size != sp_reta_size) {
5051                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5052                         "(%d) doesn't match the number hardware can supported "
5053                         "(%d)", reta_size, sp_reta_size);
5054                 return -EINVAL;
5055         }
5056
5057         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5058                 idx = i / RTE_RETA_GROUP_SIZE;
5059                 shift = i % RTE_RETA_GROUP_SIZE;
5060                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5061                                                 IXGBE_4_BIT_MASK);
5062                 if (!mask)
5063                         continue;
5064                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5065                 if (mask == IXGBE_4_BIT_MASK)
5066                         r = 0;
5067                 else
5068                         r = IXGBE_READ_REG(hw, reta_reg);
5069                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5070                         if (mask & (0x1 << j))
5071                                 reta |= reta_conf[idx].reta[shift + j] <<
5072                                                         (CHAR_BIT * j);
5073                         else
5074                                 reta |= r & (IXGBE_8_BIT_MASK <<
5075                                                 (CHAR_BIT * j));
5076                 }
5077                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5078         }
5079         adapter->rss_reta_updated = 1;
5080
5081         return 0;
5082 }
5083
5084 static int
5085 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5086                          struct rte_eth_rss_reta_entry64 *reta_conf,
5087                          uint16_t reta_size)
5088 {
5089         uint16_t i, sp_reta_size;
5090         uint8_t j, mask;
5091         uint32_t reta;
5092         uint16_t idx, shift;
5093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5094         uint32_t reta_reg;
5095
5096         PMD_INIT_FUNC_TRACE();
5097         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5098         if (reta_size != sp_reta_size) {
5099                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5100                         "(%d) doesn't match the number hardware can supported "
5101                         "(%d)", reta_size, sp_reta_size);
5102                 return -EINVAL;
5103         }
5104
5105         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5106                 idx = i / RTE_RETA_GROUP_SIZE;
5107                 shift = i % RTE_RETA_GROUP_SIZE;
5108                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5109                                                 IXGBE_4_BIT_MASK);
5110                 if (!mask)
5111                         continue;
5112
5113                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5114                 reta = IXGBE_READ_REG(hw, reta_reg);
5115                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5116                         if (mask & (0x1 << j))
5117                                 reta_conf[idx].reta[shift + j] =
5118                                         ((reta >> (CHAR_BIT * j)) &
5119                                                 IXGBE_8_BIT_MASK);
5120                 }
5121         }
5122
5123         return 0;
5124 }
5125
5126 static int
5127 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5128                                 uint32_t index, uint32_t pool)
5129 {
5130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131         uint32_t enable_addr = 1;
5132
5133         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5134                              pool, enable_addr);
5135 }
5136
5137 static void
5138 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5139 {
5140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5141
5142         ixgbe_clear_rar(hw, index);
5143 }
5144
5145 static int
5146 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5147 {
5148         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5149
5150         ixgbe_remove_rar(dev, 0);
5151         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5152
5153         return 0;
5154 }
5155
5156 static bool
5157 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5158 {
5159         if (strcmp(dev->device->driver->name, drv->driver.name))
5160                 return false;
5161
5162         return true;
5163 }
5164
5165 bool
5166 is_ixgbe_supported(struct rte_eth_dev *dev)
5167 {
5168         return is_device_supported(dev, &rte_ixgbe_pmd);
5169 }
5170
5171 static int
5172 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5173 {
5174         uint32_t hlreg0;
5175         uint32_t maxfrs;
5176         struct ixgbe_hw *hw;
5177         struct rte_eth_dev_info dev_info;
5178         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5179         struct rte_eth_dev_data *dev_data = dev->data;
5180         int ret;
5181
5182         ret = ixgbe_dev_info_get(dev, &dev_info);
5183         if (ret != 0)
5184                 return ret;
5185
5186         /* check that mtu is within the allowed range */
5187         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5188                 return -EINVAL;
5189
5190         /* If device is started, refuse mtu that requires the support of
5191          * scattered packets when this feature has not been enabled before.
5192          */
5193         if (dev_data->dev_started && !dev_data->scattered_rx &&
5194             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5195              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5196                 PMD_INIT_LOG(ERR, "Stop port first.");
5197                 return -EINVAL;
5198         }
5199
5200         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5202
5203         /* switch to jumbo mode if needed */
5204         if (frame_size > RTE_ETHER_MAX_LEN) {
5205                 dev->data->dev_conf.rxmode.offloads |=
5206                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5207                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5208         } else {
5209                 dev->data->dev_conf.rxmode.offloads &=
5210                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5211                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5212         }
5213         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5214
5215         /* update max frame size */
5216         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5217
5218         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5219         maxfrs &= 0x0000FFFF;
5220         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5221         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5222
5223         return 0;
5224 }
5225
5226 /*
5227  * Virtual Function operations
5228  */
5229 static void
5230 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5231 {
5232         struct ixgbe_interrupt *intr =
5233                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5234         struct ixgbe_hw *hw =
5235                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5236
5237         PMD_INIT_FUNC_TRACE();
5238
5239         /* Clear interrupt mask to stop from interrupts being generated */
5240         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5241
5242         IXGBE_WRITE_FLUSH(hw);
5243
5244         /* Clear mask value. */
5245         intr->mask = 0;
5246 }
5247
5248 static void
5249 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5250 {
5251         struct ixgbe_interrupt *intr =
5252                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5253         struct ixgbe_hw *hw =
5254                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5255
5256         PMD_INIT_FUNC_TRACE();
5257
5258         /* VF enable interrupt autoclean */
5259         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5260         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5261         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5262
5263         IXGBE_WRITE_FLUSH(hw);
5264
5265         /* Save IXGBE_VTEIMS value to mask. */
5266         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5267 }
5268
5269 static int
5270 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5271 {
5272         struct rte_eth_conf *conf = &dev->data->dev_conf;
5273         struct ixgbe_adapter *adapter = dev->data->dev_private;
5274
5275         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5276                      dev->data->port_id);
5277
5278         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5279                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5280
5281         /*
5282          * VF has no ability to enable/disable HW CRC
5283          * Keep the persistent behavior the same as Host PF
5284          */
5285 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5286         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5287                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5288                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5289         }
5290 #else
5291         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5292                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5293                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5294         }
5295 #endif
5296
5297         /*
5298          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5299          * allocation or vector Rx preconditions we will reset it.
5300          */
5301         adapter->rx_bulk_alloc_allowed = true;
5302         adapter->rx_vec_allowed = true;
5303
5304         return 0;
5305 }
5306
5307 static int
5308 ixgbevf_dev_start(struct rte_eth_dev *dev)
5309 {
5310         struct ixgbe_hw *hw =
5311                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5312         uint32_t intr_vector = 0;
5313         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5314         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5315
5316         int err, mask = 0;
5317
5318         PMD_INIT_FUNC_TRACE();
5319
5320         /* Stop the link setup handler before resetting the HW. */
5321         ixgbe_dev_wait_setup_link_complete(dev, 0);
5322
5323         err = hw->mac.ops.reset_hw(hw);
5324
5325         /**
5326          * In this case, reuses the MAC address assigned by VF
5327          * initialization.
5328          */
5329         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5330                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5331                 return err;
5332         }
5333
5334         hw->mac.get_link_status = true;
5335
5336         /* negotiate mailbox API version to use with the PF. */
5337         ixgbevf_negotiate_api(hw);
5338
5339         ixgbevf_dev_tx_init(dev);
5340
5341         /* This can fail when allocating mbufs for descriptor rings */
5342         err = ixgbevf_dev_rx_init(dev);
5343         if (err) {
5344                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5345                 ixgbe_dev_clear_queues(dev);
5346                 return err;
5347         }
5348
5349         /* Set vfta */
5350         ixgbevf_set_vfta_all(dev, 1);
5351
5352         /* Set HW strip */
5353         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5354                 ETH_VLAN_EXTEND_MASK;
5355         err = ixgbevf_vlan_offload_config(dev, mask);
5356         if (err) {
5357                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5358                 ixgbe_dev_clear_queues(dev);
5359                 return err;
5360         }
5361
5362         ixgbevf_dev_rxtx_start(dev);
5363
5364         /* check and configure queue intr-vector mapping */
5365         if (rte_intr_cap_multiple(intr_handle) &&
5366             dev->data->dev_conf.intr_conf.rxq) {
5367                 /* According to datasheet, only vector 0/1/2 can be used,
5368                  * now only one vector is used for Rx queue
5369                  */
5370                 intr_vector = 1;
5371                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5372                         return -1;
5373         }
5374
5375         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5376                 intr_handle->intr_vec =
5377                         rte_zmalloc("intr_vec",
5378                                     dev->data->nb_rx_queues * sizeof(int), 0);
5379                 if (intr_handle->intr_vec == NULL) {
5380                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5381                                      " intr_vec", dev->data->nb_rx_queues);
5382                         return -ENOMEM;
5383                 }
5384         }
5385         ixgbevf_configure_msix(dev);
5386
5387         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5388          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5389          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5390          * is not cleared, it will fail when following rte_intr_enable( ) tries
5391          * to map Rx queue interrupt to other VFIO vectors.
5392          * So clear uio/vfio intr/evevnfd first to avoid failure.
5393          */
5394         rte_intr_disable(intr_handle);
5395
5396         rte_intr_enable(intr_handle);
5397
5398         /* Re-enable interrupt for VF */
5399         ixgbevf_intr_enable(dev);
5400
5401         /*
5402          * Update link status right before return, because it may
5403          * start link configuration process in a separate thread.
5404          */
5405         ixgbevf_dev_link_update(dev, 0);
5406
5407         hw->adapter_stopped = false;
5408
5409         return 0;
5410 }
5411
5412 static int
5413 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5414 {
5415         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5416         struct ixgbe_adapter *adapter = dev->data->dev_private;
5417         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5418         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5419
5420         if (hw->adapter_stopped)
5421                 return 0;
5422
5423         PMD_INIT_FUNC_TRACE();
5424
5425         ixgbe_dev_wait_setup_link_complete(dev, 0);
5426
5427         ixgbevf_intr_disable(dev);
5428
5429         dev->data->dev_started = 0;
5430         hw->adapter_stopped = 1;
5431         ixgbe_stop_adapter(hw);
5432
5433         /*
5434           * Clear what we set, but we still keep shadow_vfta to
5435           * restore after device starts
5436           */
5437         ixgbevf_set_vfta_all(dev, 0);
5438
5439         /* Clear stored conf */
5440         dev->data->scattered_rx = 0;
5441
5442         ixgbe_dev_clear_queues(dev);
5443
5444         /* Clean datapath event and queue/vec mapping */
5445         rte_intr_efd_disable(intr_handle);
5446         if (intr_handle->intr_vec != NULL) {
5447                 rte_free(intr_handle->intr_vec);
5448                 intr_handle->intr_vec = NULL;
5449         }
5450
5451         adapter->rss_reta_updated = 0;
5452
5453         return 0;
5454 }
5455
5456 static int
5457 ixgbevf_dev_close(struct rte_eth_dev *dev)
5458 {
5459         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5460         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5461         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5462         int ret;
5463
5464         PMD_INIT_FUNC_TRACE();
5465         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5466                 return 0;
5467
5468         ixgbe_reset_hw(hw);
5469
5470         ret = ixgbevf_dev_stop(dev);
5471
5472         ixgbe_dev_free_queues(dev);
5473
5474         /**
5475          * Remove the VF MAC address ro ensure
5476          * that the VF traffic goes to the PF
5477          * after stop, close and detach of the VF
5478          **/
5479         ixgbevf_remove_mac_addr(dev, 0);
5480
5481         rte_intr_disable(intr_handle);
5482         rte_intr_callback_unregister(intr_handle,
5483                                      ixgbevf_dev_interrupt_handler, dev);
5484
5485         return ret;
5486 }
5487
5488 /*
5489  * Reset VF device
5490  */
5491 static int
5492 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5493 {
5494         int ret;
5495
5496         ret = eth_ixgbevf_dev_uninit(dev);
5497         if (ret)
5498                 return ret;
5499
5500         ret = eth_ixgbevf_dev_init(dev);
5501
5502         return ret;
5503 }
5504
5505 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5506 {
5507         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5508         struct ixgbe_vfta *shadow_vfta =
5509                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5510         int i = 0, j = 0, vfta = 0, mask = 1;
5511
5512         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5513                 vfta = shadow_vfta->vfta[i];
5514                 if (vfta) {
5515                         mask = 1;
5516                         for (j = 0; j < 32; j++) {
5517                                 if (vfta & mask)
5518                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5519                                                        on, false);
5520                                 mask <<= 1;
5521                         }
5522                 }
5523         }
5524
5525 }
5526
5527 static int
5528 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5529 {
5530         struct ixgbe_hw *hw =
5531                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5532         struct ixgbe_vfta *shadow_vfta =
5533                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5534         uint32_t vid_idx = 0;
5535         uint32_t vid_bit = 0;
5536         int ret = 0;
5537
5538         PMD_INIT_FUNC_TRACE();
5539
5540         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5541         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5542         if (ret) {
5543                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5544                 return ret;
5545         }
5546         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5547         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5548
5549         /* Save what we set and retore it after device reset */
5550         if (on)
5551                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5552         else
5553                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5554
5555         return 0;
5556 }
5557
5558 static void
5559 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5560 {
5561         struct ixgbe_hw *hw =
5562                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5563         uint32_t ctrl;
5564
5565         PMD_INIT_FUNC_TRACE();
5566
5567         if (queue >= hw->mac.max_rx_queues)
5568                 return;
5569
5570         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5571         if (on)
5572                 ctrl |= IXGBE_RXDCTL_VME;
5573         else
5574                 ctrl &= ~IXGBE_RXDCTL_VME;
5575         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5576
5577         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5578 }
5579
5580 static int
5581 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5582 {
5583         struct ixgbe_rx_queue *rxq;
5584         uint16_t i;
5585         int on = 0;
5586
5587         /* VF function only support hw strip feature, others are not support */
5588         if (mask & ETH_VLAN_STRIP_MASK) {
5589                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5590                         rxq = dev->data->rx_queues[i];
5591                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5592                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5593                 }
5594         }
5595
5596         return 0;
5597 }
5598
5599 static int
5600 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5601 {
5602         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5603
5604         ixgbevf_vlan_offload_config(dev, mask);
5605
5606         return 0;
5607 }
5608
5609 int
5610 ixgbe_vt_check(struct ixgbe_hw *hw)
5611 {
5612         uint32_t reg_val;
5613
5614         /* if Virtualization Technology is enabled */
5615         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5616         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5617                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5618                 return -1;
5619         }
5620
5621         return 0;
5622 }
5623
5624 static uint32_t
5625 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5626 {
5627         uint32_t vector = 0;
5628
5629         switch (hw->mac.mc_filter_type) {
5630         case 0:   /* use bits [47:36] of the address */
5631                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5632                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5633                 break;
5634         case 1:   /* use bits [46:35] of the address */
5635                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5636                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5637                 break;
5638         case 2:   /* use bits [45:34] of the address */
5639                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5640                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5641                 break;
5642         case 3:   /* use bits [43:32] of the address */
5643                 vector = ((uc_addr->addr_bytes[4]) |
5644                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5645                 break;
5646         default:  /* Invalid mc_filter_type */
5647                 break;
5648         }
5649
5650         /* vector can only be 12-bits or boundary will be exceeded */
5651         vector &= 0xFFF;
5652         return vector;
5653 }
5654
5655 static int
5656 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5657                         struct rte_ether_addr *mac_addr, uint8_t on)
5658 {
5659         uint32_t vector;
5660         uint32_t uta_idx;
5661         uint32_t reg_val;
5662         uint32_t uta_shift;
5663         uint32_t rc;
5664         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5665         const uint32_t ixgbe_uta_bit_shift = 5;
5666         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5667         const uint32_t bit1 = 0x1;
5668
5669         struct ixgbe_hw *hw =
5670                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5671         struct ixgbe_uta_info *uta_info =
5672                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5673
5674         /* The UTA table only exists on 82599 hardware and newer */
5675         if (hw->mac.type < ixgbe_mac_82599EB)
5676                 return -ENOTSUP;
5677
5678         vector = ixgbe_uta_vector(hw, mac_addr);
5679         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5680         uta_shift = vector & ixgbe_uta_bit_mask;
5681
5682         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5683         if (rc == on)
5684                 return 0;
5685
5686         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5687         if (on) {
5688                 uta_info->uta_in_use++;
5689                 reg_val |= (bit1 << uta_shift);
5690                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5691         } else {
5692                 uta_info->uta_in_use--;
5693                 reg_val &= ~(bit1 << uta_shift);
5694                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5695         }
5696
5697         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5698
5699         if (uta_info->uta_in_use > 0)
5700                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5701                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5702         else
5703                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5704
5705         return 0;
5706 }
5707
5708 static int
5709 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5710 {
5711         int i;
5712         struct ixgbe_hw *hw =
5713                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5714         struct ixgbe_uta_info *uta_info =
5715                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5716
5717         /* The UTA table only exists on 82599 hardware and newer */
5718         if (hw->mac.type < ixgbe_mac_82599EB)
5719                 return -ENOTSUP;
5720
5721         if (on) {
5722                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5723                         uta_info->uta_shadow[i] = ~0;
5724                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5725                 }
5726         } else {
5727                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5728                         uta_info->uta_shadow[i] = 0;
5729                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5730                 }
5731         }
5732         return 0;
5733
5734 }
5735
5736 uint32_t
5737 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5738 {
5739         uint32_t new_val = orig_val;
5740
5741         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5742                 new_val |= IXGBE_VMOLR_AUPE;
5743         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5744                 new_val |= IXGBE_VMOLR_ROMPE;
5745         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5746                 new_val |= IXGBE_VMOLR_ROPE;
5747         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5748                 new_val |= IXGBE_VMOLR_BAM;
5749         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5750                 new_val |= IXGBE_VMOLR_MPE;
5751
5752         return new_val;
5753 }
5754
5755 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5756 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5757 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5758 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5759 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5760         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5761         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5762
5763 static int
5764 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5765                       struct rte_eth_mirror_conf *mirror_conf,
5766                       uint8_t rule_id, uint8_t on)
5767 {
5768         uint32_t mr_ctl, vlvf;
5769         uint32_t mp_lsb = 0;
5770         uint32_t mv_msb = 0;
5771         uint32_t mv_lsb = 0;
5772         uint32_t mp_msb = 0;
5773         uint8_t i = 0;
5774         int reg_index = 0;
5775         uint64_t vlan_mask = 0;
5776
5777         const uint8_t pool_mask_offset = 32;
5778         const uint8_t vlan_mask_offset = 32;
5779         const uint8_t dst_pool_offset = 8;
5780         const uint8_t rule_mr_offset  = 4;
5781         const uint8_t mirror_rule_mask = 0x0F;
5782
5783         struct ixgbe_mirror_info *mr_info =
5784                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5785         struct ixgbe_hw *hw =
5786                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5787         uint8_t mirror_type = 0;
5788
5789         if (ixgbe_vt_check(hw) < 0)
5790                 return -ENOTSUP;
5791
5792         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5793                 return -EINVAL;
5794
5795         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5796                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5797                             mirror_conf->rule_type);
5798                 return -EINVAL;
5799         }
5800
5801         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5802                 mirror_type |= IXGBE_MRCTL_VLME;
5803                 /* Check if vlan id is valid and find conresponding VLAN ID
5804                  * index in VLVF
5805                  */
5806                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5807                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5808                                 /* search vlan id related pool vlan filter
5809                                  * index
5810                                  */
5811                                 reg_index = ixgbe_find_vlvf_slot(
5812                                                 hw,
5813                                                 mirror_conf->vlan.vlan_id[i],
5814                                                 false);
5815                                 if (reg_index < 0)
5816                                         return -EINVAL;
5817                                 vlvf = IXGBE_READ_REG(hw,
5818                                                       IXGBE_VLVF(reg_index));
5819                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5820                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5821                                       mirror_conf->vlan.vlan_id[i]))
5822                                         vlan_mask |= (1ULL << reg_index);
5823                                 else
5824                                         return -EINVAL;
5825                         }
5826                 }
5827
5828                 if (on) {
5829                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5830                         mv_msb = vlan_mask >> vlan_mask_offset;
5831
5832                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5833                                                 mirror_conf->vlan.vlan_mask;
5834                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5835                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5836                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5837                                                 mirror_conf->vlan.vlan_id[i];
5838                         }
5839                 } else {
5840                         mv_lsb = 0;
5841                         mv_msb = 0;
5842                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5843                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5844                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5845                 }
5846         }
5847
5848         /**
5849          * if enable pool mirror, write related pool mask register,if disable
5850          * pool mirror, clear PFMRVM register
5851          */
5852         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5853                 mirror_type |= IXGBE_MRCTL_VPME;
5854                 if (on) {
5855                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5856                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5857                         mr_info->mr_conf[rule_id].pool_mask =
5858                                         mirror_conf->pool_mask;
5859
5860                 } else {
5861                         mp_lsb = 0;
5862                         mp_msb = 0;
5863                         mr_info->mr_conf[rule_id].pool_mask = 0;
5864                 }
5865         }
5866         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5867                 mirror_type |= IXGBE_MRCTL_UPME;
5868         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5869                 mirror_type |= IXGBE_MRCTL_DPME;
5870
5871         /* read  mirror control register and recalculate it */
5872         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5873
5874         if (on) {
5875                 mr_ctl |= mirror_type;
5876                 mr_ctl &= mirror_rule_mask;
5877                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5878         } else {
5879                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5880         }
5881
5882         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5883         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5884
5885         /* write mirrror control  register */
5886         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5887
5888         /* write pool mirrror control  register */
5889         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5890                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5891                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5892                                 mp_msb);
5893         }
5894         /* write VLAN mirrror control  register */
5895         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5896                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5897                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5898                                 mv_msb);
5899         }
5900
5901         return 0;
5902 }
5903
5904 static int
5905 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5906 {
5907         int mr_ctl = 0;
5908         uint32_t lsb_val = 0;
5909         uint32_t msb_val = 0;
5910         const uint8_t rule_mr_offset = 4;
5911
5912         struct ixgbe_hw *hw =
5913                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5914         struct ixgbe_mirror_info *mr_info =
5915                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5916
5917         if (ixgbe_vt_check(hw) < 0)
5918                 return -ENOTSUP;
5919
5920         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5921                 return -EINVAL;
5922
5923         memset(&mr_info->mr_conf[rule_id], 0,
5924                sizeof(struct rte_eth_mirror_conf));
5925
5926         /* clear PFVMCTL register */
5927         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5928
5929         /* clear pool mask register */
5930         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5931         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5932
5933         /* clear vlan mask register */
5934         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5935         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5936
5937         return 0;
5938 }
5939
5940 static int
5941 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5942 {
5943         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5944         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5945         struct ixgbe_interrupt *intr =
5946                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5947         struct ixgbe_hw *hw =
5948                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5949         uint32_t vec = IXGBE_MISC_VEC_ID;
5950
5951         if (rte_intr_allow_others(intr_handle))
5952                 vec = IXGBE_RX_VEC_START;
5953         intr->mask |= (1 << vec);
5954         RTE_SET_USED(queue_id);
5955         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5956
5957         rte_intr_ack(intr_handle);
5958
5959         return 0;
5960 }
5961
5962 static int
5963 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5964 {
5965         struct ixgbe_interrupt *intr =
5966                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5967         struct ixgbe_hw *hw =
5968                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5969         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5970         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5971         uint32_t vec = IXGBE_MISC_VEC_ID;
5972
5973         if (rte_intr_allow_others(intr_handle))
5974                 vec = IXGBE_RX_VEC_START;
5975         intr->mask &= ~(1 << vec);
5976         RTE_SET_USED(queue_id);
5977         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5978
5979         return 0;
5980 }
5981
5982 static int
5983 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5984 {
5985         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5986         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5987         uint32_t mask;
5988         struct ixgbe_hw *hw =
5989                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5990         struct ixgbe_interrupt *intr =
5991                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5992
5993         if (queue_id < 16) {
5994                 ixgbe_disable_intr(hw);
5995                 intr->mask |= (1 << queue_id);
5996                 ixgbe_enable_intr(dev);
5997         } else if (queue_id < 32) {
5998                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5999                 mask &= (1 << queue_id);
6000                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6001         } else if (queue_id < 64) {
6002                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6003                 mask &= (1 << (queue_id - 32));
6004                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6005         }
6006         rte_intr_ack(intr_handle);
6007
6008         return 0;
6009 }
6010
6011 static int
6012 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6013 {
6014         uint32_t mask;
6015         struct ixgbe_hw *hw =
6016                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6017         struct ixgbe_interrupt *intr =
6018                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6019
6020         if (queue_id < 16) {
6021                 ixgbe_disable_intr(hw);
6022                 intr->mask &= ~(1 << queue_id);
6023                 ixgbe_enable_intr(dev);
6024         } else if (queue_id < 32) {
6025                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6026                 mask &= ~(1 << queue_id);
6027                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6028         } else if (queue_id < 64) {
6029                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6030                 mask &= ~(1 << (queue_id - 32));
6031                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6032         }
6033
6034         return 0;
6035 }
6036
6037 static void
6038 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6039                      uint8_t queue, uint8_t msix_vector)
6040 {
6041         uint32_t tmp, idx;
6042
6043         if (direction == -1) {
6044                 /* other causes */
6045                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6046                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6047                 tmp &= ~0xFF;
6048                 tmp |= msix_vector;
6049                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6050         } else {
6051                 /* rx or tx cause */
6052                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6053                 idx = ((16 * (queue & 1)) + (8 * direction));
6054                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6055                 tmp &= ~(0xFF << idx);
6056                 tmp |= (msix_vector << idx);
6057                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6058         }
6059 }
6060
6061 /**
6062  * set the IVAR registers, mapping interrupt causes to vectors
6063  * @param hw
6064  *  pointer to ixgbe_hw struct
6065  * @direction
6066  *  0 for Rx, 1 for Tx, -1 for other causes
6067  * @queue
6068  *  queue to map the corresponding interrupt to
6069  * @msix_vector
6070  *  the vector to map to the corresponding queue
6071  */
6072 static void
6073 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6074                    uint8_t queue, uint8_t msix_vector)
6075 {
6076         uint32_t tmp, idx;
6077
6078         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6079         if (hw->mac.type == ixgbe_mac_82598EB) {
6080                 if (direction == -1)
6081                         direction = 0;
6082                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6083                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6084                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6085                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6086                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6087         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6088                         (hw->mac.type == ixgbe_mac_X540) ||
6089                         (hw->mac.type == ixgbe_mac_X550) ||
6090                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6091                 if (direction == -1) {
6092                         /* other causes */
6093                         idx = ((queue & 1) * 8);
6094                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6095                         tmp &= ~(0xFF << idx);
6096                         tmp |= (msix_vector << idx);
6097                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6098                 } else {
6099                         /* rx or tx causes */
6100                         idx = ((16 * (queue & 1)) + (8 * direction));
6101                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6102                         tmp &= ~(0xFF << idx);
6103                         tmp |= (msix_vector << idx);
6104                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6105                 }
6106         }
6107 }
6108
6109 static void
6110 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6111 {
6112         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6113         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6114         struct ixgbe_hw *hw =
6115                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6116         uint32_t q_idx;
6117         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6118         uint32_t base = IXGBE_MISC_VEC_ID;
6119
6120         /* Configure VF other cause ivar */
6121         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6122
6123         /* won't configure msix register if no mapping is done
6124          * between intr vector and event fd.
6125          */
6126         if (!rte_intr_dp_is_en(intr_handle))
6127                 return;
6128
6129         if (rte_intr_allow_others(intr_handle)) {
6130                 base = IXGBE_RX_VEC_START;
6131                 vector_idx = IXGBE_RX_VEC_START;
6132         }
6133
6134         /* Configure all RX queues of VF */
6135         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6136                 /* Force all queue use vector 0,
6137                  * as IXGBE_VF_MAXMSIVECOTR = 1
6138                  */
6139                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6140                 intr_handle->intr_vec[q_idx] = vector_idx;
6141                 if (vector_idx < base + intr_handle->nb_efd - 1)
6142                         vector_idx++;
6143         }
6144
6145         /* As RX queue setting above show, all queues use the vector 0.
6146          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6147          */
6148         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6149                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6150                         | IXGBE_EITR_CNT_WDIS);
6151 }
6152
6153 /**
6154  * Sets up the hardware to properly generate MSI-X interrupts
6155  * @hw
6156  *  board private structure
6157  */
6158 static void
6159 ixgbe_configure_msix(struct rte_eth_dev *dev)
6160 {
6161         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6162         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6163         struct ixgbe_hw *hw =
6164                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6165         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6166         uint32_t vec = IXGBE_MISC_VEC_ID;
6167         uint32_t mask;
6168         uint32_t gpie;
6169
6170         /* won't configure msix register if no mapping is done
6171          * between intr vector and event fd
6172          * but if misx has been enabled already, need to configure
6173          * auto clean, auto mask and throttling.
6174          */
6175         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6176         if (!rte_intr_dp_is_en(intr_handle) &&
6177             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6178                 return;
6179
6180         if (rte_intr_allow_others(intr_handle))
6181                 vec = base = IXGBE_RX_VEC_START;
6182
6183         /* setup GPIE for MSI-x mode */
6184         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6185         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6186                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6187         /* auto clearing and auto setting corresponding bits in EIMS
6188          * when MSI-X interrupt is triggered
6189          */
6190         if (hw->mac.type == ixgbe_mac_82598EB) {
6191                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6192         } else {
6193                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6194                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6195         }
6196         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6197
6198         /* Populate the IVAR table and set the ITR values to the
6199          * corresponding register.
6200          */
6201         if (rte_intr_dp_is_en(intr_handle)) {
6202                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6203                         queue_id++) {
6204                         /* by default, 1:1 mapping */
6205                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6206                         intr_handle->intr_vec[queue_id] = vec;
6207                         if (vec < base + intr_handle->nb_efd - 1)
6208                                 vec++;
6209                 }
6210
6211                 switch (hw->mac.type) {
6212                 case ixgbe_mac_82598EB:
6213                         ixgbe_set_ivar_map(hw, -1,
6214                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6215                                            IXGBE_MISC_VEC_ID);
6216                         break;
6217                 case ixgbe_mac_82599EB:
6218                 case ixgbe_mac_X540:
6219                 case ixgbe_mac_X550:
6220                 case ixgbe_mac_X550EM_x:
6221                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6222                         break;
6223                 default:
6224                         break;
6225                 }
6226         }
6227         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6228                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6229                         | IXGBE_EITR_CNT_WDIS);
6230
6231         /* set up to autoclear timer, and the vectors */
6232         mask = IXGBE_EIMS_ENABLE_MASK;
6233         mask &= ~(IXGBE_EIMS_OTHER |
6234                   IXGBE_EIMS_MAILBOX |
6235                   IXGBE_EIMS_LSC);
6236
6237         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6238 }
6239
6240 int
6241 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6242                            uint16_t queue_idx, uint16_t tx_rate)
6243 {
6244         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6245         struct rte_eth_rxmode *rxmode;
6246         uint32_t rf_dec, rf_int;
6247         uint32_t bcnrc_val;
6248         uint16_t link_speed = dev->data->dev_link.link_speed;
6249
6250         if (queue_idx >= hw->mac.max_tx_queues)
6251                 return -EINVAL;
6252
6253         if (tx_rate != 0) {
6254                 /* Calculate the rate factor values to set */
6255                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6256                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6257                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6258
6259                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6260                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6261                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6262                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6263         } else {
6264                 bcnrc_val = 0;
6265         }
6266
6267         rxmode = &dev->data->dev_conf.rxmode;
6268         /*
6269          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6270          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6271          * set as 0x4.
6272          */
6273         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6274             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6275                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6276                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6277         else
6278                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6279                         IXGBE_MMW_SIZE_DEFAULT);
6280
6281         /* Set RTTBCNRC of queue X */
6282         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6283         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6284         IXGBE_WRITE_FLUSH(hw);
6285
6286         return 0;
6287 }
6288
6289 static int
6290 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6291                      __rte_unused uint32_t index,
6292                      __rte_unused uint32_t pool)
6293 {
6294         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6295         int diag;
6296
6297         /*
6298          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6299          * operation. Trap this case to avoid exhausting the [very limited]
6300          * set of PF resources used to store VF MAC addresses.
6301          */
6302         if (memcmp(hw->mac.perm_addr, mac_addr,
6303                         sizeof(struct rte_ether_addr)) == 0)
6304                 return -1;
6305         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6306         if (diag != 0)
6307                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6308                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6309                             mac_addr->addr_bytes[0],
6310                             mac_addr->addr_bytes[1],
6311                             mac_addr->addr_bytes[2],
6312                             mac_addr->addr_bytes[3],
6313                             mac_addr->addr_bytes[4],
6314                             mac_addr->addr_bytes[5],
6315                             diag);
6316         return diag;
6317 }
6318
6319 static void
6320 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6321 {
6322         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6323         struct rte_ether_addr *perm_addr =
6324                 (struct rte_ether_addr *)hw->mac.perm_addr;
6325         struct rte_ether_addr *mac_addr;
6326         uint32_t i;
6327         int diag;
6328
6329         /*
6330          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6331          * not support the deletion of a given MAC address.
6332          * Instead, it imposes to delete all MAC addresses, then to add again
6333          * all MAC addresses with the exception of the one to be deleted.
6334          */
6335         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6336
6337         /*
6338          * Add again all MAC addresses, with the exception of the deleted one
6339          * and of the permanent MAC address.
6340          */
6341         for (i = 0, mac_addr = dev->data->mac_addrs;
6342              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6343                 /* Skip the deleted MAC address */
6344                 if (i == index)
6345                         continue;
6346                 /* Skip NULL MAC addresses */
6347                 if (rte_is_zero_ether_addr(mac_addr))
6348                         continue;
6349                 /* Skip the permanent MAC address */
6350                 if (memcmp(perm_addr, mac_addr,
6351                                 sizeof(struct rte_ether_addr)) == 0)
6352                         continue;
6353                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6354                 if (diag != 0)
6355                         PMD_DRV_LOG(ERR,
6356                                     "Adding again MAC address "
6357                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6358                                     "diag=%d",
6359                                     mac_addr->addr_bytes[0],
6360                                     mac_addr->addr_bytes[1],
6361                                     mac_addr->addr_bytes[2],
6362                                     mac_addr->addr_bytes[3],
6363                                     mac_addr->addr_bytes[4],
6364                                     mac_addr->addr_bytes[5],
6365                                     diag);
6366         }
6367 }
6368
6369 static int
6370 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6371                         struct rte_ether_addr *addr)
6372 {
6373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6374
6375         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6376
6377         return 0;
6378 }
6379
6380 int
6381 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6382                         struct rte_eth_syn_filter *filter,
6383                         bool add)
6384 {
6385         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6386         struct ixgbe_filter_info *filter_info =
6387                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6388         uint32_t syn_info;
6389         uint32_t synqf;
6390
6391         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6392                 return -EINVAL;
6393
6394         syn_info = filter_info->syn_info;
6395
6396         if (add) {
6397                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6398                         return -EINVAL;
6399                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6400                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6401
6402                 if (filter->hig_pri)
6403                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6404                 else
6405                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6406         } else {
6407                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6408                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6409                         return -ENOENT;
6410                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6411         }
6412
6413         filter_info->syn_info = synqf;
6414         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6415         IXGBE_WRITE_FLUSH(hw);
6416         return 0;
6417 }
6418
6419 static int
6420 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6421                         struct rte_eth_syn_filter *filter)
6422 {
6423         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6424         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6425
6426         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6427                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6428                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6429                 return 0;
6430         }
6431         return -ENOENT;
6432 }
6433
6434 static int
6435 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6436                         enum rte_filter_op filter_op,
6437                         void *arg)
6438 {
6439         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6440         int ret;
6441
6442         MAC_TYPE_FILTER_SUP(hw->mac.type);
6443
6444         if (filter_op == RTE_ETH_FILTER_NOP)
6445                 return 0;
6446
6447         if (arg == NULL) {
6448                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6449                             filter_op);
6450                 return -EINVAL;
6451         }
6452
6453         switch (filter_op) {
6454         case RTE_ETH_FILTER_ADD:
6455                 ret = ixgbe_syn_filter_set(dev,
6456                                 (struct rte_eth_syn_filter *)arg,
6457                                 TRUE);
6458                 break;
6459         case RTE_ETH_FILTER_DELETE:
6460                 ret = ixgbe_syn_filter_set(dev,
6461                                 (struct rte_eth_syn_filter *)arg,
6462                                 FALSE);
6463                 break;
6464         case RTE_ETH_FILTER_GET:
6465                 ret = ixgbe_syn_filter_get(dev,
6466                                 (struct rte_eth_syn_filter *)arg);
6467                 break;
6468         default:
6469                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6470                 ret = -EINVAL;
6471                 break;
6472         }
6473
6474         return ret;
6475 }
6476
6477
6478 static inline enum ixgbe_5tuple_protocol
6479 convert_protocol_type(uint8_t protocol_value)
6480 {
6481         if (protocol_value == IPPROTO_TCP)
6482                 return IXGBE_FILTER_PROTOCOL_TCP;
6483         else if (protocol_value == IPPROTO_UDP)
6484                 return IXGBE_FILTER_PROTOCOL_UDP;
6485         else if (protocol_value == IPPROTO_SCTP)
6486                 return IXGBE_FILTER_PROTOCOL_SCTP;
6487         else
6488                 return IXGBE_FILTER_PROTOCOL_NONE;
6489 }
6490
6491 /* inject a 5-tuple filter to HW */
6492 static inline void
6493 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6494                            struct ixgbe_5tuple_filter *filter)
6495 {
6496         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6497         int i;
6498         uint32_t ftqf, sdpqf;
6499         uint32_t l34timir = 0;
6500         uint8_t mask = 0xff;
6501
6502         i = filter->index;
6503
6504         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6505                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6506         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6507
6508         ftqf = (uint32_t)(filter->filter_info.proto &
6509                 IXGBE_FTQF_PROTOCOL_MASK);
6510         ftqf |= (uint32_t)((filter->filter_info.priority &
6511                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6512         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6513                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6514         if (filter->filter_info.dst_ip_mask == 0)
6515                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6516         if (filter->filter_info.src_port_mask == 0)
6517                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6518         if (filter->filter_info.dst_port_mask == 0)
6519                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6520         if (filter->filter_info.proto_mask == 0)
6521                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6522         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6523         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6524         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6525
6526         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6527         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6528         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6529         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6530
6531         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6532         l34timir |= (uint32_t)(filter->queue <<
6533                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6534         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6535 }
6536
6537 /*
6538  * add a 5tuple filter
6539  *
6540  * @param
6541  * dev: Pointer to struct rte_eth_dev.
6542  * index: the index the filter allocates.
6543  * filter: ponter to the filter that will be added.
6544  * rx_queue: the queue id the filter assigned to.
6545  *
6546  * @return
6547  *    - On success, zero.
6548  *    - On failure, a negative value.
6549  */
6550 static int
6551 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6552                         struct ixgbe_5tuple_filter *filter)
6553 {
6554         struct ixgbe_filter_info *filter_info =
6555                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6556         int i, idx, shift;
6557
6558         /*
6559          * look for an unused 5tuple filter index,
6560          * and insert the filter to list.
6561          */
6562         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6563                 idx = i / (sizeof(uint32_t) * NBBY);
6564                 shift = i % (sizeof(uint32_t) * NBBY);
6565                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6566                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6567                         filter->index = i;
6568                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6569                                           filter,
6570                                           entries);
6571                         break;
6572                 }
6573         }
6574         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6575                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6576                 return -ENOSYS;
6577         }
6578
6579         ixgbe_inject_5tuple_filter(dev, filter);
6580
6581         return 0;
6582 }
6583
6584 /*
6585  * remove a 5tuple filter
6586  *
6587  * @param
6588  * dev: Pointer to struct rte_eth_dev.
6589  * filter: the pointer of the filter will be removed.
6590  */
6591 static void
6592 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6593                         struct ixgbe_5tuple_filter *filter)
6594 {
6595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6596         struct ixgbe_filter_info *filter_info =
6597                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6598         uint16_t index = filter->index;
6599
6600         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6601                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6602         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6603         rte_free(filter);
6604
6605         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6606         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6607         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6608         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6609         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6610 }
6611
6612 static int
6613 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6614 {
6615         struct ixgbe_hw *hw;
6616         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6617         struct rte_eth_dev_data *dev_data = dev->data;
6618
6619         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6620
6621         if (mtu < RTE_ETHER_MIN_MTU ||
6622                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6623                 return -EINVAL;
6624
6625         /* If device is started, refuse mtu that requires the support of
6626          * scattered packets when this feature has not been enabled before.
6627          */
6628         if (dev_data->dev_started && !dev_data->scattered_rx &&
6629             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6630              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6631                 PMD_INIT_LOG(ERR, "Stop port first.");
6632                 return -EINVAL;
6633         }
6634
6635         /*
6636          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6637          * request of the version 2.0 of the mailbox API.
6638          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6639          * of the mailbox API.
6640          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6641          * prior to 3.11.33 which contains the following change:
6642          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6643          */
6644         ixgbevf_rlpml_set_vf(hw, max_frame);
6645
6646         /* update max frame size */
6647         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6648         return 0;
6649 }
6650
6651 static inline struct ixgbe_5tuple_filter *
6652 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6653                         struct ixgbe_5tuple_filter_info *key)
6654 {
6655         struct ixgbe_5tuple_filter *it;
6656
6657         TAILQ_FOREACH(it, filter_list, entries) {
6658                 if (memcmp(key, &it->filter_info,
6659                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6660                         return it;
6661                 }
6662         }
6663         return NULL;
6664 }
6665
6666 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6667 static inline int
6668 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6669                         struct ixgbe_5tuple_filter_info *filter_info)
6670 {
6671         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6672                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6673                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6674                 return -EINVAL;
6675
6676         switch (filter->dst_ip_mask) {
6677         case UINT32_MAX:
6678                 filter_info->dst_ip_mask = 0;
6679                 filter_info->dst_ip = filter->dst_ip;
6680                 break;
6681         case 0:
6682                 filter_info->dst_ip_mask = 1;
6683                 break;
6684         default:
6685                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6686                 return -EINVAL;
6687         }
6688
6689         switch (filter->src_ip_mask) {
6690         case UINT32_MAX:
6691                 filter_info->src_ip_mask = 0;
6692                 filter_info->src_ip = filter->src_ip;
6693                 break;
6694         case 0:
6695                 filter_info->src_ip_mask = 1;
6696                 break;
6697         default:
6698                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6699                 return -EINVAL;
6700         }
6701
6702         switch (filter->dst_port_mask) {
6703         case UINT16_MAX:
6704                 filter_info->dst_port_mask = 0;
6705                 filter_info->dst_port = filter->dst_port;
6706                 break;
6707         case 0:
6708                 filter_info->dst_port_mask = 1;
6709                 break;
6710         default:
6711                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6712                 return -EINVAL;
6713         }
6714
6715         switch (filter->src_port_mask) {
6716         case UINT16_MAX:
6717                 filter_info->src_port_mask = 0;
6718                 filter_info->src_port = filter->src_port;
6719                 break;
6720         case 0:
6721                 filter_info->src_port_mask = 1;
6722                 break;
6723         default:
6724                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6725                 return -EINVAL;
6726         }
6727
6728         switch (filter->proto_mask) {
6729         case UINT8_MAX:
6730                 filter_info->proto_mask = 0;
6731                 filter_info->proto =
6732                         convert_protocol_type(filter->proto);
6733                 break;
6734         case 0:
6735                 filter_info->proto_mask = 1;
6736                 break;
6737         default:
6738                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6739                 return -EINVAL;
6740         }
6741
6742         filter_info->priority = (uint8_t)filter->priority;
6743         return 0;
6744 }
6745
6746 /*
6747  * add or delete a ntuple filter
6748  *
6749  * @param
6750  * dev: Pointer to struct rte_eth_dev.
6751  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6752  * add: if true, add filter, if false, remove filter
6753  *
6754  * @return
6755  *    - On success, zero.
6756  *    - On failure, a negative value.
6757  */
6758 int
6759 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6760                         struct rte_eth_ntuple_filter *ntuple_filter,
6761                         bool add)
6762 {
6763         struct ixgbe_filter_info *filter_info =
6764                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6765         struct ixgbe_5tuple_filter_info filter_5tuple;
6766         struct ixgbe_5tuple_filter *filter;
6767         int ret;
6768
6769         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6770                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6771                 return -EINVAL;
6772         }
6773
6774         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6775         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6776         if (ret < 0)
6777                 return ret;
6778
6779         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6780                                          &filter_5tuple);
6781         if (filter != NULL && add) {
6782                 PMD_DRV_LOG(ERR, "filter exists.");
6783                 return -EEXIST;
6784         }
6785         if (filter == NULL && !add) {
6786                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6787                 return -ENOENT;
6788         }
6789
6790         if (add) {
6791                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6792                                 sizeof(struct ixgbe_5tuple_filter), 0);
6793                 if (filter == NULL)
6794                         return -ENOMEM;
6795                 rte_memcpy(&filter->filter_info,
6796                                  &filter_5tuple,
6797                                  sizeof(struct ixgbe_5tuple_filter_info));
6798                 filter->queue = ntuple_filter->queue;
6799                 ret = ixgbe_add_5tuple_filter(dev, filter);
6800                 if (ret < 0) {
6801                         rte_free(filter);
6802                         return ret;
6803                 }
6804         } else
6805                 ixgbe_remove_5tuple_filter(dev, filter);
6806
6807         return 0;
6808 }
6809
6810 /*
6811  * get a ntuple filter
6812  *
6813  * @param
6814  * dev: Pointer to struct rte_eth_dev.
6815  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6816  *
6817  * @return
6818  *    - On success, zero.
6819  *    - On failure, a negative value.
6820  */
6821 static int
6822 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6823                         struct rte_eth_ntuple_filter *ntuple_filter)
6824 {
6825         struct ixgbe_filter_info *filter_info =
6826                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6827         struct ixgbe_5tuple_filter_info filter_5tuple;
6828         struct ixgbe_5tuple_filter *filter;
6829         int ret;
6830
6831         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6832                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6833                 return -EINVAL;
6834         }
6835
6836         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6837         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6838         if (ret < 0)
6839                 return ret;
6840
6841         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6842                                          &filter_5tuple);
6843         if (filter == NULL) {
6844                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6845                 return -ENOENT;
6846         }
6847         ntuple_filter->queue = filter->queue;
6848         return 0;
6849 }
6850
6851 /*
6852  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6853  * @dev: pointer to rte_eth_dev structure
6854  * @filter_op:operation will be taken.
6855  * @arg: a pointer to specific structure corresponding to the filter_op
6856  *
6857  * @return
6858  *    - On success, zero.
6859  *    - On failure, a negative value.
6860  */
6861 static int
6862 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6863                                 enum rte_filter_op filter_op,
6864                                 void *arg)
6865 {
6866         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6867         int ret;
6868
6869         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6870
6871         if (filter_op == RTE_ETH_FILTER_NOP)
6872                 return 0;
6873
6874         if (arg == NULL) {
6875                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6876                             filter_op);
6877                 return -EINVAL;
6878         }
6879
6880         switch (filter_op) {
6881         case RTE_ETH_FILTER_ADD:
6882                 ret = ixgbe_add_del_ntuple_filter(dev,
6883                         (struct rte_eth_ntuple_filter *)arg,
6884                         TRUE);
6885                 break;
6886         case RTE_ETH_FILTER_DELETE:
6887                 ret = ixgbe_add_del_ntuple_filter(dev,
6888                         (struct rte_eth_ntuple_filter *)arg,
6889                         FALSE);
6890                 break;
6891         case RTE_ETH_FILTER_GET:
6892                 ret = ixgbe_get_ntuple_filter(dev,
6893                         (struct rte_eth_ntuple_filter *)arg);
6894                 break;
6895         default:
6896                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6897                 ret = -EINVAL;
6898                 break;
6899         }
6900         return ret;
6901 }
6902
6903 int
6904 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6905                         struct rte_eth_ethertype_filter *filter,
6906                         bool add)
6907 {
6908         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6909         struct ixgbe_filter_info *filter_info =
6910                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6911         uint32_t etqf = 0;
6912         uint32_t etqs = 0;
6913         int ret;
6914         struct ixgbe_ethertype_filter ethertype_filter;
6915
6916         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6917                 return -EINVAL;
6918
6919         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6920                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6921                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6922                         " ethertype filter.", filter->ether_type);
6923                 return -EINVAL;
6924         }
6925
6926         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6927                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6928                 return -EINVAL;
6929         }
6930         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6931                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6932                 return -EINVAL;
6933         }
6934
6935         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6936         if (ret >= 0 && add) {
6937                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6938                             filter->ether_type);
6939                 return -EEXIST;
6940         }
6941         if (ret < 0 && !add) {
6942                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6943                             filter->ether_type);
6944                 return -ENOENT;
6945         }
6946
6947         if (add) {
6948                 etqf = IXGBE_ETQF_FILTER_EN;
6949                 etqf |= (uint32_t)filter->ether_type;
6950                 etqs |= (uint32_t)((filter->queue <<
6951                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6952                                     IXGBE_ETQS_RX_QUEUE);
6953                 etqs |= IXGBE_ETQS_QUEUE_EN;
6954
6955                 ethertype_filter.ethertype = filter->ether_type;
6956                 ethertype_filter.etqf = etqf;
6957                 ethertype_filter.etqs = etqs;
6958                 ethertype_filter.conf = FALSE;
6959                 ret = ixgbe_ethertype_filter_insert(filter_info,
6960                                                     &ethertype_filter);
6961                 if (ret < 0) {
6962                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6963                         return -ENOSPC;
6964                 }
6965         } else {
6966                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6967                 if (ret < 0)
6968                         return -ENOSYS;
6969         }
6970         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6971         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6972         IXGBE_WRITE_FLUSH(hw);
6973
6974         return 0;
6975 }
6976
6977 static int
6978 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6979                         struct rte_eth_ethertype_filter *filter)
6980 {
6981         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6982         struct ixgbe_filter_info *filter_info =
6983                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6984         uint32_t etqf, etqs;
6985         int ret;
6986
6987         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6988         if (ret < 0) {
6989                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6990                             filter->ether_type);
6991                 return -ENOENT;
6992         }
6993
6994         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6995         if (etqf & IXGBE_ETQF_FILTER_EN) {
6996                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6997                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6998                 filter->flags = 0;
6999                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
7000                                IXGBE_ETQS_RX_QUEUE_SHIFT;
7001                 return 0;
7002         }
7003         return -ENOENT;
7004 }
7005
7006 /*
7007  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
7008  * @dev: pointer to rte_eth_dev structure
7009  * @filter_op:operation will be taken.
7010  * @arg: a pointer to specific structure corresponding to the filter_op
7011  */
7012 static int
7013 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7014                                 enum rte_filter_op filter_op,
7015                                 void *arg)
7016 {
7017         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7018         int ret;
7019
7020         MAC_TYPE_FILTER_SUP(hw->mac.type);
7021
7022         if (filter_op == RTE_ETH_FILTER_NOP)
7023                 return 0;
7024
7025         if (arg == NULL) {
7026                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7027                             filter_op);
7028                 return -EINVAL;
7029         }
7030
7031         switch (filter_op) {
7032         case RTE_ETH_FILTER_ADD:
7033                 ret = ixgbe_add_del_ethertype_filter(dev,
7034                         (struct rte_eth_ethertype_filter *)arg,
7035                         TRUE);
7036                 break;
7037         case RTE_ETH_FILTER_DELETE:
7038                 ret = ixgbe_add_del_ethertype_filter(dev,
7039                         (struct rte_eth_ethertype_filter *)arg,
7040                         FALSE);
7041                 break;
7042         case RTE_ETH_FILTER_GET:
7043                 ret = ixgbe_get_ethertype_filter(dev,
7044                         (struct rte_eth_ethertype_filter *)arg);
7045                 break;
7046         default:
7047                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7048                 ret = -EINVAL;
7049                 break;
7050         }
7051         return ret;
7052 }
7053
7054 static int
7055 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7056                      enum rte_filter_type filter_type,
7057                      enum rte_filter_op filter_op,
7058                      void *arg)
7059 {
7060         int ret = 0;
7061
7062         switch (filter_type) {
7063         case RTE_ETH_FILTER_NTUPLE:
7064                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7065                 break;
7066         case RTE_ETH_FILTER_ETHERTYPE:
7067                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7068                 break;
7069         case RTE_ETH_FILTER_SYN:
7070                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7071                 break;
7072         case RTE_ETH_FILTER_FDIR:
7073                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7074                 break;
7075         case RTE_ETH_FILTER_L2_TUNNEL:
7076                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7077                 break;
7078         case RTE_ETH_FILTER_GENERIC:
7079                 if (filter_op != RTE_ETH_FILTER_GET)
7080                         return -EINVAL;
7081                 *(const void **)arg = &ixgbe_flow_ops;
7082                 break;
7083         default:
7084                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7085                                                         filter_type);
7086                 ret = -EINVAL;
7087                 break;
7088         }
7089
7090         return ret;
7091 }
7092
7093 static u8 *
7094 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7095                         u8 **mc_addr_ptr, u32 *vmdq)
7096 {
7097         u8 *mc_addr;
7098
7099         *vmdq = 0;
7100         mc_addr = *mc_addr_ptr;
7101         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7102         return mc_addr;
7103 }
7104
7105 static int
7106 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7107                           struct rte_ether_addr *mc_addr_set,
7108                           uint32_t nb_mc_addr)
7109 {
7110         struct ixgbe_hw *hw;
7111         u8 *mc_addr_list;
7112
7113         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7114         mc_addr_list = (u8 *)mc_addr_set;
7115         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7116                                          ixgbe_dev_addr_list_itr, TRUE);
7117 }
7118
7119 static uint64_t
7120 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7121 {
7122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7123         uint64_t systime_cycles;
7124
7125         switch (hw->mac.type) {
7126         case ixgbe_mac_X550:
7127         case ixgbe_mac_X550EM_x:
7128         case ixgbe_mac_X550EM_a:
7129                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7130                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7131                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7132                                 * NSEC_PER_SEC;
7133                 break;
7134         default:
7135                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7136                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7137                                 << 32;
7138         }
7139
7140         return systime_cycles;
7141 }
7142
7143 static uint64_t
7144 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7145 {
7146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7147         uint64_t rx_tstamp_cycles;
7148
7149         switch (hw->mac.type) {
7150         case ixgbe_mac_X550:
7151         case ixgbe_mac_X550EM_x:
7152         case ixgbe_mac_X550EM_a:
7153                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7154                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7155                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7156                                 * NSEC_PER_SEC;
7157                 break;
7158         default:
7159                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7160                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7161                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7162                                 << 32;
7163         }
7164
7165         return rx_tstamp_cycles;
7166 }
7167
7168 static uint64_t
7169 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7170 {
7171         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7172         uint64_t tx_tstamp_cycles;
7173
7174         switch (hw->mac.type) {
7175         case ixgbe_mac_X550:
7176         case ixgbe_mac_X550EM_x:
7177         case ixgbe_mac_X550EM_a:
7178                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7179                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7180                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7181                                 * NSEC_PER_SEC;
7182                 break;
7183         default:
7184                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7185                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7186                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7187                                 << 32;
7188         }
7189
7190         return tx_tstamp_cycles;
7191 }
7192
7193 static void
7194 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7195 {
7196         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7197         struct ixgbe_adapter *adapter = dev->data->dev_private;
7198         struct rte_eth_link link;
7199         uint32_t incval = 0;
7200         uint32_t shift = 0;
7201
7202         /* Get current link speed. */
7203         ixgbe_dev_link_update(dev, 1);
7204         rte_eth_linkstatus_get(dev, &link);
7205
7206         switch (link.link_speed) {
7207         case ETH_SPEED_NUM_100M:
7208                 incval = IXGBE_INCVAL_100;
7209                 shift = IXGBE_INCVAL_SHIFT_100;
7210                 break;
7211         case ETH_SPEED_NUM_1G:
7212                 incval = IXGBE_INCVAL_1GB;
7213                 shift = IXGBE_INCVAL_SHIFT_1GB;
7214                 break;
7215         case ETH_SPEED_NUM_10G:
7216         default:
7217                 incval = IXGBE_INCVAL_10GB;
7218                 shift = IXGBE_INCVAL_SHIFT_10GB;
7219                 break;
7220         }
7221
7222         switch (hw->mac.type) {
7223         case ixgbe_mac_X550:
7224         case ixgbe_mac_X550EM_x:
7225         case ixgbe_mac_X550EM_a:
7226                 /* Independent of link speed. */
7227                 incval = 1;
7228                 /* Cycles read will be interpreted as ns. */
7229                 shift = 0;
7230                 /* Fall-through */
7231         case ixgbe_mac_X540:
7232                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7233                 break;
7234         case ixgbe_mac_82599EB:
7235                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7236                 shift -= IXGBE_INCVAL_SHIFT_82599;
7237                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7238                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7239                 break;
7240         default:
7241                 /* Not supported. */
7242                 return;
7243         }
7244
7245         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7246         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7247         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7248
7249         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7250         adapter->systime_tc.cc_shift = shift;
7251         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7252
7253         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7254         adapter->rx_tstamp_tc.cc_shift = shift;
7255         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7256
7257         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7258         adapter->tx_tstamp_tc.cc_shift = shift;
7259         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7260 }
7261
7262 static int
7263 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7264 {
7265         struct ixgbe_adapter *adapter = dev->data->dev_private;
7266
7267         adapter->systime_tc.nsec += delta;
7268         adapter->rx_tstamp_tc.nsec += delta;
7269         adapter->tx_tstamp_tc.nsec += delta;
7270
7271         return 0;
7272 }
7273
7274 static int
7275 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7276 {
7277         uint64_t ns;
7278         struct ixgbe_adapter *adapter = dev->data->dev_private;
7279
7280         ns = rte_timespec_to_ns(ts);
7281         /* Set the timecounters to a new value. */
7282         adapter->systime_tc.nsec = ns;
7283         adapter->rx_tstamp_tc.nsec = ns;
7284         adapter->tx_tstamp_tc.nsec = ns;
7285
7286         return 0;
7287 }
7288
7289 static int
7290 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7291 {
7292         uint64_t ns, systime_cycles;
7293         struct ixgbe_adapter *adapter = dev->data->dev_private;
7294
7295         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7296         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7297         *ts = rte_ns_to_timespec(ns);
7298
7299         return 0;
7300 }
7301
7302 static int
7303 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7304 {
7305         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7306         uint32_t tsync_ctl;
7307         uint32_t tsauxc;
7308
7309         /* Stop the timesync system time. */
7310         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7311         /* Reset the timesync system time value. */
7312         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7313         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7314
7315         /* Enable system time for platforms where it isn't on by default. */
7316         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7317         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7318         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7319
7320         ixgbe_start_timecounters(dev);
7321
7322         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7323         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7324                         (RTE_ETHER_TYPE_1588 |
7325                          IXGBE_ETQF_FILTER_EN |
7326                          IXGBE_ETQF_1588));
7327
7328         /* Enable timestamping of received PTP packets. */
7329         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7330         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7331         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7332
7333         /* Enable timestamping of transmitted PTP packets. */
7334         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7335         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7336         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7337
7338         IXGBE_WRITE_FLUSH(hw);
7339
7340         return 0;
7341 }
7342
7343 static int
7344 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7345 {
7346         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7347         uint32_t tsync_ctl;
7348
7349         /* Disable timestamping of transmitted PTP packets. */
7350         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7351         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7352         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7353
7354         /* Disable timestamping of received PTP packets. */
7355         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7356         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7357         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7358
7359         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7360         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7361
7362         /* Stop incrementating the System Time registers. */
7363         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7364
7365         return 0;
7366 }
7367
7368 static int
7369 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7370                                  struct timespec *timestamp,
7371                                  uint32_t flags __rte_unused)
7372 {
7373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7374         struct ixgbe_adapter *adapter = dev->data->dev_private;
7375         uint32_t tsync_rxctl;
7376         uint64_t rx_tstamp_cycles;
7377         uint64_t ns;
7378
7379         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7380         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7381                 return -EINVAL;
7382
7383         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7384         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7385         *timestamp = rte_ns_to_timespec(ns);
7386
7387         return  0;
7388 }
7389
7390 static int
7391 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7392                                  struct timespec *timestamp)
7393 {
7394         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7395         struct ixgbe_adapter *adapter = dev->data->dev_private;
7396         uint32_t tsync_txctl;
7397         uint64_t tx_tstamp_cycles;
7398         uint64_t ns;
7399
7400         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7401         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7402                 return -EINVAL;
7403
7404         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7405         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7406         *timestamp = rte_ns_to_timespec(ns);
7407
7408         return 0;
7409 }
7410
7411 static int
7412 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7413 {
7414         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7415         int count = 0;
7416         int g_ind = 0;
7417         const struct reg_info *reg_group;
7418         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7419                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7420
7421         while ((reg_group = reg_set[g_ind++]))
7422                 count += ixgbe_regs_group_count(reg_group);
7423
7424         return count;
7425 }
7426
7427 static int
7428 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7429 {
7430         int count = 0;
7431         int g_ind = 0;
7432         const struct reg_info *reg_group;
7433
7434         while ((reg_group = ixgbevf_regs[g_ind++]))
7435                 count += ixgbe_regs_group_count(reg_group);
7436
7437         return count;
7438 }
7439
7440 static int
7441 ixgbe_get_regs(struct rte_eth_dev *dev,
7442               struct rte_dev_reg_info *regs)
7443 {
7444         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7445         uint32_t *data = regs->data;
7446         int g_ind = 0;
7447         int count = 0;
7448         const struct reg_info *reg_group;
7449         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7450                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7451
7452         if (data == NULL) {
7453                 regs->length = ixgbe_get_reg_length(dev);
7454                 regs->width = sizeof(uint32_t);
7455                 return 0;
7456         }
7457
7458         /* Support only full register dump */
7459         if ((regs->length == 0) ||
7460             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7461                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7462                         hw->device_id;
7463                 while ((reg_group = reg_set[g_ind++]))
7464                         count += ixgbe_read_regs_group(dev, &data[count],
7465                                 reg_group);
7466                 return 0;
7467         }
7468
7469         return -ENOTSUP;
7470 }
7471
7472 static int
7473 ixgbevf_get_regs(struct rte_eth_dev *dev,
7474                 struct rte_dev_reg_info *regs)
7475 {
7476         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7477         uint32_t *data = regs->data;
7478         int g_ind = 0;
7479         int count = 0;
7480         const struct reg_info *reg_group;
7481
7482         if (data == NULL) {
7483                 regs->length = ixgbevf_get_reg_length(dev);
7484                 regs->width = sizeof(uint32_t);
7485                 return 0;
7486         }
7487
7488         /* Support only full register dump */
7489         if ((regs->length == 0) ||
7490             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7491                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7492                         hw->device_id;
7493                 while ((reg_group = ixgbevf_regs[g_ind++]))
7494                         count += ixgbe_read_regs_group(dev, &data[count],
7495                                                       reg_group);
7496                 return 0;
7497         }
7498
7499         return -ENOTSUP;
7500 }
7501
7502 static int
7503 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7504 {
7505         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7506
7507         /* Return unit is byte count */
7508         return hw->eeprom.word_size * 2;
7509 }
7510
7511 static int
7512 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7513                 struct rte_dev_eeprom_info *in_eeprom)
7514 {
7515         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7516         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7517         uint16_t *data = in_eeprom->data;
7518         int first, length;
7519
7520         first = in_eeprom->offset >> 1;
7521         length = in_eeprom->length >> 1;
7522         if ((first > hw->eeprom.word_size) ||
7523             ((first + length) > hw->eeprom.word_size))
7524                 return -EINVAL;
7525
7526         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7527
7528         return eeprom->ops.read_buffer(hw, first, length, data);
7529 }
7530
7531 static int
7532 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7533                 struct rte_dev_eeprom_info *in_eeprom)
7534 {
7535         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7536         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7537         uint16_t *data = in_eeprom->data;
7538         int first, length;
7539
7540         first = in_eeprom->offset >> 1;
7541         length = in_eeprom->length >> 1;
7542         if ((first > hw->eeprom.word_size) ||
7543             ((first + length) > hw->eeprom.word_size))
7544                 return -EINVAL;
7545
7546         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7547
7548         return eeprom->ops.write_buffer(hw,  first, length, data);
7549 }
7550
7551 static int
7552 ixgbe_get_module_info(struct rte_eth_dev *dev,
7553                       struct rte_eth_dev_module_info *modinfo)
7554 {
7555         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7556         uint32_t status;
7557         uint8_t sff8472_rev, addr_mode;
7558         bool page_swap = false;
7559
7560         /* Check whether we support SFF-8472 or not */
7561         status = hw->phy.ops.read_i2c_eeprom(hw,
7562                                              IXGBE_SFF_SFF_8472_COMP,
7563                                              &sff8472_rev);
7564         if (status != 0)
7565                 return -EIO;
7566
7567         /* addressing mode is not supported */
7568         status = hw->phy.ops.read_i2c_eeprom(hw,
7569                                              IXGBE_SFF_SFF_8472_SWAP,
7570                                              &addr_mode);
7571         if (status != 0)
7572                 return -EIO;
7573
7574         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7575                 PMD_DRV_LOG(ERR,
7576                             "Address change required to access page 0xA2, "
7577                             "but not supported. Please report the module "
7578                             "type to the driver maintainers.");
7579                 page_swap = true;
7580         }
7581
7582         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7583                 /* We have a SFP, but it does not support SFF-8472 */
7584                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7585                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7586         } else {
7587                 /* We have a SFP which supports a revision of SFF-8472. */
7588                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7589                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7590         }
7591
7592         return 0;
7593 }
7594
7595 static int
7596 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7597                         struct rte_dev_eeprom_info *info)
7598 {
7599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7600         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7601         uint8_t databyte = 0xFF;
7602         uint8_t *data = info->data;
7603         uint32_t i = 0;
7604
7605         if (info->length == 0)
7606                 return -EINVAL;
7607
7608         for (i = info->offset; i < info->offset + info->length; i++) {
7609                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7610                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7611                 else
7612                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7613
7614                 if (status != 0)
7615                         return -EIO;
7616
7617                 data[i - info->offset] = databyte;
7618         }
7619
7620         return 0;
7621 }
7622
7623 uint16_t
7624 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7625         switch (mac_type) {
7626         case ixgbe_mac_X550:
7627         case ixgbe_mac_X550EM_x:
7628         case ixgbe_mac_X550EM_a:
7629                 return ETH_RSS_RETA_SIZE_512;
7630         case ixgbe_mac_X550_vf:
7631         case ixgbe_mac_X550EM_x_vf:
7632         case ixgbe_mac_X550EM_a_vf:
7633                 return ETH_RSS_RETA_SIZE_64;
7634         case ixgbe_mac_X540_vf:
7635         case ixgbe_mac_82599_vf:
7636                 return 0;
7637         default:
7638                 return ETH_RSS_RETA_SIZE_128;
7639         }
7640 }
7641
7642 uint32_t
7643 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7644         switch (mac_type) {
7645         case ixgbe_mac_X550:
7646         case ixgbe_mac_X550EM_x:
7647         case ixgbe_mac_X550EM_a:
7648                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7649                         return IXGBE_RETA(reta_idx >> 2);
7650                 else
7651                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7652         case ixgbe_mac_X550_vf:
7653         case ixgbe_mac_X550EM_x_vf:
7654         case ixgbe_mac_X550EM_a_vf:
7655                 return IXGBE_VFRETA(reta_idx >> 2);
7656         default:
7657                 return IXGBE_RETA(reta_idx >> 2);
7658         }
7659 }
7660
7661 uint32_t
7662 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7663         switch (mac_type) {
7664         case ixgbe_mac_X550_vf:
7665         case ixgbe_mac_X550EM_x_vf:
7666         case ixgbe_mac_X550EM_a_vf:
7667                 return IXGBE_VFMRQC;
7668         default:
7669                 return IXGBE_MRQC;
7670         }
7671 }
7672
7673 uint32_t
7674 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7675         switch (mac_type) {
7676         case ixgbe_mac_X550_vf:
7677         case ixgbe_mac_X550EM_x_vf:
7678         case ixgbe_mac_X550EM_a_vf:
7679                 return IXGBE_VFRSSRK(i);
7680         default:
7681                 return IXGBE_RSSRK(i);
7682         }
7683 }
7684
7685 bool
7686 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7687         switch (mac_type) {
7688         case ixgbe_mac_82599_vf:
7689         case ixgbe_mac_X540_vf:
7690                 return 0;
7691         default:
7692                 return 1;
7693         }
7694 }
7695
7696 static int
7697 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7698                         struct rte_eth_dcb_info *dcb_info)
7699 {
7700         struct ixgbe_dcb_config *dcb_config =
7701                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7702         struct ixgbe_dcb_tc_config *tc;
7703         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7704         uint8_t nb_tcs;
7705         uint8_t i, j;
7706
7707         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7708                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7709         else
7710                 dcb_info->nb_tcs = 1;
7711
7712         tc_queue = &dcb_info->tc_queue;
7713         nb_tcs = dcb_info->nb_tcs;
7714
7715         if (dcb_config->vt_mode) { /* vt is enabled*/
7716                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7717                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7718                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7719                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7720                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7721                         for (j = 0; j < nb_tcs; j++) {
7722                                 tc_queue->tc_rxq[0][j].base = j;
7723                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7724                                 tc_queue->tc_txq[0][j].base = j;
7725                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7726                         }
7727                 } else {
7728                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7729                                 for (j = 0; j < nb_tcs; j++) {
7730                                         tc_queue->tc_rxq[i][j].base =
7731                                                 i * nb_tcs + j;
7732                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7733                                         tc_queue->tc_txq[i][j].base =
7734                                                 i * nb_tcs + j;
7735                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7736                                 }
7737                         }
7738                 }
7739         } else { /* vt is disabled*/
7740                 struct rte_eth_dcb_rx_conf *rx_conf =
7741                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7742                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7743                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7744                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7745                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7746                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7747                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7748                         }
7749                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7750                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7751                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7752                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7753                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7754                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7755                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7756                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7757                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7758                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7759                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7760                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7761                         }
7762                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7763                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7764                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7765                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7766                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7767                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7768                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7769                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7770                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7771                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7772                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7773                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7774                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7775                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7776                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7777                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7778                 }
7779         }
7780         for (i = 0; i < dcb_info->nb_tcs; i++) {
7781                 tc = &dcb_config->tc_config[i];
7782                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7783         }
7784         return 0;
7785 }
7786
7787 /* Update e-tag ether type */
7788 static int
7789 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7790                             uint16_t ether_type)
7791 {
7792         uint32_t etag_etype;
7793
7794         if (hw->mac.type != ixgbe_mac_X550 &&
7795             hw->mac.type != ixgbe_mac_X550EM_x &&
7796             hw->mac.type != ixgbe_mac_X550EM_a) {
7797                 return -ENOTSUP;
7798         }
7799
7800         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7801         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7802         etag_etype |= ether_type;
7803         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7804         IXGBE_WRITE_FLUSH(hw);
7805
7806         return 0;
7807 }
7808
7809 /* Config l2 tunnel ether type */
7810 static int
7811 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7812                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7813 {
7814         int ret = 0;
7815         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7816         struct ixgbe_l2_tn_info *l2_tn_info =
7817                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7818
7819         if (l2_tunnel == NULL)
7820                 return -EINVAL;
7821
7822         switch (l2_tunnel->l2_tunnel_type) {
7823         case RTE_L2_TUNNEL_TYPE_E_TAG:
7824                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7825                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7826                 break;
7827         default:
7828                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7829                 ret = -EINVAL;
7830                 break;
7831         }
7832
7833         return ret;
7834 }
7835
7836 /* Enable e-tag tunnel */
7837 static int
7838 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7839 {
7840         uint32_t etag_etype;
7841
7842         if (hw->mac.type != ixgbe_mac_X550 &&
7843             hw->mac.type != ixgbe_mac_X550EM_x &&
7844             hw->mac.type != ixgbe_mac_X550EM_a) {
7845                 return -ENOTSUP;
7846         }
7847
7848         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7849         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7850         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7851         IXGBE_WRITE_FLUSH(hw);
7852
7853         return 0;
7854 }
7855
7856 /* Enable l2 tunnel */
7857 static int
7858 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7859                            enum rte_eth_tunnel_type l2_tunnel_type)
7860 {
7861         int ret = 0;
7862         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7863         struct ixgbe_l2_tn_info *l2_tn_info =
7864                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7865
7866         switch (l2_tunnel_type) {
7867         case RTE_L2_TUNNEL_TYPE_E_TAG:
7868                 l2_tn_info->e_tag_en = TRUE;
7869                 ret = ixgbe_e_tag_enable(hw);
7870                 break;
7871         default:
7872                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7873                 ret = -EINVAL;
7874                 break;
7875         }
7876
7877         return ret;
7878 }
7879
7880 /* Disable e-tag tunnel */
7881 static int
7882 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7883 {
7884         uint32_t etag_etype;
7885
7886         if (hw->mac.type != ixgbe_mac_X550 &&
7887             hw->mac.type != ixgbe_mac_X550EM_x &&
7888             hw->mac.type != ixgbe_mac_X550EM_a) {
7889                 return -ENOTSUP;
7890         }
7891
7892         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7893         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7894         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7895         IXGBE_WRITE_FLUSH(hw);
7896
7897         return 0;
7898 }
7899
7900 /* Disable l2 tunnel */
7901 static int
7902 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7903                             enum rte_eth_tunnel_type l2_tunnel_type)
7904 {
7905         int ret = 0;
7906         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7907         struct ixgbe_l2_tn_info *l2_tn_info =
7908                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7909
7910         switch (l2_tunnel_type) {
7911         case RTE_L2_TUNNEL_TYPE_E_TAG:
7912                 l2_tn_info->e_tag_en = FALSE;
7913                 ret = ixgbe_e_tag_disable(hw);
7914                 break;
7915         default:
7916                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7917                 ret = -EINVAL;
7918                 break;
7919         }
7920
7921         return ret;
7922 }
7923
7924 static int
7925 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7926                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7927 {
7928         int ret = 0;
7929         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7930         uint32_t i, rar_entries;
7931         uint32_t rar_low, rar_high;
7932
7933         if (hw->mac.type != ixgbe_mac_X550 &&
7934             hw->mac.type != ixgbe_mac_X550EM_x &&
7935             hw->mac.type != ixgbe_mac_X550EM_a) {
7936                 return -ENOTSUP;
7937         }
7938
7939         rar_entries = ixgbe_get_num_rx_addrs(hw);
7940
7941         for (i = 1; i < rar_entries; i++) {
7942                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7943                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7944                 if ((rar_high & IXGBE_RAH_AV) &&
7945                     (rar_high & IXGBE_RAH_ADTYPE) &&
7946                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7947                      l2_tunnel->tunnel_id)) {
7948                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7949                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7950
7951                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7952
7953                         return ret;
7954                 }
7955         }
7956
7957         return ret;
7958 }
7959
7960 static int
7961 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7962                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7963 {
7964         int ret = 0;
7965         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7966         uint32_t i, rar_entries;
7967         uint32_t rar_low, rar_high;
7968
7969         if (hw->mac.type != ixgbe_mac_X550 &&
7970             hw->mac.type != ixgbe_mac_X550EM_x &&
7971             hw->mac.type != ixgbe_mac_X550EM_a) {
7972                 return -ENOTSUP;
7973         }
7974
7975         /* One entry for one tunnel. Try to remove potential existing entry. */
7976         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7977
7978         rar_entries = ixgbe_get_num_rx_addrs(hw);
7979
7980         for (i = 1; i < rar_entries; i++) {
7981                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7982                 if (rar_high & IXGBE_RAH_AV) {
7983                         continue;
7984                 } else {
7985                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7986                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7987                         rar_low = l2_tunnel->tunnel_id;
7988
7989                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7990                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7991
7992                         return ret;
7993                 }
7994         }
7995
7996         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7997                      " Please remove a rule before adding a new one.");
7998         return -EINVAL;
7999 }
8000
8001 static inline struct ixgbe_l2_tn_filter *
8002 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
8003                           struct ixgbe_l2_tn_key *key)
8004 {
8005         int ret;
8006
8007         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
8008         if (ret < 0)
8009                 return NULL;
8010
8011         return l2_tn_info->hash_map[ret];
8012 }
8013
8014 static inline int
8015 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8016                           struct ixgbe_l2_tn_filter *l2_tn_filter)
8017 {
8018         int ret;
8019
8020         ret = rte_hash_add_key(l2_tn_info->hash_handle,
8021                                &l2_tn_filter->key);
8022
8023         if (ret < 0) {
8024                 PMD_DRV_LOG(ERR,
8025                             "Failed to insert L2 tunnel filter"
8026                             " to hash table %d!",
8027                             ret);
8028                 return ret;
8029         }
8030
8031         l2_tn_info->hash_map[ret] = l2_tn_filter;
8032
8033         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8034
8035         return 0;
8036 }
8037
8038 static inline int
8039 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8040                           struct ixgbe_l2_tn_key *key)
8041 {
8042         int ret;
8043         struct ixgbe_l2_tn_filter *l2_tn_filter;
8044
8045         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8046
8047         if (ret < 0) {
8048                 PMD_DRV_LOG(ERR,
8049                             "No such L2 tunnel filter to delete %d!",
8050                             ret);
8051                 return ret;
8052         }
8053
8054         l2_tn_filter = l2_tn_info->hash_map[ret];
8055         l2_tn_info->hash_map[ret] = NULL;
8056
8057         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8058         rte_free(l2_tn_filter);
8059
8060         return 0;
8061 }
8062
8063 /* Add l2 tunnel filter */
8064 int
8065 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8066                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
8067                                bool restore)
8068 {
8069         int ret;
8070         struct ixgbe_l2_tn_info *l2_tn_info =
8071                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8072         struct ixgbe_l2_tn_key key;
8073         struct ixgbe_l2_tn_filter *node;
8074
8075         if (!restore) {
8076                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8077                 key.tn_id = l2_tunnel->tunnel_id;
8078
8079                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8080
8081                 if (node) {
8082                         PMD_DRV_LOG(ERR,
8083                                     "The L2 tunnel filter already exists!");
8084                         return -EINVAL;
8085                 }
8086
8087                 node = rte_zmalloc("ixgbe_l2_tn",
8088                                    sizeof(struct ixgbe_l2_tn_filter),
8089                                    0);
8090                 if (!node)
8091                         return -ENOMEM;
8092
8093                 rte_memcpy(&node->key,
8094                                  &key,
8095                                  sizeof(struct ixgbe_l2_tn_key));
8096                 node->pool = l2_tunnel->pool;
8097                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8098                 if (ret < 0) {
8099                         rte_free(node);
8100                         return ret;
8101                 }
8102         }
8103
8104         switch (l2_tunnel->l2_tunnel_type) {
8105         case RTE_L2_TUNNEL_TYPE_E_TAG:
8106                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8107                 break;
8108         default:
8109                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8110                 ret = -EINVAL;
8111                 break;
8112         }
8113
8114         if ((!restore) && (ret < 0))
8115                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8116
8117         return ret;
8118 }
8119
8120 /* Delete l2 tunnel filter */
8121 int
8122 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8123                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8124 {
8125         int ret;
8126         struct ixgbe_l2_tn_info *l2_tn_info =
8127                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8128         struct ixgbe_l2_tn_key key;
8129
8130         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8131         key.tn_id = l2_tunnel->tunnel_id;
8132         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8133         if (ret < 0)
8134                 return ret;
8135
8136         switch (l2_tunnel->l2_tunnel_type) {
8137         case RTE_L2_TUNNEL_TYPE_E_TAG:
8138                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8139                 break;
8140         default:
8141                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8142                 ret = -EINVAL;
8143                 break;
8144         }
8145
8146         return ret;
8147 }
8148
8149 /**
8150  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8151  * @dev: pointer to rte_eth_dev structure
8152  * @filter_op:operation will be taken.
8153  * @arg: a pointer to specific structure corresponding to the filter_op
8154  */
8155 static int
8156 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8157                                   enum rte_filter_op filter_op,
8158                                   void *arg)
8159 {
8160         int ret;
8161
8162         if (filter_op == RTE_ETH_FILTER_NOP)
8163                 return 0;
8164
8165         if (arg == NULL) {
8166                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8167                             filter_op);
8168                 return -EINVAL;
8169         }
8170
8171         switch (filter_op) {
8172         case RTE_ETH_FILTER_ADD:
8173                 ret = ixgbe_dev_l2_tunnel_filter_add
8174                         (dev,
8175                          (struct rte_eth_l2_tunnel_conf *)arg,
8176                          FALSE);
8177                 break;
8178         case RTE_ETH_FILTER_DELETE:
8179                 ret = ixgbe_dev_l2_tunnel_filter_del
8180                         (dev,
8181                          (struct rte_eth_l2_tunnel_conf *)arg);
8182                 break;
8183         default:
8184                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8185                 ret = -EINVAL;
8186                 break;
8187         }
8188         return ret;
8189 }
8190
8191 static int
8192 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8193 {
8194         int ret = 0;
8195         uint32_t ctrl;
8196         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8197
8198         if (hw->mac.type != ixgbe_mac_X550 &&
8199             hw->mac.type != ixgbe_mac_X550EM_x &&
8200             hw->mac.type != ixgbe_mac_X550EM_a) {
8201                 return -ENOTSUP;
8202         }
8203
8204         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8205         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8206         if (en)
8207                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8208         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8209
8210         return ret;
8211 }
8212
8213 /* Enable l2 tunnel forwarding */
8214 static int
8215 ixgbe_dev_l2_tunnel_forwarding_enable
8216         (struct rte_eth_dev *dev,
8217          enum rte_eth_tunnel_type l2_tunnel_type)
8218 {
8219         struct ixgbe_l2_tn_info *l2_tn_info =
8220                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8221         int ret = 0;
8222
8223         switch (l2_tunnel_type) {
8224         case RTE_L2_TUNNEL_TYPE_E_TAG:
8225                 l2_tn_info->e_tag_fwd_en = TRUE;
8226                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8227                 break;
8228         default:
8229                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8230                 ret = -EINVAL;
8231                 break;
8232         }
8233
8234         return ret;
8235 }
8236
8237 /* Disable l2 tunnel forwarding */
8238 static int
8239 ixgbe_dev_l2_tunnel_forwarding_disable
8240         (struct rte_eth_dev *dev,
8241          enum rte_eth_tunnel_type l2_tunnel_type)
8242 {
8243         struct ixgbe_l2_tn_info *l2_tn_info =
8244                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8245         int ret = 0;
8246
8247         switch (l2_tunnel_type) {
8248         case RTE_L2_TUNNEL_TYPE_E_TAG:
8249                 l2_tn_info->e_tag_fwd_en = FALSE;
8250                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8251                 break;
8252         default:
8253                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8254                 ret = -EINVAL;
8255                 break;
8256         }
8257
8258         return ret;
8259 }
8260
8261 static int
8262 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8263                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8264                              bool en)
8265 {
8266         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8267         int ret = 0;
8268         uint32_t vmtir, vmvir;
8269         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8270
8271         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8272                 PMD_DRV_LOG(ERR,
8273                             "VF id %u should be less than %u",
8274                             l2_tunnel->vf_id,
8275                             pci_dev->max_vfs);
8276                 return -EINVAL;
8277         }
8278
8279         if (hw->mac.type != ixgbe_mac_X550 &&
8280             hw->mac.type != ixgbe_mac_X550EM_x &&
8281             hw->mac.type != ixgbe_mac_X550EM_a) {
8282                 return -ENOTSUP;
8283         }
8284
8285         if (en)
8286                 vmtir = l2_tunnel->tunnel_id;
8287         else
8288                 vmtir = 0;
8289
8290         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8291
8292         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8293         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8294         if (en)
8295                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8296         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8297
8298         return ret;
8299 }
8300
8301 /* Enable l2 tunnel tag insertion */
8302 static int
8303 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8304                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8305 {
8306         int ret = 0;
8307
8308         switch (l2_tunnel->l2_tunnel_type) {
8309         case RTE_L2_TUNNEL_TYPE_E_TAG:
8310                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8311                 break;
8312         default:
8313                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8314                 ret = -EINVAL;
8315                 break;
8316         }
8317
8318         return ret;
8319 }
8320
8321 /* Disable l2 tunnel tag insertion */
8322 static int
8323 ixgbe_dev_l2_tunnel_insertion_disable
8324         (struct rte_eth_dev *dev,
8325          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8326 {
8327         int ret = 0;
8328
8329         switch (l2_tunnel->l2_tunnel_type) {
8330         case RTE_L2_TUNNEL_TYPE_E_TAG:
8331                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8332                 break;
8333         default:
8334                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8335                 ret = -EINVAL;
8336                 break;
8337         }
8338
8339         return ret;
8340 }
8341
8342 static int
8343 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8344                              bool en)
8345 {
8346         int ret = 0;
8347         uint32_t qde;
8348         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8349
8350         if (hw->mac.type != ixgbe_mac_X550 &&
8351             hw->mac.type != ixgbe_mac_X550EM_x &&
8352             hw->mac.type != ixgbe_mac_X550EM_a) {
8353                 return -ENOTSUP;
8354         }
8355
8356         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8357         if (en)
8358                 qde |= IXGBE_QDE_STRIP_TAG;
8359         else
8360                 qde &= ~IXGBE_QDE_STRIP_TAG;
8361         qde &= ~IXGBE_QDE_READ;
8362         qde |= IXGBE_QDE_WRITE;
8363         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8364
8365         return ret;
8366 }
8367
8368 /* Enable l2 tunnel tag stripping */
8369 static int
8370 ixgbe_dev_l2_tunnel_stripping_enable
8371         (struct rte_eth_dev *dev,
8372          enum rte_eth_tunnel_type l2_tunnel_type)
8373 {
8374         int ret = 0;
8375
8376         switch (l2_tunnel_type) {
8377         case RTE_L2_TUNNEL_TYPE_E_TAG:
8378                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8379                 break;
8380         default:
8381                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8382                 ret = -EINVAL;
8383                 break;
8384         }
8385
8386         return ret;
8387 }
8388
8389 /* Disable l2 tunnel tag stripping */
8390 static int
8391 ixgbe_dev_l2_tunnel_stripping_disable
8392         (struct rte_eth_dev *dev,
8393          enum rte_eth_tunnel_type l2_tunnel_type)
8394 {
8395         int ret = 0;
8396
8397         switch (l2_tunnel_type) {
8398         case RTE_L2_TUNNEL_TYPE_E_TAG:
8399                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8400                 break;
8401         default:
8402                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8403                 ret = -EINVAL;
8404                 break;
8405         }
8406
8407         return ret;
8408 }
8409
8410 /* Enable/disable l2 tunnel offload functions */
8411 static int
8412 ixgbe_dev_l2_tunnel_offload_set
8413         (struct rte_eth_dev *dev,
8414          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8415          uint32_t mask,
8416          uint8_t en)
8417 {
8418         int ret = 0;
8419
8420         if (l2_tunnel == NULL)
8421                 return -EINVAL;
8422
8423         ret = -EINVAL;
8424         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8425                 if (en)
8426                         ret = ixgbe_dev_l2_tunnel_enable(
8427                                 dev,
8428                                 l2_tunnel->l2_tunnel_type);
8429                 else
8430                         ret = ixgbe_dev_l2_tunnel_disable(
8431                                 dev,
8432                                 l2_tunnel->l2_tunnel_type);
8433         }
8434
8435         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8436                 if (en)
8437                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8438                                 dev,
8439                                 l2_tunnel);
8440                 else
8441                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8442                                 dev,
8443                                 l2_tunnel);
8444         }
8445
8446         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8447                 if (en)
8448                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8449                                 dev,
8450                                 l2_tunnel->l2_tunnel_type);
8451                 else
8452                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8453                                 dev,
8454                                 l2_tunnel->l2_tunnel_type);
8455         }
8456
8457         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8458                 if (en)
8459                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8460                                 dev,
8461                                 l2_tunnel->l2_tunnel_type);
8462                 else
8463                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8464                                 dev,
8465                                 l2_tunnel->l2_tunnel_type);
8466         }
8467
8468         return ret;
8469 }
8470
8471 static int
8472 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8473                         uint16_t port)
8474 {
8475         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8476         IXGBE_WRITE_FLUSH(hw);
8477
8478         return 0;
8479 }
8480
8481 /* There's only one register for VxLAN UDP port.
8482  * So, we cannot add several ports. Will update it.
8483  */
8484 static int
8485 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8486                      uint16_t port)
8487 {
8488         if (port == 0) {
8489                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8490                 return -EINVAL;
8491         }
8492
8493         return ixgbe_update_vxlan_port(hw, port);
8494 }
8495
8496 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8497  * UDP port, it must have a value.
8498  * So, will reset it to the original value 0.
8499  */
8500 static int
8501 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8502                      uint16_t port)
8503 {
8504         uint16_t cur_port;
8505
8506         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8507
8508         if (cur_port != port) {
8509                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8510                 return -EINVAL;
8511         }
8512
8513         return ixgbe_update_vxlan_port(hw, 0);
8514 }
8515
8516 /* Add UDP tunneling port */
8517 static int
8518 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8519                               struct rte_eth_udp_tunnel *udp_tunnel)
8520 {
8521         int ret = 0;
8522         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8523
8524         if (hw->mac.type != ixgbe_mac_X550 &&
8525             hw->mac.type != ixgbe_mac_X550EM_x &&
8526             hw->mac.type != ixgbe_mac_X550EM_a) {
8527                 return -ENOTSUP;
8528         }
8529
8530         if (udp_tunnel == NULL)
8531                 return -EINVAL;
8532
8533         switch (udp_tunnel->prot_type) {
8534         case RTE_TUNNEL_TYPE_VXLAN:
8535                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8536                 break;
8537
8538         case RTE_TUNNEL_TYPE_GENEVE:
8539         case RTE_TUNNEL_TYPE_TEREDO:
8540                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8541                 ret = -EINVAL;
8542                 break;
8543
8544         default:
8545                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8546                 ret = -EINVAL;
8547                 break;
8548         }
8549
8550         return ret;
8551 }
8552
8553 /* Remove UDP tunneling port */
8554 static int
8555 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8556                               struct rte_eth_udp_tunnel *udp_tunnel)
8557 {
8558         int ret = 0;
8559         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8560
8561         if (hw->mac.type != ixgbe_mac_X550 &&
8562             hw->mac.type != ixgbe_mac_X550EM_x &&
8563             hw->mac.type != ixgbe_mac_X550EM_a) {
8564                 return -ENOTSUP;
8565         }
8566
8567         if (udp_tunnel == NULL)
8568                 return -EINVAL;
8569
8570         switch (udp_tunnel->prot_type) {
8571         case RTE_TUNNEL_TYPE_VXLAN:
8572                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8573                 break;
8574         case RTE_TUNNEL_TYPE_GENEVE:
8575         case RTE_TUNNEL_TYPE_TEREDO:
8576                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8577                 ret = -EINVAL;
8578                 break;
8579         default:
8580                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8581                 ret = -EINVAL;
8582                 break;
8583         }
8584
8585         return ret;
8586 }
8587
8588 static int
8589 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8590 {
8591         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8592         int ret;
8593
8594         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8595         case IXGBE_SUCCESS:
8596                 ret = 0;
8597                 break;
8598         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8599                 ret = -ENOTSUP;
8600                 break;
8601         default:
8602                 ret = -EAGAIN;
8603                 break;
8604         }
8605
8606         return ret;
8607 }
8608
8609 static int
8610 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8611 {
8612         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8613         int ret;
8614
8615         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8616         case IXGBE_SUCCESS:
8617                 ret = 0;
8618                 break;
8619         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8620                 ret = -ENOTSUP;
8621                 break;
8622         default:
8623                 ret = -EAGAIN;
8624                 break;
8625         }
8626
8627         return ret;
8628 }
8629
8630 static int
8631 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8632 {
8633         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8634         int ret;
8635         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8636
8637         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8638         case IXGBE_SUCCESS:
8639                 ret = 0;
8640                 break;
8641         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8642                 ret = -ENOTSUP;
8643                 break;
8644         default:
8645                 ret = -EAGAIN;
8646                 break;
8647         }
8648
8649         return ret;
8650 }
8651
8652 static int
8653 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8654 {
8655         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8656         int ret;
8657
8658         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8659         case IXGBE_SUCCESS:
8660                 ret = 0;
8661                 break;
8662         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8663                 ret = -ENOTSUP;
8664                 break;
8665         default:
8666                 ret = -EAGAIN;
8667                 break;
8668         }
8669
8670         return ret;
8671 }
8672
8673 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8674 {
8675         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8676         u32 in_msg = 0;
8677
8678         /* peek the message first */
8679         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8680
8681         /* PF reset VF event */
8682         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8683                 /* dummy mbx read to ack pf */
8684                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8685                         return;
8686                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8687                                              NULL);
8688         }
8689 }
8690
8691 static int
8692 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8693 {
8694         uint32_t eicr;
8695         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8696         struct ixgbe_interrupt *intr =
8697                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8698         ixgbevf_intr_disable(dev);
8699
8700         /* read-on-clear nic registers here */
8701         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8702         intr->flags = 0;
8703
8704         /* only one misc vector supported - mailbox */
8705         eicr &= IXGBE_VTEICR_MASK;
8706         if (eicr == IXGBE_MISC_VEC_ID)
8707                 intr->flags |= IXGBE_FLAG_MAILBOX;
8708
8709         return 0;
8710 }
8711
8712 static int
8713 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8714 {
8715         struct ixgbe_interrupt *intr =
8716                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8717
8718         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8719                 ixgbevf_mbx_process(dev);
8720                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8721         }
8722
8723         ixgbevf_intr_enable(dev);
8724
8725         return 0;
8726 }
8727
8728 static void
8729 ixgbevf_dev_interrupt_handler(void *param)
8730 {
8731         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8732
8733         ixgbevf_dev_interrupt_get_status(dev);
8734         ixgbevf_dev_interrupt_action(dev);
8735 }
8736
8737 /**
8738  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8739  *  @hw: pointer to hardware structure
8740  *
8741  *  Stops the transmit data path and waits for the HW to internally empty
8742  *  the Tx security block
8743  **/
8744 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8745 {
8746 #define IXGBE_MAX_SECTX_POLL 40
8747
8748         int i;
8749         int sectxreg;
8750
8751         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8752         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8753         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8754         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8755                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8756                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8757                         break;
8758                 /* Use interrupt-safe sleep just in case */
8759                 usec_delay(1000);
8760         }
8761
8762         /* For informational purposes only */
8763         if (i >= IXGBE_MAX_SECTX_POLL)
8764                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8765                          "path fully disabled.  Continuing with init.");
8766
8767         return IXGBE_SUCCESS;
8768 }
8769
8770 /**
8771  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8772  *  @hw: pointer to hardware structure
8773  *
8774  *  Enables the transmit data path.
8775  **/
8776 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8777 {
8778         uint32_t sectxreg;
8779
8780         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8781         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8782         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8783         IXGBE_WRITE_FLUSH(hw);
8784
8785         return IXGBE_SUCCESS;
8786 }
8787
8788 /* restore n-tuple filter */
8789 static inline void
8790 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8791 {
8792         struct ixgbe_filter_info *filter_info =
8793                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8794         struct ixgbe_5tuple_filter *node;
8795
8796         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8797                 ixgbe_inject_5tuple_filter(dev, node);
8798         }
8799 }
8800
8801 /* restore ethernet type filter */
8802 static inline void
8803 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8804 {
8805         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8806         struct ixgbe_filter_info *filter_info =
8807                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8808         int i;
8809
8810         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8811                 if (filter_info->ethertype_mask & (1 << i)) {
8812                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8813                                         filter_info->ethertype_filters[i].etqf);
8814                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8815                                         filter_info->ethertype_filters[i].etqs);
8816                         IXGBE_WRITE_FLUSH(hw);
8817                 }
8818         }
8819 }
8820
8821 /* restore SYN filter */
8822 static inline void
8823 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8824 {
8825         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8826         struct ixgbe_filter_info *filter_info =
8827                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8828         uint32_t synqf;
8829
8830         synqf = filter_info->syn_info;
8831
8832         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8833                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8834                 IXGBE_WRITE_FLUSH(hw);
8835         }
8836 }
8837
8838 /* restore L2 tunnel filter */
8839 static inline void
8840 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8841 {
8842         struct ixgbe_l2_tn_info *l2_tn_info =
8843                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8844         struct ixgbe_l2_tn_filter *node;
8845         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8846
8847         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8848                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8849                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8850                 l2_tn_conf.pool           = node->pool;
8851                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8852         }
8853 }
8854
8855 /* restore rss filter */
8856 static inline void
8857 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8858 {
8859         struct ixgbe_filter_info *filter_info =
8860                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8861
8862         if (filter_info->rss_info.conf.queue_num)
8863                 ixgbe_config_rss_filter(dev,
8864                         &filter_info->rss_info, TRUE);
8865 }
8866
8867 static int
8868 ixgbe_filter_restore(struct rte_eth_dev *dev)
8869 {
8870         ixgbe_ntuple_filter_restore(dev);
8871         ixgbe_ethertype_filter_restore(dev);
8872         ixgbe_syn_filter_restore(dev);
8873         ixgbe_fdir_filter_restore(dev);
8874         ixgbe_l2_tn_filter_restore(dev);
8875         ixgbe_rss_filter_restore(dev);
8876
8877         return 0;
8878 }
8879
8880 static void
8881 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8882 {
8883         struct ixgbe_l2_tn_info *l2_tn_info =
8884                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8886
8887         if (l2_tn_info->e_tag_en)
8888                 (void)ixgbe_e_tag_enable(hw);
8889
8890         if (l2_tn_info->e_tag_fwd_en)
8891                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8892
8893         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8894 }
8895
8896 /* remove all the n-tuple filters */
8897 void
8898 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8899 {
8900         struct ixgbe_filter_info *filter_info =
8901                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8902         struct ixgbe_5tuple_filter *p_5tuple;
8903
8904         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8905                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8906 }
8907
8908 /* remove all the ether type filters */
8909 void
8910 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8911 {
8912         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8913         struct ixgbe_filter_info *filter_info =
8914                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8915         int i;
8916
8917         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8918                 if (filter_info->ethertype_mask & (1 << i) &&
8919                     !filter_info->ethertype_filters[i].conf) {
8920                         (void)ixgbe_ethertype_filter_remove(filter_info,
8921                                                             (uint8_t)i);
8922                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8923                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8924                         IXGBE_WRITE_FLUSH(hw);
8925                 }
8926         }
8927 }
8928
8929 /* remove the SYN filter */
8930 void
8931 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8932 {
8933         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8934         struct ixgbe_filter_info *filter_info =
8935                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8936
8937         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8938                 filter_info->syn_info = 0;
8939
8940                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8941                 IXGBE_WRITE_FLUSH(hw);
8942         }
8943 }
8944
8945 /* remove all the L2 tunnel filters */
8946 int
8947 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8948 {
8949         struct ixgbe_l2_tn_info *l2_tn_info =
8950                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8951         struct ixgbe_l2_tn_filter *l2_tn_filter;
8952         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8953         int ret = 0;
8954
8955         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8956                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8957                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8958                 l2_tn_conf.pool           = l2_tn_filter->pool;
8959                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8960                 if (ret < 0)
8961                         return ret;
8962         }
8963
8964         return 0;
8965 }
8966
8967 void
8968 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8969                                 struct ixgbe_macsec_setting *macsec_setting)
8970 {
8971         struct ixgbe_macsec_setting *macsec =
8972                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8973
8974         macsec->offload_en = macsec_setting->offload_en;
8975         macsec->encrypt_en = macsec_setting->encrypt_en;
8976         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8977 }
8978
8979 void
8980 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8981 {
8982         struct ixgbe_macsec_setting *macsec =
8983                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8984
8985         macsec->offload_en = 0;
8986         macsec->encrypt_en = 0;
8987         macsec->replayprotect_en = 0;
8988 }
8989
8990 void
8991 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8992                                 struct ixgbe_macsec_setting *macsec_setting)
8993 {
8994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8995         uint32_t ctrl;
8996         uint8_t en = macsec_setting->encrypt_en;
8997         uint8_t rp = macsec_setting->replayprotect_en;
8998
8999         /**
9000          * Workaround:
9001          * As no ixgbe_disable_sec_rx_path equivalent is
9002          * implemented for tx in the base code, and we are
9003          * not allowed to modify the base code in DPDK, so
9004          * just call the hand-written one directly for now.
9005          * The hardware support has been checked by
9006          * ixgbe_disable_sec_rx_path().
9007          */
9008         ixgbe_disable_sec_tx_path_generic(hw);
9009
9010         /* Enable Ethernet CRC (required by MACsec offload) */
9011         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9012         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9013         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9014
9015         /* Enable the TX and RX crypto engines */
9016         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9017         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9018         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9019
9020         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9021         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9022         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9023
9024         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9025         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9026         ctrl |= 0x3;
9027         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9028
9029         /* Enable SA lookup */
9030         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9031         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9032         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9033                      IXGBE_LSECTXCTRL_AUTH;
9034         ctrl |= IXGBE_LSECTXCTRL_AISCI;
9035         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9036         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9037         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9038
9039         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9040         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9041         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9042         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9043         if (rp)
9044                 ctrl |= IXGBE_LSECRXCTRL_RP;
9045         else
9046                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9047         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9048
9049         /* Start the data paths */
9050         ixgbe_enable_sec_rx_path(hw);
9051         /**
9052          * Workaround:
9053          * As no ixgbe_enable_sec_rx_path equivalent is
9054          * implemented for tx in the base code, and we are
9055          * not allowed to modify the base code in DPDK, so
9056          * just call the hand-written one directly for now.
9057          */
9058         ixgbe_enable_sec_tx_path_generic(hw);
9059 }
9060
9061 void
9062 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9063 {
9064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9065         uint32_t ctrl;
9066
9067         /**
9068          * Workaround:
9069          * As no ixgbe_disable_sec_rx_path equivalent is
9070          * implemented for tx in the base code, and we are
9071          * not allowed to modify the base code in DPDK, so
9072          * just call the hand-written one directly for now.
9073          * The hardware support has been checked by
9074          * ixgbe_disable_sec_rx_path().
9075          */
9076         ixgbe_disable_sec_tx_path_generic(hw);
9077
9078         /* Disable the TX and RX crypto engines */
9079         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9080         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9081         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9082
9083         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9084         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9085         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9086
9087         /* Disable SA lookup */
9088         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9089         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9090         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9091         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9092
9093         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9094         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9095         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9096         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9097
9098         /* Start the data paths */
9099         ixgbe_enable_sec_rx_path(hw);
9100         /**
9101          * Workaround:
9102          * As no ixgbe_enable_sec_rx_path equivalent is
9103          * implemented for tx in the base code, and we are
9104          * not allowed to modify the base code in DPDK, so
9105          * just call the hand-written one directly for now.
9106          */
9107         ixgbe_enable_sec_tx_path_generic(hw);
9108 }
9109
9110 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9111 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9112 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9113 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9114 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9115 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9116 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9117                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9118
9119 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
9120 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
9121
9122 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9123 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
9124 #endif
9125 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9126 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
9127 #endif
9128 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9129 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
9130 #endif