1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
18 #include <rte_interrupts.h>
20 #include <rte_debug.h>
22 #include <rte_bus_pci.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
31 #include <rte_random.h>
33 #include <rte_hash_crc.h>
34 #ifdef RTE_LIBRTE_SECURITY
35 #include <rte_security_driver.h>
38 #include "ixgbe_logs.h"
39 #include "base/ixgbe_api.h"
40 #include "base/ixgbe_vf.h"
41 #include "base/ixgbe_common.h"
42 #include "ixgbe_ethdev.h"
43 #include "ixgbe_bypass.h"
44 #include "ixgbe_rxtx.h"
45 #include "base/ixgbe_type.h"
46 #include "base/ixgbe_phy.h"
47 #include "ixgbe_regs.h"
50 * High threshold controlling when to start sending XOFF frames. Must be at
51 * least 8 bytes less than receive packet buffer size. This value is in units
54 #define IXGBE_FC_HI 0x80
57 * Low threshold controlling when to start sending XON frames. This value is
58 * in units of 1024 bytes.
60 #define IXGBE_FC_LO 0x40
62 /* Default minimum inter-interrupt interval for EITR configuration */
63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
65 /* Timer value included in XOFF frames. */
66 #define IXGBE_FC_PAUSE 0x680
68 /*Default value of Max Rx Queue*/
69 #define IXGBE_MAX_RX_QUEUE_NUM 128
71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
72 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
73 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
75 #define IXGBE_MMW_SIZE_DEFAULT 0x4
76 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
77 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
80 * Default values for RX/TX configuration
82 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
83 #define IXGBE_DEFAULT_RX_PTHRESH 8
84 #define IXGBE_DEFAULT_RX_HTHRESH 8
85 #define IXGBE_DEFAULT_RX_WTHRESH 0
87 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
88 #define IXGBE_DEFAULT_TX_PTHRESH 32
89 #define IXGBE_DEFAULT_TX_HTHRESH 0
90 #define IXGBE_DEFAULT_TX_WTHRESH 0
91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
93 /* Bit shift and mask */
94 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
95 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
96 #define IXGBE_8_BIT_WIDTH CHAR_BIT
97 #define IXGBE_8_BIT_MASK UINT8_MAX
99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
103 /* Additional timesync values. */
104 #define NSEC_PER_SEC 1000000000L
105 #define IXGBE_INCVAL_10GB 0x66666666
106 #define IXGBE_INCVAL_1GB 0x40000000
107 #define IXGBE_INCVAL_100 0x50000000
108 #define IXGBE_INCVAL_SHIFT_10GB 28
109 #define IXGBE_INCVAL_SHIFT_1GB 24
110 #define IXGBE_INCVAL_SHIFT_100 21
111 #define IXGBE_INCVAL_SHIFT_82599 7
112 #define IXGBE_INCPER_SHIFT_82599 24
114 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
116 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
117 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
118 #define IXGBE_ETAG_ETYPE 0x00005084
119 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
120 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
121 #define IXGBE_RAH_ADTYPE 0x40000000
122 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
123 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
124 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
125 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
126 #define IXGBE_QDE_STRIP_TAG 0x00000004
127 #define IXGBE_VTEICR_MASK 0x07
129 #define IXGBE_EXVET_VET_EXT_SHIFT 16
130 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
132 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
133 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
134 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
135 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
137 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
138 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
139 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
140 static int ixgbe_dev_start(struct rte_eth_dev *dev);
141 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
142 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
143 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
144 static void ixgbe_dev_close(struct rte_eth_dev *dev);
145 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
146 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
147 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
148 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
149 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
150 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
151 int wait_to_complete);
152 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
153 struct rte_eth_stats *stats);
154 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
155 struct rte_eth_xstat *xstats, unsigned n);
156 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
157 struct rte_eth_xstat *xstats, unsigned n);
159 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
160 uint64_t *values, unsigned int n);
161 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
162 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
163 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
164 struct rte_eth_xstat_name *xstats_names,
166 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
167 struct rte_eth_xstat_name *xstats_names, unsigned limit);
168 static int ixgbe_dev_xstats_get_names_by_id(
169 struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
173 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
177 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
179 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
180 struct rte_eth_dev_info *dev_info);
181 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
182 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
183 struct rte_eth_dev_info *dev_info);
184 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
186 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
187 uint16_t vlan_id, int on);
188 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
189 enum rte_vlan_type vlan_type,
191 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
192 uint16_t queue, bool on);
193 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
204 struct rte_eth_fc_conf *fc_conf);
205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
206 struct rte_eth_fc_conf *fc_conf);
207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
208 struct rte_eth_pfc_conf *pfc_conf);
209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
210 struct rte_eth_rss_reta_entry64 *reta_conf,
212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
221 struct rte_intr_handle *handle);
222 static void ixgbe_dev_interrupt_handler(void *param);
223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
224 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
225 uint32_t index, uint32_t pool);
226 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
227 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
228 struct ether_addr *mac_addr);
229 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
230 static bool is_device_supported(struct rte_eth_dev *dev,
231 struct rte_pci_driver *drv);
233 /* For Virtual Function support */
234 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
235 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
236 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
237 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
238 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
239 int wait_to_complete);
240 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
241 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
242 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
243 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
244 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
245 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
246 struct rte_eth_stats *stats);
247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
249 uint16_t vlan_id, int on);
250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
251 uint16_t queue, int on);
252 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
259 uint8_t queue, uint8_t msix_vector);
260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
264 /* For Eth VMDQ APIs support */
265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
266 ether_addr * mac_addr, uint8_t on);
267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
268 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
269 struct rte_eth_mirror_conf *mirror_conf,
270 uint8_t rule_id, uint8_t on);
271 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
273 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
275 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
277 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
278 uint8_t queue, uint8_t msix_vector);
279 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
281 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
282 struct ether_addr *mac_addr,
283 uint32_t index, uint32_t pool);
284 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
285 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
286 struct ether_addr *mac_addr);
287 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
288 struct rte_eth_syn_filter *filter);
289 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
290 enum rte_filter_op filter_op,
292 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
293 struct ixgbe_5tuple_filter *filter);
294 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
295 struct ixgbe_5tuple_filter *filter);
296 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
297 enum rte_filter_op filter_op,
299 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
300 struct rte_eth_ntuple_filter *filter);
301 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
302 enum rte_filter_op filter_op,
304 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
305 struct rte_eth_ethertype_filter *filter);
306 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
307 enum rte_filter_type filter_type,
308 enum rte_filter_op filter_op,
310 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
312 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
313 struct ether_addr *mc_addr_set,
314 uint32_t nb_mc_addr);
315 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
316 struct rte_eth_dcb_info *dcb_info);
318 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
319 static int ixgbe_get_regs(struct rte_eth_dev *dev,
320 struct rte_dev_reg_info *regs);
321 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
322 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
323 struct rte_dev_eeprom_info *eeprom);
324 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
325 struct rte_dev_eeprom_info *eeprom);
327 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
328 struct rte_eth_dev_module_info *modinfo);
329 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
330 struct rte_dev_eeprom_info *info);
332 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
333 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
334 struct rte_dev_reg_info *regs);
336 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
337 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
338 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
339 struct timespec *timestamp,
341 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
342 struct timespec *timestamp);
343 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
344 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
345 struct timespec *timestamp);
346 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
347 const struct timespec *timestamp);
348 static void ixgbevf_dev_interrupt_handler(void *param);
350 static int ixgbe_dev_l2_tunnel_eth_type_conf
351 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
352 static int ixgbe_dev_l2_tunnel_offload_set
353 (struct rte_eth_dev *dev,
354 struct rte_eth_l2_tunnel_conf *l2_tunnel,
357 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
358 enum rte_filter_op filter_op,
361 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
362 struct rte_eth_udp_tunnel *udp_tunnel);
363 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
364 struct rte_eth_udp_tunnel *udp_tunnel);
365 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
366 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
369 * Define VF Stats MACRO for Non "cleared on read" register
371 #define UPDATE_VF_STAT(reg, last, cur) \
373 uint32_t latest = IXGBE_READ_REG(hw, reg); \
374 cur += (latest - last) & UINT_MAX; \
378 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
380 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
381 u64 new_msb = IXGBE_READ_REG(hw, msb); \
382 u64 latest = ((new_msb << 32) | new_lsb); \
383 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
387 #define IXGBE_SET_HWSTRIP(h, q) do {\
388 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
389 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
390 (h)->bitmap[idx] |= 1 << bit;\
393 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
394 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
395 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
396 (h)->bitmap[idx] &= ~(1 << bit);\
399 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
400 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
401 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
402 (r) = (h)->bitmap[idx] >> bit & 1;\
405 int ixgbe_logtype_init;
406 int ixgbe_logtype_driver;
409 * The set of PCI devices this driver supports
411 static const struct rte_pci_id pci_id_ixgbe_map[] = {
412 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
460 #ifdef RTE_LIBRTE_IXGBE_BYPASS
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
463 { .vendor_id = 0, /* sentinel */ },
467 * The set of PCI devices this driver supports (for 82599 VF)
469 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
480 { .vendor_id = 0, /* sentinel */ },
483 static const struct rte_eth_desc_lim rx_desc_lim = {
484 .nb_max = IXGBE_MAX_RING_DESC,
485 .nb_min = IXGBE_MIN_RING_DESC,
486 .nb_align = IXGBE_RXD_ALIGN,
489 static const struct rte_eth_desc_lim tx_desc_lim = {
490 .nb_max = IXGBE_MAX_RING_DESC,
491 .nb_min = IXGBE_MIN_RING_DESC,
492 .nb_align = IXGBE_TXD_ALIGN,
493 .nb_seg_max = IXGBE_TX_MAX_SEG,
494 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
497 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
498 .dev_configure = ixgbe_dev_configure,
499 .dev_start = ixgbe_dev_start,
500 .dev_stop = ixgbe_dev_stop,
501 .dev_set_link_up = ixgbe_dev_set_link_up,
502 .dev_set_link_down = ixgbe_dev_set_link_down,
503 .dev_close = ixgbe_dev_close,
504 .dev_reset = ixgbe_dev_reset,
505 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
506 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
507 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
508 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
509 .link_update = ixgbe_dev_link_update,
510 .stats_get = ixgbe_dev_stats_get,
511 .xstats_get = ixgbe_dev_xstats_get,
512 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
513 .stats_reset = ixgbe_dev_stats_reset,
514 .xstats_reset = ixgbe_dev_xstats_reset,
515 .xstats_get_names = ixgbe_dev_xstats_get_names,
516 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
517 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
518 .fw_version_get = ixgbe_fw_version_get,
519 .dev_infos_get = ixgbe_dev_info_get,
520 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
521 .mtu_set = ixgbe_dev_mtu_set,
522 .vlan_filter_set = ixgbe_vlan_filter_set,
523 .vlan_tpid_set = ixgbe_vlan_tpid_set,
524 .vlan_offload_set = ixgbe_vlan_offload_set,
525 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
526 .rx_queue_start = ixgbe_dev_rx_queue_start,
527 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
528 .tx_queue_start = ixgbe_dev_tx_queue_start,
529 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
530 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
531 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
532 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
533 .rx_queue_release = ixgbe_dev_rx_queue_release,
534 .rx_queue_count = ixgbe_dev_rx_queue_count,
535 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
536 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
537 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
538 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
539 .tx_queue_release = ixgbe_dev_tx_queue_release,
540 .dev_led_on = ixgbe_dev_led_on,
541 .dev_led_off = ixgbe_dev_led_off,
542 .flow_ctrl_get = ixgbe_flow_ctrl_get,
543 .flow_ctrl_set = ixgbe_flow_ctrl_set,
544 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
545 .mac_addr_add = ixgbe_add_rar,
546 .mac_addr_remove = ixgbe_remove_rar,
547 .mac_addr_set = ixgbe_set_default_mac_addr,
548 .uc_hash_table_set = ixgbe_uc_hash_table_set,
549 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
550 .mirror_rule_set = ixgbe_mirror_rule_set,
551 .mirror_rule_reset = ixgbe_mirror_rule_reset,
552 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
553 .reta_update = ixgbe_dev_rss_reta_update,
554 .reta_query = ixgbe_dev_rss_reta_query,
555 .rss_hash_update = ixgbe_dev_rss_hash_update,
556 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
557 .filter_ctrl = ixgbe_dev_filter_ctrl,
558 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
559 .rxq_info_get = ixgbe_rxq_info_get,
560 .txq_info_get = ixgbe_txq_info_get,
561 .timesync_enable = ixgbe_timesync_enable,
562 .timesync_disable = ixgbe_timesync_disable,
563 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
564 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
565 .get_reg = ixgbe_get_regs,
566 .get_eeprom_length = ixgbe_get_eeprom_length,
567 .get_eeprom = ixgbe_get_eeprom,
568 .set_eeprom = ixgbe_set_eeprom,
569 .get_module_info = ixgbe_get_module_info,
570 .get_module_eeprom = ixgbe_get_module_eeprom,
571 .get_dcb_info = ixgbe_dev_get_dcb_info,
572 .timesync_adjust_time = ixgbe_timesync_adjust_time,
573 .timesync_read_time = ixgbe_timesync_read_time,
574 .timesync_write_time = ixgbe_timesync_write_time,
575 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
576 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
577 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
578 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
579 .tm_ops_get = ixgbe_tm_ops_get,
583 * dev_ops for virtual function, bare necessities for basic vf
584 * operation have been implemented
586 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
587 .dev_configure = ixgbevf_dev_configure,
588 .dev_start = ixgbevf_dev_start,
589 .dev_stop = ixgbevf_dev_stop,
590 .link_update = ixgbevf_dev_link_update,
591 .stats_get = ixgbevf_dev_stats_get,
592 .xstats_get = ixgbevf_dev_xstats_get,
593 .stats_reset = ixgbevf_dev_stats_reset,
594 .xstats_reset = ixgbevf_dev_stats_reset,
595 .xstats_get_names = ixgbevf_dev_xstats_get_names,
596 .dev_close = ixgbevf_dev_close,
597 .dev_reset = ixgbevf_dev_reset,
598 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
599 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
600 .dev_infos_get = ixgbevf_dev_info_get,
601 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
602 .mtu_set = ixgbevf_dev_set_mtu,
603 .vlan_filter_set = ixgbevf_vlan_filter_set,
604 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
605 .vlan_offload_set = ixgbevf_vlan_offload_set,
606 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
607 .rx_queue_release = ixgbe_dev_rx_queue_release,
608 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
609 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
610 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
611 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
612 .tx_queue_release = ixgbe_dev_tx_queue_release,
613 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
614 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
615 .mac_addr_add = ixgbevf_add_mac_addr,
616 .mac_addr_remove = ixgbevf_remove_mac_addr,
617 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
618 .rxq_info_get = ixgbe_rxq_info_get,
619 .txq_info_get = ixgbe_txq_info_get,
620 .mac_addr_set = ixgbevf_set_default_mac_addr,
621 .get_reg = ixgbevf_get_regs,
622 .reta_update = ixgbe_dev_rss_reta_update,
623 .reta_query = ixgbe_dev_rss_reta_query,
624 .rss_hash_update = ixgbe_dev_rss_hash_update,
625 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
628 /* store statistics names and its offset in stats structure */
629 struct rte_ixgbe_xstats_name_off {
630 char name[RTE_ETH_XSTATS_NAME_SIZE];
634 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
635 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
636 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
637 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
638 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
639 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
640 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
641 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
642 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
643 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
644 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
645 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
646 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
647 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
648 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
649 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
651 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
653 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
654 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
655 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
656 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
657 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
658 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
659 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
660 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
661 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
662 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
663 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
664 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
665 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
666 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
667 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
668 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
669 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
671 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
673 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
674 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
675 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
676 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
678 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
680 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
682 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
684 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
686 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
688 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
691 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
692 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
693 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
695 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
696 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
697 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
698 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
699 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
701 {"rx_fcoe_no_direct_data_placement_ext_buff",
702 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
704 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
706 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
708 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
710 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
712 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
715 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
716 sizeof(rte_ixgbe_stats_strings[0]))
718 /* MACsec statistics */
719 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
720 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
722 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
723 out_pkts_encrypted)},
724 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
725 out_pkts_protected)},
726 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
727 out_octets_encrypted)},
728 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
729 out_octets_protected)},
730 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
732 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
734 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
736 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
737 in_pkts_unknownsci)},
738 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
739 in_octets_decrypted)},
740 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
741 in_octets_validated)},
742 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
744 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
746 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
748 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
750 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
752 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
754 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
756 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
757 in_pkts_notusingsa)},
760 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
761 sizeof(rte_ixgbe_macsec_strings[0]))
763 /* Per-queue statistics */
764 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
765 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
766 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
767 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
768 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
771 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
772 sizeof(rte_ixgbe_rxq_strings[0]))
773 #define IXGBE_NB_RXQ_PRIO_VALUES 8
775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
776 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
777 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
778 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
782 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
783 sizeof(rte_ixgbe_txq_strings[0]))
784 #define IXGBE_NB_TXQ_PRIO_VALUES 8
786 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
787 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
790 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
791 sizeof(rte_ixgbevf_stats_strings[0]))
794 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
797 ixgbe_is_sfp(struct ixgbe_hw *hw)
799 switch (hw->phy.type) {
800 case ixgbe_phy_sfp_avago:
801 case ixgbe_phy_sfp_ftl:
802 case ixgbe_phy_sfp_intel:
803 case ixgbe_phy_sfp_unknown:
804 case ixgbe_phy_sfp_passive_tyco:
805 case ixgbe_phy_sfp_passive_unknown:
812 static inline int32_t
813 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
818 status = ixgbe_reset_hw(hw);
820 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
821 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
822 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
823 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
824 IXGBE_WRITE_FLUSH(hw);
826 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
827 status = IXGBE_SUCCESS;
832 ixgbe_enable_intr(struct rte_eth_dev *dev)
834 struct ixgbe_interrupt *intr =
835 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
836 struct ixgbe_hw *hw =
837 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
839 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
840 IXGBE_WRITE_FLUSH(hw);
844 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
847 ixgbe_disable_intr(struct ixgbe_hw *hw)
849 PMD_INIT_FUNC_TRACE();
851 if (hw->mac.type == ixgbe_mac_82598EB) {
852 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
854 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
855 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
856 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
858 IXGBE_WRITE_FLUSH(hw);
862 * This function resets queue statistics mapping registers.
863 * From Niantic datasheet, Initialization of Statistics section:
864 * "...if software requires the queue counters, the RQSMR and TQSM registers
865 * must be re-programmed following a device reset.
868 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
872 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
873 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
874 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
880 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
885 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
886 #define NB_QMAP_FIELDS_PER_QSM_REG 4
887 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
889 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
890 struct ixgbe_stat_mapping_registers *stat_mappings =
891 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
892 uint32_t qsmr_mask = 0;
893 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
897 if ((hw->mac.type != ixgbe_mac_82599EB) &&
898 (hw->mac.type != ixgbe_mac_X540) &&
899 (hw->mac.type != ixgbe_mac_X550) &&
900 (hw->mac.type != ixgbe_mac_X550EM_x) &&
901 (hw->mac.type != ixgbe_mac_X550EM_a))
904 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
905 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
908 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
909 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
910 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
913 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
915 /* Now clear any previous stat_idx set */
916 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
918 stat_mappings->tqsm[n] &= ~clearing_mask;
920 stat_mappings->rqsmr[n] &= ~clearing_mask;
922 q_map = (uint32_t)stat_idx;
923 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
924 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
926 stat_mappings->tqsm[n] |= qsmr_mask;
928 stat_mappings->rqsmr[n] |= qsmr_mask;
930 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
931 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
933 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
934 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
936 /* Now write the mapping in the appropriate register */
938 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
939 stat_mappings->rqsmr[n], n);
940 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
942 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
943 stat_mappings->tqsm[n], n);
944 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
950 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
952 struct ixgbe_stat_mapping_registers *stat_mappings =
953 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
954 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
957 /* write whatever was in stat mapping table to the NIC */
958 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
960 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
963 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
968 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
971 struct ixgbe_dcb_tc_config *tc;
972 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
974 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
975 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
976 for (i = 0; i < dcb_max_tc; i++) {
977 tc = &dcb_config->tc_config[i];
978 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
979 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
980 (uint8_t)(100/dcb_max_tc + (i & 1));
981 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
982 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
983 (uint8_t)(100/dcb_max_tc + (i & 1));
984 tc->pfc = ixgbe_dcb_pfc_disabled;
987 /* Initialize default user to priority mapping, UPx->TC0 */
988 tc = &dcb_config->tc_config[0];
989 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
990 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
991 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
992 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
993 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
995 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
996 dcb_config->pfc_mode_enable = false;
997 dcb_config->vt_mode = true;
998 dcb_config->round_robin_enable = false;
999 /* support all DCB capabilities in 82599 */
1000 dcb_config->support.capabilities = 0xFF;
1002 /*we only support 4 Tcs for X540, X550 */
1003 if (hw->mac.type == ixgbe_mac_X540 ||
1004 hw->mac.type == ixgbe_mac_X550 ||
1005 hw->mac.type == ixgbe_mac_X550EM_x ||
1006 hw->mac.type == ixgbe_mac_X550EM_a) {
1007 dcb_config->num_tcs.pg_tcs = 4;
1008 dcb_config->num_tcs.pfc_tcs = 4;
1013 * Ensure that all locks are released before first NVM or PHY access
1016 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1021 * Phy lock should not fail in this early stage. If this is the case,
1022 * it is due to an improper exit of the application.
1023 * So force the release of the faulty lock. Release of common lock
1024 * is done automatically by swfw_sync function.
1026 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1027 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1028 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1030 ixgbe_release_swfw_semaphore(hw, mask);
1033 * These ones are more tricky since they are common to all ports; but
1034 * swfw_sync retries last long enough (1s) to be almost sure that if
1035 * lock can not be taken it is due to an improper lock of the
1038 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1039 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1040 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1042 ixgbe_release_swfw_semaphore(hw, mask);
1046 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1047 * It returns 0 on success.
1050 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1052 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1053 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1054 struct ixgbe_hw *hw =
1055 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1056 struct ixgbe_vfta *shadow_vfta =
1057 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1058 struct ixgbe_hwstrip *hwstrip =
1059 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1060 struct ixgbe_dcb_config *dcb_config =
1061 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1062 struct ixgbe_filter_info *filter_info =
1063 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1064 struct ixgbe_bw_conf *bw_conf =
1065 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1070 PMD_INIT_FUNC_TRACE();
1072 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1073 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1074 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1075 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1078 * For secondary processes, we don't initialise any further as primary
1079 * has already done this work. Only check we don't need a different
1080 * RX and TX function.
1082 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1083 struct ixgbe_tx_queue *txq;
1084 /* TX queue function in primary, set by last queue initialized
1085 * Tx queue may not initialized by primary process
1087 if (eth_dev->data->tx_queues) {
1088 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1089 ixgbe_set_tx_function(eth_dev, txq);
1091 /* Use default TX function if we get here */
1092 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1093 "Using default TX function.");
1096 ixgbe_set_rx_function(eth_dev);
1101 rte_eth_copy_pci_info(eth_dev, pci_dev);
1103 /* Vendor and Device ID need to be set before init of shared code */
1104 hw->device_id = pci_dev->id.device_id;
1105 hw->vendor_id = pci_dev->id.vendor_id;
1106 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1107 hw->allow_unsupported_sfp = 1;
1109 /* Initialize the shared code (base driver) */
1110 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1111 diag = ixgbe_bypass_init_shared_code(hw);
1113 diag = ixgbe_init_shared_code(hw);
1114 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1116 if (diag != IXGBE_SUCCESS) {
1117 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1121 /* pick up the PCI bus settings for reporting later */
1122 ixgbe_get_bus_info(hw);
1124 /* Unlock any pending hardware semaphore */
1125 ixgbe_swfw_lock_reset(hw);
1127 #ifdef RTE_LIBRTE_SECURITY
1128 /* Initialize security_ctx only for primary process*/
1129 if (ixgbe_ipsec_ctx_create(eth_dev))
1133 /* Initialize DCB configuration*/
1134 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1135 ixgbe_dcb_init(hw, dcb_config);
1136 /* Get Hardware Flow Control setting */
1137 hw->fc.requested_mode = ixgbe_fc_full;
1138 hw->fc.current_mode = ixgbe_fc_full;
1139 hw->fc.pause_time = IXGBE_FC_PAUSE;
1140 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1141 hw->fc.low_water[i] = IXGBE_FC_LO;
1142 hw->fc.high_water[i] = IXGBE_FC_HI;
1144 hw->fc.send_xon = 1;
1146 /* Make sure we have a good EEPROM before we read from it */
1147 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1148 if (diag != IXGBE_SUCCESS) {
1149 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1153 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1154 diag = ixgbe_bypass_init_hw(hw);
1156 diag = ixgbe_init_hw(hw);
1157 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1160 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1161 * is called too soon after the kernel driver unbinding/binding occurs.
1162 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1163 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1164 * also called. See ixgbe_identify_phy_82599(). The reason for the
1165 * failure is not known, and only occuts when virtualisation features
1166 * are disabled in the bios. A delay of 100ms was found to be enough by
1167 * trial-and-error, and is doubled to be safe.
1169 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1171 diag = ixgbe_init_hw(hw);
1174 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1175 diag = IXGBE_SUCCESS;
1177 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1178 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1179 "LOM. Please be aware there may be issues associated "
1180 "with your hardware.");
1181 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1182 "please contact your Intel or hardware representative "
1183 "who provided you with this hardware.");
1184 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1185 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1187 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1191 /* Reset the hw statistics */
1192 ixgbe_dev_stats_reset(eth_dev);
1194 /* disable interrupt */
1195 ixgbe_disable_intr(hw);
1197 /* reset mappings for queue statistics hw counters*/
1198 ixgbe_reset_qstat_mappings(hw);
1200 /* Allocate memory for storing MAC addresses */
1201 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1202 hw->mac.num_rar_entries, 0);
1203 if (eth_dev->data->mac_addrs == NULL) {
1205 "Failed to allocate %u bytes needed to store "
1207 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1210 /* Copy the permanent MAC address */
1211 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1212 ð_dev->data->mac_addrs[0]);
1214 /* Allocate memory for storing hash filter MAC addresses */
1215 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1216 IXGBE_VMDQ_NUM_UC_MAC, 0);
1217 if (eth_dev->data->hash_mac_addrs == NULL) {
1219 "Failed to allocate %d bytes needed to store MAC addresses",
1220 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1224 /* initialize the vfta */
1225 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1227 /* initialize the hw strip bitmap*/
1228 memset(hwstrip, 0, sizeof(*hwstrip));
1230 /* initialize PF if max_vfs not zero */
1231 ixgbe_pf_host_init(eth_dev);
1233 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1234 /* let hardware know driver is loaded */
1235 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1236 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1237 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1238 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1239 IXGBE_WRITE_FLUSH(hw);
1241 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1242 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1243 (int) hw->mac.type, (int) hw->phy.type,
1244 (int) hw->phy.sfp_type);
1246 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1247 (int) hw->mac.type, (int) hw->phy.type);
1249 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1250 eth_dev->data->port_id, pci_dev->id.vendor_id,
1251 pci_dev->id.device_id);
1253 rte_intr_callback_register(intr_handle,
1254 ixgbe_dev_interrupt_handler, eth_dev);
1256 /* enable uio/vfio intr/eventfd mapping */
1257 rte_intr_enable(intr_handle);
1259 /* enable support intr */
1260 ixgbe_enable_intr(eth_dev);
1262 /* initialize filter info */
1263 memset(filter_info, 0,
1264 sizeof(struct ixgbe_filter_info));
1266 /* initialize 5tuple filter list */
1267 TAILQ_INIT(&filter_info->fivetuple_list);
1269 /* initialize flow director filter list & hash */
1270 ixgbe_fdir_filter_init(eth_dev);
1272 /* initialize l2 tunnel filter list & hash */
1273 ixgbe_l2_tn_filter_init(eth_dev);
1275 /* initialize flow filter lists */
1276 ixgbe_filterlist_init();
1278 /* initialize bandwidth configuration info */
1279 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1281 /* initialize Traffic Manager configuration */
1282 ixgbe_tm_conf_init(eth_dev);
1288 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1290 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1291 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1292 struct ixgbe_hw *hw;
1296 PMD_INIT_FUNC_TRACE();
1298 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1301 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1303 if (hw->adapter_stopped == 0)
1304 ixgbe_dev_close(eth_dev);
1306 eth_dev->dev_ops = NULL;
1307 eth_dev->rx_pkt_burst = NULL;
1308 eth_dev->tx_pkt_burst = NULL;
1310 /* Unlock any pending hardware semaphore */
1311 ixgbe_swfw_lock_reset(hw);
1313 /* disable uio intr before callback unregister */
1314 rte_intr_disable(intr_handle);
1317 ret = rte_intr_callback_unregister(intr_handle,
1318 ixgbe_dev_interrupt_handler, eth_dev);
1321 } else if (ret != -EAGAIN) {
1323 "intr callback unregister failed: %d",
1328 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1330 /* uninitialize PF if max_vfs not zero */
1331 ixgbe_pf_host_uninit(eth_dev);
1333 rte_free(eth_dev->data->mac_addrs);
1334 eth_dev->data->mac_addrs = NULL;
1336 rte_free(eth_dev->data->hash_mac_addrs);
1337 eth_dev->data->hash_mac_addrs = NULL;
1339 /* remove all the fdir filters & hash */
1340 ixgbe_fdir_filter_uninit(eth_dev);
1342 /* remove all the L2 tunnel filters & hash */
1343 ixgbe_l2_tn_filter_uninit(eth_dev);
1345 /* Remove all ntuple filters of the device */
1346 ixgbe_ntuple_filter_uninit(eth_dev);
1348 /* clear all the filters list */
1349 ixgbe_filterlist_flush();
1351 /* Remove all Traffic Manager configuration */
1352 ixgbe_tm_conf_uninit(eth_dev);
1354 #ifdef RTE_LIBRTE_SECURITY
1355 rte_free(eth_dev->security_ctx);
1361 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1363 struct ixgbe_filter_info *filter_info =
1364 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1365 struct ixgbe_5tuple_filter *p_5tuple;
1367 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1368 TAILQ_REMOVE(&filter_info->fivetuple_list,
1373 memset(filter_info->fivetuple_mask, 0,
1374 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1379 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1381 struct ixgbe_hw_fdir_info *fdir_info =
1382 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1383 struct ixgbe_fdir_filter *fdir_filter;
1385 if (fdir_info->hash_map)
1386 rte_free(fdir_info->hash_map);
1387 if (fdir_info->hash_handle)
1388 rte_hash_free(fdir_info->hash_handle);
1390 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1391 TAILQ_REMOVE(&fdir_info->fdir_list,
1394 rte_free(fdir_filter);
1400 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1402 struct ixgbe_l2_tn_info *l2_tn_info =
1403 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1404 struct ixgbe_l2_tn_filter *l2_tn_filter;
1406 if (l2_tn_info->hash_map)
1407 rte_free(l2_tn_info->hash_map);
1408 if (l2_tn_info->hash_handle)
1409 rte_hash_free(l2_tn_info->hash_handle);
1411 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1412 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1415 rte_free(l2_tn_filter);
1421 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1423 struct ixgbe_hw_fdir_info *fdir_info =
1424 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1425 char fdir_hash_name[RTE_HASH_NAMESIZE];
1426 struct rte_hash_parameters fdir_hash_params = {
1427 .name = fdir_hash_name,
1428 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1429 .key_len = sizeof(union ixgbe_atr_input),
1430 .hash_func = rte_hash_crc,
1431 .hash_func_init_val = 0,
1432 .socket_id = rte_socket_id(),
1435 TAILQ_INIT(&fdir_info->fdir_list);
1436 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1437 "fdir_%s", eth_dev->device->name);
1438 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1439 if (!fdir_info->hash_handle) {
1440 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1443 fdir_info->hash_map = rte_zmalloc("ixgbe",
1444 sizeof(struct ixgbe_fdir_filter *) *
1445 IXGBE_MAX_FDIR_FILTER_NUM,
1447 if (!fdir_info->hash_map) {
1449 "Failed to allocate memory for fdir hash map!");
1452 fdir_info->mask_added = FALSE;
1457 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1459 struct ixgbe_l2_tn_info *l2_tn_info =
1460 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1461 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1462 struct rte_hash_parameters l2_tn_hash_params = {
1463 .name = l2_tn_hash_name,
1464 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1465 .key_len = sizeof(struct ixgbe_l2_tn_key),
1466 .hash_func = rte_hash_crc,
1467 .hash_func_init_val = 0,
1468 .socket_id = rte_socket_id(),
1471 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1472 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1473 "l2_tn_%s", eth_dev->device->name);
1474 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1475 if (!l2_tn_info->hash_handle) {
1476 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1479 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1480 sizeof(struct ixgbe_l2_tn_filter *) *
1481 IXGBE_MAX_L2_TN_FILTER_NUM,
1483 if (!l2_tn_info->hash_map) {
1485 "Failed to allocate memory for L2 TN hash map!");
1488 l2_tn_info->e_tag_en = FALSE;
1489 l2_tn_info->e_tag_fwd_en = FALSE;
1490 l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1495 * Negotiate mailbox API version with the PF.
1496 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1497 * Then we try to negotiate starting with the most recent one.
1498 * If all negotiation attempts fail, then we will proceed with
1499 * the default one (ixgbe_mbox_api_10).
1502 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1506 /* start with highest supported, proceed down */
1507 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1514 i != RTE_DIM(sup_ver) &&
1515 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1521 generate_random_mac_addr(struct ether_addr *mac_addr)
1525 /* Set Organizationally Unique Identifier (OUI) prefix. */
1526 mac_addr->addr_bytes[0] = 0x00;
1527 mac_addr->addr_bytes[1] = 0x09;
1528 mac_addr->addr_bytes[2] = 0xC0;
1529 /* Force indication of locally assigned MAC address. */
1530 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1531 /* Generate the last 3 bytes of the MAC address with a random number. */
1532 random = rte_rand();
1533 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1537 * Virtual Function device init
1540 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1544 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1545 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1546 struct ixgbe_hw *hw =
1547 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1548 struct ixgbe_vfta *shadow_vfta =
1549 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1550 struct ixgbe_hwstrip *hwstrip =
1551 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1552 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1554 PMD_INIT_FUNC_TRACE();
1556 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1557 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1558 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1560 /* for secondary processes, we don't initialise any further as primary
1561 * has already done this work. Only check we don't need a different
1564 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1565 struct ixgbe_tx_queue *txq;
1566 /* TX queue function in primary, set by last queue initialized
1567 * Tx queue may not initialized by primary process
1569 if (eth_dev->data->tx_queues) {
1570 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1571 ixgbe_set_tx_function(eth_dev, txq);
1573 /* Use default TX function if we get here */
1574 PMD_INIT_LOG(NOTICE,
1575 "No TX queues configured yet. Using default TX function.");
1578 ixgbe_set_rx_function(eth_dev);
1583 rte_eth_copy_pci_info(eth_dev, pci_dev);
1585 hw->device_id = pci_dev->id.device_id;
1586 hw->vendor_id = pci_dev->id.vendor_id;
1587 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1589 /* initialize the vfta */
1590 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1592 /* initialize the hw strip bitmap*/
1593 memset(hwstrip, 0, sizeof(*hwstrip));
1595 /* Initialize the shared code (base driver) */
1596 diag = ixgbe_init_shared_code(hw);
1597 if (diag != IXGBE_SUCCESS) {
1598 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1602 /* init_mailbox_params */
1603 hw->mbx.ops.init_params(hw);
1605 /* Reset the hw statistics */
1606 ixgbevf_dev_stats_reset(eth_dev);
1608 /* Disable the interrupts for VF */
1609 ixgbevf_intr_disable(hw);
1611 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1612 diag = hw->mac.ops.reset_hw(hw);
1615 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1616 * the underlying PF driver has not assigned a MAC address to the VF.
1617 * In this case, assign a random MAC address.
1619 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1620 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1624 /* negotiate mailbox API version to use with the PF. */
1625 ixgbevf_negotiate_api(hw);
1627 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1628 ixgbevf_get_queues(hw, &tcs, &tc);
1630 /* Allocate memory for storing MAC addresses */
1631 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1632 hw->mac.num_rar_entries, 0);
1633 if (eth_dev->data->mac_addrs == NULL) {
1635 "Failed to allocate %u bytes needed to store "
1637 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1641 /* Generate a random MAC address, if none was assigned by PF. */
1642 if (is_zero_ether_addr(perm_addr)) {
1643 generate_random_mac_addr(perm_addr);
1644 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1646 rte_free(eth_dev->data->mac_addrs);
1647 eth_dev->data->mac_addrs = NULL;
1650 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1651 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1652 "%02x:%02x:%02x:%02x:%02x:%02x",
1653 perm_addr->addr_bytes[0],
1654 perm_addr->addr_bytes[1],
1655 perm_addr->addr_bytes[2],
1656 perm_addr->addr_bytes[3],
1657 perm_addr->addr_bytes[4],
1658 perm_addr->addr_bytes[5]);
1661 /* Copy the permanent MAC address */
1662 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1664 /* reset the hardware with the new settings */
1665 diag = hw->mac.ops.start_hw(hw);
1671 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1675 rte_intr_callback_register(intr_handle,
1676 ixgbevf_dev_interrupt_handler, eth_dev);
1677 rte_intr_enable(intr_handle);
1678 ixgbevf_intr_enable(hw);
1680 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1681 eth_dev->data->port_id, pci_dev->id.vendor_id,
1682 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1687 /* Virtual Function device uninit */
1690 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1692 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1693 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1694 struct ixgbe_hw *hw;
1696 PMD_INIT_FUNC_TRACE();
1698 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1701 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1703 if (hw->adapter_stopped == 0)
1704 ixgbevf_dev_close(eth_dev);
1706 eth_dev->dev_ops = NULL;
1707 eth_dev->rx_pkt_burst = NULL;
1708 eth_dev->tx_pkt_burst = NULL;
1710 /* Disable the interrupts for VF */
1711 ixgbevf_intr_disable(hw);
1713 rte_free(eth_dev->data->mac_addrs);
1714 eth_dev->data->mac_addrs = NULL;
1716 rte_intr_disable(intr_handle);
1717 rte_intr_callback_unregister(intr_handle,
1718 ixgbevf_dev_interrupt_handler, eth_dev);
1723 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1724 struct rte_pci_device *pci_dev)
1726 return rte_eth_dev_pci_generic_probe(pci_dev,
1727 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1730 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1732 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1735 static struct rte_pci_driver rte_ixgbe_pmd = {
1736 .id_table = pci_id_ixgbe_map,
1737 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1738 RTE_PCI_DRV_IOVA_AS_VA,
1739 .probe = eth_ixgbe_pci_probe,
1740 .remove = eth_ixgbe_pci_remove,
1743 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1744 struct rte_pci_device *pci_dev)
1746 return rte_eth_dev_pci_generic_probe(pci_dev,
1747 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1750 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1752 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1756 * virtual function driver struct
1758 static struct rte_pci_driver rte_ixgbevf_pmd = {
1759 .id_table = pci_id_ixgbevf_map,
1760 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1761 .probe = eth_ixgbevf_pci_probe,
1762 .remove = eth_ixgbevf_pci_remove,
1766 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1768 struct ixgbe_hw *hw =
1769 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770 struct ixgbe_vfta *shadow_vfta =
1771 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1776 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1777 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1778 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1783 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1785 /* update local VFTA copy */
1786 shadow_vfta->vfta[vid_idx] = vfta;
1792 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1795 ixgbe_vlan_hw_strip_enable(dev, queue);
1797 ixgbe_vlan_hw_strip_disable(dev, queue);
1801 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1802 enum rte_vlan_type vlan_type,
1805 struct ixgbe_hw *hw =
1806 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1811 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1812 qinq &= IXGBE_DMATXCTL_GDV;
1814 switch (vlan_type) {
1815 case ETH_VLAN_TYPE_INNER:
1817 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1818 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1819 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1820 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1821 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1822 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1823 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1826 PMD_DRV_LOG(ERR, "Inner type is not supported"
1830 case ETH_VLAN_TYPE_OUTER:
1832 /* Only the high 16-bits is valid */
1833 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1834 IXGBE_EXVET_VET_EXT_SHIFT);
1836 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1837 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1838 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1839 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1840 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1841 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1842 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1848 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1856 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1858 struct ixgbe_hw *hw =
1859 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862 PMD_INIT_FUNC_TRACE();
1864 /* Filter Table Disable */
1865 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1866 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1868 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1872 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1874 struct ixgbe_hw *hw =
1875 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876 struct ixgbe_vfta *shadow_vfta =
1877 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1881 PMD_INIT_FUNC_TRACE();
1883 /* Filter Table Enable */
1884 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1885 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1886 vlnctrl |= IXGBE_VLNCTRL_VFE;
1888 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1890 /* write whatever is in local vfta copy */
1891 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1892 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1896 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1898 struct ixgbe_hwstrip *hwstrip =
1899 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1900 struct ixgbe_rx_queue *rxq;
1902 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1906 IXGBE_SET_HWSTRIP(hwstrip, queue);
1908 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1910 if (queue >= dev->data->nb_rx_queues)
1913 rxq = dev->data->rx_queues[queue];
1916 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1918 rxq->vlan_flags = PKT_RX_VLAN;
1922 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1924 struct ixgbe_hw *hw =
1925 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928 PMD_INIT_FUNC_TRACE();
1930 if (hw->mac.type == ixgbe_mac_82598EB) {
1931 /* No queue level support */
1932 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1936 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1937 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1938 ctrl &= ~IXGBE_RXDCTL_VME;
1939 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1941 /* record those setting for HW strip per queue */
1942 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1946 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1948 struct ixgbe_hw *hw =
1949 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952 PMD_INIT_FUNC_TRACE();
1954 if (hw->mac.type == ixgbe_mac_82598EB) {
1955 /* No queue level supported */
1956 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1960 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1961 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1962 ctrl |= IXGBE_RXDCTL_VME;
1963 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1965 /* record those setting for HW strip per queue */
1966 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1970 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1972 struct ixgbe_hw *hw =
1973 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1976 PMD_INIT_FUNC_TRACE();
1978 /* DMATXCTRL: Geric Double VLAN Disable */
1979 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1980 ctrl &= ~IXGBE_DMATXCTL_GDV;
1981 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1983 /* CTRL_EXT: Global Double VLAN Disable */
1984 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1985 ctrl &= ~IXGBE_EXTENDED_VLAN;
1986 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1991 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1993 struct ixgbe_hw *hw =
1994 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997 PMD_INIT_FUNC_TRACE();
1999 /* DMATXCTRL: Geric Double VLAN Enable */
2000 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2001 ctrl |= IXGBE_DMATXCTL_GDV;
2002 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2004 /* CTRL_EXT: Global Double VLAN Enable */
2005 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2006 ctrl |= IXGBE_EXTENDED_VLAN;
2007 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2009 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2010 if (hw->mac.type == ixgbe_mac_X550 ||
2011 hw->mac.type == ixgbe_mac_X550EM_x ||
2012 hw->mac.type == ixgbe_mac_X550EM_a) {
2013 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2014 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2015 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2019 * VET EXT field in the EXVET register = 0x8100 by default
2020 * So no need to change. Same to VT field of DMATXCTL register
2025 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2027 struct ixgbe_hw *hw =
2028 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2032 struct ixgbe_rx_queue *rxq;
2035 PMD_INIT_FUNC_TRACE();
2037 if (hw->mac.type == ixgbe_mac_82598EB) {
2038 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2039 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2040 ctrl |= IXGBE_VLNCTRL_VME;
2041 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2043 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2044 ctrl &= ~IXGBE_VLNCTRL_VME;
2045 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2049 * Other 10G NIC, the VLAN strip can be setup
2050 * per queue in RXDCTL
2052 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2053 rxq = dev->data->rx_queues[i];
2054 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2055 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2056 ctrl |= IXGBE_RXDCTL_VME;
2059 ctrl &= ~IXGBE_RXDCTL_VME;
2062 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2064 /* record those setting for HW strip per queue */
2065 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2071 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2073 struct rte_eth_rxmode *rxmode;
2074 rxmode = &dev->data->dev_conf.rxmode;
2076 if (mask & ETH_VLAN_STRIP_MASK) {
2077 ixgbe_vlan_hw_strip_config(dev);
2080 if (mask & ETH_VLAN_FILTER_MASK) {
2081 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2082 ixgbe_vlan_hw_filter_enable(dev);
2084 ixgbe_vlan_hw_filter_disable(dev);
2087 if (mask & ETH_VLAN_EXTEND_MASK) {
2088 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2089 ixgbe_vlan_hw_extend_enable(dev);
2091 ixgbe_vlan_hw_extend_disable(dev);
2098 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2100 struct ixgbe_hw *hw =
2101 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2103 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2105 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2106 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2110 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2112 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2117 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2120 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2126 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2127 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2128 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2129 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2134 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2136 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2137 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2138 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2139 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2141 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2142 /* check multi-queue mode */
2143 switch (dev_conf->rxmode.mq_mode) {
2144 case ETH_MQ_RX_VMDQ_DCB:
2145 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2147 case ETH_MQ_RX_VMDQ_DCB_RSS:
2148 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2149 PMD_INIT_LOG(ERR, "SRIOV active,"
2150 " unsupported mq_mode rx %d.",
2151 dev_conf->rxmode.mq_mode);
2154 case ETH_MQ_RX_VMDQ_RSS:
2155 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2156 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2157 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2158 PMD_INIT_LOG(ERR, "SRIOV is active,"
2159 " invalid queue number"
2160 " for VMDQ RSS, allowed"
2161 " value are 1, 2 or 4.");
2165 case ETH_MQ_RX_VMDQ_ONLY:
2166 case ETH_MQ_RX_NONE:
2167 /* if nothing mq mode configure, use default scheme */
2168 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2170 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2171 /* SRIOV only works in VMDq enable mode */
2172 PMD_INIT_LOG(ERR, "SRIOV is active,"
2173 " wrong mq_mode rx %d.",
2174 dev_conf->rxmode.mq_mode);
2178 switch (dev_conf->txmode.mq_mode) {
2179 case ETH_MQ_TX_VMDQ_DCB:
2180 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2181 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2183 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2184 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2188 /* check valid queue number */
2189 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2190 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2191 PMD_INIT_LOG(ERR, "SRIOV is active,"
2192 " nb_rx_q=%d nb_tx_q=%d queue number"
2193 " must be less than or equal to %d.",
2195 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2199 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2200 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2204 /* check configuration for vmdb+dcb mode */
2205 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2206 const struct rte_eth_vmdq_dcb_conf *conf;
2208 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2209 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2210 IXGBE_VMDQ_DCB_NB_QUEUES);
2213 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2214 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2215 conf->nb_queue_pools == ETH_32_POOLS)) {
2216 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2217 " nb_queue_pools must be %d or %d.",
2218 ETH_16_POOLS, ETH_32_POOLS);
2222 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2223 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2225 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2226 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2227 IXGBE_VMDQ_DCB_NB_QUEUES);
2230 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2231 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2232 conf->nb_queue_pools == ETH_32_POOLS)) {
2233 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2234 " nb_queue_pools != %d and"
2235 " nb_queue_pools != %d.",
2236 ETH_16_POOLS, ETH_32_POOLS);
2241 /* For DCB mode check our configuration before we go further */
2242 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2243 const struct rte_eth_dcb_rx_conf *conf;
2245 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2246 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2247 IXGBE_DCB_NB_QUEUES);
2250 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2251 if (!(conf->nb_tcs == ETH_4_TCS ||
2252 conf->nb_tcs == ETH_8_TCS)) {
2253 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2254 " and nb_tcs != %d.",
2255 ETH_4_TCS, ETH_8_TCS);
2260 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2261 const struct rte_eth_dcb_tx_conf *conf;
2263 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2264 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2265 IXGBE_DCB_NB_QUEUES);
2268 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2269 if (!(conf->nb_tcs == ETH_4_TCS ||
2270 conf->nb_tcs == ETH_8_TCS)) {
2271 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2272 " and nb_tcs != %d.",
2273 ETH_4_TCS, ETH_8_TCS);
2279 * When DCB/VT is off, maximum number of queues changes,
2280 * except for 82598EB, which remains constant.
2282 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2283 hw->mac.type != ixgbe_mac_82598EB) {
2284 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2286 "Neither VT nor DCB are enabled, "
2288 IXGBE_NONE_MODE_TX_NB_QUEUES);
2297 ixgbe_dev_configure(struct rte_eth_dev *dev)
2299 struct ixgbe_interrupt *intr =
2300 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2301 struct ixgbe_adapter *adapter =
2302 (struct ixgbe_adapter *)dev->data->dev_private;
2303 struct rte_eth_dev_info dev_info;
2304 uint64_t rx_offloads;
2305 uint64_t tx_offloads;
2308 PMD_INIT_FUNC_TRACE();
2309 /* multipe queue mode checking */
2310 ret = ixgbe_check_mq_mode(dev);
2312 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2317 ixgbe_dev_info_get(dev, &dev_info);
2318 rx_offloads = dev->data->dev_conf.rxmode.offloads;
2319 if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2320 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2321 "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2322 rx_offloads, dev_info.rx_offload_capa);
2325 tx_offloads = dev->data->dev_conf.txmode.offloads;
2326 if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2327 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2328 "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2329 tx_offloads, dev_info.tx_offload_capa);
2333 /* set flag to update link status after init */
2334 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2337 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2338 * allocation or vector Rx preconditions we will reset it.
2340 adapter->rx_bulk_alloc_allowed = true;
2341 adapter->rx_vec_allowed = true;
2347 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2349 struct ixgbe_hw *hw =
2350 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351 struct ixgbe_interrupt *intr =
2352 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2355 /* only set up it on X550EM_X */
2356 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2357 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2358 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2359 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2360 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2361 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2366 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2367 uint16_t tx_rate, uint64_t q_msk)
2369 struct ixgbe_hw *hw;
2370 struct ixgbe_vf_info *vfinfo;
2371 struct rte_eth_link link;
2372 uint8_t nb_q_per_pool;
2373 uint32_t queue_stride;
2374 uint32_t queue_idx, idx = 0, vf_idx;
2376 uint16_t total_rate = 0;
2377 struct rte_pci_device *pci_dev;
2379 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2380 rte_eth_link_get_nowait(dev->data->port_id, &link);
2382 if (vf >= pci_dev->max_vfs)
2385 if (tx_rate > link.link_speed)
2391 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2393 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2394 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2395 queue_idx = vf * queue_stride;
2396 queue_end = queue_idx + nb_q_per_pool - 1;
2397 if (queue_end >= hw->mac.max_tx_queues)
2401 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2404 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2406 total_rate += vfinfo[vf_idx].tx_rate[idx];
2412 /* Store tx_rate for this vf. */
2413 for (idx = 0; idx < nb_q_per_pool; idx++) {
2414 if (((uint64_t)0x1 << idx) & q_msk) {
2415 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2416 vfinfo[vf].tx_rate[idx] = tx_rate;
2417 total_rate += tx_rate;
2421 if (total_rate > dev->data->dev_link.link_speed) {
2422 /* Reset stored TX rate of the VF if it causes exceed
2425 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2429 /* Set RTTBCNRC of each queue/pool for vf X */
2430 for (; queue_idx <= queue_end; queue_idx++) {
2432 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2440 * Configure device link speed and setup link.
2441 * It returns 0 on success.
2444 ixgbe_dev_start(struct rte_eth_dev *dev)
2446 struct ixgbe_hw *hw =
2447 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2448 struct ixgbe_vf_info *vfinfo =
2449 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2450 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2451 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2452 uint32_t intr_vector = 0;
2453 int err, link_up = 0, negotiate = 0;
2455 uint32_t allowed_speeds = 0;
2459 uint32_t *link_speeds;
2460 struct ixgbe_tm_conf *tm_conf =
2461 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2463 PMD_INIT_FUNC_TRACE();
2465 /* IXGBE devices don't support:
2466 * - half duplex (checked afterwards for valid speeds)
2467 * - fixed speed: TODO implement
2469 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2471 "Invalid link_speeds for port %u, fix speed not supported",
2472 dev->data->port_id);
2476 /* disable uio/vfio intr/eventfd mapping */
2477 rte_intr_disable(intr_handle);
2480 hw->adapter_stopped = 0;
2481 ixgbe_stop_adapter(hw);
2483 /* reinitialize adapter
2484 * this calls reset and start
2486 status = ixgbe_pf_reset_hw(hw);
2489 hw->mac.ops.start_hw(hw);
2490 hw->mac.get_link_status = true;
2492 /* configure PF module if SRIOV enabled */
2493 ixgbe_pf_host_configure(dev);
2495 ixgbe_dev_phy_intr_setup(dev);
2497 /* check and configure queue intr-vector mapping */
2498 if ((rte_intr_cap_multiple(intr_handle) ||
2499 !RTE_ETH_DEV_SRIOV(dev).active) &&
2500 dev->data->dev_conf.intr_conf.rxq != 0) {
2501 intr_vector = dev->data->nb_rx_queues;
2502 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2503 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2504 IXGBE_MAX_INTR_QUEUE_NUM);
2507 if (rte_intr_efd_enable(intr_handle, intr_vector))
2511 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2512 intr_handle->intr_vec =
2513 rte_zmalloc("intr_vec",
2514 dev->data->nb_rx_queues * sizeof(int), 0);
2515 if (intr_handle->intr_vec == NULL) {
2516 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2517 " intr_vec", dev->data->nb_rx_queues);
2522 /* confiugre msix for sleep until rx interrupt */
2523 ixgbe_configure_msix(dev);
2525 /* initialize transmission unit */
2526 ixgbe_dev_tx_init(dev);
2528 /* This can fail when allocating mbufs for descriptor rings */
2529 err = ixgbe_dev_rx_init(dev);
2531 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2535 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2536 ETH_VLAN_EXTEND_MASK;
2537 err = ixgbe_vlan_offload_set(dev, mask);
2539 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2543 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2544 /* Enable vlan filtering for VMDq */
2545 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2548 /* Configure DCB hw */
2549 ixgbe_configure_dcb(dev);
2551 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2552 err = ixgbe_fdir_configure(dev);
2557 /* Restore vf rate limit */
2558 if (vfinfo != NULL) {
2559 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2560 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2561 if (vfinfo[vf].tx_rate[idx] != 0)
2562 ixgbe_set_vf_rate_limit(
2564 vfinfo[vf].tx_rate[idx],
2568 ixgbe_restore_statistics_mapping(dev);
2570 err = ixgbe_dev_rxtx_start(dev);
2572 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2576 /* Skip link setup if loopback mode is enabled for 82599. */
2577 if (hw->mac.type == ixgbe_mac_82599EB &&
2578 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2579 goto skip_link_setup;
2581 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2582 err = hw->mac.ops.setup_sfp(hw);
2587 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2588 /* Turn on the copper */
2589 ixgbe_set_phy_power(hw, true);
2591 /* Turn on the laser */
2592 ixgbe_enable_tx_laser(hw);
2595 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2598 dev->data->dev_link.link_status = link_up;
2600 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2604 switch (hw->mac.type) {
2605 case ixgbe_mac_X550:
2606 case ixgbe_mac_X550EM_x:
2607 case ixgbe_mac_X550EM_a:
2608 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2609 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2613 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2617 link_speeds = &dev->data->dev_conf.link_speeds;
2618 if (*link_speeds & ~allowed_speeds) {
2619 PMD_INIT_LOG(ERR, "Invalid link setting");
2624 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2625 switch (hw->mac.type) {
2626 case ixgbe_mac_82598EB:
2627 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2629 case ixgbe_mac_82599EB:
2630 case ixgbe_mac_X540:
2631 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2633 case ixgbe_mac_X550:
2634 case ixgbe_mac_X550EM_x:
2635 case ixgbe_mac_X550EM_a:
2636 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2639 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2642 if (*link_speeds & ETH_LINK_SPEED_10G)
2643 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2644 if (*link_speeds & ETH_LINK_SPEED_5G)
2645 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2646 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2647 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2648 if (*link_speeds & ETH_LINK_SPEED_1G)
2649 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2650 if (*link_speeds & ETH_LINK_SPEED_100M)
2651 speed |= IXGBE_LINK_SPEED_100_FULL;
2654 err = ixgbe_setup_link(hw, speed, link_up);
2658 ixgbe_dev_link_update(dev, 0);
2662 if (rte_intr_allow_others(intr_handle)) {
2663 /* check if lsc interrupt is enabled */
2664 if (dev->data->dev_conf.intr_conf.lsc != 0)
2665 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2667 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2668 ixgbe_dev_macsec_interrupt_setup(dev);
2670 rte_intr_callback_unregister(intr_handle,
2671 ixgbe_dev_interrupt_handler, dev);
2672 if (dev->data->dev_conf.intr_conf.lsc != 0)
2673 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2674 " no intr multiplex");
2677 /* check if rxq interrupt is enabled */
2678 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2679 rte_intr_dp_is_en(intr_handle))
2680 ixgbe_dev_rxq_interrupt_setup(dev);
2682 /* enable uio/vfio intr/eventfd mapping */
2683 rte_intr_enable(intr_handle);
2685 /* resume enabled intr since hw reset */
2686 ixgbe_enable_intr(dev);
2687 ixgbe_l2_tunnel_conf(dev);
2688 ixgbe_filter_restore(dev);
2690 if (tm_conf->root && !tm_conf->committed)
2691 PMD_DRV_LOG(WARNING,
2692 "please call hierarchy_commit() "
2693 "before starting the port");
2698 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2699 ixgbe_dev_clear_queues(dev);
2704 * Stop device: disable rx and tx functions to allow for reconfiguring.
2707 ixgbe_dev_stop(struct rte_eth_dev *dev)
2709 struct rte_eth_link link;
2710 struct ixgbe_hw *hw =
2711 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712 struct ixgbe_vf_info *vfinfo =
2713 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2714 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2715 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2717 struct ixgbe_tm_conf *tm_conf =
2718 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2720 PMD_INIT_FUNC_TRACE();
2722 /* disable interrupts */
2723 ixgbe_disable_intr(hw);
2726 ixgbe_pf_reset_hw(hw);
2727 hw->adapter_stopped = 0;
2730 ixgbe_stop_adapter(hw);
2732 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2733 vfinfo[vf].clear_to_send = false;
2735 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2736 /* Turn off the copper */
2737 ixgbe_set_phy_power(hw, false);
2739 /* Turn off the laser */
2740 ixgbe_disable_tx_laser(hw);
2743 ixgbe_dev_clear_queues(dev);
2745 /* Clear stored conf */
2746 dev->data->scattered_rx = 0;
2749 /* Clear recorded link status */
2750 memset(&link, 0, sizeof(link));
2751 rte_eth_linkstatus_set(dev, &link);
2753 if (!rte_intr_allow_others(intr_handle))
2754 /* resume to the default handler */
2755 rte_intr_callback_register(intr_handle,
2756 ixgbe_dev_interrupt_handler,
2759 /* Clean datapath event and queue/vec mapping */
2760 rte_intr_efd_disable(intr_handle);
2761 if (intr_handle->intr_vec != NULL) {
2762 rte_free(intr_handle->intr_vec);
2763 intr_handle->intr_vec = NULL;
2766 /* reset hierarchy commit */
2767 tm_conf->committed = false;
2771 * Set device link up: enable tx.
2774 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2776 struct ixgbe_hw *hw =
2777 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778 if (hw->mac.type == ixgbe_mac_82599EB) {
2779 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2780 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2781 /* Not suported in bypass mode */
2782 PMD_INIT_LOG(ERR, "Set link up is not supported "
2783 "by device id 0x%x", hw->device_id);
2789 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2790 /* Turn on the copper */
2791 ixgbe_set_phy_power(hw, true);
2793 /* Turn on the laser */
2794 ixgbe_enable_tx_laser(hw);
2801 * Set device link down: disable tx.
2804 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2806 struct ixgbe_hw *hw =
2807 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808 if (hw->mac.type == ixgbe_mac_82599EB) {
2809 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2810 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2811 /* Not suported in bypass mode */
2812 PMD_INIT_LOG(ERR, "Set link down is not supported "
2813 "by device id 0x%x", hw->device_id);
2819 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2820 /* Turn off the copper */
2821 ixgbe_set_phy_power(hw, false);
2823 /* Turn off the laser */
2824 ixgbe_disable_tx_laser(hw);
2831 * Reset and stop device.
2834 ixgbe_dev_close(struct rte_eth_dev *dev)
2836 struct ixgbe_hw *hw =
2837 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839 PMD_INIT_FUNC_TRACE();
2841 ixgbe_pf_reset_hw(hw);
2843 ixgbe_dev_stop(dev);
2844 hw->adapter_stopped = 1;
2846 ixgbe_dev_free_queues(dev);
2848 ixgbe_disable_pcie_master(hw);
2850 /* reprogram the RAR[0] in case user changed it. */
2851 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2858 ixgbe_dev_reset(struct rte_eth_dev *dev)
2862 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2863 * its VF to make them align with it. The detailed notification
2864 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2865 * To avoid unexpected behavior in VF, currently reset of PF with
2866 * SR-IOV activation is not supported. It might be supported later.
2868 if (dev->data->sriov.active)
2871 ret = eth_ixgbe_dev_uninit(dev);
2875 ret = eth_ixgbe_dev_init(dev);
2881 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2882 struct ixgbe_hw_stats *hw_stats,
2883 struct ixgbe_macsec_stats *macsec_stats,
2884 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2885 uint64_t *total_qprc, uint64_t *total_qprdc)
2887 uint32_t bprc, lxon, lxoff, total;
2888 uint32_t delta_gprc = 0;
2890 /* Workaround for RX byte count not including CRC bytes when CRC
2891 * strip is enabled. CRC bytes are removed from counters when crc_strip
2894 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2895 IXGBE_HLREG0_RXCRCSTRP);
2897 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2898 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2899 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2900 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2902 for (i = 0; i < 8; i++) {
2903 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2905 /* global total per queue */
2906 hw_stats->mpc[i] += mp;
2907 /* Running comprehensive total for stats display */
2908 *total_missed_rx += hw_stats->mpc[i];
2909 if (hw->mac.type == ixgbe_mac_82598EB) {
2910 hw_stats->rnbc[i] +=
2911 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2912 hw_stats->pxonrxc[i] +=
2913 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2914 hw_stats->pxoffrxc[i] +=
2915 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2917 hw_stats->pxonrxc[i] +=
2918 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2919 hw_stats->pxoffrxc[i] +=
2920 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2921 hw_stats->pxon2offc[i] +=
2922 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2924 hw_stats->pxontxc[i] +=
2925 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2926 hw_stats->pxofftxc[i] +=
2927 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2929 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2930 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2931 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2932 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2934 delta_gprc += delta_qprc;
2936 hw_stats->qprc[i] += delta_qprc;
2937 hw_stats->qptc[i] += delta_qptc;
2939 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2940 hw_stats->qbrc[i] +=
2941 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2943 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2945 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2946 hw_stats->qbtc[i] +=
2947 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2949 hw_stats->qprdc[i] += delta_qprdc;
2950 *total_qprdc += hw_stats->qprdc[i];
2952 *total_qprc += hw_stats->qprc[i];
2953 *total_qbrc += hw_stats->qbrc[i];
2955 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2956 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2957 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2960 * An errata states that gprc actually counts good + missed packets:
2961 * Workaround to set gprc to summated queue packet receives
2963 hw_stats->gprc = *total_qprc;
2965 if (hw->mac.type != ixgbe_mac_82598EB) {
2966 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2967 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2968 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2969 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2970 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2971 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2972 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2973 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2975 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2976 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2977 /* 82598 only has a counter in the high register */
2978 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2979 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2980 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2982 uint64_t old_tpr = hw_stats->tpr;
2984 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2985 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2988 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2990 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2991 hw_stats->gptc += delta_gptc;
2992 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2993 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2996 * Workaround: mprc hardware is incorrectly counting
2997 * broadcasts, so for now we subtract those.
2999 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3000 hw_stats->bprc += bprc;
3001 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3002 if (hw->mac.type == ixgbe_mac_82598EB)
3003 hw_stats->mprc -= bprc;
3005 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3006 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3007 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3008 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3009 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3010 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3012 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3013 hw_stats->lxontxc += lxon;
3014 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3015 hw_stats->lxofftxc += lxoff;
3016 total = lxon + lxoff;
3018 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3019 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3020 hw_stats->gptc -= total;
3021 hw_stats->mptc -= total;
3022 hw_stats->ptc64 -= total;
3023 hw_stats->gotc -= total * ETHER_MIN_LEN;
3025 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3026 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3027 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3028 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3029 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3030 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3031 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3032 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3033 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3034 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3035 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3036 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3037 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3038 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3039 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3040 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3041 /* Only read FCOE on 82599 */
3042 if (hw->mac.type != ixgbe_mac_82598EB) {
3043 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3044 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3045 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3046 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3047 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3050 /* Flow Director Stats registers */
3051 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3052 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3054 /* MACsec Stats registers */
3055 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3056 macsec_stats->out_pkts_encrypted +=
3057 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3058 macsec_stats->out_pkts_protected +=
3059 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3060 macsec_stats->out_octets_encrypted +=
3061 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3062 macsec_stats->out_octets_protected +=
3063 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3064 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3065 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3066 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3067 macsec_stats->in_pkts_unknownsci +=
3068 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3069 macsec_stats->in_octets_decrypted +=
3070 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3071 macsec_stats->in_octets_validated +=
3072 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3073 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3074 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3075 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3076 for (i = 0; i < 2; i++) {
3077 macsec_stats->in_pkts_ok +=
3078 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3079 macsec_stats->in_pkts_invalid +=
3080 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3081 macsec_stats->in_pkts_notvalid +=
3082 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3084 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3085 macsec_stats->in_pkts_notusingsa +=
3086 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3090 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3093 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3095 struct ixgbe_hw *hw =
3096 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3097 struct ixgbe_hw_stats *hw_stats =
3098 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3099 struct ixgbe_macsec_stats *macsec_stats =
3100 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3101 dev->data->dev_private);
3102 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3105 total_missed_rx = 0;
3110 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3111 &total_qbrc, &total_qprc, &total_qprdc);
3116 /* Fill out the rte_eth_stats statistics structure */
3117 stats->ipackets = total_qprc;
3118 stats->ibytes = total_qbrc;
3119 stats->opackets = hw_stats->gptc;
3120 stats->obytes = hw_stats->gotc;
3122 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3123 stats->q_ipackets[i] = hw_stats->qprc[i];
3124 stats->q_opackets[i] = hw_stats->qptc[i];
3125 stats->q_ibytes[i] = hw_stats->qbrc[i];
3126 stats->q_obytes[i] = hw_stats->qbtc[i];
3127 stats->q_errors[i] = hw_stats->qprdc[i];
3131 stats->imissed = total_missed_rx;
3132 stats->ierrors = hw_stats->crcerrs +
3149 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3151 struct ixgbe_hw_stats *stats =
3152 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3154 /* HW registers are cleared on read */
3155 ixgbe_dev_stats_get(dev, NULL);
3157 /* Reset software totals */
3158 memset(stats, 0, sizeof(*stats));
3161 /* This function calculates the number of xstats based on the current config */
3163 ixgbe_xstats_calc_num(void) {
3164 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3165 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3166 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3169 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3170 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3172 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3173 unsigned stat, i, count;
3175 if (xstats_names != NULL) {
3178 /* Note: limit >= cnt_stats checked upstream
3179 * in rte_eth_xstats_names()
3182 /* Extended stats from ixgbe_hw_stats */
3183 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3184 snprintf(xstats_names[count].name,
3185 sizeof(xstats_names[count].name),
3187 rte_ixgbe_stats_strings[i].name);
3192 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3193 snprintf(xstats_names[count].name,
3194 sizeof(xstats_names[count].name),
3196 rte_ixgbe_macsec_strings[i].name);
3200 /* RX Priority Stats */
3201 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3202 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3203 snprintf(xstats_names[count].name,
3204 sizeof(xstats_names[count].name),
3205 "rx_priority%u_%s", i,
3206 rte_ixgbe_rxq_strings[stat].name);
3211 /* TX Priority Stats */
3212 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3213 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3214 snprintf(xstats_names[count].name,
3215 sizeof(xstats_names[count].name),
3216 "tx_priority%u_%s", i,
3217 rte_ixgbe_txq_strings[stat].name);
3225 static int ixgbe_dev_xstats_get_names_by_id(
3226 struct rte_eth_dev *dev,
3227 struct rte_eth_xstat_name *xstats_names,
3228 const uint64_t *ids,
3232 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3233 unsigned int stat, i, count;
3235 if (xstats_names != NULL) {
3238 /* Note: limit >= cnt_stats checked upstream
3239 * in rte_eth_xstats_names()
3242 /* Extended stats from ixgbe_hw_stats */
3243 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3244 snprintf(xstats_names[count].name,
3245 sizeof(xstats_names[count].name),
3247 rte_ixgbe_stats_strings[i].name);
3252 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3253 snprintf(xstats_names[count].name,
3254 sizeof(xstats_names[count].name),
3256 rte_ixgbe_macsec_strings[i].name);
3260 /* RX Priority Stats */
3261 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3262 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3263 snprintf(xstats_names[count].name,
3264 sizeof(xstats_names[count].name),
3265 "rx_priority%u_%s", i,
3266 rte_ixgbe_rxq_strings[stat].name);
3271 /* TX Priority Stats */
3272 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3273 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3274 snprintf(xstats_names[count].name,
3275 sizeof(xstats_names[count].name),
3276 "tx_priority%u_%s", i,
3277 rte_ixgbe_txq_strings[stat].name);
3286 uint16_t size = ixgbe_xstats_calc_num();
3287 struct rte_eth_xstat_name xstats_names_copy[size];
3289 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3292 for (i = 0; i < limit; i++) {
3293 if (ids[i] >= size) {
3294 PMD_INIT_LOG(ERR, "id value isn't valid");
3297 strcpy(xstats_names[i].name,
3298 xstats_names_copy[ids[i]].name);
3303 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3304 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3308 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3311 if (xstats_names != NULL)
3312 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3313 snprintf(xstats_names[i].name,
3314 sizeof(xstats_names[i].name),
3315 "%s", rte_ixgbevf_stats_strings[i].name);
3316 return IXGBEVF_NB_XSTATS;
3320 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3323 struct ixgbe_hw *hw =
3324 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3325 struct ixgbe_hw_stats *hw_stats =
3326 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3327 struct ixgbe_macsec_stats *macsec_stats =
3328 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3329 dev->data->dev_private);
3330 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3331 unsigned i, stat, count = 0;
3333 count = ixgbe_xstats_calc_num();
3338 total_missed_rx = 0;
3343 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3344 &total_qbrc, &total_qprc, &total_qprdc);
3346 /* If this is a reset xstats is NULL, and we have cleared the
3347 * registers by reading them.
3352 /* Extended stats from ixgbe_hw_stats */
3354 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3355 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3356 rte_ixgbe_stats_strings[i].offset);
3357 xstats[count].id = count;
3362 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3363 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3364 rte_ixgbe_macsec_strings[i].offset);
3365 xstats[count].id = count;
3369 /* RX Priority Stats */
3370 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3371 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3372 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3373 rte_ixgbe_rxq_strings[stat].offset +
3374 (sizeof(uint64_t) * i));
3375 xstats[count].id = count;
3380 /* TX Priority Stats */
3381 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3382 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3383 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3384 rte_ixgbe_txq_strings[stat].offset +
3385 (sizeof(uint64_t) * i));
3386 xstats[count].id = count;
3394 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3395 uint64_t *values, unsigned int n)
3398 struct ixgbe_hw *hw =
3399 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3400 struct ixgbe_hw_stats *hw_stats =
3401 IXGBE_DEV_PRIVATE_TO_STATS(
3402 dev->data->dev_private);
3403 struct ixgbe_macsec_stats *macsec_stats =
3404 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3405 dev->data->dev_private);
3406 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3407 unsigned int i, stat, count = 0;
3409 count = ixgbe_xstats_calc_num();
3411 if (!ids && n < count)
3414 total_missed_rx = 0;
3419 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3420 &total_missed_rx, &total_qbrc, &total_qprc,
3423 /* If this is a reset xstats is NULL, and we have cleared the
3424 * registers by reading them.
3426 if (!ids && !values)
3429 /* Extended stats from ixgbe_hw_stats */
3431 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3432 values[count] = *(uint64_t *)(((char *)hw_stats) +
3433 rte_ixgbe_stats_strings[i].offset);
3438 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3439 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3440 rte_ixgbe_macsec_strings[i].offset);
3444 /* RX Priority Stats */
3445 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3446 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3448 *(uint64_t *)(((char *)hw_stats) +
3449 rte_ixgbe_rxq_strings[stat].offset +
3450 (sizeof(uint64_t) * i));
3455 /* TX Priority Stats */
3456 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3457 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3459 *(uint64_t *)(((char *)hw_stats) +
3460 rte_ixgbe_txq_strings[stat].offset +
3461 (sizeof(uint64_t) * i));
3469 uint16_t size = ixgbe_xstats_calc_num();
3470 uint64_t values_copy[size];
3472 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3474 for (i = 0; i < n; i++) {
3475 if (ids[i] >= size) {
3476 PMD_INIT_LOG(ERR, "id value isn't valid");
3479 values[i] = values_copy[ids[i]];
3485 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3487 struct ixgbe_hw_stats *stats =
3488 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3489 struct ixgbe_macsec_stats *macsec_stats =
3490 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3491 dev->data->dev_private);
3493 unsigned count = ixgbe_xstats_calc_num();
3495 /* HW registers are cleared on read */
3496 ixgbe_dev_xstats_get(dev, NULL, count);
3498 /* Reset software totals */
3499 memset(stats, 0, sizeof(*stats));
3500 memset(macsec_stats, 0, sizeof(*macsec_stats));
3504 ixgbevf_update_stats(struct rte_eth_dev *dev)
3506 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3507 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3508 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3510 /* Good Rx packet, include VF loopback */
3511 UPDATE_VF_STAT(IXGBE_VFGPRC,
3512 hw_stats->last_vfgprc, hw_stats->vfgprc);
3514 /* Good Rx octets, include VF loopback */
3515 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3516 hw_stats->last_vfgorc, hw_stats->vfgorc);
3518 /* Good Tx packet, include VF loopback */
3519 UPDATE_VF_STAT(IXGBE_VFGPTC,
3520 hw_stats->last_vfgptc, hw_stats->vfgptc);
3522 /* Good Tx octets, include VF loopback */
3523 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3524 hw_stats->last_vfgotc, hw_stats->vfgotc);
3526 /* Rx Multicst Packet */
3527 UPDATE_VF_STAT(IXGBE_VFMPRC,
3528 hw_stats->last_vfmprc, hw_stats->vfmprc);
3532 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3535 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3536 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3539 if (n < IXGBEVF_NB_XSTATS)
3540 return IXGBEVF_NB_XSTATS;
3542 ixgbevf_update_stats(dev);
3547 /* Extended stats */
3548 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3550 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3551 rte_ixgbevf_stats_strings[i].offset);
3554 return IXGBEVF_NB_XSTATS;
3558 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3560 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3561 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3563 ixgbevf_update_stats(dev);
3568 stats->ipackets = hw_stats->vfgprc;
3569 stats->ibytes = hw_stats->vfgorc;
3570 stats->opackets = hw_stats->vfgptc;
3571 stats->obytes = hw_stats->vfgotc;
3576 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3578 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3579 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3581 /* Sync HW register to the last stats */
3582 ixgbevf_dev_stats_get(dev, NULL);
3584 /* reset HW current stats*/
3585 hw_stats->vfgprc = 0;
3586 hw_stats->vfgorc = 0;
3587 hw_stats->vfgptc = 0;
3588 hw_stats->vfgotc = 0;
3592 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3594 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3595 u16 eeprom_verh, eeprom_verl;
3599 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3600 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3602 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3603 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3605 ret += 1; /* add the size of '\0' */
3606 if (fw_size < (u32)ret)
3613 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3615 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3616 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3619 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3620 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3621 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3623 * When DCB/VT is off, maximum number of queues changes,
3624 * except for 82598EB, which remains constant.
3626 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3627 hw->mac.type != ixgbe_mac_82598EB)
3628 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3630 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3631 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3632 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3633 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3634 dev_info->max_vfs = pci_dev->max_vfs;
3635 if (hw->mac.type == ixgbe_mac_82598EB)
3636 dev_info->max_vmdq_pools = ETH_16_POOLS;
3638 dev_info->max_vmdq_pools = ETH_64_POOLS;
3639 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3640 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3641 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3642 dev_info->rx_queue_offload_capa);
3643 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3644 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3646 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3648 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3649 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3650 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3652 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3657 dev_info->default_txconf = (struct rte_eth_txconf) {
3659 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3660 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3661 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3663 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3664 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3665 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3666 ETH_TXQ_FLAGS_NOOFFLOADS |
3667 ETH_TXQ_FLAGS_IGNORE,
3671 dev_info->rx_desc_lim = rx_desc_lim;
3672 dev_info->tx_desc_lim = tx_desc_lim;
3674 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3675 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3676 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3678 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3679 if (hw->mac.type == ixgbe_mac_X540 ||
3680 hw->mac.type == ixgbe_mac_X540_vf ||
3681 hw->mac.type == ixgbe_mac_X550 ||
3682 hw->mac.type == ixgbe_mac_X550_vf) {
3683 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3685 if (hw->mac.type == ixgbe_mac_X550) {
3686 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3687 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3691 static const uint32_t *
3692 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3694 static const uint32_t ptypes[] = {
3695 /* For non-vec functions,
3696 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3697 * for vec functions,
3698 * refers to _recv_raw_pkts_vec().
3702 RTE_PTYPE_L3_IPV4_EXT,
3704 RTE_PTYPE_L3_IPV6_EXT,
3708 RTE_PTYPE_TUNNEL_IP,
3709 RTE_PTYPE_INNER_L3_IPV6,
3710 RTE_PTYPE_INNER_L3_IPV6_EXT,
3711 RTE_PTYPE_INNER_L4_TCP,
3712 RTE_PTYPE_INNER_L4_UDP,
3716 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3717 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3718 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3719 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3722 #if defined(RTE_ARCH_X86)
3723 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3724 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3731 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3732 struct rte_eth_dev_info *dev_info)
3734 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3735 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3738 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3739 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3740 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3741 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3742 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3743 dev_info->max_vfs = pci_dev->max_vfs;
3744 if (hw->mac.type == ixgbe_mac_82598EB)
3745 dev_info->max_vmdq_pools = ETH_16_POOLS;
3747 dev_info->max_vmdq_pools = ETH_64_POOLS;
3748 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3749 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3750 dev_info->rx_queue_offload_capa);
3751 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3752 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3754 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3756 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3757 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3758 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3760 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3765 dev_info->default_txconf = (struct rte_eth_txconf) {
3767 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3768 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3769 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3771 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3772 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3773 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3774 ETH_TXQ_FLAGS_NOOFFLOADS |
3775 ETH_TXQ_FLAGS_IGNORE,
3779 dev_info->rx_desc_lim = rx_desc_lim;
3780 dev_info->tx_desc_lim = tx_desc_lim;
3784 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3785 int *link_up, int wait_to_complete)
3788 * for a quick link status checking, wait_to_compelet == 0,
3789 * skip PF link status checking
3791 bool no_pflink_check = wait_to_complete == 0;
3792 struct ixgbe_mbx_info *mbx = &hw->mbx;
3793 struct ixgbe_mac_info *mac = &hw->mac;
3794 uint32_t links_reg, in_msg;
3797 /* If we were hit with a reset drop the link */
3798 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3799 mac->get_link_status = true;
3801 if (!mac->get_link_status)
3804 /* if link status is down no point in checking to see if pf is up */
3805 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3806 if (!(links_reg & IXGBE_LINKS_UP))
3809 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3810 * before the link status is correct
3812 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3815 for (i = 0; i < 5; i++) {
3817 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3819 if (!(links_reg & IXGBE_LINKS_UP))
3824 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3825 case IXGBE_LINKS_SPEED_10G_82599:
3826 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3827 if (hw->mac.type >= ixgbe_mac_X550) {
3828 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3829 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3832 case IXGBE_LINKS_SPEED_1G_82599:
3833 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3835 case IXGBE_LINKS_SPEED_100_82599:
3836 *speed = IXGBE_LINK_SPEED_100_FULL;
3837 if (hw->mac.type == ixgbe_mac_X550) {
3838 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3839 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3842 case IXGBE_LINKS_SPEED_10_X550EM_A:
3843 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3844 /* Since Reserved in older MAC's */
3845 if (hw->mac.type >= ixgbe_mac_X550)
3846 *speed = IXGBE_LINK_SPEED_10_FULL;
3849 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3852 if (no_pflink_check) {
3853 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3854 mac->get_link_status = true;
3856 mac->get_link_status = false;
3860 /* if the read failed it could just be a mailbox collision, best wait
3861 * until we are called again and don't report an error
3863 if (mbx->ops.read(hw, &in_msg, 1, 0))
3866 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3867 /* msg is not CTS and is NACK we must have lost CTS status */
3868 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3873 /* the pf is talking, if we timed out in the past we reinit */
3874 if (!mbx->timeout) {
3879 /* if we passed all the tests above then the link is up and we no
3880 * longer need to check for link
3882 mac->get_link_status = false;
3885 *link_up = !mac->get_link_status;
3889 /* return 0 means link status changed, -1 means not changed */
3891 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3892 int wait_to_complete, int vf)
3894 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3895 struct rte_eth_link link;
3896 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3897 struct ixgbe_interrupt *intr =
3898 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3903 bool autoneg = false;
3905 memset(&link, 0, sizeof(link));
3906 link.link_status = ETH_LINK_DOWN;
3907 link.link_speed = ETH_SPEED_NUM_NONE;
3908 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3909 link.link_autoneg = ETH_LINK_AUTONEG;
3911 hw->mac.get_link_status = true;
3913 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3914 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3915 speed = hw->phy.autoneg_advertised;
3917 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3918 ixgbe_setup_link(hw, speed, true);
3921 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3922 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3926 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3928 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3931 link.link_speed = ETH_SPEED_NUM_100M;
3932 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3933 return rte_eth_linkstatus_set(dev, &link);
3937 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3938 return rte_eth_linkstatus_set(dev, &link);
3941 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3942 link.link_status = ETH_LINK_UP;
3943 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3945 switch (link_speed) {
3947 case IXGBE_LINK_SPEED_UNKNOWN:
3948 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3949 link.link_speed = ETH_SPEED_NUM_100M;
3952 case IXGBE_LINK_SPEED_100_FULL:
3953 link.link_speed = ETH_SPEED_NUM_100M;
3956 case IXGBE_LINK_SPEED_1GB_FULL:
3957 link.link_speed = ETH_SPEED_NUM_1G;
3960 case IXGBE_LINK_SPEED_2_5GB_FULL:
3961 link.link_speed = ETH_SPEED_NUM_2_5G;
3964 case IXGBE_LINK_SPEED_5GB_FULL:
3965 link.link_speed = ETH_SPEED_NUM_5G;
3968 case IXGBE_LINK_SPEED_10GB_FULL:
3969 link.link_speed = ETH_SPEED_NUM_10G;
3973 return rte_eth_linkstatus_set(dev, &link);
3977 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3979 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3983 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3985 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3989 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3991 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3994 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3995 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3996 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4000 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4002 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4005 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4006 fctrl &= (~IXGBE_FCTRL_UPE);
4007 if (dev->data->all_multicast == 1)
4008 fctrl |= IXGBE_FCTRL_MPE;
4010 fctrl &= (~IXGBE_FCTRL_MPE);
4011 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4015 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4017 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4020 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4021 fctrl |= IXGBE_FCTRL_MPE;
4022 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4026 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4028 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4031 if (dev->data->promiscuous == 1)
4032 return; /* must remain in all_multicast mode */
4034 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4035 fctrl &= (~IXGBE_FCTRL_MPE);
4036 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4040 * It clears the interrupt causes and enables the interrupt.
4041 * It will be called once only during nic initialized.
4044 * Pointer to struct rte_eth_dev.
4046 * Enable or Disable.
4049 * - On success, zero.
4050 * - On failure, a negative value.
4053 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4055 struct ixgbe_interrupt *intr =
4056 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4058 ixgbe_dev_link_status_print(dev);
4060 intr->mask |= IXGBE_EICR_LSC;
4062 intr->mask &= ~IXGBE_EICR_LSC;
4068 * It clears the interrupt causes and enables the interrupt.
4069 * It will be called once only during nic initialized.
4072 * Pointer to struct rte_eth_dev.
4075 * - On success, zero.
4076 * - On failure, a negative value.
4079 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4081 struct ixgbe_interrupt *intr =
4082 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4084 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4090 * It clears the interrupt causes and enables the interrupt.
4091 * It will be called once only during nic initialized.
4094 * Pointer to struct rte_eth_dev.
4097 * - On success, zero.
4098 * - On failure, a negative value.
4101 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4103 struct ixgbe_interrupt *intr =
4104 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4106 intr->mask |= IXGBE_EICR_LINKSEC;
4112 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4115 * Pointer to struct rte_eth_dev.
4118 * - On success, zero.
4119 * - On failure, a negative value.
4122 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4125 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4126 struct ixgbe_interrupt *intr =
4127 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4129 /* clear all cause mask */
4130 ixgbe_disable_intr(hw);
4132 /* read-on-clear nic registers here */
4133 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4134 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4138 /* set flag for async link update */
4139 if (eicr & IXGBE_EICR_LSC)
4140 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4142 if (eicr & IXGBE_EICR_MAILBOX)
4143 intr->flags |= IXGBE_FLAG_MAILBOX;
4145 if (eicr & IXGBE_EICR_LINKSEC)
4146 intr->flags |= IXGBE_FLAG_MACSEC;
4148 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4149 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4150 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4151 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4157 * It gets and then prints the link status.
4160 * Pointer to struct rte_eth_dev.
4163 * - On success, zero.
4164 * - On failure, a negative value.
4167 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4169 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4170 struct rte_eth_link link;
4172 rte_eth_linkstatus_get(dev, &link);
4174 if (link.link_status) {
4175 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4176 (int)(dev->data->port_id),
4177 (unsigned)link.link_speed,
4178 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4179 "full-duplex" : "half-duplex");
4181 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4182 (int)(dev->data->port_id));
4184 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4185 pci_dev->addr.domain,
4187 pci_dev->addr.devid,
4188 pci_dev->addr.function);
4192 * It executes link_update after knowing an interrupt occurred.
4195 * Pointer to struct rte_eth_dev.
4198 * - On success, zero.
4199 * - On failure, a negative value.
4202 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4203 struct rte_intr_handle *intr_handle)
4205 struct ixgbe_interrupt *intr =
4206 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4208 struct ixgbe_hw *hw =
4209 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4211 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4213 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4214 ixgbe_pf_mbx_process(dev);
4215 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4218 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4219 ixgbe_handle_lasi(hw);
4220 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4223 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4224 struct rte_eth_link link;
4226 /* get the link status before link update, for predicting later */
4227 rte_eth_linkstatus_get(dev, &link);
4229 ixgbe_dev_link_update(dev, 0);
4232 if (!link.link_status)
4233 /* handle it 1 sec later, wait it being stable */
4234 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4235 /* likely to down */
4237 /* handle it 4 sec later, wait it being stable */
4238 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4240 ixgbe_dev_link_status_print(dev);
4241 if (rte_eal_alarm_set(timeout * 1000,
4242 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4243 PMD_DRV_LOG(ERR, "Error setting alarm");
4245 /* remember original mask */
4246 intr->mask_original = intr->mask;
4247 /* only disable lsc interrupt */
4248 intr->mask &= ~IXGBE_EIMS_LSC;
4252 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4253 ixgbe_enable_intr(dev);
4254 rte_intr_enable(intr_handle);
4260 * Interrupt handler which shall be registered for alarm callback for delayed
4261 * handling specific interrupt to wait for the stable nic state. As the
4262 * NIC interrupt state is not stable for ixgbe after link is just down,
4263 * it needs to wait 4 seconds to get the stable status.
4266 * Pointer to interrupt handle.
4268 * The address of parameter (struct rte_eth_dev *) regsitered before.
4274 ixgbe_dev_interrupt_delayed_handler(void *param)
4276 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4277 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4278 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4279 struct ixgbe_interrupt *intr =
4280 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4281 struct ixgbe_hw *hw =
4282 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4285 ixgbe_disable_intr(hw);
4287 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4288 if (eicr & IXGBE_EICR_MAILBOX)
4289 ixgbe_pf_mbx_process(dev);
4291 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4292 ixgbe_handle_lasi(hw);
4293 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4296 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4297 ixgbe_dev_link_update(dev, 0);
4298 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4299 ixgbe_dev_link_status_print(dev);
4300 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4304 if (intr->flags & IXGBE_FLAG_MACSEC) {
4305 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4307 intr->flags &= ~IXGBE_FLAG_MACSEC;
4310 /* restore original mask */
4311 intr->mask = intr->mask_original;
4312 intr->mask_original = 0;
4314 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4315 ixgbe_enable_intr(dev);
4316 rte_intr_enable(intr_handle);
4320 * Interrupt handler triggered by NIC for handling
4321 * specific interrupt.
4324 * Pointer to interrupt handle.
4326 * The address of parameter (struct rte_eth_dev *) regsitered before.
4332 ixgbe_dev_interrupt_handler(void *param)
4334 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4336 ixgbe_dev_interrupt_get_status(dev);
4337 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4341 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4343 struct ixgbe_hw *hw;
4345 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4346 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4350 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4352 struct ixgbe_hw *hw;
4354 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4355 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4359 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4361 struct ixgbe_hw *hw;
4367 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4369 fc_conf->pause_time = hw->fc.pause_time;
4370 fc_conf->high_water = hw->fc.high_water[0];
4371 fc_conf->low_water = hw->fc.low_water[0];
4372 fc_conf->send_xon = hw->fc.send_xon;
4373 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4376 * Return rx_pause status according to actual setting of
4379 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4380 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4386 * Return tx_pause status according to actual setting of
4389 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4390 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4395 if (rx_pause && tx_pause)
4396 fc_conf->mode = RTE_FC_FULL;
4398 fc_conf->mode = RTE_FC_RX_PAUSE;
4400 fc_conf->mode = RTE_FC_TX_PAUSE;
4402 fc_conf->mode = RTE_FC_NONE;
4408 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4410 struct ixgbe_hw *hw;
4412 uint32_t rx_buf_size;
4413 uint32_t max_high_water;
4415 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4422 PMD_INIT_FUNC_TRACE();
4424 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4425 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4426 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4429 * At least reserve one Ethernet frame for watermark
4430 * high_water/low_water in kilo bytes for ixgbe
4432 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4433 if ((fc_conf->high_water > max_high_water) ||
4434 (fc_conf->high_water < fc_conf->low_water)) {
4435 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4436 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4440 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4441 hw->fc.pause_time = fc_conf->pause_time;
4442 hw->fc.high_water[0] = fc_conf->high_water;
4443 hw->fc.low_water[0] = fc_conf->low_water;
4444 hw->fc.send_xon = fc_conf->send_xon;
4445 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4447 err = ixgbe_fc_enable(hw);
4449 /* Not negotiated is not an error case */
4450 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4452 /* check if we want to forward MAC frames - driver doesn't have native
4453 * capability to do that, so we'll write the registers ourselves */
4455 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4457 /* set or clear MFLCN.PMCF bit depending on configuration */
4458 if (fc_conf->mac_ctrl_frame_fwd != 0)
4459 mflcn |= IXGBE_MFLCN_PMCF;
4461 mflcn &= ~IXGBE_MFLCN_PMCF;
4463 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4464 IXGBE_WRITE_FLUSH(hw);
4469 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4474 * ixgbe_pfc_enable_generic - Enable flow control
4475 * @hw: pointer to hardware structure
4476 * @tc_num: traffic class number
4477 * Enable flow control according to the current settings.
4480 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4483 uint32_t mflcn_reg, fccfg_reg;
4485 uint32_t fcrtl, fcrth;
4489 /* Validate the water mark configuration */
4490 if (!hw->fc.pause_time) {
4491 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4495 /* Low water mark of zero causes XOFF floods */
4496 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4497 /* High/Low water can not be 0 */
4498 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4499 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4500 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4504 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4505 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4506 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4510 /* Negotiate the fc mode to use */
4511 ixgbe_fc_autoneg(hw);
4513 /* Disable any previous flow control settings */
4514 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4515 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4517 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4518 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4520 switch (hw->fc.current_mode) {
4523 * If the count of enabled RX Priority Flow control >1,
4524 * and the TX pause can not be disabled
4527 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4528 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4529 if (reg & IXGBE_FCRTH_FCEN)
4533 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4535 case ixgbe_fc_rx_pause:
4537 * Rx Flow control is enabled and Tx Flow control is
4538 * disabled by software override. Since there really
4539 * isn't a way to advertise that we are capable of RX
4540 * Pause ONLY, we will advertise that we support both
4541 * symmetric and asymmetric Rx PAUSE. Later, we will
4542 * disable the adapter's ability to send PAUSE frames.
4544 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4546 * If the count of enabled RX Priority Flow control >1,
4547 * and the TX pause can not be disabled
4550 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4551 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4552 if (reg & IXGBE_FCRTH_FCEN)
4556 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4558 case ixgbe_fc_tx_pause:
4560 * Tx Flow control is enabled, and Rx Flow control is
4561 * disabled by software override.
4563 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4566 /* Flow control (both Rx and Tx) is enabled by SW override. */
4567 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4568 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4571 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4572 ret_val = IXGBE_ERR_CONFIG;
4576 /* Set 802.3x based flow control settings. */
4577 mflcn_reg |= IXGBE_MFLCN_DPF;
4578 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4579 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4581 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4582 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4583 hw->fc.high_water[tc_num]) {
4584 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4585 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4586 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4588 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4590 * In order to prevent Tx hangs when the internal Tx
4591 * switch is enabled we must set the high water mark
4592 * to the maximum FCRTH value. This allows the Tx
4593 * switch to function even under heavy Rx workloads.
4595 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4597 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4599 /* Configure pause time (2 TCs per register) */
4600 reg = hw->fc.pause_time * 0x00010001;
4601 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4602 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4604 /* Configure flow control refresh threshold value */
4605 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4612 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4614 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4615 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4617 if (hw->mac.type != ixgbe_mac_82598EB) {
4618 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4624 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4627 uint32_t rx_buf_size;
4628 uint32_t max_high_water;
4630 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4631 struct ixgbe_hw *hw =
4632 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4633 struct ixgbe_dcb_config *dcb_config =
4634 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4636 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4643 PMD_INIT_FUNC_TRACE();
4645 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4646 tc_num = map[pfc_conf->priority];
4647 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4648 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4650 * At least reserve one Ethernet frame for watermark
4651 * high_water/low_water in kilo bytes for ixgbe
4653 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4654 if ((pfc_conf->fc.high_water > max_high_water) ||
4655 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4656 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4657 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4661 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4662 hw->fc.pause_time = pfc_conf->fc.pause_time;
4663 hw->fc.send_xon = pfc_conf->fc.send_xon;
4664 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4665 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4667 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4669 /* Not negotiated is not an error case */
4670 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4673 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4678 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4679 struct rte_eth_rss_reta_entry64 *reta_conf,
4682 uint16_t i, sp_reta_size;
4685 uint16_t idx, shift;
4686 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4689 PMD_INIT_FUNC_TRACE();
4691 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4692 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4697 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4698 if (reta_size != sp_reta_size) {
4699 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4700 "(%d) doesn't match the number hardware can supported "
4701 "(%d)", reta_size, sp_reta_size);
4705 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4706 idx = i / RTE_RETA_GROUP_SIZE;
4707 shift = i % RTE_RETA_GROUP_SIZE;
4708 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4712 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4713 if (mask == IXGBE_4_BIT_MASK)
4716 r = IXGBE_READ_REG(hw, reta_reg);
4717 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4718 if (mask & (0x1 << j))
4719 reta |= reta_conf[idx].reta[shift + j] <<
4722 reta |= r & (IXGBE_8_BIT_MASK <<
4725 IXGBE_WRITE_REG(hw, reta_reg, reta);
4732 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4733 struct rte_eth_rss_reta_entry64 *reta_conf,
4736 uint16_t i, sp_reta_size;
4739 uint16_t idx, shift;
4740 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4743 PMD_INIT_FUNC_TRACE();
4744 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4745 if (reta_size != sp_reta_size) {
4746 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4747 "(%d) doesn't match the number hardware can supported "
4748 "(%d)", reta_size, sp_reta_size);
4752 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4753 idx = i / RTE_RETA_GROUP_SIZE;
4754 shift = i % RTE_RETA_GROUP_SIZE;
4755 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4760 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4761 reta = IXGBE_READ_REG(hw, reta_reg);
4762 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4763 if (mask & (0x1 << j))
4764 reta_conf[idx].reta[shift + j] =
4765 ((reta >> (CHAR_BIT * j)) &
4774 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4775 uint32_t index, uint32_t pool)
4777 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4778 uint32_t enable_addr = 1;
4780 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4785 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4787 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4789 ixgbe_clear_rar(hw, index);
4793 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4795 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4797 ixgbe_remove_rar(dev, 0);
4798 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4804 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4806 if (strcmp(dev->device->driver->name, drv->driver.name))
4813 is_ixgbe_supported(struct rte_eth_dev *dev)
4815 return is_device_supported(dev, &rte_ixgbe_pmd);
4819 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4823 struct ixgbe_hw *hw;
4824 struct rte_eth_dev_info dev_info;
4825 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4826 struct rte_eth_dev_data *dev_data = dev->data;
4828 ixgbe_dev_info_get(dev, &dev_info);
4830 /* check that mtu is within the allowed range */
4831 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4834 /* If device is started, refuse mtu that requires the support of
4835 * scattered packets when this feature has not been enabled before.
4837 if (dev_data->dev_started && !dev_data->scattered_rx &&
4838 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4839 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4840 PMD_INIT_LOG(ERR, "Stop port first.");
4844 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4847 /* switch to jumbo mode if needed */
4848 if (frame_size > ETHER_MAX_LEN) {
4849 dev->data->dev_conf.rxmode.offloads |=
4850 DEV_RX_OFFLOAD_JUMBO_FRAME;
4851 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4853 dev->data->dev_conf.rxmode.offloads &=
4854 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4855 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4857 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4859 /* update max frame size */
4860 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4862 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4863 maxfrs &= 0x0000FFFF;
4864 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4865 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4871 * Virtual Function operations
4874 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4876 PMD_INIT_FUNC_TRACE();
4878 /* Clear interrupt mask to stop from interrupts being generated */
4879 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4881 IXGBE_WRITE_FLUSH(hw);
4885 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4887 PMD_INIT_FUNC_TRACE();
4889 /* VF enable interrupt autoclean */
4890 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4891 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4892 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4894 IXGBE_WRITE_FLUSH(hw);
4898 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4900 struct rte_eth_conf *conf = &dev->data->dev_conf;
4901 struct ixgbe_adapter *adapter =
4902 (struct ixgbe_adapter *)dev->data->dev_private;
4903 struct rte_eth_dev_info dev_info;
4904 uint64_t rx_offloads;
4905 uint64_t tx_offloads;
4907 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4908 dev->data->port_id);
4910 ixgbevf_dev_info_get(dev, &dev_info);
4911 rx_offloads = dev->data->dev_conf.rxmode.offloads;
4912 if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4913 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4914 "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4915 rx_offloads, dev_info.rx_offload_capa);
4918 tx_offloads = dev->data->dev_conf.txmode.offloads;
4919 if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4920 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4921 "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4922 tx_offloads, dev_info.tx_offload_capa);
4927 * VF has no ability to enable/disable HW CRC
4928 * Keep the persistent behavior the same as Host PF
4930 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4931 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4932 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4933 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4936 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4937 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4938 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
4943 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4944 * allocation or vector Rx preconditions we will reset it.
4946 adapter->rx_bulk_alloc_allowed = true;
4947 adapter->rx_vec_allowed = true;
4953 ixgbevf_dev_start(struct rte_eth_dev *dev)
4955 struct ixgbe_hw *hw =
4956 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4957 uint32_t intr_vector = 0;
4958 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4959 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4963 PMD_INIT_FUNC_TRACE();
4965 err = hw->mac.ops.reset_hw(hw);
4967 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4970 hw->mac.get_link_status = true;
4972 /* negotiate mailbox API version to use with the PF. */
4973 ixgbevf_negotiate_api(hw);
4975 ixgbevf_dev_tx_init(dev);
4977 /* This can fail when allocating mbufs for descriptor rings */
4978 err = ixgbevf_dev_rx_init(dev);
4980 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4981 ixgbe_dev_clear_queues(dev);
4986 ixgbevf_set_vfta_all(dev, 1);
4989 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4990 ETH_VLAN_EXTEND_MASK;
4991 err = ixgbevf_vlan_offload_set(dev, mask);
4993 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4994 ixgbe_dev_clear_queues(dev);
4998 ixgbevf_dev_rxtx_start(dev);
5000 ixgbevf_dev_link_update(dev, 0);
5002 /* check and configure queue intr-vector mapping */
5003 if (rte_intr_cap_multiple(intr_handle) &&
5004 dev->data->dev_conf.intr_conf.rxq) {
5005 /* According to datasheet, only vector 0/1/2 can be used,
5006 * now only one vector is used for Rx queue
5009 if (rte_intr_efd_enable(intr_handle, intr_vector))
5013 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5014 intr_handle->intr_vec =
5015 rte_zmalloc("intr_vec",
5016 dev->data->nb_rx_queues * sizeof(int), 0);
5017 if (intr_handle->intr_vec == NULL) {
5018 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5019 " intr_vec", dev->data->nb_rx_queues);
5023 ixgbevf_configure_msix(dev);
5025 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5026 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5027 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5028 * is not cleared, it will fail when following rte_intr_enable( ) tries
5029 * to map Rx queue interrupt to other VFIO vectors.
5030 * So clear uio/vfio intr/evevnfd first to avoid failure.
5032 rte_intr_disable(intr_handle);
5034 rte_intr_enable(intr_handle);
5036 /* Re-enable interrupt for VF */
5037 ixgbevf_intr_enable(hw);
5043 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5045 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5046 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5047 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5049 PMD_INIT_FUNC_TRACE();
5051 ixgbevf_intr_disable(hw);
5053 hw->adapter_stopped = 1;
5054 ixgbe_stop_adapter(hw);
5057 * Clear what we set, but we still keep shadow_vfta to
5058 * restore after device starts
5060 ixgbevf_set_vfta_all(dev, 0);
5062 /* Clear stored conf */
5063 dev->data->scattered_rx = 0;
5065 ixgbe_dev_clear_queues(dev);
5067 /* Clean datapath event and queue/vec mapping */
5068 rte_intr_efd_disable(intr_handle);
5069 if (intr_handle->intr_vec != NULL) {
5070 rte_free(intr_handle->intr_vec);
5071 intr_handle->intr_vec = NULL;
5076 ixgbevf_dev_close(struct rte_eth_dev *dev)
5078 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5080 PMD_INIT_FUNC_TRACE();
5084 ixgbevf_dev_stop(dev);
5086 ixgbe_dev_free_queues(dev);
5089 * Remove the VF MAC address ro ensure
5090 * that the VF traffic goes to the PF
5091 * after stop, close and detach of the VF
5093 ixgbevf_remove_mac_addr(dev, 0);
5100 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5104 ret = eth_ixgbevf_dev_uninit(dev);
5108 ret = eth_ixgbevf_dev_init(dev);
5113 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5115 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5116 struct ixgbe_vfta *shadow_vfta =
5117 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5118 int i = 0, j = 0, vfta = 0, mask = 1;
5120 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5121 vfta = shadow_vfta->vfta[i];
5124 for (j = 0; j < 32; j++) {
5126 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5136 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5138 struct ixgbe_hw *hw =
5139 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140 struct ixgbe_vfta *shadow_vfta =
5141 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5142 uint32_t vid_idx = 0;
5143 uint32_t vid_bit = 0;
5146 PMD_INIT_FUNC_TRACE();
5148 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5149 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5151 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5154 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5155 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5157 /* Save what we set and retore it after device reset */
5159 shadow_vfta->vfta[vid_idx] |= vid_bit;
5161 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5167 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5169 struct ixgbe_hw *hw =
5170 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5173 PMD_INIT_FUNC_TRACE();
5175 if (queue >= hw->mac.max_rx_queues)
5178 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5180 ctrl |= IXGBE_RXDCTL_VME;
5182 ctrl &= ~IXGBE_RXDCTL_VME;
5183 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5185 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5189 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5191 struct ixgbe_rx_queue *rxq;
5195 /* VF function only support hw strip feature, others are not support */
5196 if (mask & ETH_VLAN_STRIP_MASK) {
5197 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5198 rxq = dev->data->rx_queues[i];
5199 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5200 ixgbevf_vlan_strip_queue_set(dev, i, on);
5208 ixgbe_vt_check(struct ixgbe_hw *hw)
5212 /* if Virtualization Technology is enabled */
5213 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5214 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5215 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5223 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5225 uint32_t vector = 0;
5227 switch (hw->mac.mc_filter_type) {
5228 case 0: /* use bits [47:36] of the address */
5229 vector = ((uc_addr->addr_bytes[4] >> 4) |
5230 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5232 case 1: /* use bits [46:35] of the address */
5233 vector = ((uc_addr->addr_bytes[4] >> 3) |
5234 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5236 case 2: /* use bits [45:34] of the address */
5237 vector = ((uc_addr->addr_bytes[4] >> 2) |
5238 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5240 case 3: /* use bits [43:32] of the address */
5241 vector = ((uc_addr->addr_bytes[4]) |
5242 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5244 default: /* Invalid mc_filter_type */
5248 /* vector can only be 12-bits or boundary will be exceeded */
5254 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5262 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5263 const uint32_t ixgbe_uta_bit_shift = 5;
5264 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5265 const uint32_t bit1 = 0x1;
5267 struct ixgbe_hw *hw =
5268 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5269 struct ixgbe_uta_info *uta_info =
5270 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5272 /* The UTA table only exists on 82599 hardware and newer */
5273 if (hw->mac.type < ixgbe_mac_82599EB)
5276 vector = ixgbe_uta_vector(hw, mac_addr);
5277 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5278 uta_shift = vector & ixgbe_uta_bit_mask;
5280 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5284 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5286 uta_info->uta_in_use++;
5287 reg_val |= (bit1 << uta_shift);
5288 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5290 uta_info->uta_in_use--;
5291 reg_val &= ~(bit1 << uta_shift);
5292 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5295 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5297 if (uta_info->uta_in_use > 0)
5298 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5299 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5301 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5307 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5310 struct ixgbe_hw *hw =
5311 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5312 struct ixgbe_uta_info *uta_info =
5313 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5315 /* The UTA table only exists on 82599 hardware and newer */
5316 if (hw->mac.type < ixgbe_mac_82599EB)
5320 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5321 uta_info->uta_shadow[i] = ~0;
5322 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5325 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5326 uta_info->uta_shadow[i] = 0;
5327 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5335 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5337 uint32_t new_val = orig_val;
5339 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5340 new_val |= IXGBE_VMOLR_AUPE;
5341 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5342 new_val |= IXGBE_VMOLR_ROMPE;
5343 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5344 new_val |= IXGBE_VMOLR_ROPE;
5345 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5346 new_val |= IXGBE_VMOLR_BAM;
5347 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5348 new_val |= IXGBE_VMOLR_MPE;
5353 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5354 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5355 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5356 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5357 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5358 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5359 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5362 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5363 struct rte_eth_mirror_conf *mirror_conf,
5364 uint8_t rule_id, uint8_t on)
5366 uint32_t mr_ctl, vlvf;
5367 uint32_t mp_lsb = 0;
5368 uint32_t mv_msb = 0;
5369 uint32_t mv_lsb = 0;
5370 uint32_t mp_msb = 0;
5373 uint64_t vlan_mask = 0;
5375 const uint8_t pool_mask_offset = 32;
5376 const uint8_t vlan_mask_offset = 32;
5377 const uint8_t dst_pool_offset = 8;
5378 const uint8_t rule_mr_offset = 4;
5379 const uint8_t mirror_rule_mask = 0x0F;
5381 struct ixgbe_mirror_info *mr_info =
5382 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5383 struct ixgbe_hw *hw =
5384 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5385 uint8_t mirror_type = 0;
5387 if (ixgbe_vt_check(hw) < 0)
5390 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5393 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5394 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5395 mirror_conf->rule_type);
5399 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5400 mirror_type |= IXGBE_MRCTL_VLME;
5401 /* Check if vlan id is valid and find conresponding VLAN ID
5404 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5405 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5406 /* search vlan id related pool vlan filter
5409 reg_index = ixgbe_find_vlvf_slot(
5411 mirror_conf->vlan.vlan_id[i],
5415 vlvf = IXGBE_READ_REG(hw,
5416 IXGBE_VLVF(reg_index));
5417 if ((vlvf & IXGBE_VLVF_VIEN) &&
5418 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5419 mirror_conf->vlan.vlan_id[i]))
5420 vlan_mask |= (1ULL << reg_index);
5427 mv_lsb = vlan_mask & 0xFFFFFFFF;
5428 mv_msb = vlan_mask >> vlan_mask_offset;
5430 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5431 mirror_conf->vlan.vlan_mask;
5432 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5433 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5434 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5435 mirror_conf->vlan.vlan_id[i];
5440 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5441 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5442 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5447 * if enable pool mirror, write related pool mask register,if disable
5448 * pool mirror, clear PFMRVM register
5450 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5451 mirror_type |= IXGBE_MRCTL_VPME;
5453 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5454 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5455 mr_info->mr_conf[rule_id].pool_mask =
5456 mirror_conf->pool_mask;
5461 mr_info->mr_conf[rule_id].pool_mask = 0;
5464 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5465 mirror_type |= IXGBE_MRCTL_UPME;
5466 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5467 mirror_type |= IXGBE_MRCTL_DPME;
5469 /* read mirror control register and recalculate it */
5470 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5473 mr_ctl |= mirror_type;
5474 mr_ctl &= mirror_rule_mask;
5475 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5477 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5480 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5481 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5483 /* write mirrror control register */
5484 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5486 /* write pool mirrror control register */
5487 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5488 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5489 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5492 /* write VLAN mirrror control register */
5493 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5494 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5495 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5503 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5506 uint32_t lsb_val = 0;
5507 uint32_t msb_val = 0;
5508 const uint8_t rule_mr_offset = 4;
5510 struct ixgbe_hw *hw =
5511 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5512 struct ixgbe_mirror_info *mr_info =
5513 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5515 if (ixgbe_vt_check(hw) < 0)
5518 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5521 memset(&mr_info->mr_conf[rule_id], 0,
5522 sizeof(struct rte_eth_mirror_conf));
5524 /* clear PFVMCTL register */
5525 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5527 /* clear pool mask register */
5528 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5529 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5531 /* clear vlan mask register */
5532 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5533 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5539 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5541 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5542 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5544 struct ixgbe_hw *hw =
5545 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5546 uint32_t vec = IXGBE_MISC_VEC_ID;
5548 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5549 if (rte_intr_allow_others(intr_handle))
5550 vec = IXGBE_RX_VEC_START;
5552 RTE_SET_USED(queue_id);
5553 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5555 rte_intr_enable(intr_handle);
5561 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5564 struct ixgbe_hw *hw =
5565 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5566 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5567 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5568 uint32_t vec = IXGBE_MISC_VEC_ID;
5570 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5571 if (rte_intr_allow_others(intr_handle))
5572 vec = IXGBE_RX_VEC_START;
5573 mask &= ~(1 << vec);
5574 RTE_SET_USED(queue_id);
5575 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5581 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5583 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5584 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5586 struct ixgbe_hw *hw =
5587 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5588 struct ixgbe_interrupt *intr =
5589 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5591 if (queue_id < 16) {
5592 ixgbe_disable_intr(hw);
5593 intr->mask |= (1 << queue_id);
5594 ixgbe_enable_intr(dev);
5595 } else if (queue_id < 32) {
5596 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5597 mask &= (1 << queue_id);
5598 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5599 } else if (queue_id < 64) {
5600 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5601 mask &= (1 << (queue_id - 32));
5602 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5604 rte_intr_enable(intr_handle);
5610 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5613 struct ixgbe_hw *hw =
5614 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5615 struct ixgbe_interrupt *intr =
5616 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5618 if (queue_id < 16) {
5619 ixgbe_disable_intr(hw);
5620 intr->mask &= ~(1 << queue_id);
5621 ixgbe_enable_intr(dev);
5622 } else if (queue_id < 32) {
5623 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5624 mask &= ~(1 << queue_id);
5625 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5626 } else if (queue_id < 64) {
5627 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5628 mask &= ~(1 << (queue_id - 32));
5629 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5636 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5637 uint8_t queue, uint8_t msix_vector)
5641 if (direction == -1) {
5643 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5644 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5647 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5649 /* rx or tx cause */
5650 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5651 idx = ((16 * (queue & 1)) + (8 * direction));
5652 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5653 tmp &= ~(0xFF << idx);
5654 tmp |= (msix_vector << idx);
5655 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5660 * set the IVAR registers, mapping interrupt causes to vectors
5662 * pointer to ixgbe_hw struct
5664 * 0 for Rx, 1 for Tx, -1 for other causes
5666 * queue to map the corresponding interrupt to
5668 * the vector to map to the corresponding queue
5671 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5672 uint8_t queue, uint8_t msix_vector)
5676 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5677 if (hw->mac.type == ixgbe_mac_82598EB) {
5678 if (direction == -1)
5680 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5681 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5682 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5683 tmp |= (msix_vector << (8 * (queue & 0x3)));
5684 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5685 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5686 (hw->mac.type == ixgbe_mac_X540) ||
5687 (hw->mac.type == ixgbe_mac_X550)) {
5688 if (direction == -1) {
5690 idx = ((queue & 1) * 8);
5691 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5692 tmp &= ~(0xFF << idx);
5693 tmp |= (msix_vector << idx);
5694 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5696 /* rx or tx causes */
5697 idx = ((16 * (queue & 1)) + (8 * direction));
5698 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5699 tmp &= ~(0xFF << idx);
5700 tmp |= (msix_vector << idx);
5701 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5707 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5709 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5710 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5711 struct ixgbe_hw *hw =
5712 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5714 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5715 uint32_t base = IXGBE_MISC_VEC_ID;
5717 /* Configure VF other cause ivar */
5718 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5720 /* won't configure msix register if no mapping is done
5721 * between intr vector and event fd.
5723 if (!rte_intr_dp_is_en(intr_handle))
5726 if (rte_intr_allow_others(intr_handle)) {
5727 base = IXGBE_RX_VEC_START;
5728 vector_idx = IXGBE_RX_VEC_START;
5731 /* Configure all RX queues of VF */
5732 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5733 /* Force all queue use vector 0,
5734 * as IXGBE_VF_MAXMSIVECOTR = 1
5736 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5737 intr_handle->intr_vec[q_idx] = vector_idx;
5738 if (vector_idx < base + intr_handle->nb_efd - 1)
5744 * Sets up the hardware to properly generate MSI-X interrupts
5746 * board private structure
5749 ixgbe_configure_msix(struct rte_eth_dev *dev)
5751 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5752 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5753 struct ixgbe_hw *hw =
5754 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5755 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5756 uint32_t vec = IXGBE_MISC_VEC_ID;
5760 /* won't configure msix register if no mapping is done
5761 * between intr vector and event fd
5763 if (!rte_intr_dp_is_en(intr_handle))
5766 if (rte_intr_allow_others(intr_handle))
5767 vec = base = IXGBE_RX_VEC_START;
5769 /* setup GPIE for MSI-x mode */
5770 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5771 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5772 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5773 /* auto clearing and auto setting corresponding bits in EIMS
5774 * when MSI-X interrupt is triggered
5776 if (hw->mac.type == ixgbe_mac_82598EB) {
5777 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5779 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5780 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5782 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5784 /* Populate the IVAR table and set the ITR values to the
5785 * corresponding register.
5787 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5789 /* by default, 1:1 mapping */
5790 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5791 intr_handle->intr_vec[queue_id] = vec;
5792 if (vec < base + intr_handle->nb_efd - 1)
5796 switch (hw->mac.type) {
5797 case ixgbe_mac_82598EB:
5798 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5801 case ixgbe_mac_82599EB:
5802 case ixgbe_mac_X540:
5803 case ixgbe_mac_X550:
5804 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5809 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5810 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5812 /* set up to autoclear timer, and the vectors */
5813 mask = IXGBE_EIMS_ENABLE_MASK;
5814 mask &= ~(IXGBE_EIMS_OTHER |
5815 IXGBE_EIMS_MAILBOX |
5818 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5822 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5823 uint16_t queue_idx, uint16_t tx_rate)
5825 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5826 struct rte_eth_rxmode *rxmode;
5827 uint32_t rf_dec, rf_int;
5829 uint16_t link_speed = dev->data->dev_link.link_speed;
5831 if (queue_idx >= hw->mac.max_tx_queues)
5835 /* Calculate the rate factor values to set */
5836 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5837 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5838 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5840 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5841 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5842 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5843 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5848 rxmode = &dev->data->dev_conf.rxmode;
5850 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5851 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5854 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5855 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5856 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5857 IXGBE_MMW_SIZE_JUMBO_FRAME);
5859 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5860 IXGBE_MMW_SIZE_DEFAULT);
5862 /* Set RTTBCNRC of queue X */
5863 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5864 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5865 IXGBE_WRITE_FLUSH(hw);
5871 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5872 __attribute__((unused)) uint32_t index,
5873 __attribute__((unused)) uint32_t pool)
5875 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5879 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5880 * operation. Trap this case to avoid exhausting the [very limited]
5881 * set of PF resources used to store VF MAC addresses.
5883 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5885 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5887 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5888 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5889 mac_addr->addr_bytes[0],
5890 mac_addr->addr_bytes[1],
5891 mac_addr->addr_bytes[2],
5892 mac_addr->addr_bytes[3],
5893 mac_addr->addr_bytes[4],
5894 mac_addr->addr_bytes[5],
5900 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5902 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5903 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5904 struct ether_addr *mac_addr;
5909 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5910 * not support the deletion of a given MAC address.
5911 * Instead, it imposes to delete all MAC addresses, then to add again
5912 * all MAC addresses with the exception of the one to be deleted.
5914 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5917 * Add again all MAC addresses, with the exception of the deleted one
5918 * and of the permanent MAC address.
5920 for (i = 0, mac_addr = dev->data->mac_addrs;
5921 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5922 /* Skip the deleted MAC address */
5925 /* Skip NULL MAC addresses */
5926 if (is_zero_ether_addr(mac_addr))
5928 /* Skip the permanent MAC address */
5929 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5931 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5934 "Adding again MAC address "
5935 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5937 mac_addr->addr_bytes[0],
5938 mac_addr->addr_bytes[1],
5939 mac_addr->addr_bytes[2],
5940 mac_addr->addr_bytes[3],
5941 mac_addr->addr_bytes[4],
5942 mac_addr->addr_bytes[5],
5948 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5950 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5952 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5958 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5959 struct rte_eth_syn_filter *filter,
5962 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5963 struct ixgbe_filter_info *filter_info =
5964 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5968 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5971 syn_info = filter_info->syn_info;
5974 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5976 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5977 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5979 if (filter->hig_pri)
5980 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5982 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5984 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5985 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5987 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5990 filter_info->syn_info = synqf;
5991 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5992 IXGBE_WRITE_FLUSH(hw);
5997 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5998 struct rte_eth_syn_filter *filter)
6000 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6001 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6003 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6004 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6005 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6012 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6013 enum rte_filter_op filter_op,
6016 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6019 MAC_TYPE_FILTER_SUP(hw->mac.type);
6021 if (filter_op == RTE_ETH_FILTER_NOP)
6025 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6030 switch (filter_op) {
6031 case RTE_ETH_FILTER_ADD:
6032 ret = ixgbe_syn_filter_set(dev,
6033 (struct rte_eth_syn_filter *)arg,
6036 case RTE_ETH_FILTER_DELETE:
6037 ret = ixgbe_syn_filter_set(dev,
6038 (struct rte_eth_syn_filter *)arg,
6041 case RTE_ETH_FILTER_GET:
6042 ret = ixgbe_syn_filter_get(dev,
6043 (struct rte_eth_syn_filter *)arg);
6046 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6055 static inline enum ixgbe_5tuple_protocol
6056 convert_protocol_type(uint8_t protocol_value)
6058 if (protocol_value == IPPROTO_TCP)
6059 return IXGBE_FILTER_PROTOCOL_TCP;
6060 else if (protocol_value == IPPROTO_UDP)
6061 return IXGBE_FILTER_PROTOCOL_UDP;
6062 else if (protocol_value == IPPROTO_SCTP)
6063 return IXGBE_FILTER_PROTOCOL_SCTP;
6065 return IXGBE_FILTER_PROTOCOL_NONE;
6068 /* inject a 5-tuple filter to HW */
6070 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6071 struct ixgbe_5tuple_filter *filter)
6073 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6075 uint32_t ftqf, sdpqf;
6076 uint32_t l34timir = 0;
6077 uint8_t mask = 0xff;
6081 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6082 IXGBE_SDPQF_DSTPORT_SHIFT);
6083 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6085 ftqf = (uint32_t)(filter->filter_info.proto &
6086 IXGBE_FTQF_PROTOCOL_MASK);
6087 ftqf |= (uint32_t)((filter->filter_info.priority &
6088 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6089 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6090 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6091 if (filter->filter_info.dst_ip_mask == 0)
6092 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6093 if (filter->filter_info.src_port_mask == 0)
6094 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6095 if (filter->filter_info.dst_port_mask == 0)
6096 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6097 if (filter->filter_info.proto_mask == 0)
6098 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6099 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6100 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6101 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6103 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6104 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6105 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6106 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6108 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6109 l34timir |= (uint32_t)(filter->queue <<
6110 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6111 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6115 * add a 5tuple filter
6118 * dev: Pointer to struct rte_eth_dev.
6119 * index: the index the filter allocates.
6120 * filter: ponter to the filter that will be added.
6121 * rx_queue: the queue id the filter assigned to.
6124 * - On success, zero.
6125 * - On failure, a negative value.
6128 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6129 struct ixgbe_5tuple_filter *filter)
6131 struct ixgbe_filter_info *filter_info =
6132 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6136 * look for an unused 5tuple filter index,
6137 * and insert the filter to list.
6139 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6140 idx = i / (sizeof(uint32_t) * NBBY);
6141 shift = i % (sizeof(uint32_t) * NBBY);
6142 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6143 filter_info->fivetuple_mask[idx] |= 1 << shift;
6145 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6151 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6152 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6156 ixgbe_inject_5tuple_filter(dev, filter);
6162 * remove a 5tuple filter
6165 * dev: Pointer to struct rte_eth_dev.
6166 * filter: the pointer of the filter will be removed.
6169 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6170 struct ixgbe_5tuple_filter *filter)
6172 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6173 struct ixgbe_filter_info *filter_info =
6174 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6175 uint16_t index = filter->index;
6177 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6178 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6179 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6182 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6183 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6184 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6185 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6186 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6190 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6192 struct ixgbe_hw *hw;
6193 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6194 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6196 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6198 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6201 /* refuse mtu that requires the support of scattered packets when this
6202 * feature has not been enabled before.
6204 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6205 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6206 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6210 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6211 * request of the version 2.0 of the mailbox API.
6212 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6213 * of the mailbox API.
6214 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6215 * prior to 3.11.33 which contains the following change:
6216 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6218 ixgbevf_rlpml_set_vf(hw, max_frame);
6220 /* update max frame size */
6221 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6225 static inline struct ixgbe_5tuple_filter *
6226 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6227 struct ixgbe_5tuple_filter_info *key)
6229 struct ixgbe_5tuple_filter *it;
6231 TAILQ_FOREACH(it, filter_list, entries) {
6232 if (memcmp(key, &it->filter_info,
6233 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6240 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6242 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6243 struct ixgbe_5tuple_filter_info *filter_info)
6245 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6246 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6247 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6250 switch (filter->dst_ip_mask) {
6252 filter_info->dst_ip_mask = 0;
6253 filter_info->dst_ip = filter->dst_ip;
6256 filter_info->dst_ip_mask = 1;
6259 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6263 switch (filter->src_ip_mask) {
6265 filter_info->src_ip_mask = 0;
6266 filter_info->src_ip = filter->src_ip;
6269 filter_info->src_ip_mask = 1;
6272 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6276 switch (filter->dst_port_mask) {
6278 filter_info->dst_port_mask = 0;
6279 filter_info->dst_port = filter->dst_port;
6282 filter_info->dst_port_mask = 1;
6285 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6289 switch (filter->src_port_mask) {
6291 filter_info->src_port_mask = 0;
6292 filter_info->src_port = filter->src_port;
6295 filter_info->src_port_mask = 1;
6298 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6302 switch (filter->proto_mask) {
6304 filter_info->proto_mask = 0;
6305 filter_info->proto =
6306 convert_protocol_type(filter->proto);
6309 filter_info->proto_mask = 1;
6312 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6316 filter_info->priority = (uint8_t)filter->priority;
6321 * add or delete a ntuple filter
6324 * dev: Pointer to struct rte_eth_dev.
6325 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6326 * add: if true, add filter, if false, remove filter
6329 * - On success, zero.
6330 * - On failure, a negative value.
6333 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6334 struct rte_eth_ntuple_filter *ntuple_filter,
6337 struct ixgbe_filter_info *filter_info =
6338 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6339 struct ixgbe_5tuple_filter_info filter_5tuple;
6340 struct ixgbe_5tuple_filter *filter;
6343 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6344 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6348 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6349 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6353 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6355 if (filter != NULL && add) {
6356 PMD_DRV_LOG(ERR, "filter exists.");
6359 if (filter == NULL && !add) {
6360 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6365 filter = rte_zmalloc("ixgbe_5tuple_filter",
6366 sizeof(struct ixgbe_5tuple_filter), 0);
6369 rte_memcpy(&filter->filter_info,
6371 sizeof(struct ixgbe_5tuple_filter_info));
6372 filter->queue = ntuple_filter->queue;
6373 ret = ixgbe_add_5tuple_filter(dev, filter);
6379 ixgbe_remove_5tuple_filter(dev, filter);
6385 * get a ntuple filter
6388 * dev: Pointer to struct rte_eth_dev.
6389 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6392 * - On success, zero.
6393 * - On failure, a negative value.
6396 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6397 struct rte_eth_ntuple_filter *ntuple_filter)
6399 struct ixgbe_filter_info *filter_info =
6400 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6401 struct ixgbe_5tuple_filter_info filter_5tuple;
6402 struct ixgbe_5tuple_filter *filter;
6405 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6406 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6410 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6411 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6415 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6417 if (filter == NULL) {
6418 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6421 ntuple_filter->queue = filter->queue;
6426 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6427 * @dev: pointer to rte_eth_dev structure
6428 * @filter_op:operation will be taken.
6429 * @arg: a pointer to specific structure corresponding to the filter_op
6432 * - On success, zero.
6433 * - On failure, a negative value.
6436 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6437 enum rte_filter_op filter_op,
6440 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6443 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6445 if (filter_op == RTE_ETH_FILTER_NOP)
6449 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6454 switch (filter_op) {
6455 case RTE_ETH_FILTER_ADD:
6456 ret = ixgbe_add_del_ntuple_filter(dev,
6457 (struct rte_eth_ntuple_filter *)arg,
6460 case RTE_ETH_FILTER_DELETE:
6461 ret = ixgbe_add_del_ntuple_filter(dev,
6462 (struct rte_eth_ntuple_filter *)arg,
6465 case RTE_ETH_FILTER_GET:
6466 ret = ixgbe_get_ntuple_filter(dev,
6467 (struct rte_eth_ntuple_filter *)arg);
6470 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6478 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6479 struct rte_eth_ethertype_filter *filter,
6482 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6483 struct ixgbe_filter_info *filter_info =
6484 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6488 struct ixgbe_ethertype_filter ethertype_filter;
6490 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6493 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6494 filter->ether_type == ETHER_TYPE_IPv6) {
6495 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6496 " ethertype filter.", filter->ether_type);
6500 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6501 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6504 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6505 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6509 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6510 if (ret >= 0 && add) {
6511 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6512 filter->ether_type);
6515 if (ret < 0 && !add) {
6516 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6517 filter->ether_type);
6522 etqf = IXGBE_ETQF_FILTER_EN;
6523 etqf |= (uint32_t)filter->ether_type;
6524 etqs |= (uint32_t)((filter->queue <<
6525 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6526 IXGBE_ETQS_RX_QUEUE);
6527 etqs |= IXGBE_ETQS_QUEUE_EN;
6529 ethertype_filter.ethertype = filter->ether_type;
6530 ethertype_filter.etqf = etqf;
6531 ethertype_filter.etqs = etqs;
6532 ethertype_filter.conf = FALSE;
6533 ret = ixgbe_ethertype_filter_insert(filter_info,
6536 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6540 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6544 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6545 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6546 IXGBE_WRITE_FLUSH(hw);
6552 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6553 struct rte_eth_ethertype_filter *filter)
6555 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6556 struct ixgbe_filter_info *filter_info =
6557 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6558 uint32_t etqf, etqs;
6561 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6563 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6564 filter->ether_type);
6568 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6569 if (etqf & IXGBE_ETQF_FILTER_EN) {
6570 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6571 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6573 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6574 IXGBE_ETQS_RX_QUEUE_SHIFT;
6581 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6582 * @dev: pointer to rte_eth_dev structure
6583 * @filter_op:operation will be taken.
6584 * @arg: a pointer to specific structure corresponding to the filter_op
6587 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6588 enum rte_filter_op filter_op,
6591 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6594 MAC_TYPE_FILTER_SUP(hw->mac.type);
6596 if (filter_op == RTE_ETH_FILTER_NOP)
6600 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6605 switch (filter_op) {
6606 case RTE_ETH_FILTER_ADD:
6607 ret = ixgbe_add_del_ethertype_filter(dev,
6608 (struct rte_eth_ethertype_filter *)arg,
6611 case RTE_ETH_FILTER_DELETE:
6612 ret = ixgbe_add_del_ethertype_filter(dev,
6613 (struct rte_eth_ethertype_filter *)arg,
6616 case RTE_ETH_FILTER_GET:
6617 ret = ixgbe_get_ethertype_filter(dev,
6618 (struct rte_eth_ethertype_filter *)arg);
6621 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6629 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6630 enum rte_filter_type filter_type,
6631 enum rte_filter_op filter_op,
6636 switch (filter_type) {
6637 case RTE_ETH_FILTER_NTUPLE:
6638 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6640 case RTE_ETH_FILTER_ETHERTYPE:
6641 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6643 case RTE_ETH_FILTER_SYN:
6644 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6646 case RTE_ETH_FILTER_FDIR:
6647 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6649 case RTE_ETH_FILTER_L2_TUNNEL:
6650 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6652 case RTE_ETH_FILTER_GENERIC:
6653 if (filter_op != RTE_ETH_FILTER_GET)
6655 *(const void **)arg = &ixgbe_flow_ops;
6658 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6668 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6669 u8 **mc_addr_ptr, u32 *vmdq)
6674 mc_addr = *mc_addr_ptr;
6675 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6680 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6681 struct ether_addr *mc_addr_set,
6682 uint32_t nb_mc_addr)
6684 struct ixgbe_hw *hw;
6687 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6688 mc_addr_list = (u8 *)mc_addr_set;
6689 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6690 ixgbe_dev_addr_list_itr, TRUE);
6694 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6696 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6697 uint64_t systime_cycles;
6699 switch (hw->mac.type) {
6700 case ixgbe_mac_X550:
6701 case ixgbe_mac_X550EM_x:
6702 case ixgbe_mac_X550EM_a:
6703 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6704 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6705 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6709 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6710 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6714 return systime_cycles;
6718 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6720 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6721 uint64_t rx_tstamp_cycles;
6723 switch (hw->mac.type) {
6724 case ixgbe_mac_X550:
6725 case ixgbe_mac_X550EM_x:
6726 case ixgbe_mac_X550EM_a:
6727 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6728 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6729 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6733 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6734 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6735 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6739 return rx_tstamp_cycles;
6743 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6745 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6746 uint64_t tx_tstamp_cycles;
6748 switch (hw->mac.type) {
6749 case ixgbe_mac_X550:
6750 case ixgbe_mac_X550EM_x:
6751 case ixgbe_mac_X550EM_a:
6752 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6753 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6754 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6758 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6759 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6760 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6764 return tx_tstamp_cycles;
6768 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6770 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6771 struct ixgbe_adapter *adapter =
6772 (struct ixgbe_adapter *)dev->data->dev_private;
6773 struct rte_eth_link link;
6774 uint32_t incval = 0;
6777 /* Get current link speed. */
6778 ixgbe_dev_link_update(dev, 1);
6779 rte_eth_linkstatus_get(dev, &link);
6781 switch (link.link_speed) {
6782 case ETH_SPEED_NUM_100M:
6783 incval = IXGBE_INCVAL_100;
6784 shift = IXGBE_INCVAL_SHIFT_100;
6786 case ETH_SPEED_NUM_1G:
6787 incval = IXGBE_INCVAL_1GB;
6788 shift = IXGBE_INCVAL_SHIFT_1GB;
6790 case ETH_SPEED_NUM_10G:
6792 incval = IXGBE_INCVAL_10GB;
6793 shift = IXGBE_INCVAL_SHIFT_10GB;
6797 switch (hw->mac.type) {
6798 case ixgbe_mac_X550:
6799 case ixgbe_mac_X550EM_x:
6800 case ixgbe_mac_X550EM_a:
6801 /* Independent of link speed. */
6803 /* Cycles read will be interpreted as ns. */
6806 case ixgbe_mac_X540:
6807 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6809 case ixgbe_mac_82599EB:
6810 incval >>= IXGBE_INCVAL_SHIFT_82599;
6811 shift -= IXGBE_INCVAL_SHIFT_82599;
6812 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6813 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6816 /* Not supported. */
6820 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6821 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6822 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6824 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6825 adapter->systime_tc.cc_shift = shift;
6826 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6828 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6829 adapter->rx_tstamp_tc.cc_shift = shift;
6830 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6832 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6833 adapter->tx_tstamp_tc.cc_shift = shift;
6834 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6838 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6840 struct ixgbe_adapter *adapter =
6841 (struct ixgbe_adapter *)dev->data->dev_private;
6843 adapter->systime_tc.nsec += delta;
6844 adapter->rx_tstamp_tc.nsec += delta;
6845 adapter->tx_tstamp_tc.nsec += delta;
6851 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6854 struct ixgbe_adapter *adapter =
6855 (struct ixgbe_adapter *)dev->data->dev_private;
6857 ns = rte_timespec_to_ns(ts);
6858 /* Set the timecounters to a new value. */
6859 adapter->systime_tc.nsec = ns;
6860 adapter->rx_tstamp_tc.nsec = ns;
6861 adapter->tx_tstamp_tc.nsec = ns;
6867 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6869 uint64_t ns, systime_cycles;
6870 struct ixgbe_adapter *adapter =
6871 (struct ixgbe_adapter *)dev->data->dev_private;
6873 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6874 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6875 *ts = rte_ns_to_timespec(ns);
6881 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6883 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6887 /* Stop the timesync system time. */
6888 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6889 /* Reset the timesync system time value. */
6890 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6891 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6893 /* Enable system time for platforms where it isn't on by default. */
6894 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6895 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6896 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6898 ixgbe_start_timecounters(dev);
6900 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6901 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6903 IXGBE_ETQF_FILTER_EN |
6906 /* Enable timestamping of received PTP packets. */
6907 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6908 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6909 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6911 /* Enable timestamping of transmitted PTP packets. */
6912 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6913 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6914 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6916 IXGBE_WRITE_FLUSH(hw);
6922 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6924 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6927 /* Disable timestamping of transmitted PTP packets. */
6928 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6929 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6930 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6932 /* Disable timestamping of received PTP packets. */
6933 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6934 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6935 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6937 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6938 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6940 /* Stop incrementating the System Time registers. */
6941 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6947 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6948 struct timespec *timestamp,
6949 uint32_t flags __rte_unused)
6951 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6952 struct ixgbe_adapter *adapter =
6953 (struct ixgbe_adapter *)dev->data->dev_private;
6954 uint32_t tsync_rxctl;
6955 uint64_t rx_tstamp_cycles;
6958 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6959 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6962 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6963 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6964 *timestamp = rte_ns_to_timespec(ns);
6970 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6971 struct timespec *timestamp)
6973 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6974 struct ixgbe_adapter *adapter =
6975 (struct ixgbe_adapter *)dev->data->dev_private;
6976 uint32_t tsync_txctl;
6977 uint64_t tx_tstamp_cycles;
6980 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6981 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6984 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6985 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6986 *timestamp = rte_ns_to_timespec(ns);
6992 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6994 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6997 const struct reg_info *reg_group;
6998 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6999 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7001 while ((reg_group = reg_set[g_ind++]))
7002 count += ixgbe_regs_group_count(reg_group);
7008 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7012 const struct reg_info *reg_group;
7014 while ((reg_group = ixgbevf_regs[g_ind++]))
7015 count += ixgbe_regs_group_count(reg_group);
7021 ixgbe_get_regs(struct rte_eth_dev *dev,
7022 struct rte_dev_reg_info *regs)
7024 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7025 uint32_t *data = regs->data;
7028 const struct reg_info *reg_group;
7029 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7030 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7033 regs->length = ixgbe_get_reg_length(dev);
7034 regs->width = sizeof(uint32_t);
7038 /* Support only full register dump */
7039 if ((regs->length == 0) ||
7040 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7041 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7043 while ((reg_group = reg_set[g_ind++]))
7044 count += ixgbe_read_regs_group(dev, &data[count],
7053 ixgbevf_get_regs(struct rte_eth_dev *dev,
7054 struct rte_dev_reg_info *regs)
7056 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7057 uint32_t *data = regs->data;
7060 const struct reg_info *reg_group;
7063 regs->length = ixgbevf_get_reg_length(dev);
7064 regs->width = sizeof(uint32_t);
7068 /* Support only full register dump */
7069 if ((regs->length == 0) ||
7070 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7071 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7073 while ((reg_group = ixgbevf_regs[g_ind++]))
7074 count += ixgbe_read_regs_group(dev, &data[count],
7083 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7085 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7087 /* Return unit is byte count */
7088 return hw->eeprom.word_size * 2;
7092 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7093 struct rte_dev_eeprom_info *in_eeprom)
7095 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7096 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7097 uint16_t *data = in_eeprom->data;
7100 first = in_eeprom->offset >> 1;
7101 length = in_eeprom->length >> 1;
7102 if ((first > hw->eeprom.word_size) ||
7103 ((first + length) > hw->eeprom.word_size))
7106 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7108 return eeprom->ops.read_buffer(hw, first, length, data);
7112 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7113 struct rte_dev_eeprom_info *in_eeprom)
7115 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7116 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7117 uint16_t *data = in_eeprom->data;
7120 first = in_eeprom->offset >> 1;
7121 length = in_eeprom->length >> 1;
7122 if ((first > hw->eeprom.word_size) ||
7123 ((first + length) > hw->eeprom.word_size))
7126 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7128 return eeprom->ops.write_buffer(hw, first, length, data);
7132 ixgbe_get_module_info(struct rte_eth_dev *dev,
7133 struct rte_eth_dev_module_info *modinfo)
7135 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7137 uint8_t sff8472_rev, addr_mode;
7138 bool page_swap = false;
7140 /* Check whether we support SFF-8472 or not */
7141 status = hw->phy.ops.read_i2c_eeprom(hw,
7142 IXGBE_SFF_SFF_8472_COMP,
7147 /* addressing mode is not supported */
7148 status = hw->phy.ops.read_i2c_eeprom(hw,
7149 IXGBE_SFF_SFF_8472_SWAP,
7154 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7156 "Address change required to access page 0xA2, "
7157 "but not supported. Please report the module "
7158 "type to the driver maintainers.");
7162 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7163 /* We have a SFP, but it does not support SFF-8472 */
7164 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7165 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7167 /* We have a SFP which supports a revision of SFF-8472. */
7168 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7169 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7176 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7177 struct rte_dev_eeprom_info *info)
7179 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7180 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7181 uint8_t databyte = 0xFF;
7182 uint8_t *data = info->data;
7185 if (info->length == 0)
7188 for (i = info->offset; i < info->offset + info->length; i++) {
7189 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7190 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7192 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7197 data[i - info->offset] = databyte;
7204 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7206 case ixgbe_mac_X550:
7207 case ixgbe_mac_X550EM_x:
7208 case ixgbe_mac_X550EM_a:
7209 return ETH_RSS_RETA_SIZE_512;
7210 case ixgbe_mac_X550_vf:
7211 case ixgbe_mac_X550EM_x_vf:
7212 case ixgbe_mac_X550EM_a_vf:
7213 return ETH_RSS_RETA_SIZE_64;
7215 return ETH_RSS_RETA_SIZE_128;
7220 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7222 case ixgbe_mac_X550:
7223 case ixgbe_mac_X550EM_x:
7224 case ixgbe_mac_X550EM_a:
7225 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7226 return IXGBE_RETA(reta_idx >> 2);
7228 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7229 case ixgbe_mac_X550_vf:
7230 case ixgbe_mac_X550EM_x_vf:
7231 case ixgbe_mac_X550EM_a_vf:
7232 return IXGBE_VFRETA(reta_idx >> 2);
7234 return IXGBE_RETA(reta_idx >> 2);
7239 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7241 case ixgbe_mac_X550_vf:
7242 case ixgbe_mac_X550EM_x_vf:
7243 case ixgbe_mac_X550EM_a_vf:
7244 return IXGBE_VFMRQC;
7251 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7253 case ixgbe_mac_X550_vf:
7254 case ixgbe_mac_X550EM_x_vf:
7255 case ixgbe_mac_X550EM_a_vf:
7256 return IXGBE_VFRSSRK(i);
7258 return IXGBE_RSSRK(i);
7263 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7265 case ixgbe_mac_82599_vf:
7266 case ixgbe_mac_X540_vf:
7274 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7275 struct rte_eth_dcb_info *dcb_info)
7277 struct ixgbe_dcb_config *dcb_config =
7278 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7279 struct ixgbe_dcb_tc_config *tc;
7280 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7284 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7285 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7287 dcb_info->nb_tcs = 1;
7289 tc_queue = &dcb_info->tc_queue;
7290 nb_tcs = dcb_info->nb_tcs;
7292 if (dcb_config->vt_mode) { /* vt is enabled*/
7293 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7294 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7295 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7296 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7297 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7298 for (j = 0; j < nb_tcs; j++) {
7299 tc_queue->tc_rxq[0][j].base = j;
7300 tc_queue->tc_rxq[0][j].nb_queue = 1;
7301 tc_queue->tc_txq[0][j].base = j;
7302 tc_queue->tc_txq[0][j].nb_queue = 1;
7305 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7306 for (j = 0; j < nb_tcs; j++) {
7307 tc_queue->tc_rxq[i][j].base =
7309 tc_queue->tc_rxq[i][j].nb_queue = 1;
7310 tc_queue->tc_txq[i][j].base =
7312 tc_queue->tc_txq[i][j].nb_queue = 1;
7316 } else { /* vt is disabled*/
7317 struct rte_eth_dcb_rx_conf *rx_conf =
7318 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7319 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7320 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7321 if (dcb_info->nb_tcs == ETH_4_TCS) {
7322 for (i = 0; i < dcb_info->nb_tcs; i++) {
7323 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7324 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7326 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7327 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7328 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7329 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7330 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7331 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7332 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7333 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7334 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7335 for (i = 0; i < dcb_info->nb_tcs; i++) {
7336 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7337 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7339 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7340 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7341 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7342 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7343 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7344 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7345 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7346 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7347 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7348 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7349 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7350 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7351 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7352 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7353 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7354 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7357 for (i = 0; i < dcb_info->nb_tcs; i++) {
7358 tc = &dcb_config->tc_config[i];
7359 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7364 /* Update e-tag ether type */
7366 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7367 uint16_t ether_type)
7369 uint32_t etag_etype;
7371 if (hw->mac.type != ixgbe_mac_X550 &&
7372 hw->mac.type != ixgbe_mac_X550EM_x &&
7373 hw->mac.type != ixgbe_mac_X550EM_a) {
7377 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7378 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7379 etag_etype |= ether_type;
7380 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7381 IXGBE_WRITE_FLUSH(hw);
7386 /* Config l2 tunnel ether type */
7388 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7389 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7392 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7393 struct ixgbe_l2_tn_info *l2_tn_info =
7394 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7396 if (l2_tunnel == NULL)
7399 switch (l2_tunnel->l2_tunnel_type) {
7400 case RTE_L2_TUNNEL_TYPE_E_TAG:
7401 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7402 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7405 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7413 /* Enable e-tag tunnel */
7415 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7417 uint32_t etag_etype;
7419 if (hw->mac.type != ixgbe_mac_X550 &&
7420 hw->mac.type != ixgbe_mac_X550EM_x &&
7421 hw->mac.type != ixgbe_mac_X550EM_a) {
7425 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7426 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7427 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7428 IXGBE_WRITE_FLUSH(hw);
7433 /* Enable l2 tunnel */
7435 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7436 enum rte_eth_tunnel_type l2_tunnel_type)
7439 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7440 struct ixgbe_l2_tn_info *l2_tn_info =
7441 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7443 switch (l2_tunnel_type) {
7444 case RTE_L2_TUNNEL_TYPE_E_TAG:
7445 l2_tn_info->e_tag_en = TRUE;
7446 ret = ixgbe_e_tag_enable(hw);
7449 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7457 /* Disable e-tag tunnel */
7459 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7461 uint32_t etag_etype;
7463 if (hw->mac.type != ixgbe_mac_X550 &&
7464 hw->mac.type != ixgbe_mac_X550EM_x &&
7465 hw->mac.type != ixgbe_mac_X550EM_a) {
7469 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7470 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7471 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7472 IXGBE_WRITE_FLUSH(hw);
7477 /* Disable l2 tunnel */
7479 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7480 enum rte_eth_tunnel_type l2_tunnel_type)
7483 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7484 struct ixgbe_l2_tn_info *l2_tn_info =
7485 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7487 switch (l2_tunnel_type) {
7488 case RTE_L2_TUNNEL_TYPE_E_TAG:
7489 l2_tn_info->e_tag_en = FALSE;
7490 ret = ixgbe_e_tag_disable(hw);
7493 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7502 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7503 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7506 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7507 uint32_t i, rar_entries;
7508 uint32_t rar_low, rar_high;
7510 if (hw->mac.type != ixgbe_mac_X550 &&
7511 hw->mac.type != ixgbe_mac_X550EM_x &&
7512 hw->mac.type != ixgbe_mac_X550EM_a) {
7516 rar_entries = ixgbe_get_num_rx_addrs(hw);
7518 for (i = 1; i < rar_entries; i++) {
7519 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7520 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7521 if ((rar_high & IXGBE_RAH_AV) &&
7522 (rar_high & IXGBE_RAH_ADTYPE) &&
7523 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7524 l2_tunnel->tunnel_id)) {
7525 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7526 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7528 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7538 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7539 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7542 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7543 uint32_t i, rar_entries;
7544 uint32_t rar_low, rar_high;
7546 if (hw->mac.type != ixgbe_mac_X550 &&
7547 hw->mac.type != ixgbe_mac_X550EM_x &&
7548 hw->mac.type != ixgbe_mac_X550EM_a) {
7552 /* One entry for one tunnel. Try to remove potential existing entry. */
7553 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7555 rar_entries = ixgbe_get_num_rx_addrs(hw);
7557 for (i = 1; i < rar_entries; i++) {
7558 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7559 if (rar_high & IXGBE_RAH_AV) {
7562 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7563 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7564 rar_low = l2_tunnel->tunnel_id;
7566 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7567 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7573 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7574 " Please remove a rule before adding a new one.");
7578 static inline struct ixgbe_l2_tn_filter *
7579 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7580 struct ixgbe_l2_tn_key *key)
7584 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7588 return l2_tn_info->hash_map[ret];
7592 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7593 struct ixgbe_l2_tn_filter *l2_tn_filter)
7597 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7598 &l2_tn_filter->key);
7602 "Failed to insert L2 tunnel filter"
7603 " to hash table %d!",
7608 l2_tn_info->hash_map[ret] = l2_tn_filter;
7610 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7616 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7617 struct ixgbe_l2_tn_key *key)
7620 struct ixgbe_l2_tn_filter *l2_tn_filter;
7622 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7626 "No such L2 tunnel filter to delete %d!",
7631 l2_tn_filter = l2_tn_info->hash_map[ret];
7632 l2_tn_info->hash_map[ret] = NULL;
7634 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7635 rte_free(l2_tn_filter);
7640 /* Add l2 tunnel filter */
7642 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7643 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7647 struct ixgbe_l2_tn_info *l2_tn_info =
7648 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7649 struct ixgbe_l2_tn_key key;
7650 struct ixgbe_l2_tn_filter *node;
7653 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7654 key.tn_id = l2_tunnel->tunnel_id;
7656 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7660 "The L2 tunnel filter already exists!");
7664 node = rte_zmalloc("ixgbe_l2_tn",
7665 sizeof(struct ixgbe_l2_tn_filter),
7670 rte_memcpy(&node->key,
7672 sizeof(struct ixgbe_l2_tn_key));
7673 node->pool = l2_tunnel->pool;
7674 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7681 switch (l2_tunnel->l2_tunnel_type) {
7682 case RTE_L2_TUNNEL_TYPE_E_TAG:
7683 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7686 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7691 if ((!restore) && (ret < 0))
7692 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7697 /* Delete l2 tunnel filter */
7699 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7700 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7703 struct ixgbe_l2_tn_info *l2_tn_info =
7704 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7705 struct ixgbe_l2_tn_key key;
7707 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7708 key.tn_id = l2_tunnel->tunnel_id;
7709 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7713 switch (l2_tunnel->l2_tunnel_type) {
7714 case RTE_L2_TUNNEL_TYPE_E_TAG:
7715 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7718 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7727 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7728 * @dev: pointer to rte_eth_dev structure
7729 * @filter_op:operation will be taken.
7730 * @arg: a pointer to specific structure corresponding to the filter_op
7733 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7734 enum rte_filter_op filter_op,
7739 if (filter_op == RTE_ETH_FILTER_NOP)
7743 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7748 switch (filter_op) {
7749 case RTE_ETH_FILTER_ADD:
7750 ret = ixgbe_dev_l2_tunnel_filter_add
7752 (struct rte_eth_l2_tunnel_conf *)arg,
7755 case RTE_ETH_FILTER_DELETE:
7756 ret = ixgbe_dev_l2_tunnel_filter_del
7758 (struct rte_eth_l2_tunnel_conf *)arg);
7761 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7769 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7773 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7775 if (hw->mac.type != ixgbe_mac_X550 &&
7776 hw->mac.type != ixgbe_mac_X550EM_x &&
7777 hw->mac.type != ixgbe_mac_X550EM_a) {
7781 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7782 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7784 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7785 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7790 /* Enable l2 tunnel forwarding */
7792 ixgbe_dev_l2_tunnel_forwarding_enable
7793 (struct rte_eth_dev *dev,
7794 enum rte_eth_tunnel_type l2_tunnel_type)
7796 struct ixgbe_l2_tn_info *l2_tn_info =
7797 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7800 switch (l2_tunnel_type) {
7801 case RTE_L2_TUNNEL_TYPE_E_TAG:
7802 l2_tn_info->e_tag_fwd_en = TRUE;
7803 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7806 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7814 /* Disable l2 tunnel forwarding */
7816 ixgbe_dev_l2_tunnel_forwarding_disable
7817 (struct rte_eth_dev *dev,
7818 enum rte_eth_tunnel_type l2_tunnel_type)
7820 struct ixgbe_l2_tn_info *l2_tn_info =
7821 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7824 switch (l2_tunnel_type) {
7825 case RTE_L2_TUNNEL_TYPE_E_TAG:
7826 l2_tn_info->e_tag_fwd_en = FALSE;
7827 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7830 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7839 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7840 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7843 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7845 uint32_t vmtir, vmvir;
7846 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7848 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7850 "VF id %u should be less than %u",
7856 if (hw->mac.type != ixgbe_mac_X550 &&
7857 hw->mac.type != ixgbe_mac_X550EM_x &&
7858 hw->mac.type != ixgbe_mac_X550EM_a) {
7863 vmtir = l2_tunnel->tunnel_id;
7867 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7869 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7870 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7872 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7873 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7878 /* Enable l2 tunnel tag insertion */
7880 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7881 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7885 switch (l2_tunnel->l2_tunnel_type) {
7886 case RTE_L2_TUNNEL_TYPE_E_TAG:
7887 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7890 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7898 /* Disable l2 tunnel tag insertion */
7900 ixgbe_dev_l2_tunnel_insertion_disable
7901 (struct rte_eth_dev *dev,
7902 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7906 switch (l2_tunnel->l2_tunnel_type) {
7907 case RTE_L2_TUNNEL_TYPE_E_TAG:
7908 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7911 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7920 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7925 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7927 if (hw->mac.type != ixgbe_mac_X550 &&
7928 hw->mac.type != ixgbe_mac_X550EM_x &&
7929 hw->mac.type != ixgbe_mac_X550EM_a) {
7933 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7935 qde |= IXGBE_QDE_STRIP_TAG;
7937 qde &= ~IXGBE_QDE_STRIP_TAG;
7938 qde &= ~IXGBE_QDE_READ;
7939 qde |= IXGBE_QDE_WRITE;
7940 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7945 /* Enable l2 tunnel tag stripping */
7947 ixgbe_dev_l2_tunnel_stripping_enable
7948 (struct rte_eth_dev *dev,
7949 enum rte_eth_tunnel_type l2_tunnel_type)
7953 switch (l2_tunnel_type) {
7954 case RTE_L2_TUNNEL_TYPE_E_TAG:
7955 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7958 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7966 /* Disable l2 tunnel tag stripping */
7968 ixgbe_dev_l2_tunnel_stripping_disable
7969 (struct rte_eth_dev *dev,
7970 enum rte_eth_tunnel_type l2_tunnel_type)
7974 switch (l2_tunnel_type) {
7975 case RTE_L2_TUNNEL_TYPE_E_TAG:
7976 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7979 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7987 /* Enable/disable l2 tunnel offload functions */
7989 ixgbe_dev_l2_tunnel_offload_set
7990 (struct rte_eth_dev *dev,
7991 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7997 if (l2_tunnel == NULL)
8001 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8003 ret = ixgbe_dev_l2_tunnel_enable(
8005 l2_tunnel->l2_tunnel_type);
8007 ret = ixgbe_dev_l2_tunnel_disable(
8009 l2_tunnel->l2_tunnel_type);
8012 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8014 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8018 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8023 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8025 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8027 l2_tunnel->l2_tunnel_type);
8029 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8031 l2_tunnel->l2_tunnel_type);
8034 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8036 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8038 l2_tunnel->l2_tunnel_type);
8040 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8042 l2_tunnel->l2_tunnel_type);
8049 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8052 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8053 IXGBE_WRITE_FLUSH(hw);
8058 /* There's only one register for VxLAN UDP port.
8059 * So, we cannot add several ports. Will update it.
8062 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8066 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8070 return ixgbe_update_vxlan_port(hw, port);
8073 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8074 * UDP port, it must have a value.
8075 * So, will reset it to the original value 0.
8078 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8083 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8085 if (cur_port != port) {
8086 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8090 return ixgbe_update_vxlan_port(hw, 0);
8093 /* Add UDP tunneling port */
8095 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8096 struct rte_eth_udp_tunnel *udp_tunnel)
8099 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8101 if (hw->mac.type != ixgbe_mac_X550 &&
8102 hw->mac.type != ixgbe_mac_X550EM_x &&
8103 hw->mac.type != ixgbe_mac_X550EM_a) {
8107 if (udp_tunnel == NULL)
8110 switch (udp_tunnel->prot_type) {
8111 case RTE_TUNNEL_TYPE_VXLAN:
8112 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8115 case RTE_TUNNEL_TYPE_GENEVE:
8116 case RTE_TUNNEL_TYPE_TEREDO:
8117 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8122 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8130 /* Remove UDP tunneling port */
8132 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8133 struct rte_eth_udp_tunnel *udp_tunnel)
8136 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8138 if (hw->mac.type != ixgbe_mac_X550 &&
8139 hw->mac.type != ixgbe_mac_X550EM_x &&
8140 hw->mac.type != ixgbe_mac_X550EM_a) {
8144 if (udp_tunnel == NULL)
8147 switch (udp_tunnel->prot_type) {
8148 case RTE_TUNNEL_TYPE_VXLAN:
8149 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8151 case RTE_TUNNEL_TYPE_GENEVE:
8152 case RTE_TUNNEL_TYPE_TEREDO:
8153 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8157 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8166 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8168 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8170 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8174 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8176 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8178 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8181 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8183 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8186 /* peek the message first */
8187 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8189 /* PF reset VF event */
8190 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8191 /* dummy mbx read to ack pf */
8192 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8194 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8200 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8203 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8204 struct ixgbe_interrupt *intr =
8205 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8206 ixgbevf_intr_disable(hw);
8208 /* read-on-clear nic registers here */
8209 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8212 /* only one misc vector supported - mailbox */
8213 eicr &= IXGBE_VTEICR_MASK;
8214 if (eicr == IXGBE_MISC_VEC_ID)
8215 intr->flags |= IXGBE_FLAG_MAILBOX;
8221 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8223 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8224 struct ixgbe_interrupt *intr =
8225 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8227 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8228 ixgbevf_mbx_process(dev);
8229 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8232 ixgbevf_intr_enable(hw);
8238 ixgbevf_dev_interrupt_handler(void *param)
8240 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8242 ixgbevf_dev_interrupt_get_status(dev);
8243 ixgbevf_dev_interrupt_action(dev);
8247 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8248 * @hw: pointer to hardware structure
8250 * Stops the transmit data path and waits for the HW to internally empty
8251 * the Tx security block
8253 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8255 #define IXGBE_MAX_SECTX_POLL 40
8260 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8261 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8262 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8263 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8264 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8265 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8267 /* Use interrupt-safe sleep just in case */
8271 /* For informational purposes only */
8272 if (i >= IXGBE_MAX_SECTX_POLL)
8273 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8274 "path fully disabled. Continuing with init.");
8276 return IXGBE_SUCCESS;
8280 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8281 * @hw: pointer to hardware structure
8283 * Enables the transmit data path.
8285 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8289 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8290 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8291 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8292 IXGBE_WRITE_FLUSH(hw);
8294 return IXGBE_SUCCESS;
8297 /* restore n-tuple filter */
8299 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8301 struct ixgbe_filter_info *filter_info =
8302 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8303 struct ixgbe_5tuple_filter *node;
8305 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8306 ixgbe_inject_5tuple_filter(dev, node);
8310 /* restore ethernet type filter */
8312 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8314 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8315 struct ixgbe_filter_info *filter_info =
8316 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8319 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8320 if (filter_info->ethertype_mask & (1 << i)) {
8321 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8322 filter_info->ethertype_filters[i].etqf);
8323 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8324 filter_info->ethertype_filters[i].etqs);
8325 IXGBE_WRITE_FLUSH(hw);
8330 /* restore SYN filter */
8332 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8334 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8335 struct ixgbe_filter_info *filter_info =
8336 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8339 synqf = filter_info->syn_info;
8341 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8342 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8343 IXGBE_WRITE_FLUSH(hw);
8347 /* restore L2 tunnel filter */
8349 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8351 struct ixgbe_l2_tn_info *l2_tn_info =
8352 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8353 struct ixgbe_l2_tn_filter *node;
8354 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8356 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8357 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8358 l2_tn_conf.tunnel_id = node->key.tn_id;
8359 l2_tn_conf.pool = node->pool;
8360 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8364 /* restore rss filter */
8366 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8368 struct ixgbe_filter_info *filter_info =
8369 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8371 if (filter_info->rss_info.conf.queue_num)
8372 ixgbe_config_rss_filter(dev,
8373 &filter_info->rss_info, TRUE);
8377 ixgbe_filter_restore(struct rte_eth_dev *dev)
8379 ixgbe_ntuple_filter_restore(dev);
8380 ixgbe_ethertype_filter_restore(dev);
8381 ixgbe_syn_filter_restore(dev);
8382 ixgbe_fdir_filter_restore(dev);
8383 ixgbe_l2_tn_filter_restore(dev);
8384 ixgbe_rss_filter_restore(dev);
8390 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8392 struct ixgbe_l2_tn_info *l2_tn_info =
8393 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8394 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8396 if (l2_tn_info->e_tag_en)
8397 (void)ixgbe_e_tag_enable(hw);
8399 if (l2_tn_info->e_tag_fwd_en)
8400 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8402 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8405 /* remove all the n-tuple filters */
8407 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8409 struct ixgbe_filter_info *filter_info =
8410 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8411 struct ixgbe_5tuple_filter *p_5tuple;
8413 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8414 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8417 /* remove all the ether type filters */
8419 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8421 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8422 struct ixgbe_filter_info *filter_info =
8423 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8426 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8427 if (filter_info->ethertype_mask & (1 << i) &&
8428 !filter_info->ethertype_filters[i].conf) {
8429 (void)ixgbe_ethertype_filter_remove(filter_info,
8431 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8432 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8433 IXGBE_WRITE_FLUSH(hw);
8438 /* remove the SYN filter */
8440 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8442 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8443 struct ixgbe_filter_info *filter_info =
8444 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8446 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8447 filter_info->syn_info = 0;
8449 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8450 IXGBE_WRITE_FLUSH(hw);
8454 /* remove all the L2 tunnel filters */
8456 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8458 struct ixgbe_l2_tn_info *l2_tn_info =
8459 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8460 struct ixgbe_l2_tn_filter *l2_tn_filter;
8461 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8464 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8465 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8466 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8467 l2_tn_conf.pool = l2_tn_filter->pool;
8468 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8476 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8477 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8478 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8479 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8480 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8481 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8483 RTE_INIT(ixgbe_init_log);
8485 ixgbe_init_log(void)
8487 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8488 if (ixgbe_logtype_init >= 0)
8489 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8490 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8491 if (ixgbe_logtype_driver >= 0)
8492 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);