drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 /* Additional timesync values. */
 104 #define NSEC_PER_SEC             1000000000L
 105 #define IXGBE_INCVAL_10GB        0x66666666
 106 #define IXGBE_INCVAL_1GB         0x40000000
 107 #define IXGBE_INCVAL_100         0x50000000
 108 #define IXGBE_INCVAL_SHIFT_10GB  28
 109 #define IXGBE_INCVAL_SHIFT_1GB   24
 110 #define IXGBE_INCVAL_SHIFT_100   21
 111 #define IXGBE_INCVAL_SHIFT_82599 7
 112 #define IXGBE_INCPER_SHIFT_82599 24
 113
 114 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 117 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 118 #define IXGBE_ETAG_ETYPE                       0x00005084
 119 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 120 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 121 #define IXGBE_RAH_ADTYPE                       0x40000000
 122 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 123 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 124 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 125 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 126 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 127 #define IXGBE_VTEICR_MASK                      0x07
 128
 129 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 130 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 131
 132 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 133 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 151                                 int wait_to_complete);
 152 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 153                                 struct rte_eth_stats *stats);
 154 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 155                                 struct rte_eth_xstat *xstats, unsigned n);
 156 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 157                                   struct rte_eth_xstat *xstats, unsigned n);
 158 static int
 159 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 160                 uint64_t *values, unsigned int n);
 161 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 162 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 163 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names,
 165         unsigned int size);
 166 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 168 static int ixgbe_dev_xstats_get_names_by_id(
 169         struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         const uint64_t *ids,
 172         unsigned int limit);
 173 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 174                                              uint16_t queue_id,
 175                                              uint8_t stat_idx,
 176                                              uint8_t is_rx);
 177 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 178                                  size_t fw_size);
 179 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 180                                struct rte_eth_dev_info *dev_info);
 181 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 182 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 183                                  struct rte_eth_dev_info *dev_info);
 184 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 185
 186 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 187                 uint16_t vlan_id, int on);
 188 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 189                                enum rte_vlan_type vlan_type,
 190                                uint16_t tpid_id);
 191 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 192                 uint16_t queue, bool on);
 193 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 194                 int on);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 221                                       struct rte_intr_handle *handle);
 222 static void ixgbe_dev_interrupt_handler(void *param);
 223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 224 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 225                          uint32_t index, uint32_t pool);
 226 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 227 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 228                                            struct ether_addr *mac_addr);
 229 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 230 static bool is_device_supported(struct rte_eth_dev *dev,
 231                                 struct rte_pci_driver *drv);
 232
 233 /* For Virtual Function support */
 234 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 235 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 236 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 237 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 238 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 239                                    int wait_to_complete);
 240 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 242 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 244 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 245 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 255                                             uint16_t queue_id);
 256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 257                                              uint16_t queue_id);
 258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 259                                  uint8_t queue, uint8_t msix_vector);
 260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 263
 264 /* For Eth VMDQ APIs support */
 265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 266                 ether_addr * mac_addr, uint8_t on);
 267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 268 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 269                 struct rte_eth_mirror_conf *mirror_conf,
 270                 uint8_t rule_id, uint8_t on);
 271 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 272                 uint8_t rule_id);
 273 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 274                                           uint16_t queue_id);
 275 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 276                                            uint16_t queue_id);
 277 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 278                                uint8_t queue, uint8_t msix_vector);
 279 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 280
 281 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 282                                 struct ether_addr *mac_addr,
 283                                 uint32_t index, uint32_t pool);
 284 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 285 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 286                                              struct ether_addr *mac_addr);
 287 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 288                         struct rte_eth_syn_filter *filter);
 289 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 290                         enum rte_filter_op filter_op,
 291                         void *arg);
 292 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 293                         struct ixgbe_5tuple_filter *filter);
 294 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 295                         struct ixgbe_5tuple_filter *filter);
 296 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 297                                 enum rte_filter_op filter_op,
 298                                 void *arg);
 299 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 300                         struct rte_eth_ntuple_filter *filter);
 301 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 302                                 enum rte_filter_op filter_op,
 303                                 void *arg);
 304 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 305                         struct rte_eth_ethertype_filter *filter);
 306 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 307                      enum rte_filter_type filter_type,
 308                      enum rte_filter_op filter_op,
 309                      void *arg);
 310 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 311
 312 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 313                                       struct ether_addr *mc_addr_set,
 314                                       uint32_t nb_mc_addr);
 315 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 316                                    struct rte_eth_dcb_info *dcb_info);
 317
 318 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 319 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 320                             struct rte_dev_reg_info *regs);
 321 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 323                                 struct rte_dev_eeprom_info *eeprom);
 324 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 325                                 struct rte_dev_eeprom_info *eeprom);
 326
 327 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 328                                  struct rte_eth_dev_module_info *modinfo);
 329 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 330                                    struct rte_dev_eeprom_info *info);
 331
 332 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 334                                 struct rte_dev_reg_info *regs);
 335
 336 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 337 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 339                                             struct timespec *timestamp,
 340                                             uint32_t flags);
 341 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 342                                             struct timespec *timestamp);
 343 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 344 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 345                                    struct timespec *timestamp);
 346 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 347                                    const struct timespec *timestamp);
 348 static void ixgbevf_dev_interrupt_handler(void *param);
 349
 350 static int ixgbe_dev_l2_tunnel_eth_type_conf
 351         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 352 static int ixgbe_dev_l2_tunnel_offload_set
 353         (struct rte_eth_dev *dev,
 354          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 355          uint32_t mask,
 356          uint8_t en);
 357 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 358                                              enum rte_filter_op filter_op,
 359                                              void *arg);
 360
 361 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 362                                          struct rte_eth_udp_tunnel *udp_tunnel);
 363 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 364                                          struct rte_eth_udp_tunnel *udp_tunnel);
 365 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 366 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 367
 368 /*
 369  * Define VF Stats MACRO for Non "cleared on read" register
 370  */
 371 #define UPDATE_VF_STAT(reg, last, cur)                          \
 372 {                                                               \
 373         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 374         cur += (latest - last) & UINT_MAX;                      \
 375         last = latest;                                          \
 376 }
 377
 378 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 379 {                                                                \
 380         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 381         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 382         u64 latest = ((new_msb << 32) | new_lsb);                \
 383         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 384         last = latest;                                           \
 385 }
 386
 387 #define IXGBE_SET_HWSTRIP(h, q) do {\
 388                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 389                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 390                 (h)->bitmap[idx] |= 1 << bit;\
 391         } while (0)
 392
 393 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 394                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 395                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 396                 (h)->bitmap[idx] &= ~(1 << bit);\
 397         } while (0)
 398
 399 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 400                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 402                 (r) = (h)->bitmap[idx] >> bit & 1;\
 403         } while (0)
 404
 405 int ixgbe_logtype_init;
 406 int ixgbe_logtype_driver;
 407
 408 /*
 409  * The set of PCI devices this driver supports
 410  */
 411 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 460 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 462 #endif
 463         { .vendor_id = 0, /* sentinel */ },
 464 };
 465
 466 /*
 467  * The set of PCI devices this driver supports (for 82599 VF)
 468  */
 469 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 480         { .vendor_id = 0, /* sentinel */ },
 481 };
 482
 483 static const struct rte_eth_desc_lim rx_desc_lim = {
 484         .nb_max = IXGBE_MAX_RING_DESC,
 485         .nb_min = IXGBE_MIN_RING_DESC,
 486         .nb_align = IXGBE_RXD_ALIGN,
 487 };
 488
 489 static const struct rte_eth_desc_lim tx_desc_lim = {
 490         .nb_max = IXGBE_MAX_RING_DESC,
 491         .nb_min = IXGBE_MIN_RING_DESC,
 492         .nb_align = IXGBE_TXD_ALIGN,
 493         .nb_seg_max = IXGBE_TX_MAX_SEG,
 494         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 495 };
 496
 497 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 498         .dev_configure        = ixgbe_dev_configure,
 499         .dev_start            = ixgbe_dev_start,
 500         .dev_stop             = ixgbe_dev_stop,
 501         .dev_set_link_up    = ixgbe_dev_set_link_up,
 502         .dev_set_link_down  = ixgbe_dev_set_link_down,
 503         .dev_close            = ixgbe_dev_close,
 504         .dev_reset            = ixgbe_dev_reset,
 505         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 506         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 507         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 508         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 509         .link_update          = ixgbe_dev_link_update,
 510         .stats_get            = ixgbe_dev_stats_get,
 511         .xstats_get           = ixgbe_dev_xstats_get,
 512         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 513         .stats_reset          = ixgbe_dev_stats_reset,
 514         .xstats_reset         = ixgbe_dev_xstats_reset,
 515         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 516         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 517         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 518         .fw_version_get       = ixgbe_fw_version_get,
 519         .dev_infos_get        = ixgbe_dev_info_get,
 520         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 521         .mtu_set              = ixgbe_dev_mtu_set,
 522         .vlan_filter_set      = ixgbe_vlan_filter_set,
 523         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 524         .vlan_offload_set     = ixgbe_vlan_offload_set,
 525         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 526         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 527         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 528         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 529         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 530         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 531         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 532         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 533         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 534         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 535         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 536         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 537         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 538         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 539         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 540         .dev_led_on           = ixgbe_dev_led_on,
 541         .dev_led_off          = ixgbe_dev_led_off,
 542         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 543         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 544         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 545         .mac_addr_add         = ixgbe_add_rar,
 546         .mac_addr_remove      = ixgbe_remove_rar,
 547         .mac_addr_set         = ixgbe_set_default_mac_addr,
 548         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 549         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 550         .mirror_rule_set      = ixgbe_mirror_rule_set,
 551         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 552         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 553         .reta_update          = ixgbe_dev_rss_reta_update,
 554         .reta_query           = ixgbe_dev_rss_reta_query,
 555         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 556         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 557         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 558         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 559         .rxq_info_get         = ixgbe_rxq_info_get,
 560         .txq_info_get         = ixgbe_txq_info_get,
 561         .timesync_enable      = ixgbe_timesync_enable,
 562         .timesync_disable     = ixgbe_timesync_disable,
 563         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 564         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 565         .get_reg              = ixgbe_get_regs,
 566         .get_eeprom_length    = ixgbe_get_eeprom_length,
 567         .get_eeprom           = ixgbe_get_eeprom,
 568         .set_eeprom           = ixgbe_set_eeprom,
 569         .get_module_info      = ixgbe_get_module_info,
 570         .get_module_eeprom    = ixgbe_get_module_eeprom,
 571         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 572         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 573         .timesync_read_time   = ixgbe_timesync_read_time,
 574         .timesync_write_time  = ixgbe_timesync_write_time,
 575         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 576         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 577         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 578         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 579         .tm_ops_get           = ixgbe_tm_ops_get,
 580 };
 581
 582 /*
 583  * dev_ops for virtual function, bare necessities for basic vf
 584  * operation have been implemented
 585  */
 586 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 587         .dev_configure        = ixgbevf_dev_configure,
 588         .dev_start            = ixgbevf_dev_start,
 589         .dev_stop             = ixgbevf_dev_stop,
 590         .link_update          = ixgbevf_dev_link_update,
 591         .stats_get            = ixgbevf_dev_stats_get,
 592         .xstats_get           = ixgbevf_dev_xstats_get,
 593         .stats_reset          = ixgbevf_dev_stats_reset,
 594         .xstats_reset         = ixgbevf_dev_stats_reset,
 595         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 596         .dev_close            = ixgbevf_dev_close,
 597         .dev_reset            = ixgbevf_dev_reset,
 598         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 599         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 600         .dev_infos_get        = ixgbevf_dev_info_get,
 601         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 602         .mtu_set              = ixgbevf_dev_set_mtu,
 603         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 604         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 605         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 606         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 607         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 608         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 609         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 610         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 611         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 612         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 613         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 614         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 615         .mac_addr_add         = ixgbevf_add_mac_addr,
 616         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 617         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 618         .rxq_info_get         = ixgbe_rxq_info_get,
 619         .txq_info_get         = ixgbe_txq_info_get,
 620         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 621         .get_reg              = ixgbevf_get_regs,
 622         .reta_update          = ixgbe_dev_rss_reta_update,
 623         .reta_query           = ixgbe_dev_rss_reta_query,
 624         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 625         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 626 };
 627
 628 /* store statistics names and its offset in stats structure */
 629 struct rte_ixgbe_xstats_name_off {
 630         char name[RTE_ETH_XSTATS_NAME_SIZE];
 631         unsigned offset;
 632 };
 633
 634 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 635         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 636         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 637         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 638         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 639         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 640         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 641         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 642         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 643         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 644         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 645         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 646         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 647         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 648         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 649         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 650                 prc1023)},
 651         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 652                 prc1522)},
 653         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 654         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 655         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 656         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 657         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 658         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 659         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 660         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 661         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 662         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 663         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 664         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 665         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 666         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 667         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 668         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 669         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 670                 ptc1023)},
 671         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 672                 ptc1522)},
 673         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 674         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 675         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 676         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 677
 678         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 679                 fdirustat_add)},
 680         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 681                 fdirustat_remove)},
 682         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 683                 fdirfstat_fadd)},
 684         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 685                 fdirfstat_fremove)},
 686         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 687                 fdirmatch)},
 688         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 689                 fdirmiss)},
 690
 691         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 692         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 693         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 694                 fclast)},
 695         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 696         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 697         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 698         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 699         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 700                 fcoe_noddp)},
 701         {"rx_fcoe_no_direct_data_placement_ext_buff",
 702                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 703
 704         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxontxc)},
 706         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxonrxc)},
 708         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 709                 lxofftxc)},
 710         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 711                 lxoffrxc)},
 712         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 713 };
 714
 715 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 716                            sizeof(rte_ixgbe_stats_strings[0]))
 717
 718 /* MACsec statistics */
 719 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 720         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_untagged)},
 722         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_pkts_encrypted)},
 724         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_pkts_protected)},
 726         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 727                 out_octets_encrypted)},
 728         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 729                 out_octets_protected)},
 730         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_untagged)},
 732         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_badtag)},
 734         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 735                 in_pkts_nosci)},
 736         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 737                 in_pkts_unknownsci)},
 738         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 739                 in_octets_decrypted)},
 740         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 741                 in_octets_validated)},
 742         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_unchecked)},
 744         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_delayed)},
 746         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_late)},
 748         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_ok)},
 750         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_invalid)},
 752         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notvalid)},
 754         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_unusedsa)},
 756         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_notusingsa)},
 758 };
 759
 760 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 761                            sizeof(rte_ixgbe_macsec_strings[0]))
 762
 763 /* Per-queue statistics */
 764 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 765         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 766         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 767         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 768         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 769 };
 770
 771 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 772                            sizeof(rte_ixgbe_rxq_strings[0]))
 773 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 774
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 776         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 777         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 778         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 779                 pxon2offc)},
 780 };
 781
 782 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 783                            sizeof(rte_ixgbe_txq_strings[0]))
 784 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 785
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 787         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 788 };
 789
 790 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 791                 sizeof(rte_ixgbevf_stats_strings[0]))
 792
 793 /*
 794  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 795  */
 796 static inline int
 797 ixgbe_is_sfp(struct ixgbe_hw *hw)
 798 {
 799         switch (hw->phy.type) {
 800         case ixgbe_phy_sfp_avago:
 801         case ixgbe_phy_sfp_ftl:
 802         case ixgbe_phy_sfp_intel:
 803         case ixgbe_phy_sfp_unknown:
 804         case ixgbe_phy_sfp_passive_tyco:
 805         case ixgbe_phy_sfp_passive_unknown:
 806                 return 1;
 807         default:
 808                 return 0;
 809         }
 810 }
 811
 812 static inline int32_t
 813 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 814 {
 815         uint32_t ctrl_ext;
 816         int32_t status;
 817
 818         status = ixgbe_reset_hw(hw);
 819
 820         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 821         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 822         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 823         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 824         IXGBE_WRITE_FLUSH(hw);
 825
 826         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 827                 status = IXGBE_SUCCESS;
 828         return status;
 829 }
 830
 831 static inline void
 832 ixgbe_enable_intr(struct rte_eth_dev *dev)
 833 {
 834         struct ixgbe_interrupt *intr =
 835                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 836         struct ixgbe_hw *hw =
 837                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 838
 839         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 840         IXGBE_WRITE_FLUSH(hw);
 841 }
 842
 843 /*
 844  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 845  */
 846 static void
 847 ixgbe_disable_intr(struct ixgbe_hw *hw)
 848 {
 849         PMD_INIT_FUNC_TRACE();
 850
 851         if (hw->mac.type == ixgbe_mac_82598EB) {
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 853         } else {
 854                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 857         }
 858         IXGBE_WRITE_FLUSH(hw);
 859 }
 860
 861 /*
 862  * This function resets queue statistics mapping registers.
 863  * From Niantic datasheet, Initialization of Statistics section:
 864  * "...if software requires the queue counters, the RQSMR and TQSM registers
 865  * must be re-programmed following a device reset.
 866  */
 867 static void
 868 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 869 {
 870         uint32_t i;
 871
 872         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 873                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 874                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 875         }
 876 }
 877
 878
 879 static int
 880 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 881                                   uint16_t queue_id,
 882                                   uint8_t stat_idx,
 883                                   uint8_t is_rx)
 884 {
 885 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 886 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 887 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 888
 889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 890         struct ixgbe_stat_mapping_registers *stat_mappings =
 891                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 892         uint32_t qsmr_mask = 0;
 893         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 894         uint32_t q_map;
 895         uint8_t n, offset;
 896
 897         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 898                 (hw->mac.type != ixgbe_mac_X540) &&
 899                 (hw->mac.type != ixgbe_mac_X550) &&
 900                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_a))
 902                 return -ENOSYS;
 903
 904         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 905                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 906                      queue_id, stat_idx);
 907
 908         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 909         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 910                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 911                 return -EIO;
 912         }
 913         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 914
 915         /* Now clear any previous stat_idx set */
 916         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 917         if (!is_rx)
 918                 stat_mappings->tqsm[n] &= ~clearing_mask;
 919         else
 920                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 921
 922         q_map = (uint32_t)stat_idx;
 923         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 924         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 925         if (!is_rx)
 926                 stat_mappings->tqsm[n] |= qsmr_mask;
 927         else
 928                 stat_mappings->rqsmr[n] |= qsmr_mask;
 929
 930         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 931                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 932                      queue_id, stat_idx);
 933         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 934                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 935
 936         /* Now write the mapping in the appropriate register */
 937         if (is_rx) {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 939                              stat_mappings->rqsmr[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 941         } else {
 942                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 943                              stat_mappings->tqsm[n], n);
 944                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 945         }
 946         return 0;
 947 }
 948
 949 static void
 950 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 951 {
 952         struct ixgbe_stat_mapping_registers *stat_mappings =
 953                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 955         int i;
 956
 957         /* write whatever was in stat mapping table to the NIC */
 958         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 959                 /* rx */
 960                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 961
 962                 /* tx */
 963                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 964         }
 965 }
 966
 967 static void
 968 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 969 {
 970         uint8_t i;
 971         struct ixgbe_dcb_tc_config *tc;
 972         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 973
 974         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 975         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 976         for (i = 0; i < dcb_max_tc; i++) {
 977                 tc = &dcb_config->tc_config[i];
 978                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 980                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 981                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 983                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 984                 tc->pfc = ixgbe_dcb_pfc_disabled;
 985         }
 986
 987         /* Initialize default user to priority mapping, UPx->TC0 */
 988         tc = &dcb_config->tc_config[0];
 989         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 990         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 992                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 993                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 994         }
 995         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 996         dcb_config->pfc_mode_enable = false;
 997         dcb_config->vt_mode = true;
 998         dcb_config->round_robin_enable = false;
 999         /* support all DCB capabilities in 82599 */
1000         dcb_config->support.capabilities = 0xFF;
1001
1002         /*we only support 4 Tcs for X540, X550 */
1003         if (hw->mac.type == ixgbe_mac_X540 ||
1004                 hw->mac.type == ixgbe_mac_X550 ||
1005                 hw->mac.type == ixgbe_mac_X550EM_x ||
1006                 hw->mac.type == ixgbe_mac_X550EM_a) {
1007                 dcb_config->num_tcs.pg_tcs = 4;
1008                 dcb_config->num_tcs.pfc_tcs = 4;
1009         }
1010 }
1011
1012 /*
1013  * Ensure that all locks are released before first NVM or PHY access
1014  */
1015 static void
1016 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1017 {
1018         uint16_t mask;
1019
1020         /*
1021          * Phy lock should not fail in this early stage. If this is the case,
1022          * it is due to an improper exit of the application.
1023          * So force the release of the faulty lock. Release of common lock
1024          * is done automatically by swfw_sync function.
1025          */
1026         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1027         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1028                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1029         }
1030         ixgbe_release_swfw_semaphore(hw, mask);
1031
1032         /*
1033          * These ones are more tricky since they are common to all ports; but
1034          * swfw_sync retries last long enough (1s) to be almost sure that if
1035          * lock can not be taken it is due to an improper lock of the
1036          * semaphore.
1037          */
1038         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1039         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1040                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1041         }
1042         ixgbe_release_swfw_semaphore(hw, mask);
1043 }
1044
1045 /*
1046  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1047  * It returns 0 on success.
1048  */
1049 static int
1050 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1051 {
1052         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1053         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1054         struct ixgbe_hw *hw =
1055                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1056         struct ixgbe_vfta *shadow_vfta =
1057                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1058         struct ixgbe_hwstrip *hwstrip =
1059                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1060         struct ixgbe_dcb_config *dcb_config =
1061                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1062         struct ixgbe_filter_info *filter_info =
1063                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1064         struct ixgbe_bw_conf *bw_conf =
1065                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1066         uint32_t ctrl_ext;
1067         uint16_t csum;
1068         int diag, i;
1069
1070         PMD_INIT_FUNC_TRACE();
1071
1072         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1073         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1074         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1075         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1076
1077         /*
1078          * For secondary processes, we don't initialise any further as primary
1079          * has already done this work. Only check we don't need a different
1080          * RX and TX function.
1081          */
1082         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1083                 struct ixgbe_tx_queue *txq;
1084                 /* TX queue function in primary, set by last queue initialized
1085                  * Tx queue may not initialized by primary process
1086                  */
1087                 if (eth_dev->data->tx_queues) {
1088                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1089                         ixgbe_set_tx_function(eth_dev, txq);
1090                 } else {
1091                         /* Use default TX function if we get here */
1092                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1093                                      "Using default TX function.");
1094                 }
1095
1096                 ixgbe_set_rx_function(eth_dev);
1097
1098                 return 0;
1099         }
1100
1101         rte_eth_copy_pci_info(eth_dev, pci_dev);
1102
1103         /* Vendor and Device ID need to be set before init of shared code */
1104         hw->device_id = pci_dev->id.device_id;
1105         hw->vendor_id = pci_dev->id.vendor_id;
1106         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1107         hw->allow_unsupported_sfp = 1;
1108
1109         /* Initialize the shared code (base driver) */
1110 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1111         diag = ixgbe_bypass_init_shared_code(hw);
1112 #else
1113         diag = ixgbe_init_shared_code(hw);
1114 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1115
1116         if (diag != IXGBE_SUCCESS) {
1117                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1118                 return -EIO;
1119         }
1120
1121         /* pick up the PCI bus settings for reporting later */
1122         ixgbe_get_bus_info(hw);
1123
1124         /* Unlock any pending hardware semaphore */
1125         ixgbe_swfw_lock_reset(hw);
1126
1127 #ifdef RTE_LIBRTE_SECURITY
1128         /* Initialize security_ctx only for primary process*/
1129         if (ixgbe_ipsec_ctx_create(eth_dev))
1130                 return -ENOMEM;
1131 #endif
1132
1133         /* Initialize DCB configuration*/
1134         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1135         ixgbe_dcb_init(hw, dcb_config);
1136         /* Get Hardware Flow Control setting */
1137         hw->fc.requested_mode = ixgbe_fc_full;
1138         hw->fc.current_mode = ixgbe_fc_full;
1139         hw->fc.pause_time = IXGBE_FC_PAUSE;
1140         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1141                 hw->fc.low_water[i] = IXGBE_FC_LO;
1142                 hw->fc.high_water[i] = IXGBE_FC_HI;
1143         }
1144         hw->fc.send_xon = 1;
1145
1146         /* Make sure we have a good EEPROM before we read from it */
1147         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1150                 return -EIO;
1151         }
1152
1153 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1154         diag = ixgbe_bypass_init_hw(hw);
1155 #else
1156         diag = ixgbe_init_hw(hw);
1157 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1158
1159         /*
1160          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1161          * is called too soon after the kernel driver unbinding/binding occurs.
1162          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1163          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1164          * also called. See ixgbe_identify_phy_82599(). The reason for the
1165          * failure is not known, and only occuts when virtualisation features
1166          * are disabled in the bios. A delay of 100ms  was found to be enough by
1167          * trial-and-error, and is doubled to be safe.
1168          */
1169         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1170                 rte_delay_ms(200);
1171                 diag = ixgbe_init_hw(hw);
1172         }
1173
1174         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1175                 diag = IXGBE_SUCCESS;
1176
1177         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1178                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1179                              "LOM.  Please be aware there may be issues associated "
1180                              "with your hardware.");
1181                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1182                              "please contact your Intel or hardware representative "
1183                              "who provided you with this hardware.");
1184         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1185                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1186         if (diag) {
1187                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1188                 return -EIO;
1189         }
1190
1191         /* Reset the hw statistics */
1192         ixgbe_dev_stats_reset(eth_dev);
1193
1194         /* disable interrupt */
1195         ixgbe_disable_intr(hw);
1196
1197         /* reset mappings for queue statistics hw counters*/
1198         ixgbe_reset_qstat_mappings(hw);
1199
1200         /* Allocate memory for storing MAC addresses */
1201         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1202                                                hw->mac.num_rar_entries, 0);
1203         if (eth_dev->data->mac_addrs == NULL) {
1204                 PMD_INIT_LOG(ERR,
1205                              "Failed to allocate %u bytes needed to store "
1206                              "MAC addresses",
1207                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1208                 return -ENOMEM;
1209         }
1210         /* Copy the permanent MAC address */
1211         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1212                         &eth_dev->data->mac_addrs[0]);
1213
1214         /* Allocate memory for storing hash filter MAC addresses */
1215         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1216                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1217         if (eth_dev->data->hash_mac_addrs == NULL) {
1218                 PMD_INIT_LOG(ERR,
1219                              "Failed to allocate %d bytes needed to store MAC addresses",
1220                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1221                 return -ENOMEM;
1222         }
1223
1224         /* initialize the vfta */
1225         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1226
1227         /* initialize the hw strip bitmap*/
1228         memset(hwstrip, 0, sizeof(*hwstrip));
1229
1230         /* initialize PF if max_vfs not zero */
1231         ixgbe_pf_host_init(eth_dev);
1232
1233         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1234         /* let hardware know driver is loaded */
1235         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1236         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1237         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1238         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1239         IXGBE_WRITE_FLUSH(hw);
1240
1241         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1242                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1243                              (int) hw->mac.type, (int) hw->phy.type,
1244                              (int) hw->phy.sfp_type);
1245         else
1246                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1247                              (int) hw->mac.type, (int) hw->phy.type);
1248
1249         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1250                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1251                      pci_dev->id.device_id);
1252
1253         rte_intr_callback_register(intr_handle,
1254                                    ixgbe_dev_interrupt_handler, eth_dev);
1255
1256         /* enable uio/vfio intr/eventfd mapping */
1257         rte_intr_enable(intr_handle);
1258
1259         /* enable support intr */
1260         ixgbe_enable_intr(eth_dev);
1261
1262         /* initialize filter info */
1263         memset(filter_info, 0,
1264                sizeof(struct ixgbe_filter_info));
1265
1266         /* initialize 5tuple filter list */
1267         TAILQ_INIT(&filter_info->fivetuple_list);
1268
1269         /* initialize flow director filter list & hash */
1270         ixgbe_fdir_filter_init(eth_dev);
1271
1272         /* initialize l2 tunnel filter list & hash */
1273         ixgbe_l2_tn_filter_init(eth_dev);
1274
1275         /* initialize flow filter lists */
1276         ixgbe_filterlist_init();
1277
1278         /* initialize bandwidth configuration info */
1279         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1280
1281         /* initialize Traffic Manager configuration */
1282         ixgbe_tm_conf_init(eth_dev);
1283
1284         return 0;
1285 }
1286
1287 static int
1288 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1289 {
1290         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1291         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1292         struct ixgbe_hw *hw;
1293         int retries = 0;
1294         int ret;
1295
1296         PMD_INIT_FUNC_TRACE();
1297
1298         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1299                 return -EPERM;
1300
1301         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1302
1303         if (hw->adapter_stopped == 0)
1304                 ixgbe_dev_close(eth_dev);
1305
1306         eth_dev->dev_ops = NULL;
1307         eth_dev->rx_pkt_burst = NULL;
1308         eth_dev->tx_pkt_burst = NULL;
1309
1310         /* Unlock any pending hardware semaphore */
1311         ixgbe_swfw_lock_reset(hw);
1312
1313         /* disable uio intr before callback unregister */
1314         rte_intr_disable(intr_handle);
1315
1316         do {
1317                 ret = rte_intr_callback_unregister(intr_handle,
1318                                 ixgbe_dev_interrupt_handler, eth_dev);
1319                 if (ret >= 0) {
1320                         break;
1321                 } else if (ret != -EAGAIN) {
1322                         PMD_INIT_LOG(ERR,
1323                                 "intr callback unregister failed: %d",
1324                                 ret);
1325                         return ret;
1326                 }
1327                 rte_delay_ms(100);
1328         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1329
1330         /* uninitialize PF if max_vfs not zero */
1331         ixgbe_pf_host_uninit(eth_dev);
1332
1333         rte_free(eth_dev->data->mac_addrs);
1334         eth_dev->data->mac_addrs = NULL;
1335
1336         rte_free(eth_dev->data->hash_mac_addrs);
1337         eth_dev->data->hash_mac_addrs = NULL;
1338
1339         /* remove all the fdir filters & hash */
1340         ixgbe_fdir_filter_uninit(eth_dev);
1341
1342         /* remove all the L2 tunnel filters & hash */
1343         ixgbe_l2_tn_filter_uninit(eth_dev);
1344
1345         /* Remove all ntuple filters of the device */
1346         ixgbe_ntuple_filter_uninit(eth_dev);
1347
1348         /* clear all the filters list */
1349         ixgbe_filterlist_flush();
1350
1351         /* Remove all Traffic Manager configuration */
1352         ixgbe_tm_conf_uninit(eth_dev);
1353
1354 #ifdef RTE_LIBRTE_SECURITY
1355         rte_free(eth_dev->security_ctx);
1356 #endif
1357
1358         return 0;
1359 }
1360
1361 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1362 {
1363         struct ixgbe_filter_info *filter_info =
1364                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1365         struct ixgbe_5tuple_filter *p_5tuple;
1366
1367         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1368                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1369                              p_5tuple,
1370                              entries);
1371                 rte_free(p_5tuple);
1372         }
1373         memset(filter_info->fivetuple_mask, 0,
1374                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1375
1376         return 0;
1377 }
1378
1379 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1380 {
1381         struct ixgbe_hw_fdir_info *fdir_info =
1382                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1383         struct ixgbe_fdir_filter *fdir_filter;
1384
1385                 if (fdir_info->hash_map)
1386                 rte_free(fdir_info->hash_map);
1387         if (fdir_info->hash_handle)
1388                 rte_hash_free(fdir_info->hash_handle);
1389
1390         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1391                 TAILQ_REMOVE(&fdir_info->fdir_list,
1392                              fdir_filter,
1393                              entries);
1394                 rte_free(fdir_filter);
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1401 {
1402         struct ixgbe_l2_tn_info *l2_tn_info =
1403                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1404         struct ixgbe_l2_tn_filter *l2_tn_filter;
1405
1406         if (l2_tn_info->hash_map)
1407                 rte_free(l2_tn_info->hash_map);
1408         if (l2_tn_info->hash_handle)
1409                 rte_hash_free(l2_tn_info->hash_handle);
1410
1411         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1412                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1413                              l2_tn_filter,
1414                              entries);
1415                 rte_free(l2_tn_filter);
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1422 {
1423         struct ixgbe_hw_fdir_info *fdir_info =
1424                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1425         char fdir_hash_name[RTE_HASH_NAMESIZE];
1426         struct rte_hash_parameters fdir_hash_params = {
1427                 .name = fdir_hash_name,
1428                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1429                 .key_len = sizeof(union ixgbe_atr_input),
1430                 .hash_func = rte_hash_crc,
1431                 .hash_func_init_val = 0,
1432                 .socket_id = rte_socket_id(),
1433         };
1434
1435         TAILQ_INIT(&fdir_info->fdir_list);
1436         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1437                  "fdir_%s", eth_dev->device->name);
1438         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1439         if (!fdir_info->hash_handle) {
1440                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1441                 return -EINVAL;
1442         }
1443         fdir_info->hash_map = rte_zmalloc("ixgbe",
1444                                           sizeof(struct ixgbe_fdir_filter *) *
1445                                           IXGBE_MAX_FDIR_FILTER_NUM,
1446                                           0);
1447         if (!fdir_info->hash_map) {
1448                 PMD_INIT_LOG(ERR,
1449                              "Failed to allocate memory for fdir hash map!");
1450                 return -ENOMEM;
1451         }
1452         fdir_info->mask_added = FALSE;
1453
1454         return 0;
1455 }
1456
1457 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1458 {
1459         struct ixgbe_l2_tn_info *l2_tn_info =
1460                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1461         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1462         struct rte_hash_parameters l2_tn_hash_params = {
1463                 .name = l2_tn_hash_name,
1464                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1465                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1466                 .hash_func = rte_hash_crc,
1467                 .hash_func_init_val = 0,
1468                 .socket_id = rte_socket_id(),
1469         };
1470
1471         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1472         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1473                  "l2_tn_%s", eth_dev->device->name);
1474         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1475         if (!l2_tn_info->hash_handle) {
1476                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1477                 return -EINVAL;
1478         }
1479         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1480                                    sizeof(struct ixgbe_l2_tn_filter *) *
1481                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1482                                    0);
1483         if (!l2_tn_info->hash_map) {
1484                 PMD_INIT_LOG(ERR,
1485                         "Failed to allocate memory for L2 TN hash map!");
1486                 return -ENOMEM;
1487         }
1488         l2_tn_info->e_tag_en = FALSE;
1489         l2_tn_info->e_tag_fwd_en = FALSE;
1490         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1491
1492         return 0;
1493 }
1494 /*
1495  * Negotiate mailbox API version with the PF.
1496  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1497  * Then we try to negotiate starting with the most recent one.
1498  * If all negotiation attempts fail, then we will proceed with
1499  * the default one (ixgbe_mbox_api_10).
1500  */
1501 static void
1502 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1503 {
1504         int32_t i;
1505
1506         /* start with highest supported, proceed down */
1507         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1508                 ixgbe_mbox_api_12,
1509                 ixgbe_mbox_api_11,
1510                 ixgbe_mbox_api_10,
1511         };
1512
1513         for (i = 0;
1514                         i != RTE_DIM(sup_ver) &&
1515                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1516                         i++)
1517                 ;
1518 }
1519
1520 static void
1521 generate_random_mac_addr(struct ether_addr *mac_addr)
1522 {
1523         uint64_t random;
1524
1525         /* Set Organizationally Unique Identifier (OUI) prefix. */
1526         mac_addr->addr_bytes[0] = 0x00;
1527         mac_addr->addr_bytes[1] = 0x09;
1528         mac_addr->addr_bytes[2] = 0xC0;
1529         /* Force indication of locally assigned MAC address. */
1530         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1531         /* Generate the last 3 bytes of the MAC address with a random number. */
1532         random = rte_rand();
1533         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1534 }
1535
1536 /*
1537  * Virtual Function device init
1538  */
1539 static int
1540 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1541 {
1542         int diag;
1543         uint32_t tc, tcs;
1544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1546         struct ixgbe_hw *hw =
1547                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1548         struct ixgbe_vfta *shadow_vfta =
1549                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1550         struct ixgbe_hwstrip *hwstrip =
1551                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1552         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1553
1554         PMD_INIT_FUNC_TRACE();
1555
1556         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1557         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1558         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1559
1560         /* for secondary processes, we don't initialise any further as primary
1561          * has already done this work. Only check we don't need a different
1562          * RX function
1563          */
1564         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1565                 struct ixgbe_tx_queue *txq;
1566                 /* TX queue function in primary, set by last queue initialized
1567                  * Tx queue may not initialized by primary process
1568                  */
1569                 if (eth_dev->data->tx_queues) {
1570                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1571                         ixgbe_set_tx_function(eth_dev, txq);
1572                 } else {
1573                         /* Use default TX function if we get here */
1574                         PMD_INIT_LOG(NOTICE,
1575                                      "No TX queues configured yet. Using default TX function.");
1576                 }
1577
1578                 ixgbe_set_rx_function(eth_dev);
1579
1580                 return 0;
1581         }
1582
1583         rte_eth_copy_pci_info(eth_dev, pci_dev);
1584
1585         hw->device_id = pci_dev->id.device_id;
1586         hw->vendor_id = pci_dev->id.vendor_id;
1587         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1588
1589         /* initialize the vfta */
1590         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1591
1592         /* initialize the hw strip bitmap*/
1593         memset(hwstrip, 0, sizeof(*hwstrip));
1594
1595         /* Initialize the shared code (base driver) */
1596         diag = ixgbe_init_shared_code(hw);
1597         if (diag != IXGBE_SUCCESS) {
1598                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1599                 return -EIO;
1600         }
1601
1602         /* init_mailbox_params */
1603         hw->mbx.ops.init_params(hw);
1604
1605         /* Reset the hw statistics */
1606         ixgbevf_dev_stats_reset(eth_dev);
1607
1608         /* Disable the interrupts for VF */
1609         ixgbevf_intr_disable(hw);
1610
1611         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1612         diag = hw->mac.ops.reset_hw(hw);
1613
1614         /*
1615          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1616          * the underlying PF driver has not assigned a MAC address to the VF.
1617          * In this case, assign a random MAC address.
1618          */
1619         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1620                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1621                 return diag;
1622         }
1623
1624         /* negotiate mailbox API version to use with the PF. */
1625         ixgbevf_negotiate_api(hw);
1626
1627         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1628         ixgbevf_get_queues(hw, &tcs, &tc);
1629
1630         /* Allocate memory for storing MAC addresses */
1631         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1632                                                hw->mac.num_rar_entries, 0);
1633         if (eth_dev->data->mac_addrs == NULL) {
1634                 PMD_INIT_LOG(ERR,
1635                              "Failed to allocate %u bytes needed to store "
1636                              "MAC addresses",
1637                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1638                 return -ENOMEM;
1639         }
1640
1641         /* Generate a random MAC address, if none was assigned by PF. */
1642         if (is_zero_ether_addr(perm_addr)) {
1643                 generate_random_mac_addr(perm_addr);
1644                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1645                 if (diag) {
1646                         rte_free(eth_dev->data->mac_addrs);
1647                         eth_dev->data->mac_addrs = NULL;
1648                         return diag;
1649                 }
1650                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1651                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1652                              "%02x:%02x:%02x:%02x:%02x:%02x",
1653                              perm_addr->addr_bytes[0],
1654                              perm_addr->addr_bytes[1],
1655                              perm_addr->addr_bytes[2],
1656                              perm_addr->addr_bytes[3],
1657                              perm_addr->addr_bytes[4],
1658                              perm_addr->addr_bytes[5]);
1659         }
1660
1661         /* Copy the permanent MAC address */
1662         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1663
1664         /* reset the hardware with the new settings */
1665         diag = hw->mac.ops.start_hw(hw);
1666         switch (diag) {
1667         case  0:
1668                 break;
1669
1670         default:
1671                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1672                 return -EIO;
1673         }
1674
1675         rte_intr_callback_register(intr_handle,
1676                                    ixgbevf_dev_interrupt_handler, eth_dev);
1677         rte_intr_enable(intr_handle);
1678         ixgbevf_intr_enable(hw);
1679
1680         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1681                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1682                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1683
1684         return 0;
1685 }
1686
1687 /* Virtual Function device uninit */
1688
1689 static int
1690 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1691 {
1692         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1693         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1694         struct ixgbe_hw *hw;
1695
1696         PMD_INIT_FUNC_TRACE();
1697
1698         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1699                 return -EPERM;
1700
1701         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1702
1703         if (hw->adapter_stopped == 0)
1704                 ixgbevf_dev_close(eth_dev);
1705
1706         eth_dev->dev_ops = NULL;
1707         eth_dev->rx_pkt_burst = NULL;
1708         eth_dev->tx_pkt_burst = NULL;
1709
1710         /* Disable the interrupts for VF */
1711         ixgbevf_intr_disable(hw);
1712
1713         rte_free(eth_dev->data->mac_addrs);
1714         eth_dev->data->mac_addrs = NULL;
1715
1716         rte_intr_disable(intr_handle);
1717         rte_intr_callback_unregister(intr_handle,
1718                                      ixgbevf_dev_interrupt_handler, eth_dev);
1719
1720         return 0;
1721 }
1722
1723 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1724         struct rte_pci_device *pci_dev)
1725 {
1726         return rte_eth_dev_pci_generic_probe(pci_dev,
1727                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1728 }
1729
1730 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1731 {
1732         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1733 }
1734
1735 static struct rte_pci_driver rte_ixgbe_pmd = {
1736         .id_table = pci_id_ixgbe_map,
1737         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1738                      RTE_PCI_DRV_IOVA_AS_VA,
1739         .probe = eth_ixgbe_pci_probe,
1740         .remove = eth_ixgbe_pci_remove,
1741 };
1742
1743 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1744         struct rte_pci_device *pci_dev)
1745 {
1746         return rte_eth_dev_pci_generic_probe(pci_dev,
1747                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1748 }
1749
1750 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1751 {
1752         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1753 }
1754
1755 /*
1756  * virtual function driver struct
1757  */
1758 static struct rte_pci_driver rte_ixgbevf_pmd = {
1759         .id_table = pci_id_ixgbevf_map,
1760         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1761         .probe = eth_ixgbevf_pci_probe,
1762         .remove = eth_ixgbevf_pci_remove,
1763 };
1764
1765 static int
1766 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1767 {
1768         struct ixgbe_hw *hw =
1769                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770         struct ixgbe_vfta *shadow_vfta =
1771                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1772         uint32_t vfta;
1773         uint32_t vid_idx;
1774         uint32_t vid_bit;
1775
1776         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1777         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1778         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1779         if (on)
1780                 vfta |= vid_bit;
1781         else
1782                 vfta &= ~vid_bit;
1783         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1784
1785         /* update local VFTA copy */
1786         shadow_vfta->vfta[vid_idx] = vfta;
1787
1788         return 0;
1789 }
1790
1791 static void
1792 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1793 {
1794         if (on)
1795                 ixgbe_vlan_hw_strip_enable(dev, queue);
1796         else
1797                 ixgbe_vlan_hw_strip_disable(dev, queue);
1798 }
1799
1800 static int
1801 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1802                     enum rte_vlan_type vlan_type,
1803                     uint16_t tpid)
1804 {
1805         struct ixgbe_hw *hw =
1806                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807         int ret = 0;
1808         uint32_t reg;
1809         uint32_t qinq;
1810
1811         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1812         qinq &= IXGBE_DMATXCTL_GDV;
1813
1814         switch (vlan_type) {
1815         case ETH_VLAN_TYPE_INNER:
1816                 if (qinq) {
1817                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1818                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1819                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1820                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1821                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1822                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1823                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1824                 } else {
1825                         ret = -ENOTSUP;
1826                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1827                                     " by single VLAN");
1828                 }
1829                 break;
1830         case ETH_VLAN_TYPE_OUTER:
1831                 if (qinq) {
1832                         /* Only the high 16-bits is valid */
1833                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1834                                         IXGBE_EXVET_VET_EXT_SHIFT);
1835                 } else {
1836                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1837                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1838                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1839                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1840                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1841                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1842                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1843                 }
1844
1845                 break;
1846         default:
1847                 ret = -EINVAL;
1848                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1849                 break;
1850         }
1851
1852         return ret;
1853 }
1854
1855 void
1856 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1857 {
1858         struct ixgbe_hw *hw =
1859                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860         uint32_t vlnctrl;
1861
1862         PMD_INIT_FUNC_TRACE();
1863
1864         /* Filter Table Disable */
1865         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1866         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1867
1868         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1869 }
1870
1871 void
1872 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1873 {
1874         struct ixgbe_hw *hw =
1875                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876         struct ixgbe_vfta *shadow_vfta =
1877                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1878         uint32_t vlnctrl;
1879         uint16_t i;
1880
1881         PMD_INIT_FUNC_TRACE();
1882
1883         /* Filter Table Enable */
1884         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1885         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1886         vlnctrl |= IXGBE_VLNCTRL_VFE;
1887
1888         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1889
1890         /* write whatever is in local vfta copy */
1891         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1892                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1893 }
1894
1895 static void
1896 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1897 {
1898         struct ixgbe_hwstrip *hwstrip =
1899                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1900         struct ixgbe_rx_queue *rxq;
1901
1902         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1903                 return;
1904
1905         if (on)
1906                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1907         else
1908                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1909
1910         if (queue >= dev->data->nb_rx_queues)
1911                 return;
1912
1913         rxq = dev->data->rx_queues[queue];
1914
1915         if (on)
1916                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1917         else
1918                 rxq->vlan_flags = PKT_RX_VLAN;
1919 }
1920
1921 static void
1922 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1923 {
1924         struct ixgbe_hw *hw =
1925                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         uint32_t ctrl;
1927
1928         PMD_INIT_FUNC_TRACE();
1929
1930         if (hw->mac.type == ixgbe_mac_82598EB) {
1931                 /* No queue level support */
1932                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1933                 return;
1934         }
1935
1936         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1937         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1938         ctrl &= ~IXGBE_RXDCTL_VME;
1939         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1940
1941         /* record those setting for HW strip per queue */
1942         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1943 }
1944
1945 static void
1946 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1947 {
1948         struct ixgbe_hw *hw =
1949                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950         uint32_t ctrl;
1951
1952         PMD_INIT_FUNC_TRACE();
1953
1954         if (hw->mac.type == ixgbe_mac_82598EB) {
1955                 /* No queue level supported */
1956                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1957                 return;
1958         }
1959
1960         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1961         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1962         ctrl |= IXGBE_RXDCTL_VME;
1963         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1964
1965         /* record those setting for HW strip per queue */
1966         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1967 }
1968
1969 static void
1970 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1971 {
1972         struct ixgbe_hw *hw =
1973                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974         uint32_t ctrl;
1975
1976         PMD_INIT_FUNC_TRACE();
1977
1978         /* DMATXCTRL: Geric Double VLAN Disable */
1979         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1980         ctrl &= ~IXGBE_DMATXCTL_GDV;
1981         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1982
1983         /* CTRL_EXT: Global Double VLAN Disable */
1984         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1985         ctrl &= ~IXGBE_EXTENDED_VLAN;
1986         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1987
1988 }
1989
1990 static void
1991 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1992 {
1993         struct ixgbe_hw *hw =
1994                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1995         uint32_t ctrl;
1996
1997         PMD_INIT_FUNC_TRACE();
1998
1999         /* DMATXCTRL: Geric Double VLAN Enable */
2000         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2001         ctrl |= IXGBE_DMATXCTL_GDV;
2002         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2003
2004         /* CTRL_EXT: Global Double VLAN Enable */
2005         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2006         ctrl |= IXGBE_EXTENDED_VLAN;
2007         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2008
2009         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2010         if (hw->mac.type == ixgbe_mac_X550 ||
2011             hw->mac.type == ixgbe_mac_X550EM_x ||
2012             hw->mac.type == ixgbe_mac_X550EM_a) {
2013                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2014                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2015                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2016         }
2017
2018         /*
2019          * VET EXT field in the EXVET register = 0x8100 by default
2020          * So no need to change. Same to VT field of DMATXCTL register
2021          */
2022 }
2023
2024 void
2025 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2026 {
2027         struct ixgbe_hw *hw =
2028                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2030         uint32_t ctrl;
2031         uint16_t i;
2032         struct ixgbe_rx_queue *rxq;
2033         bool on;
2034
2035         PMD_INIT_FUNC_TRACE();
2036
2037         if (hw->mac.type == ixgbe_mac_82598EB) {
2038                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2039                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2040                         ctrl |= IXGBE_VLNCTRL_VME;
2041                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2042                 } else {
2043                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2044                         ctrl &= ~IXGBE_VLNCTRL_VME;
2045                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2046                 }
2047         } else {
2048                 /*
2049                  * Other 10G NIC, the VLAN strip can be setup
2050                  * per queue in RXDCTL
2051                  */
2052                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2053                         rxq = dev->data->rx_queues[i];
2054                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2055                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2056                                 ctrl |= IXGBE_RXDCTL_VME;
2057                                 on = TRUE;
2058                         } else {
2059                                 ctrl &= ~IXGBE_RXDCTL_VME;
2060                                 on = FALSE;
2061                         }
2062                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2063
2064                         /* record those setting for HW strip per queue */
2065                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2066                 }
2067         }
2068 }
2069
2070 static int
2071 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2072 {
2073         struct rte_eth_rxmode *rxmode;
2074         rxmode = &dev->data->dev_conf.rxmode;
2075
2076         if (mask & ETH_VLAN_STRIP_MASK) {
2077                 ixgbe_vlan_hw_strip_config(dev);
2078         }
2079
2080         if (mask & ETH_VLAN_FILTER_MASK) {
2081                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2082                         ixgbe_vlan_hw_filter_enable(dev);
2083                 else
2084                         ixgbe_vlan_hw_filter_disable(dev);
2085         }
2086
2087         if (mask & ETH_VLAN_EXTEND_MASK) {
2088                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2089                         ixgbe_vlan_hw_extend_enable(dev);
2090                 else
2091                         ixgbe_vlan_hw_extend_disable(dev);
2092         }
2093
2094         return 0;
2095 }
2096
2097 static void
2098 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2099 {
2100         struct ixgbe_hw *hw =
2101                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2103         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2104
2105         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2106         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2107 }
2108
2109 static int
2110 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2111 {
2112         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2113
2114         switch (nb_rx_q) {
2115         case 1:
2116         case 2:
2117                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2118                 break;
2119         case 4:
2120                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2121                 break;
2122         default:
2123                 return -EINVAL;
2124         }
2125
2126         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2127                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2128         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2129                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2130         return 0;
2131 }
2132
2133 static int
2134 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2135 {
2136         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2137         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2138         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2139         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2140
2141         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2142                 /* check multi-queue mode */
2143                 switch (dev_conf->rxmode.mq_mode) {
2144                 case ETH_MQ_RX_VMDQ_DCB:
2145                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2146                         break;
2147                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2148                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2149                         PMD_INIT_LOG(ERR, "SRIOV active,"
2150                                         " unsupported mq_mode rx %d.",
2151                                         dev_conf->rxmode.mq_mode);
2152                         return -EINVAL;
2153                 case ETH_MQ_RX_RSS:
2154                 case ETH_MQ_RX_VMDQ_RSS:
2155                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2156                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2157                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2158                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2159                                                 " invalid queue number"
2160                                                 " for VMDQ RSS, allowed"
2161                                                 " value are 1, 2 or 4.");
2162                                         return -EINVAL;
2163                                 }
2164                         break;
2165                 case ETH_MQ_RX_VMDQ_ONLY:
2166                 case ETH_MQ_RX_NONE:
2167                         /* if nothing mq mode configure, use default scheme */
2168                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2169                         break;
2170                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2171                         /* SRIOV only works in VMDq enable mode */
2172                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2173                                         " wrong mq_mode rx %d.",
2174                                         dev_conf->rxmode.mq_mode);
2175                         return -EINVAL;
2176                 }
2177
2178                 switch (dev_conf->txmode.mq_mode) {
2179                 case ETH_MQ_TX_VMDQ_DCB:
2180                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2181                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2182                         break;
2183                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2184                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2185                         break;
2186                 }
2187
2188                 /* check valid queue number */
2189                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2190                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2191                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2192                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2193                                         " must be less than or equal to %d.",
2194                                         nb_rx_q, nb_tx_q,
2195                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2196                         return -EINVAL;
2197                 }
2198         } else {
2199                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2200                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2201                                           " not supported.");
2202                         return -EINVAL;
2203                 }
2204                 /* check configuration for vmdb+dcb mode */
2205                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2206                         const struct rte_eth_vmdq_dcb_conf *conf;
2207
2208                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2209                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2210                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2211                                 return -EINVAL;
2212                         }
2213                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2214                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2215                                conf->nb_queue_pools == ETH_32_POOLS)) {
2216                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2217                                                 " nb_queue_pools must be %d or %d.",
2218                                                 ETH_16_POOLS, ETH_32_POOLS);
2219                                 return -EINVAL;
2220                         }
2221                 }
2222                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2223                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2224
2225                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2226                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2227                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2228                                 return -EINVAL;
2229                         }
2230                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2231                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2232                                conf->nb_queue_pools == ETH_32_POOLS)) {
2233                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2234                                                 " nb_queue_pools != %d and"
2235                                                 " nb_queue_pools != %d.",
2236                                                 ETH_16_POOLS, ETH_32_POOLS);
2237                                 return -EINVAL;
2238                         }
2239                 }
2240
2241                 /* For DCB mode check our configuration before we go further */
2242                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2243                         const struct rte_eth_dcb_rx_conf *conf;
2244
2245                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2246                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2247                                                  IXGBE_DCB_NB_QUEUES);
2248                                 return -EINVAL;
2249                         }
2250                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2251                         if (!(conf->nb_tcs == ETH_4_TCS ||
2252                                conf->nb_tcs == ETH_8_TCS)) {
2253                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2254                                                 " and nb_tcs != %d.",
2255                                                 ETH_4_TCS, ETH_8_TCS);
2256                                 return -EINVAL;
2257                         }
2258                 }
2259
2260                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2261                         const struct rte_eth_dcb_tx_conf *conf;
2262
2263                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2264                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2265                                                  IXGBE_DCB_NB_QUEUES);
2266                                 return -EINVAL;
2267                         }
2268                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2269                         if (!(conf->nb_tcs == ETH_4_TCS ||
2270                                conf->nb_tcs == ETH_8_TCS)) {
2271                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2272                                                 " and nb_tcs != %d.",
2273                                                 ETH_4_TCS, ETH_8_TCS);
2274                                 return -EINVAL;
2275                         }
2276                 }
2277
2278                 /*
2279                  * When DCB/VT is off, maximum number of queues changes,
2280                  * except for 82598EB, which remains constant.
2281                  */
2282                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2283                                 hw->mac.type != ixgbe_mac_82598EB) {
2284                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2285                                 PMD_INIT_LOG(ERR,
2286                                              "Neither VT nor DCB are enabled, "
2287                                              "nb_tx_q > %d.",
2288                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2289                                 return -EINVAL;
2290                         }
2291                 }
2292         }
2293         return 0;
2294 }
2295
2296 static int
2297 ixgbe_dev_configure(struct rte_eth_dev *dev)
2298 {
2299         struct ixgbe_interrupt *intr =
2300                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2301         struct ixgbe_adapter *adapter =
2302                 (struct ixgbe_adapter *)dev->data->dev_private;
2303         struct rte_eth_dev_info dev_info;
2304         uint64_t rx_offloads;
2305         uint64_t tx_offloads;
2306         int ret;
2307
2308         PMD_INIT_FUNC_TRACE();
2309         /* multipe queue mode checking */
2310         ret  = ixgbe_check_mq_mode(dev);
2311         if (ret != 0) {
2312                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2313                             ret);
2314                 return ret;
2315         }
2316
2317         ixgbe_dev_info_get(dev, &dev_info);
2318         rx_offloads = dev->data->dev_conf.rxmode.offloads;
2319         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2320                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2321                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2322                             rx_offloads, dev_info.rx_offload_capa);
2323                 return -ENOTSUP;
2324         }
2325         tx_offloads = dev->data->dev_conf.txmode.offloads;
2326         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2327                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2328                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2329                             tx_offloads, dev_info.tx_offload_capa);
2330                 return -ENOTSUP;
2331         }
2332
2333         /* set flag to update link status after init */
2334         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2335
2336         /*
2337          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2338          * allocation or vector Rx preconditions we will reset it.
2339          */
2340         adapter->rx_bulk_alloc_allowed = true;
2341         adapter->rx_vec_allowed = true;
2342
2343         return 0;
2344 }
2345
2346 static void
2347 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2348 {
2349         struct ixgbe_hw *hw =
2350                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351         struct ixgbe_interrupt *intr =
2352                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2353         uint32_t gpie;
2354
2355         /* only set up it on X550EM_X */
2356         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2357                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2358                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2359                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2360                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2361                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2362         }
2363 }
2364
2365 int
2366 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2367                         uint16_t tx_rate, uint64_t q_msk)
2368 {
2369         struct ixgbe_hw *hw;
2370         struct ixgbe_vf_info *vfinfo;
2371         struct rte_eth_link link;
2372         uint8_t  nb_q_per_pool;
2373         uint32_t queue_stride;
2374         uint32_t queue_idx, idx = 0, vf_idx;
2375         uint32_t queue_end;
2376         uint16_t total_rate = 0;
2377         struct rte_pci_device *pci_dev;
2378
2379         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2380         rte_eth_link_get_nowait(dev->data->port_id, &link);
2381
2382         if (vf >= pci_dev->max_vfs)
2383                 return -EINVAL;
2384
2385         if (tx_rate > link.link_speed)
2386                 return -EINVAL;
2387
2388         if (q_msk == 0)
2389                 return 0;
2390
2391         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2393         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2394         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2395         queue_idx = vf * queue_stride;
2396         queue_end = queue_idx + nb_q_per_pool - 1;
2397         if (queue_end >= hw->mac.max_tx_queues)
2398                 return -EINVAL;
2399
2400         if (vfinfo) {
2401                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2402                         if (vf_idx == vf)
2403                                 continue;
2404                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2405                                 idx++)
2406                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2407                 }
2408         } else {
2409                 return -EINVAL;
2410         }
2411
2412         /* Store tx_rate for this vf. */
2413         for (idx = 0; idx < nb_q_per_pool; idx++) {
2414                 if (((uint64_t)0x1 << idx) & q_msk) {
2415                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2416                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2417                         total_rate += tx_rate;
2418                 }
2419         }
2420
2421         if (total_rate > dev->data->dev_link.link_speed) {
2422                 /* Reset stored TX rate of the VF if it causes exceed
2423                  * link speed.
2424                  */
2425                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2426                 return -EINVAL;
2427         }
2428
2429         /* Set RTTBCNRC of each queue/pool for vf X  */
2430         for (; queue_idx <= queue_end; queue_idx++) {
2431                 if (0x1 & q_msk)
2432                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2433                 q_msk = q_msk >> 1;
2434         }
2435
2436         return 0;
2437 }
2438
2439 /*
2440  * Configure device link speed and setup link.
2441  * It returns 0 on success.
2442  */
2443 static int
2444 ixgbe_dev_start(struct rte_eth_dev *dev)
2445 {
2446         struct ixgbe_hw *hw =
2447                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2448         struct ixgbe_vf_info *vfinfo =
2449                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2450         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2451         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2452         uint32_t intr_vector = 0;
2453         int err, link_up = 0, negotiate = 0;
2454         uint32_t speed = 0;
2455         uint32_t allowed_speeds = 0;
2456         int mask = 0;
2457         int status;
2458         uint16_t vf, idx;
2459         uint32_t *link_speeds;
2460         struct ixgbe_tm_conf *tm_conf =
2461                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2462
2463         PMD_INIT_FUNC_TRACE();
2464
2465         /* IXGBE devices don't support:
2466         *    - half duplex (checked afterwards for valid speeds)
2467         *    - fixed speed: TODO implement
2468         */
2469         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2470                 PMD_INIT_LOG(ERR,
2471                 "Invalid link_speeds for port %u, fix speed not supported",
2472                                 dev->data->port_id);
2473                 return -EINVAL;
2474         }
2475
2476         /* disable uio/vfio intr/eventfd mapping */
2477         rte_intr_disable(intr_handle);
2478
2479         /* stop adapter */
2480         hw->adapter_stopped = 0;
2481         ixgbe_stop_adapter(hw);
2482
2483         /* reinitialize adapter
2484          * this calls reset and start
2485          */
2486         status = ixgbe_pf_reset_hw(hw);
2487         if (status != 0)
2488                 return -1;
2489         hw->mac.ops.start_hw(hw);
2490         hw->mac.get_link_status = true;
2491
2492         /* configure PF module if SRIOV enabled */
2493         ixgbe_pf_host_configure(dev);
2494
2495         ixgbe_dev_phy_intr_setup(dev);
2496
2497         /* check and configure queue intr-vector mapping */
2498         if ((rte_intr_cap_multiple(intr_handle) ||
2499              !RTE_ETH_DEV_SRIOV(dev).active) &&
2500             dev->data->dev_conf.intr_conf.rxq != 0) {
2501                 intr_vector = dev->data->nb_rx_queues;
2502                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2503                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2504                                         IXGBE_MAX_INTR_QUEUE_NUM);
2505                         return -ENOTSUP;
2506                 }
2507                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2508                         return -1;
2509         }
2510
2511         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2512                 intr_handle->intr_vec =
2513                         rte_zmalloc("intr_vec",
2514                                     dev->data->nb_rx_queues * sizeof(int), 0);
2515                 if (intr_handle->intr_vec == NULL) {
2516                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2517                                      " intr_vec", dev->data->nb_rx_queues);
2518                         return -ENOMEM;
2519                 }
2520         }
2521
2522         /* confiugre msix for sleep until rx interrupt */
2523         ixgbe_configure_msix(dev);
2524
2525         /* initialize transmission unit */
2526         ixgbe_dev_tx_init(dev);
2527
2528         /* This can fail when allocating mbufs for descriptor rings */
2529         err = ixgbe_dev_rx_init(dev);
2530         if (err) {
2531                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2532                 goto error;
2533         }
2534
2535         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2536                 ETH_VLAN_EXTEND_MASK;
2537         err = ixgbe_vlan_offload_set(dev, mask);
2538         if (err) {
2539                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2540                 goto error;
2541         }
2542
2543         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2544                 /* Enable vlan filtering for VMDq */
2545                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2546         }
2547
2548         /* Configure DCB hw */
2549         ixgbe_configure_dcb(dev);
2550
2551         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2552                 err = ixgbe_fdir_configure(dev);
2553                 if (err)
2554                         goto error;
2555         }
2556
2557         /* Restore vf rate limit */
2558         if (vfinfo != NULL) {
2559                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2560                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2561                                 if (vfinfo[vf].tx_rate[idx] != 0)
2562                                         ixgbe_set_vf_rate_limit(
2563                                                 dev, vf,
2564                                                 vfinfo[vf].tx_rate[idx],
2565                                                 1 << idx);
2566         }
2567
2568         ixgbe_restore_statistics_mapping(dev);
2569
2570         err = ixgbe_dev_rxtx_start(dev);
2571         if (err < 0) {
2572                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2573                 goto error;
2574         }
2575
2576         /* Skip link setup if loopback mode is enabled for 82599. */
2577         if (hw->mac.type == ixgbe_mac_82599EB &&
2578                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2579                 goto skip_link_setup;
2580
2581         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2582                 err = hw->mac.ops.setup_sfp(hw);
2583                 if (err)
2584                         goto error;
2585         }
2586
2587         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2588                 /* Turn on the copper */
2589                 ixgbe_set_phy_power(hw, true);
2590         } else {
2591                 /* Turn on the laser */
2592                 ixgbe_enable_tx_laser(hw);
2593         }
2594
2595         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2596         if (err)
2597                 goto error;
2598         dev->data->dev_link.link_status = link_up;
2599
2600         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2601         if (err)
2602                 goto error;
2603
2604         switch (hw->mac.type) {
2605         case ixgbe_mac_X550:
2606         case ixgbe_mac_X550EM_x:
2607         case ixgbe_mac_X550EM_a:
2608                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2609                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2610                         ETH_LINK_SPEED_10G;
2611                 break;
2612         default:
2613                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2614                         ETH_LINK_SPEED_10G;
2615         }
2616
2617         link_speeds = &dev->data->dev_conf.link_speeds;
2618         if (*link_speeds & ~allowed_speeds) {
2619                 PMD_INIT_LOG(ERR, "Invalid link setting");
2620                 goto error;
2621         }
2622
2623         speed = 0x0;
2624         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2625                 switch (hw->mac.type) {
2626                 case ixgbe_mac_82598EB:
2627                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2628                         break;
2629                 case ixgbe_mac_82599EB:
2630                 case ixgbe_mac_X540:
2631                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2632                         break;
2633                 case ixgbe_mac_X550:
2634                 case ixgbe_mac_X550EM_x:
2635                 case ixgbe_mac_X550EM_a:
2636                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2637                         break;
2638                 default:
2639                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2640                 }
2641         } else {
2642                 if (*link_speeds & ETH_LINK_SPEED_10G)
2643                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2644                 if (*link_speeds & ETH_LINK_SPEED_5G)
2645                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2646                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2647                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2648                 if (*link_speeds & ETH_LINK_SPEED_1G)
2649                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2650                 if (*link_speeds & ETH_LINK_SPEED_100M)
2651                         speed |= IXGBE_LINK_SPEED_100_FULL;
2652         }
2653
2654         err = ixgbe_setup_link(hw, speed, link_up);
2655         if (err)
2656                 goto error;
2657
2658         ixgbe_dev_link_update(dev, 0);
2659
2660 skip_link_setup:
2661
2662         if (rte_intr_allow_others(intr_handle)) {
2663                 /* check if lsc interrupt is enabled */
2664                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2665                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2666                 else
2667                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2668                 ixgbe_dev_macsec_interrupt_setup(dev);
2669         } else {
2670                 rte_intr_callback_unregister(intr_handle,
2671                                              ixgbe_dev_interrupt_handler, dev);
2672                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2673                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2674                                      " no intr multiplex");
2675         }
2676
2677         /* check if rxq interrupt is enabled */
2678         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2679             rte_intr_dp_is_en(intr_handle))
2680                 ixgbe_dev_rxq_interrupt_setup(dev);
2681
2682         /* enable uio/vfio intr/eventfd mapping */
2683         rte_intr_enable(intr_handle);
2684
2685         /* resume enabled intr since hw reset */
2686         ixgbe_enable_intr(dev);
2687         ixgbe_l2_tunnel_conf(dev);
2688         ixgbe_filter_restore(dev);
2689
2690         if (tm_conf->root && !tm_conf->committed)
2691                 PMD_DRV_LOG(WARNING,
2692                             "please call hierarchy_commit() "
2693                             "before starting the port");
2694
2695         return 0;
2696
2697 error:
2698         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2699         ixgbe_dev_clear_queues(dev);
2700         return -EIO;
2701 }
2702
2703 /*
2704  * Stop device: disable rx and tx functions to allow for reconfiguring.
2705  */
2706 static void
2707 ixgbe_dev_stop(struct rte_eth_dev *dev)
2708 {
2709         struct rte_eth_link link;
2710         struct ixgbe_hw *hw =
2711                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712         struct ixgbe_vf_info *vfinfo =
2713                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2714         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2715         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2716         int vf;
2717         struct ixgbe_tm_conf *tm_conf =
2718                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2719
2720         PMD_INIT_FUNC_TRACE();
2721
2722         /* disable interrupts */
2723         ixgbe_disable_intr(hw);
2724
2725         /* reset the NIC */
2726         ixgbe_pf_reset_hw(hw);
2727         hw->adapter_stopped = 0;
2728
2729         /* stop adapter */
2730         ixgbe_stop_adapter(hw);
2731
2732         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2733                 vfinfo[vf].clear_to_send = false;
2734
2735         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2736                 /* Turn off the copper */
2737                 ixgbe_set_phy_power(hw, false);
2738         } else {
2739                 /* Turn off the laser */
2740                 ixgbe_disable_tx_laser(hw);
2741         }
2742
2743         ixgbe_dev_clear_queues(dev);
2744
2745         /* Clear stored conf */
2746         dev->data->scattered_rx = 0;
2747         dev->data->lro = 0;
2748
2749         /* Clear recorded link status */
2750         memset(&link, 0, sizeof(link));
2751         rte_eth_linkstatus_set(dev, &link);
2752
2753         if (!rte_intr_allow_others(intr_handle))
2754                 /* resume to the default handler */
2755                 rte_intr_callback_register(intr_handle,
2756                                            ixgbe_dev_interrupt_handler,
2757                                            (void *)dev);
2758
2759         /* Clean datapath event and queue/vec mapping */
2760         rte_intr_efd_disable(intr_handle);
2761         if (intr_handle->intr_vec != NULL) {
2762                 rte_free(intr_handle->intr_vec);
2763                 intr_handle->intr_vec = NULL;
2764         }
2765
2766         /* reset hierarchy commit */
2767         tm_conf->committed = false;
2768 }
2769
2770 /*
2771  * Set device link up: enable tx.
2772  */
2773 static int
2774 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2775 {
2776         struct ixgbe_hw *hw =
2777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778         if (hw->mac.type == ixgbe_mac_82599EB) {
2779 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2780                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2781                         /* Not suported in bypass mode */
2782                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2783                                      "by device id 0x%x", hw->device_id);
2784                         return -ENOTSUP;
2785                 }
2786 #endif
2787         }
2788
2789         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2790                 /* Turn on the copper */
2791                 ixgbe_set_phy_power(hw, true);
2792         } else {
2793                 /* Turn on the laser */
2794                 ixgbe_enable_tx_laser(hw);
2795         }
2796
2797         return 0;
2798 }
2799
2800 /*
2801  * Set device link down: disable tx.
2802  */
2803 static int
2804 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2805 {
2806         struct ixgbe_hw *hw =
2807                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808         if (hw->mac.type == ixgbe_mac_82599EB) {
2809 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2810                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2811                         /* Not suported in bypass mode */
2812                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2813                                      "by device id 0x%x", hw->device_id);
2814                         return -ENOTSUP;
2815                 }
2816 #endif
2817         }
2818
2819         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2820                 /* Turn off the copper */
2821                 ixgbe_set_phy_power(hw, false);
2822         } else {
2823                 /* Turn off the laser */
2824                 ixgbe_disable_tx_laser(hw);
2825         }
2826
2827         return 0;
2828 }
2829
2830 /*
2831  * Reset and stop device.
2832  */
2833 static void
2834 ixgbe_dev_close(struct rte_eth_dev *dev)
2835 {
2836         struct ixgbe_hw *hw =
2837                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838
2839         PMD_INIT_FUNC_TRACE();
2840
2841         ixgbe_pf_reset_hw(hw);
2842
2843         ixgbe_dev_stop(dev);
2844         hw->adapter_stopped = 1;
2845
2846         ixgbe_dev_free_queues(dev);
2847
2848         ixgbe_disable_pcie_master(hw);
2849
2850         /* reprogram the RAR[0] in case user changed it. */
2851         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2852 }
2853
2854 /*
2855  * Reset PF device.
2856  */
2857 static int
2858 ixgbe_dev_reset(struct rte_eth_dev *dev)
2859 {
2860         int ret;
2861
2862         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2863          * its VF to make them align with it. The detailed notification
2864          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2865          * To avoid unexpected behavior in VF, currently reset of PF with
2866          * SR-IOV activation is not supported. It might be supported later.
2867          */
2868         if (dev->data->sriov.active)
2869                 return -ENOTSUP;
2870
2871         ret = eth_ixgbe_dev_uninit(dev);
2872         if (ret)
2873                 return ret;
2874
2875         ret = eth_ixgbe_dev_init(dev);
2876
2877         return ret;
2878 }
2879
2880 static void
2881 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2882                            struct ixgbe_hw_stats *hw_stats,
2883                            struct ixgbe_macsec_stats *macsec_stats,
2884                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2885                            uint64_t *total_qprc, uint64_t *total_qprdc)
2886 {
2887         uint32_t bprc, lxon, lxoff, total;
2888         uint32_t delta_gprc = 0;
2889         unsigned i;
2890         /* Workaround for RX byte count not including CRC bytes when CRC
2891          * strip is enabled. CRC bytes are removed from counters when crc_strip
2892          * is disabled.
2893          */
2894         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2895                         IXGBE_HLREG0_RXCRCSTRP);
2896
2897         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2898         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2899         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2900         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2901
2902         for (i = 0; i < 8; i++) {
2903                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2904
2905                 /* global total per queue */
2906                 hw_stats->mpc[i] += mp;
2907                 /* Running comprehensive total for stats display */
2908                 *total_missed_rx += hw_stats->mpc[i];
2909                 if (hw->mac.type == ixgbe_mac_82598EB) {
2910                         hw_stats->rnbc[i] +=
2911                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2912                         hw_stats->pxonrxc[i] +=
2913                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2914                         hw_stats->pxoffrxc[i] +=
2915                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2916                 } else {
2917                         hw_stats->pxonrxc[i] +=
2918                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2919                         hw_stats->pxoffrxc[i] +=
2920                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2921                         hw_stats->pxon2offc[i] +=
2922                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2923                 }
2924                 hw_stats->pxontxc[i] +=
2925                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2926                 hw_stats->pxofftxc[i] +=
2927                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2928         }
2929         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2930                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2931                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2932                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2933
2934                 delta_gprc += delta_qprc;
2935
2936                 hw_stats->qprc[i] += delta_qprc;
2937                 hw_stats->qptc[i] += delta_qptc;
2938
2939                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2940                 hw_stats->qbrc[i] +=
2941                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2942                 if (crc_strip == 0)
2943                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2944
2945                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2946                 hw_stats->qbtc[i] +=
2947                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2948
2949                 hw_stats->qprdc[i] += delta_qprdc;
2950                 *total_qprdc += hw_stats->qprdc[i];
2951
2952                 *total_qprc += hw_stats->qprc[i];
2953                 *total_qbrc += hw_stats->qbrc[i];
2954         }
2955         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2956         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2957         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2958
2959         /*
2960          * An errata states that gprc actually counts good + missed packets:
2961          * Workaround to set gprc to summated queue packet receives
2962          */
2963         hw_stats->gprc = *total_qprc;
2964
2965         if (hw->mac.type != ixgbe_mac_82598EB) {
2966                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2967                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2968                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2969                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2970                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2971                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2972                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2973                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2974         } else {
2975                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2976                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2977                 /* 82598 only has a counter in the high register */
2978                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2979                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2980                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2981         }
2982         uint64_t old_tpr = hw_stats->tpr;
2983
2984         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2985         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2986
2987         if (crc_strip == 0)
2988                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2989
2990         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2991         hw_stats->gptc += delta_gptc;
2992         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2993         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2994
2995         /*
2996          * Workaround: mprc hardware is incorrectly counting
2997          * broadcasts, so for now we subtract those.
2998          */
2999         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3000         hw_stats->bprc += bprc;
3001         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3002         if (hw->mac.type == ixgbe_mac_82598EB)
3003                 hw_stats->mprc -= bprc;
3004
3005         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3006         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3007         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3008         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3009         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3010         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3011
3012         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3013         hw_stats->lxontxc += lxon;
3014         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3015         hw_stats->lxofftxc += lxoff;
3016         total = lxon + lxoff;
3017
3018         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3019         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3020         hw_stats->gptc -= total;
3021         hw_stats->mptc -= total;
3022         hw_stats->ptc64 -= total;
3023         hw_stats->gotc -= total * ETHER_MIN_LEN;
3024
3025         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3026         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3027         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3028         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3029         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3030         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3031         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3032         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3033         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3034         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3035         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3036         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3037         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3038         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3039         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3040         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3041         /* Only read FCOE on 82599 */
3042         if (hw->mac.type != ixgbe_mac_82598EB) {
3043                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3044                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3045                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3046                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3047                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3048         }
3049
3050         /* Flow Director Stats registers */
3051         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3052         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3053
3054         /* MACsec Stats registers */
3055         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3056         macsec_stats->out_pkts_encrypted +=
3057                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3058         macsec_stats->out_pkts_protected +=
3059                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3060         macsec_stats->out_octets_encrypted +=
3061                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3062         macsec_stats->out_octets_protected +=
3063                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3064         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3065         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3066         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3067         macsec_stats->in_pkts_unknownsci +=
3068                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3069         macsec_stats->in_octets_decrypted +=
3070                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3071         macsec_stats->in_octets_validated +=
3072                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3073         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3074         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3075         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3076         for (i = 0; i < 2; i++) {
3077                 macsec_stats->in_pkts_ok +=
3078                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3079                 macsec_stats->in_pkts_invalid +=
3080                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3081                 macsec_stats->in_pkts_notvalid +=
3082                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3083         }
3084         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3085         macsec_stats->in_pkts_notusingsa +=
3086                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3087 }
3088
3089 /*
3090  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3091  */
3092 static int
3093 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3094 {
3095         struct ixgbe_hw *hw =
3096                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3097         struct ixgbe_hw_stats *hw_stats =
3098                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3099         struct ixgbe_macsec_stats *macsec_stats =
3100                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3101                                 dev->data->dev_private);
3102         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3103         unsigned i;
3104
3105         total_missed_rx = 0;
3106         total_qbrc = 0;
3107         total_qprc = 0;
3108         total_qprdc = 0;
3109
3110         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3111                         &total_qbrc, &total_qprc, &total_qprdc);
3112
3113         if (stats == NULL)
3114                 return -EINVAL;
3115
3116         /* Fill out the rte_eth_stats statistics structure */
3117         stats->ipackets = total_qprc;
3118         stats->ibytes = total_qbrc;
3119         stats->opackets = hw_stats->gptc;
3120         stats->obytes = hw_stats->gotc;
3121
3122         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3123                 stats->q_ipackets[i] = hw_stats->qprc[i];
3124                 stats->q_opackets[i] = hw_stats->qptc[i];
3125                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3126                 stats->q_obytes[i] = hw_stats->qbtc[i];
3127                 stats->q_errors[i] = hw_stats->qprdc[i];
3128         }
3129
3130         /* Rx Errors */
3131         stats->imissed  = total_missed_rx;
3132         stats->ierrors  = hw_stats->crcerrs +
3133                           hw_stats->mspdc +
3134                           hw_stats->rlec +
3135                           hw_stats->ruc +
3136                           hw_stats->roc +
3137                           hw_stats->illerrc +
3138                           hw_stats->errbc +
3139                           hw_stats->rfc +
3140                           hw_stats->fccrc +
3141                           hw_stats->fclast;
3142
3143         /* Tx Errors */
3144         stats->oerrors  = 0;
3145         return 0;
3146 }
3147
3148 static void
3149 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3150 {
3151         struct ixgbe_hw_stats *stats =
3152                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3153
3154         /* HW registers are cleared on read */
3155         ixgbe_dev_stats_get(dev, NULL);
3156
3157         /* Reset software totals */
3158         memset(stats, 0, sizeof(*stats));
3159 }
3160
3161 /* This function calculates the number of xstats based on the current config */
3162 static unsigned
3163 ixgbe_xstats_calc_num(void) {
3164         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3165                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3166                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3167 }
3168
3169 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3170         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3171 {
3172         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3173         unsigned stat, i, count;
3174
3175         if (xstats_names != NULL) {
3176                 count = 0;
3177
3178                 /* Note: limit >= cnt_stats checked upstream
3179                  * in rte_eth_xstats_names()
3180                  */
3181
3182                 /* Extended stats from ixgbe_hw_stats */
3183                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3184                         snprintf(xstats_names[count].name,
3185                                 sizeof(xstats_names[count].name),
3186                                 "%s",
3187                                 rte_ixgbe_stats_strings[i].name);
3188                         count++;
3189                 }
3190
3191                 /* MACsec Stats */
3192                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3193                         snprintf(xstats_names[count].name,
3194                                 sizeof(xstats_names[count].name),
3195                                 "%s",
3196                                 rte_ixgbe_macsec_strings[i].name);
3197                         count++;
3198                 }
3199
3200                 /* RX Priority Stats */
3201                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3202                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3203                                 snprintf(xstats_names[count].name,
3204                                         sizeof(xstats_names[count].name),
3205                                         "rx_priority%u_%s", i,
3206                                         rte_ixgbe_rxq_strings[stat].name);
3207                                 count++;
3208                         }
3209                 }
3210
3211                 /* TX Priority Stats */
3212                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3213                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3214                                 snprintf(xstats_names[count].name,
3215                                         sizeof(xstats_names[count].name),
3216                                         "tx_priority%u_%s", i,
3217                                         rte_ixgbe_txq_strings[stat].name);
3218                                 count++;
3219                         }
3220                 }
3221         }
3222         return cnt_stats;
3223 }
3224
3225 static int ixgbe_dev_xstats_get_names_by_id(
3226         struct rte_eth_dev *dev,
3227         struct rte_eth_xstat_name *xstats_names,
3228         const uint64_t *ids,
3229         unsigned int limit)
3230 {
3231         if (!ids) {
3232                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3233                 unsigned int stat, i, count;
3234
3235                 if (xstats_names != NULL) {
3236                         count = 0;
3237
3238                         /* Note: limit >= cnt_stats checked upstream
3239                          * in rte_eth_xstats_names()
3240                          */
3241
3242                         /* Extended stats from ixgbe_hw_stats */
3243                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3244                                 snprintf(xstats_names[count].name,
3245                                         sizeof(xstats_names[count].name),
3246                                         "%s",
3247                                         rte_ixgbe_stats_strings[i].name);
3248                                 count++;
3249                         }
3250
3251                         /* MACsec Stats */
3252                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3253                                 snprintf(xstats_names[count].name,
3254                                         sizeof(xstats_names[count].name),
3255                                         "%s",
3256                                         rte_ixgbe_macsec_strings[i].name);
3257                                 count++;
3258                         }
3259
3260                         /* RX Priority Stats */
3261                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3262                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3263                                         snprintf(xstats_names[count].name,
3264                                             sizeof(xstats_names[count].name),
3265                                             "rx_priority%u_%s", i,
3266                                             rte_ixgbe_rxq_strings[stat].name);
3267                                         count++;
3268                                 }
3269                         }
3270
3271                         /* TX Priority Stats */
3272                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3273                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3274                                         snprintf(xstats_names[count].name,
3275                                             sizeof(xstats_names[count].name),
3276                                             "tx_priority%u_%s", i,
3277                                             rte_ixgbe_txq_strings[stat].name);
3278                                         count++;
3279                                 }
3280                         }
3281                 }
3282                 return cnt_stats;
3283         }
3284
3285         uint16_t i;
3286         uint16_t size = ixgbe_xstats_calc_num();
3287         struct rte_eth_xstat_name xstats_names_copy[size];
3288
3289         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3290                         size);
3291
3292         for (i = 0; i < limit; i++) {
3293                 if (ids[i] >= size) {
3294                         PMD_INIT_LOG(ERR, "id value isn't valid");
3295                         return -1;
3296                 }
3297                 strcpy(xstats_names[i].name,
3298                                 xstats_names_copy[ids[i]].name);
3299         }
3300         return limit;
3301 }
3302
3303 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3304         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3305 {
3306         unsigned i;
3307
3308         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3309                 return -ENOMEM;
3310
3311         if (xstats_names != NULL)
3312                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3313                         snprintf(xstats_names[i].name,
3314                                 sizeof(xstats_names[i].name),
3315                                 "%s", rte_ixgbevf_stats_strings[i].name);
3316         return IXGBEVF_NB_XSTATS;
3317 }
3318
3319 static int
3320 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3321                                          unsigned n)
3322 {
3323         struct ixgbe_hw *hw =
3324                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3325         struct ixgbe_hw_stats *hw_stats =
3326                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3327         struct ixgbe_macsec_stats *macsec_stats =
3328                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3329                                 dev->data->dev_private);
3330         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3331         unsigned i, stat, count = 0;
3332
3333         count = ixgbe_xstats_calc_num();
3334
3335         if (n < count)
3336                 return count;
3337
3338         total_missed_rx = 0;
3339         total_qbrc = 0;
3340         total_qprc = 0;
3341         total_qprdc = 0;
3342
3343         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3344                         &total_qbrc, &total_qprc, &total_qprdc);
3345
3346         /* If this is a reset xstats is NULL, and we have cleared the
3347          * registers by reading them.
3348          */
3349         if (!xstats)
3350                 return 0;
3351
3352         /* Extended stats from ixgbe_hw_stats */
3353         count = 0;
3354         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3355                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3356                                 rte_ixgbe_stats_strings[i].offset);
3357                 xstats[count].id = count;
3358                 count++;
3359         }
3360
3361         /* MACsec Stats */
3362         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3363                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3364                                 rte_ixgbe_macsec_strings[i].offset);
3365                 xstats[count].id = count;
3366                 count++;
3367         }
3368
3369         /* RX Priority Stats */
3370         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3371                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3372                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3373                                         rte_ixgbe_rxq_strings[stat].offset +
3374                                         (sizeof(uint64_t) * i));
3375                         xstats[count].id = count;
3376                         count++;
3377                 }
3378         }
3379
3380         /* TX Priority Stats */
3381         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3382                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3383                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3384                                         rte_ixgbe_txq_strings[stat].offset +
3385                                         (sizeof(uint64_t) * i));
3386                         xstats[count].id = count;
3387                         count++;
3388                 }
3389         }
3390         return count;
3391 }
3392
3393 static int
3394 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3395                 uint64_t *values, unsigned int n)
3396 {
3397         if (!ids) {
3398                 struct ixgbe_hw *hw =
3399                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3400                 struct ixgbe_hw_stats *hw_stats =
3401                                 IXGBE_DEV_PRIVATE_TO_STATS(
3402                                                 dev->data->dev_private);
3403                 struct ixgbe_macsec_stats *macsec_stats =
3404                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3405                                         dev->data->dev_private);
3406                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3407                 unsigned int i, stat, count = 0;
3408
3409                 count = ixgbe_xstats_calc_num();
3410
3411                 if (!ids && n < count)
3412                         return count;
3413
3414                 total_missed_rx = 0;
3415                 total_qbrc = 0;
3416                 total_qprc = 0;
3417                 total_qprdc = 0;
3418
3419                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3420                                 &total_missed_rx, &total_qbrc, &total_qprc,
3421                                 &total_qprdc);
3422
3423                 /* If this is a reset xstats is NULL, and we have cleared the
3424                  * registers by reading them.
3425                  */
3426                 if (!ids && !values)
3427                         return 0;
3428
3429                 /* Extended stats from ixgbe_hw_stats */
3430                 count = 0;
3431                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3432                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3433                                         rte_ixgbe_stats_strings[i].offset);
3434                         count++;
3435                 }
3436
3437                 /* MACsec Stats */
3438                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3439                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3440                                         rte_ixgbe_macsec_strings[i].offset);
3441                         count++;
3442                 }
3443
3444                 /* RX Priority Stats */
3445                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3446                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3447                                 values[count] =
3448                                         *(uint64_t *)(((char *)hw_stats) +
3449                                         rte_ixgbe_rxq_strings[stat].offset +
3450                                         (sizeof(uint64_t) * i));
3451                                 count++;
3452                         }
3453                 }
3454
3455                 /* TX Priority Stats */
3456                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3457                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3458                                 values[count] =
3459                                         *(uint64_t *)(((char *)hw_stats) +
3460                                         rte_ixgbe_txq_strings[stat].offset +
3461                                         (sizeof(uint64_t) * i));
3462                                 count++;
3463                         }
3464                 }
3465                 return count;
3466         }
3467
3468         uint16_t i;
3469         uint16_t size = ixgbe_xstats_calc_num();
3470         uint64_t values_copy[size];
3471
3472         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3473
3474         for (i = 0; i < n; i++) {
3475                 if (ids[i] >= size) {
3476                         PMD_INIT_LOG(ERR, "id value isn't valid");
3477                         return -1;
3478                 }
3479                 values[i] = values_copy[ids[i]];
3480         }
3481         return n;
3482 }
3483
3484 static void
3485 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3486 {
3487         struct ixgbe_hw_stats *stats =
3488                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3489         struct ixgbe_macsec_stats *macsec_stats =
3490                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3491                                 dev->data->dev_private);
3492
3493         unsigned count = ixgbe_xstats_calc_num();
3494
3495         /* HW registers are cleared on read */
3496         ixgbe_dev_xstats_get(dev, NULL, count);
3497
3498         /* Reset software totals */
3499         memset(stats, 0, sizeof(*stats));
3500         memset(macsec_stats, 0, sizeof(*macsec_stats));
3501 }
3502
3503 static void
3504 ixgbevf_update_stats(struct rte_eth_dev *dev)
3505 {
3506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3507         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3508                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3509
3510         /* Good Rx packet, include VF loopback */
3511         UPDATE_VF_STAT(IXGBE_VFGPRC,
3512             hw_stats->last_vfgprc, hw_stats->vfgprc);
3513
3514         /* Good Rx octets, include VF loopback */
3515         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3516             hw_stats->last_vfgorc, hw_stats->vfgorc);
3517
3518         /* Good Tx packet, include VF loopback */
3519         UPDATE_VF_STAT(IXGBE_VFGPTC,
3520             hw_stats->last_vfgptc, hw_stats->vfgptc);
3521
3522         /* Good Tx octets, include VF loopback */
3523         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3524             hw_stats->last_vfgotc, hw_stats->vfgotc);
3525
3526         /* Rx Multicst Packet */
3527         UPDATE_VF_STAT(IXGBE_VFMPRC,
3528             hw_stats->last_vfmprc, hw_stats->vfmprc);
3529 }
3530
3531 static int
3532 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3533                        unsigned n)
3534 {
3535         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3536                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3537         unsigned i;
3538
3539         if (n < IXGBEVF_NB_XSTATS)
3540                 return IXGBEVF_NB_XSTATS;
3541
3542         ixgbevf_update_stats(dev);
3543
3544         if (!xstats)
3545                 return 0;
3546
3547         /* Extended stats */
3548         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3549                 xstats[i].id = i;
3550                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3551                         rte_ixgbevf_stats_strings[i].offset);
3552         }
3553
3554         return IXGBEVF_NB_XSTATS;
3555 }
3556
3557 static int
3558 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3559 {
3560         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3561                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3562
3563         ixgbevf_update_stats(dev);
3564
3565         if (stats == NULL)
3566                 return -EINVAL;
3567
3568         stats->ipackets = hw_stats->vfgprc;
3569         stats->ibytes = hw_stats->vfgorc;
3570         stats->opackets = hw_stats->vfgptc;
3571         stats->obytes = hw_stats->vfgotc;
3572         return 0;
3573 }
3574
3575 static void
3576 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3577 {
3578         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3579                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3580
3581         /* Sync HW register to the last stats */
3582         ixgbevf_dev_stats_get(dev, NULL);
3583
3584         /* reset HW current stats*/
3585         hw_stats->vfgprc = 0;
3586         hw_stats->vfgorc = 0;
3587         hw_stats->vfgptc = 0;
3588         hw_stats->vfgotc = 0;
3589 }
3590
3591 static int
3592 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3593 {
3594         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3595         u16 eeprom_verh, eeprom_verl;
3596         u32 etrack_id;
3597         int ret;
3598
3599         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3600         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3601
3602         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3603         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3604
3605         ret += 1; /* add the size of '\0' */
3606         if (fw_size < (u32)ret)
3607                 return ret;
3608         else
3609                 return 0;
3610 }
3611
3612 static void
3613 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3614 {
3615         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3616         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3618
3619         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3620         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3621         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3622                 /*
3623                  * When DCB/VT is off, maximum number of queues changes,
3624                  * except for 82598EB, which remains constant.
3625                  */
3626                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3627                                 hw->mac.type != ixgbe_mac_82598EB)
3628                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3629         }
3630         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3631         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3632         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3633         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3634         dev_info->max_vfs = pci_dev->max_vfs;
3635         if (hw->mac.type == ixgbe_mac_82598EB)
3636                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3637         else
3638                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3639         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3640         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3641         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3642                                      dev_info->rx_queue_offload_capa);
3643         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3644         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3645
3646         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3647                 .rx_thresh = {
3648                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3649                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3650                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3651                 },
3652                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3653                 .rx_drop_en = 0,
3654                 .offloads = 0,
3655         };
3656
3657         dev_info->default_txconf = (struct rte_eth_txconf) {
3658                 .tx_thresh = {
3659                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3660                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3661                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3662                 },
3663                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3664                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3665                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3666                              ETH_TXQ_FLAGS_NOOFFLOADS |
3667                              ETH_TXQ_FLAGS_IGNORE,
3668                 .offloads = 0,
3669         };
3670
3671         dev_info->rx_desc_lim = rx_desc_lim;
3672         dev_info->tx_desc_lim = tx_desc_lim;
3673
3674         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3675         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3676         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3677
3678         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3679         if (hw->mac.type == ixgbe_mac_X540 ||
3680             hw->mac.type == ixgbe_mac_X540_vf ||
3681             hw->mac.type == ixgbe_mac_X550 ||
3682             hw->mac.type == ixgbe_mac_X550_vf) {
3683                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3684         }
3685         if (hw->mac.type == ixgbe_mac_X550) {
3686                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3687                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3688         }
3689 }
3690
3691 static const uint32_t *
3692 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3693 {
3694         static const uint32_t ptypes[] = {
3695                 /* For non-vec functions,
3696                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3697                  * for vec functions,
3698                  * refers to _recv_raw_pkts_vec().
3699                  */
3700                 RTE_PTYPE_L2_ETHER,
3701                 RTE_PTYPE_L3_IPV4,
3702                 RTE_PTYPE_L3_IPV4_EXT,
3703                 RTE_PTYPE_L3_IPV6,
3704                 RTE_PTYPE_L3_IPV6_EXT,
3705                 RTE_PTYPE_L4_SCTP,
3706                 RTE_PTYPE_L4_TCP,
3707                 RTE_PTYPE_L4_UDP,
3708                 RTE_PTYPE_TUNNEL_IP,
3709                 RTE_PTYPE_INNER_L3_IPV6,
3710                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3711                 RTE_PTYPE_INNER_L4_TCP,
3712                 RTE_PTYPE_INNER_L4_UDP,
3713                 RTE_PTYPE_UNKNOWN
3714         };
3715
3716         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3717             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3718             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3719             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3720                 return ptypes;
3721
3722 #if defined(RTE_ARCH_X86)
3723         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3724             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3725                 return ptypes;
3726 #endif
3727         return NULL;
3728 }
3729
3730 static void
3731 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3732                      struct rte_eth_dev_info *dev_info)
3733 {
3734         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3735         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3736
3737         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3738         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3739         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3740         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3741         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3742         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3743         dev_info->max_vfs = pci_dev->max_vfs;
3744         if (hw->mac.type == ixgbe_mac_82598EB)
3745                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3746         else
3747                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3748         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3749         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3750                                      dev_info->rx_queue_offload_capa);
3751         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3752         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3753
3754         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3755                 .rx_thresh = {
3756                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3757                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3758                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3759                 },
3760                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3761                 .rx_drop_en = 0,
3762                 .offloads = 0,
3763         };
3764
3765         dev_info->default_txconf = (struct rte_eth_txconf) {
3766                 .tx_thresh = {
3767                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3768                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3769                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3770                 },
3771                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3772                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3773                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3774                              ETH_TXQ_FLAGS_NOOFFLOADS |
3775                              ETH_TXQ_FLAGS_IGNORE,
3776                 .offloads = 0,
3777         };
3778
3779         dev_info->rx_desc_lim = rx_desc_lim;
3780         dev_info->tx_desc_lim = tx_desc_lim;
3781 }
3782
3783 static int
3784 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3785                    int *link_up, int wait_to_complete)
3786 {
3787         /**
3788          * for a quick link status checking, wait_to_compelet == 0,
3789          * skip PF link status checking
3790          */
3791         bool no_pflink_check = wait_to_complete == 0;
3792         struct ixgbe_mbx_info *mbx = &hw->mbx;
3793         struct ixgbe_mac_info *mac = &hw->mac;
3794         uint32_t links_reg, in_msg;
3795         int ret_val = 0;
3796
3797         /* If we were hit with a reset drop the link */
3798         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3799                 mac->get_link_status = true;
3800
3801         if (!mac->get_link_status)
3802                 goto out;
3803
3804         /* if link status is down no point in checking to see if pf is up */
3805         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3806         if (!(links_reg & IXGBE_LINKS_UP))
3807                 goto out;
3808
3809         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3810          * before the link status is correct
3811          */
3812         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3813                 int i;
3814
3815                 for (i = 0; i < 5; i++) {
3816                         rte_delay_us(100);
3817                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3818
3819                         if (!(links_reg & IXGBE_LINKS_UP))
3820                                 goto out;
3821                 }
3822         }
3823
3824         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3825         case IXGBE_LINKS_SPEED_10G_82599:
3826                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3827                 if (hw->mac.type >= ixgbe_mac_X550) {
3828                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3829                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3830                 }
3831                 break;
3832         case IXGBE_LINKS_SPEED_1G_82599:
3833                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3834                 break;
3835         case IXGBE_LINKS_SPEED_100_82599:
3836                 *speed = IXGBE_LINK_SPEED_100_FULL;
3837                 if (hw->mac.type == ixgbe_mac_X550) {
3838                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3839                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3840                 }
3841                 break;
3842         case IXGBE_LINKS_SPEED_10_X550EM_A:
3843                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3844                 /* Since Reserved in older MAC's */
3845                 if (hw->mac.type >= ixgbe_mac_X550)
3846                         *speed = IXGBE_LINK_SPEED_10_FULL;
3847                 break;
3848         default:
3849                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3850         }
3851
3852         if (no_pflink_check) {
3853                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3854                         mac->get_link_status = true;
3855                 else
3856                         mac->get_link_status = false;
3857
3858                 goto out;
3859         }
3860         /* if the read failed it could just be a mailbox collision, best wait
3861          * until we are called again and don't report an error
3862          */
3863         if (mbx->ops.read(hw, &in_msg, 1, 0))
3864                 goto out;
3865
3866         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3867                 /* msg is not CTS and is NACK we must have lost CTS status */
3868                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3869                         ret_val = -1;
3870                 goto out;
3871         }
3872
3873         /* the pf is talking, if we timed out in the past we reinit */
3874         if (!mbx->timeout) {
3875                 ret_val = -1;
3876                 goto out;
3877         }
3878
3879         /* if we passed all the tests above then the link is up and we no
3880          * longer need to check for link
3881          */
3882         mac->get_link_status = false;
3883
3884 out:
3885         *link_up = !mac->get_link_status;
3886         return ret_val;
3887 }
3888
3889 /* return 0 means link status changed, -1 means not changed */
3890 static int
3891 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3892                             int wait_to_complete, int vf)
3893 {
3894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3895         struct rte_eth_link link;
3896         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3897         struct ixgbe_interrupt *intr =
3898                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3899         int link_up;
3900         int diag;
3901         u32 speed = 0;
3902         int wait = 1;
3903         bool autoneg = false;
3904
3905         memset(&link, 0, sizeof(link));
3906         link.link_status = ETH_LINK_DOWN;
3907         link.link_speed = ETH_SPEED_NUM_NONE;
3908         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3909         link.link_autoneg = ETH_LINK_AUTONEG;
3910
3911         hw->mac.get_link_status = true;
3912
3913         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3914                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3915                 speed = hw->phy.autoneg_advertised;
3916                 if (!speed)
3917                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3918                 ixgbe_setup_link(hw, speed, true);
3919         }
3920
3921         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3922         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3923                 wait = 0;
3924
3925         if (vf)
3926                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3927         else
3928                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3929
3930         if (diag != 0) {
3931                 link.link_speed = ETH_SPEED_NUM_100M;
3932                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3933                 return rte_eth_linkstatus_set(dev, &link);
3934         }
3935
3936         if (link_up == 0) {
3937                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3938                 return rte_eth_linkstatus_set(dev, &link);
3939         }
3940
3941         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3942         link.link_status = ETH_LINK_UP;
3943         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3944
3945         switch (link_speed) {
3946         default:
3947         case IXGBE_LINK_SPEED_UNKNOWN:
3948                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3949                 link.link_speed = ETH_SPEED_NUM_100M;
3950                 break;
3951
3952         case IXGBE_LINK_SPEED_100_FULL:
3953                 link.link_speed = ETH_SPEED_NUM_100M;
3954                 break;
3955
3956         case IXGBE_LINK_SPEED_1GB_FULL:
3957                 link.link_speed = ETH_SPEED_NUM_1G;
3958                 break;
3959
3960         case IXGBE_LINK_SPEED_2_5GB_FULL:
3961                 link.link_speed = ETH_SPEED_NUM_2_5G;
3962                 break;
3963
3964         case IXGBE_LINK_SPEED_5GB_FULL:
3965                 link.link_speed = ETH_SPEED_NUM_5G;
3966                 break;
3967
3968         case IXGBE_LINK_SPEED_10GB_FULL:
3969                 link.link_speed = ETH_SPEED_NUM_10G;
3970                 break;
3971         }
3972
3973         return rte_eth_linkstatus_set(dev, &link);
3974 }
3975
3976 static int
3977 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3978 {
3979         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3980 }
3981
3982 static int
3983 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3984 {
3985         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3986 }
3987
3988 static void
3989 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3990 {
3991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3992         uint32_t fctrl;
3993
3994         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3995         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3996         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3997 }
3998
3999 static void
4000 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4001 {
4002         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4003         uint32_t fctrl;
4004
4005         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4006         fctrl &= (~IXGBE_FCTRL_UPE);
4007         if (dev->data->all_multicast == 1)
4008                 fctrl |= IXGBE_FCTRL_MPE;
4009         else
4010                 fctrl &= (~IXGBE_FCTRL_MPE);
4011         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4012 }
4013
4014 static void
4015 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4016 {
4017         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4018         uint32_t fctrl;
4019
4020         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4021         fctrl |= IXGBE_FCTRL_MPE;
4022         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4023 }
4024
4025 static void
4026 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4027 {
4028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4029         uint32_t fctrl;
4030
4031         if (dev->data->promiscuous == 1)
4032                 return; /* must remain in all_multicast mode */
4033
4034         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4035         fctrl &= (~IXGBE_FCTRL_MPE);
4036         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4037 }
4038
4039 /**
4040  * It clears the interrupt causes and enables the interrupt.
4041  * It will be called once only during nic initialized.
4042  *
4043  * @param dev
4044  *  Pointer to struct rte_eth_dev.
4045  * @param on
4046  *  Enable or Disable.
4047  *
4048  * @return
4049  *  - On success, zero.
4050  *  - On failure, a negative value.
4051  */
4052 static int
4053 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4054 {
4055         struct ixgbe_interrupt *intr =
4056                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4057
4058         ixgbe_dev_link_status_print(dev);
4059         if (on)
4060                 intr->mask |= IXGBE_EICR_LSC;
4061         else
4062                 intr->mask &= ~IXGBE_EICR_LSC;
4063
4064         return 0;
4065 }
4066
4067 /**
4068  * It clears the interrupt causes and enables the interrupt.
4069  * It will be called once only during nic initialized.
4070  *
4071  * @param dev
4072  *  Pointer to struct rte_eth_dev.
4073  *
4074  * @return
4075  *  - On success, zero.
4076  *  - On failure, a negative value.
4077  */
4078 static int
4079 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4080 {
4081         struct ixgbe_interrupt *intr =
4082                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4083
4084         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4085
4086         return 0;
4087 }
4088
4089 /**
4090  * It clears the interrupt causes and enables the interrupt.
4091  * It will be called once only during nic initialized.
4092  *
4093  * @param dev
4094  *  Pointer to struct rte_eth_dev.
4095  *
4096  * @return
4097  *  - On success, zero.
4098  *  - On failure, a negative value.
4099  */
4100 static int
4101 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4102 {
4103         struct ixgbe_interrupt *intr =
4104                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4105
4106         intr->mask |= IXGBE_EICR_LINKSEC;
4107
4108         return 0;
4109 }
4110
4111 /*
4112  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4113  *
4114  * @param dev
4115  *  Pointer to struct rte_eth_dev.
4116  *
4117  * @return
4118  *  - On success, zero.
4119  *  - On failure, a negative value.
4120  */
4121 static int
4122 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4123 {
4124         uint32_t eicr;
4125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4126         struct ixgbe_interrupt *intr =
4127                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4128
4129         /* clear all cause mask */
4130         ixgbe_disable_intr(hw);
4131
4132         /* read-on-clear nic registers here */
4133         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4134         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4135
4136         intr->flags = 0;
4137
4138         /* set flag for async link update */
4139         if (eicr & IXGBE_EICR_LSC)
4140                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4141
4142         if (eicr & IXGBE_EICR_MAILBOX)
4143                 intr->flags |= IXGBE_FLAG_MAILBOX;
4144
4145         if (eicr & IXGBE_EICR_LINKSEC)
4146                 intr->flags |= IXGBE_FLAG_MACSEC;
4147
4148         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4149             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4150             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4151                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4152
4153         return 0;
4154 }
4155
4156 /**
4157  * It gets and then prints the link status.
4158  *
4159  * @param dev
4160  *  Pointer to struct rte_eth_dev.
4161  *
4162  * @return
4163  *  - On success, zero.
4164  *  - On failure, a negative value.
4165  */
4166 static void
4167 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4168 {
4169         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4170         struct rte_eth_link link;
4171
4172         rte_eth_linkstatus_get(dev, &link);
4173
4174         if (link.link_status) {
4175                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4176                                         (int)(dev->data->port_id),
4177                                         (unsigned)link.link_speed,
4178                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4179                                         "full-duplex" : "half-duplex");
4180         } else {
4181                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4182                                 (int)(dev->data->port_id));
4183         }
4184         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4185                                 pci_dev->addr.domain,
4186                                 pci_dev->addr.bus,
4187                                 pci_dev->addr.devid,
4188                                 pci_dev->addr.function);
4189 }
4190
4191 /*
4192  * It executes link_update after knowing an interrupt occurred.
4193  *
4194  * @param dev
4195  *  Pointer to struct rte_eth_dev.
4196  *
4197  * @return
4198  *  - On success, zero.
4199  *  - On failure, a negative value.
4200  */
4201 static int
4202 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4203                            struct rte_intr_handle *intr_handle)
4204 {
4205         struct ixgbe_interrupt *intr =
4206                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4207         int64_t timeout;
4208         struct ixgbe_hw *hw =
4209                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4210
4211         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4212
4213         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4214                 ixgbe_pf_mbx_process(dev);
4215                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4216         }
4217
4218         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4219                 ixgbe_handle_lasi(hw);
4220                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4221         }
4222
4223         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4224                 struct rte_eth_link link;
4225
4226                 /* get the link status before link update, for predicting later */
4227                 rte_eth_linkstatus_get(dev, &link);
4228
4229                 ixgbe_dev_link_update(dev, 0);
4230
4231                 /* likely to up */
4232                 if (!link.link_status)
4233                         /* handle it 1 sec later, wait it being stable */
4234                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4235                 /* likely to down */
4236                 else
4237                         /* handle it 4 sec later, wait it being stable */
4238                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4239
4240                 ixgbe_dev_link_status_print(dev);
4241                 if (rte_eal_alarm_set(timeout * 1000,
4242                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4243                         PMD_DRV_LOG(ERR, "Error setting alarm");
4244                 else {
4245                         /* remember original mask */
4246                         intr->mask_original = intr->mask;
4247                         /* only disable lsc interrupt */
4248                         intr->mask &= ~IXGBE_EIMS_LSC;
4249                 }
4250         }
4251
4252         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4253         ixgbe_enable_intr(dev);
4254         rte_intr_enable(intr_handle);
4255
4256         return 0;
4257 }
4258
4259 /**
4260  * Interrupt handler which shall be registered for alarm callback for delayed
4261  * handling specific interrupt to wait for the stable nic state. As the
4262  * NIC interrupt state is not stable for ixgbe after link is just down,
4263  * it needs to wait 4 seconds to get the stable status.
4264  *
4265  * @param handle
4266  *  Pointer to interrupt handle.
4267  * @param param
4268  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4269  *
4270  * @return
4271  *  void
4272  */
4273 static void
4274 ixgbe_dev_interrupt_delayed_handler(void *param)
4275 {
4276         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4277         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4278         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4279         struct ixgbe_interrupt *intr =
4280                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4281         struct ixgbe_hw *hw =
4282                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4283         uint32_t eicr;
4284
4285         ixgbe_disable_intr(hw);
4286
4287         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4288         if (eicr & IXGBE_EICR_MAILBOX)
4289                 ixgbe_pf_mbx_process(dev);
4290
4291         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4292                 ixgbe_handle_lasi(hw);
4293                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4294         }
4295
4296         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4297                 ixgbe_dev_link_update(dev, 0);
4298                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4299                 ixgbe_dev_link_status_print(dev);
4300                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4301                                               NULL);
4302         }
4303
4304         if (intr->flags & IXGBE_FLAG_MACSEC) {
4305                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4306                                               NULL);
4307                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4308         }
4309
4310         /* restore original mask */
4311         intr->mask = intr->mask_original;
4312         intr->mask_original = 0;
4313
4314         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4315         ixgbe_enable_intr(dev);
4316         rte_intr_enable(intr_handle);
4317 }
4318
4319 /**
4320  * Interrupt handler triggered by NIC  for handling
4321  * specific interrupt.
4322  *
4323  * @param handle
4324  *  Pointer to interrupt handle.
4325  * @param param
4326  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4327  *
4328  * @return
4329  *  void
4330  */
4331 static void
4332 ixgbe_dev_interrupt_handler(void *param)
4333 {
4334         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4335
4336         ixgbe_dev_interrupt_get_status(dev);
4337         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4338 }
4339
4340 static int
4341 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4342 {
4343         struct ixgbe_hw *hw;
4344
4345         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4346         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4347 }
4348
4349 static int
4350 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4351 {
4352         struct ixgbe_hw *hw;
4353
4354         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4355         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4356 }
4357
4358 static int
4359 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4360 {
4361         struct ixgbe_hw *hw;
4362         uint32_t mflcn_reg;
4363         uint32_t fccfg_reg;
4364         int rx_pause;
4365         int tx_pause;
4366
4367         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4368
4369         fc_conf->pause_time = hw->fc.pause_time;
4370         fc_conf->high_water = hw->fc.high_water[0];
4371         fc_conf->low_water = hw->fc.low_water[0];
4372         fc_conf->send_xon = hw->fc.send_xon;
4373         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4374
4375         /*
4376          * Return rx_pause status according to actual setting of
4377          * MFLCN register.
4378          */
4379         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4380         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4381                 rx_pause = 1;
4382         else
4383                 rx_pause = 0;
4384
4385         /*
4386          * Return tx_pause status according to actual setting of
4387          * FCCFG register.
4388          */
4389         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4390         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4391                 tx_pause = 1;
4392         else
4393                 tx_pause = 0;
4394
4395         if (rx_pause && tx_pause)
4396                 fc_conf->mode = RTE_FC_FULL;
4397         else if (rx_pause)
4398                 fc_conf->mode = RTE_FC_RX_PAUSE;
4399         else if (tx_pause)
4400                 fc_conf->mode = RTE_FC_TX_PAUSE;
4401         else
4402                 fc_conf->mode = RTE_FC_NONE;
4403
4404         return 0;
4405 }
4406
4407 static int
4408 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4409 {
4410         struct ixgbe_hw *hw;
4411         int err;
4412         uint32_t rx_buf_size;
4413         uint32_t max_high_water;
4414         uint32_t mflcn;
4415         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4416                 ixgbe_fc_none,
4417                 ixgbe_fc_rx_pause,
4418                 ixgbe_fc_tx_pause,
4419                 ixgbe_fc_full
4420         };
4421
4422         PMD_INIT_FUNC_TRACE();
4423
4424         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4425         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4426         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4427
4428         /*
4429          * At least reserve one Ethernet frame for watermark
4430          * high_water/low_water in kilo bytes for ixgbe
4431          */
4432         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4433         if ((fc_conf->high_water > max_high_water) ||
4434                 (fc_conf->high_water < fc_conf->low_water)) {
4435                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4436                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4437                 return -EINVAL;
4438         }
4439
4440         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4441         hw->fc.pause_time     = fc_conf->pause_time;
4442         hw->fc.high_water[0]  = fc_conf->high_water;
4443         hw->fc.low_water[0]   = fc_conf->low_water;
4444         hw->fc.send_xon       = fc_conf->send_xon;
4445         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4446
4447         err = ixgbe_fc_enable(hw);
4448
4449         /* Not negotiated is not an error case */
4450         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4451
4452                 /* check if we want to forward MAC frames - driver doesn't have native
4453                  * capability to do that, so we'll write the registers ourselves */
4454
4455                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4456
4457                 /* set or clear MFLCN.PMCF bit depending on configuration */
4458                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4459                         mflcn |= IXGBE_MFLCN_PMCF;
4460                 else
4461                         mflcn &= ~IXGBE_MFLCN_PMCF;
4462
4463                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4464                 IXGBE_WRITE_FLUSH(hw);
4465
4466                 return 0;
4467         }
4468
4469         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4470         return -EIO;
4471 }
4472
4473 /**
4474  *  ixgbe_pfc_enable_generic - Enable flow control
4475  *  @hw: pointer to hardware structure
4476  *  @tc_num: traffic class number
4477  *  Enable flow control according to the current settings.
4478  */
4479 static int
4480 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4481 {
4482         int ret_val = 0;
4483         uint32_t mflcn_reg, fccfg_reg;
4484         uint32_t reg;
4485         uint32_t fcrtl, fcrth;
4486         uint8_t i;
4487         uint8_t nb_rx_en;
4488
4489         /* Validate the water mark configuration */
4490         if (!hw->fc.pause_time) {
4491                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4492                 goto out;
4493         }
4494
4495         /* Low water mark of zero causes XOFF floods */
4496         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4497                  /* High/Low water can not be 0 */
4498                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4499                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4500                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4501                         goto out;
4502                 }
4503
4504                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4505                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4506                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4507                         goto out;
4508                 }
4509         }
4510         /* Negotiate the fc mode to use */
4511         ixgbe_fc_autoneg(hw);
4512
4513         /* Disable any previous flow control settings */
4514         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4515         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4516
4517         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4518         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4519
4520         switch (hw->fc.current_mode) {
4521         case ixgbe_fc_none:
4522                 /*
4523                  * If the count of enabled RX Priority Flow control >1,
4524                  * and the TX pause can not be disabled
4525                  */
4526                 nb_rx_en = 0;
4527                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4528                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4529                         if (reg & IXGBE_FCRTH_FCEN)
4530                                 nb_rx_en++;
4531                 }
4532                 if (nb_rx_en > 1)
4533                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4534                 break;
4535         case ixgbe_fc_rx_pause:
4536                 /*
4537                  * Rx Flow control is enabled and Tx Flow control is
4538                  * disabled by software override. Since there really
4539                  * isn't a way to advertise that we are capable of RX
4540                  * Pause ONLY, we will advertise that we support both
4541                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4542                  * disable the adapter's ability to send PAUSE frames.
4543                  */
4544                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4545                 /*
4546                  * If the count of enabled RX Priority Flow control >1,
4547                  * and the TX pause can not be disabled
4548                  */
4549                 nb_rx_en = 0;
4550                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4551                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4552                         if (reg & IXGBE_FCRTH_FCEN)
4553                                 nb_rx_en++;
4554                 }
4555                 if (nb_rx_en > 1)
4556                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4557                 break;
4558         case ixgbe_fc_tx_pause:
4559                 /*
4560                  * Tx Flow control is enabled, and Rx Flow control is
4561                  * disabled by software override.
4562                  */
4563                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4564                 break;
4565         case ixgbe_fc_full:
4566                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4567                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4568                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4569                 break;
4570         default:
4571                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4572                 ret_val = IXGBE_ERR_CONFIG;
4573                 goto out;
4574         }
4575
4576         /* Set 802.3x based flow control settings. */
4577         mflcn_reg |= IXGBE_MFLCN_DPF;
4578         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4579         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4580
4581         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4582         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4583                 hw->fc.high_water[tc_num]) {
4584                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4585                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4586                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4587         } else {
4588                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4589                 /*
4590                  * In order to prevent Tx hangs when the internal Tx
4591                  * switch is enabled we must set the high water mark
4592                  * to the maximum FCRTH value.  This allows the Tx
4593                  * switch to function even under heavy Rx workloads.
4594                  */
4595                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4596         }
4597         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4598
4599         /* Configure pause time (2 TCs per register) */
4600         reg = hw->fc.pause_time * 0x00010001;
4601         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4602                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4603
4604         /* Configure flow control refresh threshold value */
4605         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4606
4607 out:
4608         return ret_val;
4609 }
4610
4611 static int
4612 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4613 {
4614         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4615         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4616
4617         if (hw->mac.type != ixgbe_mac_82598EB) {
4618                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4619         }
4620         return ret_val;
4621 }
4622
4623 static int
4624 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4625 {
4626         int err;
4627         uint32_t rx_buf_size;
4628         uint32_t max_high_water;
4629         uint8_t tc_num;
4630         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4631         struct ixgbe_hw *hw =
4632                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4633         struct ixgbe_dcb_config *dcb_config =
4634                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4635
4636         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4637                 ixgbe_fc_none,
4638                 ixgbe_fc_rx_pause,
4639                 ixgbe_fc_tx_pause,
4640                 ixgbe_fc_full
4641         };
4642
4643         PMD_INIT_FUNC_TRACE();
4644
4645         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4646         tc_num = map[pfc_conf->priority];
4647         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4648         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4649         /*
4650          * At least reserve one Ethernet frame for watermark
4651          * high_water/low_water in kilo bytes for ixgbe
4652          */
4653         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4654         if ((pfc_conf->fc.high_water > max_high_water) ||
4655             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4656                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4657                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4658                 return -EINVAL;
4659         }
4660
4661         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4662         hw->fc.pause_time = pfc_conf->fc.pause_time;
4663         hw->fc.send_xon = pfc_conf->fc.send_xon;
4664         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4665         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4666
4667         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4668
4669         /* Not negotiated is not an error case */
4670         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4671                 return 0;
4672
4673         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4674         return -EIO;
4675 }
4676
4677 static int
4678 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4679                           struct rte_eth_rss_reta_entry64 *reta_conf,
4680                           uint16_t reta_size)
4681 {
4682         uint16_t i, sp_reta_size;
4683         uint8_t j, mask;
4684         uint32_t reta, r;
4685         uint16_t idx, shift;
4686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4687         uint32_t reta_reg;
4688
4689         PMD_INIT_FUNC_TRACE();
4690
4691         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4692                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4693                         "NIC.");
4694                 return -ENOTSUP;
4695         }
4696
4697         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4698         if (reta_size != sp_reta_size) {
4699                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4700                         "(%d) doesn't match the number hardware can supported "
4701                         "(%d)", reta_size, sp_reta_size);
4702                 return -EINVAL;
4703         }
4704
4705         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4706                 idx = i / RTE_RETA_GROUP_SIZE;
4707                 shift = i % RTE_RETA_GROUP_SIZE;
4708                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4709                                                 IXGBE_4_BIT_MASK);
4710                 if (!mask)
4711                         continue;
4712                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4713                 if (mask == IXGBE_4_BIT_MASK)
4714                         r = 0;
4715                 else
4716                         r = IXGBE_READ_REG(hw, reta_reg);
4717                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4718                         if (mask & (0x1 << j))
4719                                 reta |= reta_conf[idx].reta[shift + j] <<
4720                                                         (CHAR_BIT * j);
4721                         else
4722                                 reta |= r & (IXGBE_8_BIT_MASK <<
4723                                                 (CHAR_BIT * j));
4724                 }
4725                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4726         }
4727
4728         return 0;
4729 }
4730
4731 static int
4732 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4733                          struct rte_eth_rss_reta_entry64 *reta_conf,
4734                          uint16_t reta_size)
4735 {
4736         uint16_t i, sp_reta_size;
4737         uint8_t j, mask;
4738         uint32_t reta;
4739         uint16_t idx, shift;
4740         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4741         uint32_t reta_reg;
4742
4743         PMD_INIT_FUNC_TRACE();
4744         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4745         if (reta_size != sp_reta_size) {
4746                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4747                         "(%d) doesn't match the number hardware can supported "
4748                         "(%d)", reta_size, sp_reta_size);
4749                 return -EINVAL;
4750         }
4751
4752         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4753                 idx = i / RTE_RETA_GROUP_SIZE;
4754                 shift = i % RTE_RETA_GROUP_SIZE;
4755                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4756                                                 IXGBE_4_BIT_MASK);
4757                 if (!mask)
4758                         continue;
4759
4760                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4761                 reta = IXGBE_READ_REG(hw, reta_reg);
4762                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4763                         if (mask & (0x1 << j))
4764                                 reta_conf[idx].reta[shift + j] =
4765                                         ((reta >> (CHAR_BIT * j)) &
4766                                                 IXGBE_8_BIT_MASK);
4767                 }
4768         }
4769
4770         return 0;
4771 }
4772
4773 static int
4774 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4775                                 uint32_t index, uint32_t pool)
4776 {
4777         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4778         uint32_t enable_addr = 1;
4779
4780         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4781                              pool, enable_addr);
4782 }
4783
4784 static void
4785 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4786 {
4787         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4788
4789         ixgbe_clear_rar(hw, index);
4790 }
4791
4792 static int
4793 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4794 {
4795         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4796
4797         ixgbe_remove_rar(dev, 0);
4798         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4799
4800         return 0;
4801 }
4802
4803 static bool
4804 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4805 {
4806         if (strcmp(dev->device->driver->name, drv->driver.name))
4807                 return false;
4808
4809         return true;
4810 }
4811
4812 bool
4813 is_ixgbe_supported(struct rte_eth_dev *dev)
4814 {
4815         return is_device_supported(dev, &rte_ixgbe_pmd);
4816 }
4817
4818 static int
4819 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4820 {
4821         uint32_t hlreg0;
4822         uint32_t maxfrs;
4823         struct ixgbe_hw *hw;
4824         struct rte_eth_dev_info dev_info;
4825         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4826         struct rte_eth_dev_data *dev_data = dev->data;
4827
4828         ixgbe_dev_info_get(dev, &dev_info);
4829
4830         /* check that mtu is within the allowed range */
4831         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4832                 return -EINVAL;
4833
4834         /* If device is started, refuse mtu that requires the support of
4835          * scattered packets when this feature has not been enabled before.
4836          */
4837         if (dev_data->dev_started && !dev_data->scattered_rx &&
4838             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4839              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4840                 PMD_INIT_LOG(ERR, "Stop port first.");
4841                 return -EINVAL;
4842         }
4843
4844         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4846
4847         /* switch to jumbo mode if needed */
4848         if (frame_size > ETHER_MAX_LEN) {
4849                 dev->data->dev_conf.rxmode.offloads |=
4850                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4851                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4852         } else {
4853                 dev->data->dev_conf.rxmode.offloads &=
4854                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4855                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4856         }
4857         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4858
4859         /* update max frame size */
4860         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4861
4862         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4863         maxfrs &= 0x0000FFFF;
4864         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4865         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4866
4867         return 0;
4868 }
4869
4870 /*
4871  * Virtual Function operations
4872  */
4873 static void
4874 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4875 {
4876         PMD_INIT_FUNC_TRACE();
4877
4878         /* Clear interrupt mask to stop from interrupts being generated */
4879         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4880
4881         IXGBE_WRITE_FLUSH(hw);
4882 }
4883
4884 static void
4885 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4886 {
4887         PMD_INIT_FUNC_TRACE();
4888
4889         /* VF enable interrupt autoclean */
4890         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4891         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4892         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4893
4894         IXGBE_WRITE_FLUSH(hw);
4895 }
4896
4897 static int
4898 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4899 {
4900         struct rte_eth_conf *conf = &dev->data->dev_conf;
4901         struct ixgbe_adapter *adapter =
4902                         (struct ixgbe_adapter *)dev->data->dev_private;
4903         struct rte_eth_dev_info dev_info;
4904         uint64_t rx_offloads;
4905         uint64_t tx_offloads;
4906
4907         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4908                      dev->data->port_id);
4909
4910         ixgbevf_dev_info_get(dev, &dev_info);
4911         rx_offloads = dev->data->dev_conf.rxmode.offloads;
4912         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4913                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4914                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4915                             rx_offloads, dev_info.rx_offload_capa);
4916                 return -ENOTSUP;
4917         }
4918         tx_offloads = dev->data->dev_conf.txmode.offloads;
4919         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4920                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4921                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4922                             tx_offloads, dev_info.tx_offload_capa);
4923                 return -ENOTSUP;
4924         }
4925
4926         /*
4927          * VF has no ability to enable/disable HW CRC
4928          * Keep the persistent behavior the same as Host PF
4929          */
4930 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4931         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4932                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4933                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4934         }
4935 #else
4936         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4937                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4938                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
4939         }
4940 #endif
4941
4942         /*
4943          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4944          * allocation or vector Rx preconditions we will reset it.
4945          */
4946         adapter->rx_bulk_alloc_allowed = true;
4947         adapter->rx_vec_allowed = true;
4948
4949         return 0;
4950 }
4951
4952 static int
4953 ixgbevf_dev_start(struct rte_eth_dev *dev)
4954 {
4955         struct ixgbe_hw *hw =
4956                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4957         uint32_t intr_vector = 0;
4958         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4959         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4960
4961         int err, mask = 0;
4962
4963         PMD_INIT_FUNC_TRACE();
4964
4965         err = hw->mac.ops.reset_hw(hw);
4966         if (err) {
4967                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4968                 return err;
4969         }
4970         hw->mac.get_link_status = true;
4971
4972         /* negotiate mailbox API version to use with the PF. */
4973         ixgbevf_negotiate_api(hw);
4974
4975         ixgbevf_dev_tx_init(dev);
4976
4977         /* This can fail when allocating mbufs for descriptor rings */
4978         err = ixgbevf_dev_rx_init(dev);
4979         if (err) {
4980                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4981                 ixgbe_dev_clear_queues(dev);
4982                 return err;
4983         }
4984
4985         /* Set vfta */
4986         ixgbevf_set_vfta_all(dev, 1);
4987
4988         /* Set HW strip */
4989         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4990                 ETH_VLAN_EXTEND_MASK;
4991         err = ixgbevf_vlan_offload_set(dev, mask);
4992         if (err) {
4993                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4994                 ixgbe_dev_clear_queues(dev);
4995                 return err;
4996         }
4997
4998         ixgbevf_dev_rxtx_start(dev);
4999
5000         ixgbevf_dev_link_update(dev, 0);
5001
5002         /* check and configure queue intr-vector mapping */
5003         if (rte_intr_cap_multiple(intr_handle) &&
5004             dev->data->dev_conf.intr_conf.rxq) {
5005                 /* According to datasheet, only vector 0/1/2 can be used,
5006                  * now only one vector is used for Rx queue
5007                  */
5008                 intr_vector = 1;
5009                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5010                         return -1;
5011         }
5012
5013         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5014                 intr_handle->intr_vec =
5015                         rte_zmalloc("intr_vec",
5016                                     dev->data->nb_rx_queues * sizeof(int), 0);
5017                 if (intr_handle->intr_vec == NULL) {
5018                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5019                                      " intr_vec", dev->data->nb_rx_queues);
5020                         return -ENOMEM;
5021                 }
5022         }
5023         ixgbevf_configure_msix(dev);
5024
5025         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5026          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5027          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5028          * is not cleared, it will fail when following rte_intr_enable( ) tries
5029          * to map Rx queue interrupt to other VFIO vectors.
5030          * So clear uio/vfio intr/evevnfd first to avoid failure.
5031          */
5032         rte_intr_disable(intr_handle);
5033
5034         rte_intr_enable(intr_handle);
5035
5036         /* Re-enable interrupt for VF */
5037         ixgbevf_intr_enable(hw);
5038
5039         return 0;
5040 }
5041
5042 static void
5043 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5044 {
5045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5046         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5047         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5048
5049         PMD_INIT_FUNC_TRACE();
5050
5051         ixgbevf_intr_disable(hw);
5052
5053         hw->adapter_stopped = 1;
5054         ixgbe_stop_adapter(hw);
5055
5056         /*
5057           * Clear what we set, but we still keep shadow_vfta to
5058           * restore after device starts
5059           */
5060         ixgbevf_set_vfta_all(dev, 0);
5061
5062         /* Clear stored conf */
5063         dev->data->scattered_rx = 0;
5064
5065         ixgbe_dev_clear_queues(dev);
5066
5067         /* Clean datapath event and queue/vec mapping */
5068         rte_intr_efd_disable(intr_handle);
5069         if (intr_handle->intr_vec != NULL) {
5070                 rte_free(intr_handle->intr_vec);
5071                 intr_handle->intr_vec = NULL;
5072         }
5073 }
5074
5075 static void
5076 ixgbevf_dev_close(struct rte_eth_dev *dev)
5077 {
5078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5079
5080         PMD_INIT_FUNC_TRACE();
5081
5082         ixgbe_reset_hw(hw);
5083
5084         ixgbevf_dev_stop(dev);
5085
5086         ixgbe_dev_free_queues(dev);
5087
5088         /**
5089          * Remove the VF MAC address ro ensure
5090          * that the VF traffic goes to the PF
5091          * after stop, close and detach of the VF
5092          **/
5093         ixgbevf_remove_mac_addr(dev, 0);
5094 }
5095
5096 /*
5097  * Reset VF device
5098  */
5099 static int
5100 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5101 {
5102         int ret;
5103
5104         ret = eth_ixgbevf_dev_uninit(dev);
5105         if (ret)
5106                 return ret;
5107
5108         ret = eth_ixgbevf_dev_init(dev);
5109
5110         return ret;
5111 }
5112
5113 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5114 {
5115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5116         struct ixgbe_vfta *shadow_vfta =
5117                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5118         int i = 0, j = 0, vfta = 0, mask = 1;
5119
5120         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5121                 vfta = shadow_vfta->vfta[i];
5122                 if (vfta) {
5123                         mask = 1;
5124                         for (j = 0; j < 32; j++) {
5125                                 if (vfta & mask)
5126                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5127                                                        on, false);
5128                                 mask <<= 1;
5129                         }
5130                 }
5131         }
5132
5133 }
5134
5135 static int
5136 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5137 {
5138         struct ixgbe_hw *hw =
5139                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140         struct ixgbe_vfta *shadow_vfta =
5141                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5142         uint32_t vid_idx = 0;
5143         uint32_t vid_bit = 0;
5144         int ret = 0;
5145
5146         PMD_INIT_FUNC_TRACE();
5147
5148         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5149         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5150         if (ret) {
5151                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5152                 return ret;
5153         }
5154         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5155         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5156
5157         /* Save what we set and retore it after device reset */
5158         if (on)
5159                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5160         else
5161                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5162
5163         return 0;
5164 }
5165
5166 static void
5167 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5168 {
5169         struct ixgbe_hw *hw =
5170                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5171         uint32_t ctrl;
5172
5173         PMD_INIT_FUNC_TRACE();
5174
5175         if (queue >= hw->mac.max_rx_queues)
5176                 return;
5177
5178         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5179         if (on)
5180                 ctrl |= IXGBE_RXDCTL_VME;
5181         else
5182                 ctrl &= ~IXGBE_RXDCTL_VME;
5183         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5184
5185         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5186 }
5187
5188 static int
5189 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5190 {
5191         struct ixgbe_rx_queue *rxq;
5192         uint16_t i;
5193         int on = 0;
5194
5195         /* VF function only support hw strip feature, others are not support */
5196         if (mask & ETH_VLAN_STRIP_MASK) {
5197                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5198                         rxq = dev->data->rx_queues[i];
5199                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5200                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5201                 }
5202         }
5203
5204         return 0;
5205 }
5206
5207 int
5208 ixgbe_vt_check(struct ixgbe_hw *hw)
5209 {
5210         uint32_t reg_val;
5211
5212         /* if Virtualization Technology is enabled */
5213         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5214         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5215                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5216                 return -1;
5217         }
5218
5219         return 0;
5220 }
5221
5222 static uint32_t
5223 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5224 {
5225         uint32_t vector = 0;
5226
5227         switch (hw->mac.mc_filter_type) {
5228         case 0:   /* use bits [47:36] of the address */
5229                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5230                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5231                 break;
5232         case 1:   /* use bits [46:35] of the address */
5233                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5234                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5235                 break;
5236         case 2:   /* use bits [45:34] of the address */
5237                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5238                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5239                 break;
5240         case 3:   /* use bits [43:32] of the address */
5241                 vector = ((uc_addr->addr_bytes[4]) |
5242                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5243                 break;
5244         default:  /* Invalid mc_filter_type */
5245                 break;
5246         }
5247
5248         /* vector can only be 12-bits or boundary will be exceeded */
5249         vector &= 0xFFF;
5250         return vector;
5251 }
5252
5253 static int
5254 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5255                         uint8_t on)
5256 {
5257         uint32_t vector;
5258         uint32_t uta_idx;
5259         uint32_t reg_val;
5260         uint32_t uta_shift;
5261         uint32_t rc;
5262         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5263         const uint32_t ixgbe_uta_bit_shift = 5;
5264         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5265         const uint32_t bit1 = 0x1;
5266
5267         struct ixgbe_hw *hw =
5268                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5269         struct ixgbe_uta_info *uta_info =
5270                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5271
5272         /* The UTA table only exists on 82599 hardware and newer */
5273         if (hw->mac.type < ixgbe_mac_82599EB)
5274                 return -ENOTSUP;
5275
5276         vector = ixgbe_uta_vector(hw, mac_addr);
5277         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5278         uta_shift = vector & ixgbe_uta_bit_mask;
5279
5280         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5281         if (rc == on)
5282                 return 0;
5283
5284         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5285         if (on) {
5286                 uta_info->uta_in_use++;
5287                 reg_val |= (bit1 << uta_shift);
5288                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5289         } else {
5290                 uta_info->uta_in_use--;
5291                 reg_val &= ~(bit1 << uta_shift);
5292                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5293         }
5294
5295         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5296
5297         if (uta_info->uta_in_use > 0)
5298                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5299                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5300         else
5301                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5302
5303         return 0;
5304 }
5305
5306 static int
5307 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5308 {
5309         int i;
5310         struct ixgbe_hw *hw =
5311                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5312         struct ixgbe_uta_info *uta_info =
5313                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5314
5315         /* The UTA table only exists on 82599 hardware and newer */
5316         if (hw->mac.type < ixgbe_mac_82599EB)
5317                 return -ENOTSUP;
5318
5319         if (on) {
5320                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5321                         uta_info->uta_shadow[i] = ~0;
5322                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5323                 }
5324         } else {
5325                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5326                         uta_info->uta_shadow[i] = 0;
5327                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5328                 }
5329         }
5330         return 0;
5331
5332 }
5333
5334 uint32_t
5335 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5336 {
5337         uint32_t new_val = orig_val;
5338
5339         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5340                 new_val |= IXGBE_VMOLR_AUPE;
5341         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5342                 new_val |= IXGBE_VMOLR_ROMPE;
5343         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5344                 new_val |= IXGBE_VMOLR_ROPE;
5345         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5346                 new_val |= IXGBE_VMOLR_BAM;
5347         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5348                 new_val |= IXGBE_VMOLR_MPE;
5349
5350         return new_val;
5351 }
5352
5353 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5354 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5355 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5356 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5357 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5358         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5359         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5360
5361 static int
5362 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5363                       struct rte_eth_mirror_conf *mirror_conf,
5364                       uint8_t rule_id, uint8_t on)
5365 {
5366         uint32_t mr_ctl, vlvf;
5367         uint32_t mp_lsb = 0;
5368         uint32_t mv_msb = 0;
5369         uint32_t mv_lsb = 0;
5370         uint32_t mp_msb = 0;
5371         uint8_t i = 0;
5372         int reg_index = 0;
5373         uint64_t vlan_mask = 0;
5374
5375         const uint8_t pool_mask_offset = 32;
5376         const uint8_t vlan_mask_offset = 32;
5377         const uint8_t dst_pool_offset = 8;
5378         const uint8_t rule_mr_offset  = 4;
5379         const uint8_t mirror_rule_mask = 0x0F;
5380
5381         struct ixgbe_mirror_info *mr_info =
5382                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5383         struct ixgbe_hw *hw =
5384                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5385         uint8_t mirror_type = 0;
5386
5387         if (ixgbe_vt_check(hw) < 0)
5388                 return -ENOTSUP;
5389
5390         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5391                 return -EINVAL;
5392
5393         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5394                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5395                             mirror_conf->rule_type);
5396                 return -EINVAL;
5397         }
5398
5399         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5400                 mirror_type |= IXGBE_MRCTL_VLME;
5401                 /* Check if vlan id is valid and find conresponding VLAN ID
5402                  * index in VLVF
5403                  */
5404                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5405                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5406                                 /* search vlan id related pool vlan filter
5407                                  * index
5408                                  */
5409                                 reg_index = ixgbe_find_vlvf_slot(
5410                                                 hw,
5411                                                 mirror_conf->vlan.vlan_id[i],
5412                                                 false);
5413                                 if (reg_index < 0)
5414                                         return -EINVAL;
5415                                 vlvf = IXGBE_READ_REG(hw,
5416                                                       IXGBE_VLVF(reg_index));
5417                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5418                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5419                                       mirror_conf->vlan.vlan_id[i]))
5420                                         vlan_mask |= (1ULL << reg_index);
5421                                 else
5422                                         return -EINVAL;
5423                         }
5424                 }
5425
5426                 if (on) {
5427                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5428                         mv_msb = vlan_mask >> vlan_mask_offset;
5429
5430                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5431                                                 mirror_conf->vlan.vlan_mask;
5432                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5433                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5434                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5435                                                 mirror_conf->vlan.vlan_id[i];
5436                         }
5437                 } else {
5438                         mv_lsb = 0;
5439                         mv_msb = 0;
5440                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5441                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5442                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5443                 }
5444         }
5445
5446         /**
5447          * if enable pool mirror, write related pool mask register,if disable
5448          * pool mirror, clear PFMRVM register
5449          */
5450         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5451                 mirror_type |= IXGBE_MRCTL_VPME;
5452                 if (on) {
5453                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5454                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5455                         mr_info->mr_conf[rule_id].pool_mask =
5456                                         mirror_conf->pool_mask;
5457
5458                 } else {
5459                         mp_lsb = 0;
5460                         mp_msb = 0;
5461                         mr_info->mr_conf[rule_id].pool_mask = 0;
5462                 }
5463         }
5464         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5465                 mirror_type |= IXGBE_MRCTL_UPME;
5466         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5467                 mirror_type |= IXGBE_MRCTL_DPME;
5468
5469         /* read  mirror control register and recalculate it */
5470         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5471
5472         if (on) {
5473                 mr_ctl |= mirror_type;
5474                 mr_ctl &= mirror_rule_mask;
5475                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5476         } else {
5477                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5478         }
5479
5480         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5481         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5482
5483         /* write mirrror control  register */
5484         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5485
5486         /* write pool mirrror control  register */
5487         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5488                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5489                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5490                                 mp_msb);
5491         }
5492         /* write VLAN mirrror control  register */
5493         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5494                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5495                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5496                                 mv_msb);
5497         }
5498
5499         return 0;
5500 }
5501
5502 static int
5503 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5504 {
5505         int mr_ctl = 0;
5506         uint32_t lsb_val = 0;
5507         uint32_t msb_val = 0;
5508         const uint8_t rule_mr_offset = 4;
5509
5510         struct ixgbe_hw *hw =
5511                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5512         struct ixgbe_mirror_info *mr_info =
5513                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5514
5515         if (ixgbe_vt_check(hw) < 0)
5516                 return -ENOTSUP;
5517
5518         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5519                 return -EINVAL;
5520
5521         memset(&mr_info->mr_conf[rule_id], 0,
5522                sizeof(struct rte_eth_mirror_conf));
5523
5524         /* clear PFVMCTL register */
5525         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5526
5527         /* clear pool mask register */
5528         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5529         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5530
5531         /* clear vlan mask register */
5532         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5533         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5534
5535         return 0;
5536 }
5537
5538 static int
5539 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5540 {
5541         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5543         uint32_t mask;
5544         struct ixgbe_hw *hw =
5545                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5546         uint32_t vec = IXGBE_MISC_VEC_ID;
5547
5548         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5549         if (rte_intr_allow_others(intr_handle))
5550                 vec = IXGBE_RX_VEC_START;
5551         mask |= (1 << vec);
5552         RTE_SET_USED(queue_id);
5553         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5554
5555         rte_intr_enable(intr_handle);
5556
5557         return 0;
5558 }
5559
5560 static int
5561 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5562 {
5563         uint32_t mask;
5564         struct ixgbe_hw *hw =
5565                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5566         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5567         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5568         uint32_t vec = IXGBE_MISC_VEC_ID;
5569
5570         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5571         if (rte_intr_allow_others(intr_handle))
5572                 vec = IXGBE_RX_VEC_START;
5573         mask &= ~(1 << vec);
5574         RTE_SET_USED(queue_id);
5575         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5576
5577         return 0;
5578 }
5579
5580 static int
5581 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5582 {
5583         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5584         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5585         uint32_t mask;
5586         struct ixgbe_hw *hw =
5587                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5588         struct ixgbe_interrupt *intr =
5589                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5590
5591         if (queue_id < 16) {
5592                 ixgbe_disable_intr(hw);
5593                 intr->mask |= (1 << queue_id);
5594                 ixgbe_enable_intr(dev);
5595         } else if (queue_id < 32) {
5596                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5597                 mask &= (1 << queue_id);
5598                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5599         } else if (queue_id < 64) {
5600                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5601                 mask &= (1 << (queue_id - 32));
5602                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5603         }
5604         rte_intr_enable(intr_handle);
5605
5606         return 0;
5607 }
5608
5609 static int
5610 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5611 {
5612         uint32_t mask;
5613         struct ixgbe_hw *hw =
5614                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5615         struct ixgbe_interrupt *intr =
5616                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5617
5618         if (queue_id < 16) {
5619                 ixgbe_disable_intr(hw);
5620                 intr->mask &= ~(1 << queue_id);
5621                 ixgbe_enable_intr(dev);
5622         } else if (queue_id < 32) {
5623                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5624                 mask &= ~(1 << queue_id);
5625                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5626         } else if (queue_id < 64) {
5627                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5628                 mask &= ~(1 << (queue_id - 32));
5629                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5630         }
5631
5632         return 0;
5633 }
5634
5635 static void
5636 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5637                      uint8_t queue, uint8_t msix_vector)
5638 {
5639         uint32_t tmp, idx;
5640
5641         if (direction == -1) {
5642                 /* other causes */
5643                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5644                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5645                 tmp &= ~0xFF;
5646                 tmp |= msix_vector;
5647                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5648         } else {
5649                 /* rx or tx cause */
5650                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5651                 idx = ((16 * (queue & 1)) + (8 * direction));
5652                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5653                 tmp &= ~(0xFF << idx);
5654                 tmp |= (msix_vector << idx);
5655                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5656         }
5657 }
5658
5659 /**
5660  * set the IVAR registers, mapping interrupt causes to vectors
5661  * @param hw
5662  *  pointer to ixgbe_hw struct
5663  * @direction
5664  *  0 for Rx, 1 for Tx, -1 for other causes
5665  * @queue
5666  *  queue to map the corresponding interrupt to
5667  * @msix_vector
5668  *  the vector to map to the corresponding queue
5669  */
5670 static void
5671 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5672                    uint8_t queue, uint8_t msix_vector)
5673 {
5674         uint32_t tmp, idx;
5675
5676         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5677         if (hw->mac.type == ixgbe_mac_82598EB) {
5678                 if (direction == -1)
5679                         direction = 0;
5680                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5681                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5682                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5683                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5684                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5685         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5686                         (hw->mac.type == ixgbe_mac_X540) ||
5687                         (hw->mac.type == ixgbe_mac_X550)) {
5688                 if (direction == -1) {
5689                         /* other causes */
5690                         idx = ((queue & 1) * 8);
5691                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5692                         tmp &= ~(0xFF << idx);
5693                         tmp |= (msix_vector << idx);
5694                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5695                 } else {
5696                         /* rx or tx causes */
5697                         idx = ((16 * (queue & 1)) + (8 * direction));
5698                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5699                         tmp &= ~(0xFF << idx);
5700                         tmp |= (msix_vector << idx);
5701                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5702                 }
5703         }
5704 }
5705
5706 static void
5707 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5708 {
5709         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5710         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5711         struct ixgbe_hw *hw =
5712                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5713         uint32_t q_idx;
5714         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5715         uint32_t base = IXGBE_MISC_VEC_ID;
5716
5717         /* Configure VF other cause ivar */
5718         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5719
5720         /* won't configure msix register if no mapping is done
5721          * between intr vector and event fd.
5722          */
5723         if (!rte_intr_dp_is_en(intr_handle))
5724                 return;
5725
5726         if (rte_intr_allow_others(intr_handle)) {
5727                 base = IXGBE_RX_VEC_START;
5728                 vector_idx = IXGBE_RX_VEC_START;
5729         }
5730
5731         /* Configure all RX queues of VF */
5732         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5733                 /* Force all queue use vector 0,
5734                  * as IXGBE_VF_MAXMSIVECOTR = 1
5735                  */
5736                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5737                 intr_handle->intr_vec[q_idx] = vector_idx;
5738                 if (vector_idx < base + intr_handle->nb_efd - 1)
5739                         vector_idx++;
5740         }
5741 }
5742
5743 /**
5744  * Sets up the hardware to properly generate MSI-X interrupts
5745  * @hw
5746  *  board private structure
5747  */
5748 static void
5749 ixgbe_configure_msix(struct rte_eth_dev *dev)
5750 {
5751         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5752         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5753         struct ixgbe_hw *hw =
5754                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5755         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5756         uint32_t vec = IXGBE_MISC_VEC_ID;
5757         uint32_t mask;
5758         uint32_t gpie;
5759
5760         /* won't configure msix register if no mapping is done
5761          * between intr vector and event fd
5762          */
5763         if (!rte_intr_dp_is_en(intr_handle))
5764                 return;
5765
5766         if (rte_intr_allow_others(intr_handle))
5767                 vec = base = IXGBE_RX_VEC_START;
5768
5769         /* setup GPIE for MSI-x mode */
5770         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5771         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5772                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5773         /* auto clearing and auto setting corresponding bits in EIMS
5774          * when MSI-X interrupt is triggered
5775          */
5776         if (hw->mac.type == ixgbe_mac_82598EB) {
5777                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5778         } else {
5779                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5780                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5781         }
5782         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5783
5784         /* Populate the IVAR table and set the ITR values to the
5785          * corresponding register.
5786          */
5787         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5788              queue_id++) {
5789                 /* by default, 1:1 mapping */
5790                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5791                 intr_handle->intr_vec[queue_id] = vec;
5792                 if (vec < base + intr_handle->nb_efd - 1)
5793                         vec++;
5794         }
5795
5796         switch (hw->mac.type) {
5797         case ixgbe_mac_82598EB:
5798                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5799                                    IXGBE_MISC_VEC_ID);
5800                 break;
5801         case ixgbe_mac_82599EB:
5802         case ixgbe_mac_X540:
5803         case ixgbe_mac_X550:
5804                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5805                 break;
5806         default:
5807                 break;
5808         }
5809         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5810                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5811
5812         /* set up to autoclear timer, and the vectors */
5813         mask = IXGBE_EIMS_ENABLE_MASK;
5814         mask &= ~(IXGBE_EIMS_OTHER |
5815                   IXGBE_EIMS_MAILBOX |
5816                   IXGBE_EIMS_LSC);
5817
5818         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5819 }
5820
5821 int
5822 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5823                            uint16_t queue_idx, uint16_t tx_rate)
5824 {
5825         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5826         struct rte_eth_rxmode *rxmode;
5827         uint32_t rf_dec, rf_int;
5828         uint32_t bcnrc_val;
5829         uint16_t link_speed = dev->data->dev_link.link_speed;
5830
5831         if (queue_idx >= hw->mac.max_tx_queues)
5832                 return -EINVAL;
5833
5834         if (tx_rate != 0) {
5835                 /* Calculate the rate factor values to set */
5836                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5837                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5838                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5839
5840                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5841                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5842                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5843                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5844         } else {
5845                 bcnrc_val = 0;
5846         }
5847
5848         rxmode = &dev->data->dev_conf.rxmode;
5849         /*
5850          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5851          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5852          * set as 0x4.
5853          */
5854         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5855             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5856                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5857                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5858         else
5859                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5860                         IXGBE_MMW_SIZE_DEFAULT);
5861
5862         /* Set RTTBCNRC of queue X */
5863         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5864         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5865         IXGBE_WRITE_FLUSH(hw);
5866
5867         return 0;
5868 }
5869
5870 static int
5871 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5872                      __attribute__((unused)) uint32_t index,
5873                      __attribute__((unused)) uint32_t pool)
5874 {
5875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5876         int diag;
5877
5878         /*
5879          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5880          * operation. Trap this case to avoid exhausting the [very limited]
5881          * set of PF resources used to store VF MAC addresses.
5882          */
5883         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5884                 return -1;
5885         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5886         if (diag != 0)
5887                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5888                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5889                             mac_addr->addr_bytes[0],
5890                             mac_addr->addr_bytes[1],
5891                             mac_addr->addr_bytes[2],
5892                             mac_addr->addr_bytes[3],
5893                             mac_addr->addr_bytes[4],
5894                             mac_addr->addr_bytes[5],
5895                             diag);
5896         return diag;
5897 }
5898
5899 static void
5900 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5901 {
5902         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5903         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5904         struct ether_addr *mac_addr;
5905         uint32_t i;
5906         int diag;
5907
5908         /*
5909          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5910          * not support the deletion of a given MAC address.
5911          * Instead, it imposes to delete all MAC addresses, then to add again
5912          * all MAC addresses with the exception of the one to be deleted.
5913          */
5914         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5915
5916         /*
5917          * Add again all MAC addresses, with the exception of the deleted one
5918          * and of the permanent MAC address.
5919          */
5920         for (i = 0, mac_addr = dev->data->mac_addrs;
5921              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5922                 /* Skip the deleted MAC address */
5923                 if (i == index)
5924                         continue;
5925                 /* Skip NULL MAC addresses */
5926                 if (is_zero_ether_addr(mac_addr))
5927                         continue;
5928                 /* Skip the permanent MAC address */
5929                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5930                         continue;
5931                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5932                 if (diag != 0)
5933                         PMD_DRV_LOG(ERR,
5934                                     "Adding again MAC address "
5935                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5936                                     "diag=%d",
5937                                     mac_addr->addr_bytes[0],
5938                                     mac_addr->addr_bytes[1],
5939                                     mac_addr->addr_bytes[2],
5940                                     mac_addr->addr_bytes[3],
5941                                     mac_addr->addr_bytes[4],
5942                                     mac_addr->addr_bytes[5],
5943                                     diag);
5944         }
5945 }
5946
5947 static int
5948 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5949 {
5950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5951
5952         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5953
5954         return 0;
5955 }
5956
5957 int
5958 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5959                         struct rte_eth_syn_filter *filter,
5960                         bool add)
5961 {
5962         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5963         struct ixgbe_filter_info *filter_info =
5964                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5965         uint32_t syn_info;
5966         uint32_t synqf;
5967
5968         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5969                 return -EINVAL;
5970
5971         syn_info = filter_info->syn_info;
5972
5973         if (add) {
5974                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5975                         return -EINVAL;
5976                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5977                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5978
5979                 if (filter->hig_pri)
5980                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5981                 else
5982                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5983         } else {
5984                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5985                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5986                         return -ENOENT;
5987                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5988         }
5989
5990         filter_info->syn_info = synqf;
5991         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5992         IXGBE_WRITE_FLUSH(hw);
5993         return 0;
5994 }
5995
5996 static int
5997 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5998                         struct rte_eth_syn_filter *filter)
5999 {
6000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6001         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6002
6003         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6004                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6005                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6006                 return 0;
6007         }
6008         return -ENOENT;
6009 }
6010
6011 static int
6012 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6013                         enum rte_filter_op filter_op,
6014                         void *arg)
6015 {
6016         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6017         int ret;
6018
6019         MAC_TYPE_FILTER_SUP(hw->mac.type);
6020
6021         if (filter_op == RTE_ETH_FILTER_NOP)
6022                 return 0;
6023
6024         if (arg == NULL) {
6025                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6026                             filter_op);
6027                 return -EINVAL;
6028         }
6029
6030         switch (filter_op) {
6031         case RTE_ETH_FILTER_ADD:
6032                 ret = ixgbe_syn_filter_set(dev,
6033                                 (struct rte_eth_syn_filter *)arg,
6034                                 TRUE);
6035                 break;
6036         case RTE_ETH_FILTER_DELETE:
6037                 ret = ixgbe_syn_filter_set(dev,
6038                                 (struct rte_eth_syn_filter *)arg,
6039                                 FALSE);
6040                 break;
6041         case RTE_ETH_FILTER_GET:
6042                 ret = ixgbe_syn_filter_get(dev,
6043                                 (struct rte_eth_syn_filter *)arg);
6044                 break;
6045         default:
6046                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6047                 ret = -EINVAL;
6048                 break;
6049         }
6050
6051         return ret;
6052 }
6053
6054
6055 static inline enum ixgbe_5tuple_protocol
6056 convert_protocol_type(uint8_t protocol_value)
6057 {
6058         if (protocol_value == IPPROTO_TCP)
6059                 return IXGBE_FILTER_PROTOCOL_TCP;
6060         else if (protocol_value == IPPROTO_UDP)
6061                 return IXGBE_FILTER_PROTOCOL_UDP;
6062         else if (protocol_value == IPPROTO_SCTP)
6063                 return IXGBE_FILTER_PROTOCOL_SCTP;
6064         else
6065                 return IXGBE_FILTER_PROTOCOL_NONE;
6066 }
6067
6068 /* inject a 5-tuple filter to HW */
6069 static inline void
6070 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6071                            struct ixgbe_5tuple_filter *filter)
6072 {
6073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6074         int i;
6075         uint32_t ftqf, sdpqf;
6076         uint32_t l34timir = 0;
6077         uint8_t mask = 0xff;
6078
6079         i = filter->index;
6080
6081         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6082                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6083         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6084
6085         ftqf = (uint32_t)(filter->filter_info.proto &
6086                 IXGBE_FTQF_PROTOCOL_MASK);
6087         ftqf |= (uint32_t)((filter->filter_info.priority &
6088                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6089         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6090                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6091         if (filter->filter_info.dst_ip_mask == 0)
6092                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6093         if (filter->filter_info.src_port_mask == 0)
6094                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6095         if (filter->filter_info.dst_port_mask == 0)
6096                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6097         if (filter->filter_info.proto_mask == 0)
6098                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6099         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6100         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6101         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6102
6103         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6104         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6105         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6106         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6107
6108         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6109         l34timir |= (uint32_t)(filter->queue <<
6110                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6111         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6112 }
6113
6114 /*
6115  * add a 5tuple filter
6116  *
6117  * @param
6118  * dev: Pointer to struct rte_eth_dev.
6119  * index: the index the filter allocates.
6120  * filter: ponter to the filter that will be added.
6121  * rx_queue: the queue id the filter assigned to.
6122  *
6123  * @return
6124  *    - On success, zero.
6125  *    - On failure, a negative value.
6126  */
6127 static int
6128 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6129                         struct ixgbe_5tuple_filter *filter)
6130 {
6131         struct ixgbe_filter_info *filter_info =
6132                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6133         int i, idx, shift;
6134
6135         /*
6136          * look for an unused 5tuple filter index,
6137          * and insert the filter to list.
6138          */
6139         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6140                 idx = i / (sizeof(uint32_t) * NBBY);
6141                 shift = i % (sizeof(uint32_t) * NBBY);
6142                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6143                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6144                         filter->index = i;
6145                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6146                                           filter,
6147                                           entries);
6148                         break;
6149                 }
6150         }
6151         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6152                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6153                 return -ENOSYS;
6154         }
6155
6156         ixgbe_inject_5tuple_filter(dev, filter);
6157
6158         return 0;
6159 }
6160
6161 /*
6162  * remove a 5tuple filter
6163  *
6164  * @param
6165  * dev: Pointer to struct rte_eth_dev.
6166  * filter: the pointer of the filter will be removed.
6167  */
6168 static void
6169 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6170                         struct ixgbe_5tuple_filter *filter)
6171 {
6172         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6173         struct ixgbe_filter_info *filter_info =
6174                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6175         uint16_t index = filter->index;
6176
6177         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6178                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6179         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6180         rte_free(filter);
6181
6182         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6183         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6184         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6185         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6186         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6187 }
6188
6189 static int
6190 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6191 {
6192         struct ixgbe_hw *hw;
6193         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6194         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6195
6196         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6197
6198         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6199                 return -EINVAL;
6200
6201         /* refuse mtu that requires the support of scattered packets when this
6202          * feature has not been enabled before.
6203          */
6204         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6205             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6206              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6207                 return -EINVAL;
6208
6209         /*
6210          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6211          * request of the version 2.0 of the mailbox API.
6212          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6213          * of the mailbox API.
6214          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6215          * prior to 3.11.33 which contains the following change:
6216          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6217          */
6218         ixgbevf_rlpml_set_vf(hw, max_frame);
6219
6220         /* update max frame size */
6221         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6222         return 0;
6223 }
6224
6225 static inline struct ixgbe_5tuple_filter *
6226 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6227                         struct ixgbe_5tuple_filter_info *key)
6228 {
6229         struct ixgbe_5tuple_filter *it;
6230
6231         TAILQ_FOREACH(it, filter_list, entries) {
6232                 if (memcmp(key, &it->filter_info,
6233                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6234                         return it;
6235                 }
6236         }
6237         return NULL;
6238 }
6239
6240 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6241 static inline int
6242 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6243                         struct ixgbe_5tuple_filter_info *filter_info)
6244 {
6245         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6246                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6247                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6248                 return -EINVAL;
6249
6250         switch (filter->dst_ip_mask) {
6251         case UINT32_MAX:
6252                 filter_info->dst_ip_mask = 0;
6253                 filter_info->dst_ip = filter->dst_ip;
6254                 break;
6255         case 0:
6256                 filter_info->dst_ip_mask = 1;
6257                 break;
6258         default:
6259                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6260                 return -EINVAL;
6261         }
6262
6263         switch (filter->src_ip_mask) {
6264         case UINT32_MAX:
6265                 filter_info->src_ip_mask = 0;
6266                 filter_info->src_ip = filter->src_ip;
6267                 break;
6268         case 0:
6269                 filter_info->src_ip_mask = 1;
6270                 break;
6271         default:
6272                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6273                 return -EINVAL;
6274         }
6275
6276         switch (filter->dst_port_mask) {
6277         case UINT16_MAX:
6278                 filter_info->dst_port_mask = 0;
6279                 filter_info->dst_port = filter->dst_port;
6280                 break;
6281         case 0:
6282                 filter_info->dst_port_mask = 1;
6283                 break;
6284         default:
6285                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6286                 return -EINVAL;
6287         }
6288
6289         switch (filter->src_port_mask) {
6290         case UINT16_MAX:
6291                 filter_info->src_port_mask = 0;
6292                 filter_info->src_port = filter->src_port;
6293                 break;
6294         case 0:
6295                 filter_info->src_port_mask = 1;
6296                 break;
6297         default:
6298                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6299                 return -EINVAL;
6300         }
6301
6302         switch (filter->proto_mask) {
6303         case UINT8_MAX:
6304                 filter_info->proto_mask = 0;
6305                 filter_info->proto =
6306                         convert_protocol_type(filter->proto);
6307                 break;
6308         case 0:
6309                 filter_info->proto_mask = 1;
6310                 break;
6311         default:
6312                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6313                 return -EINVAL;
6314         }
6315
6316         filter_info->priority = (uint8_t)filter->priority;
6317         return 0;
6318 }
6319
6320 /*
6321  * add or delete a ntuple filter
6322  *
6323  * @param
6324  * dev: Pointer to struct rte_eth_dev.
6325  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6326  * add: if true, add filter, if false, remove filter
6327  *
6328  * @return
6329  *    - On success, zero.
6330  *    - On failure, a negative value.
6331  */
6332 int
6333 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6334                         struct rte_eth_ntuple_filter *ntuple_filter,
6335                         bool add)
6336 {
6337         struct ixgbe_filter_info *filter_info =
6338                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6339         struct ixgbe_5tuple_filter_info filter_5tuple;
6340         struct ixgbe_5tuple_filter *filter;
6341         int ret;
6342
6343         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6344                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6345                 return -EINVAL;
6346         }
6347
6348         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6349         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6350         if (ret < 0)
6351                 return ret;
6352
6353         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6354                                          &filter_5tuple);
6355         if (filter != NULL && add) {
6356                 PMD_DRV_LOG(ERR, "filter exists.");
6357                 return -EEXIST;
6358         }
6359         if (filter == NULL && !add) {
6360                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6361                 return -ENOENT;
6362         }
6363
6364         if (add) {
6365                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6366                                 sizeof(struct ixgbe_5tuple_filter), 0);
6367                 if (filter == NULL)
6368                         return -ENOMEM;
6369                 rte_memcpy(&filter->filter_info,
6370                                  &filter_5tuple,
6371                                  sizeof(struct ixgbe_5tuple_filter_info));
6372                 filter->queue = ntuple_filter->queue;
6373                 ret = ixgbe_add_5tuple_filter(dev, filter);
6374                 if (ret < 0) {
6375                         rte_free(filter);
6376                         return ret;
6377                 }
6378         } else
6379                 ixgbe_remove_5tuple_filter(dev, filter);
6380
6381         return 0;
6382 }
6383
6384 /*
6385  * get a ntuple filter
6386  *
6387  * @param
6388  * dev: Pointer to struct rte_eth_dev.
6389  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6390  *
6391  * @return
6392  *    - On success, zero.
6393  *    - On failure, a negative value.
6394  */
6395 static int
6396 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6397                         struct rte_eth_ntuple_filter *ntuple_filter)
6398 {
6399         struct ixgbe_filter_info *filter_info =
6400                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6401         struct ixgbe_5tuple_filter_info filter_5tuple;
6402         struct ixgbe_5tuple_filter *filter;
6403         int ret;
6404
6405         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6406                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6407                 return -EINVAL;
6408         }
6409
6410         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6411         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6412         if (ret < 0)
6413                 return ret;
6414
6415         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6416                                          &filter_5tuple);
6417         if (filter == NULL) {
6418                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6419                 return -ENOENT;
6420         }
6421         ntuple_filter->queue = filter->queue;
6422         return 0;
6423 }
6424
6425 /*
6426  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6427  * @dev: pointer to rte_eth_dev structure
6428  * @filter_op:operation will be taken.
6429  * @arg: a pointer to specific structure corresponding to the filter_op
6430  *
6431  * @return
6432  *    - On success, zero.
6433  *    - On failure, a negative value.
6434  */
6435 static int
6436 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6437                                 enum rte_filter_op filter_op,
6438                                 void *arg)
6439 {
6440         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6441         int ret;
6442
6443         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6444
6445         if (filter_op == RTE_ETH_FILTER_NOP)
6446                 return 0;
6447
6448         if (arg == NULL) {
6449                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6450                             filter_op);
6451                 return -EINVAL;
6452         }
6453
6454         switch (filter_op) {
6455         case RTE_ETH_FILTER_ADD:
6456                 ret = ixgbe_add_del_ntuple_filter(dev,
6457                         (struct rte_eth_ntuple_filter *)arg,
6458                         TRUE);
6459                 break;
6460         case RTE_ETH_FILTER_DELETE:
6461                 ret = ixgbe_add_del_ntuple_filter(dev,
6462                         (struct rte_eth_ntuple_filter *)arg,
6463                         FALSE);
6464                 break;
6465         case RTE_ETH_FILTER_GET:
6466                 ret = ixgbe_get_ntuple_filter(dev,
6467                         (struct rte_eth_ntuple_filter *)arg);
6468                 break;
6469         default:
6470                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6471                 ret = -EINVAL;
6472                 break;
6473         }
6474         return ret;
6475 }
6476
6477 int
6478 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6479                         struct rte_eth_ethertype_filter *filter,
6480                         bool add)
6481 {
6482         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6483         struct ixgbe_filter_info *filter_info =
6484                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6485         uint32_t etqf = 0;
6486         uint32_t etqs = 0;
6487         int ret;
6488         struct ixgbe_ethertype_filter ethertype_filter;
6489
6490         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6491                 return -EINVAL;
6492
6493         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6494                 filter->ether_type == ETHER_TYPE_IPv6) {
6495                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6496                         " ethertype filter.", filter->ether_type);
6497                 return -EINVAL;
6498         }
6499
6500         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6501                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6502                 return -EINVAL;
6503         }
6504         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6505                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6506                 return -EINVAL;
6507         }
6508
6509         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6510         if (ret >= 0 && add) {
6511                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6512                             filter->ether_type);
6513                 return -EEXIST;
6514         }
6515         if (ret < 0 && !add) {
6516                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6517                             filter->ether_type);
6518                 return -ENOENT;
6519         }
6520
6521         if (add) {
6522                 etqf = IXGBE_ETQF_FILTER_EN;
6523                 etqf |= (uint32_t)filter->ether_type;
6524                 etqs |= (uint32_t)((filter->queue <<
6525                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6526                                     IXGBE_ETQS_RX_QUEUE);
6527                 etqs |= IXGBE_ETQS_QUEUE_EN;
6528
6529                 ethertype_filter.ethertype = filter->ether_type;
6530                 ethertype_filter.etqf = etqf;
6531                 ethertype_filter.etqs = etqs;
6532                 ethertype_filter.conf = FALSE;
6533                 ret = ixgbe_ethertype_filter_insert(filter_info,
6534                                                     &ethertype_filter);
6535                 if (ret < 0) {
6536                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6537                         return -ENOSPC;
6538                 }
6539         } else {
6540                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6541                 if (ret < 0)
6542                         return -ENOSYS;
6543         }
6544         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6545         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6546         IXGBE_WRITE_FLUSH(hw);
6547
6548         return 0;
6549 }
6550
6551 static int
6552 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6553                         struct rte_eth_ethertype_filter *filter)
6554 {
6555         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6556         struct ixgbe_filter_info *filter_info =
6557                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6558         uint32_t etqf, etqs;
6559         int ret;
6560
6561         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6562         if (ret < 0) {
6563                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6564                             filter->ether_type);
6565                 return -ENOENT;
6566         }
6567
6568         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6569         if (etqf & IXGBE_ETQF_FILTER_EN) {
6570                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6571                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6572                 filter->flags = 0;
6573                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6574                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6575                 return 0;
6576         }
6577         return -ENOENT;
6578 }
6579
6580 /*
6581  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6582  * @dev: pointer to rte_eth_dev structure
6583  * @filter_op:operation will be taken.
6584  * @arg: a pointer to specific structure corresponding to the filter_op
6585  */
6586 static int
6587 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6588                                 enum rte_filter_op filter_op,
6589                                 void *arg)
6590 {
6591         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6592         int ret;
6593
6594         MAC_TYPE_FILTER_SUP(hw->mac.type);
6595
6596         if (filter_op == RTE_ETH_FILTER_NOP)
6597                 return 0;
6598
6599         if (arg == NULL) {
6600                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6601                             filter_op);
6602                 return -EINVAL;
6603         }
6604
6605         switch (filter_op) {
6606         case RTE_ETH_FILTER_ADD:
6607                 ret = ixgbe_add_del_ethertype_filter(dev,
6608                         (struct rte_eth_ethertype_filter *)arg,
6609                         TRUE);
6610                 break;
6611         case RTE_ETH_FILTER_DELETE:
6612                 ret = ixgbe_add_del_ethertype_filter(dev,
6613                         (struct rte_eth_ethertype_filter *)arg,
6614                         FALSE);
6615                 break;
6616         case RTE_ETH_FILTER_GET:
6617                 ret = ixgbe_get_ethertype_filter(dev,
6618                         (struct rte_eth_ethertype_filter *)arg);
6619                 break;
6620         default:
6621                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6622                 ret = -EINVAL;
6623                 break;
6624         }
6625         return ret;
6626 }
6627
6628 static int
6629 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6630                      enum rte_filter_type filter_type,
6631                      enum rte_filter_op filter_op,
6632                      void *arg)
6633 {
6634         int ret = 0;
6635
6636         switch (filter_type) {
6637         case RTE_ETH_FILTER_NTUPLE:
6638                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6639                 break;
6640         case RTE_ETH_FILTER_ETHERTYPE:
6641                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6642                 break;
6643         case RTE_ETH_FILTER_SYN:
6644                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6645                 break;
6646         case RTE_ETH_FILTER_FDIR:
6647                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6648                 break;
6649         case RTE_ETH_FILTER_L2_TUNNEL:
6650                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6651                 break;
6652         case RTE_ETH_FILTER_GENERIC:
6653                 if (filter_op != RTE_ETH_FILTER_GET)
6654                         return -EINVAL;
6655                 *(const void **)arg = &ixgbe_flow_ops;
6656                 break;
6657         default:
6658                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6659                                                         filter_type);
6660                 ret = -EINVAL;
6661                 break;
6662         }
6663
6664         return ret;
6665 }
6666
6667 static u8 *
6668 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6669                         u8 **mc_addr_ptr, u32 *vmdq)
6670 {
6671         u8 *mc_addr;
6672
6673         *vmdq = 0;
6674         mc_addr = *mc_addr_ptr;
6675         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6676         return mc_addr;
6677 }
6678
6679 static int
6680 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6681                           struct ether_addr *mc_addr_set,
6682                           uint32_t nb_mc_addr)
6683 {
6684         struct ixgbe_hw *hw;
6685         u8 *mc_addr_list;
6686
6687         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6688         mc_addr_list = (u8 *)mc_addr_set;
6689         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6690                                          ixgbe_dev_addr_list_itr, TRUE);
6691 }
6692
6693 static uint64_t
6694 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6695 {
6696         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6697         uint64_t systime_cycles;
6698
6699         switch (hw->mac.type) {
6700         case ixgbe_mac_X550:
6701         case ixgbe_mac_X550EM_x:
6702         case ixgbe_mac_X550EM_a:
6703                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6704                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6705                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6706                                 * NSEC_PER_SEC;
6707                 break;
6708         default:
6709                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6710                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6711                                 << 32;
6712         }
6713
6714         return systime_cycles;
6715 }
6716
6717 static uint64_t
6718 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6719 {
6720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6721         uint64_t rx_tstamp_cycles;
6722
6723         switch (hw->mac.type) {
6724         case ixgbe_mac_X550:
6725         case ixgbe_mac_X550EM_x:
6726         case ixgbe_mac_X550EM_a:
6727                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6728                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6729                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6730                                 * NSEC_PER_SEC;
6731                 break;
6732         default:
6733                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6734                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6735                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6736                                 << 32;
6737         }
6738
6739         return rx_tstamp_cycles;
6740 }
6741
6742 static uint64_t
6743 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6744 {
6745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6746         uint64_t tx_tstamp_cycles;
6747
6748         switch (hw->mac.type) {
6749         case ixgbe_mac_X550:
6750         case ixgbe_mac_X550EM_x:
6751         case ixgbe_mac_X550EM_a:
6752                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6753                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6754                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6755                                 * NSEC_PER_SEC;
6756                 break;
6757         default:
6758                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6759                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6760                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6761                                 << 32;
6762         }
6763
6764         return tx_tstamp_cycles;
6765 }
6766
6767 static void
6768 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6769 {
6770         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6771         struct ixgbe_adapter *adapter =
6772                 (struct ixgbe_adapter *)dev->data->dev_private;
6773         struct rte_eth_link link;
6774         uint32_t incval = 0;
6775         uint32_t shift = 0;
6776
6777         /* Get current link speed. */
6778         ixgbe_dev_link_update(dev, 1);
6779         rte_eth_linkstatus_get(dev, &link);
6780
6781         switch (link.link_speed) {
6782         case ETH_SPEED_NUM_100M:
6783                 incval = IXGBE_INCVAL_100;
6784                 shift = IXGBE_INCVAL_SHIFT_100;
6785                 break;
6786         case ETH_SPEED_NUM_1G:
6787                 incval = IXGBE_INCVAL_1GB;
6788                 shift = IXGBE_INCVAL_SHIFT_1GB;
6789                 break;
6790         case ETH_SPEED_NUM_10G:
6791         default:
6792                 incval = IXGBE_INCVAL_10GB;
6793                 shift = IXGBE_INCVAL_SHIFT_10GB;
6794                 break;
6795         }
6796
6797         switch (hw->mac.type) {
6798         case ixgbe_mac_X550:
6799         case ixgbe_mac_X550EM_x:
6800         case ixgbe_mac_X550EM_a:
6801                 /* Independent of link speed. */
6802                 incval = 1;
6803                 /* Cycles read will be interpreted as ns. */
6804                 shift = 0;
6805                 /* Fall-through */
6806         case ixgbe_mac_X540:
6807                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6808                 break;
6809         case ixgbe_mac_82599EB:
6810                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6811                 shift -= IXGBE_INCVAL_SHIFT_82599;
6812                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6813                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6814                 break;
6815         default:
6816                 /* Not supported. */
6817                 return;
6818         }
6819
6820         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6821         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6822         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6823
6824         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6825         adapter->systime_tc.cc_shift = shift;
6826         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6827
6828         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6829         adapter->rx_tstamp_tc.cc_shift = shift;
6830         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6831
6832         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6833         adapter->tx_tstamp_tc.cc_shift = shift;
6834         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6835 }
6836
6837 static int
6838 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6839 {
6840         struct ixgbe_adapter *adapter =
6841                         (struct ixgbe_adapter *)dev->data->dev_private;
6842
6843         adapter->systime_tc.nsec += delta;
6844         adapter->rx_tstamp_tc.nsec += delta;
6845         adapter->tx_tstamp_tc.nsec += delta;
6846
6847         return 0;
6848 }
6849
6850 static int
6851 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6852 {
6853         uint64_t ns;
6854         struct ixgbe_adapter *adapter =
6855                         (struct ixgbe_adapter *)dev->data->dev_private;
6856
6857         ns = rte_timespec_to_ns(ts);
6858         /* Set the timecounters to a new value. */
6859         adapter->systime_tc.nsec = ns;
6860         adapter->rx_tstamp_tc.nsec = ns;
6861         adapter->tx_tstamp_tc.nsec = ns;
6862
6863         return 0;
6864 }
6865
6866 static int
6867 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6868 {
6869         uint64_t ns, systime_cycles;
6870         struct ixgbe_adapter *adapter =
6871                         (struct ixgbe_adapter *)dev->data->dev_private;
6872
6873         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6874         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6875         *ts = rte_ns_to_timespec(ns);
6876
6877         return 0;
6878 }
6879
6880 static int
6881 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6882 {
6883         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6884         uint32_t tsync_ctl;
6885         uint32_t tsauxc;
6886
6887         /* Stop the timesync system time. */
6888         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6889         /* Reset the timesync system time value. */
6890         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6891         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6892
6893         /* Enable system time for platforms where it isn't on by default. */
6894         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6895         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6896         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6897
6898         ixgbe_start_timecounters(dev);
6899
6900         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6901         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6902                         (ETHER_TYPE_1588 |
6903                          IXGBE_ETQF_FILTER_EN |
6904                          IXGBE_ETQF_1588));
6905
6906         /* Enable timestamping of received PTP packets. */
6907         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6908         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6909         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6910
6911         /* Enable timestamping of transmitted PTP packets. */
6912         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6913         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6914         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6915
6916         IXGBE_WRITE_FLUSH(hw);
6917
6918         return 0;
6919 }
6920
6921 static int
6922 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6923 {
6924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6925         uint32_t tsync_ctl;
6926
6927         /* Disable timestamping of transmitted PTP packets. */
6928         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6929         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6930         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6931
6932         /* Disable timestamping of received PTP packets. */
6933         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6934         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6935         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6936
6937         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6938         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6939
6940         /* Stop incrementating the System Time registers. */
6941         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6942
6943         return 0;
6944 }
6945
6946 static int
6947 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6948                                  struct timespec *timestamp,
6949                                  uint32_t flags __rte_unused)
6950 {
6951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6952         struct ixgbe_adapter *adapter =
6953                 (struct ixgbe_adapter *)dev->data->dev_private;
6954         uint32_t tsync_rxctl;
6955         uint64_t rx_tstamp_cycles;
6956         uint64_t ns;
6957
6958         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6959         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6960                 return -EINVAL;
6961
6962         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6963         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6964         *timestamp = rte_ns_to_timespec(ns);
6965
6966         return  0;
6967 }
6968
6969 static int
6970 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6971                                  struct timespec *timestamp)
6972 {
6973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6974         struct ixgbe_adapter *adapter =
6975                 (struct ixgbe_adapter *)dev->data->dev_private;
6976         uint32_t tsync_txctl;
6977         uint64_t tx_tstamp_cycles;
6978         uint64_t ns;
6979
6980         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6981         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6982                 return -EINVAL;
6983
6984         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6985         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6986         *timestamp = rte_ns_to_timespec(ns);
6987
6988         return 0;
6989 }
6990
6991 static int
6992 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6993 {
6994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6995         int count = 0;
6996         int g_ind = 0;
6997         const struct reg_info *reg_group;
6998         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6999                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7000
7001         while ((reg_group = reg_set[g_ind++]))
7002                 count += ixgbe_regs_group_count(reg_group);
7003
7004         return count;
7005 }
7006
7007 static int
7008 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7009 {
7010         int count = 0;
7011         int g_ind = 0;
7012         const struct reg_info *reg_group;
7013
7014         while ((reg_group = ixgbevf_regs[g_ind++]))
7015                 count += ixgbe_regs_group_count(reg_group);
7016
7017         return count;
7018 }
7019
7020 static int
7021 ixgbe_get_regs(struct rte_eth_dev *dev,
7022               struct rte_dev_reg_info *regs)
7023 {
7024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7025         uint32_t *data = regs->data;
7026         int g_ind = 0;
7027         int count = 0;
7028         const struct reg_info *reg_group;
7029         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7030                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7031
7032         if (data == NULL) {
7033                 regs->length = ixgbe_get_reg_length(dev);
7034                 regs->width = sizeof(uint32_t);
7035                 return 0;
7036         }
7037
7038         /* Support only full register dump */
7039         if ((regs->length == 0) ||
7040             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7041                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7042                         hw->device_id;
7043                 while ((reg_group = reg_set[g_ind++]))
7044                         count += ixgbe_read_regs_group(dev, &data[count],
7045                                 reg_group);
7046                 return 0;
7047         }
7048
7049         return -ENOTSUP;
7050 }
7051
7052 static int
7053 ixgbevf_get_regs(struct rte_eth_dev *dev,
7054                 struct rte_dev_reg_info *regs)
7055 {
7056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7057         uint32_t *data = regs->data;
7058         int g_ind = 0;
7059         int count = 0;
7060         const struct reg_info *reg_group;
7061
7062         if (data == NULL) {
7063                 regs->length = ixgbevf_get_reg_length(dev);
7064                 regs->width = sizeof(uint32_t);
7065                 return 0;
7066         }
7067
7068         /* Support only full register dump */
7069         if ((regs->length == 0) ||
7070             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7071                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7072                         hw->device_id;
7073                 while ((reg_group = ixgbevf_regs[g_ind++]))
7074                         count += ixgbe_read_regs_group(dev, &data[count],
7075                                                       reg_group);
7076                 return 0;
7077         }
7078
7079         return -ENOTSUP;
7080 }
7081
7082 static int
7083 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7084 {
7085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7086
7087         /* Return unit is byte count */
7088         return hw->eeprom.word_size * 2;
7089 }
7090
7091 static int
7092 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7093                 struct rte_dev_eeprom_info *in_eeprom)
7094 {
7095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7096         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7097         uint16_t *data = in_eeprom->data;
7098         int first, length;
7099
7100         first = in_eeprom->offset >> 1;
7101         length = in_eeprom->length >> 1;
7102         if ((first > hw->eeprom.word_size) ||
7103             ((first + length) > hw->eeprom.word_size))
7104                 return -EINVAL;
7105
7106         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7107
7108         return eeprom->ops.read_buffer(hw, first, length, data);
7109 }
7110
7111 static int
7112 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7113                 struct rte_dev_eeprom_info *in_eeprom)
7114 {
7115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7116         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7117         uint16_t *data = in_eeprom->data;
7118         int first, length;
7119
7120         first = in_eeprom->offset >> 1;
7121         length = in_eeprom->length >> 1;
7122         if ((first > hw->eeprom.word_size) ||
7123             ((first + length) > hw->eeprom.word_size))
7124                 return -EINVAL;
7125
7126         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7127
7128         return eeprom->ops.write_buffer(hw,  first, length, data);
7129 }
7130
7131 static int
7132 ixgbe_get_module_info(struct rte_eth_dev *dev,
7133                       struct rte_eth_dev_module_info *modinfo)
7134 {
7135         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7136         uint32_t status;
7137         uint8_t sff8472_rev, addr_mode;
7138         bool page_swap = false;
7139
7140         /* Check whether we support SFF-8472 or not */
7141         status = hw->phy.ops.read_i2c_eeprom(hw,
7142                                              IXGBE_SFF_SFF_8472_COMP,
7143                                              &sff8472_rev);
7144         if (status != 0)
7145                 return -EIO;
7146
7147         /* addressing mode is not supported */
7148         status = hw->phy.ops.read_i2c_eeprom(hw,
7149                                              IXGBE_SFF_SFF_8472_SWAP,
7150                                              &addr_mode);
7151         if (status != 0)
7152                 return -EIO;
7153
7154         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7155                 PMD_DRV_LOG(ERR,
7156                             "Address change required to access page 0xA2, "
7157                             "but not supported. Please report the module "
7158                             "type to the driver maintainers.");
7159                 page_swap = true;
7160         }
7161
7162         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7163                 /* We have a SFP, but it does not support SFF-8472 */
7164                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7165                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7166         } else {
7167                 /* We have a SFP which supports a revision of SFF-8472. */
7168                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7169                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7170         }
7171
7172         return 0;
7173 }
7174
7175 static int
7176 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7177                         struct rte_dev_eeprom_info *info)
7178 {
7179         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7180         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7181         uint8_t databyte = 0xFF;
7182         uint8_t *data = info->data;
7183         uint32_t i = 0;
7184
7185         if (info->length == 0)
7186                 return -EINVAL;
7187
7188         for (i = info->offset; i < info->offset + info->length; i++) {
7189                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7190                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7191                 else
7192                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7193
7194                 if (status != 0)
7195                         return -EIO;
7196
7197                 data[i - info->offset] = databyte;
7198         }
7199
7200         return 0;
7201 }
7202
7203 uint16_t
7204 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7205         switch (mac_type) {
7206         case ixgbe_mac_X550:
7207         case ixgbe_mac_X550EM_x:
7208         case ixgbe_mac_X550EM_a:
7209                 return ETH_RSS_RETA_SIZE_512;
7210         case ixgbe_mac_X550_vf:
7211         case ixgbe_mac_X550EM_x_vf:
7212         case ixgbe_mac_X550EM_a_vf:
7213                 return ETH_RSS_RETA_SIZE_64;
7214         default:
7215                 return ETH_RSS_RETA_SIZE_128;
7216         }
7217 }
7218
7219 uint32_t
7220 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7221         switch (mac_type) {
7222         case ixgbe_mac_X550:
7223         case ixgbe_mac_X550EM_x:
7224         case ixgbe_mac_X550EM_a:
7225                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7226                         return IXGBE_RETA(reta_idx >> 2);
7227                 else
7228                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7229         case ixgbe_mac_X550_vf:
7230         case ixgbe_mac_X550EM_x_vf:
7231         case ixgbe_mac_X550EM_a_vf:
7232                 return IXGBE_VFRETA(reta_idx >> 2);
7233         default:
7234                 return IXGBE_RETA(reta_idx >> 2);
7235         }
7236 }
7237
7238 uint32_t
7239 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7240         switch (mac_type) {
7241         case ixgbe_mac_X550_vf:
7242         case ixgbe_mac_X550EM_x_vf:
7243         case ixgbe_mac_X550EM_a_vf:
7244                 return IXGBE_VFMRQC;
7245         default:
7246                 return IXGBE_MRQC;
7247         }
7248 }
7249
7250 uint32_t
7251 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7252         switch (mac_type) {
7253         case ixgbe_mac_X550_vf:
7254         case ixgbe_mac_X550EM_x_vf:
7255         case ixgbe_mac_X550EM_a_vf:
7256                 return IXGBE_VFRSSRK(i);
7257         default:
7258                 return IXGBE_RSSRK(i);
7259         }
7260 }
7261
7262 bool
7263 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7264         switch (mac_type) {
7265         case ixgbe_mac_82599_vf:
7266         case ixgbe_mac_X540_vf:
7267                 return 0;
7268         default:
7269                 return 1;
7270         }
7271 }
7272
7273 static int
7274 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7275                         struct rte_eth_dcb_info *dcb_info)
7276 {
7277         struct ixgbe_dcb_config *dcb_config =
7278                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7279         struct ixgbe_dcb_tc_config *tc;
7280         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7281         uint8_t nb_tcs;
7282         uint8_t i, j;
7283
7284         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7285                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7286         else
7287                 dcb_info->nb_tcs = 1;
7288
7289         tc_queue = &dcb_info->tc_queue;
7290         nb_tcs = dcb_info->nb_tcs;
7291
7292         if (dcb_config->vt_mode) { /* vt is enabled*/
7293                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7294                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7295                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7296                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7297                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7298                         for (j = 0; j < nb_tcs; j++) {
7299                                 tc_queue->tc_rxq[0][j].base = j;
7300                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7301                                 tc_queue->tc_txq[0][j].base = j;
7302                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7303                         }
7304                 } else {
7305                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7306                                 for (j = 0; j < nb_tcs; j++) {
7307                                         tc_queue->tc_rxq[i][j].base =
7308                                                 i * nb_tcs + j;
7309                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7310                                         tc_queue->tc_txq[i][j].base =
7311                                                 i * nb_tcs + j;
7312                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7313                                 }
7314                         }
7315                 }
7316         } else { /* vt is disabled*/
7317                 struct rte_eth_dcb_rx_conf *rx_conf =
7318                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7319                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7320                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7321                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7322                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7323                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7324                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7325                         }
7326                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7327                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7328                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7329                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7330                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7331                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7332                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7333                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7334                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7335                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7336                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7337                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7338                         }
7339                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7340                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7341                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7342                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7343                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7344                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7345                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7346                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7347                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7348                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7349                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7350                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7351                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7352                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7353                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7354                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7355                 }
7356         }
7357         for (i = 0; i < dcb_info->nb_tcs; i++) {
7358                 tc = &dcb_config->tc_config[i];
7359                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7360         }
7361         return 0;
7362 }
7363
7364 /* Update e-tag ether type */
7365 static int
7366 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7367                             uint16_t ether_type)
7368 {
7369         uint32_t etag_etype;
7370
7371         if (hw->mac.type != ixgbe_mac_X550 &&
7372             hw->mac.type != ixgbe_mac_X550EM_x &&
7373             hw->mac.type != ixgbe_mac_X550EM_a) {
7374                 return -ENOTSUP;
7375         }
7376
7377         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7378         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7379         etag_etype |= ether_type;
7380         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7381         IXGBE_WRITE_FLUSH(hw);
7382
7383         return 0;
7384 }
7385
7386 /* Config l2 tunnel ether type */
7387 static int
7388 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7389                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7390 {
7391         int ret = 0;
7392         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7393         struct ixgbe_l2_tn_info *l2_tn_info =
7394                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7395
7396         if (l2_tunnel == NULL)
7397                 return -EINVAL;
7398
7399         switch (l2_tunnel->l2_tunnel_type) {
7400         case RTE_L2_TUNNEL_TYPE_E_TAG:
7401                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7402                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7403                 break;
7404         default:
7405                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7406                 ret = -EINVAL;
7407                 break;
7408         }
7409
7410         return ret;
7411 }
7412
7413 /* Enable e-tag tunnel */
7414 static int
7415 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7416 {
7417         uint32_t etag_etype;
7418
7419         if (hw->mac.type != ixgbe_mac_X550 &&
7420             hw->mac.type != ixgbe_mac_X550EM_x &&
7421             hw->mac.type != ixgbe_mac_X550EM_a) {
7422                 return -ENOTSUP;
7423         }
7424
7425         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7426         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7427         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7428         IXGBE_WRITE_FLUSH(hw);
7429
7430         return 0;
7431 }
7432
7433 /* Enable l2 tunnel */
7434 static int
7435 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7436                            enum rte_eth_tunnel_type l2_tunnel_type)
7437 {
7438         int ret = 0;
7439         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7440         struct ixgbe_l2_tn_info *l2_tn_info =
7441                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7442
7443         switch (l2_tunnel_type) {
7444         case RTE_L2_TUNNEL_TYPE_E_TAG:
7445                 l2_tn_info->e_tag_en = TRUE;
7446                 ret = ixgbe_e_tag_enable(hw);
7447                 break;
7448         default:
7449                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7450                 ret = -EINVAL;
7451                 break;
7452         }
7453
7454         return ret;
7455 }
7456
7457 /* Disable e-tag tunnel */
7458 static int
7459 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7460 {
7461         uint32_t etag_etype;
7462
7463         if (hw->mac.type != ixgbe_mac_X550 &&
7464             hw->mac.type != ixgbe_mac_X550EM_x &&
7465             hw->mac.type != ixgbe_mac_X550EM_a) {
7466                 return -ENOTSUP;
7467         }
7468
7469         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7470         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7471         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7472         IXGBE_WRITE_FLUSH(hw);
7473
7474         return 0;
7475 }
7476
7477 /* Disable l2 tunnel */
7478 static int
7479 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7480                             enum rte_eth_tunnel_type l2_tunnel_type)
7481 {
7482         int ret = 0;
7483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7484         struct ixgbe_l2_tn_info *l2_tn_info =
7485                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7486
7487         switch (l2_tunnel_type) {
7488         case RTE_L2_TUNNEL_TYPE_E_TAG:
7489                 l2_tn_info->e_tag_en = FALSE;
7490                 ret = ixgbe_e_tag_disable(hw);
7491                 break;
7492         default:
7493                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7494                 ret = -EINVAL;
7495                 break;
7496         }
7497
7498         return ret;
7499 }
7500
7501 static int
7502 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7503                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7504 {
7505         int ret = 0;
7506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7507         uint32_t i, rar_entries;
7508         uint32_t rar_low, rar_high;
7509
7510         if (hw->mac.type != ixgbe_mac_X550 &&
7511             hw->mac.type != ixgbe_mac_X550EM_x &&
7512             hw->mac.type != ixgbe_mac_X550EM_a) {
7513                 return -ENOTSUP;
7514         }
7515
7516         rar_entries = ixgbe_get_num_rx_addrs(hw);
7517
7518         for (i = 1; i < rar_entries; i++) {
7519                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7520                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7521                 if ((rar_high & IXGBE_RAH_AV) &&
7522                     (rar_high & IXGBE_RAH_ADTYPE) &&
7523                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7524                      l2_tunnel->tunnel_id)) {
7525                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7526                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7527
7528                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7529
7530                         return ret;
7531                 }
7532         }
7533
7534         return ret;
7535 }
7536
7537 static int
7538 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7539                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7540 {
7541         int ret = 0;
7542         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7543         uint32_t i, rar_entries;
7544         uint32_t rar_low, rar_high;
7545
7546         if (hw->mac.type != ixgbe_mac_X550 &&
7547             hw->mac.type != ixgbe_mac_X550EM_x &&
7548             hw->mac.type != ixgbe_mac_X550EM_a) {
7549                 return -ENOTSUP;
7550         }
7551
7552         /* One entry for one tunnel. Try to remove potential existing entry. */
7553         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7554
7555         rar_entries = ixgbe_get_num_rx_addrs(hw);
7556
7557         for (i = 1; i < rar_entries; i++) {
7558                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7559                 if (rar_high & IXGBE_RAH_AV) {
7560                         continue;
7561                 } else {
7562                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7563                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7564                         rar_low = l2_tunnel->tunnel_id;
7565
7566                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7567                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7568
7569                         return ret;
7570                 }
7571         }
7572
7573         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7574                      " Please remove a rule before adding a new one.");
7575         return -EINVAL;
7576 }
7577
7578 static inline struct ixgbe_l2_tn_filter *
7579 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7580                           struct ixgbe_l2_tn_key *key)
7581 {
7582         int ret;
7583
7584         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7585         if (ret < 0)
7586                 return NULL;
7587
7588         return l2_tn_info->hash_map[ret];
7589 }
7590
7591 static inline int
7592 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7593                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7594 {
7595         int ret;
7596
7597         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7598                                &l2_tn_filter->key);
7599
7600         if (ret < 0) {
7601                 PMD_DRV_LOG(ERR,
7602                             "Failed to insert L2 tunnel filter"
7603                             " to hash table %d!",
7604                             ret);
7605                 return ret;
7606         }
7607
7608         l2_tn_info->hash_map[ret] = l2_tn_filter;
7609
7610         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7611
7612         return 0;
7613 }
7614
7615 static inline int
7616 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7617                           struct ixgbe_l2_tn_key *key)
7618 {
7619         int ret;
7620         struct ixgbe_l2_tn_filter *l2_tn_filter;
7621
7622         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7623
7624         if (ret < 0) {
7625                 PMD_DRV_LOG(ERR,
7626                             "No such L2 tunnel filter to delete %d!",
7627                             ret);
7628                 return ret;
7629         }
7630
7631         l2_tn_filter = l2_tn_info->hash_map[ret];
7632         l2_tn_info->hash_map[ret] = NULL;
7633
7634         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7635         rte_free(l2_tn_filter);
7636
7637         return 0;
7638 }
7639
7640 /* Add l2 tunnel filter */
7641 int
7642 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7643                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7644                                bool restore)
7645 {
7646         int ret;
7647         struct ixgbe_l2_tn_info *l2_tn_info =
7648                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7649         struct ixgbe_l2_tn_key key;
7650         struct ixgbe_l2_tn_filter *node;
7651
7652         if (!restore) {
7653                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7654                 key.tn_id = l2_tunnel->tunnel_id;
7655
7656                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7657
7658                 if (node) {
7659                         PMD_DRV_LOG(ERR,
7660                                     "The L2 tunnel filter already exists!");
7661                         return -EINVAL;
7662                 }
7663
7664                 node = rte_zmalloc("ixgbe_l2_tn",
7665                                    sizeof(struct ixgbe_l2_tn_filter),
7666                                    0);
7667                 if (!node)
7668                         return -ENOMEM;
7669
7670                 rte_memcpy(&node->key,
7671                                  &key,
7672                                  sizeof(struct ixgbe_l2_tn_key));
7673                 node->pool = l2_tunnel->pool;
7674                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7675                 if (ret < 0) {
7676                         rte_free(node);
7677                         return ret;
7678                 }
7679         }
7680
7681         switch (l2_tunnel->l2_tunnel_type) {
7682         case RTE_L2_TUNNEL_TYPE_E_TAG:
7683                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7684                 break;
7685         default:
7686                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7687                 ret = -EINVAL;
7688                 break;
7689         }
7690
7691         if ((!restore) && (ret < 0))
7692                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7693
7694         return ret;
7695 }
7696
7697 /* Delete l2 tunnel filter */
7698 int
7699 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7700                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7701 {
7702         int ret;
7703         struct ixgbe_l2_tn_info *l2_tn_info =
7704                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7705         struct ixgbe_l2_tn_key key;
7706
7707         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7708         key.tn_id = l2_tunnel->tunnel_id;
7709         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7710         if (ret < 0)
7711                 return ret;
7712
7713         switch (l2_tunnel->l2_tunnel_type) {
7714         case RTE_L2_TUNNEL_TYPE_E_TAG:
7715                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7716                 break;
7717         default:
7718                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7719                 ret = -EINVAL;
7720                 break;
7721         }
7722
7723         return ret;
7724 }
7725
7726 /**
7727  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7728  * @dev: pointer to rte_eth_dev structure
7729  * @filter_op:operation will be taken.
7730  * @arg: a pointer to specific structure corresponding to the filter_op
7731  */
7732 static int
7733 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7734                                   enum rte_filter_op filter_op,
7735                                   void *arg)
7736 {
7737         int ret;
7738
7739         if (filter_op == RTE_ETH_FILTER_NOP)
7740                 return 0;
7741
7742         if (arg == NULL) {
7743                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7744                             filter_op);
7745                 return -EINVAL;
7746         }
7747
7748         switch (filter_op) {
7749         case RTE_ETH_FILTER_ADD:
7750                 ret = ixgbe_dev_l2_tunnel_filter_add
7751                         (dev,
7752                          (struct rte_eth_l2_tunnel_conf *)arg,
7753                          FALSE);
7754                 break;
7755         case RTE_ETH_FILTER_DELETE:
7756                 ret = ixgbe_dev_l2_tunnel_filter_del
7757                         (dev,
7758                          (struct rte_eth_l2_tunnel_conf *)arg);
7759                 break;
7760         default:
7761                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7762                 ret = -EINVAL;
7763                 break;
7764         }
7765         return ret;
7766 }
7767
7768 static int
7769 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7770 {
7771         int ret = 0;
7772         uint32_t ctrl;
7773         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7774
7775         if (hw->mac.type != ixgbe_mac_X550 &&
7776             hw->mac.type != ixgbe_mac_X550EM_x &&
7777             hw->mac.type != ixgbe_mac_X550EM_a) {
7778                 return -ENOTSUP;
7779         }
7780
7781         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7782         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7783         if (en)
7784                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7785         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7786
7787         return ret;
7788 }
7789
7790 /* Enable l2 tunnel forwarding */
7791 static int
7792 ixgbe_dev_l2_tunnel_forwarding_enable
7793         (struct rte_eth_dev *dev,
7794          enum rte_eth_tunnel_type l2_tunnel_type)
7795 {
7796         struct ixgbe_l2_tn_info *l2_tn_info =
7797                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7798         int ret = 0;
7799
7800         switch (l2_tunnel_type) {
7801         case RTE_L2_TUNNEL_TYPE_E_TAG:
7802                 l2_tn_info->e_tag_fwd_en = TRUE;
7803                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7804                 break;
7805         default:
7806                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7807                 ret = -EINVAL;
7808                 break;
7809         }
7810
7811         return ret;
7812 }
7813
7814 /* Disable l2 tunnel forwarding */
7815 static int
7816 ixgbe_dev_l2_tunnel_forwarding_disable
7817         (struct rte_eth_dev *dev,
7818          enum rte_eth_tunnel_type l2_tunnel_type)
7819 {
7820         struct ixgbe_l2_tn_info *l2_tn_info =
7821                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7822         int ret = 0;
7823
7824         switch (l2_tunnel_type) {
7825         case RTE_L2_TUNNEL_TYPE_E_TAG:
7826                 l2_tn_info->e_tag_fwd_en = FALSE;
7827                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7828                 break;
7829         default:
7830                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7831                 ret = -EINVAL;
7832                 break;
7833         }
7834
7835         return ret;
7836 }
7837
7838 static int
7839 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7840                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7841                              bool en)
7842 {
7843         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7844         int ret = 0;
7845         uint32_t vmtir, vmvir;
7846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7847
7848         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7849                 PMD_DRV_LOG(ERR,
7850                             "VF id %u should be less than %u",
7851                             l2_tunnel->vf_id,
7852                             pci_dev->max_vfs);
7853                 return -EINVAL;
7854         }
7855
7856         if (hw->mac.type != ixgbe_mac_X550 &&
7857             hw->mac.type != ixgbe_mac_X550EM_x &&
7858             hw->mac.type != ixgbe_mac_X550EM_a) {
7859                 return -ENOTSUP;
7860         }
7861
7862         if (en)
7863                 vmtir = l2_tunnel->tunnel_id;
7864         else
7865                 vmtir = 0;
7866
7867         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7868
7869         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7870         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7871         if (en)
7872                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7873         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7874
7875         return ret;
7876 }
7877
7878 /* Enable l2 tunnel tag insertion */
7879 static int
7880 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7881                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7882 {
7883         int ret = 0;
7884
7885         switch (l2_tunnel->l2_tunnel_type) {
7886         case RTE_L2_TUNNEL_TYPE_E_TAG:
7887                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7888                 break;
7889         default:
7890                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7891                 ret = -EINVAL;
7892                 break;
7893         }
7894
7895         return ret;
7896 }
7897
7898 /* Disable l2 tunnel tag insertion */
7899 static int
7900 ixgbe_dev_l2_tunnel_insertion_disable
7901         (struct rte_eth_dev *dev,
7902          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7903 {
7904         int ret = 0;
7905
7906         switch (l2_tunnel->l2_tunnel_type) {
7907         case RTE_L2_TUNNEL_TYPE_E_TAG:
7908                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7909                 break;
7910         default:
7911                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7912                 ret = -EINVAL;
7913                 break;
7914         }
7915
7916         return ret;
7917 }
7918
7919 static int
7920 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7921                              bool en)
7922 {
7923         int ret = 0;
7924         uint32_t qde;
7925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7926
7927         if (hw->mac.type != ixgbe_mac_X550 &&
7928             hw->mac.type != ixgbe_mac_X550EM_x &&
7929             hw->mac.type != ixgbe_mac_X550EM_a) {
7930                 return -ENOTSUP;
7931         }
7932
7933         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7934         if (en)
7935                 qde |= IXGBE_QDE_STRIP_TAG;
7936         else
7937                 qde &= ~IXGBE_QDE_STRIP_TAG;
7938         qde &= ~IXGBE_QDE_READ;
7939         qde |= IXGBE_QDE_WRITE;
7940         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7941
7942         return ret;
7943 }
7944
7945 /* Enable l2 tunnel tag stripping */
7946 static int
7947 ixgbe_dev_l2_tunnel_stripping_enable
7948         (struct rte_eth_dev *dev,
7949          enum rte_eth_tunnel_type l2_tunnel_type)
7950 {
7951         int ret = 0;
7952
7953         switch (l2_tunnel_type) {
7954         case RTE_L2_TUNNEL_TYPE_E_TAG:
7955                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7956                 break;
7957         default:
7958                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7959                 ret = -EINVAL;
7960                 break;
7961         }
7962
7963         return ret;
7964 }
7965
7966 /* Disable l2 tunnel tag stripping */
7967 static int
7968 ixgbe_dev_l2_tunnel_stripping_disable
7969         (struct rte_eth_dev *dev,
7970          enum rte_eth_tunnel_type l2_tunnel_type)
7971 {
7972         int ret = 0;
7973
7974         switch (l2_tunnel_type) {
7975         case RTE_L2_TUNNEL_TYPE_E_TAG:
7976                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7977                 break;
7978         default:
7979                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7980                 ret = -EINVAL;
7981                 break;
7982         }
7983
7984         return ret;
7985 }
7986
7987 /* Enable/disable l2 tunnel offload functions */
7988 static int
7989 ixgbe_dev_l2_tunnel_offload_set
7990         (struct rte_eth_dev *dev,
7991          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7992          uint32_t mask,
7993          uint8_t en)
7994 {
7995         int ret = 0;
7996
7997         if (l2_tunnel == NULL)
7998                 return -EINVAL;
7999
8000         ret = -EINVAL;
8001         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8002                 if (en)
8003                         ret = ixgbe_dev_l2_tunnel_enable(
8004                                 dev,
8005                                 l2_tunnel->l2_tunnel_type);
8006                 else
8007                         ret = ixgbe_dev_l2_tunnel_disable(
8008                                 dev,
8009                                 l2_tunnel->l2_tunnel_type);
8010         }
8011
8012         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8013                 if (en)
8014                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8015                                 dev,
8016                                 l2_tunnel);
8017                 else
8018                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8019                                 dev,
8020                                 l2_tunnel);
8021         }
8022
8023         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8024                 if (en)
8025                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8026                                 dev,
8027                                 l2_tunnel->l2_tunnel_type);
8028                 else
8029                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8030                                 dev,
8031                                 l2_tunnel->l2_tunnel_type);
8032         }
8033
8034         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8035                 if (en)
8036                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8037                                 dev,
8038                                 l2_tunnel->l2_tunnel_type);
8039                 else
8040                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8041                                 dev,
8042                                 l2_tunnel->l2_tunnel_type);
8043         }
8044
8045         return ret;
8046 }
8047
8048 static int
8049 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8050                         uint16_t port)
8051 {
8052         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8053         IXGBE_WRITE_FLUSH(hw);
8054
8055         return 0;
8056 }
8057
8058 /* There's only one register for VxLAN UDP port.
8059  * So, we cannot add several ports. Will update it.
8060  */
8061 static int
8062 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8063                      uint16_t port)
8064 {
8065         if (port == 0) {
8066                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8067                 return -EINVAL;
8068         }
8069
8070         return ixgbe_update_vxlan_port(hw, port);
8071 }
8072
8073 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8074  * UDP port, it must have a value.
8075  * So, will reset it to the original value 0.
8076  */
8077 static int
8078 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8079                      uint16_t port)
8080 {
8081         uint16_t cur_port;
8082
8083         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8084
8085         if (cur_port != port) {
8086                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8087                 return -EINVAL;
8088         }
8089
8090         return ixgbe_update_vxlan_port(hw, 0);
8091 }
8092
8093 /* Add UDP tunneling port */
8094 static int
8095 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8096                               struct rte_eth_udp_tunnel *udp_tunnel)
8097 {
8098         int ret = 0;
8099         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8100
8101         if (hw->mac.type != ixgbe_mac_X550 &&
8102             hw->mac.type != ixgbe_mac_X550EM_x &&
8103             hw->mac.type != ixgbe_mac_X550EM_a) {
8104                 return -ENOTSUP;
8105         }
8106
8107         if (udp_tunnel == NULL)
8108                 return -EINVAL;
8109
8110         switch (udp_tunnel->prot_type) {
8111         case RTE_TUNNEL_TYPE_VXLAN:
8112                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8113                 break;
8114
8115         case RTE_TUNNEL_TYPE_GENEVE:
8116         case RTE_TUNNEL_TYPE_TEREDO:
8117                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8118                 ret = -EINVAL;
8119                 break;
8120
8121         default:
8122                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8123                 ret = -EINVAL;
8124                 break;
8125         }
8126
8127         return ret;
8128 }
8129
8130 /* Remove UDP tunneling port */
8131 static int
8132 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8133                               struct rte_eth_udp_tunnel *udp_tunnel)
8134 {
8135         int ret = 0;
8136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8137
8138         if (hw->mac.type != ixgbe_mac_X550 &&
8139             hw->mac.type != ixgbe_mac_X550EM_x &&
8140             hw->mac.type != ixgbe_mac_X550EM_a) {
8141                 return -ENOTSUP;
8142         }
8143
8144         if (udp_tunnel == NULL)
8145                 return -EINVAL;
8146
8147         switch (udp_tunnel->prot_type) {
8148         case RTE_TUNNEL_TYPE_VXLAN:
8149                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8150                 break;
8151         case RTE_TUNNEL_TYPE_GENEVE:
8152         case RTE_TUNNEL_TYPE_TEREDO:
8153                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8154                 ret = -EINVAL;
8155                 break;
8156         default:
8157                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8158                 ret = -EINVAL;
8159                 break;
8160         }
8161
8162         return ret;
8163 }
8164
8165 static void
8166 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8167 {
8168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8169
8170         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8171 }
8172
8173 static void
8174 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8175 {
8176         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8177
8178         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8179 }
8180
8181 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8182 {
8183         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8184         u32 in_msg = 0;
8185
8186         /* peek the message first */
8187         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8188
8189         /* PF reset VF event */
8190         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8191                 /* dummy mbx read to ack pf */
8192                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8193                         return;
8194                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8195                                               NULL);
8196         }
8197 }
8198
8199 static int
8200 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8201 {
8202         uint32_t eicr;
8203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8204         struct ixgbe_interrupt *intr =
8205                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8206         ixgbevf_intr_disable(hw);
8207
8208         /* read-on-clear nic registers here */
8209         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8210         intr->flags = 0;
8211
8212         /* only one misc vector supported - mailbox */
8213         eicr &= IXGBE_VTEICR_MASK;
8214         if (eicr == IXGBE_MISC_VEC_ID)
8215                 intr->flags |= IXGBE_FLAG_MAILBOX;
8216
8217         return 0;
8218 }
8219
8220 static int
8221 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8222 {
8223         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8224         struct ixgbe_interrupt *intr =
8225                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8226
8227         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8228                 ixgbevf_mbx_process(dev);
8229                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8230         }
8231
8232         ixgbevf_intr_enable(hw);
8233
8234         return 0;
8235 }
8236
8237 static void
8238 ixgbevf_dev_interrupt_handler(void *param)
8239 {
8240         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8241
8242         ixgbevf_dev_interrupt_get_status(dev);
8243         ixgbevf_dev_interrupt_action(dev);
8244 }
8245
8246 /**
8247  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8248  *  @hw: pointer to hardware structure
8249  *
8250  *  Stops the transmit data path and waits for the HW to internally empty
8251  *  the Tx security block
8252  **/
8253 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8254 {
8255 #define IXGBE_MAX_SECTX_POLL 40
8256
8257         int i;
8258         int sectxreg;
8259
8260         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8261         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8262         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8263         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8264                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8265                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8266                         break;
8267                 /* Use interrupt-safe sleep just in case */
8268                 usec_delay(1000);
8269         }
8270
8271         /* For informational purposes only */
8272         if (i >= IXGBE_MAX_SECTX_POLL)
8273                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8274                          "path fully disabled.  Continuing with init.");
8275
8276         return IXGBE_SUCCESS;
8277 }
8278
8279 /**
8280  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8281  *  @hw: pointer to hardware structure
8282  *
8283  *  Enables the transmit data path.
8284  **/
8285 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8286 {
8287         uint32_t sectxreg;
8288
8289         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8290         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8291         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8292         IXGBE_WRITE_FLUSH(hw);
8293
8294         return IXGBE_SUCCESS;
8295 }
8296
8297 /* restore n-tuple filter */
8298 static inline void
8299 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8300 {
8301         struct ixgbe_filter_info *filter_info =
8302                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8303         struct ixgbe_5tuple_filter *node;
8304
8305         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8306                 ixgbe_inject_5tuple_filter(dev, node);
8307         }
8308 }
8309
8310 /* restore ethernet type filter */
8311 static inline void
8312 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8313 {
8314         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8315         struct ixgbe_filter_info *filter_info =
8316                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8317         int i;
8318
8319         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8320                 if (filter_info->ethertype_mask & (1 << i)) {
8321                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8322                                         filter_info->ethertype_filters[i].etqf);
8323                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8324                                         filter_info->ethertype_filters[i].etqs);
8325                         IXGBE_WRITE_FLUSH(hw);
8326                 }
8327         }
8328 }
8329
8330 /* restore SYN filter */
8331 static inline void
8332 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8333 {
8334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8335         struct ixgbe_filter_info *filter_info =
8336                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8337         uint32_t synqf;
8338
8339         synqf = filter_info->syn_info;
8340
8341         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8342                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8343                 IXGBE_WRITE_FLUSH(hw);
8344         }
8345 }
8346
8347 /* restore L2 tunnel filter */
8348 static inline void
8349 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8350 {
8351         struct ixgbe_l2_tn_info *l2_tn_info =
8352                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8353         struct ixgbe_l2_tn_filter *node;
8354         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8355
8356         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8357                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8358                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8359                 l2_tn_conf.pool           = node->pool;
8360                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8361         }
8362 }
8363
8364 /* restore rss filter */
8365 static inline void
8366 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8367 {
8368         struct ixgbe_filter_info *filter_info =
8369                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8370
8371         if (filter_info->rss_info.conf.queue_num)
8372                 ixgbe_config_rss_filter(dev,
8373                         &filter_info->rss_info, TRUE);
8374 }
8375
8376 static int
8377 ixgbe_filter_restore(struct rte_eth_dev *dev)
8378 {
8379         ixgbe_ntuple_filter_restore(dev);
8380         ixgbe_ethertype_filter_restore(dev);
8381         ixgbe_syn_filter_restore(dev);
8382         ixgbe_fdir_filter_restore(dev);
8383         ixgbe_l2_tn_filter_restore(dev);
8384         ixgbe_rss_filter_restore(dev);
8385
8386         return 0;
8387 }
8388
8389 static void
8390 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8391 {
8392         struct ixgbe_l2_tn_info *l2_tn_info =
8393                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8394         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8395
8396         if (l2_tn_info->e_tag_en)
8397                 (void)ixgbe_e_tag_enable(hw);
8398
8399         if (l2_tn_info->e_tag_fwd_en)
8400                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8401
8402         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8403 }
8404
8405 /* remove all the n-tuple filters */
8406 void
8407 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8408 {
8409         struct ixgbe_filter_info *filter_info =
8410                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8411         struct ixgbe_5tuple_filter *p_5tuple;
8412
8413         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8414                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8415 }
8416
8417 /* remove all the ether type filters */
8418 void
8419 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8420 {
8421         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8422         struct ixgbe_filter_info *filter_info =
8423                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8424         int i;
8425
8426         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8427                 if (filter_info->ethertype_mask & (1 << i) &&
8428                     !filter_info->ethertype_filters[i].conf) {
8429                         (void)ixgbe_ethertype_filter_remove(filter_info,
8430                                                             (uint8_t)i);
8431                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8432                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8433                         IXGBE_WRITE_FLUSH(hw);
8434                 }
8435         }
8436 }
8437
8438 /* remove the SYN filter */
8439 void
8440 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8441 {
8442         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8443         struct ixgbe_filter_info *filter_info =
8444                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8445
8446         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8447                 filter_info->syn_info = 0;
8448
8449                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8450                 IXGBE_WRITE_FLUSH(hw);
8451         }
8452 }
8453
8454 /* remove all the L2 tunnel filters */
8455 int
8456 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8457 {
8458         struct ixgbe_l2_tn_info *l2_tn_info =
8459                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8460         struct ixgbe_l2_tn_filter *l2_tn_filter;
8461         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8462         int ret = 0;
8463
8464         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8465                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8466                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8467                 l2_tn_conf.pool           = l2_tn_filter->pool;
8468                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8469                 if (ret < 0)
8470                         return ret;
8471         }
8472
8473         return 0;
8474 }
8475
8476 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8477 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8478 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8479 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8480 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8481 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8482
8483 RTE_INIT(ixgbe_init_log);
8484 static void
8485 ixgbe_init_log(void)
8486 {
8487         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8488         if (ixgbe_logtype_init >= 0)
8489                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8490         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8491         if (ixgbe_logtype_driver >= 0)
8492                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8493 }