drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 /*
  77  * High threshold controlling when to start sending XOFF frames. Must be at
  78  * least 8 bytes less than receive packet buffer size. This value is in units
  79  * of 1024 bytes.
  80  */
  81 #define IXGBE_FC_HI    0x80
  82
  83 /*
  84  * Low threshold controlling when to start sending XON frames. This value is
  85  * in units of 1024 bytes.
  86  */
  87 #define IXGBE_FC_LO    0x40
  88
  89 /* Default minimum inter-interrupt interval for EITR configuration */
  90 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  91
  92 /* Timer value included in XOFF frames. */
  93 #define IXGBE_FC_PAUSE 0x680
  94
  95 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  96 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  97 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  98
  99 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 100 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 101 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 102
 103 /*
 104  *  Default values for RX/TX configuration
 105  */
 106 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 107 #define IXGBE_DEFAULT_RX_PTHRESH      8
 108 #define IXGBE_DEFAULT_RX_HTHRESH      8
 109 #define IXGBE_DEFAULT_RX_WTHRESH      0
 110
 111 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 112 #define IXGBE_DEFAULT_TX_PTHRESH      32
 113 #define IXGBE_DEFAULT_TX_HTHRESH      0
 114 #define IXGBE_DEFAULT_TX_WTHRESH      0
 115 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 116
 117 /* Bit shift and mask */
 118 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 119 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 120 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 121 #define IXGBE_8_BIT_MASK   UINT8_MAX
 122
 123 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 124
 125 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 126
 127 #define IXGBE_HKEY_MAX_INDEX 10
 128
 129 /* Additional timesync values. */
 130 #define NSEC_PER_SEC             1000000000L
 131 #define IXGBE_INCVAL_10GB        0x66666666
 132 #define IXGBE_INCVAL_1GB         0x40000000
 133 #define IXGBE_INCVAL_100         0x50000000
 134 #define IXGBE_INCVAL_SHIFT_10GB  28
 135 #define IXGBE_INCVAL_SHIFT_1GB   24
 136 #define IXGBE_INCVAL_SHIFT_100   21
 137 #define IXGBE_INCVAL_SHIFT_82599 7
 138 #define IXGBE_INCPER_SHIFT_82599 24
 139
 140 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 141
 142 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 143 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 144 #define DEFAULT_ETAG_ETYPE                     0x893f
 145 #define IXGBE_ETAG_ETYPE                       0x00005084
 146 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 147 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 148 #define IXGBE_RAH_ADTYPE                       0x40000000
 149 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 150 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 151 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 152 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 153 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 154 #define IXGBE_VTEICR_MASK                      0x07
 155
 156 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 157 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 158
 159 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 160 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 161 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 167 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 177                                 int wait_to_complete);
 178 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 179                                 struct rte_eth_stats *stats);
 180 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_xstat *xstats, unsigned n);
 182 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 183                                   struct rte_eth_xstat *xstats, unsigned n);
 184 static int
 185 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 186                 uint64_t *values, unsigned int n);
 187 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 188 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 189 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 190         struct rte_eth_xstat_name *xstats_names,
 191         unsigned int size);
 192 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 193         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 194 static int ixgbe_dev_xstats_get_names_by_id(
 195         struct rte_eth_dev *dev,
 196         struct rte_eth_xstat_name *xstats_names,
 197         const uint64_t *ids,
 198         unsigned int limit);
 199 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 200                                              uint16_t queue_id,
 201                                              uint8_t stat_idx,
 202                                              uint8_t is_rx);
 203 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 204                                  size_t fw_size);
 205 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 206                                struct rte_eth_dev_info *dev_info);
 207 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 208 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 209                                  struct rte_eth_dev_info *dev_info);
 210 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 211
 212 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 213                 uint16_t vlan_id, int on);
 214 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 215                                enum rte_vlan_type vlan_type,
 216                                uint16_t tpid_id);
 217 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 218                 uint16_t queue, bool on);
 219 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 220                 int on);
 221 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 222 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 223 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 225 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 226
 227 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 229 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_fc_conf *fc_conf);
 231 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 232                                struct rte_eth_fc_conf *fc_conf);
 233 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 234                 struct rte_eth_pfc_conf *pfc_conf);
 235 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 236                         struct rte_eth_rss_reta_entry64 *reta_conf,
 237                         uint16_t reta_size);
 238 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 239                         struct rte_eth_rss_reta_entry64 *reta_conf,
 240                         uint16_t reta_size);
 241 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 242 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 247                                       struct rte_intr_handle *handle);
 248 static void ixgbe_dev_interrupt_handler(void *param);
 249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 250 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 251                          uint32_t index, uint32_t pool);
 252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 254                                            struct ether_addr *mac_addr);
 255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 256 static bool is_device_supported(struct rte_eth_dev *dev,
 257                                 struct rte_pci_driver *drv);
 258
 259 /* For Virtual Function support */
 260 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 261 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 262 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 263 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 264 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 265                                    int wait_to_complete);
 266 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 267 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 268 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 269 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 270 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 271                 struct rte_eth_stats *stats);
 272 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 273 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 274                 uint16_t vlan_id, int on);
 275 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 276                 uint16_t queue, int on);
 277 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 278 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 279 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 280                                             uint16_t queue_id);
 281 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 282                                              uint16_t queue_id);
 283 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 284                                  uint8_t queue, uint8_t msix_vector);
 285 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 286 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 287 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 288
 289 /* For Eth VMDQ APIs support */
 290 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 291                 ether_addr * mac_addr, uint8_t on);
 292 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 293 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 294                 struct rte_eth_mirror_conf *mirror_conf,
 295                 uint8_t rule_id, uint8_t on);
 296 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 297                 uint8_t rule_id);
 298 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 299                                           uint16_t queue_id);
 300 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 301                                            uint16_t queue_id);
 302 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 303                                uint8_t queue, uint8_t msix_vector);
 304 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 305
 306 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 307                                 struct ether_addr *mac_addr,
 308                                 uint32_t index, uint32_t pool);
 309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 311                                              struct ether_addr *mac_addr);
 312 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 313                         struct rte_eth_syn_filter *filter);
 314 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 315                         enum rte_filter_op filter_op,
 316                         void *arg);
 317 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 318                         struct ixgbe_5tuple_filter *filter);
 319 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ntuple_filter *filter);
 326 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 327                                 enum rte_filter_op filter_op,
 328                                 void *arg);
 329 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 330                         struct rte_eth_ethertype_filter *filter);
 331 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 332                      enum rte_filter_type filter_type,
 333                      enum rte_filter_op filter_op,
 334                      void *arg);
 335 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 336
 337 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 338                                       struct ether_addr *mc_addr_set,
 339                                       uint32_t nb_mc_addr);
 340 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 341                                    struct rte_eth_dcb_info *dcb_info);
 342
 343 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 344 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 345                             struct rte_dev_reg_info *regs);
 346 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 347 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 348                                 struct rte_dev_eeprom_info *eeprom);
 349 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351
 352 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 353 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 354                                 struct rte_dev_reg_info *regs);
 355
 356 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 357 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 358 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 359                                             struct timespec *timestamp,
 360                                             uint32_t flags);
 361 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 362                                             struct timespec *timestamp);
 363 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 364 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 365                                    struct timespec *timestamp);
 366 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 367                                    const struct timespec *timestamp);
 368 static void ixgbevf_dev_interrupt_handler(void *param);
 369
 370 static int ixgbe_dev_l2_tunnel_eth_type_conf
 371         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 372 static int ixgbe_dev_l2_tunnel_offload_set
 373         (struct rte_eth_dev *dev,
 374          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 375          uint32_t mask,
 376          uint8_t en);
 377 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 378                                              enum rte_filter_op filter_op,
 379                                              void *arg);
 380
 381 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 382                                          struct rte_eth_udp_tunnel *udp_tunnel);
 383 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 384                                          struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 386 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 387
 388 /*
 389  * Define VF Stats MACRO for Non "cleared on read" register
 390  */
 391 #define UPDATE_VF_STAT(reg, last, cur)                          \
 392 {                                                               \
 393         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 394         cur += (latest - last) & UINT_MAX;                      \
 395         last = latest;                                          \
 396 }
 397
 398 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 399 {                                                                \
 400         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 401         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 402         u64 latest = ((new_msb << 32) | new_lsb);                \
 403         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 404         last = latest;                                           \
 405 }
 406
 407 #define IXGBE_SET_HWSTRIP(h, q) do {\
 408                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 409                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 410                 (h)->bitmap[idx] |= 1 << bit;\
 411         } while (0)
 412
 413 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (h)->bitmap[idx] &= ~(1 << bit);\
 417         } while (0)
 418
 419 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 420                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 421                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 422                 (r) = (h)->bitmap[idx] >> bit & 1;\
 423         } while (0)
 424
 425 /*
 426  * The set of PCI devices this driver supports
 427  */
 428 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 482 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 484 #endif
 485         { .vendor_id = 0, /* sentinel */ },
 486 };
 487
 488 /*
 489  * The set of PCI devices this driver supports (for 82599 VF)
 490  */
 491 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 502         { .vendor_id = 0, /* sentinel */ },
 503 };
 504
 505 static const struct rte_eth_desc_lim rx_desc_lim = {
 506         .nb_max = IXGBE_MAX_RING_DESC,
 507         .nb_min = IXGBE_MIN_RING_DESC,
 508         .nb_align = IXGBE_RXD_ALIGN,
 509 };
 510
 511 static const struct rte_eth_desc_lim tx_desc_lim = {
 512         .nb_max = IXGBE_MAX_RING_DESC,
 513         .nb_min = IXGBE_MIN_RING_DESC,
 514         .nb_align = IXGBE_TXD_ALIGN,
 515         .nb_seg_max = IXGBE_TX_MAX_SEG,
 516         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 517 };
 518
 519 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 520         .dev_configure        = ixgbe_dev_configure,
 521         .dev_start            = ixgbe_dev_start,
 522         .dev_stop             = ixgbe_dev_stop,
 523         .dev_set_link_up    = ixgbe_dev_set_link_up,
 524         .dev_set_link_down  = ixgbe_dev_set_link_down,
 525         .dev_close            = ixgbe_dev_close,
 526         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 527         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 528         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 529         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 530         .link_update          = ixgbe_dev_link_update,
 531         .stats_get            = ixgbe_dev_stats_get,
 532         .xstats_get           = ixgbe_dev_xstats_get,
 533         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 534         .stats_reset          = ixgbe_dev_stats_reset,
 535         .xstats_reset         = ixgbe_dev_xstats_reset,
 536         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 537         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 538         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 539         .fw_version_get       = ixgbe_fw_version_get,
 540         .dev_infos_get        = ixgbe_dev_info_get,
 541         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 542         .mtu_set              = ixgbe_dev_mtu_set,
 543         .vlan_filter_set      = ixgbe_vlan_filter_set,
 544         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 545         .vlan_offload_set     = ixgbe_vlan_offload_set,
 546         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 547         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 548         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 549         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 550         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 551         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 552         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 553         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 554         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 555         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 556         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 557         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 558         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 559         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 560         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 561         .dev_led_on           = ixgbe_dev_led_on,
 562         .dev_led_off          = ixgbe_dev_led_off,
 563         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 564         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 565         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 566         .mac_addr_add         = ixgbe_add_rar,
 567         .mac_addr_remove      = ixgbe_remove_rar,
 568         .mac_addr_set         = ixgbe_set_default_mac_addr,
 569         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 570         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 571         .mirror_rule_set      = ixgbe_mirror_rule_set,
 572         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 573         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 574         .reta_update          = ixgbe_dev_rss_reta_update,
 575         .reta_query           = ixgbe_dev_rss_reta_query,
 576         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 577         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 578         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 579         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 580         .rxq_info_get         = ixgbe_rxq_info_get,
 581         .txq_info_get         = ixgbe_txq_info_get,
 582         .timesync_enable      = ixgbe_timesync_enable,
 583         .timesync_disable     = ixgbe_timesync_disable,
 584         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 585         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 586         .get_reg              = ixgbe_get_regs,
 587         .get_eeprom_length    = ixgbe_get_eeprom_length,
 588         .get_eeprom           = ixgbe_get_eeprom,
 589         .set_eeprom           = ixgbe_set_eeprom,
 590         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 591         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 592         .timesync_read_time   = ixgbe_timesync_read_time,
 593         .timesync_write_time  = ixgbe_timesync_write_time,
 594         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 595         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 596         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 597         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 598         .tm_ops_get           = ixgbe_tm_ops_get,
 599 };
 600
 601 /*
 602  * dev_ops for virtual function, bare necessities for basic vf
 603  * operation have been implemented
 604  */
 605 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 606         .dev_configure        = ixgbevf_dev_configure,
 607         .dev_start            = ixgbevf_dev_start,
 608         .dev_stop             = ixgbevf_dev_stop,
 609         .link_update          = ixgbevf_dev_link_update,
 610         .stats_get            = ixgbevf_dev_stats_get,
 611         .xstats_get           = ixgbevf_dev_xstats_get,
 612         .stats_reset          = ixgbevf_dev_stats_reset,
 613         .xstats_reset         = ixgbevf_dev_stats_reset,
 614         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 615         .dev_close            = ixgbevf_dev_close,
 616         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 617         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 618         .dev_infos_get        = ixgbevf_dev_info_get,
 619         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 620         .mtu_set              = ixgbevf_dev_set_mtu,
 621         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 622         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 623         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 624         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 625         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 626         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 627         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 628         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 629         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 630         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 631         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 632         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 633         .mac_addr_add         = ixgbevf_add_mac_addr,
 634         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 635         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 636         .rxq_info_get         = ixgbe_rxq_info_get,
 637         .txq_info_get         = ixgbe_txq_info_get,
 638         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 639         .get_reg              = ixgbevf_get_regs,
 640         .reta_update          = ixgbe_dev_rss_reta_update,
 641         .reta_query           = ixgbe_dev_rss_reta_query,
 642         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 643         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 644 };
 645
 646 /* store statistics names and its offset in stats structure */
 647 struct rte_ixgbe_xstats_name_off {
 648         char name[RTE_ETH_XSTATS_NAME_SIZE];
 649         unsigned offset;
 650 };
 651
 652 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 653         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 654         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 655         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 656         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 657         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 658         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 659         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 660         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 661         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 662         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 663         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 664         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 665         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 666         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 667         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 668                 prc1023)},
 669         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 670                 prc1522)},
 671         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 672         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 673         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 674         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 675         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 676         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 677         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 678         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 679         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 680         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 681         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 682         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 683         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 684         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 685         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 686         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 687         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 688                 ptc1023)},
 689         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 690                 ptc1522)},
 691         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 692         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 693         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 694         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 695
 696         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 697                 fdirustat_add)},
 698         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 699                 fdirustat_remove)},
 700         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 701                 fdirfstat_fadd)},
 702         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 703                 fdirfstat_fremove)},
 704         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirmatch)},
 706         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 707                 fdirmiss)},
 708
 709         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 710         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 711         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 712                 fclast)},
 713         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 714         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 715         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 716         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 717         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 718                 fcoe_noddp)},
 719         {"rx_fcoe_no_direct_data_placement_ext_buff",
 720                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 721
 722         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 723                 lxontxc)},
 724         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 725                 lxonrxc)},
 726         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxofftxc)},
 728         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 729                 lxoffrxc)},
 730         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 731 };
 732
 733 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 734                            sizeof(rte_ixgbe_stats_strings[0]))
 735
 736 /* MACsec statistics */
 737 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 738         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 739                 out_pkts_untagged)},
 740         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 741                 out_pkts_encrypted)},
 742         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 743                 out_pkts_protected)},
 744         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 745                 out_octets_encrypted)},
 746         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 747                 out_octets_protected)},
 748         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_untagged)},
 750         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_badtag)},
 752         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_nosci)},
 754         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_unknownsci)},
 756         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 757                 in_octets_decrypted)},
 758         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 759                 in_octets_validated)},
 760         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_unchecked)},
 762         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_delayed)},
 764         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_late)},
 766         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_ok)},
 768         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_invalid)},
 770         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_notvalid)},
 772         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_unusedsa)},
 774         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_notusingsa)},
 776 };
 777
 778 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 779                            sizeof(rte_ixgbe_macsec_strings[0]))
 780
 781 /* Per-queue statistics */
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 783         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 784         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 785         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 786         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 787 };
 788
 789 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 790                            sizeof(rte_ixgbe_rxq_strings[0]))
 791 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 792
 793 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 794         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 795         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 796         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 797                 pxon2offc)},
 798 };
 799
 800 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 801                            sizeof(rte_ixgbe_txq_strings[0]))
 802 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 803
 804 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 805         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 806 };
 807
 808 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 809                 sizeof(rte_ixgbevf_stats_strings[0]))
 810
 811 /**
 812  * Atomically reads the link status information from global
 813  * structure rte_eth_dev.
 814  *
 815  * @param dev
 816  *   - Pointer to the structure rte_eth_dev to read from.
 817  *   - Pointer to the buffer to be saved with the link status.
 818  *
 819  * @return
 820  *   - On success, zero.
 821  *   - On failure, negative value.
 822  */
 823 static inline int
 824 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 825                                 struct rte_eth_link *link)
 826 {
 827         struct rte_eth_link *dst = link;
 828         struct rte_eth_link *src = &(dev->data->dev_link);
 829
 830         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 831                                         *(uint64_t *)src) == 0)
 832                 return -1;
 833
 834         return 0;
 835 }
 836
 837 /**
 838  * Atomically writes the link status information into global
 839  * structure rte_eth_dev.
 840  *
 841  * @param dev
 842  *   - Pointer to the structure rte_eth_dev to read from.
 843  *   - Pointer to the buffer to be saved with the link status.
 844  *
 845  * @return
 846  *   - On success, zero.
 847  *   - On failure, negative value.
 848  */
 849 static inline int
 850 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 851                                 struct rte_eth_link *link)
 852 {
 853         struct rte_eth_link *dst = &(dev->data->dev_link);
 854         struct rte_eth_link *src = link;
 855
 856         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 857                                         *(uint64_t *)src) == 0)
 858                 return -1;
 859
 860         return 0;
 861 }
 862
 863 /*
 864  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 865  */
 866 static inline int
 867 ixgbe_is_sfp(struct ixgbe_hw *hw)
 868 {
 869         switch (hw->phy.type) {
 870         case ixgbe_phy_sfp_avago:
 871         case ixgbe_phy_sfp_ftl:
 872         case ixgbe_phy_sfp_intel:
 873         case ixgbe_phy_sfp_unknown:
 874         case ixgbe_phy_sfp_passive_tyco:
 875         case ixgbe_phy_sfp_passive_unknown:
 876                 return 1;
 877         default:
 878                 return 0;
 879         }
 880 }
 881
 882 static inline int32_t
 883 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 884 {
 885         uint32_t ctrl_ext;
 886         int32_t status;
 887
 888         status = ixgbe_reset_hw(hw);
 889
 890         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 891         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 892         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 893         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 894         IXGBE_WRITE_FLUSH(hw);
 895
 896         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 897                 status = IXGBE_SUCCESS;
 898         return status;
 899 }
 900
 901 static inline void
 902 ixgbe_enable_intr(struct rte_eth_dev *dev)
 903 {
 904         struct ixgbe_interrupt *intr =
 905                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 906         struct ixgbe_hw *hw =
 907                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 908
 909         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 910         IXGBE_WRITE_FLUSH(hw);
 911 }
 912
 913 /*
 914  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 915  */
 916 static void
 917 ixgbe_disable_intr(struct ixgbe_hw *hw)
 918 {
 919         PMD_INIT_FUNC_TRACE();
 920
 921         if (hw->mac.type == ixgbe_mac_82598EB) {
 922                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 923         } else {
 924                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 927         }
 928         IXGBE_WRITE_FLUSH(hw);
 929 }
 930
 931 /*
 932  * This function resets queue statistics mapping registers.
 933  * From Niantic datasheet, Initialization of Statistics section:
 934  * "...if software requires the queue counters, the RQSMR and TQSM registers
 935  * must be re-programmed following a device reset.
 936  */
 937 static void
 938 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 939 {
 940         uint32_t i;
 941
 942         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 943                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 944                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 945         }
 946 }
 947
 948
 949 static int
 950 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 951                                   uint16_t queue_id,
 952                                   uint8_t stat_idx,
 953                                   uint8_t is_rx)
 954 {
 955 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 956 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 957 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 958
 959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 960         struct ixgbe_stat_mapping_registers *stat_mappings =
 961                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 962         uint32_t qsmr_mask = 0;
 963         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 964         uint32_t q_map;
 965         uint8_t n, offset;
 966
 967         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 968                 (hw->mac.type != ixgbe_mac_X540) &&
 969                 (hw->mac.type != ixgbe_mac_X550) &&
 970                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 971                 (hw->mac.type != ixgbe_mac_X550EM_a))
 972                 return -ENOSYS;
 973
 974         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 975                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 976                      queue_id, stat_idx);
 977
 978         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 979         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 980                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 981                 return -EIO;
 982         }
 983         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 984
 985         /* Now clear any previous stat_idx set */
 986         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 987         if (!is_rx)
 988                 stat_mappings->tqsm[n] &= ~clearing_mask;
 989         else
 990                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 991
 992         q_map = (uint32_t)stat_idx;
 993         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 994         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 995         if (!is_rx)
 996                 stat_mappings->tqsm[n] |= qsmr_mask;
 997         else
 998                 stat_mappings->rqsmr[n] |= qsmr_mask;
 999
1000         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1001                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1002                      queue_id, stat_idx);
1003         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1004                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1005
1006         /* Now write the mapping in the appropriate register */
1007         if (is_rx) {
1008                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1009                              stat_mappings->rqsmr[n], n);
1010                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1011         } else {
1012                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1013                              stat_mappings->tqsm[n], n);
1014                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1015         }
1016         return 0;
1017 }
1018
1019 static void
1020 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1021 {
1022         struct ixgbe_stat_mapping_registers *stat_mappings =
1023                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1025         int i;
1026
1027         /* write whatever was in stat mapping table to the NIC */
1028         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1029                 /* rx */
1030                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1031
1032                 /* tx */
1033                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1034         }
1035 }
1036
1037 static void
1038 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1039 {
1040         uint8_t i;
1041         struct ixgbe_dcb_tc_config *tc;
1042         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1043
1044         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1045         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1046         for (i = 0; i < dcb_max_tc; i++) {
1047                 tc = &dcb_config->tc_config[i];
1048                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1049                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1050                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1051                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1052                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1053                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1054                 tc->pfc = ixgbe_dcb_pfc_disabled;
1055         }
1056
1057         /* Initialize default user to priority mapping, UPx->TC0 */
1058         tc = &dcb_config->tc_config[0];
1059         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1060         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1061         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1062                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1063                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1064         }
1065         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1066         dcb_config->pfc_mode_enable = false;
1067         dcb_config->vt_mode = true;
1068         dcb_config->round_robin_enable = false;
1069         /* support all DCB capabilities in 82599 */
1070         dcb_config->support.capabilities = 0xFF;
1071
1072         /*we only support 4 Tcs for X540, X550 */
1073         if (hw->mac.type == ixgbe_mac_X540 ||
1074                 hw->mac.type == ixgbe_mac_X550 ||
1075                 hw->mac.type == ixgbe_mac_X550EM_x ||
1076                 hw->mac.type == ixgbe_mac_X550EM_a) {
1077                 dcb_config->num_tcs.pg_tcs = 4;
1078                 dcb_config->num_tcs.pfc_tcs = 4;
1079         }
1080 }
1081
1082 /*
1083  * Ensure that all locks are released before first NVM or PHY access
1084  */
1085 static void
1086 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1087 {
1088         uint16_t mask;
1089
1090         /*
1091          * Phy lock should not fail in this early stage. If this is the case,
1092          * it is due to an improper exit of the application.
1093          * So force the release of the faulty lock. Release of common lock
1094          * is done automatically by swfw_sync function.
1095          */
1096         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1097         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1098                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1099         }
1100         ixgbe_release_swfw_semaphore(hw, mask);
1101
1102         /*
1103          * These ones are more tricky since they are common to all ports; but
1104          * swfw_sync retries last long enough (1s) to be almost sure that if
1105          * lock can not be taken it is due to an improper lock of the
1106          * semaphore.
1107          */
1108         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1109         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1111         }
1112         ixgbe_release_swfw_semaphore(hw, mask);
1113 }
1114
1115 /*
1116  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1117  * It returns 0 on success.
1118  */
1119 static int
1120 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1121 {
1122         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1123         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1124         struct ixgbe_hw *hw =
1125                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1126         struct ixgbe_vfta *shadow_vfta =
1127                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1128         struct ixgbe_hwstrip *hwstrip =
1129                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1130         struct ixgbe_dcb_config *dcb_config =
1131                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1132         struct ixgbe_filter_info *filter_info =
1133                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1134         struct ixgbe_bw_conf *bw_conf =
1135                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1136         uint32_t ctrl_ext;
1137         uint16_t csum;
1138         int diag, i;
1139
1140         PMD_INIT_FUNC_TRACE();
1141
1142         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1143         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1144         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1145         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1146
1147         /*
1148          * For secondary processes, we don't initialise any further as primary
1149          * has already done this work. Only check we don't need a different
1150          * RX and TX function.
1151          */
1152         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1153                 struct ixgbe_tx_queue *txq;
1154                 /* TX queue function in primary, set by last queue initialized
1155                  * Tx queue may not initialized by primary process
1156                  */
1157                 if (eth_dev->data->tx_queues) {
1158                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1159                         ixgbe_set_tx_function(eth_dev, txq);
1160                 } else {
1161                         /* Use default TX function if we get here */
1162                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1163                                      "Using default TX function.");
1164                 }
1165
1166                 ixgbe_set_rx_function(eth_dev);
1167
1168                 return 0;
1169         }
1170
1171         rte_eth_copy_pci_info(eth_dev, pci_dev);
1172         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1173
1174         /* Vendor and Device ID need to be set before init of shared code */
1175         hw->device_id = pci_dev->id.device_id;
1176         hw->vendor_id = pci_dev->id.vendor_id;
1177         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1178         hw->allow_unsupported_sfp = 1;
1179
1180         /* Initialize the shared code (base driver) */
1181 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1182         diag = ixgbe_bypass_init_shared_code(hw);
1183 #else
1184         diag = ixgbe_init_shared_code(hw);
1185 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1186
1187         if (diag != IXGBE_SUCCESS) {
1188                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1189                 return -EIO;
1190         }
1191
1192         /* pick up the PCI bus settings for reporting later */
1193         ixgbe_get_bus_info(hw);
1194
1195         /* Unlock any pending hardware semaphore */
1196         ixgbe_swfw_lock_reset(hw);
1197
1198         /* Initialize DCB configuration*/
1199         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1200         ixgbe_dcb_init(hw, dcb_config);
1201         /* Get Hardware Flow Control setting */
1202         hw->fc.requested_mode = ixgbe_fc_full;
1203         hw->fc.current_mode = ixgbe_fc_full;
1204         hw->fc.pause_time = IXGBE_FC_PAUSE;
1205         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1206                 hw->fc.low_water[i] = IXGBE_FC_LO;
1207                 hw->fc.high_water[i] = IXGBE_FC_HI;
1208         }
1209         hw->fc.send_xon = 1;
1210
1211         /* Make sure we have a good EEPROM before we read from it */
1212         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1213         if (diag != IXGBE_SUCCESS) {
1214                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1215                 return -EIO;
1216         }
1217
1218 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1219         diag = ixgbe_bypass_init_hw(hw);
1220 #else
1221         diag = ixgbe_init_hw(hw);
1222 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1223
1224         /*
1225          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1226          * is called too soon after the kernel driver unbinding/binding occurs.
1227          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1228          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1229          * also called. See ixgbe_identify_phy_82599(). The reason for the
1230          * failure is not known, and only occuts when virtualisation features
1231          * are disabled in the bios. A delay of 100ms  was found to be enough by
1232          * trial-and-error, and is doubled to be safe.
1233          */
1234         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1235                 rte_delay_ms(200);
1236                 diag = ixgbe_init_hw(hw);
1237         }
1238
1239         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1240                 diag = IXGBE_SUCCESS;
1241
1242         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1243                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1244                              "LOM.  Please be aware there may be issues associated "
1245                              "with your hardware.");
1246                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1247                              "please contact your Intel or hardware representative "
1248                              "who provided you with this hardware.");
1249         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1250                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1251         if (diag) {
1252                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1253                 return -EIO;
1254         }
1255
1256         /* Reset the hw statistics */
1257         ixgbe_dev_stats_reset(eth_dev);
1258
1259         /* disable interrupt */
1260         ixgbe_disable_intr(hw);
1261
1262         /* reset mappings for queue statistics hw counters*/
1263         ixgbe_reset_qstat_mappings(hw);
1264
1265         /* Allocate memory for storing MAC addresses */
1266         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1267                                                hw->mac.num_rar_entries, 0);
1268         if (eth_dev->data->mac_addrs == NULL) {
1269                 PMD_INIT_LOG(ERR,
1270                              "Failed to allocate %u bytes needed to store "
1271                              "MAC addresses",
1272                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1273                 return -ENOMEM;
1274         }
1275         /* Copy the permanent MAC address */
1276         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1277                         &eth_dev->data->mac_addrs[0]);
1278
1279         /* Allocate memory for storing hash filter MAC addresses */
1280         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1281                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1282         if (eth_dev->data->hash_mac_addrs == NULL) {
1283                 PMD_INIT_LOG(ERR,
1284                              "Failed to allocate %d bytes needed to store MAC addresses",
1285                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1286                 return -ENOMEM;
1287         }
1288
1289         /* initialize the vfta */
1290         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1291
1292         /* initialize the hw strip bitmap*/
1293         memset(hwstrip, 0, sizeof(*hwstrip));
1294
1295         /* initialize PF if max_vfs not zero */
1296         ixgbe_pf_host_init(eth_dev);
1297
1298         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1299         /* let hardware know driver is loaded */
1300         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1301         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1302         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1303         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1304         IXGBE_WRITE_FLUSH(hw);
1305
1306         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1307                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1308                              (int) hw->mac.type, (int) hw->phy.type,
1309                              (int) hw->phy.sfp_type);
1310         else
1311                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1312                              (int) hw->mac.type, (int) hw->phy.type);
1313
1314         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1315                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1316                      pci_dev->id.device_id);
1317
1318         rte_intr_callback_register(intr_handle,
1319                                    ixgbe_dev_interrupt_handler, eth_dev);
1320
1321         /* enable uio/vfio intr/eventfd mapping */
1322         rte_intr_enable(intr_handle);
1323
1324         /* enable support intr */
1325         ixgbe_enable_intr(eth_dev);
1326
1327         /* initialize filter info */
1328         memset(filter_info, 0,
1329                sizeof(struct ixgbe_filter_info));
1330
1331         /* initialize 5tuple filter list */
1332         TAILQ_INIT(&filter_info->fivetuple_list);
1333
1334         /* initialize flow director filter list & hash */
1335         ixgbe_fdir_filter_init(eth_dev);
1336
1337         /* initialize l2 tunnel filter list & hash */
1338         ixgbe_l2_tn_filter_init(eth_dev);
1339
1340         TAILQ_INIT(&filter_ntuple_list);
1341         TAILQ_INIT(&filter_ethertype_list);
1342         TAILQ_INIT(&filter_syn_list);
1343         TAILQ_INIT(&filter_fdir_list);
1344         TAILQ_INIT(&filter_l2_tunnel_list);
1345         TAILQ_INIT(&ixgbe_flow_list);
1346
1347         /* initialize bandwidth configuration info */
1348         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1349
1350         /* initialize Traffic Manager configuration */
1351         ixgbe_tm_conf_init(eth_dev);
1352
1353         return 0;
1354 }
1355
1356 static int
1357 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1358 {
1359         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1360         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1361         struct ixgbe_hw *hw;
1362
1363         PMD_INIT_FUNC_TRACE();
1364
1365         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1366                 return -EPERM;
1367
1368         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1369
1370         if (hw->adapter_stopped == 0)
1371                 ixgbe_dev_close(eth_dev);
1372
1373         eth_dev->dev_ops = NULL;
1374         eth_dev->rx_pkt_burst = NULL;
1375         eth_dev->tx_pkt_burst = NULL;
1376
1377         /* Unlock any pending hardware semaphore */
1378         ixgbe_swfw_lock_reset(hw);
1379
1380         /* disable uio intr before callback unregister */
1381         rte_intr_disable(intr_handle);
1382         rte_intr_callback_unregister(intr_handle,
1383                                      ixgbe_dev_interrupt_handler, eth_dev);
1384
1385         /* uninitialize PF if max_vfs not zero */
1386         ixgbe_pf_host_uninit(eth_dev);
1387
1388         rte_free(eth_dev->data->mac_addrs);
1389         eth_dev->data->mac_addrs = NULL;
1390
1391         rte_free(eth_dev->data->hash_mac_addrs);
1392         eth_dev->data->hash_mac_addrs = NULL;
1393
1394         /* remove all the fdir filters & hash */
1395         ixgbe_fdir_filter_uninit(eth_dev);
1396
1397         /* remove all the L2 tunnel filters & hash */
1398         ixgbe_l2_tn_filter_uninit(eth_dev);
1399
1400         /* Remove all ntuple filters of the device */
1401         ixgbe_ntuple_filter_uninit(eth_dev);
1402
1403         /* clear all the filters list */
1404         ixgbe_filterlist_flush();
1405
1406         /* Remove all Traffic Manager configuration */
1407         ixgbe_tm_conf_uninit(eth_dev);
1408
1409         return 0;
1410 }
1411
1412 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1413 {
1414         struct ixgbe_filter_info *filter_info =
1415                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1416         struct ixgbe_5tuple_filter *p_5tuple;
1417
1418         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1419                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1420                              p_5tuple,
1421                              entries);
1422                 rte_free(p_5tuple);
1423         }
1424         memset(filter_info->fivetuple_mask, 0,
1425                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1426
1427         return 0;
1428 }
1429
1430 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1431 {
1432         struct ixgbe_hw_fdir_info *fdir_info =
1433                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1434         struct ixgbe_fdir_filter *fdir_filter;
1435
1436                 if (fdir_info->hash_map)
1437                 rte_free(fdir_info->hash_map);
1438         if (fdir_info->hash_handle)
1439                 rte_hash_free(fdir_info->hash_handle);
1440
1441         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1442                 TAILQ_REMOVE(&fdir_info->fdir_list,
1443                              fdir_filter,
1444                              entries);
1445                 rte_free(fdir_filter);
1446         }
1447
1448         return 0;
1449 }
1450
1451 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1452 {
1453         struct ixgbe_l2_tn_info *l2_tn_info =
1454                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1455         struct ixgbe_l2_tn_filter *l2_tn_filter;
1456
1457         if (l2_tn_info->hash_map)
1458                 rte_free(l2_tn_info->hash_map);
1459         if (l2_tn_info->hash_handle)
1460                 rte_hash_free(l2_tn_info->hash_handle);
1461
1462         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1463                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1464                              l2_tn_filter,
1465                              entries);
1466                 rte_free(l2_tn_filter);
1467         }
1468
1469         return 0;
1470 }
1471
1472 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1473 {
1474         struct ixgbe_hw_fdir_info *fdir_info =
1475                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1476         char fdir_hash_name[RTE_HASH_NAMESIZE];
1477         struct rte_hash_parameters fdir_hash_params = {
1478                 .name = fdir_hash_name,
1479                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1480                 .key_len = sizeof(union ixgbe_atr_input),
1481                 .hash_func = rte_hash_crc,
1482                 .hash_func_init_val = 0,
1483                 .socket_id = rte_socket_id(),
1484         };
1485
1486         TAILQ_INIT(&fdir_info->fdir_list);
1487         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1488                  "fdir_%s", eth_dev->device->name);
1489         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1490         if (!fdir_info->hash_handle) {
1491                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1492                 return -EINVAL;
1493         }
1494         fdir_info->hash_map = rte_zmalloc("ixgbe",
1495                                           sizeof(struct ixgbe_fdir_filter *) *
1496                                           IXGBE_MAX_FDIR_FILTER_NUM,
1497                                           0);
1498         if (!fdir_info->hash_map) {
1499                 PMD_INIT_LOG(ERR,
1500                              "Failed to allocate memory for fdir hash map!");
1501                 return -ENOMEM;
1502         }
1503         fdir_info->mask_added = FALSE;
1504
1505         return 0;
1506 }
1507
1508 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1509 {
1510         struct ixgbe_l2_tn_info *l2_tn_info =
1511                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1512         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1513         struct rte_hash_parameters l2_tn_hash_params = {
1514                 .name = l2_tn_hash_name,
1515                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1516                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1517                 .hash_func = rte_hash_crc,
1518                 .hash_func_init_val = 0,
1519                 .socket_id = rte_socket_id(),
1520         };
1521
1522         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1523         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1524                  "l2_tn_%s", eth_dev->device->name);
1525         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1526         if (!l2_tn_info->hash_handle) {
1527                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1528                 return -EINVAL;
1529         }
1530         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1531                                    sizeof(struct ixgbe_l2_tn_filter *) *
1532                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1533                                    0);
1534         if (!l2_tn_info->hash_map) {
1535                 PMD_INIT_LOG(ERR,
1536                         "Failed to allocate memory for L2 TN hash map!");
1537                 return -ENOMEM;
1538         }
1539         l2_tn_info->e_tag_en = FALSE;
1540         l2_tn_info->e_tag_fwd_en = FALSE;
1541         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1542
1543         return 0;
1544 }
1545 /*
1546  * Negotiate mailbox API version with the PF.
1547  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1548  * Then we try to negotiate starting with the most recent one.
1549  * If all negotiation attempts fail, then we will proceed with
1550  * the default one (ixgbe_mbox_api_10).
1551  */
1552 static void
1553 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1554 {
1555         int32_t i;
1556
1557         /* start with highest supported, proceed down */
1558         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1559                 ixgbe_mbox_api_12,
1560                 ixgbe_mbox_api_11,
1561                 ixgbe_mbox_api_10,
1562         };
1563
1564         for (i = 0;
1565                         i != RTE_DIM(sup_ver) &&
1566                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1567                         i++)
1568                 ;
1569 }
1570
1571 static void
1572 generate_random_mac_addr(struct ether_addr *mac_addr)
1573 {
1574         uint64_t random;
1575
1576         /* Set Organizationally Unique Identifier (OUI) prefix. */
1577         mac_addr->addr_bytes[0] = 0x00;
1578         mac_addr->addr_bytes[1] = 0x09;
1579         mac_addr->addr_bytes[2] = 0xC0;
1580         /* Force indication of locally assigned MAC address. */
1581         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1582         /* Generate the last 3 bytes of the MAC address with a random number. */
1583         random = rte_rand();
1584         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1585 }
1586
1587 /*
1588  * Virtual Function device init
1589  */
1590 static int
1591 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1592 {
1593         int diag;
1594         uint32_t tc, tcs;
1595         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1596         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1597         struct ixgbe_hw *hw =
1598                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1599         struct ixgbe_vfta *shadow_vfta =
1600                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1601         struct ixgbe_hwstrip *hwstrip =
1602                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1603         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1604
1605         PMD_INIT_FUNC_TRACE();
1606
1607         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1608         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1609         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1610
1611         /* for secondary processes, we don't initialise any further as primary
1612          * has already done this work. Only check we don't need a different
1613          * RX function
1614          */
1615         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1616                 struct ixgbe_tx_queue *txq;
1617                 /* TX queue function in primary, set by last queue initialized
1618                  * Tx queue may not initialized by primary process
1619                  */
1620                 if (eth_dev->data->tx_queues) {
1621                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1622                         ixgbe_set_tx_function(eth_dev, txq);
1623                 } else {
1624                         /* Use default TX function if we get here */
1625                         PMD_INIT_LOG(NOTICE,
1626                                      "No TX queues configured yet. Using default TX function.");
1627                 }
1628
1629                 ixgbe_set_rx_function(eth_dev);
1630
1631                 return 0;
1632         }
1633
1634         rte_eth_copy_pci_info(eth_dev, pci_dev);
1635         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1636
1637         hw->device_id = pci_dev->id.device_id;
1638         hw->vendor_id = pci_dev->id.vendor_id;
1639         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1640
1641         /* initialize the vfta */
1642         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1643
1644         /* initialize the hw strip bitmap*/
1645         memset(hwstrip, 0, sizeof(*hwstrip));
1646
1647         /* Initialize the shared code (base driver) */
1648         diag = ixgbe_init_shared_code(hw);
1649         if (diag != IXGBE_SUCCESS) {
1650                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1651                 return -EIO;
1652         }
1653
1654         /* init_mailbox_params */
1655         hw->mbx.ops.init_params(hw);
1656
1657         /* Reset the hw statistics */
1658         ixgbevf_dev_stats_reset(eth_dev);
1659
1660         /* Disable the interrupts for VF */
1661         ixgbevf_intr_disable(hw);
1662
1663         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1664         diag = hw->mac.ops.reset_hw(hw);
1665
1666         /*
1667          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1668          * the underlying PF driver has not assigned a MAC address to the VF.
1669          * In this case, assign a random MAC address.
1670          */
1671         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1672                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1673                 return diag;
1674         }
1675
1676         /* negotiate mailbox API version to use with the PF. */
1677         ixgbevf_negotiate_api(hw);
1678
1679         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1680         ixgbevf_get_queues(hw, &tcs, &tc);
1681
1682         /* Allocate memory for storing MAC addresses */
1683         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1684                                                hw->mac.num_rar_entries, 0);
1685         if (eth_dev->data->mac_addrs == NULL) {
1686                 PMD_INIT_LOG(ERR,
1687                              "Failed to allocate %u bytes needed to store "
1688                              "MAC addresses",
1689                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1690                 return -ENOMEM;
1691         }
1692
1693         /* Generate a random MAC address, if none was assigned by PF. */
1694         if (is_zero_ether_addr(perm_addr)) {
1695                 generate_random_mac_addr(perm_addr);
1696                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1697                 if (diag) {
1698                         rte_free(eth_dev->data->mac_addrs);
1699                         eth_dev->data->mac_addrs = NULL;
1700                         return diag;
1701                 }
1702                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1703                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1704                              "%02x:%02x:%02x:%02x:%02x:%02x",
1705                              perm_addr->addr_bytes[0],
1706                              perm_addr->addr_bytes[1],
1707                              perm_addr->addr_bytes[2],
1708                              perm_addr->addr_bytes[3],
1709                              perm_addr->addr_bytes[4],
1710                              perm_addr->addr_bytes[5]);
1711         }
1712
1713         /* Copy the permanent MAC address */
1714         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1715
1716         /* reset the hardware with the new settings */
1717         diag = hw->mac.ops.start_hw(hw);
1718         switch (diag) {
1719         case  0:
1720                 break;
1721
1722         default:
1723                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1724                 return -EIO;
1725         }
1726
1727         rte_intr_callback_register(intr_handle,
1728                                    ixgbevf_dev_interrupt_handler, eth_dev);
1729         rte_intr_enable(intr_handle);
1730         ixgbevf_intr_enable(hw);
1731
1732         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1733                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1734                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1735
1736         return 0;
1737 }
1738
1739 /* Virtual Function device uninit */
1740
1741 static int
1742 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1743 {
1744         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1745         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1746         struct ixgbe_hw *hw;
1747
1748         PMD_INIT_FUNC_TRACE();
1749
1750         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1751                 return -EPERM;
1752
1753         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1754
1755         if (hw->adapter_stopped == 0)
1756                 ixgbevf_dev_close(eth_dev);
1757
1758         eth_dev->dev_ops = NULL;
1759         eth_dev->rx_pkt_burst = NULL;
1760         eth_dev->tx_pkt_burst = NULL;
1761
1762         /* Disable the interrupts for VF */
1763         ixgbevf_intr_disable(hw);
1764
1765         rte_free(eth_dev->data->mac_addrs);
1766         eth_dev->data->mac_addrs = NULL;
1767
1768         rte_intr_disable(intr_handle);
1769         rte_intr_callback_unregister(intr_handle,
1770                                      ixgbevf_dev_interrupt_handler, eth_dev);
1771
1772         return 0;
1773 }
1774
1775 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1776         struct rte_pci_device *pci_dev)
1777 {
1778         return rte_eth_dev_pci_generic_probe(pci_dev,
1779                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1780 }
1781
1782 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1783 {
1784         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1785 }
1786
1787 static struct rte_pci_driver rte_ixgbe_pmd = {
1788         .id_table = pci_id_ixgbe_map,
1789         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1790         .probe = eth_ixgbe_pci_probe,
1791         .remove = eth_ixgbe_pci_remove,
1792 };
1793
1794 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1795         struct rte_pci_device *pci_dev)
1796 {
1797         return rte_eth_dev_pci_generic_probe(pci_dev,
1798                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1799 }
1800
1801 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1802 {
1803         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1804 }
1805
1806 /*
1807  * virtual function driver struct
1808  */
1809 static struct rte_pci_driver rte_ixgbevf_pmd = {
1810         .id_table = pci_id_ixgbevf_map,
1811         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1812         .probe = eth_ixgbevf_pci_probe,
1813         .remove = eth_ixgbevf_pci_remove,
1814 };
1815
1816 static int
1817 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1818 {
1819         struct ixgbe_hw *hw =
1820                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1821         struct ixgbe_vfta *shadow_vfta =
1822                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1823         uint32_t vfta;
1824         uint32_t vid_idx;
1825         uint32_t vid_bit;
1826
1827         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1828         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1829         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1830         if (on)
1831                 vfta |= vid_bit;
1832         else
1833                 vfta &= ~vid_bit;
1834         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1835
1836         /* update local VFTA copy */
1837         shadow_vfta->vfta[vid_idx] = vfta;
1838
1839         return 0;
1840 }
1841
1842 static void
1843 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1844 {
1845         if (on)
1846                 ixgbe_vlan_hw_strip_enable(dev, queue);
1847         else
1848                 ixgbe_vlan_hw_strip_disable(dev, queue);
1849 }
1850
1851 static int
1852 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1853                     enum rte_vlan_type vlan_type,
1854                     uint16_t tpid)
1855 {
1856         struct ixgbe_hw *hw =
1857                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858         int ret = 0;
1859         uint32_t reg;
1860         uint32_t qinq;
1861
1862         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1863         qinq &= IXGBE_DMATXCTL_GDV;
1864
1865         switch (vlan_type) {
1866         case ETH_VLAN_TYPE_INNER:
1867                 if (qinq) {
1868                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1869                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1870                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1871                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1872                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1873                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1874                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1875                 } else {
1876                         ret = -ENOTSUP;
1877                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1878                                     " by single VLAN");
1879                 }
1880                 break;
1881         case ETH_VLAN_TYPE_OUTER:
1882                 if (qinq) {
1883                         /* Only the high 16-bits is valid */
1884                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1885                                         IXGBE_EXVET_VET_EXT_SHIFT);
1886                 } else {
1887                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1888                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1889                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1890                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1891                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1892                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1893                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1894                 }
1895
1896                 break;
1897         default:
1898                 ret = -EINVAL;
1899                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1900                 break;
1901         }
1902
1903         return ret;
1904 }
1905
1906 void
1907 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1908 {
1909         struct ixgbe_hw *hw =
1910                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911         uint32_t vlnctrl;
1912
1913         PMD_INIT_FUNC_TRACE();
1914
1915         /* Filter Table Disable */
1916         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1917         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1918
1919         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1920 }
1921
1922 void
1923 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1924 {
1925         struct ixgbe_hw *hw =
1926                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927         struct ixgbe_vfta *shadow_vfta =
1928                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1929         uint32_t vlnctrl;
1930         uint16_t i;
1931
1932         PMD_INIT_FUNC_TRACE();
1933
1934         /* Filter Table Enable */
1935         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1936         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1937         vlnctrl |= IXGBE_VLNCTRL_VFE;
1938
1939         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1940
1941         /* write whatever is in local vfta copy */
1942         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1943                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1944 }
1945
1946 static void
1947 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1948 {
1949         struct ixgbe_hwstrip *hwstrip =
1950                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1951         struct ixgbe_rx_queue *rxq;
1952
1953         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1954                 return;
1955
1956         if (on)
1957                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1958         else
1959                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1960
1961         if (queue >= dev->data->nb_rx_queues)
1962                 return;
1963
1964         rxq = dev->data->rx_queues[queue];
1965
1966         if (on)
1967                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1968         else
1969                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1970 }
1971
1972 static void
1973 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1974 {
1975         struct ixgbe_hw *hw =
1976                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1977         uint32_t ctrl;
1978
1979         PMD_INIT_FUNC_TRACE();
1980
1981         if (hw->mac.type == ixgbe_mac_82598EB) {
1982                 /* No queue level support */
1983                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1984                 return;
1985         }
1986
1987         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1988         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1989         ctrl &= ~IXGBE_RXDCTL_VME;
1990         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1991
1992         /* record those setting for HW strip per queue */
1993         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1994 }
1995
1996 static void
1997 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1998 {
1999         struct ixgbe_hw *hw =
2000                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001         uint32_t ctrl;
2002
2003         PMD_INIT_FUNC_TRACE();
2004
2005         if (hw->mac.type == ixgbe_mac_82598EB) {
2006                 /* No queue level supported */
2007                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2008                 return;
2009         }
2010
2011         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2012         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2013         ctrl |= IXGBE_RXDCTL_VME;
2014         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2015
2016         /* record those setting for HW strip per queue */
2017         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2018 }
2019
2020 void
2021 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2022 {
2023         struct ixgbe_hw *hw =
2024                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025         uint32_t ctrl;
2026         uint16_t i;
2027         struct ixgbe_rx_queue *rxq;
2028
2029         PMD_INIT_FUNC_TRACE();
2030
2031         if (hw->mac.type == ixgbe_mac_82598EB) {
2032                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2033                 ctrl &= ~IXGBE_VLNCTRL_VME;
2034                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2035         } else {
2036                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2037                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2038                         rxq = dev->data->rx_queues[i];
2039                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2040                         ctrl &= ~IXGBE_RXDCTL_VME;
2041                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2042
2043                         /* record those setting for HW strip per queue */
2044                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2045                 }
2046         }
2047 }
2048
2049 void
2050 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2051 {
2052         struct ixgbe_hw *hw =
2053                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054         uint32_t ctrl;
2055         uint16_t i;
2056         struct ixgbe_rx_queue *rxq;
2057
2058         PMD_INIT_FUNC_TRACE();
2059
2060         if (hw->mac.type == ixgbe_mac_82598EB) {
2061                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2062                 ctrl |= IXGBE_VLNCTRL_VME;
2063                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2064         } else {
2065                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2066                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2067                         rxq = dev->data->rx_queues[i];
2068                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2069                         ctrl |= IXGBE_RXDCTL_VME;
2070                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2071
2072                         /* record those setting for HW strip per queue */
2073                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2074                 }
2075         }
2076 }
2077
2078 static void
2079 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2080 {
2081         struct ixgbe_hw *hw =
2082                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083         uint32_t ctrl;
2084
2085         PMD_INIT_FUNC_TRACE();
2086
2087         /* DMATXCTRL: Geric Double VLAN Disable */
2088         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2089         ctrl &= ~IXGBE_DMATXCTL_GDV;
2090         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2091
2092         /* CTRL_EXT: Global Double VLAN Disable */
2093         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2094         ctrl &= ~IXGBE_EXTENDED_VLAN;
2095         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2096
2097 }
2098
2099 static void
2100 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2101 {
2102         struct ixgbe_hw *hw =
2103                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2104         uint32_t ctrl;
2105
2106         PMD_INIT_FUNC_TRACE();
2107
2108         /* DMATXCTRL: Geric Double VLAN Enable */
2109         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2110         ctrl |= IXGBE_DMATXCTL_GDV;
2111         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2112
2113         /* CTRL_EXT: Global Double VLAN Enable */
2114         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2115         ctrl |= IXGBE_EXTENDED_VLAN;
2116         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2117
2118         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2119         if (hw->mac.type == ixgbe_mac_X550 ||
2120             hw->mac.type == ixgbe_mac_X550EM_x ||
2121             hw->mac.type == ixgbe_mac_X550EM_a) {
2122                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2123                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2124                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2125         }
2126
2127         /*
2128          * VET EXT field in the EXVET register = 0x8100 by default
2129          * So no need to change. Same to VT field of DMATXCTL register
2130          */
2131 }
2132
2133 static void
2134 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2135 {
2136         if (mask & ETH_VLAN_STRIP_MASK) {
2137                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2138                         ixgbe_vlan_hw_strip_enable_all(dev);
2139                 else
2140                         ixgbe_vlan_hw_strip_disable_all(dev);
2141         }
2142
2143         if (mask & ETH_VLAN_FILTER_MASK) {
2144                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2145                         ixgbe_vlan_hw_filter_enable(dev);
2146                 else
2147                         ixgbe_vlan_hw_filter_disable(dev);
2148         }
2149
2150         if (mask & ETH_VLAN_EXTEND_MASK) {
2151                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2152                         ixgbe_vlan_hw_extend_enable(dev);
2153                 else
2154                         ixgbe_vlan_hw_extend_disable(dev);
2155         }
2156 }
2157
2158 static void
2159 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2160 {
2161         struct ixgbe_hw *hw =
2162                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2164         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2165
2166         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2167         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2168 }
2169
2170 static int
2171 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2172 {
2173         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2174
2175         switch (nb_rx_q) {
2176         case 1:
2177         case 2:
2178                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2179                 break;
2180         case 4:
2181                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2182                 break;
2183         default:
2184                 return -EINVAL;
2185         }
2186
2187         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2188         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2189
2190         return 0;
2191 }
2192
2193 static int
2194 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2195 {
2196         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2197         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2199         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2200
2201         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2202                 /* check multi-queue mode */
2203                 switch (dev_conf->rxmode.mq_mode) {
2204                 case ETH_MQ_RX_VMDQ_DCB:
2205                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2206                         break;
2207                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2208                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2209                         PMD_INIT_LOG(ERR, "SRIOV active,"
2210                                         " unsupported mq_mode rx %d.",
2211                                         dev_conf->rxmode.mq_mode);
2212                         return -EINVAL;
2213                 case ETH_MQ_RX_RSS:
2214                 case ETH_MQ_RX_VMDQ_RSS:
2215                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2216                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2217                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2218                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2219                                                 " invalid queue number"
2220                                                 " for VMDQ RSS, allowed"
2221                                                 " value are 1, 2 or 4.");
2222                                         return -EINVAL;
2223                                 }
2224                         break;
2225                 case ETH_MQ_RX_VMDQ_ONLY:
2226                 case ETH_MQ_RX_NONE:
2227                         /* if nothing mq mode configure, use default scheme */
2228                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2229                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2230                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2231                         break;
2232                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2233                         /* SRIOV only works in VMDq enable mode */
2234                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2235                                         " wrong mq_mode rx %d.",
2236                                         dev_conf->rxmode.mq_mode);
2237                         return -EINVAL;
2238                 }
2239
2240                 switch (dev_conf->txmode.mq_mode) {
2241                 case ETH_MQ_TX_VMDQ_DCB:
2242                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2243                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2244                         break;
2245                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2246                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2247                         break;
2248                 }
2249
2250                 /* check valid queue number */
2251                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2252                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2253                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2254                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2255                                         " must be less than or equal to %d.",
2256                                         nb_rx_q, nb_tx_q,
2257                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2258                         return -EINVAL;
2259                 }
2260         } else {
2261                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2262                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2263                                           " not supported.");
2264                         return -EINVAL;
2265                 }
2266                 /* check configuration for vmdb+dcb mode */
2267                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2268                         const struct rte_eth_vmdq_dcb_conf *conf;
2269
2270                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2271                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2272                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2273                                 return -EINVAL;
2274                         }
2275                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2276                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2277                                conf->nb_queue_pools == ETH_32_POOLS)) {
2278                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2279                                                 " nb_queue_pools must be %d or %d.",
2280                                                 ETH_16_POOLS, ETH_32_POOLS);
2281                                 return -EINVAL;
2282                         }
2283                 }
2284                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2285                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2286
2287                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2288                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2289                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2290                                 return -EINVAL;
2291                         }
2292                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2293                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2294                                conf->nb_queue_pools == ETH_32_POOLS)) {
2295                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2296                                                 " nb_queue_pools != %d and"
2297                                                 " nb_queue_pools != %d.",
2298                                                 ETH_16_POOLS, ETH_32_POOLS);
2299                                 return -EINVAL;
2300                         }
2301                 }
2302
2303                 /* For DCB mode check our configuration before we go further */
2304                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2305                         const struct rte_eth_dcb_rx_conf *conf;
2306
2307                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2308                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2309                                                  IXGBE_DCB_NB_QUEUES);
2310                                 return -EINVAL;
2311                         }
2312                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2313                         if (!(conf->nb_tcs == ETH_4_TCS ||
2314                                conf->nb_tcs == ETH_8_TCS)) {
2315                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2316                                                 " and nb_tcs != %d.",
2317                                                 ETH_4_TCS, ETH_8_TCS);
2318                                 return -EINVAL;
2319                         }
2320                 }
2321
2322                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2323                         const struct rte_eth_dcb_tx_conf *conf;
2324
2325                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2326                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2327                                                  IXGBE_DCB_NB_QUEUES);
2328                                 return -EINVAL;
2329                         }
2330                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2331                         if (!(conf->nb_tcs == ETH_4_TCS ||
2332                                conf->nb_tcs == ETH_8_TCS)) {
2333                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2334                                                 " and nb_tcs != %d.",
2335                                                 ETH_4_TCS, ETH_8_TCS);
2336                                 return -EINVAL;
2337                         }
2338                 }
2339
2340                 /*
2341                  * When DCB/VT is off, maximum number of queues changes,
2342                  * except for 82598EB, which remains constant.
2343                  */
2344                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2345                                 hw->mac.type != ixgbe_mac_82598EB) {
2346                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2347                                 PMD_INIT_LOG(ERR,
2348                                              "Neither VT nor DCB are enabled, "
2349                                              "nb_tx_q > %d.",
2350                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2351                                 return -EINVAL;
2352                         }
2353                 }
2354         }
2355         return 0;
2356 }
2357
2358 static int
2359 ixgbe_dev_configure(struct rte_eth_dev *dev)
2360 {
2361         struct ixgbe_interrupt *intr =
2362                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2363         struct ixgbe_adapter *adapter =
2364                 (struct ixgbe_adapter *)dev->data->dev_private;
2365         int ret;
2366
2367         PMD_INIT_FUNC_TRACE();
2368         /* multipe queue mode checking */
2369         ret  = ixgbe_check_mq_mode(dev);
2370         if (ret != 0) {
2371                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2372                             ret);
2373                 return ret;
2374         }
2375
2376         /* set flag to update link status after init */
2377         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2378
2379         /*
2380          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2381          * allocation or vector Rx preconditions we will reset it.
2382          */
2383         adapter->rx_bulk_alloc_allowed = true;
2384         adapter->rx_vec_allowed = true;
2385
2386         return 0;
2387 }
2388
2389 static void
2390 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2391 {
2392         struct ixgbe_hw *hw =
2393                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2394         struct ixgbe_interrupt *intr =
2395                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2396         uint32_t gpie;
2397
2398         /* only set up it on X550EM_X */
2399         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2400                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2401                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2402                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2403                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2404                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2405         }
2406 }
2407
2408 int
2409 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2410                         uint16_t tx_rate, uint64_t q_msk)
2411 {
2412         struct ixgbe_hw *hw;
2413         struct ixgbe_vf_info *vfinfo;
2414         struct rte_eth_link link;
2415         uint8_t  nb_q_per_pool;
2416         uint32_t queue_stride;
2417         uint32_t queue_idx, idx = 0, vf_idx;
2418         uint32_t queue_end;
2419         uint16_t total_rate = 0;
2420         struct rte_pci_device *pci_dev;
2421
2422         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2423         rte_eth_link_get_nowait(dev->data->port_id, &link);
2424
2425         if (vf >= pci_dev->max_vfs)
2426                 return -EINVAL;
2427
2428         if (tx_rate > link.link_speed)
2429                 return -EINVAL;
2430
2431         if (q_msk == 0)
2432                 return 0;
2433
2434         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2436         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2437         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2438         queue_idx = vf * queue_stride;
2439         queue_end = queue_idx + nb_q_per_pool - 1;
2440         if (queue_end >= hw->mac.max_tx_queues)
2441                 return -EINVAL;
2442
2443         if (vfinfo) {
2444                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2445                         if (vf_idx == vf)
2446                                 continue;
2447                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2448                                 idx++)
2449                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2450                 }
2451         } else {
2452                 return -EINVAL;
2453         }
2454
2455         /* Store tx_rate for this vf. */
2456         for (idx = 0; idx < nb_q_per_pool; idx++) {
2457                 if (((uint64_t)0x1 << idx) & q_msk) {
2458                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2459                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2460                         total_rate += tx_rate;
2461                 }
2462         }
2463
2464         if (total_rate > dev->data->dev_link.link_speed) {
2465                 /* Reset stored TX rate of the VF if it causes exceed
2466                  * link speed.
2467                  */
2468                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2469                 return -EINVAL;
2470         }
2471
2472         /* Set RTTBCNRC of each queue/pool for vf X  */
2473         for (; queue_idx <= queue_end; queue_idx++) {
2474                 if (0x1 & q_msk)
2475                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2476                 q_msk = q_msk >> 1;
2477         }
2478
2479         return 0;
2480 }
2481
2482 /*
2483  * Configure device link speed and setup link.
2484  * It returns 0 on success.
2485  */
2486 static int
2487 ixgbe_dev_start(struct rte_eth_dev *dev)
2488 {
2489         struct ixgbe_hw *hw =
2490                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491         struct ixgbe_vf_info *vfinfo =
2492                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2493         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2494         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2495         uint32_t intr_vector = 0;
2496         int err, link_up = 0, negotiate = 0;
2497         uint32_t speed = 0;
2498         int mask = 0;
2499         int status;
2500         uint16_t vf, idx;
2501         uint32_t *link_speeds;
2502         struct ixgbe_tm_conf *tm_conf =
2503                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2504
2505         PMD_INIT_FUNC_TRACE();
2506
2507         /* IXGBE devices don't support:
2508         *    - half duplex (checked afterwards for valid speeds)
2509         *    - fixed speed: TODO implement
2510         */
2511         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2512                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2513                              dev->data->port_id);
2514                 return -EINVAL;
2515         }
2516
2517         /* disable uio/vfio intr/eventfd mapping */
2518         rte_intr_disable(intr_handle);
2519
2520         /* stop adapter */
2521         hw->adapter_stopped = 0;
2522         ixgbe_stop_adapter(hw);
2523
2524         /* reinitialize adapter
2525          * this calls reset and start
2526          */
2527         status = ixgbe_pf_reset_hw(hw);
2528         if (status != 0)
2529                 return -1;
2530         hw->mac.ops.start_hw(hw);
2531         hw->mac.get_link_status = true;
2532
2533         /* configure PF module if SRIOV enabled */
2534         ixgbe_pf_host_configure(dev);
2535
2536         ixgbe_dev_phy_intr_setup(dev);
2537
2538         /* check and configure queue intr-vector mapping */
2539         if ((rte_intr_cap_multiple(intr_handle) ||
2540              !RTE_ETH_DEV_SRIOV(dev).active) &&
2541             dev->data->dev_conf.intr_conf.rxq != 0) {
2542                 intr_vector = dev->data->nb_rx_queues;
2543                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2544                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2545                                         IXGBE_MAX_INTR_QUEUE_NUM);
2546                         return -ENOTSUP;
2547                 }
2548                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2549                         return -1;
2550         }
2551
2552         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2553                 intr_handle->intr_vec =
2554                         rte_zmalloc("intr_vec",
2555                                     dev->data->nb_rx_queues * sizeof(int), 0);
2556                 if (intr_handle->intr_vec == NULL) {
2557                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2558                                      " intr_vec", dev->data->nb_rx_queues);
2559                         return -ENOMEM;
2560                 }
2561         }
2562
2563         /* confiugre msix for sleep until rx interrupt */
2564         ixgbe_configure_msix(dev);
2565
2566         /* initialize transmission unit */
2567         ixgbe_dev_tx_init(dev);
2568
2569         /* This can fail when allocating mbufs for descriptor rings */
2570         err = ixgbe_dev_rx_init(dev);
2571         if (err) {
2572                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2573                 goto error;
2574         }
2575
2576     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2577                 ETH_VLAN_EXTEND_MASK;
2578         ixgbe_vlan_offload_set(dev, mask);
2579
2580         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2581                 /* Enable vlan filtering for VMDq */
2582                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2583         }
2584
2585         /* Configure DCB hw */
2586         ixgbe_configure_dcb(dev);
2587
2588         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2589                 err = ixgbe_fdir_configure(dev);
2590                 if (err)
2591                         goto error;
2592         }
2593
2594         /* Restore vf rate limit */
2595         if (vfinfo != NULL) {
2596                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2597                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2598                                 if (vfinfo[vf].tx_rate[idx] != 0)
2599                                         ixgbe_set_vf_rate_limit(
2600                                                 dev, vf,
2601                                                 vfinfo[vf].tx_rate[idx],
2602                                                 1 << idx);
2603         }
2604
2605         ixgbe_restore_statistics_mapping(dev);
2606
2607         err = ixgbe_dev_rxtx_start(dev);
2608         if (err < 0) {
2609                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2610                 goto error;
2611         }
2612
2613         /* Skip link setup if loopback mode is enabled for 82599. */
2614         if (hw->mac.type == ixgbe_mac_82599EB &&
2615                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2616                 goto skip_link_setup;
2617
2618         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2619                 err = hw->mac.ops.setup_sfp(hw);
2620                 if (err)
2621                         goto error;
2622         }
2623
2624         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2625                 /* Turn on the copper */
2626                 ixgbe_set_phy_power(hw, true);
2627         } else {
2628                 /* Turn on the laser */
2629                 ixgbe_enable_tx_laser(hw);
2630         }
2631
2632         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2633         if (err)
2634                 goto error;
2635         dev->data->dev_link.link_status = link_up;
2636
2637         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2638         if (err)
2639                 goto error;
2640
2641         link_speeds = &dev->data->dev_conf.link_speeds;
2642         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2643                         ETH_LINK_SPEED_10G)) {
2644                 PMD_INIT_LOG(ERR, "Invalid link setting");
2645                 goto error;
2646         }
2647
2648         speed = 0x0;
2649         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2650                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2651                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2652                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2653         } else {
2654                 if (*link_speeds & ETH_LINK_SPEED_10G)
2655                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2656                 if (*link_speeds & ETH_LINK_SPEED_1G)
2657                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2658                 if (*link_speeds & ETH_LINK_SPEED_100M)
2659                         speed |= IXGBE_LINK_SPEED_100_FULL;
2660         }
2661
2662         err = ixgbe_setup_link(hw, speed, link_up);
2663         if (err)
2664                 goto error;
2665
2666 skip_link_setup:
2667
2668         if (rte_intr_allow_others(intr_handle)) {
2669                 /* check if lsc interrupt is enabled */
2670                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2671                         ixgbe_dev_lsc_interrupt_setup(dev);
2672                 ixgbe_dev_macsec_interrupt_setup(dev);
2673         } else {
2674                 rte_intr_callback_unregister(intr_handle,
2675                                              ixgbe_dev_interrupt_handler, dev);
2676                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2677                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2678                                      " no intr multiplex");
2679         }
2680
2681         /* check if rxq interrupt is enabled */
2682         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2683             rte_intr_dp_is_en(intr_handle))
2684                 ixgbe_dev_rxq_interrupt_setup(dev);
2685
2686         /* enable uio/vfio intr/eventfd mapping */
2687         rte_intr_enable(intr_handle);
2688
2689         /* resume enabled intr since hw reset */
2690         ixgbe_enable_intr(dev);
2691         ixgbe_l2_tunnel_conf(dev);
2692         ixgbe_filter_restore(dev);
2693
2694         if (!tm_conf->committed)
2695                 PMD_DRV_LOG(WARNING,
2696                             "please call hierarchy_commit() "
2697                             "before starting the port");
2698
2699         return 0;
2700
2701 error:
2702         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2703         ixgbe_dev_clear_queues(dev);
2704         return -EIO;
2705 }
2706
2707 /*
2708  * Stop device: disable rx and tx functions to allow for reconfiguring.
2709  */
2710 static void
2711 ixgbe_dev_stop(struct rte_eth_dev *dev)
2712 {
2713         struct rte_eth_link link;
2714         struct ixgbe_hw *hw =
2715                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2716         struct ixgbe_vf_info *vfinfo =
2717                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2718         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2719         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2720         int vf;
2721         struct ixgbe_tm_conf *tm_conf =
2722                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2723
2724         PMD_INIT_FUNC_TRACE();
2725
2726         /* disable interrupts */
2727         ixgbe_disable_intr(hw);
2728
2729         /* reset the NIC */
2730         ixgbe_pf_reset_hw(hw);
2731         hw->adapter_stopped = 0;
2732
2733         /* stop adapter */
2734         ixgbe_stop_adapter(hw);
2735
2736         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2737                 vfinfo[vf].clear_to_send = false;
2738
2739         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2740                 /* Turn off the copper */
2741                 ixgbe_set_phy_power(hw, false);
2742         } else {
2743                 /* Turn off the laser */
2744                 ixgbe_disable_tx_laser(hw);
2745         }
2746
2747         ixgbe_dev_clear_queues(dev);
2748
2749         /* Clear stored conf */
2750         dev->data->scattered_rx = 0;
2751         dev->data->lro = 0;
2752
2753         /* Clear recorded link status */
2754         memset(&link, 0, sizeof(link));
2755         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2756
2757         if (!rte_intr_allow_others(intr_handle))
2758                 /* resume to the default handler */
2759                 rte_intr_callback_register(intr_handle,
2760                                            ixgbe_dev_interrupt_handler,
2761                                            (void *)dev);
2762
2763         /* Clean datapath event and queue/vec mapping */
2764         rte_intr_efd_disable(intr_handle);
2765         if (intr_handle->intr_vec != NULL) {
2766                 rte_free(intr_handle->intr_vec);
2767                 intr_handle->intr_vec = NULL;
2768         }
2769
2770         /* reset hierarchy commit */
2771         tm_conf->committed = false;
2772 }
2773
2774 /*
2775  * Set device link up: enable tx.
2776  */
2777 static int
2778 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2779 {
2780         struct ixgbe_hw *hw =
2781                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782         if (hw->mac.type == ixgbe_mac_82599EB) {
2783 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2784                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2785                         /* Not suported in bypass mode */
2786                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2787                                      "by device id 0x%x", hw->device_id);
2788                         return -ENOTSUP;
2789                 }
2790 #endif
2791         }
2792
2793         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2794                 /* Turn on the copper */
2795                 ixgbe_set_phy_power(hw, true);
2796         } else {
2797                 /* Turn on the laser */
2798                 ixgbe_enable_tx_laser(hw);
2799         }
2800
2801         return 0;
2802 }
2803
2804 /*
2805  * Set device link down: disable tx.
2806  */
2807 static int
2808 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2809 {
2810         struct ixgbe_hw *hw =
2811                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812         if (hw->mac.type == ixgbe_mac_82599EB) {
2813 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2814                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2815                         /* Not suported in bypass mode */
2816                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2817                                      "by device id 0x%x", hw->device_id);
2818                         return -ENOTSUP;
2819                 }
2820 #endif
2821         }
2822
2823         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2824                 /* Turn off the copper */
2825                 ixgbe_set_phy_power(hw, false);
2826         } else {
2827                 /* Turn off the laser */
2828                 ixgbe_disable_tx_laser(hw);
2829         }
2830
2831         return 0;
2832 }
2833
2834 /*
2835  * Reest and stop device.
2836  */
2837 static void
2838 ixgbe_dev_close(struct rte_eth_dev *dev)
2839 {
2840         struct ixgbe_hw *hw =
2841                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842
2843         PMD_INIT_FUNC_TRACE();
2844
2845         ixgbe_pf_reset_hw(hw);
2846
2847         ixgbe_dev_stop(dev);
2848         hw->adapter_stopped = 1;
2849
2850         ixgbe_dev_free_queues(dev);
2851
2852         ixgbe_disable_pcie_master(hw);
2853
2854         /* reprogram the RAR[0] in case user changed it. */
2855         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2856 }
2857
2858 static void
2859 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2860                            struct ixgbe_hw_stats *hw_stats,
2861                            struct ixgbe_macsec_stats *macsec_stats,
2862                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2863                            uint64_t *total_qprc, uint64_t *total_qprdc)
2864 {
2865         uint32_t bprc, lxon, lxoff, total;
2866         uint32_t delta_gprc = 0;
2867         unsigned i;
2868         /* Workaround for RX byte count not including CRC bytes when CRC
2869          * strip is enabled. CRC bytes are removed from counters when crc_strip
2870          * is disabled.
2871          */
2872         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2873                         IXGBE_HLREG0_RXCRCSTRP);
2874
2875         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2876         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2877         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2878         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2879
2880         for (i = 0; i < 8; i++) {
2881                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2882
2883                 /* global total per queue */
2884                 hw_stats->mpc[i] += mp;
2885                 /* Running comprehensive total for stats display */
2886                 *total_missed_rx += hw_stats->mpc[i];
2887                 if (hw->mac.type == ixgbe_mac_82598EB) {
2888                         hw_stats->rnbc[i] +=
2889                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2890                         hw_stats->pxonrxc[i] +=
2891                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2892                         hw_stats->pxoffrxc[i] +=
2893                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2894                 } else {
2895                         hw_stats->pxonrxc[i] +=
2896                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2897                         hw_stats->pxoffrxc[i] +=
2898                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2899                         hw_stats->pxon2offc[i] +=
2900                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2901                 }
2902                 hw_stats->pxontxc[i] +=
2903                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2904                 hw_stats->pxofftxc[i] +=
2905                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2906         }
2907         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2908                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2909                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2910                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2911
2912                 delta_gprc += delta_qprc;
2913
2914                 hw_stats->qprc[i] += delta_qprc;
2915                 hw_stats->qptc[i] += delta_qptc;
2916
2917                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2918                 hw_stats->qbrc[i] +=
2919                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2920                 if (crc_strip == 0)
2921                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2922
2923                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2924                 hw_stats->qbtc[i] +=
2925                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2926
2927                 hw_stats->qprdc[i] += delta_qprdc;
2928                 *total_qprdc += hw_stats->qprdc[i];
2929
2930                 *total_qprc += hw_stats->qprc[i];
2931                 *total_qbrc += hw_stats->qbrc[i];
2932         }
2933         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2934         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2935         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2936
2937         /*
2938          * An errata states that gprc actually counts good + missed packets:
2939          * Workaround to set gprc to summated queue packet receives
2940          */
2941         hw_stats->gprc = *total_qprc;
2942
2943         if (hw->mac.type != ixgbe_mac_82598EB) {
2944                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2945                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2946                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2947                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2948                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2949                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2950                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2951                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2952         } else {
2953                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2954                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2955                 /* 82598 only has a counter in the high register */
2956                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2957                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2958                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2959         }
2960         uint64_t old_tpr = hw_stats->tpr;
2961
2962         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2963         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2964
2965         if (crc_strip == 0)
2966                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2967
2968         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2969         hw_stats->gptc += delta_gptc;
2970         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2971         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2972
2973         /*
2974          * Workaround: mprc hardware is incorrectly counting
2975          * broadcasts, so for now we subtract those.
2976          */
2977         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2978         hw_stats->bprc += bprc;
2979         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2980         if (hw->mac.type == ixgbe_mac_82598EB)
2981                 hw_stats->mprc -= bprc;
2982
2983         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2984         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2985         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2986         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2987         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2988         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2989
2990         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2991         hw_stats->lxontxc += lxon;
2992         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2993         hw_stats->lxofftxc += lxoff;
2994         total = lxon + lxoff;
2995
2996         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2997         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2998         hw_stats->gptc -= total;
2999         hw_stats->mptc -= total;
3000         hw_stats->ptc64 -= total;
3001         hw_stats->gotc -= total * ETHER_MIN_LEN;
3002
3003         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3004         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3005         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3006         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3007         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3008         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3009         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3010         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3011         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3012         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3013         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3014         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3015         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3016         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3017         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3018         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3019         /* Only read FCOE on 82599 */
3020         if (hw->mac.type != ixgbe_mac_82598EB) {
3021                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3022                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3023                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3024                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3025                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3026         }
3027
3028         /* Flow Director Stats registers */
3029         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3030         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3031
3032         /* MACsec Stats registers */
3033         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3034         macsec_stats->out_pkts_encrypted +=
3035                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3036         macsec_stats->out_pkts_protected +=
3037                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3038         macsec_stats->out_octets_encrypted +=
3039                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3040         macsec_stats->out_octets_protected +=
3041                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3042         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3043         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3044         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3045         macsec_stats->in_pkts_unknownsci +=
3046                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3047         macsec_stats->in_octets_decrypted +=
3048                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3049         macsec_stats->in_octets_validated +=
3050                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3051         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3052         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3053         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3054         for (i = 0; i < 2; i++) {
3055                 macsec_stats->in_pkts_ok +=
3056                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3057                 macsec_stats->in_pkts_invalid +=
3058                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3059                 macsec_stats->in_pkts_notvalid +=
3060                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3061         }
3062         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3063         macsec_stats->in_pkts_notusingsa +=
3064                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3065 }
3066
3067 /*
3068  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3069  */
3070 static void
3071 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3072 {
3073         struct ixgbe_hw *hw =
3074                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3075         struct ixgbe_hw_stats *hw_stats =
3076                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3077         struct ixgbe_macsec_stats *macsec_stats =
3078                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3079                                 dev->data->dev_private);
3080         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3081         unsigned i;
3082
3083         total_missed_rx = 0;
3084         total_qbrc = 0;
3085         total_qprc = 0;
3086         total_qprdc = 0;
3087
3088         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3089                         &total_qbrc, &total_qprc, &total_qprdc);
3090
3091         if (stats == NULL)
3092                 return;
3093
3094         /* Fill out the rte_eth_stats statistics structure */
3095         stats->ipackets = total_qprc;
3096         stats->ibytes = total_qbrc;
3097         stats->opackets = hw_stats->gptc;
3098         stats->obytes = hw_stats->gotc;
3099
3100         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3101                 stats->q_ipackets[i] = hw_stats->qprc[i];
3102                 stats->q_opackets[i] = hw_stats->qptc[i];
3103                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3104                 stats->q_obytes[i] = hw_stats->qbtc[i];
3105                 stats->q_errors[i] = hw_stats->qprdc[i];
3106         }
3107
3108         /* Rx Errors */
3109         stats->imissed  = total_missed_rx;
3110         stats->ierrors  = hw_stats->crcerrs +
3111                           hw_stats->mspdc +
3112                           hw_stats->rlec +
3113                           hw_stats->ruc +
3114                           hw_stats->roc +
3115                           hw_stats->illerrc +
3116                           hw_stats->errbc +
3117                           hw_stats->rfc +
3118                           hw_stats->fccrc +
3119                           hw_stats->fclast;
3120
3121         /* Tx Errors */
3122         stats->oerrors  = 0;
3123 }
3124
3125 static void
3126 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3127 {
3128         struct ixgbe_hw_stats *stats =
3129                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3130
3131         /* HW registers are cleared on read */
3132         ixgbe_dev_stats_get(dev, NULL);
3133
3134         /* Reset software totals */
3135         memset(stats, 0, sizeof(*stats));
3136 }
3137
3138 /* This function calculates the number of xstats based on the current config */
3139 static unsigned
3140 ixgbe_xstats_calc_num(void) {
3141         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3142                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3143                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3144 }
3145
3146 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3147         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3148 {
3149         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3150         unsigned stat, i, count;
3151
3152         if (xstats_names != NULL) {
3153                 count = 0;
3154
3155                 /* Note: limit >= cnt_stats checked upstream
3156                  * in rte_eth_xstats_names()
3157                  */
3158
3159                 /* Extended stats from ixgbe_hw_stats */
3160                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3161                         snprintf(xstats_names[count].name,
3162                                 sizeof(xstats_names[count].name),
3163                                 "%s",
3164                                 rte_ixgbe_stats_strings[i].name);
3165                         count++;
3166                 }
3167
3168                 /* MACsec Stats */
3169                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3170                         snprintf(xstats_names[count].name,
3171                                 sizeof(xstats_names[count].name),
3172                                 "%s",
3173                                 rte_ixgbe_macsec_strings[i].name);
3174                         count++;
3175                 }
3176
3177                 /* RX Priority Stats */
3178                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3179                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3180                                 snprintf(xstats_names[count].name,
3181                                         sizeof(xstats_names[count].name),
3182                                         "rx_priority%u_%s", i,
3183                                         rte_ixgbe_rxq_strings[stat].name);
3184                                 count++;
3185                         }
3186                 }
3187
3188                 /* TX Priority Stats */
3189                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3190                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3191                                 snprintf(xstats_names[count].name,
3192                                         sizeof(xstats_names[count].name),
3193                                         "tx_priority%u_%s", i,
3194                                         rte_ixgbe_txq_strings[stat].name);
3195                                 count++;
3196                         }
3197                 }
3198         }
3199         return cnt_stats;
3200 }
3201
3202 static int ixgbe_dev_xstats_get_names_by_id(
3203         struct rte_eth_dev *dev,
3204         struct rte_eth_xstat_name *xstats_names,
3205         const uint64_t *ids,
3206         unsigned int limit)
3207 {
3208         if (!ids) {
3209                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3210                 unsigned int stat, i, count;
3211
3212                 if (xstats_names != NULL) {
3213                         count = 0;
3214
3215                         /* Note: limit >= cnt_stats checked upstream
3216                          * in rte_eth_xstats_names()
3217                          */
3218
3219                         /* Extended stats from ixgbe_hw_stats */
3220                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3221                                 snprintf(xstats_names[count].name,
3222                                         sizeof(xstats_names[count].name),
3223                                         "%s",
3224                                         rte_ixgbe_stats_strings[i].name);
3225                                 count++;
3226                         }
3227
3228                         /* MACsec Stats */
3229                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3230                                 snprintf(xstats_names[count].name,
3231                                         sizeof(xstats_names[count].name),
3232                                         "%s",
3233                                         rte_ixgbe_macsec_strings[i].name);
3234                                 count++;
3235                         }
3236
3237                         /* RX Priority Stats */
3238                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3239                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3240                                         snprintf(xstats_names[count].name,
3241                                             sizeof(xstats_names[count].name),
3242                                             "rx_priority%u_%s", i,
3243                                             rte_ixgbe_rxq_strings[stat].name);
3244                                         count++;
3245                                 }
3246                         }
3247
3248                         /* TX Priority Stats */
3249                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3250                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3251                                         snprintf(xstats_names[count].name,
3252                                             sizeof(xstats_names[count].name),
3253                                             "tx_priority%u_%s", i,
3254                                             rte_ixgbe_txq_strings[stat].name);
3255                                         count++;
3256                                 }
3257                         }
3258                 }
3259                 return cnt_stats;
3260         }
3261
3262         uint16_t i;
3263         uint16_t size = ixgbe_xstats_calc_num();
3264         struct rte_eth_xstat_name xstats_names_copy[size];
3265
3266         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3267                         size);
3268
3269         for (i = 0; i < limit; i++) {
3270                 if (ids[i] >= size) {
3271                         PMD_INIT_LOG(ERR, "id value isn't valid");
3272                         return -1;
3273                 }
3274                 strcpy(xstats_names[i].name,
3275                                 xstats_names_copy[ids[i]].name);
3276         }
3277         return limit;
3278 }
3279
3280 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3281         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3282 {
3283         unsigned i;
3284
3285         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3286                 return -ENOMEM;
3287
3288         if (xstats_names != NULL)
3289                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3290                         snprintf(xstats_names[i].name,
3291                                 sizeof(xstats_names[i].name),
3292                                 "%s", rte_ixgbevf_stats_strings[i].name);
3293         return IXGBEVF_NB_XSTATS;
3294 }
3295
3296 static int
3297 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3298                                          unsigned n)
3299 {
3300         struct ixgbe_hw *hw =
3301                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3302         struct ixgbe_hw_stats *hw_stats =
3303                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3304         struct ixgbe_macsec_stats *macsec_stats =
3305                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3306                                 dev->data->dev_private);
3307         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3308         unsigned i, stat, count = 0;
3309
3310         count = ixgbe_xstats_calc_num();
3311
3312         if (n < count)
3313                 return count;
3314
3315         total_missed_rx = 0;
3316         total_qbrc = 0;
3317         total_qprc = 0;
3318         total_qprdc = 0;
3319
3320         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3321                         &total_qbrc, &total_qprc, &total_qprdc);
3322
3323         /* If this is a reset xstats is NULL, and we have cleared the
3324          * registers by reading them.
3325          */
3326         if (!xstats)
3327                 return 0;
3328
3329         /* Extended stats from ixgbe_hw_stats */
3330         count = 0;
3331         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3332                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3333                                 rte_ixgbe_stats_strings[i].offset);
3334                 xstats[count].id = count;
3335                 count++;
3336         }
3337
3338         /* MACsec Stats */
3339         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3340                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3341                                 rte_ixgbe_macsec_strings[i].offset);
3342                 xstats[count].id = count;
3343                 count++;
3344         }
3345
3346         /* RX Priority Stats */
3347         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3348                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3349                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3350                                         rte_ixgbe_rxq_strings[stat].offset +
3351                                         (sizeof(uint64_t) * i));
3352                         xstats[count].id = count;
3353                         count++;
3354                 }
3355         }
3356
3357         /* TX Priority Stats */
3358         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3359                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3360                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3361                                         rte_ixgbe_txq_strings[stat].offset +
3362                                         (sizeof(uint64_t) * i));
3363                         xstats[count].id = count;
3364                         count++;
3365                 }
3366         }
3367         return count;
3368 }
3369
3370 static int
3371 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3372                 uint64_t *values, unsigned int n)
3373 {
3374         if (!ids) {
3375                 struct ixgbe_hw *hw =
3376                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3377                 struct ixgbe_hw_stats *hw_stats =
3378                                 IXGBE_DEV_PRIVATE_TO_STATS(
3379                                                 dev->data->dev_private);
3380                 struct ixgbe_macsec_stats *macsec_stats =
3381                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3382                                         dev->data->dev_private);
3383                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3384                 unsigned int i, stat, count = 0;
3385
3386                 count = ixgbe_xstats_calc_num();
3387
3388                 if (!ids && n < count)
3389                         return count;
3390
3391                 total_missed_rx = 0;
3392                 total_qbrc = 0;
3393                 total_qprc = 0;
3394                 total_qprdc = 0;
3395
3396                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3397                                 &total_missed_rx, &total_qbrc, &total_qprc,
3398                                 &total_qprdc);
3399
3400                 /* If this is a reset xstats is NULL, and we have cleared the
3401                  * registers by reading them.
3402                  */
3403                 if (!ids && !values)
3404                         return 0;
3405
3406                 /* Extended stats from ixgbe_hw_stats */
3407                 count = 0;
3408                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3409                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3410                                         rte_ixgbe_stats_strings[i].offset);
3411                         count++;
3412                 }
3413
3414                 /* MACsec Stats */
3415                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3416                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3417                                         rte_ixgbe_macsec_strings[i].offset);
3418                         count++;
3419                 }
3420
3421                 /* RX Priority Stats */
3422                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3423                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3424                                 values[count] =
3425                                         *(uint64_t *)(((char *)hw_stats) +
3426                                         rte_ixgbe_rxq_strings[stat].offset +
3427                                         (sizeof(uint64_t) * i));
3428                                 count++;
3429                         }
3430                 }
3431
3432                 /* TX Priority Stats */
3433                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3434                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3435                                 values[count] =
3436                                         *(uint64_t *)(((char *)hw_stats) +
3437                                         rte_ixgbe_txq_strings[stat].offset +
3438                                         (sizeof(uint64_t) * i));
3439                                 count++;
3440                         }
3441                 }
3442                 return count;
3443         }
3444
3445         uint16_t i;
3446         uint16_t size = ixgbe_xstats_calc_num();
3447         uint64_t values_copy[size];
3448
3449         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3450
3451         for (i = 0; i < n; i++) {
3452                 if (ids[i] >= size) {
3453                         PMD_INIT_LOG(ERR, "id value isn't valid");
3454                         return -1;
3455                 }
3456                 values[i] = values_copy[ids[i]];
3457         }
3458         return n;
3459 }
3460
3461 static void
3462 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3463 {
3464         struct ixgbe_hw_stats *stats =
3465                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3466         struct ixgbe_macsec_stats *macsec_stats =
3467                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3468                                 dev->data->dev_private);
3469
3470         unsigned count = ixgbe_xstats_calc_num();
3471
3472         /* HW registers are cleared on read */
3473         ixgbe_dev_xstats_get(dev, NULL, count);
3474
3475         /* Reset software totals */
3476         memset(stats, 0, sizeof(*stats));
3477         memset(macsec_stats, 0, sizeof(*macsec_stats));
3478 }
3479
3480 static void
3481 ixgbevf_update_stats(struct rte_eth_dev *dev)
3482 {
3483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3484         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3485                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3486
3487         /* Good Rx packet, include VF loopback */
3488         UPDATE_VF_STAT(IXGBE_VFGPRC,
3489             hw_stats->last_vfgprc, hw_stats->vfgprc);
3490
3491         /* Good Rx octets, include VF loopback */
3492         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3493             hw_stats->last_vfgorc, hw_stats->vfgorc);
3494
3495         /* Good Tx packet, include VF loopback */
3496         UPDATE_VF_STAT(IXGBE_VFGPTC,
3497             hw_stats->last_vfgptc, hw_stats->vfgptc);
3498
3499         /* Good Tx octets, include VF loopback */
3500         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3501             hw_stats->last_vfgotc, hw_stats->vfgotc);
3502
3503         /* Rx Multicst Packet */
3504         UPDATE_VF_STAT(IXGBE_VFMPRC,
3505             hw_stats->last_vfmprc, hw_stats->vfmprc);
3506 }
3507
3508 static int
3509 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3510                        unsigned n)
3511 {
3512         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3513                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3514         unsigned i;
3515
3516         if (n < IXGBEVF_NB_XSTATS)
3517                 return IXGBEVF_NB_XSTATS;
3518
3519         ixgbevf_update_stats(dev);
3520
3521         if (!xstats)
3522                 return 0;
3523
3524         /* Extended stats */
3525         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3526                 xstats[i].id = i;
3527                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3528                         rte_ixgbevf_stats_strings[i].offset);
3529         }
3530
3531         return IXGBEVF_NB_XSTATS;
3532 }
3533
3534 static void
3535 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3536 {
3537         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3538                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3539
3540         ixgbevf_update_stats(dev);
3541
3542         if (stats == NULL)
3543                 return;
3544
3545         stats->ipackets = hw_stats->vfgprc;
3546         stats->ibytes = hw_stats->vfgorc;
3547         stats->opackets = hw_stats->vfgptc;
3548         stats->obytes = hw_stats->vfgotc;
3549 }
3550
3551 static void
3552 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3553 {
3554         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3555                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3556
3557         /* Sync HW register to the last stats */
3558         ixgbevf_dev_stats_get(dev, NULL);
3559
3560         /* reset HW current stats*/
3561         hw_stats->vfgprc = 0;
3562         hw_stats->vfgorc = 0;
3563         hw_stats->vfgptc = 0;
3564         hw_stats->vfgotc = 0;
3565 }
3566
3567 static int
3568 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3569 {
3570         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3571         u16 eeprom_verh, eeprom_verl;
3572         u32 etrack_id;
3573         int ret;
3574
3575         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3576         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3577
3578         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3579         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3580
3581         ret += 1; /* add the size of '\0' */
3582         if (fw_size < (u32)ret)
3583                 return ret;
3584         else
3585                 return 0;
3586 }
3587
3588 static void
3589 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3590 {
3591         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3593         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3594
3595         dev_info->pci_dev = pci_dev;
3596         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3597         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3598         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3599                 /*
3600                  * When DCB/VT is off, maximum number of queues changes,
3601                  * except for 82598EB, which remains constant.
3602                  */
3603                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3604                                 hw->mac.type != ixgbe_mac_82598EB)
3605                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3606         }
3607         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3608         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3609         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3610         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3611         dev_info->max_vfs = pci_dev->max_vfs;
3612         if (hw->mac.type == ixgbe_mac_82598EB)
3613                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3614         else
3615                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3616         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3617         dev_info->rx_offload_capa =
3618                 DEV_RX_OFFLOAD_VLAN_STRIP |
3619                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3620                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3621                 DEV_RX_OFFLOAD_TCP_CKSUM;
3622
3623         /*
3624          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3625          * mode.
3626          */
3627         if ((hw->mac.type == ixgbe_mac_82599EB ||
3628              hw->mac.type == ixgbe_mac_X540) &&
3629             !RTE_ETH_DEV_SRIOV(dev).active)
3630                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3631
3632         if (hw->mac.type == ixgbe_mac_82599EB ||
3633             hw->mac.type == ixgbe_mac_X540)
3634                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3635
3636         if (hw->mac.type == ixgbe_mac_X550 ||
3637             hw->mac.type == ixgbe_mac_X550EM_x ||
3638             hw->mac.type == ixgbe_mac_X550EM_a)
3639                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3640
3641         dev_info->tx_offload_capa =
3642                 DEV_TX_OFFLOAD_VLAN_INSERT |
3643                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3644                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3645                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3646                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3647                 DEV_TX_OFFLOAD_TCP_TSO;
3648
3649         if (hw->mac.type == ixgbe_mac_82599EB ||
3650             hw->mac.type == ixgbe_mac_X540)
3651                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3652
3653         if (hw->mac.type == ixgbe_mac_X550 ||
3654             hw->mac.type == ixgbe_mac_X550EM_x ||
3655             hw->mac.type == ixgbe_mac_X550EM_a)
3656                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3657
3658         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3659                 .rx_thresh = {
3660                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3661                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3662                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3663                 },
3664                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3665                 .rx_drop_en = 0,
3666         };
3667
3668         dev_info->default_txconf = (struct rte_eth_txconf) {
3669                 .tx_thresh = {
3670                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3671                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3672                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3673                 },
3674                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3675                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3676                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3677                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3678         };
3679
3680         dev_info->rx_desc_lim = rx_desc_lim;
3681         dev_info->tx_desc_lim = tx_desc_lim;
3682
3683         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3684         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3685         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3686
3687         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3688         if (hw->mac.type == ixgbe_mac_X540 ||
3689             hw->mac.type == ixgbe_mac_X540_vf ||
3690             hw->mac.type == ixgbe_mac_X550 ||
3691             hw->mac.type == ixgbe_mac_X550_vf) {
3692                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3693         }
3694 }
3695
3696 static const uint32_t *
3697 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3698 {
3699         static const uint32_t ptypes[] = {
3700                 /* For non-vec functions,
3701                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3702                  * for vec functions,
3703                  * refers to _recv_raw_pkts_vec().
3704                  */
3705                 RTE_PTYPE_L2_ETHER,
3706                 RTE_PTYPE_L3_IPV4,
3707                 RTE_PTYPE_L3_IPV4_EXT,
3708                 RTE_PTYPE_L3_IPV6,
3709                 RTE_PTYPE_L3_IPV6_EXT,
3710                 RTE_PTYPE_L4_SCTP,
3711                 RTE_PTYPE_L4_TCP,
3712                 RTE_PTYPE_L4_UDP,
3713                 RTE_PTYPE_TUNNEL_IP,
3714                 RTE_PTYPE_INNER_L3_IPV6,
3715                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3716                 RTE_PTYPE_INNER_L4_TCP,
3717                 RTE_PTYPE_INNER_L4_UDP,
3718                 RTE_PTYPE_UNKNOWN
3719         };
3720
3721         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3722             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3723             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3724             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3725                 return ptypes;
3726
3727 #if defined(RTE_ARCH_X86)
3728         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3729             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3730                 return ptypes;
3731 #endif
3732         return NULL;
3733 }
3734
3735 static void
3736 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3737                      struct rte_eth_dev_info *dev_info)
3738 {
3739         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3740         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3741
3742         dev_info->pci_dev = pci_dev;
3743         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3744         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3745         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3746         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3747         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3748         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3749         dev_info->max_vfs = pci_dev->max_vfs;
3750         if (hw->mac.type == ixgbe_mac_82598EB)
3751                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3752         else
3753                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3754         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3755                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3756                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3757                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3758         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3759                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3760                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3761                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3762                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3763                                 DEV_TX_OFFLOAD_TCP_TSO;
3764
3765         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3766                 .rx_thresh = {
3767                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3768                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3769                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3770                 },
3771                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3772                 .rx_drop_en = 0,
3773         };
3774
3775         dev_info->default_txconf = (struct rte_eth_txconf) {
3776                 .tx_thresh = {
3777                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3778                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3779                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3780                 },
3781                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3782                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3783                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3784                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3785         };
3786
3787         dev_info->rx_desc_lim = rx_desc_lim;
3788         dev_info->tx_desc_lim = tx_desc_lim;
3789 }
3790
3791 static int
3792 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3793                    int *link_up, int wait_to_complete)
3794 {
3795         /**
3796          * for a quick link status checking, wait_to_compelet == 0,
3797          * skip PF link status checking
3798          */
3799         bool no_pflink_check = wait_to_complete == 0;
3800         struct ixgbe_mbx_info *mbx = &hw->mbx;
3801         struct ixgbe_mac_info *mac = &hw->mac;
3802         uint32_t links_reg, in_msg;
3803         int ret_val = 0;
3804
3805         /* If we were hit with a reset drop the link */
3806         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3807                 mac->get_link_status = true;
3808
3809         if (!mac->get_link_status)
3810                 goto out;
3811
3812         /* if link status is down no point in checking to see if pf is up */
3813         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3814         if (!(links_reg & IXGBE_LINKS_UP))
3815                 goto out;
3816
3817         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3818          * before the link status is correct
3819          */
3820         if (mac->type == ixgbe_mac_82599_vf) {
3821                 int i;
3822
3823                 for (i = 0; i < 5; i++) {
3824                         rte_delay_us(100);
3825                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3826
3827                         if (!(links_reg & IXGBE_LINKS_UP))
3828                                 goto out;
3829                 }
3830         }
3831
3832         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3833         case IXGBE_LINKS_SPEED_10G_82599:
3834                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3835                 if (hw->mac.type >= ixgbe_mac_X550) {
3836                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3837                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3838                 }
3839                 break;
3840         case IXGBE_LINKS_SPEED_1G_82599:
3841                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3842                 break;
3843         case IXGBE_LINKS_SPEED_100_82599:
3844                 *speed = IXGBE_LINK_SPEED_100_FULL;
3845                 if (hw->mac.type == ixgbe_mac_X550) {
3846                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3847                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3848                 }
3849                 break;
3850         case IXGBE_LINKS_SPEED_10_X550EM_A:
3851                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3852                 /* Since Reserved in older MAC's */
3853                 if (hw->mac.type >= ixgbe_mac_X550)
3854                         *speed = IXGBE_LINK_SPEED_10_FULL;
3855                 break;
3856         default:
3857                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3858         }
3859
3860         if (no_pflink_check) {
3861                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3862                         mac->get_link_status = true;
3863                 else
3864                         mac->get_link_status = false;
3865
3866                 goto out;
3867         }
3868         /* if the read failed it could just be a mailbox collision, best wait
3869          * until we are called again and don't report an error
3870          */
3871         if (mbx->ops.read(hw, &in_msg, 1, 0))
3872                 goto out;
3873
3874         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3875                 /* msg is not CTS and is NACK we must have lost CTS status */
3876                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3877                         ret_val = -1;
3878                 goto out;
3879         }
3880
3881         /* the pf is talking, if we timed out in the past we reinit */
3882         if (!mbx->timeout) {
3883                 ret_val = -1;
3884                 goto out;
3885         }
3886
3887         /* if we passed all the tests above then the link is up and we no
3888          * longer need to check for link
3889          */
3890         mac->get_link_status = false;
3891
3892 out:
3893         *link_up = !mac->get_link_status;
3894         return ret_val;
3895 }
3896
3897 /* return 0 means link status changed, -1 means not changed */
3898 static int
3899 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3900                             int wait_to_complete, int vf)
3901 {
3902         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3903         struct rte_eth_link link, old;
3904         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3905         struct ixgbe_interrupt *intr =
3906                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3907         int link_up;
3908         int diag;
3909         u32 speed = 0;
3910         int wait = 1;
3911         bool autoneg = false;
3912
3913         link.link_status = ETH_LINK_DOWN;
3914         link.link_speed = 0;
3915         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3916         memset(&old, 0, sizeof(old));
3917         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3918
3919         hw->mac.get_link_status = true;
3920
3921         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3922                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3923                 speed = hw->phy.autoneg_advertised;
3924                 if (!speed)
3925                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3926                 ixgbe_setup_link(hw, speed, true);
3927         }
3928
3929         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3930         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3931                 wait = 0;
3932
3933         if (vf)
3934                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3935         else
3936                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3937
3938         if (diag != 0) {
3939                 link.link_speed = ETH_SPEED_NUM_100M;
3940                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3941                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3942                 if (link.link_status == old.link_status)
3943                         return -1;
3944                 return 0;
3945         }
3946
3947         if (link_up == 0) {
3948                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3949                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3950                 if (link.link_status == old.link_status)
3951                         return -1;
3952                 return 0;
3953         }
3954         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3955         link.link_status = ETH_LINK_UP;
3956         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3957
3958         switch (link_speed) {
3959         default:
3960         case IXGBE_LINK_SPEED_UNKNOWN:
3961                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3962                 link.link_speed = ETH_SPEED_NUM_100M;
3963                 break;
3964
3965         case IXGBE_LINK_SPEED_100_FULL:
3966                 link.link_speed = ETH_SPEED_NUM_100M;
3967                 break;
3968
3969         case IXGBE_LINK_SPEED_1GB_FULL:
3970                 link.link_speed = ETH_SPEED_NUM_1G;
3971                 break;
3972
3973         case IXGBE_LINK_SPEED_10GB_FULL:
3974                 link.link_speed = ETH_SPEED_NUM_10G;
3975                 break;
3976         }
3977         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3978
3979         if (link.link_status == old.link_status)
3980                 return -1;
3981
3982         return 0;
3983 }
3984
3985 static int
3986 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3987 {
3988         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3989 }
3990
3991 static int
3992 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3993 {
3994         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3995 }
3996
3997 static void
3998 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3999 {
4000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4001         uint32_t fctrl;
4002
4003         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4004         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4005         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4006 }
4007
4008 static void
4009 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4010 {
4011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4012         uint32_t fctrl;
4013
4014         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4015         fctrl &= (~IXGBE_FCTRL_UPE);
4016         if (dev->data->all_multicast == 1)
4017                 fctrl |= IXGBE_FCTRL_MPE;
4018         else
4019                 fctrl &= (~IXGBE_FCTRL_MPE);
4020         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4021 }
4022
4023 static void
4024 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4025 {
4026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4027         uint32_t fctrl;
4028
4029         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4030         fctrl |= IXGBE_FCTRL_MPE;
4031         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4032 }
4033
4034 static void
4035 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4036 {
4037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4038         uint32_t fctrl;
4039
4040         if (dev->data->promiscuous == 1)
4041                 return; /* must remain in all_multicast mode */
4042
4043         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4044         fctrl &= (~IXGBE_FCTRL_MPE);
4045         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4046 }
4047
4048 /**
4049  * It clears the interrupt causes and enables the interrupt.
4050  * It will be called once only during nic initialized.
4051  *
4052  * @param dev
4053  *  Pointer to struct rte_eth_dev.
4054  *
4055  * @return
4056  *  - On success, zero.
4057  *  - On failure, a negative value.
4058  */
4059 static int
4060 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
4061 {
4062         struct ixgbe_interrupt *intr =
4063                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4064
4065         ixgbe_dev_link_status_print(dev);
4066         intr->mask |= IXGBE_EICR_LSC;
4067
4068         return 0;
4069 }
4070
4071 /**
4072  * It clears the interrupt causes and enables the interrupt.
4073  * It will be called once only during nic initialized.
4074  *
4075  * @param dev
4076  *  Pointer to struct rte_eth_dev.
4077  *
4078  * @return
4079  *  - On success, zero.
4080  *  - On failure, a negative value.
4081  */
4082 static int
4083 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4084 {
4085         struct ixgbe_interrupt *intr =
4086                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4087
4088         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4089
4090         return 0;
4091 }
4092
4093 /**
4094  * It clears the interrupt causes and enables the interrupt.
4095  * It will be called once only during nic initialized.
4096  *
4097  * @param dev
4098  *  Pointer to struct rte_eth_dev.
4099  *
4100  * @return
4101  *  - On success, zero.
4102  *  - On failure, a negative value.
4103  */
4104 static int
4105 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4106 {
4107         struct ixgbe_interrupt *intr =
4108                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4109
4110         intr->mask |= IXGBE_EICR_LINKSEC;
4111
4112         return 0;
4113 }
4114
4115 /*
4116  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4117  *
4118  * @param dev
4119  *  Pointer to struct rte_eth_dev.
4120  *
4121  * @return
4122  *  - On success, zero.
4123  *  - On failure, a negative value.
4124  */
4125 static int
4126 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4127 {
4128         uint32_t eicr;
4129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4130         struct ixgbe_interrupt *intr =
4131                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4132
4133         /* clear all cause mask */
4134         ixgbe_disable_intr(hw);
4135
4136         /* read-on-clear nic registers here */
4137         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4138         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4139
4140         intr->flags = 0;
4141
4142         /* set flag for async link update */
4143         if (eicr & IXGBE_EICR_LSC)
4144                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4145
4146         if (eicr & IXGBE_EICR_MAILBOX)
4147                 intr->flags |= IXGBE_FLAG_MAILBOX;
4148
4149         if (eicr & IXGBE_EICR_LINKSEC)
4150                 intr->flags |= IXGBE_FLAG_MACSEC;
4151
4152         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4153             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4154             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4155                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4156
4157         return 0;
4158 }
4159
4160 /**
4161  * It gets and then prints the link status.
4162  *
4163  * @param dev
4164  *  Pointer to struct rte_eth_dev.
4165  *
4166  * @return
4167  *  - On success, zero.
4168  *  - On failure, a negative value.
4169  */
4170 static void
4171 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4172 {
4173         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4174         struct rte_eth_link link;
4175
4176         memset(&link, 0, sizeof(link));
4177         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4178         if (link.link_status) {
4179                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4180                                         (int)(dev->data->port_id),
4181                                         (unsigned)link.link_speed,
4182                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4183                                         "full-duplex" : "half-duplex");
4184         } else {
4185                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4186                                 (int)(dev->data->port_id));
4187         }
4188         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4189                                 pci_dev->addr.domain,
4190                                 pci_dev->addr.bus,
4191                                 pci_dev->addr.devid,
4192                                 pci_dev->addr.function);
4193 }
4194
4195 /*
4196  * It executes link_update after knowing an interrupt occurred.
4197  *
4198  * @param dev
4199  *  Pointer to struct rte_eth_dev.
4200  *
4201  * @return
4202  *  - On success, zero.
4203  *  - On failure, a negative value.
4204  */
4205 static int
4206 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4207                            struct rte_intr_handle *intr_handle)
4208 {
4209         struct ixgbe_interrupt *intr =
4210                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4211         int64_t timeout;
4212         struct rte_eth_link link;
4213         struct ixgbe_hw *hw =
4214                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4215
4216         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4217
4218         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4219                 ixgbe_pf_mbx_process(dev);
4220                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4221         }
4222
4223         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4224                 ixgbe_handle_lasi(hw);
4225                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4226         }
4227
4228         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4229                 /* get the link status before link update, for predicting later */
4230                 memset(&link, 0, sizeof(link));
4231                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4232
4233                 ixgbe_dev_link_update(dev, 0);
4234
4235                 /* likely to up */
4236                 if (!link.link_status)
4237                         /* handle it 1 sec later, wait it being stable */
4238                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4239                 /* likely to down */
4240                 else
4241                         /* handle it 4 sec later, wait it being stable */
4242                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4243
4244                 ixgbe_dev_link_status_print(dev);
4245                 if (rte_eal_alarm_set(timeout * 1000,
4246                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4247                         PMD_DRV_LOG(ERR, "Error setting alarm");
4248                 else {
4249                         /* remember original mask */
4250                         intr->mask_original = intr->mask;
4251                         /* only disable lsc interrupt */
4252                         intr->mask &= ~IXGBE_EIMS_LSC;
4253                 }
4254         }
4255
4256         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4257         ixgbe_enable_intr(dev);
4258         rte_intr_enable(intr_handle);
4259
4260         return 0;
4261 }
4262
4263 /**
4264  * Interrupt handler which shall be registered for alarm callback for delayed
4265  * handling specific interrupt to wait for the stable nic state. As the
4266  * NIC interrupt state is not stable for ixgbe after link is just down,
4267  * it needs to wait 4 seconds to get the stable status.
4268  *
4269  * @param handle
4270  *  Pointer to interrupt handle.
4271  * @param param
4272  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4273  *
4274  * @return
4275  *  void
4276  */
4277 static void
4278 ixgbe_dev_interrupt_delayed_handler(void *param)
4279 {
4280         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4281         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4282         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4283         struct ixgbe_interrupt *intr =
4284                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4285         struct ixgbe_hw *hw =
4286                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4287         uint32_t eicr;
4288
4289         ixgbe_disable_intr(hw);
4290
4291         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4292         if (eicr & IXGBE_EICR_MAILBOX)
4293                 ixgbe_pf_mbx_process(dev);
4294
4295         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4296                 ixgbe_handle_lasi(hw);
4297                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4298         }
4299
4300         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4301                 ixgbe_dev_link_update(dev, 0);
4302                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4303                 ixgbe_dev_link_status_print(dev);
4304                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4305                                               NULL, NULL);
4306         }
4307
4308         if (intr->flags & IXGBE_FLAG_MACSEC) {
4309                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4310                                               NULL, NULL);
4311                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4312         }
4313
4314         /* restore original mask */
4315         intr->mask = intr->mask_original;
4316         intr->mask_original = 0;
4317
4318         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4319         ixgbe_enable_intr(dev);
4320         rte_intr_enable(intr_handle);
4321 }
4322
4323 /**
4324  * Interrupt handler triggered by NIC  for handling
4325  * specific interrupt.
4326  *
4327  * @param handle
4328  *  Pointer to interrupt handle.
4329  * @param param
4330  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4331  *
4332  * @return
4333  *  void
4334  */
4335 static void
4336 ixgbe_dev_interrupt_handler(void *param)
4337 {
4338         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4339
4340         ixgbe_dev_interrupt_get_status(dev);
4341         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4342 }
4343
4344 static int
4345 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4346 {
4347         struct ixgbe_hw *hw;
4348
4349         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4350         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4351 }
4352
4353 static int
4354 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4355 {
4356         struct ixgbe_hw *hw;
4357
4358         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4359         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4360 }
4361
4362 static int
4363 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4364 {
4365         struct ixgbe_hw *hw;
4366         uint32_t mflcn_reg;
4367         uint32_t fccfg_reg;
4368         int rx_pause;
4369         int tx_pause;
4370
4371         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4372
4373         fc_conf->pause_time = hw->fc.pause_time;
4374         fc_conf->high_water = hw->fc.high_water[0];
4375         fc_conf->low_water = hw->fc.low_water[0];
4376         fc_conf->send_xon = hw->fc.send_xon;
4377         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4378
4379         /*
4380          * Return rx_pause status according to actual setting of
4381          * MFLCN register.
4382          */
4383         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4384         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4385                 rx_pause = 1;
4386         else
4387                 rx_pause = 0;
4388
4389         /*
4390          * Return tx_pause status according to actual setting of
4391          * FCCFG register.
4392          */
4393         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4394         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4395                 tx_pause = 1;
4396         else
4397                 tx_pause = 0;
4398
4399         if (rx_pause && tx_pause)
4400                 fc_conf->mode = RTE_FC_FULL;
4401         else if (rx_pause)
4402                 fc_conf->mode = RTE_FC_RX_PAUSE;
4403         else if (tx_pause)
4404                 fc_conf->mode = RTE_FC_TX_PAUSE;
4405         else
4406                 fc_conf->mode = RTE_FC_NONE;
4407
4408         return 0;
4409 }
4410
4411 static int
4412 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4413 {
4414         struct ixgbe_hw *hw;
4415         int err;
4416         uint32_t rx_buf_size;
4417         uint32_t max_high_water;
4418         uint32_t mflcn;
4419         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4420                 ixgbe_fc_none,
4421                 ixgbe_fc_rx_pause,
4422                 ixgbe_fc_tx_pause,
4423                 ixgbe_fc_full
4424         };
4425
4426         PMD_INIT_FUNC_TRACE();
4427
4428         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4429         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4430         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4431
4432         /*
4433          * At least reserve one Ethernet frame for watermark
4434          * high_water/low_water in kilo bytes for ixgbe
4435          */
4436         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4437         if ((fc_conf->high_water > max_high_water) ||
4438                 (fc_conf->high_water < fc_conf->low_water)) {
4439                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4440                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4441                 return -EINVAL;
4442         }
4443
4444         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4445         hw->fc.pause_time     = fc_conf->pause_time;
4446         hw->fc.high_water[0]  = fc_conf->high_water;
4447         hw->fc.low_water[0]   = fc_conf->low_water;
4448         hw->fc.send_xon       = fc_conf->send_xon;
4449         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4450
4451         err = ixgbe_fc_enable(hw);
4452
4453         /* Not negotiated is not an error case */
4454         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4455
4456                 /* check if we want to forward MAC frames - driver doesn't have native
4457                  * capability to do that, so we'll write the registers ourselves */
4458
4459                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4460
4461                 /* set or clear MFLCN.PMCF bit depending on configuration */
4462                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4463                         mflcn |= IXGBE_MFLCN_PMCF;
4464                 else
4465                         mflcn &= ~IXGBE_MFLCN_PMCF;
4466
4467                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4468                 IXGBE_WRITE_FLUSH(hw);
4469
4470                 return 0;
4471         }
4472
4473         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4474         return -EIO;
4475 }
4476
4477 /**
4478  *  ixgbe_pfc_enable_generic - Enable flow control
4479  *  @hw: pointer to hardware structure
4480  *  @tc_num: traffic class number
4481  *  Enable flow control according to the current settings.
4482  */
4483 static int
4484 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4485 {
4486         int ret_val = 0;
4487         uint32_t mflcn_reg, fccfg_reg;
4488         uint32_t reg;
4489         uint32_t fcrtl, fcrth;
4490         uint8_t i;
4491         uint8_t nb_rx_en;
4492
4493         /* Validate the water mark configuration */
4494         if (!hw->fc.pause_time) {
4495                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4496                 goto out;
4497         }
4498
4499         /* Low water mark of zero causes XOFF floods */
4500         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4501                  /* High/Low water can not be 0 */
4502                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4503                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4504                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4505                         goto out;
4506                 }
4507
4508                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4509                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4510                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4511                         goto out;
4512                 }
4513         }
4514         /* Negotiate the fc mode to use */
4515         ixgbe_fc_autoneg(hw);
4516
4517         /* Disable any previous flow control settings */
4518         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4519         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4520
4521         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4522         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4523
4524         switch (hw->fc.current_mode) {
4525         case ixgbe_fc_none:
4526                 /*
4527                  * If the count of enabled RX Priority Flow control >1,
4528                  * and the TX pause can not be disabled
4529                  */
4530                 nb_rx_en = 0;
4531                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4532                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4533                         if (reg & IXGBE_FCRTH_FCEN)
4534                                 nb_rx_en++;
4535                 }
4536                 if (nb_rx_en > 1)
4537                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4538                 break;
4539         case ixgbe_fc_rx_pause:
4540                 /*
4541                  * Rx Flow control is enabled and Tx Flow control is
4542                  * disabled by software override. Since there really
4543                  * isn't a way to advertise that we are capable of RX
4544                  * Pause ONLY, we will advertise that we support both
4545                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4546                  * disable the adapter's ability to send PAUSE frames.
4547                  */
4548                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4549                 /*
4550                  * If the count of enabled RX Priority Flow control >1,
4551                  * and the TX pause can not be disabled
4552                  */
4553                 nb_rx_en = 0;
4554                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4555                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4556                         if (reg & IXGBE_FCRTH_FCEN)
4557                                 nb_rx_en++;
4558                 }
4559                 if (nb_rx_en > 1)
4560                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4561                 break;
4562         case ixgbe_fc_tx_pause:
4563                 /*
4564                  * Tx Flow control is enabled, and Rx Flow control is
4565                  * disabled by software override.
4566                  */
4567                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4568                 break;
4569         case ixgbe_fc_full:
4570                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4571                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4572                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4573                 break;
4574         default:
4575                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4576                 ret_val = IXGBE_ERR_CONFIG;
4577                 goto out;
4578         }
4579
4580         /* Set 802.3x based flow control settings. */
4581         mflcn_reg |= IXGBE_MFLCN_DPF;
4582         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4583         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4584
4585         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4586         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4587                 hw->fc.high_water[tc_num]) {
4588                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4589                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4590                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4591         } else {
4592                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4593                 /*
4594                  * In order to prevent Tx hangs when the internal Tx
4595                  * switch is enabled we must set the high water mark
4596                  * to the maximum FCRTH value.  This allows the Tx
4597                  * switch to function even under heavy Rx workloads.
4598                  */
4599                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4600         }
4601         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4602
4603         /* Configure pause time (2 TCs per register) */
4604         reg = hw->fc.pause_time * 0x00010001;
4605         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4606                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4607
4608         /* Configure flow control refresh threshold value */
4609         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4610
4611 out:
4612         return ret_val;
4613 }
4614
4615 static int
4616 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4617 {
4618         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4619         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4620
4621         if (hw->mac.type != ixgbe_mac_82598EB) {
4622                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4623         }
4624         return ret_val;
4625 }
4626
4627 static int
4628 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4629 {
4630         int err;
4631         uint32_t rx_buf_size;
4632         uint32_t max_high_water;
4633         uint8_t tc_num;
4634         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4635         struct ixgbe_hw *hw =
4636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4637         struct ixgbe_dcb_config *dcb_config =
4638                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4639
4640         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4641                 ixgbe_fc_none,
4642                 ixgbe_fc_rx_pause,
4643                 ixgbe_fc_tx_pause,
4644                 ixgbe_fc_full
4645         };
4646
4647         PMD_INIT_FUNC_TRACE();
4648
4649         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4650         tc_num = map[pfc_conf->priority];
4651         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4652         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4653         /*
4654          * At least reserve one Ethernet frame for watermark
4655          * high_water/low_water in kilo bytes for ixgbe
4656          */
4657         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4658         if ((pfc_conf->fc.high_water > max_high_water) ||
4659             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4660                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4661                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4662                 return -EINVAL;
4663         }
4664
4665         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4666         hw->fc.pause_time = pfc_conf->fc.pause_time;
4667         hw->fc.send_xon = pfc_conf->fc.send_xon;
4668         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4669         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4670
4671         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4672
4673         /* Not negotiated is not an error case */
4674         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4675                 return 0;
4676
4677         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4678         return -EIO;
4679 }
4680
4681 static int
4682 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4683                           struct rte_eth_rss_reta_entry64 *reta_conf,
4684                           uint16_t reta_size)
4685 {
4686         uint16_t i, sp_reta_size;
4687         uint8_t j, mask;
4688         uint32_t reta, r;
4689         uint16_t idx, shift;
4690         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4691         uint32_t reta_reg;
4692
4693         PMD_INIT_FUNC_TRACE();
4694
4695         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4696                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4697                         "NIC.");
4698                 return -ENOTSUP;
4699         }
4700
4701         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4702         if (reta_size != sp_reta_size) {
4703                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4704                         "(%d) doesn't match the number hardware can supported "
4705                         "(%d)", reta_size, sp_reta_size);
4706                 return -EINVAL;
4707         }
4708
4709         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4710                 idx = i / RTE_RETA_GROUP_SIZE;
4711                 shift = i % RTE_RETA_GROUP_SIZE;
4712                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4713                                                 IXGBE_4_BIT_MASK);
4714                 if (!mask)
4715                         continue;
4716                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4717                 if (mask == IXGBE_4_BIT_MASK)
4718                         r = 0;
4719                 else
4720                         r = IXGBE_READ_REG(hw, reta_reg);
4721                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4722                         if (mask & (0x1 << j))
4723                                 reta |= reta_conf[idx].reta[shift + j] <<
4724                                                         (CHAR_BIT * j);
4725                         else
4726                                 reta |= r & (IXGBE_8_BIT_MASK <<
4727                                                 (CHAR_BIT * j));
4728                 }
4729                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4730         }
4731
4732         return 0;
4733 }
4734
4735 static int
4736 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4737                          struct rte_eth_rss_reta_entry64 *reta_conf,
4738                          uint16_t reta_size)
4739 {
4740         uint16_t i, sp_reta_size;
4741         uint8_t j, mask;
4742         uint32_t reta;
4743         uint16_t idx, shift;
4744         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4745         uint32_t reta_reg;
4746
4747         PMD_INIT_FUNC_TRACE();
4748         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4749         if (reta_size != sp_reta_size) {
4750                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4751                         "(%d) doesn't match the number hardware can supported "
4752                         "(%d)", reta_size, sp_reta_size);
4753                 return -EINVAL;
4754         }
4755
4756         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4757                 idx = i / RTE_RETA_GROUP_SIZE;
4758                 shift = i % RTE_RETA_GROUP_SIZE;
4759                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4760                                                 IXGBE_4_BIT_MASK);
4761                 if (!mask)
4762                         continue;
4763
4764                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4765                 reta = IXGBE_READ_REG(hw, reta_reg);
4766                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4767                         if (mask & (0x1 << j))
4768                                 reta_conf[idx].reta[shift + j] =
4769                                         ((reta >> (CHAR_BIT * j)) &
4770                                                 IXGBE_8_BIT_MASK);
4771                 }
4772         }
4773
4774         return 0;
4775 }
4776
4777 static int
4778 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4779                                 uint32_t index, uint32_t pool)
4780 {
4781         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4782         uint32_t enable_addr = 1;
4783
4784         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4785                              pool, enable_addr);
4786 }
4787
4788 static void
4789 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4790 {
4791         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4792
4793         ixgbe_clear_rar(hw, index);
4794 }
4795
4796 static void
4797 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4798 {
4799         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4800
4801         ixgbe_remove_rar(dev, 0);
4802
4803         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4804 }
4805
4806 static bool
4807 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4808 {
4809         if (strcmp(dev->device->driver->name, drv->driver.name))
4810                 return false;
4811
4812         return true;
4813 }
4814
4815 bool
4816 is_ixgbe_supported(struct rte_eth_dev *dev)
4817 {
4818         return is_device_supported(dev, &rte_ixgbe_pmd);
4819 }
4820
4821 static int
4822 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4823 {
4824         uint32_t hlreg0;
4825         uint32_t maxfrs;
4826         struct ixgbe_hw *hw;
4827         struct rte_eth_dev_info dev_info;
4828         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4829         struct rte_eth_dev_data *dev_data = dev->data;
4830
4831         ixgbe_dev_info_get(dev, &dev_info);
4832
4833         /* check that mtu is within the allowed range */
4834         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4835                 return -EINVAL;
4836
4837         /* If device is started, refuse mtu that requires the support of
4838          * scattered packets when this feature has not been enabled before.
4839          */
4840         if (dev_data->dev_started && !dev_data->scattered_rx &&
4841             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4842              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4843                 PMD_INIT_LOG(ERR, "Stop port first.");
4844                 return -EINVAL;
4845         }
4846
4847         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4848         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4849
4850         /* switch to jumbo mode if needed */
4851         if (frame_size > ETHER_MAX_LEN) {
4852                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4853                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4854         } else {
4855                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4856                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4857         }
4858         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4859
4860         /* update max frame size */
4861         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4862
4863         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4864         maxfrs &= 0x0000FFFF;
4865         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4866         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4867
4868         return 0;
4869 }
4870
4871 /*
4872  * Virtual Function operations
4873  */
4874 static void
4875 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4876 {
4877         PMD_INIT_FUNC_TRACE();
4878
4879         /* Clear interrupt mask to stop from interrupts being generated */
4880         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4881
4882         IXGBE_WRITE_FLUSH(hw);
4883 }
4884
4885 static void
4886 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4887 {
4888         PMD_INIT_FUNC_TRACE();
4889
4890         /* VF enable interrupt autoclean */
4891         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4892         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4893         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4894
4895         IXGBE_WRITE_FLUSH(hw);
4896 }
4897
4898 static int
4899 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4900 {
4901         struct rte_eth_conf *conf = &dev->data->dev_conf;
4902         struct ixgbe_adapter *adapter =
4903                         (struct ixgbe_adapter *)dev->data->dev_private;
4904
4905         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4906                      dev->data->port_id);
4907
4908         /*
4909          * VF has no ability to enable/disable HW CRC
4910          * Keep the persistent behavior the same as Host PF
4911          */
4912 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4913         if (!conf->rxmode.hw_strip_crc) {
4914                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4915                 conf->rxmode.hw_strip_crc = 1;
4916         }
4917 #else
4918         if (conf->rxmode.hw_strip_crc) {
4919                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4920                 conf->rxmode.hw_strip_crc = 0;
4921         }
4922 #endif
4923
4924         /*
4925          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4926          * allocation or vector Rx preconditions we will reset it.
4927          */
4928         adapter->rx_bulk_alloc_allowed = true;
4929         adapter->rx_vec_allowed = true;
4930
4931         return 0;
4932 }
4933
4934 static int
4935 ixgbevf_dev_start(struct rte_eth_dev *dev)
4936 {
4937         struct ixgbe_hw *hw =
4938                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939         uint32_t intr_vector = 0;
4940         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4941         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4942
4943         int err, mask = 0;
4944
4945         PMD_INIT_FUNC_TRACE();
4946
4947         hw->mac.ops.reset_hw(hw);
4948         hw->mac.get_link_status = true;
4949
4950         /* negotiate mailbox API version to use with the PF. */
4951         ixgbevf_negotiate_api(hw);
4952
4953         ixgbevf_dev_tx_init(dev);
4954
4955         /* This can fail when allocating mbufs for descriptor rings */
4956         err = ixgbevf_dev_rx_init(dev);
4957         if (err) {
4958                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4959                 ixgbe_dev_clear_queues(dev);
4960                 return err;
4961         }
4962
4963         /* Set vfta */
4964         ixgbevf_set_vfta_all(dev, 1);
4965
4966         /* Set HW strip */
4967         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4968                 ETH_VLAN_EXTEND_MASK;
4969         ixgbevf_vlan_offload_set(dev, mask);
4970
4971         ixgbevf_dev_rxtx_start(dev);
4972
4973         /* check and configure queue intr-vector mapping */
4974         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4975                 intr_vector = dev->data->nb_rx_queues;
4976                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4977                         return -1;
4978         }
4979
4980         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4981                 intr_handle->intr_vec =
4982                         rte_zmalloc("intr_vec",
4983                                     dev->data->nb_rx_queues * sizeof(int), 0);
4984                 if (intr_handle->intr_vec == NULL) {
4985                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4986                                      " intr_vec", dev->data->nb_rx_queues);
4987                         return -ENOMEM;
4988                 }
4989         }
4990         ixgbevf_configure_msix(dev);
4991
4992         rte_intr_enable(intr_handle);
4993
4994         /* Re-enable interrupt for VF */
4995         ixgbevf_intr_enable(hw);
4996
4997         return 0;
4998 }
4999
5000 static void
5001 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5002 {
5003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5004         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5005         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5006
5007         PMD_INIT_FUNC_TRACE();
5008
5009         ixgbevf_intr_disable(hw);
5010
5011         hw->adapter_stopped = 1;
5012         ixgbe_stop_adapter(hw);
5013
5014         /*
5015           * Clear what we set, but we still keep shadow_vfta to
5016           * restore after device starts
5017           */
5018         ixgbevf_set_vfta_all(dev, 0);
5019
5020         /* Clear stored conf */
5021         dev->data->scattered_rx = 0;
5022
5023         ixgbe_dev_clear_queues(dev);
5024
5025         /* Clean datapath event and queue/vec mapping */
5026         rte_intr_efd_disable(intr_handle);
5027         if (intr_handle->intr_vec != NULL) {
5028                 rte_free(intr_handle->intr_vec);
5029                 intr_handle->intr_vec = NULL;
5030         }
5031 }
5032
5033 static void
5034 ixgbevf_dev_close(struct rte_eth_dev *dev)
5035 {
5036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5037
5038         PMD_INIT_FUNC_TRACE();
5039
5040         ixgbe_reset_hw(hw);
5041
5042         ixgbevf_dev_stop(dev);
5043
5044         ixgbe_dev_free_queues(dev);
5045
5046         /**
5047          * Remove the VF MAC address ro ensure
5048          * that the VF traffic goes to the PF
5049          * after stop, close and detach of the VF
5050          **/
5051         ixgbevf_remove_mac_addr(dev, 0);
5052 }
5053
5054 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5055 {
5056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057         struct ixgbe_vfta *shadow_vfta =
5058                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5059         int i = 0, j = 0, vfta = 0, mask = 1;
5060
5061         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5062                 vfta = shadow_vfta->vfta[i];
5063                 if (vfta) {
5064                         mask = 1;
5065                         for (j = 0; j < 32; j++) {
5066                                 if (vfta & mask)
5067                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5068                                                        on, false);
5069                                 mask <<= 1;
5070                         }
5071                 }
5072         }
5073
5074 }
5075
5076 static int
5077 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5078 {
5079         struct ixgbe_hw *hw =
5080                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5081         struct ixgbe_vfta *shadow_vfta =
5082                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5083         uint32_t vid_idx = 0;
5084         uint32_t vid_bit = 0;
5085         int ret = 0;
5086
5087         PMD_INIT_FUNC_TRACE();
5088
5089         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5090         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5091         if (ret) {
5092                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5093                 return ret;
5094         }
5095         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5096         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5097
5098         /* Save what we set and retore it after device reset */
5099         if (on)
5100                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5101         else
5102                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5103
5104         return 0;
5105 }
5106
5107 static void
5108 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5109 {
5110         struct ixgbe_hw *hw =
5111                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5112         uint32_t ctrl;
5113
5114         PMD_INIT_FUNC_TRACE();
5115
5116         if (queue >= hw->mac.max_rx_queues)
5117                 return;
5118
5119         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5120         if (on)
5121                 ctrl |= IXGBE_RXDCTL_VME;
5122         else
5123                 ctrl &= ~IXGBE_RXDCTL_VME;
5124         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5125
5126         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5127 }
5128
5129 static void
5130 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5131 {
5132         struct ixgbe_hw *hw =
5133                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5134         uint16_t i;
5135         int on = 0;
5136
5137         /* VF function only support hw strip feature, others are not support */
5138         if (mask & ETH_VLAN_STRIP_MASK) {
5139                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5140
5141                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5142                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5143         }
5144 }
5145
5146 int
5147 ixgbe_vt_check(struct ixgbe_hw *hw)
5148 {
5149         uint32_t reg_val;
5150
5151         /* if Virtualization Technology is enabled */
5152         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5153         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5154                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5155                 return -1;
5156         }
5157
5158         return 0;
5159 }
5160
5161 static uint32_t
5162 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5163 {
5164         uint32_t vector = 0;
5165
5166         switch (hw->mac.mc_filter_type) {
5167         case 0:   /* use bits [47:36] of the address */
5168                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5169                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5170                 break;
5171         case 1:   /* use bits [46:35] of the address */
5172                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5173                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5174                 break;
5175         case 2:   /* use bits [45:34] of the address */
5176                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5177                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5178                 break;
5179         case 3:   /* use bits [43:32] of the address */
5180                 vector = ((uc_addr->addr_bytes[4]) |
5181                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5182                 break;
5183         default:  /* Invalid mc_filter_type */
5184                 break;
5185         }
5186
5187         /* vector can only be 12-bits or boundary will be exceeded */
5188         vector &= 0xFFF;
5189         return vector;
5190 }
5191
5192 static int
5193 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5194                         uint8_t on)
5195 {
5196         uint32_t vector;
5197         uint32_t uta_idx;
5198         uint32_t reg_val;
5199         uint32_t uta_shift;
5200         uint32_t rc;
5201         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5202         const uint32_t ixgbe_uta_bit_shift = 5;
5203         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5204         const uint32_t bit1 = 0x1;
5205
5206         struct ixgbe_hw *hw =
5207                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5208         struct ixgbe_uta_info *uta_info =
5209                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5210
5211         /* The UTA table only exists on 82599 hardware and newer */
5212         if (hw->mac.type < ixgbe_mac_82599EB)
5213                 return -ENOTSUP;
5214
5215         vector = ixgbe_uta_vector(hw, mac_addr);
5216         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5217         uta_shift = vector & ixgbe_uta_bit_mask;
5218
5219         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5220         if (rc == on)
5221                 return 0;
5222
5223         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5224         if (on) {
5225                 uta_info->uta_in_use++;
5226                 reg_val |= (bit1 << uta_shift);
5227                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5228         } else {
5229                 uta_info->uta_in_use--;
5230                 reg_val &= ~(bit1 << uta_shift);
5231                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5232         }
5233
5234         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5235
5236         if (uta_info->uta_in_use > 0)
5237                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5238                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5239         else
5240                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5241
5242         return 0;
5243 }
5244
5245 static int
5246 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5247 {
5248         int i;
5249         struct ixgbe_hw *hw =
5250                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5251         struct ixgbe_uta_info *uta_info =
5252                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5253
5254         /* The UTA table only exists on 82599 hardware and newer */
5255         if (hw->mac.type < ixgbe_mac_82599EB)
5256                 return -ENOTSUP;
5257
5258         if (on) {
5259                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5260                         uta_info->uta_shadow[i] = ~0;
5261                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5262                 }
5263         } else {
5264                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5265                         uta_info->uta_shadow[i] = 0;
5266                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5267                 }
5268         }
5269         return 0;
5270
5271 }
5272
5273 uint32_t
5274 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5275 {
5276         uint32_t new_val = orig_val;
5277
5278         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5279                 new_val |= IXGBE_VMOLR_AUPE;
5280         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5281                 new_val |= IXGBE_VMOLR_ROMPE;
5282         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5283                 new_val |= IXGBE_VMOLR_ROPE;
5284         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5285                 new_val |= IXGBE_VMOLR_BAM;
5286         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5287                 new_val |= IXGBE_VMOLR_MPE;
5288
5289         return new_val;
5290 }
5291
5292 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5293 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5294 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5295 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5296 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5297         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5298         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5299
5300 static int
5301 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5302                       struct rte_eth_mirror_conf *mirror_conf,
5303                       uint8_t rule_id, uint8_t on)
5304 {
5305         uint32_t mr_ctl, vlvf;
5306         uint32_t mp_lsb = 0;
5307         uint32_t mv_msb = 0;
5308         uint32_t mv_lsb = 0;
5309         uint32_t mp_msb = 0;
5310         uint8_t i = 0;
5311         int reg_index = 0;
5312         uint64_t vlan_mask = 0;
5313
5314         const uint8_t pool_mask_offset = 32;
5315         const uint8_t vlan_mask_offset = 32;
5316         const uint8_t dst_pool_offset = 8;
5317         const uint8_t rule_mr_offset  = 4;
5318         const uint8_t mirror_rule_mask = 0x0F;
5319
5320         struct ixgbe_mirror_info *mr_info =
5321                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5322         struct ixgbe_hw *hw =
5323                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5324         uint8_t mirror_type = 0;
5325
5326         if (ixgbe_vt_check(hw) < 0)
5327                 return -ENOTSUP;
5328
5329         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5330                 return -EINVAL;
5331
5332         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5333                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5334                             mirror_conf->rule_type);
5335                 return -EINVAL;
5336         }
5337
5338         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5339                 mirror_type |= IXGBE_MRCTL_VLME;
5340                 /* Check if vlan id is valid and find conresponding VLAN ID
5341                  * index in VLVF
5342                  */
5343                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5344                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5345                                 /* search vlan id related pool vlan filter
5346                                  * index
5347                                  */
5348                                 reg_index = ixgbe_find_vlvf_slot(
5349                                                 hw,
5350                                                 mirror_conf->vlan.vlan_id[i],
5351                                                 false);
5352                                 if (reg_index < 0)
5353                                         return -EINVAL;
5354                                 vlvf = IXGBE_READ_REG(hw,
5355                                                       IXGBE_VLVF(reg_index));
5356                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5357                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5358                                       mirror_conf->vlan.vlan_id[i]))
5359                                         vlan_mask |= (1ULL << reg_index);
5360                                 else
5361                                         return -EINVAL;
5362                         }
5363                 }
5364
5365                 if (on) {
5366                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5367                         mv_msb = vlan_mask >> vlan_mask_offset;
5368
5369                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5370                                                 mirror_conf->vlan.vlan_mask;
5371                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5372                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5373                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5374                                                 mirror_conf->vlan.vlan_id[i];
5375                         }
5376                 } else {
5377                         mv_lsb = 0;
5378                         mv_msb = 0;
5379                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5380                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5381                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5382                 }
5383         }
5384
5385         /**
5386          * if enable pool mirror, write related pool mask register,if disable
5387          * pool mirror, clear PFMRVM register
5388          */
5389         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5390                 mirror_type |= IXGBE_MRCTL_VPME;
5391                 if (on) {
5392                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5393                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5394                         mr_info->mr_conf[rule_id].pool_mask =
5395                                         mirror_conf->pool_mask;
5396
5397                 } else {
5398                         mp_lsb = 0;
5399                         mp_msb = 0;
5400                         mr_info->mr_conf[rule_id].pool_mask = 0;
5401                 }
5402         }
5403         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5404                 mirror_type |= IXGBE_MRCTL_UPME;
5405         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5406                 mirror_type |= IXGBE_MRCTL_DPME;
5407
5408         /* read  mirror control register and recalculate it */
5409         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5410
5411         if (on) {
5412                 mr_ctl |= mirror_type;
5413                 mr_ctl &= mirror_rule_mask;
5414                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5415         } else {
5416                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5417         }
5418
5419         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5420         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5421
5422         /* write mirrror control  register */
5423         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5424
5425         /* write pool mirrror control  register */
5426         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5427                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5428                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5429                                 mp_msb);
5430         }
5431         /* write VLAN mirrror control  register */
5432         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5433                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5434                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5435                                 mv_msb);
5436         }
5437
5438         return 0;
5439 }
5440
5441 static int
5442 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5443 {
5444         int mr_ctl = 0;
5445         uint32_t lsb_val = 0;
5446         uint32_t msb_val = 0;
5447         const uint8_t rule_mr_offset = 4;
5448
5449         struct ixgbe_hw *hw =
5450                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5451         struct ixgbe_mirror_info *mr_info =
5452                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5453
5454         if (ixgbe_vt_check(hw) < 0)
5455                 return -ENOTSUP;
5456
5457         memset(&mr_info->mr_conf[rule_id], 0,
5458                sizeof(struct rte_eth_mirror_conf));
5459
5460         /* clear PFVMCTL register */
5461         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5462
5463         /* clear pool mask register */
5464         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5465         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5466
5467         /* clear vlan mask register */
5468         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5469         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5470
5471         return 0;
5472 }
5473
5474 static int
5475 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5476 {
5477         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5478         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5479         uint32_t mask;
5480         struct ixgbe_hw *hw =
5481                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5482
5483         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5484         mask |= (1 << IXGBE_MISC_VEC_ID);
5485         RTE_SET_USED(queue_id);
5486         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5487
5488         rte_intr_enable(intr_handle);
5489
5490         return 0;
5491 }
5492
5493 static int
5494 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5495 {
5496         uint32_t mask;
5497         struct ixgbe_hw *hw =
5498                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5499
5500         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5501         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5502         RTE_SET_USED(queue_id);
5503         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5504
5505         return 0;
5506 }
5507
5508 static int
5509 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5510 {
5511         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5512         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5513         uint32_t mask;
5514         struct ixgbe_hw *hw =
5515                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5516         struct ixgbe_interrupt *intr =
5517                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5518
5519         if (queue_id < 16) {
5520                 ixgbe_disable_intr(hw);
5521                 intr->mask |= (1 << queue_id);
5522                 ixgbe_enable_intr(dev);
5523         } else if (queue_id < 32) {
5524                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5525                 mask &= (1 << queue_id);
5526                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5527         } else if (queue_id < 64) {
5528                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5529                 mask &= (1 << (queue_id - 32));
5530                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5531         }
5532         rte_intr_enable(intr_handle);
5533
5534         return 0;
5535 }
5536
5537 static int
5538 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5539 {
5540         uint32_t mask;
5541         struct ixgbe_hw *hw =
5542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5543         struct ixgbe_interrupt *intr =
5544                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5545
5546         if (queue_id < 16) {
5547                 ixgbe_disable_intr(hw);
5548                 intr->mask &= ~(1 << queue_id);
5549                 ixgbe_enable_intr(dev);
5550         } else if (queue_id < 32) {
5551                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5552                 mask &= ~(1 << queue_id);
5553                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5554         } else if (queue_id < 64) {
5555                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5556                 mask &= ~(1 << (queue_id - 32));
5557                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5558         }
5559
5560         return 0;
5561 }
5562
5563 static void
5564 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5565                      uint8_t queue, uint8_t msix_vector)
5566 {
5567         uint32_t tmp, idx;
5568
5569         if (direction == -1) {
5570                 /* other causes */
5571                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5572                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5573                 tmp &= ~0xFF;
5574                 tmp |= msix_vector;
5575                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5576         } else {
5577                 /* rx or tx cause */
5578                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5579                 idx = ((16 * (queue & 1)) + (8 * direction));
5580                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5581                 tmp &= ~(0xFF << idx);
5582                 tmp |= (msix_vector << idx);
5583                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5584         }
5585 }
5586
5587 /**
5588  * set the IVAR registers, mapping interrupt causes to vectors
5589  * @param hw
5590  *  pointer to ixgbe_hw struct
5591  * @direction
5592  *  0 for Rx, 1 for Tx, -1 for other causes
5593  * @queue
5594  *  queue to map the corresponding interrupt to
5595  * @msix_vector
5596  *  the vector to map to the corresponding queue
5597  */
5598 static void
5599 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5600                    uint8_t queue, uint8_t msix_vector)
5601 {
5602         uint32_t tmp, idx;
5603
5604         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5605         if (hw->mac.type == ixgbe_mac_82598EB) {
5606                 if (direction == -1)
5607                         direction = 0;
5608                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5609                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5610                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5611                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5612                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5613         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5614                         (hw->mac.type == ixgbe_mac_X540)) {
5615                 if (direction == -1) {
5616                         /* other causes */
5617                         idx = ((queue & 1) * 8);
5618                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5619                         tmp &= ~(0xFF << idx);
5620                         tmp |= (msix_vector << idx);
5621                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5622                 } else {
5623                         /* rx or tx causes */
5624                         idx = ((16 * (queue & 1)) + (8 * direction));
5625                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5626                         tmp &= ~(0xFF << idx);
5627                         tmp |= (msix_vector << idx);
5628                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5629                 }
5630         }
5631 }
5632
5633 static void
5634 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5635 {
5636         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5637         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5638         struct ixgbe_hw *hw =
5639                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5640         uint32_t q_idx;
5641         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5642
5643         /* Configure VF other cause ivar */
5644         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5645
5646         /* won't configure msix register if no mapping is done
5647          * between intr vector and event fd.
5648          */
5649         if (!rte_intr_dp_is_en(intr_handle))
5650                 return;
5651
5652         /* Configure all RX queues of VF */
5653         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5654                 /* Force all queue use vector 0,
5655                  * as IXGBE_VF_MAXMSIVECOTR = 1
5656                  */
5657                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5658                 intr_handle->intr_vec[q_idx] = vector_idx;
5659         }
5660 }
5661
5662 /**
5663  * Sets up the hardware to properly generate MSI-X interrupts
5664  * @hw
5665  *  board private structure
5666  */
5667 static void
5668 ixgbe_configure_msix(struct rte_eth_dev *dev)
5669 {
5670         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5671         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5672         struct ixgbe_hw *hw =
5673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5674         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5675         uint32_t vec = IXGBE_MISC_VEC_ID;
5676         uint32_t mask;
5677         uint32_t gpie;
5678
5679         /* won't configure msix register if no mapping is done
5680          * between intr vector and event fd
5681          */
5682         if (!rte_intr_dp_is_en(intr_handle))
5683                 return;
5684
5685         if (rte_intr_allow_others(intr_handle))
5686                 vec = base = IXGBE_RX_VEC_START;
5687
5688         /* setup GPIE for MSI-x mode */
5689         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5690         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5691                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5692         /* auto clearing and auto setting corresponding bits in EIMS
5693          * when MSI-X interrupt is triggered
5694          */
5695         if (hw->mac.type == ixgbe_mac_82598EB) {
5696                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5697         } else {
5698                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5699                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5700         }
5701         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5702
5703         /* Populate the IVAR table and set the ITR values to the
5704          * corresponding register.
5705          */
5706         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5707              queue_id++) {
5708                 /* by default, 1:1 mapping */
5709                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5710                 intr_handle->intr_vec[queue_id] = vec;
5711                 if (vec < base + intr_handle->nb_efd - 1)
5712                         vec++;
5713         }
5714
5715         switch (hw->mac.type) {
5716         case ixgbe_mac_82598EB:
5717                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5718                                    IXGBE_MISC_VEC_ID);
5719                 break;
5720         case ixgbe_mac_82599EB:
5721         case ixgbe_mac_X540:
5722                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5723                 break;
5724         default:
5725                 break;
5726         }
5727         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5728                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5729
5730         /* set up to autoclear timer, and the vectors */
5731         mask = IXGBE_EIMS_ENABLE_MASK;
5732         mask &= ~(IXGBE_EIMS_OTHER |
5733                   IXGBE_EIMS_MAILBOX |
5734                   IXGBE_EIMS_LSC);
5735
5736         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5737 }
5738
5739 int
5740 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5741                            uint16_t queue_idx, uint16_t tx_rate)
5742 {
5743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5744         uint32_t rf_dec, rf_int;
5745         uint32_t bcnrc_val;
5746         uint16_t link_speed = dev->data->dev_link.link_speed;
5747
5748         if (queue_idx >= hw->mac.max_tx_queues)
5749                 return -EINVAL;
5750
5751         if (tx_rate != 0) {
5752                 /* Calculate the rate factor values to set */
5753                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5754                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5755                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5756
5757                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5758                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5759                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5760                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5761         } else {
5762                 bcnrc_val = 0;
5763         }
5764
5765         /*
5766          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5767          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5768          * set as 0x4.
5769          */
5770         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5771                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5772                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5773                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5774                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5775         else
5776                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5777                         IXGBE_MMW_SIZE_DEFAULT);
5778
5779         /* Set RTTBCNRC of queue X */
5780         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5781         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5782         IXGBE_WRITE_FLUSH(hw);
5783
5784         return 0;
5785 }
5786
5787 static int
5788 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5789                      __attribute__((unused)) uint32_t index,
5790                      __attribute__((unused)) uint32_t pool)
5791 {
5792         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5793         int diag;
5794
5795         /*
5796          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5797          * operation. Trap this case to avoid exhausting the [very limited]
5798          * set of PF resources used to store VF MAC addresses.
5799          */
5800         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5801                 return -1;
5802         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5803         if (diag != 0)
5804                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5805                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5806                             mac_addr->addr_bytes[0],
5807                             mac_addr->addr_bytes[1],
5808                             mac_addr->addr_bytes[2],
5809                             mac_addr->addr_bytes[3],
5810                             mac_addr->addr_bytes[4],
5811                             mac_addr->addr_bytes[5],
5812                             diag);
5813         return diag;
5814 }
5815
5816 static void
5817 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5818 {
5819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5820         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5821         struct ether_addr *mac_addr;
5822         uint32_t i;
5823         int diag;
5824
5825         /*
5826          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5827          * not support the deletion of a given MAC address.
5828          * Instead, it imposes to delete all MAC addresses, then to add again
5829          * all MAC addresses with the exception of the one to be deleted.
5830          */
5831         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5832
5833         /*
5834          * Add again all MAC addresses, with the exception of the deleted one
5835          * and of the permanent MAC address.
5836          */
5837         for (i = 0, mac_addr = dev->data->mac_addrs;
5838              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5839                 /* Skip the deleted MAC address */
5840                 if (i == index)
5841                         continue;
5842                 /* Skip NULL MAC addresses */
5843                 if (is_zero_ether_addr(mac_addr))
5844                         continue;
5845                 /* Skip the permanent MAC address */
5846                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5847                         continue;
5848                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5849                 if (diag != 0)
5850                         PMD_DRV_LOG(ERR,
5851                                     "Adding again MAC address "
5852                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5853                                     "diag=%d",
5854                                     mac_addr->addr_bytes[0],
5855                                     mac_addr->addr_bytes[1],
5856                                     mac_addr->addr_bytes[2],
5857                                     mac_addr->addr_bytes[3],
5858                                     mac_addr->addr_bytes[4],
5859                                     mac_addr->addr_bytes[5],
5860                                     diag);
5861         }
5862 }
5863
5864 static void
5865 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5866 {
5867         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5868
5869         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5870 }
5871
5872 int
5873 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5874                         struct rte_eth_syn_filter *filter,
5875                         bool add)
5876 {
5877         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5878         struct ixgbe_filter_info *filter_info =
5879                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5880         uint32_t syn_info;
5881         uint32_t synqf;
5882
5883         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5884                 return -EINVAL;
5885
5886         syn_info = filter_info->syn_info;
5887
5888         if (add) {
5889                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5890                         return -EINVAL;
5891                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5892                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5893
5894                 if (filter->hig_pri)
5895                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5896                 else
5897                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5898         } else {
5899                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5900                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5901                         return -ENOENT;
5902                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5903         }
5904
5905         filter_info->syn_info = synqf;
5906         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5907         IXGBE_WRITE_FLUSH(hw);
5908         return 0;
5909 }
5910
5911 static int
5912 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5913                         struct rte_eth_syn_filter *filter)
5914 {
5915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5916         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5917
5918         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5919                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5920                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5921                 return 0;
5922         }
5923         return -ENOENT;
5924 }
5925
5926 static int
5927 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5928                         enum rte_filter_op filter_op,
5929                         void *arg)
5930 {
5931         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5932         int ret;
5933
5934         MAC_TYPE_FILTER_SUP(hw->mac.type);
5935
5936         if (filter_op == RTE_ETH_FILTER_NOP)
5937                 return 0;
5938
5939         if (arg == NULL) {
5940                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5941                             filter_op);
5942                 return -EINVAL;
5943         }
5944
5945         switch (filter_op) {
5946         case RTE_ETH_FILTER_ADD:
5947                 ret = ixgbe_syn_filter_set(dev,
5948                                 (struct rte_eth_syn_filter *)arg,
5949                                 TRUE);
5950                 break;
5951         case RTE_ETH_FILTER_DELETE:
5952                 ret = ixgbe_syn_filter_set(dev,
5953                                 (struct rte_eth_syn_filter *)arg,
5954                                 FALSE);
5955                 break;
5956         case RTE_ETH_FILTER_GET:
5957                 ret = ixgbe_syn_filter_get(dev,
5958                                 (struct rte_eth_syn_filter *)arg);
5959                 break;
5960         default:
5961                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5962                 ret = -EINVAL;
5963                 break;
5964         }
5965
5966         return ret;
5967 }
5968
5969
5970 static inline enum ixgbe_5tuple_protocol
5971 convert_protocol_type(uint8_t protocol_value)
5972 {
5973         if (protocol_value == IPPROTO_TCP)
5974                 return IXGBE_FILTER_PROTOCOL_TCP;
5975         else if (protocol_value == IPPROTO_UDP)
5976                 return IXGBE_FILTER_PROTOCOL_UDP;
5977         else if (protocol_value == IPPROTO_SCTP)
5978                 return IXGBE_FILTER_PROTOCOL_SCTP;
5979         else
5980                 return IXGBE_FILTER_PROTOCOL_NONE;
5981 }
5982
5983 /* inject a 5-tuple filter to HW */
5984 static inline void
5985 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5986                            struct ixgbe_5tuple_filter *filter)
5987 {
5988         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5989         int i;
5990         uint32_t ftqf, sdpqf;
5991         uint32_t l34timir = 0;
5992         uint8_t mask = 0xff;
5993
5994         i = filter->index;
5995
5996         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5997                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5998         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5999
6000         ftqf = (uint32_t)(filter->filter_info.proto &
6001                 IXGBE_FTQF_PROTOCOL_MASK);
6002         ftqf |= (uint32_t)((filter->filter_info.priority &
6003                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6004         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6005                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6006         if (filter->filter_info.dst_ip_mask == 0)
6007                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6008         if (filter->filter_info.src_port_mask == 0)
6009                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6010         if (filter->filter_info.dst_port_mask == 0)
6011                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6012         if (filter->filter_info.proto_mask == 0)
6013                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6014         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6015         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6016         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6017
6018         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6019         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6020         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6021         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6022
6023         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6024         l34timir |= (uint32_t)(filter->queue <<
6025                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6026         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6027 }
6028
6029 /*
6030  * add a 5tuple filter
6031  *
6032  * @param
6033  * dev: Pointer to struct rte_eth_dev.
6034  * index: the index the filter allocates.
6035  * filter: ponter to the filter that will be added.
6036  * rx_queue: the queue id the filter assigned to.
6037  *
6038  * @return
6039  *    - On success, zero.
6040  *    - On failure, a negative value.
6041  */
6042 static int
6043 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6044                         struct ixgbe_5tuple_filter *filter)
6045 {
6046         struct ixgbe_filter_info *filter_info =
6047                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6048         int i, idx, shift;
6049
6050         /*
6051          * look for an unused 5tuple filter index,
6052          * and insert the filter to list.
6053          */
6054         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6055                 idx = i / (sizeof(uint32_t) * NBBY);
6056                 shift = i % (sizeof(uint32_t) * NBBY);
6057                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6058                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6059                         filter->index = i;
6060                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6061                                           filter,
6062                                           entries);
6063                         break;
6064                 }
6065         }
6066         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6067                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6068                 return -ENOSYS;
6069         }
6070
6071         ixgbe_inject_5tuple_filter(dev, filter);
6072
6073         return 0;
6074 }
6075
6076 /*
6077  * remove a 5tuple filter
6078  *
6079  * @param
6080  * dev: Pointer to struct rte_eth_dev.
6081  * filter: the pointer of the filter will be removed.
6082  */
6083 static void
6084 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6085                         struct ixgbe_5tuple_filter *filter)
6086 {
6087         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6088         struct ixgbe_filter_info *filter_info =
6089                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6090         uint16_t index = filter->index;
6091
6092         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6093                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6094         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6095         rte_free(filter);
6096
6097         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6098         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6099         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6100         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6101         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6102 }
6103
6104 static int
6105 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6106 {
6107         struct ixgbe_hw *hw;
6108         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6109         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6110
6111         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6112
6113         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6114                 return -EINVAL;
6115
6116         /* refuse mtu that requires the support of scattered packets when this
6117          * feature has not been enabled before.
6118          */
6119         if (!rx_conf->enable_scatter &&
6120             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6121              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6122                 return -EINVAL;
6123
6124         /*
6125          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6126          * request of the version 2.0 of the mailbox API.
6127          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6128          * of the mailbox API.
6129          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6130          * prior to 3.11.33 which contains the following change:
6131          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6132          */
6133         ixgbevf_rlpml_set_vf(hw, max_frame);
6134
6135         /* update max frame size */
6136         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6137         return 0;
6138 }
6139
6140 static inline struct ixgbe_5tuple_filter *
6141 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6142                         struct ixgbe_5tuple_filter_info *key)
6143 {
6144         struct ixgbe_5tuple_filter *it;
6145
6146         TAILQ_FOREACH(it, filter_list, entries) {
6147                 if (memcmp(key, &it->filter_info,
6148                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6149                         return it;
6150                 }
6151         }
6152         return NULL;
6153 }
6154
6155 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6156 static inline int
6157 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6158                         struct ixgbe_5tuple_filter_info *filter_info)
6159 {
6160         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6161                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6162                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6163                 return -EINVAL;
6164
6165         switch (filter->dst_ip_mask) {
6166         case UINT32_MAX:
6167                 filter_info->dst_ip_mask = 0;
6168                 filter_info->dst_ip = filter->dst_ip;
6169                 break;
6170         case 0:
6171                 filter_info->dst_ip_mask = 1;
6172                 break;
6173         default:
6174                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6175                 return -EINVAL;
6176         }
6177
6178         switch (filter->src_ip_mask) {
6179         case UINT32_MAX:
6180                 filter_info->src_ip_mask = 0;
6181                 filter_info->src_ip = filter->src_ip;
6182                 break;
6183         case 0:
6184                 filter_info->src_ip_mask = 1;
6185                 break;
6186         default:
6187                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6188                 return -EINVAL;
6189         }
6190
6191         switch (filter->dst_port_mask) {
6192         case UINT16_MAX:
6193                 filter_info->dst_port_mask = 0;
6194                 filter_info->dst_port = filter->dst_port;
6195                 break;
6196         case 0:
6197                 filter_info->dst_port_mask = 1;
6198                 break;
6199         default:
6200                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6201                 return -EINVAL;
6202         }
6203
6204         switch (filter->src_port_mask) {
6205         case UINT16_MAX:
6206                 filter_info->src_port_mask = 0;
6207                 filter_info->src_port = filter->src_port;
6208                 break;
6209         case 0:
6210                 filter_info->src_port_mask = 1;
6211                 break;
6212         default:
6213                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6214                 return -EINVAL;
6215         }
6216
6217         switch (filter->proto_mask) {
6218         case UINT8_MAX:
6219                 filter_info->proto_mask = 0;
6220                 filter_info->proto =
6221                         convert_protocol_type(filter->proto);
6222                 break;
6223         case 0:
6224                 filter_info->proto_mask = 1;
6225                 break;
6226         default:
6227                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6228                 return -EINVAL;
6229         }
6230
6231         filter_info->priority = (uint8_t)filter->priority;
6232         return 0;
6233 }
6234
6235 /*
6236  * add or delete a ntuple filter
6237  *
6238  * @param
6239  * dev: Pointer to struct rte_eth_dev.
6240  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6241  * add: if true, add filter, if false, remove filter
6242  *
6243  * @return
6244  *    - On success, zero.
6245  *    - On failure, a negative value.
6246  */
6247 int
6248 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6249                         struct rte_eth_ntuple_filter *ntuple_filter,
6250                         bool add)
6251 {
6252         struct ixgbe_filter_info *filter_info =
6253                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6254         struct ixgbe_5tuple_filter_info filter_5tuple;
6255         struct ixgbe_5tuple_filter *filter;
6256         int ret;
6257
6258         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6259                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6260                 return -EINVAL;
6261         }
6262
6263         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6264         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6265         if (ret < 0)
6266                 return ret;
6267
6268         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6269                                          &filter_5tuple);
6270         if (filter != NULL && add) {
6271                 PMD_DRV_LOG(ERR, "filter exists.");
6272                 return -EEXIST;
6273         }
6274         if (filter == NULL && !add) {
6275                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6276                 return -ENOENT;
6277         }
6278
6279         if (add) {
6280                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6281                                 sizeof(struct ixgbe_5tuple_filter), 0);
6282                 if (filter == NULL)
6283                         return -ENOMEM;
6284                 (void)rte_memcpy(&filter->filter_info,
6285                                  &filter_5tuple,
6286                                  sizeof(struct ixgbe_5tuple_filter_info));
6287                 filter->queue = ntuple_filter->queue;
6288                 ret = ixgbe_add_5tuple_filter(dev, filter);
6289                 if (ret < 0) {
6290                         rte_free(filter);
6291                         return ret;
6292                 }
6293         } else
6294                 ixgbe_remove_5tuple_filter(dev, filter);
6295
6296         return 0;
6297 }
6298
6299 /*
6300  * get a ntuple filter
6301  *
6302  * @param
6303  * dev: Pointer to struct rte_eth_dev.
6304  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6305  *
6306  * @return
6307  *    - On success, zero.
6308  *    - On failure, a negative value.
6309  */
6310 static int
6311 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6312                         struct rte_eth_ntuple_filter *ntuple_filter)
6313 {
6314         struct ixgbe_filter_info *filter_info =
6315                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6316         struct ixgbe_5tuple_filter_info filter_5tuple;
6317         struct ixgbe_5tuple_filter *filter;
6318         int ret;
6319
6320         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6321                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6322                 return -EINVAL;
6323         }
6324
6325         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6326         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6327         if (ret < 0)
6328                 return ret;
6329
6330         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6331                                          &filter_5tuple);
6332         if (filter == NULL) {
6333                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6334                 return -ENOENT;
6335         }
6336         ntuple_filter->queue = filter->queue;
6337         return 0;
6338 }
6339
6340 /*
6341  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6342  * @dev: pointer to rte_eth_dev structure
6343  * @filter_op:operation will be taken.
6344  * @arg: a pointer to specific structure corresponding to the filter_op
6345  *
6346  * @return
6347  *    - On success, zero.
6348  *    - On failure, a negative value.
6349  */
6350 static int
6351 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6352                                 enum rte_filter_op filter_op,
6353                                 void *arg)
6354 {
6355         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6356         int ret;
6357
6358         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6359
6360         if (filter_op == RTE_ETH_FILTER_NOP)
6361                 return 0;
6362
6363         if (arg == NULL) {
6364                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6365                             filter_op);
6366                 return -EINVAL;
6367         }
6368
6369         switch (filter_op) {
6370         case RTE_ETH_FILTER_ADD:
6371                 ret = ixgbe_add_del_ntuple_filter(dev,
6372                         (struct rte_eth_ntuple_filter *)arg,
6373                         TRUE);
6374                 break;
6375         case RTE_ETH_FILTER_DELETE:
6376                 ret = ixgbe_add_del_ntuple_filter(dev,
6377                         (struct rte_eth_ntuple_filter *)arg,
6378                         FALSE);
6379                 break;
6380         case RTE_ETH_FILTER_GET:
6381                 ret = ixgbe_get_ntuple_filter(dev,
6382                         (struct rte_eth_ntuple_filter *)arg);
6383                 break;
6384         default:
6385                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6386                 ret = -EINVAL;
6387                 break;
6388         }
6389         return ret;
6390 }
6391
6392 int
6393 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6394                         struct rte_eth_ethertype_filter *filter,
6395                         bool add)
6396 {
6397         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6398         struct ixgbe_filter_info *filter_info =
6399                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6400         uint32_t etqf = 0;
6401         uint32_t etqs = 0;
6402         int ret;
6403         struct ixgbe_ethertype_filter ethertype_filter;
6404
6405         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6406                 return -EINVAL;
6407
6408         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6409                 filter->ether_type == ETHER_TYPE_IPv6) {
6410                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6411                         " ethertype filter.", filter->ether_type);
6412                 return -EINVAL;
6413         }
6414
6415         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6416                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6417                 return -EINVAL;
6418         }
6419         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6420                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6421                 return -EINVAL;
6422         }
6423
6424         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6425         if (ret >= 0 && add) {
6426                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6427                             filter->ether_type);
6428                 return -EEXIST;
6429         }
6430         if (ret < 0 && !add) {
6431                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6432                             filter->ether_type);
6433                 return -ENOENT;
6434         }
6435
6436         if (add) {
6437                 etqf = IXGBE_ETQF_FILTER_EN;
6438                 etqf |= (uint32_t)filter->ether_type;
6439                 etqs |= (uint32_t)((filter->queue <<
6440                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6441                                     IXGBE_ETQS_RX_QUEUE);
6442                 etqs |= IXGBE_ETQS_QUEUE_EN;
6443
6444                 ethertype_filter.ethertype = filter->ether_type;
6445                 ethertype_filter.etqf = etqf;
6446                 ethertype_filter.etqs = etqs;
6447                 ethertype_filter.conf = FALSE;
6448                 ret = ixgbe_ethertype_filter_insert(filter_info,
6449                                                     &ethertype_filter);
6450                 if (ret < 0) {
6451                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6452                         return -ENOSPC;
6453                 }
6454         } else {
6455                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6456                 if (ret < 0)
6457                         return -ENOSYS;
6458         }
6459         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6460         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6461         IXGBE_WRITE_FLUSH(hw);
6462
6463         return 0;
6464 }
6465
6466 static int
6467 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6468                         struct rte_eth_ethertype_filter *filter)
6469 {
6470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6471         struct ixgbe_filter_info *filter_info =
6472                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6473         uint32_t etqf, etqs;
6474         int ret;
6475
6476         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6477         if (ret < 0) {
6478                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6479                             filter->ether_type);
6480                 return -ENOENT;
6481         }
6482
6483         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6484         if (etqf & IXGBE_ETQF_FILTER_EN) {
6485                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6486                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6487                 filter->flags = 0;
6488                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6489                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6490                 return 0;
6491         }
6492         return -ENOENT;
6493 }
6494
6495 /*
6496  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6497  * @dev: pointer to rte_eth_dev structure
6498  * @filter_op:operation will be taken.
6499  * @arg: a pointer to specific structure corresponding to the filter_op
6500  */
6501 static int
6502 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6503                                 enum rte_filter_op filter_op,
6504                                 void *arg)
6505 {
6506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6507         int ret;
6508
6509         MAC_TYPE_FILTER_SUP(hw->mac.type);
6510
6511         if (filter_op == RTE_ETH_FILTER_NOP)
6512                 return 0;
6513
6514         if (arg == NULL) {
6515                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6516                             filter_op);
6517                 return -EINVAL;
6518         }
6519
6520         switch (filter_op) {
6521         case RTE_ETH_FILTER_ADD:
6522                 ret = ixgbe_add_del_ethertype_filter(dev,
6523                         (struct rte_eth_ethertype_filter *)arg,
6524                         TRUE);
6525                 break;
6526         case RTE_ETH_FILTER_DELETE:
6527                 ret = ixgbe_add_del_ethertype_filter(dev,
6528                         (struct rte_eth_ethertype_filter *)arg,
6529                         FALSE);
6530                 break;
6531         case RTE_ETH_FILTER_GET:
6532                 ret = ixgbe_get_ethertype_filter(dev,
6533                         (struct rte_eth_ethertype_filter *)arg);
6534                 break;
6535         default:
6536                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6537                 ret = -EINVAL;
6538                 break;
6539         }
6540         return ret;
6541 }
6542
6543 static int
6544 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6545                      enum rte_filter_type filter_type,
6546                      enum rte_filter_op filter_op,
6547                      void *arg)
6548 {
6549         int ret = 0;
6550
6551         switch (filter_type) {
6552         case RTE_ETH_FILTER_NTUPLE:
6553                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6554                 break;
6555         case RTE_ETH_FILTER_ETHERTYPE:
6556                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6557                 break;
6558         case RTE_ETH_FILTER_SYN:
6559                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6560                 break;
6561         case RTE_ETH_FILTER_FDIR:
6562                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6563                 break;
6564         case RTE_ETH_FILTER_L2_TUNNEL:
6565                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6566                 break;
6567         case RTE_ETH_FILTER_GENERIC:
6568                 if (filter_op != RTE_ETH_FILTER_GET)
6569                         return -EINVAL;
6570                 *(const void **)arg = &ixgbe_flow_ops;
6571                 break;
6572         default:
6573                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6574                                                         filter_type);
6575                 ret = -EINVAL;
6576                 break;
6577         }
6578
6579         return ret;
6580 }
6581
6582 static u8 *
6583 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6584                         u8 **mc_addr_ptr, u32 *vmdq)
6585 {
6586         u8 *mc_addr;
6587
6588         *vmdq = 0;
6589         mc_addr = *mc_addr_ptr;
6590         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6591         return mc_addr;
6592 }
6593
6594 static int
6595 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6596                           struct ether_addr *mc_addr_set,
6597                           uint32_t nb_mc_addr)
6598 {
6599         struct ixgbe_hw *hw;
6600         u8 *mc_addr_list;
6601
6602         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6603         mc_addr_list = (u8 *)mc_addr_set;
6604         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6605                                          ixgbe_dev_addr_list_itr, TRUE);
6606 }
6607
6608 static uint64_t
6609 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6610 {
6611         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6612         uint64_t systime_cycles;
6613
6614         switch (hw->mac.type) {
6615         case ixgbe_mac_X550:
6616         case ixgbe_mac_X550EM_x:
6617         case ixgbe_mac_X550EM_a:
6618                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6619                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6620                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6621                                 * NSEC_PER_SEC;
6622                 break;
6623         default:
6624                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6625                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6626                                 << 32;
6627         }
6628
6629         return systime_cycles;
6630 }
6631
6632 static uint64_t
6633 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6634 {
6635         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6636         uint64_t rx_tstamp_cycles;
6637
6638         switch (hw->mac.type) {
6639         case ixgbe_mac_X550:
6640         case ixgbe_mac_X550EM_x:
6641         case ixgbe_mac_X550EM_a:
6642                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6643                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6644                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6645                                 * NSEC_PER_SEC;
6646                 break;
6647         default:
6648                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6649                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6650                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6651                                 << 32;
6652         }
6653
6654         return rx_tstamp_cycles;
6655 }
6656
6657 static uint64_t
6658 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6659 {
6660         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6661         uint64_t tx_tstamp_cycles;
6662
6663         switch (hw->mac.type) {
6664         case ixgbe_mac_X550:
6665         case ixgbe_mac_X550EM_x:
6666         case ixgbe_mac_X550EM_a:
6667                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6668                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6669                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6670                                 * NSEC_PER_SEC;
6671                 break;
6672         default:
6673                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6674                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6675                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6676                                 << 32;
6677         }
6678
6679         return tx_tstamp_cycles;
6680 }
6681
6682 static void
6683 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6684 {
6685         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6686         struct ixgbe_adapter *adapter =
6687                 (struct ixgbe_adapter *)dev->data->dev_private;
6688         struct rte_eth_link link;
6689         uint32_t incval = 0;
6690         uint32_t shift = 0;
6691
6692         /* Get current link speed. */
6693         memset(&link, 0, sizeof(link));
6694         ixgbe_dev_link_update(dev, 1);
6695         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6696
6697         switch (link.link_speed) {
6698         case ETH_SPEED_NUM_100M:
6699                 incval = IXGBE_INCVAL_100;
6700                 shift = IXGBE_INCVAL_SHIFT_100;
6701                 break;
6702         case ETH_SPEED_NUM_1G:
6703                 incval = IXGBE_INCVAL_1GB;
6704                 shift = IXGBE_INCVAL_SHIFT_1GB;
6705                 break;
6706         case ETH_SPEED_NUM_10G:
6707         default:
6708                 incval = IXGBE_INCVAL_10GB;
6709                 shift = IXGBE_INCVAL_SHIFT_10GB;
6710                 break;
6711         }
6712
6713         switch (hw->mac.type) {
6714         case ixgbe_mac_X550:
6715         case ixgbe_mac_X550EM_x:
6716         case ixgbe_mac_X550EM_a:
6717                 /* Independent of link speed. */
6718                 incval = 1;
6719                 /* Cycles read will be interpreted as ns. */
6720                 shift = 0;
6721                 /* Fall-through */
6722         case ixgbe_mac_X540:
6723                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6724                 break;
6725         case ixgbe_mac_82599EB:
6726                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6727                 shift -= IXGBE_INCVAL_SHIFT_82599;
6728                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6729                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6730                 break;
6731         default:
6732                 /* Not supported. */
6733                 return;
6734         }
6735
6736         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6737         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6738         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6739
6740         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6741         adapter->systime_tc.cc_shift = shift;
6742         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6743
6744         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6745         adapter->rx_tstamp_tc.cc_shift = shift;
6746         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6747
6748         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6749         adapter->tx_tstamp_tc.cc_shift = shift;
6750         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6751 }
6752
6753 static int
6754 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6755 {
6756         struct ixgbe_adapter *adapter =
6757                         (struct ixgbe_adapter *)dev->data->dev_private;
6758
6759         adapter->systime_tc.nsec += delta;
6760         adapter->rx_tstamp_tc.nsec += delta;
6761         adapter->tx_tstamp_tc.nsec += delta;
6762
6763         return 0;
6764 }
6765
6766 static int
6767 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6768 {
6769         uint64_t ns;
6770         struct ixgbe_adapter *adapter =
6771                         (struct ixgbe_adapter *)dev->data->dev_private;
6772
6773         ns = rte_timespec_to_ns(ts);
6774         /* Set the timecounters to a new value. */
6775         adapter->systime_tc.nsec = ns;
6776         adapter->rx_tstamp_tc.nsec = ns;
6777         adapter->tx_tstamp_tc.nsec = ns;
6778
6779         return 0;
6780 }
6781
6782 static int
6783 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6784 {
6785         uint64_t ns, systime_cycles;
6786         struct ixgbe_adapter *adapter =
6787                         (struct ixgbe_adapter *)dev->data->dev_private;
6788
6789         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6790         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6791         *ts = rte_ns_to_timespec(ns);
6792
6793         return 0;
6794 }
6795
6796 static int
6797 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6798 {
6799         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6800         uint32_t tsync_ctl;
6801         uint32_t tsauxc;
6802
6803         /* Stop the timesync system time. */
6804         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6805         /* Reset the timesync system time value. */
6806         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6807         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6808
6809         /* Enable system time for platforms where it isn't on by default. */
6810         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6811         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6812         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6813
6814         ixgbe_start_timecounters(dev);
6815
6816         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6817         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6818                         (ETHER_TYPE_1588 |
6819                          IXGBE_ETQF_FILTER_EN |
6820                          IXGBE_ETQF_1588));
6821
6822         /* Enable timestamping of received PTP packets. */
6823         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6824         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6825         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6826
6827         /* Enable timestamping of transmitted PTP packets. */
6828         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6829         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6830         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6831
6832         IXGBE_WRITE_FLUSH(hw);
6833
6834         return 0;
6835 }
6836
6837 static int
6838 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6839 {
6840         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6841         uint32_t tsync_ctl;
6842
6843         /* Disable timestamping of transmitted PTP packets. */
6844         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6845         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6846         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6847
6848         /* Disable timestamping of received PTP packets. */
6849         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6850         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6851         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6852
6853         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6854         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6855
6856         /* Stop incrementating the System Time registers. */
6857         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6858
6859         return 0;
6860 }
6861
6862 static int
6863 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6864                                  struct timespec *timestamp,
6865                                  uint32_t flags __rte_unused)
6866 {
6867         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6868         struct ixgbe_adapter *adapter =
6869                 (struct ixgbe_adapter *)dev->data->dev_private;
6870         uint32_t tsync_rxctl;
6871         uint64_t rx_tstamp_cycles;
6872         uint64_t ns;
6873
6874         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6875         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6876                 return -EINVAL;
6877
6878         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6879         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6880         *timestamp = rte_ns_to_timespec(ns);
6881
6882         return  0;
6883 }
6884
6885 static int
6886 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6887                                  struct timespec *timestamp)
6888 {
6889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6890         struct ixgbe_adapter *adapter =
6891                 (struct ixgbe_adapter *)dev->data->dev_private;
6892         uint32_t tsync_txctl;
6893         uint64_t tx_tstamp_cycles;
6894         uint64_t ns;
6895
6896         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6897         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6898                 return -EINVAL;
6899
6900         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6901         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6902         *timestamp = rte_ns_to_timespec(ns);
6903
6904         return 0;
6905 }
6906
6907 static int
6908 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6909 {
6910         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6911         int count = 0;
6912         int g_ind = 0;
6913         const struct reg_info *reg_group;
6914         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6915                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6916
6917         while ((reg_group = reg_set[g_ind++]))
6918                 count += ixgbe_regs_group_count(reg_group);
6919
6920         return count;
6921 }
6922
6923 static int
6924 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6925 {
6926         int count = 0;
6927         int g_ind = 0;
6928         const struct reg_info *reg_group;
6929
6930         while ((reg_group = ixgbevf_regs[g_ind++]))
6931                 count += ixgbe_regs_group_count(reg_group);
6932
6933         return count;
6934 }
6935
6936 static int
6937 ixgbe_get_regs(struct rte_eth_dev *dev,
6938               struct rte_dev_reg_info *regs)
6939 {
6940         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6941         uint32_t *data = regs->data;
6942         int g_ind = 0;
6943         int count = 0;
6944         const struct reg_info *reg_group;
6945         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6946                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6947
6948         if (data == NULL) {
6949                 regs->length = ixgbe_get_reg_length(dev);
6950                 regs->width = sizeof(uint32_t);
6951                 return 0;
6952         }
6953
6954         /* Support only full register dump */
6955         if ((regs->length == 0) ||
6956             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6957                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6958                         hw->device_id;
6959                 while ((reg_group = reg_set[g_ind++]))
6960                         count += ixgbe_read_regs_group(dev, &data[count],
6961                                 reg_group);
6962                 return 0;
6963         }
6964
6965         return -ENOTSUP;
6966 }
6967
6968 static int
6969 ixgbevf_get_regs(struct rte_eth_dev *dev,
6970                 struct rte_dev_reg_info *regs)
6971 {
6972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6973         uint32_t *data = regs->data;
6974         int g_ind = 0;
6975         int count = 0;
6976         const struct reg_info *reg_group;
6977
6978         if (data == NULL) {
6979                 regs->length = ixgbevf_get_reg_length(dev);
6980                 regs->width = sizeof(uint32_t);
6981                 return 0;
6982         }
6983
6984         /* Support only full register dump */
6985         if ((regs->length == 0) ||
6986             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6987                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6988                         hw->device_id;
6989                 while ((reg_group = ixgbevf_regs[g_ind++]))
6990                         count += ixgbe_read_regs_group(dev, &data[count],
6991                                                       reg_group);
6992                 return 0;
6993         }
6994
6995         return -ENOTSUP;
6996 }
6997
6998 static int
6999 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7000 {
7001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7002
7003         /* Return unit is byte count */
7004         return hw->eeprom.word_size * 2;
7005 }
7006
7007 static int
7008 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7009                 struct rte_dev_eeprom_info *in_eeprom)
7010 {
7011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7012         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7013         uint16_t *data = in_eeprom->data;
7014         int first, length;
7015
7016         first = in_eeprom->offset >> 1;
7017         length = in_eeprom->length >> 1;
7018         if ((first > hw->eeprom.word_size) ||
7019             ((first + length) > hw->eeprom.word_size))
7020                 return -EINVAL;
7021
7022         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7023
7024         return eeprom->ops.read_buffer(hw, first, length, data);
7025 }
7026
7027 static int
7028 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7029                 struct rte_dev_eeprom_info *in_eeprom)
7030 {
7031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7032         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7033         uint16_t *data = in_eeprom->data;
7034         int first, length;
7035
7036         first = in_eeprom->offset >> 1;
7037         length = in_eeprom->length >> 1;
7038         if ((first > hw->eeprom.word_size) ||
7039             ((first + length) > hw->eeprom.word_size))
7040                 return -EINVAL;
7041
7042         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7043
7044         return eeprom->ops.write_buffer(hw,  first, length, data);
7045 }
7046
7047 uint16_t
7048 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7049         switch (mac_type) {
7050         case ixgbe_mac_X550:
7051         case ixgbe_mac_X550EM_x:
7052         case ixgbe_mac_X550EM_a:
7053                 return ETH_RSS_RETA_SIZE_512;
7054         case ixgbe_mac_X550_vf:
7055         case ixgbe_mac_X550EM_x_vf:
7056         case ixgbe_mac_X550EM_a_vf:
7057                 return ETH_RSS_RETA_SIZE_64;
7058         default:
7059                 return ETH_RSS_RETA_SIZE_128;
7060         }
7061 }
7062
7063 uint32_t
7064 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7065         switch (mac_type) {
7066         case ixgbe_mac_X550:
7067         case ixgbe_mac_X550EM_x:
7068         case ixgbe_mac_X550EM_a:
7069                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7070                         return IXGBE_RETA(reta_idx >> 2);
7071                 else
7072                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7073         case ixgbe_mac_X550_vf:
7074         case ixgbe_mac_X550EM_x_vf:
7075         case ixgbe_mac_X550EM_a_vf:
7076                 return IXGBE_VFRETA(reta_idx >> 2);
7077         default:
7078                 return IXGBE_RETA(reta_idx >> 2);
7079         }
7080 }
7081
7082 uint32_t
7083 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7084         switch (mac_type) {
7085         case ixgbe_mac_X550_vf:
7086         case ixgbe_mac_X550EM_x_vf:
7087         case ixgbe_mac_X550EM_a_vf:
7088                 return IXGBE_VFMRQC;
7089         default:
7090                 return IXGBE_MRQC;
7091         }
7092 }
7093
7094 uint32_t
7095 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7096         switch (mac_type) {
7097         case ixgbe_mac_X550_vf:
7098         case ixgbe_mac_X550EM_x_vf:
7099         case ixgbe_mac_X550EM_a_vf:
7100                 return IXGBE_VFRSSRK(i);
7101         default:
7102                 return IXGBE_RSSRK(i);
7103         }
7104 }
7105
7106 bool
7107 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7108         switch (mac_type) {
7109         case ixgbe_mac_82599_vf:
7110         case ixgbe_mac_X540_vf:
7111                 return 0;
7112         default:
7113                 return 1;
7114         }
7115 }
7116
7117 static int
7118 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7119                         struct rte_eth_dcb_info *dcb_info)
7120 {
7121         struct ixgbe_dcb_config *dcb_config =
7122                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7123         struct ixgbe_dcb_tc_config *tc;
7124         uint8_t i, j;
7125
7126         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7127                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7128         else
7129                 dcb_info->nb_tcs = 1;
7130
7131         if (dcb_config->vt_mode) { /* vt is enabled*/
7132                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7133                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7134                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7135                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7136                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7137                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7138                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7139                                                 i * dcb_info->nb_tcs + j;
7140                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7141                                 dcb_info->tc_queue.tc_txq[i][j].base =
7142                                                 i * dcb_info->nb_tcs + j;
7143                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7144                         }
7145                 }
7146         } else { /* vt is disabled*/
7147                 struct rte_eth_dcb_rx_conf *rx_conf =
7148                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7149                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7150                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7151                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7152                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7153                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7154                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7155                         }
7156                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7157                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7158                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7159                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7160                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7161                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7162                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7163                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7164                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7165                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7166                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7167                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7168                         }
7169                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7170                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7171                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7172                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7173                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7174                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7175                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7176                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7177                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7178                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7179                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7180                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7181                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7182                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7183                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7184                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7185                 }
7186         }
7187         for (i = 0; i < dcb_info->nb_tcs; i++) {
7188                 tc = &dcb_config->tc_config[i];
7189                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7190         }
7191         return 0;
7192 }
7193
7194 /* Update e-tag ether type */
7195 static int
7196 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7197                             uint16_t ether_type)
7198 {
7199         uint32_t etag_etype;
7200
7201         if (hw->mac.type != ixgbe_mac_X550 &&
7202             hw->mac.type != ixgbe_mac_X550EM_x &&
7203             hw->mac.type != ixgbe_mac_X550EM_a) {
7204                 return -ENOTSUP;
7205         }
7206
7207         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7208         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7209         etag_etype |= ether_type;
7210         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7211         IXGBE_WRITE_FLUSH(hw);
7212
7213         return 0;
7214 }
7215
7216 /* Config l2 tunnel ether type */
7217 static int
7218 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7219                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7220 {
7221         int ret = 0;
7222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7223         struct ixgbe_l2_tn_info *l2_tn_info =
7224                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7225
7226         if (l2_tunnel == NULL)
7227                 return -EINVAL;
7228
7229         switch (l2_tunnel->l2_tunnel_type) {
7230         case RTE_L2_TUNNEL_TYPE_E_TAG:
7231                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7232                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7233                 break;
7234         default:
7235                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7236                 ret = -EINVAL;
7237                 break;
7238         }
7239
7240         return ret;
7241 }
7242
7243 /* Enable e-tag tunnel */
7244 static int
7245 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7246 {
7247         uint32_t etag_etype;
7248
7249         if (hw->mac.type != ixgbe_mac_X550 &&
7250             hw->mac.type != ixgbe_mac_X550EM_x &&
7251             hw->mac.type != ixgbe_mac_X550EM_a) {
7252                 return -ENOTSUP;
7253         }
7254
7255         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7256         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7257         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7258         IXGBE_WRITE_FLUSH(hw);
7259
7260         return 0;
7261 }
7262
7263 /* Enable l2 tunnel */
7264 static int
7265 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7266                            enum rte_eth_tunnel_type l2_tunnel_type)
7267 {
7268         int ret = 0;
7269         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7270         struct ixgbe_l2_tn_info *l2_tn_info =
7271                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7272
7273         switch (l2_tunnel_type) {
7274         case RTE_L2_TUNNEL_TYPE_E_TAG:
7275                 l2_tn_info->e_tag_en = TRUE;
7276                 ret = ixgbe_e_tag_enable(hw);
7277                 break;
7278         default:
7279                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7280                 ret = -EINVAL;
7281                 break;
7282         }
7283
7284         return ret;
7285 }
7286
7287 /* Disable e-tag tunnel */
7288 static int
7289 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7290 {
7291         uint32_t etag_etype;
7292
7293         if (hw->mac.type != ixgbe_mac_X550 &&
7294             hw->mac.type != ixgbe_mac_X550EM_x &&
7295             hw->mac.type != ixgbe_mac_X550EM_a) {
7296                 return -ENOTSUP;
7297         }
7298
7299         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7300         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7301         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7302         IXGBE_WRITE_FLUSH(hw);
7303
7304         return 0;
7305 }
7306
7307 /* Disable l2 tunnel */
7308 static int
7309 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7310                             enum rte_eth_tunnel_type l2_tunnel_type)
7311 {
7312         int ret = 0;
7313         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7314         struct ixgbe_l2_tn_info *l2_tn_info =
7315                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7316
7317         switch (l2_tunnel_type) {
7318         case RTE_L2_TUNNEL_TYPE_E_TAG:
7319                 l2_tn_info->e_tag_en = FALSE;
7320                 ret = ixgbe_e_tag_disable(hw);
7321                 break;
7322         default:
7323                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7324                 ret = -EINVAL;
7325                 break;
7326         }
7327
7328         return ret;
7329 }
7330
7331 static int
7332 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7333                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7334 {
7335         int ret = 0;
7336         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7337         uint32_t i, rar_entries;
7338         uint32_t rar_low, rar_high;
7339
7340         if (hw->mac.type != ixgbe_mac_X550 &&
7341             hw->mac.type != ixgbe_mac_X550EM_x &&
7342             hw->mac.type != ixgbe_mac_X550EM_a) {
7343                 return -ENOTSUP;
7344         }
7345
7346         rar_entries = ixgbe_get_num_rx_addrs(hw);
7347
7348         for (i = 1; i < rar_entries; i++) {
7349                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7350                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7351                 if ((rar_high & IXGBE_RAH_AV) &&
7352                     (rar_high & IXGBE_RAH_ADTYPE) &&
7353                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7354                      l2_tunnel->tunnel_id)) {
7355                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7356                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7357
7358                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7359
7360                         return ret;
7361                 }
7362         }
7363
7364         return ret;
7365 }
7366
7367 static int
7368 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7369                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7370 {
7371         int ret = 0;
7372         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7373         uint32_t i, rar_entries;
7374         uint32_t rar_low, rar_high;
7375
7376         if (hw->mac.type != ixgbe_mac_X550 &&
7377             hw->mac.type != ixgbe_mac_X550EM_x &&
7378             hw->mac.type != ixgbe_mac_X550EM_a) {
7379                 return -ENOTSUP;
7380         }
7381
7382         /* One entry for one tunnel. Try to remove potential existing entry. */
7383         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7384
7385         rar_entries = ixgbe_get_num_rx_addrs(hw);
7386
7387         for (i = 1; i < rar_entries; i++) {
7388                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7389                 if (rar_high & IXGBE_RAH_AV) {
7390                         continue;
7391                 } else {
7392                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7393                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7394                         rar_low = l2_tunnel->tunnel_id;
7395
7396                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7397                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7398
7399                         return ret;
7400                 }
7401         }
7402
7403         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7404                      " Please remove a rule before adding a new one.");
7405         return -EINVAL;
7406 }
7407
7408 static inline struct ixgbe_l2_tn_filter *
7409 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7410                           struct ixgbe_l2_tn_key *key)
7411 {
7412         int ret;
7413
7414         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7415         if (ret < 0)
7416                 return NULL;
7417
7418         return l2_tn_info->hash_map[ret];
7419 }
7420
7421 static inline int
7422 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7423                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7424 {
7425         int ret;
7426
7427         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7428                                &l2_tn_filter->key);
7429
7430         if (ret < 0) {
7431                 PMD_DRV_LOG(ERR,
7432                             "Failed to insert L2 tunnel filter"
7433                             " to hash table %d!",
7434                             ret);
7435                 return ret;
7436         }
7437
7438         l2_tn_info->hash_map[ret] = l2_tn_filter;
7439
7440         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7441
7442         return 0;
7443 }
7444
7445 static inline int
7446 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7447                           struct ixgbe_l2_tn_key *key)
7448 {
7449         int ret;
7450         struct ixgbe_l2_tn_filter *l2_tn_filter;
7451
7452         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7453
7454         if (ret < 0) {
7455                 PMD_DRV_LOG(ERR,
7456                             "No such L2 tunnel filter to delete %d!",
7457                             ret);
7458                 return ret;
7459         }
7460
7461         l2_tn_filter = l2_tn_info->hash_map[ret];
7462         l2_tn_info->hash_map[ret] = NULL;
7463
7464         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7465         rte_free(l2_tn_filter);
7466
7467         return 0;
7468 }
7469
7470 /* Add l2 tunnel filter */
7471 int
7472 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7473                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7474                                bool restore)
7475 {
7476         int ret;
7477         struct ixgbe_l2_tn_info *l2_tn_info =
7478                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7479         struct ixgbe_l2_tn_key key;
7480         struct ixgbe_l2_tn_filter *node;
7481
7482         if (!restore) {
7483                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7484                 key.tn_id = l2_tunnel->tunnel_id;
7485
7486                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7487
7488                 if (node) {
7489                         PMD_DRV_LOG(ERR,
7490                                     "The L2 tunnel filter already exists!");
7491                         return -EINVAL;
7492                 }
7493
7494                 node = rte_zmalloc("ixgbe_l2_tn",
7495                                    sizeof(struct ixgbe_l2_tn_filter),
7496                                    0);
7497                 if (!node)
7498                         return -ENOMEM;
7499
7500                 (void)rte_memcpy(&node->key,
7501                                  &key,
7502                                  sizeof(struct ixgbe_l2_tn_key));
7503                 node->pool = l2_tunnel->pool;
7504                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7505                 if (ret < 0) {
7506                         rte_free(node);
7507                         return ret;
7508                 }
7509         }
7510
7511         switch (l2_tunnel->l2_tunnel_type) {
7512         case RTE_L2_TUNNEL_TYPE_E_TAG:
7513                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7514                 break;
7515         default:
7516                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7517                 ret = -EINVAL;
7518                 break;
7519         }
7520
7521         if ((!restore) && (ret < 0))
7522                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7523
7524         return ret;
7525 }
7526
7527 /* Delete l2 tunnel filter */
7528 int
7529 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7530                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7531 {
7532         int ret;
7533         struct ixgbe_l2_tn_info *l2_tn_info =
7534                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7535         struct ixgbe_l2_tn_key key;
7536
7537         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7538         key.tn_id = l2_tunnel->tunnel_id;
7539         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7540         if (ret < 0)
7541                 return ret;
7542
7543         switch (l2_tunnel->l2_tunnel_type) {
7544         case RTE_L2_TUNNEL_TYPE_E_TAG:
7545                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7546                 break;
7547         default:
7548                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7549                 ret = -EINVAL;
7550                 break;
7551         }
7552
7553         return ret;
7554 }
7555
7556 /**
7557  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7558  * @dev: pointer to rte_eth_dev structure
7559  * @filter_op:operation will be taken.
7560  * @arg: a pointer to specific structure corresponding to the filter_op
7561  */
7562 static int
7563 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7564                                   enum rte_filter_op filter_op,
7565                                   void *arg)
7566 {
7567         int ret;
7568
7569         if (filter_op == RTE_ETH_FILTER_NOP)
7570                 return 0;
7571
7572         if (arg == NULL) {
7573                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7574                             filter_op);
7575                 return -EINVAL;
7576         }
7577
7578         switch (filter_op) {
7579         case RTE_ETH_FILTER_ADD:
7580                 ret = ixgbe_dev_l2_tunnel_filter_add
7581                         (dev,
7582                          (struct rte_eth_l2_tunnel_conf *)arg,
7583                          FALSE);
7584                 break;
7585         case RTE_ETH_FILTER_DELETE:
7586                 ret = ixgbe_dev_l2_tunnel_filter_del
7587                         (dev,
7588                          (struct rte_eth_l2_tunnel_conf *)arg);
7589                 break;
7590         default:
7591                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7592                 ret = -EINVAL;
7593                 break;
7594         }
7595         return ret;
7596 }
7597
7598 static int
7599 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7600 {
7601         int ret = 0;
7602         uint32_t ctrl;
7603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7604
7605         if (hw->mac.type != ixgbe_mac_X550 &&
7606             hw->mac.type != ixgbe_mac_X550EM_x &&
7607             hw->mac.type != ixgbe_mac_X550EM_a) {
7608                 return -ENOTSUP;
7609         }
7610
7611         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7612         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7613         if (en)
7614                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7615         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7616
7617         return ret;
7618 }
7619
7620 /* Enable l2 tunnel forwarding */
7621 static int
7622 ixgbe_dev_l2_tunnel_forwarding_enable
7623         (struct rte_eth_dev *dev,
7624          enum rte_eth_tunnel_type l2_tunnel_type)
7625 {
7626         struct ixgbe_l2_tn_info *l2_tn_info =
7627                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7628         int ret = 0;
7629
7630         switch (l2_tunnel_type) {
7631         case RTE_L2_TUNNEL_TYPE_E_TAG:
7632                 l2_tn_info->e_tag_fwd_en = TRUE;
7633                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7634                 break;
7635         default:
7636                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7637                 ret = -EINVAL;
7638                 break;
7639         }
7640
7641         return ret;
7642 }
7643
7644 /* Disable l2 tunnel forwarding */
7645 static int
7646 ixgbe_dev_l2_tunnel_forwarding_disable
7647         (struct rte_eth_dev *dev,
7648          enum rte_eth_tunnel_type l2_tunnel_type)
7649 {
7650         struct ixgbe_l2_tn_info *l2_tn_info =
7651                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7652         int ret = 0;
7653
7654         switch (l2_tunnel_type) {
7655         case RTE_L2_TUNNEL_TYPE_E_TAG:
7656                 l2_tn_info->e_tag_fwd_en = FALSE;
7657                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7658                 break;
7659         default:
7660                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7661                 ret = -EINVAL;
7662                 break;
7663         }
7664
7665         return ret;
7666 }
7667
7668 static int
7669 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7670                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7671                              bool en)
7672 {
7673         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7674         int ret = 0;
7675         uint32_t vmtir, vmvir;
7676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7677
7678         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7679                 PMD_DRV_LOG(ERR,
7680                             "VF id %u should be less than %u",
7681                             l2_tunnel->vf_id,
7682                             pci_dev->max_vfs);
7683                 return -EINVAL;
7684         }
7685
7686         if (hw->mac.type != ixgbe_mac_X550 &&
7687             hw->mac.type != ixgbe_mac_X550EM_x &&
7688             hw->mac.type != ixgbe_mac_X550EM_a) {
7689                 return -ENOTSUP;
7690         }
7691
7692         if (en)
7693                 vmtir = l2_tunnel->tunnel_id;
7694         else
7695                 vmtir = 0;
7696
7697         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7698
7699         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7700         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7701         if (en)
7702                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7703         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7704
7705         return ret;
7706 }
7707
7708 /* Enable l2 tunnel tag insertion */
7709 static int
7710 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7711                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7712 {
7713         int ret = 0;
7714
7715         switch (l2_tunnel->l2_tunnel_type) {
7716         case RTE_L2_TUNNEL_TYPE_E_TAG:
7717                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7718                 break;
7719         default:
7720                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7721                 ret = -EINVAL;
7722                 break;
7723         }
7724
7725         return ret;
7726 }
7727
7728 /* Disable l2 tunnel tag insertion */
7729 static int
7730 ixgbe_dev_l2_tunnel_insertion_disable
7731         (struct rte_eth_dev *dev,
7732          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7733 {
7734         int ret = 0;
7735
7736         switch (l2_tunnel->l2_tunnel_type) {
7737         case RTE_L2_TUNNEL_TYPE_E_TAG:
7738                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7739                 break;
7740         default:
7741                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7742                 ret = -EINVAL;
7743                 break;
7744         }
7745
7746         return ret;
7747 }
7748
7749 static int
7750 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7751                              bool en)
7752 {
7753         int ret = 0;
7754         uint32_t qde;
7755         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7756
7757         if (hw->mac.type != ixgbe_mac_X550 &&
7758             hw->mac.type != ixgbe_mac_X550EM_x &&
7759             hw->mac.type != ixgbe_mac_X550EM_a) {
7760                 return -ENOTSUP;
7761         }
7762
7763         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7764         if (en)
7765                 qde |= IXGBE_QDE_STRIP_TAG;
7766         else
7767                 qde &= ~IXGBE_QDE_STRIP_TAG;
7768         qde &= ~IXGBE_QDE_READ;
7769         qde |= IXGBE_QDE_WRITE;
7770         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7771
7772         return ret;
7773 }
7774
7775 /* Enable l2 tunnel tag stripping */
7776 static int
7777 ixgbe_dev_l2_tunnel_stripping_enable
7778         (struct rte_eth_dev *dev,
7779          enum rte_eth_tunnel_type l2_tunnel_type)
7780 {
7781         int ret = 0;
7782
7783         switch (l2_tunnel_type) {
7784         case RTE_L2_TUNNEL_TYPE_E_TAG:
7785                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7786                 break;
7787         default:
7788                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7789                 ret = -EINVAL;
7790                 break;
7791         }
7792
7793         return ret;
7794 }
7795
7796 /* Disable l2 tunnel tag stripping */
7797 static int
7798 ixgbe_dev_l2_tunnel_stripping_disable
7799         (struct rte_eth_dev *dev,
7800          enum rte_eth_tunnel_type l2_tunnel_type)
7801 {
7802         int ret = 0;
7803
7804         switch (l2_tunnel_type) {
7805         case RTE_L2_TUNNEL_TYPE_E_TAG:
7806                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7807                 break;
7808         default:
7809                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7810                 ret = -EINVAL;
7811                 break;
7812         }
7813
7814         return ret;
7815 }
7816
7817 /* Enable/disable l2 tunnel offload functions */
7818 static int
7819 ixgbe_dev_l2_tunnel_offload_set
7820         (struct rte_eth_dev *dev,
7821          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7822          uint32_t mask,
7823          uint8_t en)
7824 {
7825         int ret = 0;
7826
7827         if (l2_tunnel == NULL)
7828                 return -EINVAL;
7829
7830         ret = -EINVAL;
7831         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7832                 if (en)
7833                         ret = ixgbe_dev_l2_tunnel_enable(
7834                                 dev,
7835                                 l2_tunnel->l2_tunnel_type);
7836                 else
7837                         ret = ixgbe_dev_l2_tunnel_disable(
7838                                 dev,
7839                                 l2_tunnel->l2_tunnel_type);
7840         }
7841
7842         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7843                 if (en)
7844                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7845                                 dev,
7846                                 l2_tunnel);
7847                 else
7848                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7849                                 dev,
7850                                 l2_tunnel);
7851         }
7852
7853         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7854                 if (en)
7855                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7856                                 dev,
7857                                 l2_tunnel->l2_tunnel_type);
7858                 else
7859                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7860                                 dev,
7861                                 l2_tunnel->l2_tunnel_type);
7862         }
7863
7864         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7865                 if (en)
7866                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7867                                 dev,
7868                                 l2_tunnel->l2_tunnel_type);
7869                 else
7870                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7871                                 dev,
7872                                 l2_tunnel->l2_tunnel_type);
7873         }
7874
7875         return ret;
7876 }
7877
7878 static int
7879 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7880                         uint16_t port)
7881 {
7882         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7883         IXGBE_WRITE_FLUSH(hw);
7884
7885         return 0;
7886 }
7887
7888 /* There's only one register for VxLAN UDP port.
7889  * So, we cannot add several ports. Will update it.
7890  */
7891 static int
7892 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7893                      uint16_t port)
7894 {
7895         if (port == 0) {
7896                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7897                 return -EINVAL;
7898         }
7899
7900         return ixgbe_update_vxlan_port(hw, port);
7901 }
7902
7903 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7904  * UDP port, it must have a value.
7905  * So, will reset it to the original value 0.
7906  */
7907 static int
7908 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7909                      uint16_t port)
7910 {
7911         uint16_t cur_port;
7912
7913         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7914
7915         if (cur_port != port) {
7916                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7917                 return -EINVAL;
7918         }
7919
7920         return ixgbe_update_vxlan_port(hw, 0);
7921 }
7922
7923 /* Add UDP tunneling port */
7924 static int
7925 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7926                               struct rte_eth_udp_tunnel *udp_tunnel)
7927 {
7928         int ret = 0;
7929         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7930
7931         if (hw->mac.type != ixgbe_mac_X550 &&
7932             hw->mac.type != ixgbe_mac_X550EM_x &&
7933             hw->mac.type != ixgbe_mac_X550EM_a) {
7934                 return -ENOTSUP;
7935         }
7936
7937         if (udp_tunnel == NULL)
7938                 return -EINVAL;
7939
7940         switch (udp_tunnel->prot_type) {
7941         case RTE_TUNNEL_TYPE_VXLAN:
7942                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7943                 break;
7944
7945         case RTE_TUNNEL_TYPE_GENEVE:
7946         case RTE_TUNNEL_TYPE_TEREDO:
7947                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7948                 ret = -EINVAL;
7949                 break;
7950
7951         default:
7952                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7953                 ret = -EINVAL;
7954                 break;
7955         }
7956
7957         return ret;
7958 }
7959
7960 /* Remove UDP tunneling port */
7961 static int
7962 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7963                               struct rte_eth_udp_tunnel *udp_tunnel)
7964 {
7965         int ret = 0;
7966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7967
7968         if (hw->mac.type != ixgbe_mac_X550 &&
7969             hw->mac.type != ixgbe_mac_X550EM_x &&
7970             hw->mac.type != ixgbe_mac_X550EM_a) {
7971                 return -ENOTSUP;
7972         }
7973
7974         if (udp_tunnel == NULL)
7975                 return -EINVAL;
7976
7977         switch (udp_tunnel->prot_type) {
7978         case RTE_TUNNEL_TYPE_VXLAN:
7979                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7980                 break;
7981         case RTE_TUNNEL_TYPE_GENEVE:
7982         case RTE_TUNNEL_TYPE_TEREDO:
7983                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7984                 ret = -EINVAL;
7985                 break;
7986         default:
7987                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7988                 ret = -EINVAL;
7989                 break;
7990         }
7991
7992         return ret;
7993 }
7994
7995 static void
7996 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7997 {
7998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7999
8000         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8001 }
8002
8003 static void
8004 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8005 {
8006         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8007
8008         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8009 }
8010
8011 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8012 {
8013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8014         u32 in_msg = 0;
8015
8016         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8017                 return;
8018
8019         /* PF reset VF event */
8020         if (in_msg == IXGBE_PF_CONTROL_MSG)
8021                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8022                                               NULL, NULL);
8023 }
8024
8025 static int
8026 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8027 {
8028         uint32_t eicr;
8029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8030         struct ixgbe_interrupt *intr =
8031                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8032         ixgbevf_intr_disable(hw);
8033
8034         /* read-on-clear nic registers here */
8035         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8036         intr->flags = 0;
8037
8038         /* only one misc vector supported - mailbox */
8039         eicr &= IXGBE_VTEICR_MASK;
8040         if (eicr == IXGBE_MISC_VEC_ID)
8041                 intr->flags |= IXGBE_FLAG_MAILBOX;
8042
8043         return 0;
8044 }
8045
8046 static int
8047 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8048 {
8049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8050         struct ixgbe_interrupt *intr =
8051                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8052
8053         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8054                 ixgbevf_mbx_process(dev);
8055                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8056         }
8057
8058         ixgbevf_intr_enable(hw);
8059
8060         return 0;
8061 }
8062
8063 static void
8064 ixgbevf_dev_interrupt_handler(void *param)
8065 {
8066         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8067
8068         ixgbevf_dev_interrupt_get_status(dev);
8069         ixgbevf_dev_interrupt_action(dev);
8070 }
8071
8072 /**
8073  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8074  *  @hw: pointer to hardware structure
8075  *
8076  *  Stops the transmit data path and waits for the HW to internally empty
8077  *  the Tx security block
8078  **/
8079 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8080 {
8081 #define IXGBE_MAX_SECTX_POLL 40
8082
8083         int i;
8084         int sectxreg;
8085
8086         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8087         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8088         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8089         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8090                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8091                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8092                         break;
8093                 /* Use interrupt-safe sleep just in case */
8094                 usec_delay(1000);
8095         }
8096
8097         /* For informational purposes only */
8098         if (i >= IXGBE_MAX_SECTX_POLL)
8099                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8100                          "path fully disabled.  Continuing with init.");
8101
8102         return IXGBE_SUCCESS;
8103 }
8104
8105 /**
8106  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8107  *  @hw: pointer to hardware structure
8108  *
8109  *  Enables the transmit data path.
8110  **/
8111 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8112 {
8113         uint32_t sectxreg;
8114
8115         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8116         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8117         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8118         IXGBE_WRITE_FLUSH(hw);
8119
8120         return IXGBE_SUCCESS;
8121 }
8122
8123 /* restore n-tuple filter */
8124 static inline void
8125 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8126 {
8127         struct ixgbe_filter_info *filter_info =
8128                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8129         struct ixgbe_5tuple_filter *node;
8130
8131         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8132                 ixgbe_inject_5tuple_filter(dev, node);
8133         }
8134 }
8135
8136 /* restore ethernet type filter */
8137 static inline void
8138 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8139 {
8140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8141         struct ixgbe_filter_info *filter_info =
8142                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8143         int i;
8144
8145         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8146                 if (filter_info->ethertype_mask & (1 << i)) {
8147                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8148                                         filter_info->ethertype_filters[i].etqf);
8149                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8150                                         filter_info->ethertype_filters[i].etqs);
8151                         IXGBE_WRITE_FLUSH(hw);
8152                 }
8153         }
8154 }
8155
8156 /* restore SYN filter */
8157 static inline void
8158 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8159 {
8160         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8161         struct ixgbe_filter_info *filter_info =
8162                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8163         uint32_t synqf;
8164
8165         synqf = filter_info->syn_info;
8166
8167         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8168                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8169                 IXGBE_WRITE_FLUSH(hw);
8170         }
8171 }
8172
8173 /* restore L2 tunnel filter */
8174 static inline void
8175 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8176 {
8177         struct ixgbe_l2_tn_info *l2_tn_info =
8178                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8179         struct ixgbe_l2_tn_filter *node;
8180         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8181
8182         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8183                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8184                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8185                 l2_tn_conf.pool           = node->pool;
8186                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8187         }
8188 }
8189
8190 static int
8191 ixgbe_filter_restore(struct rte_eth_dev *dev)
8192 {
8193         ixgbe_ntuple_filter_restore(dev);
8194         ixgbe_ethertype_filter_restore(dev);
8195         ixgbe_syn_filter_restore(dev);
8196         ixgbe_fdir_filter_restore(dev);
8197         ixgbe_l2_tn_filter_restore(dev);
8198
8199         return 0;
8200 }
8201
8202 static void
8203 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8204 {
8205         struct ixgbe_l2_tn_info *l2_tn_info =
8206                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8208
8209         if (l2_tn_info->e_tag_en)
8210                 (void)ixgbe_e_tag_enable(hw);
8211
8212         if (l2_tn_info->e_tag_fwd_en)
8213                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8214
8215         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8216 }
8217
8218 /* remove all the n-tuple filters */
8219 void
8220 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8221 {
8222         struct ixgbe_filter_info *filter_info =
8223                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8224         struct ixgbe_5tuple_filter *p_5tuple;
8225
8226         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8227                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8228 }
8229
8230 /* remove all the ether type filters */
8231 void
8232 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8233 {
8234         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8235         struct ixgbe_filter_info *filter_info =
8236                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8237         int i;
8238
8239         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8240                 if (filter_info->ethertype_mask & (1 << i) &&
8241                     !filter_info->ethertype_filters[i].conf) {
8242                         (void)ixgbe_ethertype_filter_remove(filter_info,
8243                                                             (uint8_t)i);
8244                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8245                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8246                         IXGBE_WRITE_FLUSH(hw);
8247                 }
8248         }
8249 }
8250
8251 /* remove the SYN filter */
8252 void
8253 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8254 {
8255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8256         struct ixgbe_filter_info *filter_info =
8257                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8258
8259         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8260                 filter_info->syn_info = 0;
8261
8262                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8263                 IXGBE_WRITE_FLUSH(hw);
8264         }
8265 }
8266
8267 /* remove all the L2 tunnel filters */
8268 int
8269 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8270 {
8271         struct ixgbe_l2_tn_info *l2_tn_info =
8272                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8273         struct ixgbe_l2_tn_filter *l2_tn_filter;
8274         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8275         int ret = 0;
8276
8277         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8278                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8279                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8280                 l2_tn_conf.pool           = l2_tn_filter->pool;
8281                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8282                 if (ret < 0)
8283                         return ret;
8284         }
8285
8286         return 0;
8287 }
8288
8289 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8290 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8291 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8292 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8293 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8294 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");