4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
65 #include "ixgbe_logs.h"
66 #include "base/ixgbe_api.h"
67 #include "base/ixgbe_vf.h"
68 #include "base/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
72 #include "base/ixgbe_type.h"
73 #include "base/ixgbe_phy.h"
74 #include "ixgbe_regs.h"
77 * High threshold controlling when to start sending XOFF frames. Must be at
78 * least 8 bytes less than receive packet buffer size. This value is in units
81 #define IXGBE_FC_HI 0x80
84 * Low threshold controlling when to start sending XON frames. This value is
85 * in units of 1024 bytes.
87 #define IXGBE_FC_LO 0x40
89 /* Default minimum inter-interrupt interval for EITR configuration */
90 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
92 /* Timer value included in XOFF frames. */
93 #define IXGBE_FC_PAUSE 0x680
95 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
96 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
97 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
99 #define IXGBE_MMW_SIZE_DEFAULT 0x4
100 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
101 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
104 * Default values for RX/TX configuration
106 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
107 #define IXGBE_DEFAULT_RX_PTHRESH 8
108 #define IXGBE_DEFAULT_RX_HTHRESH 8
109 #define IXGBE_DEFAULT_RX_WTHRESH 0
111 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
112 #define IXGBE_DEFAULT_TX_PTHRESH 32
113 #define IXGBE_DEFAULT_TX_HTHRESH 0
114 #define IXGBE_DEFAULT_TX_WTHRESH 0
115 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
117 /* Bit shift and mask */
118 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
119 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
120 #define IXGBE_8_BIT_WIDTH CHAR_BIT
121 #define IXGBE_8_BIT_MASK UINT8_MAX
123 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
125 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
127 #define IXGBE_HKEY_MAX_INDEX 10
129 /* Additional timesync values. */
130 #define NSEC_PER_SEC 1000000000L
131 #define IXGBE_INCVAL_10GB 0x66666666
132 #define IXGBE_INCVAL_1GB 0x40000000
133 #define IXGBE_INCVAL_100 0x50000000
134 #define IXGBE_INCVAL_SHIFT_10GB 28
135 #define IXGBE_INCVAL_SHIFT_1GB 24
136 #define IXGBE_INCVAL_SHIFT_100 21
137 #define IXGBE_INCVAL_SHIFT_82599 7
138 #define IXGBE_INCPER_SHIFT_82599 24
140 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
142 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
143 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
144 #define DEFAULT_ETAG_ETYPE 0x893f
145 #define IXGBE_ETAG_ETYPE 0x00005084
146 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
147 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
148 #define IXGBE_RAH_ADTYPE 0x40000000
149 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
150 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
151 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
152 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
153 #define IXGBE_QDE_STRIP_TAG 0x00000004
154 #define IXGBE_VTEICR_MASK 0x07
156 #define IXGBE_EXVET_VET_EXT_SHIFT 16
157 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
159 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
160 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
161 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
162 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
163 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
164 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
165 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
167 static int ixgbe_dev_start(struct rte_eth_dev *dev);
168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
169 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
172 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
178 int wait_to_complete);
179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
180 struct rte_eth_stats *stats);
181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
182 struct rte_eth_xstat *xstats, unsigned n);
183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
184 struct rte_eth_xstat *xstats, unsigned n);
186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
187 uint64_t *values, unsigned int n);
188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
190 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
191 struct rte_eth_xstat_name *xstats_names,
193 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
194 struct rte_eth_xstat_name *xstats_names, unsigned limit);
195 static int ixgbe_dev_xstats_get_names_by_id(
196 struct rte_eth_dev *dev,
197 struct rte_eth_xstat_name *xstats_names,
200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
207 struct rte_eth_dev_info *dev_info);
208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
210 struct rte_eth_dev_info *dev_info);
211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
214 uint16_t vlan_id, int on);
215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
216 enum rte_vlan_type vlan_type,
218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
219 uint16_t queue, bool on);
220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
231 struct rte_eth_fc_conf *fc_conf);
232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
233 struct rte_eth_fc_conf *fc_conf);
234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
235 struct rte_eth_pfc_conf *pfc_conf);
236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
237 struct rte_eth_rss_reta_entry64 *reta_conf,
239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
240 struct rte_eth_rss_reta_entry64 *reta_conf,
242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
248 struct rte_intr_handle *handle);
249 static void ixgbe_dev_interrupt_handler(void *param);
250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
252 uint32_t index, uint32_t pool);
253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
255 struct ether_addr *mac_addr);
256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
257 static bool is_device_supported(struct rte_eth_dev *dev,
258 struct rte_pci_driver *drv);
260 /* For Virtual Function support */
261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
263 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
264 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
265 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
266 int wait_to_complete);
267 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
268 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
269 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
270 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
271 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
272 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
273 struct rte_eth_stats *stats);
274 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
275 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
276 uint16_t vlan_id, int on);
277 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
278 uint16_t queue, int on);
279 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
280 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
281 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
283 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
285 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
286 uint8_t queue, uint8_t msix_vector);
287 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
288 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
289 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
291 /* For Eth VMDQ APIs support */
292 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
293 ether_addr * mac_addr, uint8_t on);
294 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
295 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
296 struct rte_eth_mirror_conf *mirror_conf,
297 uint8_t rule_id, uint8_t on);
298 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
300 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
302 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
304 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
305 uint8_t queue, uint8_t msix_vector);
306 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
308 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
309 struct ether_addr *mac_addr,
310 uint32_t index, uint32_t pool);
311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
313 struct ether_addr *mac_addr);
314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
315 struct rte_eth_syn_filter *filter);
316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
317 enum rte_filter_op filter_op,
319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
320 struct ixgbe_5tuple_filter *filter);
321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
322 struct ixgbe_5tuple_filter *filter);
323 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
324 enum rte_filter_op filter_op,
326 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
327 struct rte_eth_ntuple_filter *filter);
328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
329 enum rte_filter_op filter_op,
331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
332 struct rte_eth_ethertype_filter *filter);
333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
334 enum rte_filter_type filter_type,
335 enum rte_filter_op filter_op,
337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
340 struct ether_addr *mc_addr_set,
341 uint32_t nb_mc_addr);
342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
343 struct rte_eth_dcb_info *dcb_info);
345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
347 struct rte_dev_reg_info *regs);
348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
350 struct rte_dev_eeprom_info *eeprom);
351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
352 struct rte_dev_eeprom_info *eeprom);
354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
356 struct rte_dev_reg_info *regs);
358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
361 struct timespec *timestamp,
363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
364 struct timespec *timestamp);
365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
367 struct timespec *timestamp);
368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
369 const struct timespec *timestamp);
370 static void ixgbevf_dev_interrupt_handler(void *param);
372 static int ixgbe_dev_l2_tunnel_eth_type_conf
373 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
374 static int ixgbe_dev_l2_tunnel_offload_set
375 (struct rte_eth_dev *dev,
376 struct rte_eth_l2_tunnel_conf *l2_tunnel,
379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
380 enum rte_filter_op filter_op,
383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
384 struct rte_eth_udp_tunnel *udp_tunnel);
385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
386 struct rte_eth_udp_tunnel *udp_tunnel);
387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
391 * Define VF Stats MACRO for Non "cleared on read" register
393 #define UPDATE_VF_STAT(reg, last, cur) \
395 uint32_t latest = IXGBE_READ_REG(hw, reg); \
396 cur += (latest - last) & UINT_MAX; \
400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
402 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
403 u64 new_msb = IXGBE_READ_REG(hw, msb); \
404 u64 latest = ((new_msb << 32) | new_lsb); \
405 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
409 #define IXGBE_SET_HWSTRIP(h, q) do {\
410 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
411 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
412 (h)->bitmap[idx] |= 1 << bit;\
415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
416 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
417 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
418 (h)->bitmap[idx] &= ~(1 << bit);\
421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
422 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
423 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
424 (r) = (h)->bitmap[idx] >> bit & 1;\
428 * The set of PCI devices this driver supports
430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
479 #ifdef RTE_LIBRTE_IXGBE_BYPASS
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
482 { .vendor_id = 0, /* sentinel */ },
486 * The set of PCI devices this driver supports (for 82599 VF)
488 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
499 { .vendor_id = 0, /* sentinel */ },
502 static const struct rte_eth_desc_lim rx_desc_lim = {
503 .nb_max = IXGBE_MAX_RING_DESC,
504 .nb_min = IXGBE_MIN_RING_DESC,
505 .nb_align = IXGBE_RXD_ALIGN,
508 static const struct rte_eth_desc_lim tx_desc_lim = {
509 .nb_max = IXGBE_MAX_RING_DESC,
510 .nb_min = IXGBE_MIN_RING_DESC,
511 .nb_align = IXGBE_TXD_ALIGN,
512 .nb_seg_max = IXGBE_TX_MAX_SEG,
513 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
516 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
517 .dev_configure = ixgbe_dev_configure,
518 .dev_start = ixgbe_dev_start,
519 .dev_stop = ixgbe_dev_stop,
520 .dev_set_link_up = ixgbe_dev_set_link_up,
521 .dev_set_link_down = ixgbe_dev_set_link_down,
522 .dev_close = ixgbe_dev_close,
523 .dev_reset = ixgbe_dev_reset,
524 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
525 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
526 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
527 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
528 .link_update = ixgbe_dev_link_update,
529 .stats_get = ixgbe_dev_stats_get,
530 .xstats_get = ixgbe_dev_xstats_get,
531 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
532 .stats_reset = ixgbe_dev_stats_reset,
533 .xstats_reset = ixgbe_dev_xstats_reset,
534 .xstats_get_names = ixgbe_dev_xstats_get_names,
535 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
536 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
537 .fw_version_get = ixgbe_fw_version_get,
538 .dev_infos_get = ixgbe_dev_info_get,
539 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
540 .mtu_set = ixgbe_dev_mtu_set,
541 .vlan_filter_set = ixgbe_vlan_filter_set,
542 .vlan_tpid_set = ixgbe_vlan_tpid_set,
543 .vlan_offload_set = ixgbe_vlan_offload_set,
544 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
545 .rx_queue_start = ixgbe_dev_rx_queue_start,
546 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
547 .tx_queue_start = ixgbe_dev_tx_queue_start,
548 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
549 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
550 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
551 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
552 .rx_queue_release = ixgbe_dev_rx_queue_release,
553 .rx_queue_count = ixgbe_dev_rx_queue_count,
554 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
555 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
556 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
557 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
558 .tx_queue_release = ixgbe_dev_tx_queue_release,
559 .dev_led_on = ixgbe_dev_led_on,
560 .dev_led_off = ixgbe_dev_led_off,
561 .flow_ctrl_get = ixgbe_flow_ctrl_get,
562 .flow_ctrl_set = ixgbe_flow_ctrl_set,
563 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
564 .mac_addr_add = ixgbe_add_rar,
565 .mac_addr_remove = ixgbe_remove_rar,
566 .mac_addr_set = ixgbe_set_default_mac_addr,
567 .uc_hash_table_set = ixgbe_uc_hash_table_set,
568 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
569 .mirror_rule_set = ixgbe_mirror_rule_set,
570 .mirror_rule_reset = ixgbe_mirror_rule_reset,
571 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
572 .reta_update = ixgbe_dev_rss_reta_update,
573 .reta_query = ixgbe_dev_rss_reta_query,
574 .rss_hash_update = ixgbe_dev_rss_hash_update,
575 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
576 .filter_ctrl = ixgbe_dev_filter_ctrl,
577 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
578 .rxq_info_get = ixgbe_rxq_info_get,
579 .txq_info_get = ixgbe_txq_info_get,
580 .timesync_enable = ixgbe_timesync_enable,
581 .timesync_disable = ixgbe_timesync_disable,
582 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
583 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
584 .get_reg = ixgbe_get_regs,
585 .get_eeprom_length = ixgbe_get_eeprom_length,
586 .get_eeprom = ixgbe_get_eeprom,
587 .set_eeprom = ixgbe_set_eeprom,
588 .get_dcb_info = ixgbe_dev_get_dcb_info,
589 .timesync_adjust_time = ixgbe_timesync_adjust_time,
590 .timesync_read_time = ixgbe_timesync_read_time,
591 .timesync_write_time = ixgbe_timesync_write_time,
592 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
593 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
594 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
595 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
596 .tm_ops_get = ixgbe_tm_ops_get,
600 * dev_ops for virtual function, bare necessities for basic vf
601 * operation have been implemented
603 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
604 .dev_configure = ixgbevf_dev_configure,
605 .dev_start = ixgbevf_dev_start,
606 .dev_stop = ixgbevf_dev_stop,
607 .link_update = ixgbevf_dev_link_update,
608 .stats_get = ixgbevf_dev_stats_get,
609 .xstats_get = ixgbevf_dev_xstats_get,
610 .stats_reset = ixgbevf_dev_stats_reset,
611 .xstats_reset = ixgbevf_dev_stats_reset,
612 .xstats_get_names = ixgbevf_dev_xstats_get_names,
613 .dev_close = ixgbevf_dev_close,
614 .dev_reset = ixgbevf_dev_reset,
615 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
616 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
617 .dev_infos_get = ixgbevf_dev_info_get,
618 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
619 .mtu_set = ixgbevf_dev_set_mtu,
620 .vlan_filter_set = ixgbevf_vlan_filter_set,
621 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
622 .vlan_offload_set = ixgbevf_vlan_offload_set,
623 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
624 .rx_queue_release = ixgbe_dev_rx_queue_release,
625 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
626 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
627 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
628 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
629 .tx_queue_release = ixgbe_dev_tx_queue_release,
630 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
631 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
632 .mac_addr_add = ixgbevf_add_mac_addr,
633 .mac_addr_remove = ixgbevf_remove_mac_addr,
634 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
635 .rxq_info_get = ixgbe_rxq_info_get,
636 .txq_info_get = ixgbe_txq_info_get,
637 .mac_addr_set = ixgbevf_set_default_mac_addr,
638 .get_reg = ixgbevf_get_regs,
639 .reta_update = ixgbe_dev_rss_reta_update,
640 .reta_query = ixgbe_dev_rss_reta_query,
641 .rss_hash_update = ixgbe_dev_rss_hash_update,
642 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
645 /* store statistics names and its offset in stats structure */
646 struct rte_ixgbe_xstats_name_off {
647 char name[RTE_ETH_XSTATS_NAME_SIZE];
651 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
652 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
653 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
654 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
655 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
656 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
657 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
658 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
659 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
660 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
661 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
662 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
663 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
664 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
665 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
666 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
668 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
670 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
671 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
672 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
673 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
674 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
675 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
676 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
677 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
678 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
679 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
680 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
681 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
682 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
683 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
684 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
685 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
686 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
688 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
690 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
691 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
692 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
693 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
695 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
697 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
699 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
701 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
703 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
705 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
708 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
709 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
710 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
712 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
713 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
714 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
715 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
716 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
718 {"rx_fcoe_no_direct_data_placement_ext_buff",
719 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
721 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
723 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
725 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
727 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
729 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
732 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
733 sizeof(rte_ixgbe_stats_strings[0]))
735 /* MACsec statistics */
736 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
737 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
739 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
740 out_pkts_encrypted)},
741 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
742 out_pkts_protected)},
743 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
744 out_octets_encrypted)},
745 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
746 out_octets_protected)},
747 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
749 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
751 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
753 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
754 in_pkts_unknownsci)},
755 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
756 in_octets_decrypted)},
757 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
758 in_octets_validated)},
759 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
761 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
763 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
765 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
769 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
771 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
773 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
774 in_pkts_notusingsa)},
777 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
778 sizeof(rte_ixgbe_macsec_strings[0]))
780 /* Per-queue statistics */
781 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
782 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
783 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
784 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
785 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
788 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
789 sizeof(rte_ixgbe_rxq_strings[0]))
790 #define IXGBE_NB_RXQ_PRIO_VALUES 8
792 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
793 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
794 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
795 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
799 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
800 sizeof(rte_ixgbe_txq_strings[0]))
801 #define IXGBE_NB_TXQ_PRIO_VALUES 8
803 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
804 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
807 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
808 sizeof(rte_ixgbevf_stats_strings[0]))
811 * Atomically reads the link status information from global
812 * structure rte_eth_dev.
815 * - Pointer to the structure rte_eth_dev to read from.
816 * - Pointer to the buffer to be saved with the link status.
819 * - On success, zero.
820 * - On failure, negative value.
823 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
824 struct rte_eth_link *link)
826 struct rte_eth_link *dst = link;
827 struct rte_eth_link *src = &(dev->data->dev_link);
829 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
830 *(uint64_t *)src) == 0)
837 * Atomically writes the link status information into global
838 * structure rte_eth_dev.
841 * - Pointer to the structure rte_eth_dev to read from.
842 * - Pointer to the buffer to be saved with the link status.
845 * - On success, zero.
846 * - On failure, negative value.
849 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
850 struct rte_eth_link *link)
852 struct rte_eth_link *dst = &(dev->data->dev_link);
853 struct rte_eth_link *src = link;
855 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
856 *(uint64_t *)src) == 0)
863 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
866 ixgbe_is_sfp(struct ixgbe_hw *hw)
868 switch (hw->phy.type) {
869 case ixgbe_phy_sfp_avago:
870 case ixgbe_phy_sfp_ftl:
871 case ixgbe_phy_sfp_intel:
872 case ixgbe_phy_sfp_unknown:
873 case ixgbe_phy_sfp_passive_tyco:
874 case ixgbe_phy_sfp_passive_unknown:
881 static inline int32_t
882 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
887 status = ixgbe_reset_hw(hw);
889 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
890 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
891 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
892 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
893 IXGBE_WRITE_FLUSH(hw);
895 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
896 status = IXGBE_SUCCESS;
901 ixgbe_enable_intr(struct rte_eth_dev *dev)
903 struct ixgbe_interrupt *intr =
904 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
905 struct ixgbe_hw *hw =
906 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
908 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
909 IXGBE_WRITE_FLUSH(hw);
913 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
916 ixgbe_disable_intr(struct ixgbe_hw *hw)
918 PMD_INIT_FUNC_TRACE();
920 if (hw->mac.type == ixgbe_mac_82598EB) {
921 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
923 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
924 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
925 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
927 IXGBE_WRITE_FLUSH(hw);
931 * This function resets queue statistics mapping registers.
932 * From Niantic datasheet, Initialization of Statistics section:
933 * "...if software requires the queue counters, the RQSMR and TQSM registers
934 * must be re-programmed following a device reset.
937 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
941 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
942 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
943 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
949 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
954 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
955 #define NB_QMAP_FIELDS_PER_QSM_REG 4
956 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
958 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
959 struct ixgbe_stat_mapping_registers *stat_mappings =
960 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
961 uint32_t qsmr_mask = 0;
962 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
966 if ((hw->mac.type != ixgbe_mac_82599EB) &&
967 (hw->mac.type != ixgbe_mac_X540) &&
968 (hw->mac.type != ixgbe_mac_X550) &&
969 (hw->mac.type != ixgbe_mac_X550EM_x) &&
970 (hw->mac.type != ixgbe_mac_X550EM_a))
973 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
974 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
977 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
978 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
979 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
982 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
984 /* Now clear any previous stat_idx set */
985 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
987 stat_mappings->tqsm[n] &= ~clearing_mask;
989 stat_mappings->rqsmr[n] &= ~clearing_mask;
991 q_map = (uint32_t)stat_idx;
992 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
993 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
995 stat_mappings->tqsm[n] |= qsmr_mask;
997 stat_mappings->rqsmr[n] |= qsmr_mask;
999 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1000 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1001 queue_id, stat_idx);
1002 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1003 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1005 /* Now write the mapping in the appropriate register */
1007 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1008 stat_mappings->rqsmr[n], n);
1009 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1011 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1012 stat_mappings->tqsm[n], n);
1013 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1019 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1021 struct ixgbe_stat_mapping_registers *stat_mappings =
1022 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1023 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026 /* write whatever was in stat mapping table to the NIC */
1027 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1029 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1032 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1037 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1040 struct ixgbe_dcb_tc_config *tc;
1041 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1043 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1044 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1045 for (i = 0; i < dcb_max_tc; i++) {
1046 tc = &dcb_config->tc_config[i];
1047 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1048 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1049 (uint8_t)(100/dcb_max_tc + (i & 1));
1050 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1051 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1052 (uint8_t)(100/dcb_max_tc + (i & 1));
1053 tc->pfc = ixgbe_dcb_pfc_disabled;
1056 /* Initialize default user to priority mapping, UPx->TC0 */
1057 tc = &dcb_config->tc_config[0];
1058 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1059 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1060 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1061 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1062 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1064 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1065 dcb_config->pfc_mode_enable = false;
1066 dcb_config->vt_mode = true;
1067 dcb_config->round_robin_enable = false;
1068 /* support all DCB capabilities in 82599 */
1069 dcb_config->support.capabilities = 0xFF;
1071 /*we only support 4 Tcs for X540, X550 */
1072 if (hw->mac.type == ixgbe_mac_X540 ||
1073 hw->mac.type == ixgbe_mac_X550 ||
1074 hw->mac.type == ixgbe_mac_X550EM_x ||
1075 hw->mac.type == ixgbe_mac_X550EM_a) {
1076 dcb_config->num_tcs.pg_tcs = 4;
1077 dcb_config->num_tcs.pfc_tcs = 4;
1082 * Ensure that all locks are released before first NVM or PHY access
1085 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1090 * Phy lock should not fail in this early stage. If this is the case,
1091 * it is due to an improper exit of the application.
1092 * So force the release of the faulty lock. Release of common lock
1093 * is done automatically by swfw_sync function.
1095 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1096 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1097 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1099 ixgbe_release_swfw_semaphore(hw, mask);
1102 * These ones are more tricky since they are common to all ports; but
1103 * swfw_sync retries last long enough (1s) to be almost sure that if
1104 * lock can not be taken it is due to an improper lock of the
1107 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1108 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1109 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1111 ixgbe_release_swfw_semaphore(hw, mask);
1115 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1116 * It returns 0 on success.
1119 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1121 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1122 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1123 struct ixgbe_hw *hw =
1124 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1125 struct ixgbe_vfta *shadow_vfta =
1126 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1127 struct ixgbe_hwstrip *hwstrip =
1128 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1129 struct ixgbe_dcb_config *dcb_config =
1130 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1131 struct ixgbe_filter_info *filter_info =
1132 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1133 struct ixgbe_bw_conf *bw_conf =
1134 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1139 PMD_INIT_FUNC_TRACE();
1141 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1142 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1143 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1144 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1147 * For secondary processes, we don't initialise any further as primary
1148 * has already done this work. Only check we don't need a different
1149 * RX and TX function.
1151 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1152 struct ixgbe_tx_queue *txq;
1153 /* TX queue function in primary, set by last queue initialized
1154 * Tx queue may not initialized by primary process
1156 if (eth_dev->data->tx_queues) {
1157 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1158 ixgbe_set_tx_function(eth_dev, txq);
1160 /* Use default TX function if we get here */
1161 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1162 "Using default TX function.");
1165 ixgbe_set_rx_function(eth_dev);
1170 rte_eth_copy_pci_info(eth_dev, pci_dev);
1171 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1173 /* Vendor and Device ID need to be set before init of shared code */
1174 hw->device_id = pci_dev->id.device_id;
1175 hw->vendor_id = pci_dev->id.vendor_id;
1176 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1177 hw->allow_unsupported_sfp = 1;
1179 /* Initialize the shared code (base driver) */
1180 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1181 diag = ixgbe_bypass_init_shared_code(hw);
1183 diag = ixgbe_init_shared_code(hw);
1184 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1186 if (diag != IXGBE_SUCCESS) {
1187 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1191 /* pick up the PCI bus settings for reporting later */
1192 ixgbe_get_bus_info(hw);
1194 /* Unlock any pending hardware semaphore */
1195 ixgbe_swfw_lock_reset(hw);
1197 /* Initialize DCB configuration*/
1198 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1199 ixgbe_dcb_init(hw, dcb_config);
1200 /* Get Hardware Flow Control setting */
1201 hw->fc.requested_mode = ixgbe_fc_full;
1202 hw->fc.current_mode = ixgbe_fc_full;
1203 hw->fc.pause_time = IXGBE_FC_PAUSE;
1204 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1205 hw->fc.low_water[i] = IXGBE_FC_LO;
1206 hw->fc.high_water[i] = IXGBE_FC_HI;
1208 hw->fc.send_xon = 1;
1210 /* Make sure we have a good EEPROM before we read from it */
1211 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1212 if (diag != IXGBE_SUCCESS) {
1213 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1217 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1218 diag = ixgbe_bypass_init_hw(hw);
1220 diag = ixgbe_init_hw(hw);
1221 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1224 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1225 * is called too soon after the kernel driver unbinding/binding occurs.
1226 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1227 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1228 * also called. See ixgbe_identify_phy_82599(). The reason for the
1229 * failure is not known, and only occuts when virtualisation features
1230 * are disabled in the bios. A delay of 100ms was found to be enough by
1231 * trial-and-error, and is doubled to be safe.
1233 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1235 diag = ixgbe_init_hw(hw);
1238 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1239 diag = IXGBE_SUCCESS;
1241 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1242 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1243 "LOM. Please be aware there may be issues associated "
1244 "with your hardware.");
1245 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1246 "please contact your Intel or hardware representative "
1247 "who provided you with this hardware.");
1248 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1249 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1251 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1255 /* Reset the hw statistics */
1256 ixgbe_dev_stats_reset(eth_dev);
1258 /* disable interrupt */
1259 ixgbe_disable_intr(hw);
1261 /* reset mappings for queue statistics hw counters*/
1262 ixgbe_reset_qstat_mappings(hw);
1264 /* Allocate memory for storing MAC addresses */
1265 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1266 hw->mac.num_rar_entries, 0);
1267 if (eth_dev->data->mac_addrs == NULL) {
1269 "Failed to allocate %u bytes needed to store "
1271 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1274 /* Copy the permanent MAC address */
1275 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1276 ð_dev->data->mac_addrs[0]);
1278 /* Allocate memory for storing hash filter MAC addresses */
1279 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1280 IXGBE_VMDQ_NUM_UC_MAC, 0);
1281 if (eth_dev->data->hash_mac_addrs == NULL) {
1283 "Failed to allocate %d bytes needed to store MAC addresses",
1284 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1288 /* initialize the vfta */
1289 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1291 /* initialize the hw strip bitmap*/
1292 memset(hwstrip, 0, sizeof(*hwstrip));
1294 /* initialize PF if max_vfs not zero */
1295 ixgbe_pf_host_init(eth_dev);
1297 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1298 /* let hardware know driver is loaded */
1299 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1300 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1301 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1302 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1303 IXGBE_WRITE_FLUSH(hw);
1305 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1306 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1307 (int) hw->mac.type, (int) hw->phy.type,
1308 (int) hw->phy.sfp_type);
1310 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1311 (int) hw->mac.type, (int) hw->phy.type);
1313 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1314 eth_dev->data->port_id, pci_dev->id.vendor_id,
1315 pci_dev->id.device_id);
1317 rte_intr_callback_register(intr_handle,
1318 ixgbe_dev_interrupt_handler, eth_dev);
1320 /* enable uio/vfio intr/eventfd mapping */
1321 rte_intr_enable(intr_handle);
1323 /* enable support intr */
1324 ixgbe_enable_intr(eth_dev);
1326 /* initialize filter info */
1327 memset(filter_info, 0,
1328 sizeof(struct ixgbe_filter_info));
1330 /* initialize 5tuple filter list */
1331 TAILQ_INIT(&filter_info->fivetuple_list);
1333 /* initialize flow director filter list & hash */
1334 ixgbe_fdir_filter_init(eth_dev);
1336 /* initialize l2 tunnel filter list & hash */
1337 ixgbe_l2_tn_filter_init(eth_dev);
1339 TAILQ_INIT(&filter_ntuple_list);
1340 TAILQ_INIT(&filter_ethertype_list);
1341 TAILQ_INIT(&filter_syn_list);
1342 TAILQ_INIT(&filter_fdir_list);
1343 TAILQ_INIT(&filter_l2_tunnel_list);
1344 TAILQ_INIT(&ixgbe_flow_list);
1346 /* initialize bandwidth configuration info */
1347 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1349 /* initialize Traffic Manager configuration */
1350 ixgbe_tm_conf_init(eth_dev);
1356 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1358 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1359 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1360 struct ixgbe_hw *hw;
1362 PMD_INIT_FUNC_TRACE();
1364 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1367 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1369 if (hw->adapter_stopped == 0)
1370 ixgbe_dev_close(eth_dev);
1372 eth_dev->dev_ops = NULL;
1373 eth_dev->rx_pkt_burst = NULL;
1374 eth_dev->tx_pkt_burst = NULL;
1376 /* Unlock any pending hardware semaphore */
1377 ixgbe_swfw_lock_reset(hw);
1379 /* disable uio intr before callback unregister */
1380 rte_intr_disable(intr_handle);
1381 rte_intr_callback_unregister(intr_handle,
1382 ixgbe_dev_interrupt_handler, eth_dev);
1384 /* uninitialize PF if max_vfs not zero */
1385 ixgbe_pf_host_uninit(eth_dev);
1387 rte_free(eth_dev->data->mac_addrs);
1388 eth_dev->data->mac_addrs = NULL;
1390 rte_free(eth_dev->data->hash_mac_addrs);
1391 eth_dev->data->hash_mac_addrs = NULL;
1393 /* remove all the fdir filters & hash */
1394 ixgbe_fdir_filter_uninit(eth_dev);
1396 /* remove all the L2 tunnel filters & hash */
1397 ixgbe_l2_tn_filter_uninit(eth_dev);
1399 /* Remove all ntuple filters of the device */
1400 ixgbe_ntuple_filter_uninit(eth_dev);
1402 /* clear all the filters list */
1403 ixgbe_filterlist_flush();
1405 /* Remove all Traffic Manager configuration */
1406 ixgbe_tm_conf_uninit(eth_dev);
1411 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1413 struct ixgbe_filter_info *filter_info =
1414 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1415 struct ixgbe_5tuple_filter *p_5tuple;
1417 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1418 TAILQ_REMOVE(&filter_info->fivetuple_list,
1423 memset(filter_info->fivetuple_mask, 0,
1424 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1429 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1431 struct ixgbe_hw_fdir_info *fdir_info =
1432 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1433 struct ixgbe_fdir_filter *fdir_filter;
1435 if (fdir_info->hash_map)
1436 rte_free(fdir_info->hash_map);
1437 if (fdir_info->hash_handle)
1438 rte_hash_free(fdir_info->hash_handle);
1440 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1441 TAILQ_REMOVE(&fdir_info->fdir_list,
1444 rte_free(fdir_filter);
1450 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1452 struct ixgbe_l2_tn_info *l2_tn_info =
1453 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1454 struct ixgbe_l2_tn_filter *l2_tn_filter;
1456 if (l2_tn_info->hash_map)
1457 rte_free(l2_tn_info->hash_map);
1458 if (l2_tn_info->hash_handle)
1459 rte_hash_free(l2_tn_info->hash_handle);
1461 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1462 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1465 rte_free(l2_tn_filter);
1471 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1473 struct ixgbe_hw_fdir_info *fdir_info =
1474 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1475 char fdir_hash_name[RTE_HASH_NAMESIZE];
1476 struct rte_hash_parameters fdir_hash_params = {
1477 .name = fdir_hash_name,
1478 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1479 .key_len = sizeof(union ixgbe_atr_input),
1480 .hash_func = rte_hash_crc,
1481 .hash_func_init_val = 0,
1482 .socket_id = rte_socket_id(),
1485 TAILQ_INIT(&fdir_info->fdir_list);
1486 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1487 "fdir_%s", eth_dev->device->name);
1488 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1489 if (!fdir_info->hash_handle) {
1490 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1493 fdir_info->hash_map = rte_zmalloc("ixgbe",
1494 sizeof(struct ixgbe_fdir_filter *) *
1495 IXGBE_MAX_FDIR_FILTER_NUM,
1497 if (!fdir_info->hash_map) {
1499 "Failed to allocate memory for fdir hash map!");
1502 fdir_info->mask_added = FALSE;
1507 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1509 struct ixgbe_l2_tn_info *l2_tn_info =
1510 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1511 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1512 struct rte_hash_parameters l2_tn_hash_params = {
1513 .name = l2_tn_hash_name,
1514 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1515 .key_len = sizeof(struct ixgbe_l2_tn_key),
1516 .hash_func = rte_hash_crc,
1517 .hash_func_init_val = 0,
1518 .socket_id = rte_socket_id(),
1521 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1522 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1523 "l2_tn_%s", eth_dev->device->name);
1524 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1525 if (!l2_tn_info->hash_handle) {
1526 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1529 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1530 sizeof(struct ixgbe_l2_tn_filter *) *
1531 IXGBE_MAX_L2_TN_FILTER_NUM,
1533 if (!l2_tn_info->hash_map) {
1535 "Failed to allocate memory for L2 TN hash map!");
1538 l2_tn_info->e_tag_en = FALSE;
1539 l2_tn_info->e_tag_fwd_en = FALSE;
1540 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1545 * Negotiate mailbox API version with the PF.
1546 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1547 * Then we try to negotiate starting with the most recent one.
1548 * If all negotiation attempts fail, then we will proceed with
1549 * the default one (ixgbe_mbox_api_10).
1552 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1556 /* start with highest supported, proceed down */
1557 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1564 i != RTE_DIM(sup_ver) &&
1565 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1571 generate_random_mac_addr(struct ether_addr *mac_addr)
1575 /* Set Organizationally Unique Identifier (OUI) prefix. */
1576 mac_addr->addr_bytes[0] = 0x00;
1577 mac_addr->addr_bytes[1] = 0x09;
1578 mac_addr->addr_bytes[2] = 0xC0;
1579 /* Force indication of locally assigned MAC address. */
1580 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1581 /* Generate the last 3 bytes of the MAC address with a random number. */
1582 random = rte_rand();
1583 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1587 * Virtual Function device init
1590 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1594 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1595 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1596 struct ixgbe_hw *hw =
1597 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1598 struct ixgbe_vfta *shadow_vfta =
1599 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1600 struct ixgbe_hwstrip *hwstrip =
1601 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1602 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1604 PMD_INIT_FUNC_TRACE();
1606 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1607 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1608 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1610 /* for secondary processes, we don't initialise any further as primary
1611 * has already done this work. Only check we don't need a different
1614 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1615 struct ixgbe_tx_queue *txq;
1616 /* TX queue function in primary, set by last queue initialized
1617 * Tx queue may not initialized by primary process
1619 if (eth_dev->data->tx_queues) {
1620 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1621 ixgbe_set_tx_function(eth_dev, txq);
1623 /* Use default TX function if we get here */
1624 PMD_INIT_LOG(NOTICE,
1625 "No TX queues configured yet. Using default TX function.");
1628 ixgbe_set_rx_function(eth_dev);
1633 rte_eth_copy_pci_info(eth_dev, pci_dev);
1634 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1636 hw->device_id = pci_dev->id.device_id;
1637 hw->vendor_id = pci_dev->id.vendor_id;
1638 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1640 /* initialize the vfta */
1641 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1643 /* initialize the hw strip bitmap*/
1644 memset(hwstrip, 0, sizeof(*hwstrip));
1646 /* Initialize the shared code (base driver) */
1647 diag = ixgbe_init_shared_code(hw);
1648 if (diag != IXGBE_SUCCESS) {
1649 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1653 /* init_mailbox_params */
1654 hw->mbx.ops.init_params(hw);
1656 /* Reset the hw statistics */
1657 ixgbevf_dev_stats_reset(eth_dev);
1659 /* Disable the interrupts for VF */
1660 ixgbevf_intr_disable(hw);
1662 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1663 diag = hw->mac.ops.reset_hw(hw);
1666 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1667 * the underlying PF driver has not assigned a MAC address to the VF.
1668 * In this case, assign a random MAC address.
1670 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1671 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1675 /* negotiate mailbox API version to use with the PF. */
1676 ixgbevf_negotiate_api(hw);
1678 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1679 ixgbevf_get_queues(hw, &tcs, &tc);
1681 /* Allocate memory for storing MAC addresses */
1682 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1683 hw->mac.num_rar_entries, 0);
1684 if (eth_dev->data->mac_addrs == NULL) {
1686 "Failed to allocate %u bytes needed to store "
1688 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1692 /* Generate a random MAC address, if none was assigned by PF. */
1693 if (is_zero_ether_addr(perm_addr)) {
1694 generate_random_mac_addr(perm_addr);
1695 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1697 rte_free(eth_dev->data->mac_addrs);
1698 eth_dev->data->mac_addrs = NULL;
1701 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1702 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1703 "%02x:%02x:%02x:%02x:%02x:%02x",
1704 perm_addr->addr_bytes[0],
1705 perm_addr->addr_bytes[1],
1706 perm_addr->addr_bytes[2],
1707 perm_addr->addr_bytes[3],
1708 perm_addr->addr_bytes[4],
1709 perm_addr->addr_bytes[5]);
1712 /* Copy the permanent MAC address */
1713 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1715 /* reset the hardware with the new settings */
1716 diag = hw->mac.ops.start_hw(hw);
1722 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1726 rte_intr_callback_register(intr_handle,
1727 ixgbevf_dev_interrupt_handler, eth_dev);
1728 rte_intr_enable(intr_handle);
1729 ixgbevf_intr_enable(hw);
1731 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1732 eth_dev->data->port_id, pci_dev->id.vendor_id,
1733 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1738 /* Virtual Function device uninit */
1741 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1743 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1744 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1745 struct ixgbe_hw *hw;
1747 PMD_INIT_FUNC_TRACE();
1749 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1752 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1754 if (hw->adapter_stopped == 0)
1755 ixgbevf_dev_close(eth_dev);
1757 eth_dev->dev_ops = NULL;
1758 eth_dev->rx_pkt_burst = NULL;
1759 eth_dev->tx_pkt_burst = NULL;
1761 /* Disable the interrupts for VF */
1762 ixgbevf_intr_disable(hw);
1764 rte_free(eth_dev->data->mac_addrs);
1765 eth_dev->data->mac_addrs = NULL;
1767 rte_intr_disable(intr_handle);
1768 rte_intr_callback_unregister(intr_handle,
1769 ixgbevf_dev_interrupt_handler, eth_dev);
1774 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1775 struct rte_pci_device *pci_dev)
1777 return rte_eth_dev_pci_generic_probe(pci_dev,
1778 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1781 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1783 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1786 static struct rte_pci_driver rte_ixgbe_pmd = {
1787 .id_table = pci_id_ixgbe_map,
1788 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1789 .probe = eth_ixgbe_pci_probe,
1790 .remove = eth_ixgbe_pci_remove,
1793 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1794 struct rte_pci_device *pci_dev)
1796 return rte_eth_dev_pci_generic_probe(pci_dev,
1797 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1800 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1802 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1806 * virtual function driver struct
1808 static struct rte_pci_driver rte_ixgbevf_pmd = {
1809 .id_table = pci_id_ixgbevf_map,
1810 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1811 .probe = eth_ixgbevf_pci_probe,
1812 .remove = eth_ixgbevf_pci_remove,
1816 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1818 struct ixgbe_hw *hw =
1819 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820 struct ixgbe_vfta *shadow_vfta =
1821 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1826 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1827 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1828 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1833 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1835 /* update local VFTA copy */
1836 shadow_vfta->vfta[vid_idx] = vfta;
1842 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1845 ixgbe_vlan_hw_strip_enable(dev, queue);
1847 ixgbe_vlan_hw_strip_disable(dev, queue);
1851 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1852 enum rte_vlan_type vlan_type,
1855 struct ixgbe_hw *hw =
1856 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1861 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1862 qinq &= IXGBE_DMATXCTL_GDV;
1864 switch (vlan_type) {
1865 case ETH_VLAN_TYPE_INNER:
1867 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1868 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1869 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1870 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1871 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1872 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1873 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1876 PMD_DRV_LOG(ERR, "Inner type is not supported"
1880 case ETH_VLAN_TYPE_OUTER:
1882 /* Only the high 16-bits is valid */
1883 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1884 IXGBE_EXVET_VET_EXT_SHIFT);
1886 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1887 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1888 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1889 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1890 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1891 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1892 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1898 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1906 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1908 struct ixgbe_hw *hw =
1909 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912 PMD_INIT_FUNC_TRACE();
1914 /* Filter Table Disable */
1915 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1916 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1918 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1922 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1924 struct ixgbe_hw *hw =
1925 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926 struct ixgbe_vfta *shadow_vfta =
1927 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1931 PMD_INIT_FUNC_TRACE();
1933 /* Filter Table Enable */
1934 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1935 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1936 vlnctrl |= IXGBE_VLNCTRL_VFE;
1938 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1940 /* write whatever is in local vfta copy */
1941 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1942 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1946 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1948 struct ixgbe_hwstrip *hwstrip =
1949 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1950 struct ixgbe_rx_queue *rxq;
1952 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1956 IXGBE_SET_HWSTRIP(hwstrip, queue);
1958 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1960 if (queue >= dev->data->nb_rx_queues)
1963 rxq = dev->data->rx_queues[queue];
1966 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1968 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1972 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1974 struct ixgbe_hw *hw =
1975 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978 PMD_INIT_FUNC_TRACE();
1980 if (hw->mac.type == ixgbe_mac_82598EB) {
1981 /* No queue level support */
1982 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1986 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1987 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1988 ctrl &= ~IXGBE_RXDCTL_VME;
1989 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1991 /* record those setting for HW strip per queue */
1992 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1996 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1998 struct ixgbe_hw *hw =
1999 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2002 PMD_INIT_FUNC_TRACE();
2004 if (hw->mac.type == ixgbe_mac_82598EB) {
2005 /* No queue level supported */
2006 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2010 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2011 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2012 ctrl |= IXGBE_RXDCTL_VME;
2013 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2015 /* record those setting for HW strip per queue */
2016 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2020 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2022 struct ixgbe_hw *hw =
2023 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2026 struct ixgbe_rx_queue *rxq;
2028 PMD_INIT_FUNC_TRACE();
2030 if (hw->mac.type == ixgbe_mac_82598EB) {
2031 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2032 ctrl &= ~IXGBE_VLNCTRL_VME;
2033 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2035 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2036 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2037 rxq = dev->data->rx_queues[i];
2038 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2039 ctrl &= ~IXGBE_RXDCTL_VME;
2040 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2042 /* record those setting for HW strip per queue */
2043 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2049 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2051 struct ixgbe_hw *hw =
2052 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055 struct ixgbe_rx_queue *rxq;
2057 PMD_INIT_FUNC_TRACE();
2059 if (hw->mac.type == ixgbe_mac_82598EB) {
2060 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2061 ctrl |= IXGBE_VLNCTRL_VME;
2062 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2064 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2065 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2066 rxq = dev->data->rx_queues[i];
2067 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2068 ctrl |= IXGBE_RXDCTL_VME;
2069 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2071 /* record those setting for HW strip per queue */
2072 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2078 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2080 struct ixgbe_hw *hw =
2081 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084 PMD_INIT_FUNC_TRACE();
2086 /* DMATXCTRL: Geric Double VLAN Disable */
2087 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2088 ctrl &= ~IXGBE_DMATXCTL_GDV;
2089 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2091 /* CTRL_EXT: Global Double VLAN Disable */
2092 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2093 ctrl &= ~IXGBE_EXTENDED_VLAN;
2094 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2099 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2101 struct ixgbe_hw *hw =
2102 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105 PMD_INIT_FUNC_TRACE();
2107 /* DMATXCTRL: Geric Double VLAN Enable */
2108 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2109 ctrl |= IXGBE_DMATXCTL_GDV;
2110 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2112 /* CTRL_EXT: Global Double VLAN Enable */
2113 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2114 ctrl |= IXGBE_EXTENDED_VLAN;
2115 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2117 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2118 if (hw->mac.type == ixgbe_mac_X550 ||
2119 hw->mac.type == ixgbe_mac_X550EM_x ||
2120 hw->mac.type == ixgbe_mac_X550EM_a) {
2121 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2122 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2123 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2127 * VET EXT field in the EXVET register = 0x8100 by default
2128 * So no need to change. Same to VT field of DMATXCTL register
2133 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2135 if (mask & ETH_VLAN_STRIP_MASK) {
2136 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2137 ixgbe_vlan_hw_strip_enable_all(dev);
2139 ixgbe_vlan_hw_strip_disable_all(dev);
2142 if (mask & ETH_VLAN_FILTER_MASK) {
2143 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2144 ixgbe_vlan_hw_filter_enable(dev);
2146 ixgbe_vlan_hw_filter_disable(dev);
2149 if (mask & ETH_VLAN_EXTEND_MASK) {
2150 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2151 ixgbe_vlan_hw_extend_enable(dev);
2153 ixgbe_vlan_hw_extend_disable(dev);
2158 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2160 struct ixgbe_hw *hw =
2161 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2162 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2163 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2165 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2166 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2170 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2172 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2177 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2180 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2186 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2187 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2193 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2195 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2196 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2197 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2198 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2200 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2201 /* check multi-queue mode */
2202 switch (dev_conf->rxmode.mq_mode) {
2203 case ETH_MQ_RX_VMDQ_DCB:
2204 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2206 case ETH_MQ_RX_VMDQ_DCB_RSS:
2207 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2208 PMD_INIT_LOG(ERR, "SRIOV active,"
2209 " unsupported mq_mode rx %d.",
2210 dev_conf->rxmode.mq_mode);
2213 case ETH_MQ_RX_VMDQ_RSS:
2214 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2215 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2216 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2217 PMD_INIT_LOG(ERR, "SRIOV is active,"
2218 " invalid queue number"
2219 " for VMDQ RSS, allowed"
2220 " value are 1, 2 or 4.");
2224 case ETH_MQ_RX_VMDQ_ONLY:
2225 case ETH_MQ_RX_NONE:
2226 /* if nothing mq mode configure, use default scheme */
2227 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2228 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2229 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2231 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2232 /* SRIOV only works in VMDq enable mode */
2233 PMD_INIT_LOG(ERR, "SRIOV is active,"
2234 " wrong mq_mode rx %d.",
2235 dev_conf->rxmode.mq_mode);
2239 switch (dev_conf->txmode.mq_mode) {
2240 case ETH_MQ_TX_VMDQ_DCB:
2241 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2242 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2244 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2245 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2249 /* check valid queue number */
2250 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2251 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2252 PMD_INIT_LOG(ERR, "SRIOV is active,"
2253 " nb_rx_q=%d nb_tx_q=%d queue number"
2254 " must be less than or equal to %d.",
2256 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2260 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2261 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2265 /* check configuration for vmdb+dcb mode */
2266 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2267 const struct rte_eth_vmdq_dcb_conf *conf;
2269 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2270 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2271 IXGBE_VMDQ_DCB_NB_QUEUES);
2274 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2275 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2276 conf->nb_queue_pools == ETH_32_POOLS)) {
2277 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2278 " nb_queue_pools must be %d or %d.",
2279 ETH_16_POOLS, ETH_32_POOLS);
2283 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2284 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2286 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2287 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2288 IXGBE_VMDQ_DCB_NB_QUEUES);
2291 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2292 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2293 conf->nb_queue_pools == ETH_32_POOLS)) {
2294 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2295 " nb_queue_pools != %d and"
2296 " nb_queue_pools != %d.",
2297 ETH_16_POOLS, ETH_32_POOLS);
2302 /* For DCB mode check our configuration before we go further */
2303 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2304 const struct rte_eth_dcb_rx_conf *conf;
2306 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2307 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2308 IXGBE_DCB_NB_QUEUES);
2311 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2312 if (!(conf->nb_tcs == ETH_4_TCS ||
2313 conf->nb_tcs == ETH_8_TCS)) {
2314 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2315 " and nb_tcs != %d.",
2316 ETH_4_TCS, ETH_8_TCS);
2321 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2322 const struct rte_eth_dcb_tx_conf *conf;
2324 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2325 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2326 IXGBE_DCB_NB_QUEUES);
2329 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2330 if (!(conf->nb_tcs == ETH_4_TCS ||
2331 conf->nb_tcs == ETH_8_TCS)) {
2332 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2333 " and nb_tcs != %d.",
2334 ETH_4_TCS, ETH_8_TCS);
2340 * When DCB/VT is off, maximum number of queues changes,
2341 * except for 82598EB, which remains constant.
2343 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2344 hw->mac.type != ixgbe_mac_82598EB) {
2345 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2347 "Neither VT nor DCB are enabled, "
2349 IXGBE_NONE_MODE_TX_NB_QUEUES);
2358 ixgbe_dev_configure(struct rte_eth_dev *dev)
2360 struct ixgbe_interrupt *intr =
2361 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2362 struct ixgbe_adapter *adapter =
2363 (struct ixgbe_adapter *)dev->data->dev_private;
2366 PMD_INIT_FUNC_TRACE();
2367 /* multipe queue mode checking */
2368 ret = ixgbe_check_mq_mode(dev);
2370 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2375 /* set flag to update link status after init */
2376 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2379 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2380 * allocation or vector Rx preconditions we will reset it.
2382 adapter->rx_bulk_alloc_allowed = true;
2383 adapter->rx_vec_allowed = true;
2389 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2391 struct ixgbe_hw *hw =
2392 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2393 struct ixgbe_interrupt *intr =
2394 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2397 /* only set up it on X550EM_X */
2398 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2399 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2400 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2401 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2402 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2403 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2408 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2409 uint16_t tx_rate, uint64_t q_msk)
2411 struct ixgbe_hw *hw;
2412 struct ixgbe_vf_info *vfinfo;
2413 struct rte_eth_link link;
2414 uint8_t nb_q_per_pool;
2415 uint32_t queue_stride;
2416 uint32_t queue_idx, idx = 0, vf_idx;
2418 uint16_t total_rate = 0;
2419 struct rte_pci_device *pci_dev;
2421 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2422 rte_eth_link_get_nowait(dev->data->port_id, &link);
2424 if (vf >= pci_dev->max_vfs)
2427 if (tx_rate > link.link_speed)
2433 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2434 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2435 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2436 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2437 queue_idx = vf * queue_stride;
2438 queue_end = queue_idx + nb_q_per_pool - 1;
2439 if (queue_end >= hw->mac.max_tx_queues)
2443 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2446 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2448 total_rate += vfinfo[vf_idx].tx_rate[idx];
2454 /* Store tx_rate for this vf. */
2455 for (idx = 0; idx < nb_q_per_pool; idx++) {
2456 if (((uint64_t)0x1 << idx) & q_msk) {
2457 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2458 vfinfo[vf].tx_rate[idx] = tx_rate;
2459 total_rate += tx_rate;
2463 if (total_rate > dev->data->dev_link.link_speed) {
2464 /* Reset stored TX rate of the VF if it causes exceed
2467 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2471 /* Set RTTBCNRC of each queue/pool for vf X */
2472 for (; queue_idx <= queue_end; queue_idx++) {
2474 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2482 * Configure device link speed and setup link.
2483 * It returns 0 on success.
2486 ixgbe_dev_start(struct rte_eth_dev *dev)
2488 struct ixgbe_hw *hw =
2489 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490 struct ixgbe_vf_info *vfinfo =
2491 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2492 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2493 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2494 uint32_t intr_vector = 0;
2495 int err, link_up = 0, negotiate = 0;
2500 uint32_t *link_speeds;
2501 struct ixgbe_tm_conf *tm_conf =
2502 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2504 PMD_INIT_FUNC_TRACE();
2506 /* IXGBE devices don't support:
2507 * - half duplex (checked afterwards for valid speeds)
2508 * - fixed speed: TODO implement
2510 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2511 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2512 dev->data->port_id);
2516 /* disable uio/vfio intr/eventfd mapping */
2517 rte_intr_disable(intr_handle);
2520 hw->adapter_stopped = 0;
2521 ixgbe_stop_adapter(hw);
2523 /* reinitialize adapter
2524 * this calls reset and start
2526 status = ixgbe_pf_reset_hw(hw);
2529 hw->mac.ops.start_hw(hw);
2530 hw->mac.get_link_status = true;
2532 /* configure PF module if SRIOV enabled */
2533 ixgbe_pf_host_configure(dev);
2535 ixgbe_dev_phy_intr_setup(dev);
2537 /* check and configure queue intr-vector mapping */
2538 if ((rte_intr_cap_multiple(intr_handle) ||
2539 !RTE_ETH_DEV_SRIOV(dev).active) &&
2540 dev->data->dev_conf.intr_conf.rxq != 0) {
2541 intr_vector = dev->data->nb_rx_queues;
2542 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2543 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2544 IXGBE_MAX_INTR_QUEUE_NUM);
2547 if (rte_intr_efd_enable(intr_handle, intr_vector))
2551 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2552 intr_handle->intr_vec =
2553 rte_zmalloc("intr_vec",
2554 dev->data->nb_rx_queues * sizeof(int), 0);
2555 if (intr_handle->intr_vec == NULL) {
2556 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2557 " intr_vec", dev->data->nb_rx_queues);
2562 /* confiugre msix for sleep until rx interrupt */
2563 ixgbe_configure_msix(dev);
2565 /* initialize transmission unit */
2566 ixgbe_dev_tx_init(dev);
2568 /* This can fail when allocating mbufs for descriptor rings */
2569 err = ixgbe_dev_rx_init(dev);
2571 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2575 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2576 ETH_VLAN_EXTEND_MASK;
2577 ixgbe_vlan_offload_set(dev, mask);
2579 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2580 /* Enable vlan filtering for VMDq */
2581 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2584 /* Configure DCB hw */
2585 ixgbe_configure_dcb(dev);
2587 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2588 err = ixgbe_fdir_configure(dev);
2593 /* Restore vf rate limit */
2594 if (vfinfo != NULL) {
2595 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2596 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2597 if (vfinfo[vf].tx_rate[idx] != 0)
2598 ixgbe_set_vf_rate_limit(
2600 vfinfo[vf].tx_rate[idx],
2604 ixgbe_restore_statistics_mapping(dev);
2606 err = ixgbe_dev_rxtx_start(dev);
2608 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2612 /* Skip link setup if loopback mode is enabled for 82599. */
2613 if (hw->mac.type == ixgbe_mac_82599EB &&
2614 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2615 goto skip_link_setup;
2617 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2618 err = hw->mac.ops.setup_sfp(hw);
2623 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2624 /* Turn on the copper */
2625 ixgbe_set_phy_power(hw, true);
2627 /* Turn on the laser */
2628 ixgbe_enable_tx_laser(hw);
2631 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2634 dev->data->dev_link.link_status = link_up;
2636 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2640 link_speeds = &dev->data->dev_conf.link_speeds;
2641 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2642 ETH_LINK_SPEED_10G)) {
2643 PMD_INIT_LOG(ERR, "Invalid link setting");
2648 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2649 switch (hw->mac.type) {
2650 case ixgbe_mac_82598EB:
2651 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2653 case ixgbe_mac_82599EB:
2654 case ixgbe_mac_X540:
2655 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2657 case ixgbe_mac_X550:
2658 case ixgbe_mac_X550EM_x:
2659 case ixgbe_mac_X550EM_a:
2660 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2663 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2666 if (*link_speeds & ETH_LINK_SPEED_10G)
2667 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2668 if (*link_speeds & ETH_LINK_SPEED_1G)
2669 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2670 if (*link_speeds & ETH_LINK_SPEED_100M)
2671 speed |= IXGBE_LINK_SPEED_100_FULL;
2674 err = ixgbe_setup_link(hw, speed, link_up);
2680 if (rte_intr_allow_others(intr_handle)) {
2681 /* check if lsc interrupt is enabled */
2682 if (dev->data->dev_conf.intr_conf.lsc != 0)
2683 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2685 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2686 ixgbe_dev_macsec_interrupt_setup(dev);
2688 rte_intr_callback_unregister(intr_handle,
2689 ixgbe_dev_interrupt_handler, dev);
2690 if (dev->data->dev_conf.intr_conf.lsc != 0)
2691 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2692 " no intr multiplex");
2695 /* check if rxq interrupt is enabled */
2696 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2697 rte_intr_dp_is_en(intr_handle))
2698 ixgbe_dev_rxq_interrupt_setup(dev);
2700 /* enable uio/vfio intr/eventfd mapping */
2701 rte_intr_enable(intr_handle);
2703 /* resume enabled intr since hw reset */
2704 ixgbe_enable_intr(dev);
2705 ixgbe_l2_tunnel_conf(dev);
2706 ixgbe_filter_restore(dev);
2708 if (tm_conf->root && !tm_conf->committed)
2709 PMD_DRV_LOG(WARNING,
2710 "please call hierarchy_commit() "
2711 "before starting the port");
2716 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2717 ixgbe_dev_clear_queues(dev);
2722 * Stop device: disable rx and tx functions to allow for reconfiguring.
2725 ixgbe_dev_stop(struct rte_eth_dev *dev)
2727 struct rte_eth_link link;
2728 struct ixgbe_hw *hw =
2729 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2730 struct ixgbe_vf_info *vfinfo =
2731 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2732 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2733 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2735 struct ixgbe_tm_conf *tm_conf =
2736 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2738 PMD_INIT_FUNC_TRACE();
2740 /* disable interrupts */
2741 ixgbe_disable_intr(hw);
2744 ixgbe_pf_reset_hw(hw);
2745 hw->adapter_stopped = 0;
2748 ixgbe_stop_adapter(hw);
2750 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2751 vfinfo[vf].clear_to_send = false;
2753 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2754 /* Turn off the copper */
2755 ixgbe_set_phy_power(hw, false);
2757 /* Turn off the laser */
2758 ixgbe_disable_tx_laser(hw);
2761 ixgbe_dev_clear_queues(dev);
2763 /* Clear stored conf */
2764 dev->data->scattered_rx = 0;
2767 /* Clear recorded link status */
2768 memset(&link, 0, sizeof(link));
2769 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2771 if (!rte_intr_allow_others(intr_handle))
2772 /* resume to the default handler */
2773 rte_intr_callback_register(intr_handle,
2774 ixgbe_dev_interrupt_handler,
2777 /* Clean datapath event and queue/vec mapping */
2778 rte_intr_efd_disable(intr_handle);
2779 if (intr_handle->intr_vec != NULL) {
2780 rte_free(intr_handle->intr_vec);
2781 intr_handle->intr_vec = NULL;
2784 /* reset hierarchy commit */
2785 tm_conf->committed = false;
2789 * Set device link up: enable tx.
2792 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2794 struct ixgbe_hw *hw =
2795 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2796 if (hw->mac.type == ixgbe_mac_82599EB) {
2797 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2798 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2799 /* Not suported in bypass mode */
2800 PMD_INIT_LOG(ERR, "Set link up is not supported "
2801 "by device id 0x%x", hw->device_id);
2807 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2808 /* Turn on the copper */
2809 ixgbe_set_phy_power(hw, true);
2811 /* Turn on the laser */
2812 ixgbe_enable_tx_laser(hw);
2819 * Set device link down: disable tx.
2822 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2824 struct ixgbe_hw *hw =
2825 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2826 if (hw->mac.type == ixgbe_mac_82599EB) {
2827 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2828 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2829 /* Not suported in bypass mode */
2830 PMD_INIT_LOG(ERR, "Set link down is not supported "
2831 "by device id 0x%x", hw->device_id);
2837 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2838 /* Turn off the copper */
2839 ixgbe_set_phy_power(hw, false);
2841 /* Turn off the laser */
2842 ixgbe_disable_tx_laser(hw);
2849 * Reset and stop device.
2852 ixgbe_dev_close(struct rte_eth_dev *dev)
2854 struct ixgbe_hw *hw =
2855 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2857 PMD_INIT_FUNC_TRACE();
2859 ixgbe_pf_reset_hw(hw);
2861 ixgbe_dev_stop(dev);
2862 hw->adapter_stopped = 1;
2864 ixgbe_dev_free_queues(dev);
2866 ixgbe_disable_pcie_master(hw);
2868 /* reprogram the RAR[0] in case user changed it. */
2869 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2876 ixgbe_dev_reset(struct rte_eth_dev *dev)
2880 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2881 * its VF to make them align with it. The detailed notification
2882 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2883 * To avoid unexpected behavior in VF, currently reset of PF with
2884 * SR-IOV activation is not supported. It might be supported later.
2886 if (dev->data->sriov.active)
2889 ret = eth_ixgbe_dev_uninit(dev);
2893 ret = eth_ixgbe_dev_init(dev);
2899 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2900 struct ixgbe_hw_stats *hw_stats,
2901 struct ixgbe_macsec_stats *macsec_stats,
2902 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2903 uint64_t *total_qprc, uint64_t *total_qprdc)
2905 uint32_t bprc, lxon, lxoff, total;
2906 uint32_t delta_gprc = 0;
2908 /* Workaround for RX byte count not including CRC bytes when CRC
2909 * strip is enabled. CRC bytes are removed from counters when crc_strip
2912 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2913 IXGBE_HLREG0_RXCRCSTRP);
2915 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2916 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2917 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2918 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2920 for (i = 0; i < 8; i++) {
2921 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2923 /* global total per queue */
2924 hw_stats->mpc[i] += mp;
2925 /* Running comprehensive total for stats display */
2926 *total_missed_rx += hw_stats->mpc[i];
2927 if (hw->mac.type == ixgbe_mac_82598EB) {
2928 hw_stats->rnbc[i] +=
2929 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2930 hw_stats->pxonrxc[i] +=
2931 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2932 hw_stats->pxoffrxc[i] +=
2933 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2935 hw_stats->pxonrxc[i] +=
2936 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2937 hw_stats->pxoffrxc[i] +=
2938 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2939 hw_stats->pxon2offc[i] +=
2940 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2942 hw_stats->pxontxc[i] +=
2943 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2944 hw_stats->pxofftxc[i] +=
2945 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2947 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2948 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2949 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2950 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2952 delta_gprc += delta_qprc;
2954 hw_stats->qprc[i] += delta_qprc;
2955 hw_stats->qptc[i] += delta_qptc;
2957 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2958 hw_stats->qbrc[i] +=
2959 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2961 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2963 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2964 hw_stats->qbtc[i] +=
2965 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2967 hw_stats->qprdc[i] += delta_qprdc;
2968 *total_qprdc += hw_stats->qprdc[i];
2970 *total_qprc += hw_stats->qprc[i];
2971 *total_qbrc += hw_stats->qbrc[i];
2973 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2974 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2975 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2978 * An errata states that gprc actually counts good + missed packets:
2979 * Workaround to set gprc to summated queue packet receives
2981 hw_stats->gprc = *total_qprc;
2983 if (hw->mac.type != ixgbe_mac_82598EB) {
2984 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2985 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2986 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2987 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2988 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2989 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2990 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2991 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2993 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2994 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2995 /* 82598 only has a counter in the high register */
2996 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2997 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2998 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3000 uint64_t old_tpr = hw_stats->tpr;
3002 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3003 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3006 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3008 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3009 hw_stats->gptc += delta_gptc;
3010 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3011 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3014 * Workaround: mprc hardware is incorrectly counting
3015 * broadcasts, so for now we subtract those.
3017 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3018 hw_stats->bprc += bprc;
3019 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3020 if (hw->mac.type == ixgbe_mac_82598EB)
3021 hw_stats->mprc -= bprc;
3023 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3024 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3025 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3026 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3027 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3028 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3030 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3031 hw_stats->lxontxc += lxon;
3032 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3033 hw_stats->lxofftxc += lxoff;
3034 total = lxon + lxoff;
3036 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3037 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3038 hw_stats->gptc -= total;
3039 hw_stats->mptc -= total;
3040 hw_stats->ptc64 -= total;
3041 hw_stats->gotc -= total * ETHER_MIN_LEN;
3043 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3044 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3045 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3046 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3047 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3048 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3049 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3050 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3051 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3052 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3053 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3054 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3055 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3056 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3057 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3058 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3059 /* Only read FCOE on 82599 */
3060 if (hw->mac.type != ixgbe_mac_82598EB) {
3061 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3062 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3063 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3064 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3065 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3068 /* Flow Director Stats registers */
3069 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3070 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3072 /* MACsec Stats registers */
3073 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3074 macsec_stats->out_pkts_encrypted +=
3075 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3076 macsec_stats->out_pkts_protected +=
3077 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3078 macsec_stats->out_octets_encrypted +=
3079 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3080 macsec_stats->out_octets_protected +=
3081 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3082 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3083 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3084 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3085 macsec_stats->in_pkts_unknownsci +=
3086 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3087 macsec_stats->in_octets_decrypted +=
3088 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3089 macsec_stats->in_octets_validated +=
3090 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3091 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3092 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3093 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3094 for (i = 0; i < 2; i++) {
3095 macsec_stats->in_pkts_ok +=
3096 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3097 macsec_stats->in_pkts_invalid +=
3098 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3099 macsec_stats->in_pkts_notvalid +=
3100 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3102 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3103 macsec_stats->in_pkts_notusingsa +=
3104 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3108 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3111 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3113 struct ixgbe_hw *hw =
3114 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3115 struct ixgbe_hw_stats *hw_stats =
3116 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3117 struct ixgbe_macsec_stats *macsec_stats =
3118 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3119 dev->data->dev_private);
3120 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3123 total_missed_rx = 0;
3128 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3129 &total_qbrc, &total_qprc, &total_qprdc);
3134 /* Fill out the rte_eth_stats statistics structure */
3135 stats->ipackets = total_qprc;
3136 stats->ibytes = total_qbrc;
3137 stats->opackets = hw_stats->gptc;
3138 stats->obytes = hw_stats->gotc;
3140 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3141 stats->q_ipackets[i] = hw_stats->qprc[i];
3142 stats->q_opackets[i] = hw_stats->qptc[i];
3143 stats->q_ibytes[i] = hw_stats->qbrc[i];
3144 stats->q_obytes[i] = hw_stats->qbtc[i];
3145 stats->q_errors[i] = hw_stats->qprdc[i];
3149 stats->imissed = total_missed_rx;
3150 stats->ierrors = hw_stats->crcerrs +
3166 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3168 struct ixgbe_hw_stats *stats =
3169 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3171 /* HW registers are cleared on read */
3172 ixgbe_dev_stats_get(dev, NULL);
3174 /* Reset software totals */
3175 memset(stats, 0, sizeof(*stats));
3178 /* This function calculates the number of xstats based on the current config */
3180 ixgbe_xstats_calc_num(void) {
3181 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3182 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3183 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3186 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3187 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3189 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3190 unsigned stat, i, count;
3192 if (xstats_names != NULL) {
3195 /* Note: limit >= cnt_stats checked upstream
3196 * in rte_eth_xstats_names()
3199 /* Extended stats from ixgbe_hw_stats */
3200 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3201 snprintf(xstats_names[count].name,
3202 sizeof(xstats_names[count].name),
3204 rte_ixgbe_stats_strings[i].name);
3209 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3210 snprintf(xstats_names[count].name,
3211 sizeof(xstats_names[count].name),
3213 rte_ixgbe_macsec_strings[i].name);
3217 /* RX Priority Stats */
3218 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3219 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3220 snprintf(xstats_names[count].name,
3221 sizeof(xstats_names[count].name),
3222 "rx_priority%u_%s", i,
3223 rte_ixgbe_rxq_strings[stat].name);
3228 /* TX Priority Stats */
3229 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3230 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3231 snprintf(xstats_names[count].name,
3232 sizeof(xstats_names[count].name),
3233 "tx_priority%u_%s", i,
3234 rte_ixgbe_txq_strings[stat].name);
3242 static int ixgbe_dev_xstats_get_names_by_id(
3243 struct rte_eth_dev *dev,
3244 struct rte_eth_xstat_name *xstats_names,
3245 const uint64_t *ids,
3249 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3250 unsigned int stat, i, count;
3252 if (xstats_names != NULL) {
3255 /* Note: limit >= cnt_stats checked upstream
3256 * in rte_eth_xstats_names()
3259 /* Extended stats from ixgbe_hw_stats */
3260 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3261 snprintf(xstats_names[count].name,
3262 sizeof(xstats_names[count].name),
3264 rte_ixgbe_stats_strings[i].name);
3269 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3270 snprintf(xstats_names[count].name,
3271 sizeof(xstats_names[count].name),
3273 rte_ixgbe_macsec_strings[i].name);
3277 /* RX Priority Stats */
3278 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3279 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3280 snprintf(xstats_names[count].name,
3281 sizeof(xstats_names[count].name),
3282 "rx_priority%u_%s", i,
3283 rte_ixgbe_rxq_strings[stat].name);
3288 /* TX Priority Stats */
3289 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3290 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3291 snprintf(xstats_names[count].name,
3292 sizeof(xstats_names[count].name),
3293 "tx_priority%u_%s", i,
3294 rte_ixgbe_txq_strings[stat].name);
3303 uint16_t size = ixgbe_xstats_calc_num();
3304 struct rte_eth_xstat_name xstats_names_copy[size];
3306 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3309 for (i = 0; i < limit; i++) {
3310 if (ids[i] >= size) {
3311 PMD_INIT_LOG(ERR, "id value isn't valid");
3314 strcpy(xstats_names[i].name,
3315 xstats_names_copy[ids[i]].name);
3320 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3321 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3325 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3328 if (xstats_names != NULL)
3329 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3330 snprintf(xstats_names[i].name,
3331 sizeof(xstats_names[i].name),
3332 "%s", rte_ixgbevf_stats_strings[i].name);
3333 return IXGBEVF_NB_XSTATS;
3337 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3340 struct ixgbe_hw *hw =
3341 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3342 struct ixgbe_hw_stats *hw_stats =
3343 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3344 struct ixgbe_macsec_stats *macsec_stats =
3345 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3346 dev->data->dev_private);
3347 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3348 unsigned i, stat, count = 0;
3350 count = ixgbe_xstats_calc_num();
3355 total_missed_rx = 0;
3360 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3361 &total_qbrc, &total_qprc, &total_qprdc);
3363 /* If this is a reset xstats is NULL, and we have cleared the
3364 * registers by reading them.
3369 /* Extended stats from ixgbe_hw_stats */
3371 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3372 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3373 rte_ixgbe_stats_strings[i].offset);
3374 xstats[count].id = count;
3379 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3380 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3381 rte_ixgbe_macsec_strings[i].offset);
3382 xstats[count].id = count;
3386 /* RX Priority Stats */
3387 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3388 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3389 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3390 rte_ixgbe_rxq_strings[stat].offset +
3391 (sizeof(uint64_t) * i));
3392 xstats[count].id = count;
3397 /* TX Priority Stats */
3398 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3399 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3400 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3401 rte_ixgbe_txq_strings[stat].offset +
3402 (sizeof(uint64_t) * i));
3403 xstats[count].id = count;
3411 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3412 uint64_t *values, unsigned int n)
3415 struct ixgbe_hw *hw =
3416 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417 struct ixgbe_hw_stats *hw_stats =
3418 IXGBE_DEV_PRIVATE_TO_STATS(
3419 dev->data->dev_private);
3420 struct ixgbe_macsec_stats *macsec_stats =
3421 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3422 dev->data->dev_private);
3423 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3424 unsigned int i, stat, count = 0;
3426 count = ixgbe_xstats_calc_num();
3428 if (!ids && n < count)
3431 total_missed_rx = 0;
3436 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3437 &total_missed_rx, &total_qbrc, &total_qprc,
3440 /* If this is a reset xstats is NULL, and we have cleared the
3441 * registers by reading them.
3443 if (!ids && !values)
3446 /* Extended stats from ixgbe_hw_stats */
3448 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3449 values[count] = *(uint64_t *)(((char *)hw_stats) +
3450 rte_ixgbe_stats_strings[i].offset);
3455 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3456 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3457 rte_ixgbe_macsec_strings[i].offset);
3461 /* RX Priority Stats */
3462 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3463 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3465 *(uint64_t *)(((char *)hw_stats) +
3466 rte_ixgbe_rxq_strings[stat].offset +
3467 (sizeof(uint64_t) * i));
3472 /* TX Priority Stats */
3473 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3474 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3476 *(uint64_t *)(((char *)hw_stats) +
3477 rte_ixgbe_txq_strings[stat].offset +
3478 (sizeof(uint64_t) * i));
3486 uint16_t size = ixgbe_xstats_calc_num();
3487 uint64_t values_copy[size];
3489 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3491 for (i = 0; i < n; i++) {
3492 if (ids[i] >= size) {
3493 PMD_INIT_LOG(ERR, "id value isn't valid");
3496 values[i] = values_copy[ids[i]];
3502 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3504 struct ixgbe_hw_stats *stats =
3505 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3506 struct ixgbe_macsec_stats *macsec_stats =
3507 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3508 dev->data->dev_private);
3510 unsigned count = ixgbe_xstats_calc_num();
3512 /* HW registers are cleared on read */
3513 ixgbe_dev_xstats_get(dev, NULL, count);
3515 /* Reset software totals */
3516 memset(stats, 0, sizeof(*stats));
3517 memset(macsec_stats, 0, sizeof(*macsec_stats));
3521 ixgbevf_update_stats(struct rte_eth_dev *dev)
3523 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3524 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3525 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3527 /* Good Rx packet, include VF loopback */
3528 UPDATE_VF_STAT(IXGBE_VFGPRC,
3529 hw_stats->last_vfgprc, hw_stats->vfgprc);
3531 /* Good Rx octets, include VF loopback */
3532 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3533 hw_stats->last_vfgorc, hw_stats->vfgorc);
3535 /* Good Tx packet, include VF loopback */
3536 UPDATE_VF_STAT(IXGBE_VFGPTC,
3537 hw_stats->last_vfgptc, hw_stats->vfgptc);
3539 /* Good Tx octets, include VF loopback */
3540 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3541 hw_stats->last_vfgotc, hw_stats->vfgotc);
3543 /* Rx Multicst Packet */
3544 UPDATE_VF_STAT(IXGBE_VFMPRC,
3545 hw_stats->last_vfmprc, hw_stats->vfmprc);
3549 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3552 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3553 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3556 if (n < IXGBEVF_NB_XSTATS)
3557 return IXGBEVF_NB_XSTATS;
3559 ixgbevf_update_stats(dev);
3564 /* Extended stats */
3565 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3567 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3568 rte_ixgbevf_stats_strings[i].offset);
3571 return IXGBEVF_NB_XSTATS;
3575 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3577 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3578 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3580 ixgbevf_update_stats(dev);
3585 stats->ipackets = hw_stats->vfgprc;
3586 stats->ibytes = hw_stats->vfgorc;
3587 stats->opackets = hw_stats->vfgptc;
3588 stats->obytes = hw_stats->vfgotc;
3592 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3594 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3595 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3597 /* Sync HW register to the last stats */
3598 ixgbevf_dev_stats_get(dev, NULL);
3600 /* reset HW current stats*/
3601 hw_stats->vfgprc = 0;
3602 hw_stats->vfgorc = 0;
3603 hw_stats->vfgptc = 0;
3604 hw_stats->vfgotc = 0;
3608 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3610 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3611 u16 eeprom_verh, eeprom_verl;
3615 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3616 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3618 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3619 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3621 ret += 1; /* add the size of '\0' */
3622 if (fw_size < (u32)ret)
3629 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3631 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3632 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3633 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3635 dev_info->pci_dev = pci_dev;
3636 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3637 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3638 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3640 * When DCB/VT is off, maximum number of queues changes,
3641 * except for 82598EB, which remains constant.
3643 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3644 hw->mac.type != ixgbe_mac_82598EB)
3645 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3647 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3648 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3649 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3650 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3651 dev_info->max_vfs = pci_dev->max_vfs;
3652 if (hw->mac.type == ixgbe_mac_82598EB)
3653 dev_info->max_vmdq_pools = ETH_16_POOLS;
3655 dev_info->max_vmdq_pools = ETH_64_POOLS;
3656 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3657 dev_info->rx_offload_capa =
3658 DEV_RX_OFFLOAD_VLAN_STRIP |
3659 DEV_RX_OFFLOAD_IPV4_CKSUM |
3660 DEV_RX_OFFLOAD_UDP_CKSUM |
3661 DEV_RX_OFFLOAD_TCP_CKSUM;
3664 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3667 if ((hw->mac.type == ixgbe_mac_82599EB ||
3668 hw->mac.type == ixgbe_mac_X540) &&
3669 !RTE_ETH_DEV_SRIOV(dev).active)
3670 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3672 if (hw->mac.type == ixgbe_mac_82599EB ||
3673 hw->mac.type == ixgbe_mac_X540)
3674 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3676 if (hw->mac.type == ixgbe_mac_X550 ||
3677 hw->mac.type == ixgbe_mac_X550EM_x ||
3678 hw->mac.type == ixgbe_mac_X550EM_a)
3679 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3681 dev_info->tx_offload_capa =
3682 DEV_TX_OFFLOAD_VLAN_INSERT |
3683 DEV_TX_OFFLOAD_IPV4_CKSUM |
3684 DEV_TX_OFFLOAD_UDP_CKSUM |
3685 DEV_TX_OFFLOAD_TCP_CKSUM |
3686 DEV_TX_OFFLOAD_SCTP_CKSUM |
3687 DEV_TX_OFFLOAD_TCP_TSO;
3689 if (hw->mac.type == ixgbe_mac_82599EB ||
3690 hw->mac.type == ixgbe_mac_X540)
3691 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3693 if (hw->mac.type == ixgbe_mac_X550 ||
3694 hw->mac.type == ixgbe_mac_X550EM_x ||
3695 hw->mac.type == ixgbe_mac_X550EM_a)
3696 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3698 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3700 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3701 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3702 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3704 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3708 dev_info->default_txconf = (struct rte_eth_txconf) {
3710 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3711 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3712 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3714 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3715 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3716 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3717 ETH_TXQ_FLAGS_NOOFFLOADS,
3720 dev_info->rx_desc_lim = rx_desc_lim;
3721 dev_info->tx_desc_lim = tx_desc_lim;
3723 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3724 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3725 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3727 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3728 if (hw->mac.type == ixgbe_mac_X540 ||
3729 hw->mac.type == ixgbe_mac_X540_vf ||
3730 hw->mac.type == ixgbe_mac_X550 ||
3731 hw->mac.type == ixgbe_mac_X550_vf) {
3732 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3734 if (hw->mac.type == ixgbe_mac_X550) {
3735 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3736 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3740 static const uint32_t *
3741 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3743 static const uint32_t ptypes[] = {
3744 /* For non-vec functions,
3745 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3746 * for vec functions,
3747 * refers to _recv_raw_pkts_vec().
3751 RTE_PTYPE_L3_IPV4_EXT,
3753 RTE_PTYPE_L3_IPV6_EXT,
3757 RTE_PTYPE_TUNNEL_IP,
3758 RTE_PTYPE_INNER_L3_IPV6,
3759 RTE_PTYPE_INNER_L3_IPV6_EXT,
3760 RTE_PTYPE_INNER_L4_TCP,
3761 RTE_PTYPE_INNER_L4_UDP,
3765 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3766 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3767 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3768 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3771 #if defined(RTE_ARCH_X86)
3772 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3773 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3780 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3781 struct rte_eth_dev_info *dev_info)
3783 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3784 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786 dev_info->pci_dev = pci_dev;
3787 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3788 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3789 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3790 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3791 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3792 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3793 dev_info->max_vfs = pci_dev->max_vfs;
3794 if (hw->mac.type == ixgbe_mac_82598EB)
3795 dev_info->max_vmdq_pools = ETH_16_POOLS;
3797 dev_info->max_vmdq_pools = ETH_64_POOLS;
3798 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3799 DEV_RX_OFFLOAD_IPV4_CKSUM |
3800 DEV_RX_OFFLOAD_UDP_CKSUM |
3801 DEV_RX_OFFLOAD_TCP_CKSUM;
3802 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3803 DEV_TX_OFFLOAD_IPV4_CKSUM |
3804 DEV_TX_OFFLOAD_UDP_CKSUM |
3805 DEV_TX_OFFLOAD_TCP_CKSUM |
3806 DEV_TX_OFFLOAD_SCTP_CKSUM |
3807 DEV_TX_OFFLOAD_TCP_TSO;
3809 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3811 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3812 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3813 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3815 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3819 dev_info->default_txconf = (struct rte_eth_txconf) {
3821 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3822 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3823 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3825 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3826 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3827 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3828 ETH_TXQ_FLAGS_NOOFFLOADS,
3831 dev_info->rx_desc_lim = rx_desc_lim;
3832 dev_info->tx_desc_lim = tx_desc_lim;
3836 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3837 int *link_up, int wait_to_complete)
3840 * for a quick link status checking, wait_to_compelet == 0,
3841 * skip PF link status checking
3843 bool no_pflink_check = wait_to_complete == 0;
3844 struct ixgbe_mbx_info *mbx = &hw->mbx;
3845 struct ixgbe_mac_info *mac = &hw->mac;
3846 uint32_t links_reg, in_msg;
3849 /* If we were hit with a reset drop the link */
3850 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3851 mac->get_link_status = true;
3853 if (!mac->get_link_status)
3856 /* if link status is down no point in checking to see if pf is up */
3857 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3858 if (!(links_reg & IXGBE_LINKS_UP))
3861 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3862 * before the link status is correct
3864 if (mac->type == ixgbe_mac_82599_vf) {
3867 for (i = 0; i < 5; i++) {
3869 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3871 if (!(links_reg & IXGBE_LINKS_UP))
3876 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3877 case IXGBE_LINKS_SPEED_10G_82599:
3878 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3879 if (hw->mac.type >= ixgbe_mac_X550) {
3880 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3881 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3884 case IXGBE_LINKS_SPEED_1G_82599:
3885 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3887 case IXGBE_LINKS_SPEED_100_82599:
3888 *speed = IXGBE_LINK_SPEED_100_FULL;
3889 if (hw->mac.type == ixgbe_mac_X550) {
3890 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3891 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3894 case IXGBE_LINKS_SPEED_10_X550EM_A:
3895 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3896 /* Since Reserved in older MAC's */
3897 if (hw->mac.type >= ixgbe_mac_X550)
3898 *speed = IXGBE_LINK_SPEED_10_FULL;
3901 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3904 if (no_pflink_check) {
3905 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3906 mac->get_link_status = true;
3908 mac->get_link_status = false;
3912 /* if the read failed it could just be a mailbox collision, best wait
3913 * until we are called again and don't report an error
3915 if (mbx->ops.read(hw, &in_msg, 1, 0))
3918 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3919 /* msg is not CTS and is NACK we must have lost CTS status */
3920 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3925 /* the pf is talking, if we timed out in the past we reinit */
3926 if (!mbx->timeout) {
3931 /* if we passed all the tests above then the link is up and we no
3932 * longer need to check for link
3934 mac->get_link_status = false;
3937 *link_up = !mac->get_link_status;
3941 /* return 0 means link status changed, -1 means not changed */
3943 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3944 int wait_to_complete, int vf)
3946 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3947 struct rte_eth_link link, old;
3948 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3949 struct ixgbe_interrupt *intr =
3950 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3955 bool autoneg = false;
3957 link.link_status = ETH_LINK_DOWN;
3958 link.link_speed = 0;
3959 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3960 memset(&old, 0, sizeof(old));
3961 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3963 hw->mac.get_link_status = true;
3965 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3966 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3967 speed = hw->phy.autoneg_advertised;
3969 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3970 ixgbe_setup_link(hw, speed, true);
3973 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3974 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3978 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3980 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3983 link.link_speed = ETH_SPEED_NUM_100M;
3984 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3985 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3986 if (link.link_status == old.link_status)
3992 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3993 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3994 if (link.link_status == old.link_status)
3998 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3999 link.link_status = ETH_LINK_UP;
4000 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4002 switch (link_speed) {
4004 case IXGBE_LINK_SPEED_UNKNOWN:
4005 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4006 link.link_speed = ETH_SPEED_NUM_100M;
4009 case IXGBE_LINK_SPEED_100_FULL:
4010 link.link_speed = ETH_SPEED_NUM_100M;
4013 case IXGBE_LINK_SPEED_1GB_FULL:
4014 link.link_speed = ETH_SPEED_NUM_1G;
4017 case IXGBE_LINK_SPEED_2_5GB_FULL:
4018 link.link_speed = ETH_SPEED_NUM_2_5G;
4021 case IXGBE_LINK_SPEED_5GB_FULL:
4022 link.link_speed = ETH_SPEED_NUM_5G;
4025 case IXGBE_LINK_SPEED_10GB_FULL:
4026 link.link_speed = ETH_SPEED_NUM_10G;
4029 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4031 if (link.link_status == old.link_status)
4038 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4040 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4044 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4046 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4050 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4052 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4056 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4057 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4061 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4063 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4066 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4067 fctrl &= (~IXGBE_FCTRL_UPE);
4068 if (dev->data->all_multicast == 1)
4069 fctrl |= IXGBE_FCTRL_MPE;
4071 fctrl &= (~IXGBE_FCTRL_MPE);
4072 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4076 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4078 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4081 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4082 fctrl |= IXGBE_FCTRL_MPE;
4083 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4087 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4089 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4092 if (dev->data->promiscuous == 1)
4093 return; /* must remain in all_multicast mode */
4095 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4096 fctrl &= (~IXGBE_FCTRL_MPE);
4097 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4101 * It clears the interrupt causes and enables the interrupt.
4102 * It will be called once only during nic initialized.
4105 * Pointer to struct rte_eth_dev.
4107 * Enable or Disable.
4110 * - On success, zero.
4111 * - On failure, a negative value.
4114 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4116 struct ixgbe_interrupt *intr =
4117 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4119 ixgbe_dev_link_status_print(dev);
4121 intr->mask |= IXGBE_EICR_LSC;
4123 intr->mask &= ~IXGBE_EICR_LSC;
4129 * It clears the interrupt causes and enables the interrupt.
4130 * It will be called once only during nic initialized.
4133 * Pointer to struct rte_eth_dev.
4136 * - On success, zero.
4137 * - On failure, a negative value.
4140 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4142 struct ixgbe_interrupt *intr =
4143 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4145 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4151 * It clears the interrupt causes and enables the interrupt.
4152 * It will be called once only during nic initialized.
4155 * Pointer to struct rte_eth_dev.
4158 * - On success, zero.
4159 * - On failure, a negative value.
4162 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4164 struct ixgbe_interrupt *intr =
4165 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4167 intr->mask |= IXGBE_EICR_LINKSEC;
4173 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4176 * Pointer to struct rte_eth_dev.
4179 * - On success, zero.
4180 * - On failure, a negative value.
4183 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4186 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4187 struct ixgbe_interrupt *intr =
4188 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4190 /* clear all cause mask */
4191 ixgbe_disable_intr(hw);
4193 /* read-on-clear nic registers here */
4194 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4195 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4199 /* set flag for async link update */
4200 if (eicr & IXGBE_EICR_LSC)
4201 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4203 if (eicr & IXGBE_EICR_MAILBOX)
4204 intr->flags |= IXGBE_FLAG_MAILBOX;
4206 if (eicr & IXGBE_EICR_LINKSEC)
4207 intr->flags |= IXGBE_FLAG_MACSEC;
4209 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4210 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4211 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4212 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4218 * It gets and then prints the link status.
4221 * Pointer to struct rte_eth_dev.
4224 * - On success, zero.
4225 * - On failure, a negative value.
4228 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4230 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4231 struct rte_eth_link link;
4233 memset(&link, 0, sizeof(link));
4234 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4235 if (link.link_status) {
4236 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4237 (int)(dev->data->port_id),
4238 (unsigned)link.link_speed,
4239 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4240 "full-duplex" : "half-duplex");
4242 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4243 (int)(dev->data->port_id));
4245 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4246 pci_dev->addr.domain,
4248 pci_dev->addr.devid,
4249 pci_dev->addr.function);
4253 * It executes link_update after knowing an interrupt occurred.
4256 * Pointer to struct rte_eth_dev.
4259 * - On success, zero.
4260 * - On failure, a negative value.
4263 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4264 struct rte_intr_handle *intr_handle)
4266 struct ixgbe_interrupt *intr =
4267 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4269 struct rte_eth_link link;
4270 struct ixgbe_hw *hw =
4271 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4273 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4275 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4276 ixgbe_pf_mbx_process(dev);
4277 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4280 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4281 ixgbe_handle_lasi(hw);
4282 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4285 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4286 /* get the link status before link update, for predicting later */
4287 memset(&link, 0, sizeof(link));
4288 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4290 ixgbe_dev_link_update(dev, 0);
4293 if (!link.link_status)
4294 /* handle it 1 sec later, wait it being stable */
4295 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4296 /* likely to down */
4298 /* handle it 4 sec later, wait it being stable */
4299 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4301 ixgbe_dev_link_status_print(dev);
4302 if (rte_eal_alarm_set(timeout * 1000,
4303 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4304 PMD_DRV_LOG(ERR, "Error setting alarm");
4306 /* remember original mask */
4307 intr->mask_original = intr->mask;
4308 /* only disable lsc interrupt */
4309 intr->mask &= ~IXGBE_EIMS_LSC;
4313 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4314 ixgbe_enable_intr(dev);
4315 rte_intr_enable(intr_handle);
4321 * Interrupt handler which shall be registered for alarm callback for delayed
4322 * handling specific interrupt to wait for the stable nic state. As the
4323 * NIC interrupt state is not stable for ixgbe after link is just down,
4324 * it needs to wait 4 seconds to get the stable status.
4327 * Pointer to interrupt handle.
4329 * The address of parameter (struct rte_eth_dev *) regsitered before.
4335 ixgbe_dev_interrupt_delayed_handler(void *param)
4337 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4338 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4339 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4340 struct ixgbe_interrupt *intr =
4341 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4342 struct ixgbe_hw *hw =
4343 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4346 ixgbe_disable_intr(hw);
4348 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4349 if (eicr & IXGBE_EICR_MAILBOX)
4350 ixgbe_pf_mbx_process(dev);
4352 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4353 ixgbe_handle_lasi(hw);
4354 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4357 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4358 ixgbe_dev_link_update(dev, 0);
4359 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4360 ixgbe_dev_link_status_print(dev);
4361 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4365 if (intr->flags & IXGBE_FLAG_MACSEC) {
4366 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4368 intr->flags &= ~IXGBE_FLAG_MACSEC;
4371 /* restore original mask */
4372 intr->mask = intr->mask_original;
4373 intr->mask_original = 0;
4375 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4376 ixgbe_enable_intr(dev);
4377 rte_intr_enable(intr_handle);
4381 * Interrupt handler triggered by NIC for handling
4382 * specific interrupt.
4385 * Pointer to interrupt handle.
4387 * The address of parameter (struct rte_eth_dev *) regsitered before.
4393 ixgbe_dev_interrupt_handler(void *param)
4395 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4397 ixgbe_dev_interrupt_get_status(dev);
4398 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4402 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4404 struct ixgbe_hw *hw;
4406 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4411 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4413 struct ixgbe_hw *hw;
4415 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4416 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4420 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4422 struct ixgbe_hw *hw;
4428 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4430 fc_conf->pause_time = hw->fc.pause_time;
4431 fc_conf->high_water = hw->fc.high_water[0];
4432 fc_conf->low_water = hw->fc.low_water[0];
4433 fc_conf->send_xon = hw->fc.send_xon;
4434 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4437 * Return rx_pause status according to actual setting of
4440 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4441 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4447 * Return tx_pause status according to actual setting of
4450 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4451 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4456 if (rx_pause && tx_pause)
4457 fc_conf->mode = RTE_FC_FULL;
4459 fc_conf->mode = RTE_FC_RX_PAUSE;
4461 fc_conf->mode = RTE_FC_TX_PAUSE;
4463 fc_conf->mode = RTE_FC_NONE;
4469 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4471 struct ixgbe_hw *hw;
4473 uint32_t rx_buf_size;
4474 uint32_t max_high_water;
4476 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4483 PMD_INIT_FUNC_TRACE();
4485 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4486 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4487 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4490 * At least reserve one Ethernet frame for watermark
4491 * high_water/low_water in kilo bytes for ixgbe
4493 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4494 if ((fc_conf->high_water > max_high_water) ||
4495 (fc_conf->high_water < fc_conf->low_water)) {
4496 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4497 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4501 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4502 hw->fc.pause_time = fc_conf->pause_time;
4503 hw->fc.high_water[0] = fc_conf->high_water;
4504 hw->fc.low_water[0] = fc_conf->low_water;
4505 hw->fc.send_xon = fc_conf->send_xon;
4506 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4508 err = ixgbe_fc_enable(hw);
4510 /* Not negotiated is not an error case */
4511 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4513 /* check if we want to forward MAC frames - driver doesn't have native
4514 * capability to do that, so we'll write the registers ourselves */
4516 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4518 /* set or clear MFLCN.PMCF bit depending on configuration */
4519 if (fc_conf->mac_ctrl_frame_fwd != 0)
4520 mflcn |= IXGBE_MFLCN_PMCF;
4522 mflcn &= ~IXGBE_MFLCN_PMCF;
4524 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4525 IXGBE_WRITE_FLUSH(hw);
4530 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4535 * ixgbe_pfc_enable_generic - Enable flow control
4536 * @hw: pointer to hardware structure
4537 * @tc_num: traffic class number
4538 * Enable flow control according to the current settings.
4541 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4544 uint32_t mflcn_reg, fccfg_reg;
4546 uint32_t fcrtl, fcrth;
4550 /* Validate the water mark configuration */
4551 if (!hw->fc.pause_time) {
4552 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4556 /* Low water mark of zero causes XOFF floods */
4557 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4558 /* High/Low water can not be 0 */
4559 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4560 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4561 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4565 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4566 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4567 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4571 /* Negotiate the fc mode to use */
4572 ixgbe_fc_autoneg(hw);
4574 /* Disable any previous flow control settings */
4575 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4576 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4578 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4579 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4581 switch (hw->fc.current_mode) {
4584 * If the count of enabled RX Priority Flow control >1,
4585 * and the TX pause can not be disabled
4588 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4589 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4590 if (reg & IXGBE_FCRTH_FCEN)
4594 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4596 case ixgbe_fc_rx_pause:
4598 * Rx Flow control is enabled and Tx Flow control is
4599 * disabled by software override. Since there really
4600 * isn't a way to advertise that we are capable of RX
4601 * Pause ONLY, we will advertise that we support both
4602 * symmetric and asymmetric Rx PAUSE. Later, we will
4603 * disable the adapter's ability to send PAUSE frames.
4605 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4607 * If the count of enabled RX Priority Flow control >1,
4608 * and the TX pause can not be disabled
4611 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4612 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4613 if (reg & IXGBE_FCRTH_FCEN)
4617 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4619 case ixgbe_fc_tx_pause:
4621 * Tx Flow control is enabled, and Rx Flow control is
4622 * disabled by software override.
4624 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4627 /* Flow control (both Rx and Tx) is enabled by SW override. */
4628 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4629 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4632 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4633 ret_val = IXGBE_ERR_CONFIG;
4637 /* Set 802.3x based flow control settings. */
4638 mflcn_reg |= IXGBE_MFLCN_DPF;
4639 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4640 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4642 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4643 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4644 hw->fc.high_water[tc_num]) {
4645 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4646 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4647 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4649 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4651 * In order to prevent Tx hangs when the internal Tx
4652 * switch is enabled we must set the high water mark
4653 * to the maximum FCRTH value. This allows the Tx
4654 * switch to function even under heavy Rx workloads.
4656 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4658 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4660 /* Configure pause time (2 TCs per register) */
4661 reg = hw->fc.pause_time * 0x00010001;
4662 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4663 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4665 /* Configure flow control refresh threshold value */
4666 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4673 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4675 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4676 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4678 if (hw->mac.type != ixgbe_mac_82598EB) {
4679 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4685 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4688 uint32_t rx_buf_size;
4689 uint32_t max_high_water;
4691 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4692 struct ixgbe_hw *hw =
4693 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4694 struct ixgbe_dcb_config *dcb_config =
4695 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4697 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4704 PMD_INIT_FUNC_TRACE();
4706 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4707 tc_num = map[pfc_conf->priority];
4708 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4709 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4711 * At least reserve one Ethernet frame for watermark
4712 * high_water/low_water in kilo bytes for ixgbe
4714 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4715 if ((pfc_conf->fc.high_water > max_high_water) ||
4716 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4717 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4718 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4722 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4723 hw->fc.pause_time = pfc_conf->fc.pause_time;
4724 hw->fc.send_xon = pfc_conf->fc.send_xon;
4725 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4726 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4728 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4730 /* Not negotiated is not an error case */
4731 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4734 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4739 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4740 struct rte_eth_rss_reta_entry64 *reta_conf,
4743 uint16_t i, sp_reta_size;
4746 uint16_t idx, shift;
4747 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4750 PMD_INIT_FUNC_TRACE();
4752 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4753 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4758 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4759 if (reta_size != sp_reta_size) {
4760 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4761 "(%d) doesn't match the number hardware can supported "
4762 "(%d)", reta_size, sp_reta_size);
4766 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4767 idx = i / RTE_RETA_GROUP_SIZE;
4768 shift = i % RTE_RETA_GROUP_SIZE;
4769 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4773 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4774 if (mask == IXGBE_4_BIT_MASK)
4777 r = IXGBE_READ_REG(hw, reta_reg);
4778 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4779 if (mask & (0x1 << j))
4780 reta |= reta_conf[idx].reta[shift + j] <<
4783 reta |= r & (IXGBE_8_BIT_MASK <<
4786 IXGBE_WRITE_REG(hw, reta_reg, reta);
4793 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4794 struct rte_eth_rss_reta_entry64 *reta_conf,
4797 uint16_t i, sp_reta_size;
4800 uint16_t idx, shift;
4801 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804 PMD_INIT_FUNC_TRACE();
4805 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4806 if (reta_size != sp_reta_size) {
4807 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4808 "(%d) doesn't match the number hardware can supported "
4809 "(%d)", reta_size, sp_reta_size);
4813 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4814 idx = i / RTE_RETA_GROUP_SIZE;
4815 shift = i % RTE_RETA_GROUP_SIZE;
4816 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4821 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4822 reta = IXGBE_READ_REG(hw, reta_reg);
4823 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4824 if (mask & (0x1 << j))
4825 reta_conf[idx].reta[shift + j] =
4826 ((reta >> (CHAR_BIT * j)) &
4835 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4836 uint32_t index, uint32_t pool)
4838 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839 uint32_t enable_addr = 1;
4841 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4846 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4848 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850 ixgbe_clear_rar(hw, index);
4854 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4856 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4858 ixgbe_remove_rar(dev, 0);
4860 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4864 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4866 if (strcmp(dev->device->driver->name, drv->driver.name))
4873 is_ixgbe_supported(struct rte_eth_dev *dev)
4875 return is_device_supported(dev, &rte_ixgbe_pmd);
4879 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4883 struct ixgbe_hw *hw;
4884 struct rte_eth_dev_info dev_info;
4885 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4886 struct rte_eth_dev_data *dev_data = dev->data;
4888 ixgbe_dev_info_get(dev, &dev_info);
4890 /* check that mtu is within the allowed range */
4891 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4894 /* If device is started, refuse mtu that requires the support of
4895 * scattered packets when this feature has not been enabled before.
4897 if (dev_data->dev_started && !dev_data->scattered_rx &&
4898 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4899 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4900 PMD_INIT_LOG(ERR, "Stop port first.");
4904 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4905 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4907 /* switch to jumbo mode if needed */
4908 if (frame_size > ETHER_MAX_LEN) {
4909 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4910 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4912 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4913 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4915 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4917 /* update max frame size */
4918 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4920 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4921 maxfrs &= 0x0000FFFF;
4922 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4923 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4929 * Virtual Function operations
4932 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4934 PMD_INIT_FUNC_TRACE();
4936 /* Clear interrupt mask to stop from interrupts being generated */
4937 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4939 IXGBE_WRITE_FLUSH(hw);
4943 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4945 PMD_INIT_FUNC_TRACE();
4947 /* VF enable interrupt autoclean */
4948 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4949 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4950 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4952 IXGBE_WRITE_FLUSH(hw);
4956 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4958 struct rte_eth_conf *conf = &dev->data->dev_conf;
4959 struct ixgbe_adapter *adapter =
4960 (struct ixgbe_adapter *)dev->data->dev_private;
4962 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4963 dev->data->port_id);
4966 * VF has no ability to enable/disable HW CRC
4967 * Keep the persistent behavior the same as Host PF
4969 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4970 if (!conf->rxmode.hw_strip_crc) {
4971 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4972 conf->rxmode.hw_strip_crc = 1;
4975 if (conf->rxmode.hw_strip_crc) {
4976 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4977 conf->rxmode.hw_strip_crc = 0;
4982 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4983 * allocation or vector Rx preconditions we will reset it.
4985 adapter->rx_bulk_alloc_allowed = true;
4986 adapter->rx_vec_allowed = true;
4992 ixgbevf_dev_start(struct rte_eth_dev *dev)
4994 struct ixgbe_hw *hw =
4995 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4996 uint32_t intr_vector = 0;
4997 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4998 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5002 PMD_INIT_FUNC_TRACE();
5004 hw->mac.ops.reset_hw(hw);
5005 hw->mac.get_link_status = true;
5007 /* negotiate mailbox API version to use with the PF. */
5008 ixgbevf_negotiate_api(hw);
5010 ixgbevf_dev_tx_init(dev);
5012 /* This can fail when allocating mbufs for descriptor rings */
5013 err = ixgbevf_dev_rx_init(dev);
5015 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5016 ixgbe_dev_clear_queues(dev);
5021 ixgbevf_set_vfta_all(dev, 1);
5024 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5025 ETH_VLAN_EXTEND_MASK;
5026 ixgbevf_vlan_offload_set(dev, mask);
5028 ixgbevf_dev_rxtx_start(dev);
5030 /* check and configure queue intr-vector mapping */
5031 if (dev->data->dev_conf.intr_conf.rxq != 0) {
5032 intr_vector = dev->data->nb_rx_queues;
5033 if (rte_intr_efd_enable(intr_handle, intr_vector))
5037 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5038 intr_handle->intr_vec =
5039 rte_zmalloc("intr_vec",
5040 dev->data->nb_rx_queues * sizeof(int), 0);
5041 if (intr_handle->intr_vec == NULL) {
5042 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5043 " intr_vec", dev->data->nb_rx_queues);
5047 ixgbevf_configure_msix(dev);
5049 rte_intr_enable(intr_handle);
5051 /* Re-enable interrupt for VF */
5052 ixgbevf_intr_enable(hw);
5058 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5060 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5061 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5062 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5064 PMD_INIT_FUNC_TRACE();
5066 ixgbevf_intr_disable(hw);
5068 hw->adapter_stopped = 1;
5069 ixgbe_stop_adapter(hw);
5072 * Clear what we set, but we still keep shadow_vfta to
5073 * restore after device starts
5075 ixgbevf_set_vfta_all(dev, 0);
5077 /* Clear stored conf */
5078 dev->data->scattered_rx = 0;
5080 ixgbe_dev_clear_queues(dev);
5082 /* Clean datapath event and queue/vec mapping */
5083 rte_intr_efd_disable(intr_handle);
5084 if (intr_handle->intr_vec != NULL) {
5085 rte_free(intr_handle->intr_vec);
5086 intr_handle->intr_vec = NULL;
5091 ixgbevf_dev_close(struct rte_eth_dev *dev)
5093 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5095 PMD_INIT_FUNC_TRACE();
5099 ixgbevf_dev_stop(dev);
5101 ixgbe_dev_free_queues(dev);
5104 * Remove the VF MAC address ro ensure
5105 * that the VF traffic goes to the PF
5106 * after stop, close and detach of the VF
5108 ixgbevf_remove_mac_addr(dev, 0);
5115 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5119 ret = eth_ixgbevf_dev_uninit(dev);
5123 ret = eth_ixgbevf_dev_init(dev);
5128 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5130 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131 struct ixgbe_vfta *shadow_vfta =
5132 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5133 int i = 0, j = 0, vfta = 0, mask = 1;
5135 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5136 vfta = shadow_vfta->vfta[i];
5139 for (j = 0; j < 32; j++) {
5141 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5151 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5153 struct ixgbe_hw *hw =
5154 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5155 struct ixgbe_vfta *shadow_vfta =
5156 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5157 uint32_t vid_idx = 0;
5158 uint32_t vid_bit = 0;
5161 PMD_INIT_FUNC_TRACE();
5163 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5164 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5166 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5169 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5170 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5172 /* Save what we set and retore it after device reset */
5174 shadow_vfta->vfta[vid_idx] |= vid_bit;
5176 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5182 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5184 struct ixgbe_hw *hw =
5185 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5188 PMD_INIT_FUNC_TRACE();
5190 if (queue >= hw->mac.max_rx_queues)
5193 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5195 ctrl |= IXGBE_RXDCTL_VME;
5197 ctrl &= ~IXGBE_RXDCTL_VME;
5198 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5200 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5204 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5206 struct ixgbe_hw *hw =
5207 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5211 /* VF function only support hw strip feature, others are not support */
5212 if (mask & ETH_VLAN_STRIP_MASK) {
5213 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5215 for (i = 0; i < hw->mac.max_rx_queues; i++)
5216 ixgbevf_vlan_strip_queue_set(dev, i, on);
5221 ixgbe_vt_check(struct ixgbe_hw *hw)
5225 /* if Virtualization Technology is enabled */
5226 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5227 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5228 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5236 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5238 uint32_t vector = 0;
5240 switch (hw->mac.mc_filter_type) {
5241 case 0: /* use bits [47:36] of the address */
5242 vector = ((uc_addr->addr_bytes[4] >> 4) |
5243 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5245 case 1: /* use bits [46:35] of the address */
5246 vector = ((uc_addr->addr_bytes[4] >> 3) |
5247 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5249 case 2: /* use bits [45:34] of the address */
5250 vector = ((uc_addr->addr_bytes[4] >> 2) |
5251 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5253 case 3: /* use bits [43:32] of the address */
5254 vector = ((uc_addr->addr_bytes[4]) |
5255 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5257 default: /* Invalid mc_filter_type */
5261 /* vector can only be 12-bits or boundary will be exceeded */
5267 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5275 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5276 const uint32_t ixgbe_uta_bit_shift = 5;
5277 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5278 const uint32_t bit1 = 0x1;
5280 struct ixgbe_hw *hw =
5281 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5282 struct ixgbe_uta_info *uta_info =
5283 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5285 /* The UTA table only exists on 82599 hardware and newer */
5286 if (hw->mac.type < ixgbe_mac_82599EB)
5289 vector = ixgbe_uta_vector(hw, mac_addr);
5290 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5291 uta_shift = vector & ixgbe_uta_bit_mask;
5293 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5297 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5299 uta_info->uta_in_use++;
5300 reg_val |= (bit1 << uta_shift);
5301 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5303 uta_info->uta_in_use--;
5304 reg_val &= ~(bit1 << uta_shift);
5305 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5308 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5310 if (uta_info->uta_in_use > 0)
5311 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5312 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5314 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5320 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5323 struct ixgbe_hw *hw =
5324 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5325 struct ixgbe_uta_info *uta_info =
5326 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5328 /* The UTA table only exists on 82599 hardware and newer */
5329 if (hw->mac.type < ixgbe_mac_82599EB)
5333 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5334 uta_info->uta_shadow[i] = ~0;
5335 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5338 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5339 uta_info->uta_shadow[i] = 0;
5340 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5348 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5350 uint32_t new_val = orig_val;
5352 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5353 new_val |= IXGBE_VMOLR_AUPE;
5354 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5355 new_val |= IXGBE_VMOLR_ROMPE;
5356 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5357 new_val |= IXGBE_VMOLR_ROPE;
5358 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5359 new_val |= IXGBE_VMOLR_BAM;
5360 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5361 new_val |= IXGBE_VMOLR_MPE;
5366 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5367 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5368 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5369 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5370 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5371 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5372 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5375 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5376 struct rte_eth_mirror_conf *mirror_conf,
5377 uint8_t rule_id, uint8_t on)
5379 uint32_t mr_ctl, vlvf;
5380 uint32_t mp_lsb = 0;
5381 uint32_t mv_msb = 0;
5382 uint32_t mv_lsb = 0;
5383 uint32_t mp_msb = 0;
5386 uint64_t vlan_mask = 0;
5388 const uint8_t pool_mask_offset = 32;
5389 const uint8_t vlan_mask_offset = 32;
5390 const uint8_t dst_pool_offset = 8;
5391 const uint8_t rule_mr_offset = 4;
5392 const uint8_t mirror_rule_mask = 0x0F;
5394 struct ixgbe_mirror_info *mr_info =
5395 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5396 struct ixgbe_hw *hw =
5397 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5398 uint8_t mirror_type = 0;
5400 if (ixgbe_vt_check(hw) < 0)
5403 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5406 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5407 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5408 mirror_conf->rule_type);
5412 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5413 mirror_type |= IXGBE_MRCTL_VLME;
5414 /* Check if vlan id is valid and find conresponding VLAN ID
5417 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5418 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5419 /* search vlan id related pool vlan filter
5422 reg_index = ixgbe_find_vlvf_slot(
5424 mirror_conf->vlan.vlan_id[i],
5428 vlvf = IXGBE_READ_REG(hw,
5429 IXGBE_VLVF(reg_index));
5430 if ((vlvf & IXGBE_VLVF_VIEN) &&
5431 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5432 mirror_conf->vlan.vlan_id[i]))
5433 vlan_mask |= (1ULL << reg_index);
5440 mv_lsb = vlan_mask & 0xFFFFFFFF;
5441 mv_msb = vlan_mask >> vlan_mask_offset;
5443 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5444 mirror_conf->vlan.vlan_mask;
5445 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5446 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5447 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5448 mirror_conf->vlan.vlan_id[i];
5453 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5454 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5455 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5460 * if enable pool mirror, write related pool mask register,if disable
5461 * pool mirror, clear PFMRVM register
5463 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5464 mirror_type |= IXGBE_MRCTL_VPME;
5466 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5467 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5468 mr_info->mr_conf[rule_id].pool_mask =
5469 mirror_conf->pool_mask;
5474 mr_info->mr_conf[rule_id].pool_mask = 0;
5477 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5478 mirror_type |= IXGBE_MRCTL_UPME;
5479 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5480 mirror_type |= IXGBE_MRCTL_DPME;
5482 /* read mirror control register and recalculate it */
5483 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5486 mr_ctl |= mirror_type;
5487 mr_ctl &= mirror_rule_mask;
5488 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5490 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5493 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5494 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5496 /* write mirrror control register */
5497 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5499 /* write pool mirrror control register */
5500 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5501 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5502 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5505 /* write VLAN mirrror control register */
5506 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5507 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5508 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5516 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5519 uint32_t lsb_val = 0;
5520 uint32_t msb_val = 0;
5521 const uint8_t rule_mr_offset = 4;
5523 struct ixgbe_hw *hw =
5524 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5525 struct ixgbe_mirror_info *mr_info =
5526 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5528 if (ixgbe_vt_check(hw) < 0)
5531 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5534 memset(&mr_info->mr_conf[rule_id], 0,
5535 sizeof(struct rte_eth_mirror_conf));
5537 /* clear PFVMCTL register */
5538 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5540 /* clear pool mask register */
5541 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5542 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5544 /* clear vlan mask register */
5545 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5546 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5552 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5554 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5555 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5557 struct ixgbe_hw *hw =
5558 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5560 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5561 mask |= (1 << IXGBE_MISC_VEC_ID);
5562 RTE_SET_USED(queue_id);
5563 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5565 rte_intr_enable(intr_handle);
5571 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5574 struct ixgbe_hw *hw =
5575 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5577 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5578 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5579 RTE_SET_USED(queue_id);
5580 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5586 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5588 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5589 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5591 struct ixgbe_hw *hw =
5592 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5593 struct ixgbe_interrupt *intr =
5594 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5596 if (queue_id < 16) {
5597 ixgbe_disable_intr(hw);
5598 intr->mask |= (1 << queue_id);
5599 ixgbe_enable_intr(dev);
5600 } else if (queue_id < 32) {
5601 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5602 mask &= (1 << queue_id);
5603 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5604 } else if (queue_id < 64) {
5605 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5606 mask &= (1 << (queue_id - 32));
5607 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5609 rte_intr_enable(intr_handle);
5615 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5618 struct ixgbe_hw *hw =
5619 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5620 struct ixgbe_interrupt *intr =
5621 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5623 if (queue_id < 16) {
5624 ixgbe_disable_intr(hw);
5625 intr->mask &= ~(1 << queue_id);
5626 ixgbe_enable_intr(dev);
5627 } else if (queue_id < 32) {
5628 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5629 mask &= ~(1 << queue_id);
5630 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5631 } else if (queue_id < 64) {
5632 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5633 mask &= ~(1 << (queue_id - 32));
5634 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5641 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5642 uint8_t queue, uint8_t msix_vector)
5646 if (direction == -1) {
5648 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5649 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5652 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5654 /* rx or tx cause */
5655 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5656 idx = ((16 * (queue & 1)) + (8 * direction));
5657 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5658 tmp &= ~(0xFF << idx);
5659 tmp |= (msix_vector << idx);
5660 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5665 * set the IVAR registers, mapping interrupt causes to vectors
5667 * pointer to ixgbe_hw struct
5669 * 0 for Rx, 1 for Tx, -1 for other causes
5671 * queue to map the corresponding interrupt to
5673 * the vector to map to the corresponding queue
5676 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5677 uint8_t queue, uint8_t msix_vector)
5681 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5682 if (hw->mac.type == ixgbe_mac_82598EB) {
5683 if (direction == -1)
5685 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5686 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5687 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5688 tmp |= (msix_vector << (8 * (queue & 0x3)));
5689 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5690 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5691 (hw->mac.type == ixgbe_mac_X540) ||
5692 (hw->mac.type == ixgbe_mac_X550)) {
5693 if (direction == -1) {
5695 idx = ((queue & 1) * 8);
5696 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5697 tmp &= ~(0xFF << idx);
5698 tmp |= (msix_vector << idx);
5699 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5701 /* rx or tx causes */
5702 idx = ((16 * (queue & 1)) + (8 * direction));
5703 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5704 tmp &= ~(0xFF << idx);
5705 tmp |= (msix_vector << idx);
5706 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5712 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5714 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5715 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5716 struct ixgbe_hw *hw =
5717 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5719 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5721 /* Configure VF other cause ivar */
5722 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5724 /* won't configure msix register if no mapping is done
5725 * between intr vector and event fd.
5727 if (!rte_intr_dp_is_en(intr_handle))
5730 /* Configure all RX queues of VF */
5731 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5732 /* Force all queue use vector 0,
5733 * as IXGBE_VF_MAXMSIVECOTR = 1
5735 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5736 intr_handle->intr_vec[q_idx] = vector_idx;
5741 * Sets up the hardware to properly generate MSI-X interrupts
5743 * board private structure
5746 ixgbe_configure_msix(struct rte_eth_dev *dev)
5748 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5749 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5750 struct ixgbe_hw *hw =
5751 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5752 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5753 uint32_t vec = IXGBE_MISC_VEC_ID;
5757 /* won't configure msix register if no mapping is done
5758 * between intr vector and event fd
5760 if (!rte_intr_dp_is_en(intr_handle))
5763 if (rte_intr_allow_others(intr_handle))
5764 vec = base = IXGBE_RX_VEC_START;
5766 /* setup GPIE for MSI-x mode */
5767 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5768 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5769 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5770 /* auto clearing and auto setting corresponding bits in EIMS
5771 * when MSI-X interrupt is triggered
5773 if (hw->mac.type == ixgbe_mac_82598EB) {
5774 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5776 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5777 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5779 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5781 /* Populate the IVAR table and set the ITR values to the
5782 * corresponding register.
5784 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5786 /* by default, 1:1 mapping */
5787 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5788 intr_handle->intr_vec[queue_id] = vec;
5789 if (vec < base + intr_handle->nb_efd - 1)
5793 switch (hw->mac.type) {
5794 case ixgbe_mac_82598EB:
5795 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5798 case ixgbe_mac_82599EB:
5799 case ixgbe_mac_X540:
5800 case ixgbe_mac_X550:
5801 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5806 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5807 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5809 /* set up to autoclear timer, and the vectors */
5810 mask = IXGBE_EIMS_ENABLE_MASK;
5811 mask &= ~(IXGBE_EIMS_OTHER |
5812 IXGBE_EIMS_MAILBOX |
5815 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5819 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5820 uint16_t queue_idx, uint16_t tx_rate)
5822 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5823 uint32_t rf_dec, rf_int;
5825 uint16_t link_speed = dev->data->dev_link.link_speed;
5827 if (queue_idx >= hw->mac.max_tx_queues)
5831 /* Calculate the rate factor values to set */
5832 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5833 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5834 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5836 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5837 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5838 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5839 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5845 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5846 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5849 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5850 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5851 IXGBE_MAX_JUMBO_FRAME_SIZE))
5852 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5853 IXGBE_MMW_SIZE_JUMBO_FRAME);
5855 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5856 IXGBE_MMW_SIZE_DEFAULT);
5858 /* Set RTTBCNRC of queue X */
5859 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5860 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5861 IXGBE_WRITE_FLUSH(hw);
5867 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5868 __attribute__((unused)) uint32_t index,
5869 __attribute__((unused)) uint32_t pool)
5871 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5875 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5876 * operation. Trap this case to avoid exhausting the [very limited]
5877 * set of PF resources used to store VF MAC addresses.
5879 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5881 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5883 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5884 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5885 mac_addr->addr_bytes[0],
5886 mac_addr->addr_bytes[1],
5887 mac_addr->addr_bytes[2],
5888 mac_addr->addr_bytes[3],
5889 mac_addr->addr_bytes[4],
5890 mac_addr->addr_bytes[5],
5896 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5898 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5899 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5900 struct ether_addr *mac_addr;
5905 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5906 * not support the deletion of a given MAC address.
5907 * Instead, it imposes to delete all MAC addresses, then to add again
5908 * all MAC addresses with the exception of the one to be deleted.
5910 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5913 * Add again all MAC addresses, with the exception of the deleted one
5914 * and of the permanent MAC address.
5916 for (i = 0, mac_addr = dev->data->mac_addrs;
5917 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5918 /* Skip the deleted MAC address */
5921 /* Skip NULL MAC addresses */
5922 if (is_zero_ether_addr(mac_addr))
5924 /* Skip the permanent MAC address */
5925 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5927 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5930 "Adding again MAC address "
5931 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5933 mac_addr->addr_bytes[0],
5934 mac_addr->addr_bytes[1],
5935 mac_addr->addr_bytes[2],
5936 mac_addr->addr_bytes[3],
5937 mac_addr->addr_bytes[4],
5938 mac_addr->addr_bytes[5],
5944 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5946 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5948 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5952 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5953 struct rte_eth_syn_filter *filter,
5956 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5957 struct ixgbe_filter_info *filter_info =
5958 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5962 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5965 syn_info = filter_info->syn_info;
5968 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5970 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5971 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5973 if (filter->hig_pri)
5974 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5976 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5978 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5979 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5981 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5984 filter_info->syn_info = synqf;
5985 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5986 IXGBE_WRITE_FLUSH(hw);
5991 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5992 struct rte_eth_syn_filter *filter)
5994 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5995 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5997 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5998 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5999 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6006 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6007 enum rte_filter_op filter_op,
6010 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6013 MAC_TYPE_FILTER_SUP(hw->mac.type);
6015 if (filter_op == RTE_ETH_FILTER_NOP)
6019 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6024 switch (filter_op) {
6025 case RTE_ETH_FILTER_ADD:
6026 ret = ixgbe_syn_filter_set(dev,
6027 (struct rte_eth_syn_filter *)arg,
6030 case RTE_ETH_FILTER_DELETE:
6031 ret = ixgbe_syn_filter_set(dev,
6032 (struct rte_eth_syn_filter *)arg,
6035 case RTE_ETH_FILTER_GET:
6036 ret = ixgbe_syn_filter_get(dev,
6037 (struct rte_eth_syn_filter *)arg);
6040 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6049 static inline enum ixgbe_5tuple_protocol
6050 convert_protocol_type(uint8_t protocol_value)
6052 if (protocol_value == IPPROTO_TCP)
6053 return IXGBE_FILTER_PROTOCOL_TCP;
6054 else if (protocol_value == IPPROTO_UDP)
6055 return IXGBE_FILTER_PROTOCOL_UDP;
6056 else if (protocol_value == IPPROTO_SCTP)
6057 return IXGBE_FILTER_PROTOCOL_SCTP;
6059 return IXGBE_FILTER_PROTOCOL_NONE;
6062 /* inject a 5-tuple filter to HW */
6064 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6065 struct ixgbe_5tuple_filter *filter)
6067 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6069 uint32_t ftqf, sdpqf;
6070 uint32_t l34timir = 0;
6071 uint8_t mask = 0xff;
6075 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6076 IXGBE_SDPQF_DSTPORT_SHIFT);
6077 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6079 ftqf = (uint32_t)(filter->filter_info.proto &
6080 IXGBE_FTQF_PROTOCOL_MASK);
6081 ftqf |= (uint32_t)((filter->filter_info.priority &
6082 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6083 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6084 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6085 if (filter->filter_info.dst_ip_mask == 0)
6086 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6087 if (filter->filter_info.src_port_mask == 0)
6088 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6089 if (filter->filter_info.dst_port_mask == 0)
6090 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6091 if (filter->filter_info.proto_mask == 0)
6092 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6093 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6094 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6095 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6097 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6098 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6099 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6100 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6102 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6103 l34timir |= (uint32_t)(filter->queue <<
6104 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6105 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6109 * add a 5tuple filter
6112 * dev: Pointer to struct rte_eth_dev.
6113 * index: the index the filter allocates.
6114 * filter: ponter to the filter that will be added.
6115 * rx_queue: the queue id the filter assigned to.
6118 * - On success, zero.
6119 * - On failure, a negative value.
6122 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6123 struct ixgbe_5tuple_filter *filter)
6125 struct ixgbe_filter_info *filter_info =
6126 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6130 * look for an unused 5tuple filter index,
6131 * and insert the filter to list.
6133 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6134 idx = i / (sizeof(uint32_t) * NBBY);
6135 shift = i % (sizeof(uint32_t) * NBBY);
6136 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6137 filter_info->fivetuple_mask[idx] |= 1 << shift;
6139 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6145 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6146 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6150 ixgbe_inject_5tuple_filter(dev, filter);
6156 * remove a 5tuple filter
6159 * dev: Pointer to struct rte_eth_dev.
6160 * filter: the pointer of the filter will be removed.
6163 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6164 struct ixgbe_5tuple_filter *filter)
6166 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6167 struct ixgbe_filter_info *filter_info =
6168 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6169 uint16_t index = filter->index;
6171 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6172 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6173 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6176 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6177 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6178 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6179 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6180 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6184 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6186 struct ixgbe_hw *hw;
6187 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6188 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6190 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6192 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6195 /* refuse mtu that requires the support of scattered packets when this
6196 * feature has not been enabled before.
6198 if (!rx_conf->enable_scatter &&
6199 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6200 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6204 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6205 * request of the version 2.0 of the mailbox API.
6206 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6207 * of the mailbox API.
6208 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6209 * prior to 3.11.33 which contains the following change:
6210 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6212 ixgbevf_rlpml_set_vf(hw, max_frame);
6214 /* update max frame size */
6215 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6219 static inline struct ixgbe_5tuple_filter *
6220 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6221 struct ixgbe_5tuple_filter_info *key)
6223 struct ixgbe_5tuple_filter *it;
6225 TAILQ_FOREACH(it, filter_list, entries) {
6226 if (memcmp(key, &it->filter_info,
6227 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6234 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6236 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6237 struct ixgbe_5tuple_filter_info *filter_info)
6239 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6240 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6241 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6244 switch (filter->dst_ip_mask) {
6246 filter_info->dst_ip_mask = 0;
6247 filter_info->dst_ip = filter->dst_ip;
6250 filter_info->dst_ip_mask = 1;
6253 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6257 switch (filter->src_ip_mask) {
6259 filter_info->src_ip_mask = 0;
6260 filter_info->src_ip = filter->src_ip;
6263 filter_info->src_ip_mask = 1;
6266 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6270 switch (filter->dst_port_mask) {
6272 filter_info->dst_port_mask = 0;
6273 filter_info->dst_port = filter->dst_port;
6276 filter_info->dst_port_mask = 1;
6279 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6283 switch (filter->src_port_mask) {
6285 filter_info->src_port_mask = 0;
6286 filter_info->src_port = filter->src_port;
6289 filter_info->src_port_mask = 1;
6292 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6296 switch (filter->proto_mask) {
6298 filter_info->proto_mask = 0;
6299 filter_info->proto =
6300 convert_protocol_type(filter->proto);
6303 filter_info->proto_mask = 1;
6306 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6310 filter_info->priority = (uint8_t)filter->priority;
6315 * add or delete a ntuple filter
6318 * dev: Pointer to struct rte_eth_dev.
6319 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6320 * add: if true, add filter, if false, remove filter
6323 * - On success, zero.
6324 * - On failure, a negative value.
6327 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6328 struct rte_eth_ntuple_filter *ntuple_filter,
6331 struct ixgbe_filter_info *filter_info =
6332 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6333 struct ixgbe_5tuple_filter_info filter_5tuple;
6334 struct ixgbe_5tuple_filter *filter;
6337 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6338 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6342 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6343 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6347 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6349 if (filter != NULL && add) {
6350 PMD_DRV_LOG(ERR, "filter exists.");
6353 if (filter == NULL && !add) {
6354 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6359 filter = rte_zmalloc("ixgbe_5tuple_filter",
6360 sizeof(struct ixgbe_5tuple_filter), 0);
6363 (void)rte_memcpy(&filter->filter_info,
6365 sizeof(struct ixgbe_5tuple_filter_info));
6366 filter->queue = ntuple_filter->queue;
6367 ret = ixgbe_add_5tuple_filter(dev, filter);
6373 ixgbe_remove_5tuple_filter(dev, filter);
6379 * get a ntuple filter
6382 * dev: Pointer to struct rte_eth_dev.
6383 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6386 * - On success, zero.
6387 * - On failure, a negative value.
6390 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6391 struct rte_eth_ntuple_filter *ntuple_filter)
6393 struct ixgbe_filter_info *filter_info =
6394 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6395 struct ixgbe_5tuple_filter_info filter_5tuple;
6396 struct ixgbe_5tuple_filter *filter;
6399 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6400 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6404 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6405 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6409 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6411 if (filter == NULL) {
6412 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6415 ntuple_filter->queue = filter->queue;
6420 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6421 * @dev: pointer to rte_eth_dev structure
6422 * @filter_op:operation will be taken.
6423 * @arg: a pointer to specific structure corresponding to the filter_op
6426 * - On success, zero.
6427 * - On failure, a negative value.
6430 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6431 enum rte_filter_op filter_op,
6434 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6437 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6439 if (filter_op == RTE_ETH_FILTER_NOP)
6443 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6448 switch (filter_op) {
6449 case RTE_ETH_FILTER_ADD:
6450 ret = ixgbe_add_del_ntuple_filter(dev,
6451 (struct rte_eth_ntuple_filter *)arg,
6454 case RTE_ETH_FILTER_DELETE:
6455 ret = ixgbe_add_del_ntuple_filter(dev,
6456 (struct rte_eth_ntuple_filter *)arg,
6459 case RTE_ETH_FILTER_GET:
6460 ret = ixgbe_get_ntuple_filter(dev,
6461 (struct rte_eth_ntuple_filter *)arg);
6464 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6472 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6473 struct rte_eth_ethertype_filter *filter,
6476 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6477 struct ixgbe_filter_info *filter_info =
6478 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6482 struct ixgbe_ethertype_filter ethertype_filter;
6484 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6487 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6488 filter->ether_type == ETHER_TYPE_IPv6) {
6489 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6490 " ethertype filter.", filter->ether_type);
6494 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6495 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6498 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6499 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6503 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6504 if (ret >= 0 && add) {
6505 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6506 filter->ether_type);
6509 if (ret < 0 && !add) {
6510 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6511 filter->ether_type);
6516 etqf = IXGBE_ETQF_FILTER_EN;
6517 etqf |= (uint32_t)filter->ether_type;
6518 etqs |= (uint32_t)((filter->queue <<
6519 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6520 IXGBE_ETQS_RX_QUEUE);
6521 etqs |= IXGBE_ETQS_QUEUE_EN;
6523 ethertype_filter.ethertype = filter->ether_type;
6524 ethertype_filter.etqf = etqf;
6525 ethertype_filter.etqs = etqs;
6526 ethertype_filter.conf = FALSE;
6527 ret = ixgbe_ethertype_filter_insert(filter_info,
6530 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6534 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6538 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6539 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6540 IXGBE_WRITE_FLUSH(hw);
6546 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6547 struct rte_eth_ethertype_filter *filter)
6549 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6550 struct ixgbe_filter_info *filter_info =
6551 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6552 uint32_t etqf, etqs;
6555 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6557 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6558 filter->ether_type);
6562 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6563 if (etqf & IXGBE_ETQF_FILTER_EN) {
6564 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6565 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6567 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6568 IXGBE_ETQS_RX_QUEUE_SHIFT;
6575 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6576 * @dev: pointer to rte_eth_dev structure
6577 * @filter_op:operation will be taken.
6578 * @arg: a pointer to specific structure corresponding to the filter_op
6581 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6582 enum rte_filter_op filter_op,
6585 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6588 MAC_TYPE_FILTER_SUP(hw->mac.type);
6590 if (filter_op == RTE_ETH_FILTER_NOP)
6594 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6599 switch (filter_op) {
6600 case RTE_ETH_FILTER_ADD:
6601 ret = ixgbe_add_del_ethertype_filter(dev,
6602 (struct rte_eth_ethertype_filter *)arg,
6605 case RTE_ETH_FILTER_DELETE:
6606 ret = ixgbe_add_del_ethertype_filter(dev,
6607 (struct rte_eth_ethertype_filter *)arg,
6610 case RTE_ETH_FILTER_GET:
6611 ret = ixgbe_get_ethertype_filter(dev,
6612 (struct rte_eth_ethertype_filter *)arg);
6615 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6623 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6624 enum rte_filter_type filter_type,
6625 enum rte_filter_op filter_op,
6630 switch (filter_type) {
6631 case RTE_ETH_FILTER_NTUPLE:
6632 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6634 case RTE_ETH_FILTER_ETHERTYPE:
6635 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6637 case RTE_ETH_FILTER_SYN:
6638 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6640 case RTE_ETH_FILTER_FDIR:
6641 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6643 case RTE_ETH_FILTER_L2_TUNNEL:
6644 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6646 case RTE_ETH_FILTER_GENERIC:
6647 if (filter_op != RTE_ETH_FILTER_GET)
6649 *(const void **)arg = &ixgbe_flow_ops;
6652 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6662 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6663 u8 **mc_addr_ptr, u32 *vmdq)
6668 mc_addr = *mc_addr_ptr;
6669 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6674 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6675 struct ether_addr *mc_addr_set,
6676 uint32_t nb_mc_addr)
6678 struct ixgbe_hw *hw;
6681 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6682 mc_addr_list = (u8 *)mc_addr_set;
6683 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6684 ixgbe_dev_addr_list_itr, TRUE);
6688 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6690 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6691 uint64_t systime_cycles;
6693 switch (hw->mac.type) {
6694 case ixgbe_mac_X550:
6695 case ixgbe_mac_X550EM_x:
6696 case ixgbe_mac_X550EM_a:
6697 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6698 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6699 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6703 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6704 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6708 return systime_cycles;
6712 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6714 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6715 uint64_t rx_tstamp_cycles;
6717 switch (hw->mac.type) {
6718 case ixgbe_mac_X550:
6719 case ixgbe_mac_X550EM_x:
6720 case ixgbe_mac_X550EM_a:
6721 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6722 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6723 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6727 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6728 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6729 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6733 return rx_tstamp_cycles;
6737 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6739 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6740 uint64_t tx_tstamp_cycles;
6742 switch (hw->mac.type) {
6743 case ixgbe_mac_X550:
6744 case ixgbe_mac_X550EM_x:
6745 case ixgbe_mac_X550EM_a:
6746 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6747 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6748 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6752 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6753 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6754 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6758 return tx_tstamp_cycles;
6762 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6764 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6765 struct ixgbe_adapter *adapter =
6766 (struct ixgbe_adapter *)dev->data->dev_private;
6767 struct rte_eth_link link;
6768 uint32_t incval = 0;
6771 /* Get current link speed. */
6772 memset(&link, 0, sizeof(link));
6773 ixgbe_dev_link_update(dev, 1);
6774 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6776 switch (link.link_speed) {
6777 case ETH_SPEED_NUM_100M:
6778 incval = IXGBE_INCVAL_100;
6779 shift = IXGBE_INCVAL_SHIFT_100;
6781 case ETH_SPEED_NUM_1G:
6782 incval = IXGBE_INCVAL_1GB;
6783 shift = IXGBE_INCVAL_SHIFT_1GB;
6785 case ETH_SPEED_NUM_10G:
6787 incval = IXGBE_INCVAL_10GB;
6788 shift = IXGBE_INCVAL_SHIFT_10GB;
6792 switch (hw->mac.type) {
6793 case ixgbe_mac_X550:
6794 case ixgbe_mac_X550EM_x:
6795 case ixgbe_mac_X550EM_a:
6796 /* Independent of link speed. */
6798 /* Cycles read will be interpreted as ns. */
6801 case ixgbe_mac_X540:
6802 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6804 case ixgbe_mac_82599EB:
6805 incval >>= IXGBE_INCVAL_SHIFT_82599;
6806 shift -= IXGBE_INCVAL_SHIFT_82599;
6807 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6808 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6811 /* Not supported. */
6815 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6816 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6817 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6819 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6820 adapter->systime_tc.cc_shift = shift;
6821 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6823 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6824 adapter->rx_tstamp_tc.cc_shift = shift;
6825 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6827 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6828 adapter->tx_tstamp_tc.cc_shift = shift;
6829 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6833 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6835 struct ixgbe_adapter *adapter =
6836 (struct ixgbe_adapter *)dev->data->dev_private;
6838 adapter->systime_tc.nsec += delta;
6839 adapter->rx_tstamp_tc.nsec += delta;
6840 adapter->tx_tstamp_tc.nsec += delta;
6846 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6849 struct ixgbe_adapter *adapter =
6850 (struct ixgbe_adapter *)dev->data->dev_private;
6852 ns = rte_timespec_to_ns(ts);
6853 /* Set the timecounters to a new value. */
6854 adapter->systime_tc.nsec = ns;
6855 adapter->rx_tstamp_tc.nsec = ns;
6856 adapter->tx_tstamp_tc.nsec = ns;
6862 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6864 uint64_t ns, systime_cycles;
6865 struct ixgbe_adapter *adapter =
6866 (struct ixgbe_adapter *)dev->data->dev_private;
6868 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6869 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6870 *ts = rte_ns_to_timespec(ns);
6876 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6878 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6882 /* Stop the timesync system time. */
6883 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6884 /* Reset the timesync system time value. */
6885 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6886 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6888 /* Enable system time for platforms where it isn't on by default. */
6889 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6890 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6891 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6893 ixgbe_start_timecounters(dev);
6895 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6896 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6898 IXGBE_ETQF_FILTER_EN |
6901 /* Enable timestamping of received PTP packets. */
6902 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6903 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6904 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6906 /* Enable timestamping of transmitted PTP packets. */
6907 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6908 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6909 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6911 IXGBE_WRITE_FLUSH(hw);
6917 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6919 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6922 /* Disable timestamping of transmitted PTP packets. */
6923 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6924 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6925 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6927 /* Disable timestamping of received PTP packets. */
6928 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6929 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6930 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6932 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6933 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6935 /* Stop incrementating the System Time registers. */
6936 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6942 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6943 struct timespec *timestamp,
6944 uint32_t flags __rte_unused)
6946 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6947 struct ixgbe_adapter *adapter =
6948 (struct ixgbe_adapter *)dev->data->dev_private;
6949 uint32_t tsync_rxctl;
6950 uint64_t rx_tstamp_cycles;
6953 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6954 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6957 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6958 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6959 *timestamp = rte_ns_to_timespec(ns);
6965 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6966 struct timespec *timestamp)
6968 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6969 struct ixgbe_adapter *adapter =
6970 (struct ixgbe_adapter *)dev->data->dev_private;
6971 uint32_t tsync_txctl;
6972 uint64_t tx_tstamp_cycles;
6975 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6976 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6979 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6980 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6981 *timestamp = rte_ns_to_timespec(ns);
6987 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6989 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6992 const struct reg_info *reg_group;
6993 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6994 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6996 while ((reg_group = reg_set[g_ind++]))
6997 count += ixgbe_regs_group_count(reg_group);
7003 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7007 const struct reg_info *reg_group;
7009 while ((reg_group = ixgbevf_regs[g_ind++]))
7010 count += ixgbe_regs_group_count(reg_group);
7016 ixgbe_get_regs(struct rte_eth_dev *dev,
7017 struct rte_dev_reg_info *regs)
7019 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7020 uint32_t *data = regs->data;
7023 const struct reg_info *reg_group;
7024 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7025 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7028 regs->length = ixgbe_get_reg_length(dev);
7029 regs->width = sizeof(uint32_t);
7033 /* Support only full register dump */
7034 if ((regs->length == 0) ||
7035 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7036 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7038 while ((reg_group = reg_set[g_ind++]))
7039 count += ixgbe_read_regs_group(dev, &data[count],
7048 ixgbevf_get_regs(struct rte_eth_dev *dev,
7049 struct rte_dev_reg_info *regs)
7051 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7052 uint32_t *data = regs->data;
7055 const struct reg_info *reg_group;
7058 regs->length = ixgbevf_get_reg_length(dev);
7059 regs->width = sizeof(uint32_t);
7063 /* Support only full register dump */
7064 if ((regs->length == 0) ||
7065 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7066 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7068 while ((reg_group = ixgbevf_regs[g_ind++]))
7069 count += ixgbe_read_regs_group(dev, &data[count],
7078 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7080 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7082 /* Return unit is byte count */
7083 return hw->eeprom.word_size * 2;
7087 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7088 struct rte_dev_eeprom_info *in_eeprom)
7090 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7091 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7092 uint16_t *data = in_eeprom->data;
7095 first = in_eeprom->offset >> 1;
7096 length = in_eeprom->length >> 1;
7097 if ((first > hw->eeprom.word_size) ||
7098 ((first + length) > hw->eeprom.word_size))
7101 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7103 return eeprom->ops.read_buffer(hw, first, length, data);
7107 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7108 struct rte_dev_eeprom_info *in_eeprom)
7110 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7111 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7112 uint16_t *data = in_eeprom->data;
7115 first = in_eeprom->offset >> 1;
7116 length = in_eeprom->length >> 1;
7117 if ((first > hw->eeprom.word_size) ||
7118 ((first + length) > hw->eeprom.word_size))
7121 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7123 return eeprom->ops.write_buffer(hw, first, length, data);
7127 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7129 case ixgbe_mac_X550:
7130 case ixgbe_mac_X550EM_x:
7131 case ixgbe_mac_X550EM_a:
7132 return ETH_RSS_RETA_SIZE_512;
7133 case ixgbe_mac_X550_vf:
7134 case ixgbe_mac_X550EM_x_vf:
7135 case ixgbe_mac_X550EM_a_vf:
7136 return ETH_RSS_RETA_SIZE_64;
7138 return ETH_RSS_RETA_SIZE_128;
7143 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7145 case ixgbe_mac_X550:
7146 case ixgbe_mac_X550EM_x:
7147 case ixgbe_mac_X550EM_a:
7148 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7149 return IXGBE_RETA(reta_idx >> 2);
7151 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7152 case ixgbe_mac_X550_vf:
7153 case ixgbe_mac_X550EM_x_vf:
7154 case ixgbe_mac_X550EM_a_vf:
7155 return IXGBE_VFRETA(reta_idx >> 2);
7157 return IXGBE_RETA(reta_idx >> 2);
7162 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7164 case ixgbe_mac_X550_vf:
7165 case ixgbe_mac_X550EM_x_vf:
7166 case ixgbe_mac_X550EM_a_vf:
7167 return IXGBE_VFMRQC;
7174 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7176 case ixgbe_mac_X550_vf:
7177 case ixgbe_mac_X550EM_x_vf:
7178 case ixgbe_mac_X550EM_a_vf:
7179 return IXGBE_VFRSSRK(i);
7181 return IXGBE_RSSRK(i);
7186 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7188 case ixgbe_mac_82599_vf:
7189 case ixgbe_mac_X540_vf:
7197 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7198 struct rte_eth_dcb_info *dcb_info)
7200 struct ixgbe_dcb_config *dcb_config =
7201 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7202 struct ixgbe_dcb_tc_config *tc;
7205 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7206 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7208 dcb_info->nb_tcs = 1;
7210 if (dcb_config->vt_mode) { /* vt is enabled*/
7211 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7212 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7213 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7214 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7215 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7216 for (j = 0; j < dcb_info->nb_tcs; j++) {
7217 dcb_info->tc_queue.tc_rxq[i][j].base =
7218 i * dcb_info->nb_tcs + j;
7219 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7220 dcb_info->tc_queue.tc_txq[i][j].base =
7221 i * dcb_info->nb_tcs + j;
7222 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7225 } else { /* vt is disabled*/
7226 struct rte_eth_dcb_rx_conf *rx_conf =
7227 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7228 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7229 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7230 if (dcb_info->nb_tcs == ETH_4_TCS) {
7231 for (i = 0; i < dcb_info->nb_tcs; i++) {
7232 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7233 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7235 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7236 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7237 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7238 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7239 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7240 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7241 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7242 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7243 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7244 for (i = 0; i < dcb_info->nb_tcs; i++) {
7245 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7246 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7248 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7249 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7250 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7251 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7252 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7253 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7254 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7255 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7256 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7257 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7258 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7259 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7260 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7261 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7262 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7263 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7266 for (i = 0; i < dcb_info->nb_tcs; i++) {
7267 tc = &dcb_config->tc_config[i];
7268 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7273 /* Update e-tag ether type */
7275 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7276 uint16_t ether_type)
7278 uint32_t etag_etype;
7280 if (hw->mac.type != ixgbe_mac_X550 &&
7281 hw->mac.type != ixgbe_mac_X550EM_x &&
7282 hw->mac.type != ixgbe_mac_X550EM_a) {
7286 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7287 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7288 etag_etype |= ether_type;
7289 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7290 IXGBE_WRITE_FLUSH(hw);
7295 /* Config l2 tunnel ether type */
7297 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7298 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7301 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7302 struct ixgbe_l2_tn_info *l2_tn_info =
7303 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7305 if (l2_tunnel == NULL)
7308 switch (l2_tunnel->l2_tunnel_type) {
7309 case RTE_L2_TUNNEL_TYPE_E_TAG:
7310 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7311 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7314 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7322 /* Enable e-tag tunnel */
7324 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7326 uint32_t etag_etype;
7328 if (hw->mac.type != ixgbe_mac_X550 &&
7329 hw->mac.type != ixgbe_mac_X550EM_x &&
7330 hw->mac.type != ixgbe_mac_X550EM_a) {
7334 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7335 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7336 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7337 IXGBE_WRITE_FLUSH(hw);
7342 /* Enable l2 tunnel */
7344 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7345 enum rte_eth_tunnel_type l2_tunnel_type)
7348 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7349 struct ixgbe_l2_tn_info *l2_tn_info =
7350 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7352 switch (l2_tunnel_type) {
7353 case RTE_L2_TUNNEL_TYPE_E_TAG:
7354 l2_tn_info->e_tag_en = TRUE;
7355 ret = ixgbe_e_tag_enable(hw);
7358 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7366 /* Disable e-tag tunnel */
7368 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7370 uint32_t etag_etype;
7372 if (hw->mac.type != ixgbe_mac_X550 &&
7373 hw->mac.type != ixgbe_mac_X550EM_x &&
7374 hw->mac.type != ixgbe_mac_X550EM_a) {
7378 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7379 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7380 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7381 IXGBE_WRITE_FLUSH(hw);
7386 /* Disable l2 tunnel */
7388 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7389 enum rte_eth_tunnel_type l2_tunnel_type)
7392 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7393 struct ixgbe_l2_tn_info *l2_tn_info =
7394 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7396 switch (l2_tunnel_type) {
7397 case RTE_L2_TUNNEL_TYPE_E_TAG:
7398 l2_tn_info->e_tag_en = FALSE;
7399 ret = ixgbe_e_tag_disable(hw);
7402 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7411 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7412 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7415 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7416 uint32_t i, rar_entries;
7417 uint32_t rar_low, rar_high;
7419 if (hw->mac.type != ixgbe_mac_X550 &&
7420 hw->mac.type != ixgbe_mac_X550EM_x &&
7421 hw->mac.type != ixgbe_mac_X550EM_a) {
7425 rar_entries = ixgbe_get_num_rx_addrs(hw);
7427 for (i = 1; i < rar_entries; i++) {
7428 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7429 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7430 if ((rar_high & IXGBE_RAH_AV) &&
7431 (rar_high & IXGBE_RAH_ADTYPE) &&
7432 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7433 l2_tunnel->tunnel_id)) {
7434 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7435 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7437 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7447 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7448 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7451 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7452 uint32_t i, rar_entries;
7453 uint32_t rar_low, rar_high;
7455 if (hw->mac.type != ixgbe_mac_X550 &&
7456 hw->mac.type != ixgbe_mac_X550EM_x &&
7457 hw->mac.type != ixgbe_mac_X550EM_a) {
7461 /* One entry for one tunnel. Try to remove potential existing entry. */
7462 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7464 rar_entries = ixgbe_get_num_rx_addrs(hw);
7466 for (i = 1; i < rar_entries; i++) {
7467 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7468 if (rar_high & IXGBE_RAH_AV) {
7471 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7472 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7473 rar_low = l2_tunnel->tunnel_id;
7475 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7476 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7482 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7483 " Please remove a rule before adding a new one.");
7487 static inline struct ixgbe_l2_tn_filter *
7488 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7489 struct ixgbe_l2_tn_key *key)
7493 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7497 return l2_tn_info->hash_map[ret];
7501 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7502 struct ixgbe_l2_tn_filter *l2_tn_filter)
7506 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7507 &l2_tn_filter->key);
7511 "Failed to insert L2 tunnel filter"
7512 " to hash table %d!",
7517 l2_tn_info->hash_map[ret] = l2_tn_filter;
7519 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7525 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7526 struct ixgbe_l2_tn_key *key)
7529 struct ixgbe_l2_tn_filter *l2_tn_filter;
7531 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7535 "No such L2 tunnel filter to delete %d!",
7540 l2_tn_filter = l2_tn_info->hash_map[ret];
7541 l2_tn_info->hash_map[ret] = NULL;
7543 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7544 rte_free(l2_tn_filter);
7549 /* Add l2 tunnel filter */
7551 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7552 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7556 struct ixgbe_l2_tn_info *l2_tn_info =
7557 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7558 struct ixgbe_l2_tn_key key;
7559 struct ixgbe_l2_tn_filter *node;
7562 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7563 key.tn_id = l2_tunnel->tunnel_id;
7565 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7569 "The L2 tunnel filter already exists!");
7573 node = rte_zmalloc("ixgbe_l2_tn",
7574 sizeof(struct ixgbe_l2_tn_filter),
7579 (void)rte_memcpy(&node->key,
7581 sizeof(struct ixgbe_l2_tn_key));
7582 node->pool = l2_tunnel->pool;
7583 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7590 switch (l2_tunnel->l2_tunnel_type) {
7591 case RTE_L2_TUNNEL_TYPE_E_TAG:
7592 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7595 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7600 if ((!restore) && (ret < 0))
7601 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7606 /* Delete l2 tunnel filter */
7608 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7609 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7612 struct ixgbe_l2_tn_info *l2_tn_info =
7613 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7614 struct ixgbe_l2_tn_key key;
7616 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7617 key.tn_id = l2_tunnel->tunnel_id;
7618 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7622 switch (l2_tunnel->l2_tunnel_type) {
7623 case RTE_L2_TUNNEL_TYPE_E_TAG:
7624 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7627 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7636 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7637 * @dev: pointer to rte_eth_dev structure
7638 * @filter_op:operation will be taken.
7639 * @arg: a pointer to specific structure corresponding to the filter_op
7642 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7643 enum rte_filter_op filter_op,
7648 if (filter_op == RTE_ETH_FILTER_NOP)
7652 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7657 switch (filter_op) {
7658 case RTE_ETH_FILTER_ADD:
7659 ret = ixgbe_dev_l2_tunnel_filter_add
7661 (struct rte_eth_l2_tunnel_conf *)arg,
7664 case RTE_ETH_FILTER_DELETE:
7665 ret = ixgbe_dev_l2_tunnel_filter_del
7667 (struct rte_eth_l2_tunnel_conf *)arg);
7670 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7678 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7682 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7684 if (hw->mac.type != ixgbe_mac_X550 &&
7685 hw->mac.type != ixgbe_mac_X550EM_x &&
7686 hw->mac.type != ixgbe_mac_X550EM_a) {
7690 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7691 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7693 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7694 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7699 /* Enable l2 tunnel forwarding */
7701 ixgbe_dev_l2_tunnel_forwarding_enable
7702 (struct rte_eth_dev *dev,
7703 enum rte_eth_tunnel_type l2_tunnel_type)
7705 struct ixgbe_l2_tn_info *l2_tn_info =
7706 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7709 switch (l2_tunnel_type) {
7710 case RTE_L2_TUNNEL_TYPE_E_TAG:
7711 l2_tn_info->e_tag_fwd_en = TRUE;
7712 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7715 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7723 /* Disable l2 tunnel forwarding */
7725 ixgbe_dev_l2_tunnel_forwarding_disable
7726 (struct rte_eth_dev *dev,
7727 enum rte_eth_tunnel_type l2_tunnel_type)
7729 struct ixgbe_l2_tn_info *l2_tn_info =
7730 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7733 switch (l2_tunnel_type) {
7734 case RTE_L2_TUNNEL_TYPE_E_TAG:
7735 l2_tn_info->e_tag_fwd_en = FALSE;
7736 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7739 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7748 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7749 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7752 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7754 uint32_t vmtir, vmvir;
7755 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7757 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7759 "VF id %u should be less than %u",
7765 if (hw->mac.type != ixgbe_mac_X550 &&
7766 hw->mac.type != ixgbe_mac_X550EM_x &&
7767 hw->mac.type != ixgbe_mac_X550EM_a) {
7772 vmtir = l2_tunnel->tunnel_id;
7776 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7778 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7779 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7781 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7782 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7787 /* Enable l2 tunnel tag insertion */
7789 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7790 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7794 switch (l2_tunnel->l2_tunnel_type) {
7795 case RTE_L2_TUNNEL_TYPE_E_TAG:
7796 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7799 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7807 /* Disable l2 tunnel tag insertion */
7809 ixgbe_dev_l2_tunnel_insertion_disable
7810 (struct rte_eth_dev *dev,
7811 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7815 switch (l2_tunnel->l2_tunnel_type) {
7816 case RTE_L2_TUNNEL_TYPE_E_TAG:
7817 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7820 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7829 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7834 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7836 if (hw->mac.type != ixgbe_mac_X550 &&
7837 hw->mac.type != ixgbe_mac_X550EM_x &&
7838 hw->mac.type != ixgbe_mac_X550EM_a) {
7842 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7844 qde |= IXGBE_QDE_STRIP_TAG;
7846 qde &= ~IXGBE_QDE_STRIP_TAG;
7847 qde &= ~IXGBE_QDE_READ;
7848 qde |= IXGBE_QDE_WRITE;
7849 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7854 /* Enable l2 tunnel tag stripping */
7856 ixgbe_dev_l2_tunnel_stripping_enable
7857 (struct rte_eth_dev *dev,
7858 enum rte_eth_tunnel_type l2_tunnel_type)
7862 switch (l2_tunnel_type) {
7863 case RTE_L2_TUNNEL_TYPE_E_TAG:
7864 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7867 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7875 /* Disable l2 tunnel tag stripping */
7877 ixgbe_dev_l2_tunnel_stripping_disable
7878 (struct rte_eth_dev *dev,
7879 enum rte_eth_tunnel_type l2_tunnel_type)
7883 switch (l2_tunnel_type) {
7884 case RTE_L2_TUNNEL_TYPE_E_TAG:
7885 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7888 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7896 /* Enable/disable l2 tunnel offload functions */
7898 ixgbe_dev_l2_tunnel_offload_set
7899 (struct rte_eth_dev *dev,
7900 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7906 if (l2_tunnel == NULL)
7910 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7912 ret = ixgbe_dev_l2_tunnel_enable(
7914 l2_tunnel->l2_tunnel_type);
7916 ret = ixgbe_dev_l2_tunnel_disable(
7918 l2_tunnel->l2_tunnel_type);
7921 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7923 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7927 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7932 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7934 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7936 l2_tunnel->l2_tunnel_type);
7938 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7940 l2_tunnel->l2_tunnel_type);
7943 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7945 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7947 l2_tunnel->l2_tunnel_type);
7949 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7951 l2_tunnel->l2_tunnel_type);
7958 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7961 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7962 IXGBE_WRITE_FLUSH(hw);
7967 /* There's only one register for VxLAN UDP port.
7968 * So, we cannot add several ports. Will update it.
7971 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7975 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7979 return ixgbe_update_vxlan_port(hw, port);
7982 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7983 * UDP port, it must have a value.
7984 * So, will reset it to the original value 0.
7987 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7992 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7994 if (cur_port != port) {
7995 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7999 return ixgbe_update_vxlan_port(hw, 0);
8002 /* Add UDP tunneling port */
8004 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8005 struct rte_eth_udp_tunnel *udp_tunnel)
8008 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8010 if (hw->mac.type != ixgbe_mac_X550 &&
8011 hw->mac.type != ixgbe_mac_X550EM_x &&
8012 hw->mac.type != ixgbe_mac_X550EM_a) {
8016 if (udp_tunnel == NULL)
8019 switch (udp_tunnel->prot_type) {
8020 case RTE_TUNNEL_TYPE_VXLAN:
8021 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8024 case RTE_TUNNEL_TYPE_GENEVE:
8025 case RTE_TUNNEL_TYPE_TEREDO:
8026 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8031 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8039 /* Remove UDP tunneling port */
8041 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8042 struct rte_eth_udp_tunnel *udp_tunnel)
8045 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8047 if (hw->mac.type != ixgbe_mac_X550 &&
8048 hw->mac.type != ixgbe_mac_X550EM_x &&
8049 hw->mac.type != ixgbe_mac_X550EM_a) {
8053 if (udp_tunnel == NULL)
8056 switch (udp_tunnel->prot_type) {
8057 case RTE_TUNNEL_TYPE_VXLAN:
8058 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8060 case RTE_TUNNEL_TYPE_GENEVE:
8061 case RTE_TUNNEL_TYPE_TEREDO:
8062 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8066 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8075 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8077 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8079 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8083 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8085 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8087 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8090 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8092 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8095 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8098 /* PF reset VF event */
8099 if (in_msg == IXGBE_PF_CONTROL_MSG)
8100 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8105 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8108 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8109 struct ixgbe_interrupt *intr =
8110 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8111 ixgbevf_intr_disable(hw);
8113 /* read-on-clear nic registers here */
8114 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8117 /* only one misc vector supported - mailbox */
8118 eicr &= IXGBE_VTEICR_MASK;
8119 if (eicr == IXGBE_MISC_VEC_ID)
8120 intr->flags |= IXGBE_FLAG_MAILBOX;
8126 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8128 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8129 struct ixgbe_interrupt *intr =
8130 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8132 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8133 ixgbevf_mbx_process(dev);
8134 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8137 ixgbevf_intr_enable(hw);
8143 ixgbevf_dev_interrupt_handler(void *param)
8145 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8147 ixgbevf_dev_interrupt_get_status(dev);
8148 ixgbevf_dev_interrupt_action(dev);
8152 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8153 * @hw: pointer to hardware structure
8155 * Stops the transmit data path and waits for the HW to internally empty
8156 * the Tx security block
8158 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8160 #define IXGBE_MAX_SECTX_POLL 40
8165 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8166 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8167 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8168 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8169 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8170 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8172 /* Use interrupt-safe sleep just in case */
8176 /* For informational purposes only */
8177 if (i >= IXGBE_MAX_SECTX_POLL)
8178 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8179 "path fully disabled. Continuing with init.");
8181 return IXGBE_SUCCESS;
8185 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8186 * @hw: pointer to hardware structure
8188 * Enables the transmit data path.
8190 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8194 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8195 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8196 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8197 IXGBE_WRITE_FLUSH(hw);
8199 return IXGBE_SUCCESS;
8202 /* restore n-tuple filter */
8204 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8206 struct ixgbe_filter_info *filter_info =
8207 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8208 struct ixgbe_5tuple_filter *node;
8210 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8211 ixgbe_inject_5tuple_filter(dev, node);
8215 /* restore ethernet type filter */
8217 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8219 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8220 struct ixgbe_filter_info *filter_info =
8221 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8224 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8225 if (filter_info->ethertype_mask & (1 << i)) {
8226 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8227 filter_info->ethertype_filters[i].etqf);
8228 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8229 filter_info->ethertype_filters[i].etqs);
8230 IXGBE_WRITE_FLUSH(hw);
8235 /* restore SYN filter */
8237 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8239 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8240 struct ixgbe_filter_info *filter_info =
8241 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8244 synqf = filter_info->syn_info;
8246 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8247 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8248 IXGBE_WRITE_FLUSH(hw);
8252 /* restore L2 tunnel filter */
8254 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8256 struct ixgbe_l2_tn_info *l2_tn_info =
8257 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8258 struct ixgbe_l2_tn_filter *node;
8259 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8261 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8262 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8263 l2_tn_conf.tunnel_id = node->key.tn_id;
8264 l2_tn_conf.pool = node->pool;
8265 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8270 ixgbe_filter_restore(struct rte_eth_dev *dev)
8272 ixgbe_ntuple_filter_restore(dev);
8273 ixgbe_ethertype_filter_restore(dev);
8274 ixgbe_syn_filter_restore(dev);
8275 ixgbe_fdir_filter_restore(dev);
8276 ixgbe_l2_tn_filter_restore(dev);
8282 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8284 struct ixgbe_l2_tn_info *l2_tn_info =
8285 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8286 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8288 if (l2_tn_info->e_tag_en)
8289 (void)ixgbe_e_tag_enable(hw);
8291 if (l2_tn_info->e_tag_fwd_en)
8292 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8294 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8297 /* remove all the n-tuple filters */
8299 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8301 struct ixgbe_filter_info *filter_info =
8302 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8303 struct ixgbe_5tuple_filter *p_5tuple;
8305 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8306 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8309 /* remove all the ether type filters */
8311 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8313 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8314 struct ixgbe_filter_info *filter_info =
8315 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8318 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8319 if (filter_info->ethertype_mask & (1 << i) &&
8320 !filter_info->ethertype_filters[i].conf) {
8321 (void)ixgbe_ethertype_filter_remove(filter_info,
8323 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8324 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8325 IXGBE_WRITE_FLUSH(hw);
8330 /* remove the SYN filter */
8332 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8334 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8335 struct ixgbe_filter_info *filter_info =
8336 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8338 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8339 filter_info->syn_info = 0;
8341 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8342 IXGBE_WRITE_FLUSH(hw);
8346 /* remove all the L2 tunnel filters */
8348 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8350 struct ixgbe_l2_tn_info *l2_tn_info =
8351 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8352 struct ixgbe_l2_tn_filter *l2_tn_filter;
8353 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8356 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8357 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8358 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8359 l2_tn_conf.pool = l2_tn_filter->pool;
8360 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8368 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8369 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8370 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8371 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8372 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8373 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");