4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_hash_crc.h>
66 #include "ixgbe_logs.h"
67 #include "base/ixgbe_api.h"
68 #include "base/ixgbe_vf.h"
69 #include "base/ixgbe_common.h"
70 #include "ixgbe_ethdev.h"
71 #include "ixgbe_bypass.h"
72 #include "ixgbe_rxtx.h"
73 #include "base/ixgbe_type.h"
74 #include "base/ixgbe_phy.h"
75 #include "ixgbe_regs.h"
78 * High threshold controlling when to start sending XOFF frames. Must be at
79 * least 8 bytes less than receive packet buffer size. This value is in units
82 #define IXGBE_FC_HI 0x80
85 * Low threshold controlling when to start sending XON frames. This value is
86 * in units of 1024 bytes.
88 #define IXGBE_FC_LO 0x40
90 /* Default minimum inter-interrupt interval for EITR configuration */
91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
93 /* Timer value included in XOFF frames. */
94 #define IXGBE_FC_PAUSE 0x680
96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
97 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
98 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
100 #define IXGBE_MMW_SIZE_DEFAULT 0x4
101 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
102 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
105 * Default values for RX/TX configuration
107 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
108 #define IXGBE_DEFAULT_RX_PTHRESH 8
109 #define IXGBE_DEFAULT_RX_HTHRESH 8
110 #define IXGBE_DEFAULT_RX_WTHRESH 0
112 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
113 #define IXGBE_DEFAULT_TX_PTHRESH 32
114 #define IXGBE_DEFAULT_TX_HTHRESH 0
115 #define IXGBE_DEFAULT_TX_WTHRESH 0
116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
118 /* Bit shift and mask */
119 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
120 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
121 #define IXGBE_8_BIT_WIDTH CHAR_BIT
122 #define IXGBE_8_BIT_MASK UINT8_MAX
124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
128 #define IXGBE_HKEY_MAX_INDEX 10
130 /* Additional timesync values. */
131 #define NSEC_PER_SEC 1000000000L
132 #define IXGBE_INCVAL_10GB 0x66666666
133 #define IXGBE_INCVAL_1GB 0x40000000
134 #define IXGBE_INCVAL_100 0x50000000
135 #define IXGBE_INCVAL_SHIFT_10GB 28
136 #define IXGBE_INCVAL_SHIFT_1GB 24
137 #define IXGBE_INCVAL_SHIFT_100 21
138 #define IXGBE_INCVAL_SHIFT_82599 7
139 #define IXGBE_INCPER_SHIFT_82599 24
141 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
143 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
145 #define DEFAULT_ETAG_ETYPE 0x893f
146 #define IXGBE_ETAG_ETYPE 0x00005084
147 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
148 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
149 #define IXGBE_RAH_ADTYPE 0x40000000
150 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
151 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
154 #define IXGBE_QDE_STRIP_TAG 0x00000004
155 #define IXGBE_VTEICR_MASK 0x07
157 #define IXGBE_EXVET_VET_EXT_SHIFT 16
158 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
167 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
168 static int ixgbe_dev_start(struct rte_eth_dev *dev);
169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
171 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
178 int wait_to_complete);
179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
180 struct rte_eth_stats *stats);
181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
182 struct rte_eth_xstat *xstats, unsigned n);
183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
184 struct rte_eth_xstat *xstats, unsigned n);
186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
187 uint64_t *values, unsigned int n);
188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
190 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
191 struct rte_eth_xstat_name *xstats_names,
193 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
194 struct rte_eth_xstat_name *xstats_names, unsigned limit);
195 static int ixgbe_dev_xstats_get_names_by_id(
196 struct rte_eth_dev *dev,
197 struct rte_eth_xstat_name *xstats_names,
200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
207 struct rte_eth_dev_info *dev_info);
208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
210 struct rte_eth_dev_info *dev_info);
211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
214 uint16_t vlan_id, int on);
215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
216 enum rte_vlan_type vlan_type,
218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
219 uint16_t queue, bool on);
220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
231 struct rte_eth_fc_conf *fc_conf);
232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
233 struct rte_eth_fc_conf *fc_conf);
234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
235 struct rte_eth_pfc_conf *pfc_conf);
236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
237 struct rte_eth_rss_reta_entry64 *reta_conf,
239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
240 struct rte_eth_rss_reta_entry64 *reta_conf,
242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
248 struct rte_intr_handle *handle);
249 static void ixgbe_dev_interrupt_handler(void *param);
250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
252 uint32_t index, uint32_t pool);
253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
255 struct ether_addr *mac_addr);
256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
257 static bool is_device_supported(struct rte_eth_dev *dev,
258 struct rte_pci_driver *drv);
260 /* For Virtual Function support */
261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
263 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
264 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
265 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
266 int wait_to_complete);
267 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
268 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
269 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
270 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
271 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
272 struct rte_eth_stats *stats);
273 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
274 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
275 uint16_t vlan_id, int on);
276 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
277 uint16_t queue, int on);
278 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
279 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
280 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
282 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
284 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
285 uint8_t queue, uint8_t msix_vector);
286 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
287 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
288 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
290 /* For Eth VMDQ APIs support */
291 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
292 ether_addr * mac_addr, uint8_t on);
293 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
294 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
295 struct rte_eth_mirror_conf *mirror_conf,
296 uint8_t rule_id, uint8_t on);
297 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
299 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
301 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
303 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
304 uint8_t queue, uint8_t msix_vector);
305 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
307 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
308 uint16_t queue_idx, uint16_t tx_rate);
310 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
311 struct ether_addr *mac_addr,
312 uint32_t index, uint32_t pool);
313 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
314 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
315 struct ether_addr *mac_addr);
316 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
317 struct rte_eth_syn_filter *filter);
318 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
319 enum rte_filter_op filter_op,
321 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
322 struct ixgbe_5tuple_filter *filter);
323 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
324 struct ixgbe_5tuple_filter *filter);
325 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
326 enum rte_filter_op filter_op,
328 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
329 struct rte_eth_ntuple_filter *filter);
330 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
331 enum rte_filter_op filter_op,
333 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
334 struct rte_eth_ethertype_filter *filter);
335 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
336 enum rte_filter_type filter_type,
337 enum rte_filter_op filter_op,
339 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
341 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
342 struct ether_addr *mc_addr_set,
343 uint32_t nb_mc_addr);
344 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
345 struct rte_eth_dcb_info *dcb_info);
347 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
348 static int ixgbe_get_regs(struct rte_eth_dev *dev,
349 struct rte_dev_reg_info *regs);
350 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
351 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
352 struct rte_dev_eeprom_info *eeprom);
353 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
354 struct rte_dev_eeprom_info *eeprom);
356 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
357 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
358 struct rte_dev_reg_info *regs);
360 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
361 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
362 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
363 struct timespec *timestamp,
365 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
366 struct timespec *timestamp);
367 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
368 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
369 struct timespec *timestamp);
370 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
371 const struct timespec *timestamp);
372 static void ixgbevf_dev_interrupt_handler(void *param);
374 static int ixgbe_dev_l2_tunnel_eth_type_conf
375 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
376 static int ixgbe_dev_l2_tunnel_offload_set
377 (struct rte_eth_dev *dev,
378 struct rte_eth_l2_tunnel_conf *l2_tunnel,
381 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
382 enum rte_filter_op filter_op,
385 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
386 struct rte_eth_udp_tunnel *udp_tunnel);
387 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
388 struct rte_eth_udp_tunnel *udp_tunnel);
389 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
390 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
393 * Define VF Stats MACRO for Non "cleared on read" register
395 #define UPDATE_VF_STAT(reg, last, cur) \
397 uint32_t latest = IXGBE_READ_REG(hw, reg); \
398 cur += (latest - last) & UINT_MAX; \
402 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
404 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
405 u64 new_msb = IXGBE_READ_REG(hw, msb); \
406 u64 latest = ((new_msb << 32) | new_lsb); \
407 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
411 #define IXGBE_SET_HWSTRIP(h, q) do {\
412 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
413 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
414 (h)->bitmap[idx] |= 1 << bit;\
417 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
418 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
419 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
420 (h)->bitmap[idx] &= ~(1 << bit);\
423 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
424 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
425 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
426 (r) = (h)->bitmap[idx] >> bit & 1;\
430 * The set of PCI devices this driver supports
432 static const struct rte_pci_id pci_id_ixgbe_map[] = {
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
486 #ifdef RTE_LIBRTE_IXGBE_BYPASS
487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
489 { .vendor_id = 0, /* sentinel */ },
493 * The set of PCI devices this driver supports (for 82599 VF)
495 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
504 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
505 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
506 { .vendor_id = 0, /* sentinel */ },
509 static const struct rte_eth_desc_lim rx_desc_lim = {
510 .nb_max = IXGBE_MAX_RING_DESC,
511 .nb_min = IXGBE_MIN_RING_DESC,
512 .nb_align = IXGBE_RXD_ALIGN,
515 static const struct rte_eth_desc_lim tx_desc_lim = {
516 .nb_max = IXGBE_MAX_RING_DESC,
517 .nb_min = IXGBE_MIN_RING_DESC,
518 .nb_align = IXGBE_TXD_ALIGN,
519 .nb_seg_max = IXGBE_TX_MAX_SEG,
520 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
523 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
524 .dev_configure = ixgbe_dev_configure,
525 .dev_start = ixgbe_dev_start,
526 .dev_stop = ixgbe_dev_stop,
527 .dev_set_link_up = ixgbe_dev_set_link_up,
528 .dev_set_link_down = ixgbe_dev_set_link_down,
529 .dev_close = ixgbe_dev_close,
530 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
531 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
532 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
533 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
534 .link_update = ixgbe_dev_link_update,
535 .stats_get = ixgbe_dev_stats_get,
536 .xstats_get = ixgbe_dev_xstats_get,
537 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
538 .stats_reset = ixgbe_dev_stats_reset,
539 .xstats_reset = ixgbe_dev_xstats_reset,
540 .xstats_get_names = ixgbe_dev_xstats_get_names,
541 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
542 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
543 .fw_version_get = ixgbe_fw_version_get,
544 .dev_infos_get = ixgbe_dev_info_get,
545 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
546 .mtu_set = ixgbe_dev_mtu_set,
547 .vlan_filter_set = ixgbe_vlan_filter_set,
548 .vlan_tpid_set = ixgbe_vlan_tpid_set,
549 .vlan_offload_set = ixgbe_vlan_offload_set,
550 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
551 .rx_queue_start = ixgbe_dev_rx_queue_start,
552 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
553 .tx_queue_start = ixgbe_dev_tx_queue_start,
554 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
555 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
556 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
557 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
558 .rx_queue_release = ixgbe_dev_rx_queue_release,
559 .rx_queue_count = ixgbe_dev_rx_queue_count,
560 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
561 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
562 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
563 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
564 .tx_queue_release = ixgbe_dev_tx_queue_release,
565 .dev_led_on = ixgbe_dev_led_on,
566 .dev_led_off = ixgbe_dev_led_off,
567 .flow_ctrl_get = ixgbe_flow_ctrl_get,
568 .flow_ctrl_set = ixgbe_flow_ctrl_set,
569 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
570 .mac_addr_add = ixgbe_add_rar,
571 .mac_addr_remove = ixgbe_remove_rar,
572 .mac_addr_set = ixgbe_set_default_mac_addr,
573 .uc_hash_table_set = ixgbe_uc_hash_table_set,
574 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
575 .mirror_rule_set = ixgbe_mirror_rule_set,
576 .mirror_rule_reset = ixgbe_mirror_rule_reset,
577 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
578 .reta_update = ixgbe_dev_rss_reta_update,
579 .reta_query = ixgbe_dev_rss_reta_query,
580 .rss_hash_update = ixgbe_dev_rss_hash_update,
581 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
582 .filter_ctrl = ixgbe_dev_filter_ctrl,
583 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
584 .rxq_info_get = ixgbe_rxq_info_get,
585 .txq_info_get = ixgbe_txq_info_get,
586 .timesync_enable = ixgbe_timesync_enable,
587 .timesync_disable = ixgbe_timesync_disable,
588 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
589 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
590 .get_reg = ixgbe_get_regs,
591 .get_eeprom_length = ixgbe_get_eeprom_length,
592 .get_eeprom = ixgbe_get_eeprom,
593 .set_eeprom = ixgbe_set_eeprom,
594 .get_dcb_info = ixgbe_dev_get_dcb_info,
595 .timesync_adjust_time = ixgbe_timesync_adjust_time,
596 .timesync_read_time = ixgbe_timesync_read_time,
597 .timesync_write_time = ixgbe_timesync_write_time,
598 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
599 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
600 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
601 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
605 * dev_ops for virtual function, bare necessities for basic vf
606 * operation have been implemented
608 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
609 .dev_configure = ixgbevf_dev_configure,
610 .dev_start = ixgbevf_dev_start,
611 .dev_stop = ixgbevf_dev_stop,
612 .link_update = ixgbevf_dev_link_update,
613 .stats_get = ixgbevf_dev_stats_get,
614 .xstats_get = ixgbevf_dev_xstats_get,
615 .stats_reset = ixgbevf_dev_stats_reset,
616 .xstats_reset = ixgbevf_dev_stats_reset,
617 .xstats_get_names = ixgbevf_dev_xstats_get_names,
618 .dev_close = ixgbevf_dev_close,
619 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
620 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
621 .dev_infos_get = ixgbevf_dev_info_get,
622 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
623 .mtu_set = ixgbevf_dev_set_mtu,
624 .vlan_filter_set = ixgbevf_vlan_filter_set,
625 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
626 .vlan_offload_set = ixgbevf_vlan_offload_set,
627 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
628 .rx_queue_release = ixgbe_dev_rx_queue_release,
629 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
630 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
631 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
632 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
633 .tx_queue_release = ixgbe_dev_tx_queue_release,
634 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
635 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
636 .mac_addr_add = ixgbevf_add_mac_addr,
637 .mac_addr_remove = ixgbevf_remove_mac_addr,
638 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
639 .rxq_info_get = ixgbe_rxq_info_get,
640 .txq_info_get = ixgbe_txq_info_get,
641 .mac_addr_set = ixgbevf_set_default_mac_addr,
642 .get_reg = ixgbevf_get_regs,
643 .reta_update = ixgbe_dev_rss_reta_update,
644 .reta_query = ixgbe_dev_rss_reta_query,
645 .rss_hash_update = ixgbe_dev_rss_hash_update,
646 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
649 /* store statistics names and its offset in stats structure */
650 struct rte_ixgbe_xstats_name_off {
651 char name[RTE_ETH_XSTATS_NAME_SIZE];
655 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
656 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
657 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
658 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
659 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
660 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
661 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
662 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
663 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
664 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
665 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
666 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
667 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
668 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
669 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
670 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
672 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
674 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
675 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
676 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
677 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
678 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
679 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
680 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
681 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
682 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
683 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
684 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
685 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
686 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
687 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
688 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
689 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
690 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
692 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
694 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
695 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
696 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
697 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
699 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
701 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
703 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
705 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
707 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
709 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
712 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
713 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
714 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
716 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
717 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
718 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
719 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
720 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
722 {"rx_fcoe_no_direct_data_placement_ext_buff",
723 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
725 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
727 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
729 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
731 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
733 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
736 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
737 sizeof(rte_ixgbe_stats_strings[0]))
739 /* MACsec statistics */
740 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
741 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
743 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
744 out_pkts_encrypted)},
745 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
746 out_pkts_protected)},
747 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
748 out_octets_encrypted)},
749 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
750 out_octets_protected)},
751 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
753 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
755 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
757 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
758 in_pkts_unknownsci)},
759 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
760 in_octets_decrypted)},
761 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
762 in_octets_validated)},
763 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
765 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
769 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
771 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
773 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
775 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
777 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
778 in_pkts_notusingsa)},
781 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
782 sizeof(rte_ixgbe_macsec_strings[0]))
784 /* Per-queue statistics */
785 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
786 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
787 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
788 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
789 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
792 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
793 sizeof(rte_ixgbe_rxq_strings[0]))
794 #define IXGBE_NB_RXQ_PRIO_VALUES 8
796 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
797 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
798 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
799 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
803 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
804 sizeof(rte_ixgbe_txq_strings[0]))
805 #define IXGBE_NB_TXQ_PRIO_VALUES 8
807 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
808 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
811 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
812 sizeof(rte_ixgbevf_stats_strings[0]))
815 * Atomically reads the link status information from global
816 * structure rte_eth_dev.
819 * - Pointer to the structure rte_eth_dev to read from.
820 * - Pointer to the buffer to be saved with the link status.
823 * - On success, zero.
824 * - On failure, negative value.
827 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
828 struct rte_eth_link *link)
830 struct rte_eth_link *dst = link;
831 struct rte_eth_link *src = &(dev->data->dev_link);
833 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
834 *(uint64_t *)src) == 0)
841 * Atomically writes the link status information into global
842 * structure rte_eth_dev.
845 * - Pointer to the structure rte_eth_dev to read from.
846 * - Pointer to the buffer to be saved with the link status.
849 * - On success, zero.
850 * - On failure, negative value.
853 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
854 struct rte_eth_link *link)
856 struct rte_eth_link *dst = &(dev->data->dev_link);
857 struct rte_eth_link *src = link;
859 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
860 *(uint64_t *)src) == 0)
867 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
870 ixgbe_is_sfp(struct ixgbe_hw *hw)
872 switch (hw->phy.type) {
873 case ixgbe_phy_sfp_avago:
874 case ixgbe_phy_sfp_ftl:
875 case ixgbe_phy_sfp_intel:
876 case ixgbe_phy_sfp_unknown:
877 case ixgbe_phy_sfp_passive_tyco:
878 case ixgbe_phy_sfp_passive_unknown:
885 static inline int32_t
886 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
891 status = ixgbe_reset_hw(hw);
893 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
894 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
895 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
896 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
897 IXGBE_WRITE_FLUSH(hw);
899 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
900 status = IXGBE_SUCCESS;
905 ixgbe_enable_intr(struct rte_eth_dev *dev)
907 struct ixgbe_interrupt *intr =
908 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
909 struct ixgbe_hw *hw =
910 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
912 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
913 IXGBE_WRITE_FLUSH(hw);
917 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
920 ixgbe_disable_intr(struct ixgbe_hw *hw)
922 PMD_INIT_FUNC_TRACE();
924 if (hw->mac.type == ixgbe_mac_82598EB) {
925 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
927 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
928 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
929 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
931 IXGBE_WRITE_FLUSH(hw);
935 * This function resets queue statistics mapping registers.
936 * From Niantic datasheet, Initialization of Statistics section:
937 * "...if software requires the queue counters, the RQSMR and TQSM registers
938 * must be re-programmed following a device reset.
941 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
945 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
946 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
947 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
953 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
958 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
959 #define NB_QMAP_FIELDS_PER_QSM_REG 4
960 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
962 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
963 struct ixgbe_stat_mapping_registers *stat_mappings =
964 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
965 uint32_t qsmr_mask = 0;
966 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
970 if ((hw->mac.type != ixgbe_mac_82599EB) &&
971 (hw->mac.type != ixgbe_mac_X540) &&
972 (hw->mac.type != ixgbe_mac_X550) &&
973 (hw->mac.type != ixgbe_mac_X550EM_x) &&
974 (hw->mac.type != ixgbe_mac_X550EM_a))
977 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
978 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
981 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
982 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
983 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
986 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
988 /* Now clear any previous stat_idx set */
989 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
991 stat_mappings->tqsm[n] &= ~clearing_mask;
993 stat_mappings->rqsmr[n] &= ~clearing_mask;
995 q_map = (uint32_t)stat_idx;
996 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
997 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
999 stat_mappings->tqsm[n] |= qsmr_mask;
1001 stat_mappings->rqsmr[n] |= qsmr_mask;
1003 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1004 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1005 queue_id, stat_idx);
1006 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1007 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1009 /* Now write the mapping in the appropriate register */
1011 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1012 stat_mappings->rqsmr[n], n);
1013 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1015 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1016 stat_mappings->tqsm[n], n);
1017 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1023 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1025 struct ixgbe_stat_mapping_registers *stat_mappings =
1026 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1027 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030 /* write whatever was in stat mapping table to the NIC */
1031 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1033 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1036 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1041 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1044 struct ixgbe_dcb_tc_config *tc;
1045 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1047 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1048 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1049 for (i = 0; i < dcb_max_tc; i++) {
1050 tc = &dcb_config->tc_config[i];
1051 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1052 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1053 (uint8_t)(100/dcb_max_tc + (i & 1));
1054 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1055 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1056 (uint8_t)(100/dcb_max_tc + (i & 1));
1057 tc->pfc = ixgbe_dcb_pfc_disabled;
1060 /* Initialize default user to priority mapping, UPx->TC0 */
1061 tc = &dcb_config->tc_config[0];
1062 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1063 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1064 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1065 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1066 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1068 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1069 dcb_config->pfc_mode_enable = false;
1070 dcb_config->vt_mode = true;
1071 dcb_config->round_robin_enable = false;
1072 /* support all DCB capabilities in 82599 */
1073 dcb_config->support.capabilities = 0xFF;
1075 /*we only support 4 Tcs for X540, X550 */
1076 if (hw->mac.type == ixgbe_mac_X540 ||
1077 hw->mac.type == ixgbe_mac_X550 ||
1078 hw->mac.type == ixgbe_mac_X550EM_x ||
1079 hw->mac.type == ixgbe_mac_X550EM_a) {
1080 dcb_config->num_tcs.pg_tcs = 4;
1081 dcb_config->num_tcs.pfc_tcs = 4;
1086 * Ensure that all locks are released before first NVM or PHY access
1089 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1094 * Phy lock should not fail in this early stage. If this is the case,
1095 * it is due to an improper exit of the application.
1096 * So force the release of the faulty lock. Release of common lock
1097 * is done automatically by swfw_sync function.
1099 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1100 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1101 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1103 ixgbe_release_swfw_semaphore(hw, mask);
1106 * These ones are more tricky since they are common to all ports; but
1107 * swfw_sync retries last long enough (1s) to be almost sure that if
1108 * lock can not be taken it is due to an improper lock of the
1111 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1112 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1113 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1115 ixgbe_release_swfw_semaphore(hw, mask);
1119 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1120 * It returns 0 on success.
1123 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1125 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1126 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1127 struct ixgbe_hw *hw =
1128 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1129 struct ixgbe_vfta *shadow_vfta =
1130 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1131 struct ixgbe_hwstrip *hwstrip =
1132 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1133 struct ixgbe_dcb_config *dcb_config =
1134 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1135 struct ixgbe_filter_info *filter_info =
1136 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1137 struct ixgbe_bw_conf *bw_conf =
1138 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1143 PMD_INIT_FUNC_TRACE();
1145 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1146 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1147 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1148 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1151 * For secondary processes, we don't initialise any further as primary
1152 * has already done this work. Only check we don't need a different
1153 * RX and TX function.
1155 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1156 struct ixgbe_tx_queue *txq;
1157 /* TX queue function in primary, set by last queue initialized
1158 * Tx queue may not initialized by primary process
1160 if (eth_dev->data->tx_queues) {
1161 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1162 ixgbe_set_tx_function(eth_dev, txq);
1164 /* Use default TX function if we get here */
1165 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1166 "Using default TX function.");
1169 ixgbe_set_rx_function(eth_dev);
1174 rte_eth_copy_pci_info(eth_dev, pci_dev);
1175 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1177 /* Vendor and Device ID need to be set before init of shared code */
1178 hw->device_id = pci_dev->id.device_id;
1179 hw->vendor_id = pci_dev->id.vendor_id;
1180 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1181 hw->allow_unsupported_sfp = 1;
1183 /* Initialize the shared code (base driver) */
1184 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1185 diag = ixgbe_bypass_init_shared_code(hw);
1187 diag = ixgbe_init_shared_code(hw);
1188 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1190 if (diag != IXGBE_SUCCESS) {
1191 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1195 /* pick up the PCI bus settings for reporting later */
1196 ixgbe_get_bus_info(hw);
1198 /* Unlock any pending hardware semaphore */
1199 ixgbe_swfw_lock_reset(hw);
1201 /* Initialize DCB configuration*/
1202 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1203 ixgbe_dcb_init(hw, dcb_config);
1204 /* Get Hardware Flow Control setting */
1205 hw->fc.requested_mode = ixgbe_fc_full;
1206 hw->fc.current_mode = ixgbe_fc_full;
1207 hw->fc.pause_time = IXGBE_FC_PAUSE;
1208 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1209 hw->fc.low_water[i] = IXGBE_FC_LO;
1210 hw->fc.high_water[i] = IXGBE_FC_HI;
1212 hw->fc.send_xon = 1;
1214 /* Make sure we have a good EEPROM before we read from it */
1215 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1216 if (diag != IXGBE_SUCCESS) {
1217 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1221 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1222 diag = ixgbe_bypass_init_hw(hw);
1224 diag = ixgbe_init_hw(hw);
1225 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1228 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1229 * is called too soon after the kernel driver unbinding/binding occurs.
1230 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1231 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1232 * also called. See ixgbe_identify_phy_82599(). The reason for the
1233 * failure is not known, and only occuts when virtualisation features
1234 * are disabled in the bios. A delay of 100ms was found to be enough by
1235 * trial-and-error, and is doubled to be safe.
1237 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1239 diag = ixgbe_init_hw(hw);
1242 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1243 diag = IXGBE_SUCCESS;
1245 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1246 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1247 "LOM. Please be aware there may be issues associated "
1248 "with your hardware.");
1249 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1250 "please contact your Intel or hardware representative "
1251 "who provided you with this hardware.");
1252 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1253 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1255 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1259 /* Reset the hw statistics */
1260 ixgbe_dev_stats_reset(eth_dev);
1262 /* disable interrupt */
1263 ixgbe_disable_intr(hw);
1265 /* reset mappings for queue statistics hw counters*/
1266 ixgbe_reset_qstat_mappings(hw);
1268 /* Allocate memory for storing MAC addresses */
1269 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1270 hw->mac.num_rar_entries, 0);
1271 if (eth_dev->data->mac_addrs == NULL) {
1273 "Failed to allocate %u bytes needed to store "
1275 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1278 /* Copy the permanent MAC address */
1279 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1280 ð_dev->data->mac_addrs[0]);
1282 /* Allocate memory for storing hash filter MAC addresses */
1283 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1284 IXGBE_VMDQ_NUM_UC_MAC, 0);
1285 if (eth_dev->data->hash_mac_addrs == NULL) {
1287 "Failed to allocate %d bytes needed to store MAC addresses",
1288 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1292 /* initialize the vfta */
1293 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1295 /* initialize the hw strip bitmap*/
1296 memset(hwstrip, 0, sizeof(*hwstrip));
1298 /* initialize PF if max_vfs not zero */
1299 ixgbe_pf_host_init(eth_dev);
1301 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1302 /* let hardware know driver is loaded */
1303 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1304 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1305 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1306 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1307 IXGBE_WRITE_FLUSH(hw);
1309 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1310 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1311 (int) hw->mac.type, (int) hw->phy.type,
1312 (int) hw->phy.sfp_type);
1314 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1315 (int) hw->mac.type, (int) hw->phy.type);
1317 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1318 eth_dev->data->port_id, pci_dev->id.vendor_id,
1319 pci_dev->id.device_id);
1321 rte_intr_callback_register(intr_handle,
1322 ixgbe_dev_interrupt_handler, eth_dev);
1324 /* enable uio/vfio intr/eventfd mapping */
1325 rte_intr_enable(intr_handle);
1327 /* enable support intr */
1328 ixgbe_enable_intr(eth_dev);
1330 /* initialize filter info */
1331 memset(filter_info, 0,
1332 sizeof(struct ixgbe_filter_info));
1334 /* initialize 5tuple filter list */
1335 TAILQ_INIT(&filter_info->fivetuple_list);
1337 /* initialize flow director filter list & hash */
1338 ixgbe_fdir_filter_init(eth_dev);
1340 /* initialize l2 tunnel filter list & hash */
1341 ixgbe_l2_tn_filter_init(eth_dev);
1343 TAILQ_INIT(&filter_ntuple_list);
1344 TAILQ_INIT(&filter_ethertype_list);
1345 TAILQ_INIT(&filter_syn_list);
1346 TAILQ_INIT(&filter_fdir_list);
1347 TAILQ_INIT(&filter_l2_tunnel_list);
1348 TAILQ_INIT(&ixgbe_flow_list);
1350 /* initialize bandwidth configuration info */
1351 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1357 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1359 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1360 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1361 struct ixgbe_hw *hw;
1363 PMD_INIT_FUNC_TRACE();
1365 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1368 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1370 if (hw->adapter_stopped == 0)
1371 ixgbe_dev_close(eth_dev);
1373 eth_dev->dev_ops = NULL;
1374 eth_dev->rx_pkt_burst = NULL;
1375 eth_dev->tx_pkt_burst = NULL;
1377 /* Unlock any pending hardware semaphore */
1378 ixgbe_swfw_lock_reset(hw);
1380 /* disable uio intr before callback unregister */
1381 rte_intr_disable(intr_handle);
1382 rte_intr_callback_unregister(intr_handle,
1383 ixgbe_dev_interrupt_handler, eth_dev);
1385 /* uninitialize PF if max_vfs not zero */
1386 ixgbe_pf_host_uninit(eth_dev);
1388 rte_free(eth_dev->data->mac_addrs);
1389 eth_dev->data->mac_addrs = NULL;
1391 rte_free(eth_dev->data->hash_mac_addrs);
1392 eth_dev->data->hash_mac_addrs = NULL;
1394 /* remove all the fdir filters & hash */
1395 ixgbe_fdir_filter_uninit(eth_dev);
1397 /* remove all the L2 tunnel filters & hash */
1398 ixgbe_l2_tn_filter_uninit(eth_dev);
1400 /* Remove all ntuple filters of the device */
1401 ixgbe_ntuple_filter_uninit(eth_dev);
1403 /* clear all the filters list */
1404 ixgbe_filterlist_flush();
1409 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1411 struct ixgbe_filter_info *filter_info =
1412 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1413 struct ixgbe_5tuple_filter *p_5tuple;
1415 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1416 TAILQ_REMOVE(&filter_info->fivetuple_list,
1421 memset(filter_info->fivetuple_mask, 0,
1422 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1427 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1429 struct ixgbe_hw_fdir_info *fdir_info =
1430 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1431 struct ixgbe_fdir_filter *fdir_filter;
1433 if (fdir_info->hash_map)
1434 rte_free(fdir_info->hash_map);
1435 if (fdir_info->hash_handle)
1436 rte_hash_free(fdir_info->hash_handle);
1438 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1439 TAILQ_REMOVE(&fdir_info->fdir_list,
1442 rte_free(fdir_filter);
1448 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1450 struct ixgbe_l2_tn_info *l2_tn_info =
1451 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1452 struct ixgbe_l2_tn_filter *l2_tn_filter;
1454 if (l2_tn_info->hash_map)
1455 rte_free(l2_tn_info->hash_map);
1456 if (l2_tn_info->hash_handle)
1457 rte_hash_free(l2_tn_info->hash_handle);
1459 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1460 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1463 rte_free(l2_tn_filter);
1469 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1471 struct ixgbe_hw_fdir_info *fdir_info =
1472 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1473 char fdir_hash_name[RTE_HASH_NAMESIZE];
1474 struct rte_hash_parameters fdir_hash_params = {
1475 .name = fdir_hash_name,
1476 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1477 .key_len = sizeof(union ixgbe_atr_input),
1478 .hash_func = rte_hash_crc,
1479 .hash_func_init_val = 0,
1480 .socket_id = rte_socket_id(),
1483 TAILQ_INIT(&fdir_info->fdir_list);
1484 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1485 "fdir_%s", eth_dev->device->name);
1486 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1487 if (!fdir_info->hash_handle) {
1488 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1491 fdir_info->hash_map = rte_zmalloc("ixgbe",
1492 sizeof(struct ixgbe_fdir_filter *) *
1493 IXGBE_MAX_FDIR_FILTER_NUM,
1495 if (!fdir_info->hash_map) {
1497 "Failed to allocate memory for fdir hash map!");
1500 fdir_info->mask_added = FALSE;
1505 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1507 struct ixgbe_l2_tn_info *l2_tn_info =
1508 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1509 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1510 struct rte_hash_parameters l2_tn_hash_params = {
1511 .name = l2_tn_hash_name,
1512 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1513 .key_len = sizeof(struct ixgbe_l2_tn_key),
1514 .hash_func = rte_hash_crc,
1515 .hash_func_init_val = 0,
1516 .socket_id = rte_socket_id(),
1519 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1520 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1521 "l2_tn_%s", eth_dev->device->name);
1522 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1523 if (!l2_tn_info->hash_handle) {
1524 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1527 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1528 sizeof(struct ixgbe_l2_tn_filter *) *
1529 IXGBE_MAX_L2_TN_FILTER_NUM,
1531 if (!l2_tn_info->hash_map) {
1533 "Failed to allocate memory for L2 TN hash map!");
1536 l2_tn_info->e_tag_en = FALSE;
1537 l2_tn_info->e_tag_fwd_en = FALSE;
1538 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1543 * Negotiate mailbox API version with the PF.
1544 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1545 * Then we try to negotiate starting with the most recent one.
1546 * If all negotiation attempts fail, then we will proceed with
1547 * the default one (ixgbe_mbox_api_10).
1550 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1554 /* start with highest supported, proceed down */
1555 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1562 i != RTE_DIM(sup_ver) &&
1563 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1569 generate_random_mac_addr(struct ether_addr *mac_addr)
1573 /* Set Organizationally Unique Identifier (OUI) prefix. */
1574 mac_addr->addr_bytes[0] = 0x00;
1575 mac_addr->addr_bytes[1] = 0x09;
1576 mac_addr->addr_bytes[2] = 0xC0;
1577 /* Force indication of locally assigned MAC address. */
1578 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1579 /* Generate the last 3 bytes of the MAC address with a random number. */
1580 random = rte_rand();
1581 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1585 * Virtual Function device init
1588 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1592 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1593 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1594 struct ixgbe_hw *hw =
1595 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1596 struct ixgbe_vfta *shadow_vfta =
1597 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1598 struct ixgbe_hwstrip *hwstrip =
1599 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1600 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1602 PMD_INIT_FUNC_TRACE();
1604 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1605 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1606 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1608 /* for secondary processes, we don't initialise any further as primary
1609 * has already done this work. Only check we don't need a different
1612 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1613 struct ixgbe_tx_queue *txq;
1614 /* TX queue function in primary, set by last queue initialized
1615 * Tx queue may not initialized by primary process
1617 if (eth_dev->data->tx_queues) {
1618 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1619 ixgbe_set_tx_function(eth_dev, txq);
1621 /* Use default TX function if we get here */
1622 PMD_INIT_LOG(NOTICE,
1623 "No TX queues configured yet. Using default TX function.");
1626 ixgbe_set_rx_function(eth_dev);
1631 rte_eth_copy_pci_info(eth_dev, pci_dev);
1632 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1634 hw->device_id = pci_dev->id.device_id;
1635 hw->vendor_id = pci_dev->id.vendor_id;
1636 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1638 /* initialize the vfta */
1639 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1641 /* initialize the hw strip bitmap*/
1642 memset(hwstrip, 0, sizeof(*hwstrip));
1644 /* Initialize the shared code (base driver) */
1645 diag = ixgbe_init_shared_code(hw);
1646 if (diag != IXGBE_SUCCESS) {
1647 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1651 /* init_mailbox_params */
1652 hw->mbx.ops.init_params(hw);
1654 /* Reset the hw statistics */
1655 ixgbevf_dev_stats_reset(eth_dev);
1657 /* Disable the interrupts for VF */
1658 ixgbevf_intr_disable(hw);
1660 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1661 diag = hw->mac.ops.reset_hw(hw);
1664 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1665 * the underlying PF driver has not assigned a MAC address to the VF.
1666 * In this case, assign a random MAC address.
1668 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1669 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1673 /* negotiate mailbox API version to use with the PF. */
1674 ixgbevf_negotiate_api(hw);
1676 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1677 ixgbevf_get_queues(hw, &tcs, &tc);
1679 /* Allocate memory for storing MAC addresses */
1680 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1681 hw->mac.num_rar_entries, 0);
1682 if (eth_dev->data->mac_addrs == NULL) {
1684 "Failed to allocate %u bytes needed to store "
1686 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1690 /* Generate a random MAC address, if none was assigned by PF. */
1691 if (is_zero_ether_addr(perm_addr)) {
1692 generate_random_mac_addr(perm_addr);
1693 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1695 rte_free(eth_dev->data->mac_addrs);
1696 eth_dev->data->mac_addrs = NULL;
1699 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1700 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1701 "%02x:%02x:%02x:%02x:%02x:%02x",
1702 perm_addr->addr_bytes[0],
1703 perm_addr->addr_bytes[1],
1704 perm_addr->addr_bytes[2],
1705 perm_addr->addr_bytes[3],
1706 perm_addr->addr_bytes[4],
1707 perm_addr->addr_bytes[5]);
1710 /* Copy the permanent MAC address */
1711 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1713 /* reset the hardware with the new settings */
1714 diag = hw->mac.ops.start_hw(hw);
1720 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1724 rte_intr_callback_register(intr_handle,
1725 ixgbevf_dev_interrupt_handler, eth_dev);
1726 rte_intr_enable(intr_handle);
1727 ixgbevf_intr_enable(hw);
1729 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1730 eth_dev->data->port_id, pci_dev->id.vendor_id,
1731 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1736 /* Virtual Function device uninit */
1739 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1741 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1742 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1743 struct ixgbe_hw *hw;
1745 PMD_INIT_FUNC_TRACE();
1747 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1750 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1752 if (hw->adapter_stopped == 0)
1753 ixgbevf_dev_close(eth_dev);
1755 eth_dev->dev_ops = NULL;
1756 eth_dev->rx_pkt_burst = NULL;
1757 eth_dev->tx_pkt_burst = NULL;
1759 /* Disable the interrupts for VF */
1760 ixgbevf_intr_disable(hw);
1762 rte_free(eth_dev->data->mac_addrs);
1763 eth_dev->data->mac_addrs = NULL;
1765 rte_intr_disable(intr_handle);
1766 rte_intr_callback_unregister(intr_handle,
1767 ixgbevf_dev_interrupt_handler, eth_dev);
1772 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1773 struct rte_pci_device *pci_dev)
1775 return rte_eth_dev_pci_generic_probe(pci_dev,
1776 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1779 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1781 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1784 static struct rte_pci_driver rte_ixgbe_pmd = {
1785 .id_table = pci_id_ixgbe_map,
1786 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1787 .probe = eth_ixgbe_pci_probe,
1788 .remove = eth_ixgbe_pci_remove,
1791 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1792 struct rte_pci_device *pci_dev)
1794 return rte_eth_dev_pci_generic_probe(pci_dev,
1795 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1798 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1800 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1804 * virtual function driver struct
1806 static struct rte_pci_driver rte_ixgbevf_pmd = {
1807 .id_table = pci_id_ixgbevf_map,
1808 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1809 .probe = eth_ixgbevf_pci_probe,
1810 .remove = eth_ixgbevf_pci_remove,
1814 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1816 struct ixgbe_hw *hw =
1817 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818 struct ixgbe_vfta *shadow_vfta =
1819 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1824 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1825 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1826 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1831 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1833 /* update local VFTA copy */
1834 shadow_vfta->vfta[vid_idx] = vfta;
1840 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1843 ixgbe_vlan_hw_strip_enable(dev, queue);
1845 ixgbe_vlan_hw_strip_disable(dev, queue);
1849 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1850 enum rte_vlan_type vlan_type,
1853 struct ixgbe_hw *hw =
1854 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1860 qinq &= IXGBE_DMATXCTL_GDV;
1862 switch (vlan_type) {
1863 case ETH_VLAN_TYPE_INNER:
1865 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1866 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1867 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1868 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1869 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1870 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1871 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1874 PMD_DRV_LOG(ERR, "Inner type is not supported"
1878 case ETH_VLAN_TYPE_OUTER:
1880 /* Only the high 16-bits is valid */
1881 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1882 IXGBE_EXVET_VET_EXT_SHIFT);
1884 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1885 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1886 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1887 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1888 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1889 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1890 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1896 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1904 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1906 struct ixgbe_hw *hw =
1907 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910 PMD_INIT_FUNC_TRACE();
1912 /* Filter Table Disable */
1913 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1914 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1916 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1920 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1922 struct ixgbe_hw *hw =
1923 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924 struct ixgbe_vfta *shadow_vfta =
1925 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1929 PMD_INIT_FUNC_TRACE();
1931 /* Filter Table Enable */
1932 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1933 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1934 vlnctrl |= IXGBE_VLNCTRL_VFE;
1936 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1938 /* write whatever is in local vfta copy */
1939 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1940 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1944 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1946 struct ixgbe_hwstrip *hwstrip =
1947 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1948 struct ixgbe_rx_queue *rxq;
1950 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1954 IXGBE_SET_HWSTRIP(hwstrip, queue);
1956 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1958 if (queue >= dev->data->nb_rx_queues)
1961 rxq = dev->data->rx_queues[queue];
1964 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1966 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1970 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1972 struct ixgbe_hw *hw =
1973 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1976 PMD_INIT_FUNC_TRACE();
1978 if (hw->mac.type == ixgbe_mac_82598EB) {
1979 /* No queue level support */
1980 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1984 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1985 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1986 ctrl &= ~IXGBE_RXDCTL_VME;
1987 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1989 /* record those setting for HW strip per queue */
1990 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1994 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1996 struct ixgbe_hw *hw =
1997 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2000 PMD_INIT_FUNC_TRACE();
2002 if (hw->mac.type == ixgbe_mac_82598EB) {
2003 /* No queue level supported */
2004 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2008 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2009 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2010 ctrl |= IXGBE_RXDCTL_VME;
2011 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2013 /* record those setting for HW strip per queue */
2014 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2018 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2020 struct ixgbe_hw *hw =
2021 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024 struct ixgbe_rx_queue *rxq;
2026 PMD_INIT_FUNC_TRACE();
2028 if (hw->mac.type == ixgbe_mac_82598EB) {
2029 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2030 ctrl &= ~IXGBE_VLNCTRL_VME;
2031 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2033 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2034 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2035 rxq = dev->data->rx_queues[i];
2036 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2037 ctrl &= ~IXGBE_RXDCTL_VME;
2038 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2040 /* record those setting for HW strip per queue */
2041 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2047 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2049 struct ixgbe_hw *hw =
2050 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 struct ixgbe_rx_queue *rxq;
2055 PMD_INIT_FUNC_TRACE();
2057 if (hw->mac.type == ixgbe_mac_82598EB) {
2058 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2059 ctrl |= IXGBE_VLNCTRL_VME;
2060 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2062 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2063 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2064 rxq = dev->data->rx_queues[i];
2065 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2066 ctrl |= IXGBE_RXDCTL_VME;
2067 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2069 /* record those setting for HW strip per queue */
2070 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2076 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2078 struct ixgbe_hw *hw =
2079 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082 PMD_INIT_FUNC_TRACE();
2084 /* DMATXCTRL: Geric Double VLAN Disable */
2085 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2086 ctrl &= ~IXGBE_DMATXCTL_GDV;
2087 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2089 /* CTRL_EXT: Global Double VLAN Disable */
2090 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2091 ctrl &= ~IXGBE_EXTENDED_VLAN;
2092 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2097 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2099 struct ixgbe_hw *hw =
2100 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103 PMD_INIT_FUNC_TRACE();
2105 /* DMATXCTRL: Geric Double VLAN Enable */
2106 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2107 ctrl |= IXGBE_DMATXCTL_GDV;
2108 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2110 /* CTRL_EXT: Global Double VLAN Enable */
2111 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2112 ctrl |= IXGBE_EXTENDED_VLAN;
2113 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2115 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2116 if (hw->mac.type == ixgbe_mac_X550 ||
2117 hw->mac.type == ixgbe_mac_X550EM_x ||
2118 hw->mac.type == ixgbe_mac_X550EM_a) {
2119 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2120 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2121 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2125 * VET EXT field in the EXVET register = 0x8100 by default
2126 * So no need to change. Same to VT field of DMATXCTL register
2131 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2133 if (mask & ETH_VLAN_STRIP_MASK) {
2134 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2135 ixgbe_vlan_hw_strip_enable_all(dev);
2137 ixgbe_vlan_hw_strip_disable_all(dev);
2140 if (mask & ETH_VLAN_FILTER_MASK) {
2141 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2142 ixgbe_vlan_hw_filter_enable(dev);
2144 ixgbe_vlan_hw_filter_disable(dev);
2147 if (mask & ETH_VLAN_EXTEND_MASK) {
2148 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2149 ixgbe_vlan_hw_extend_enable(dev);
2151 ixgbe_vlan_hw_extend_disable(dev);
2156 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2158 struct ixgbe_hw *hw =
2159 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2160 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2161 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2163 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2164 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2168 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2170 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2175 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2178 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2184 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2185 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2191 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2193 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2194 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2196 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2198 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2199 /* check multi-queue mode */
2200 switch (dev_conf->rxmode.mq_mode) {
2201 case ETH_MQ_RX_VMDQ_DCB:
2202 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2204 case ETH_MQ_RX_VMDQ_DCB_RSS:
2205 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2206 PMD_INIT_LOG(ERR, "SRIOV active,"
2207 " unsupported mq_mode rx %d.",
2208 dev_conf->rxmode.mq_mode);
2211 case ETH_MQ_RX_VMDQ_RSS:
2212 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2213 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2214 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2215 PMD_INIT_LOG(ERR, "SRIOV is active,"
2216 " invalid queue number"
2217 " for VMDQ RSS, allowed"
2218 " value are 1, 2 or 4.");
2222 case ETH_MQ_RX_VMDQ_ONLY:
2223 case ETH_MQ_RX_NONE:
2224 /* if nothing mq mode configure, use default scheme */
2225 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2226 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2227 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2229 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2230 /* SRIOV only works in VMDq enable mode */
2231 PMD_INIT_LOG(ERR, "SRIOV is active,"
2232 " wrong mq_mode rx %d.",
2233 dev_conf->rxmode.mq_mode);
2237 switch (dev_conf->txmode.mq_mode) {
2238 case ETH_MQ_TX_VMDQ_DCB:
2239 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2240 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2242 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2243 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2247 /* check valid queue number */
2248 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2249 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2250 PMD_INIT_LOG(ERR, "SRIOV is active,"
2251 " nb_rx_q=%d nb_tx_q=%d queue number"
2252 " must be less than or equal to %d.",
2254 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2258 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2259 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2263 /* check configuration for vmdb+dcb mode */
2264 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2265 const struct rte_eth_vmdq_dcb_conf *conf;
2267 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2268 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2269 IXGBE_VMDQ_DCB_NB_QUEUES);
2272 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2273 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2274 conf->nb_queue_pools == ETH_32_POOLS)) {
2275 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2276 " nb_queue_pools must be %d or %d.",
2277 ETH_16_POOLS, ETH_32_POOLS);
2281 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2282 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2284 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2285 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2286 IXGBE_VMDQ_DCB_NB_QUEUES);
2289 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2290 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2291 conf->nb_queue_pools == ETH_32_POOLS)) {
2292 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2293 " nb_queue_pools != %d and"
2294 " nb_queue_pools != %d.",
2295 ETH_16_POOLS, ETH_32_POOLS);
2300 /* For DCB mode check our configuration before we go further */
2301 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2302 const struct rte_eth_dcb_rx_conf *conf;
2304 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2305 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2306 IXGBE_DCB_NB_QUEUES);
2309 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2310 if (!(conf->nb_tcs == ETH_4_TCS ||
2311 conf->nb_tcs == ETH_8_TCS)) {
2312 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2313 " and nb_tcs != %d.",
2314 ETH_4_TCS, ETH_8_TCS);
2319 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2320 const struct rte_eth_dcb_tx_conf *conf;
2322 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2323 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2324 IXGBE_DCB_NB_QUEUES);
2327 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2328 if (!(conf->nb_tcs == ETH_4_TCS ||
2329 conf->nb_tcs == ETH_8_TCS)) {
2330 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2331 " and nb_tcs != %d.",
2332 ETH_4_TCS, ETH_8_TCS);
2338 * When DCB/VT is off, maximum number of queues changes,
2339 * except for 82598EB, which remains constant.
2341 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2342 hw->mac.type != ixgbe_mac_82598EB) {
2343 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2345 "Neither VT nor DCB are enabled, "
2347 IXGBE_NONE_MODE_TX_NB_QUEUES);
2356 ixgbe_dev_configure(struct rte_eth_dev *dev)
2358 struct ixgbe_interrupt *intr =
2359 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2360 struct ixgbe_adapter *adapter =
2361 (struct ixgbe_adapter *)dev->data->dev_private;
2364 PMD_INIT_FUNC_TRACE();
2365 /* multipe queue mode checking */
2366 ret = ixgbe_check_mq_mode(dev);
2368 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2373 /* set flag to update link status after init */
2374 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2377 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2378 * allocation or vector Rx preconditions we will reset it.
2380 adapter->rx_bulk_alloc_allowed = true;
2381 adapter->rx_vec_allowed = true;
2387 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2389 struct ixgbe_hw *hw =
2390 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391 struct ixgbe_interrupt *intr =
2392 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2395 /* only set up it on X550EM_X */
2396 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2397 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2398 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2399 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2400 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2401 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2406 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2407 uint16_t tx_rate, uint64_t q_msk)
2409 struct ixgbe_hw *hw;
2410 struct ixgbe_vf_info *vfinfo;
2411 struct rte_eth_link link;
2412 uint8_t nb_q_per_pool;
2413 uint32_t queue_stride;
2414 uint32_t queue_idx, idx = 0, vf_idx;
2416 uint16_t total_rate = 0;
2417 struct rte_pci_device *pci_dev;
2419 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2420 rte_eth_link_get_nowait(dev->data->port_id, &link);
2422 if (vf >= pci_dev->max_vfs)
2425 if (tx_rate > link.link_speed)
2431 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2432 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2433 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2434 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2435 queue_idx = vf * queue_stride;
2436 queue_end = queue_idx + nb_q_per_pool - 1;
2437 if (queue_end >= hw->mac.max_tx_queues)
2441 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2444 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2446 total_rate += vfinfo[vf_idx].tx_rate[idx];
2452 /* Store tx_rate for this vf. */
2453 for (idx = 0; idx < nb_q_per_pool; idx++) {
2454 if (((uint64_t)0x1 << idx) & q_msk) {
2455 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2456 vfinfo[vf].tx_rate[idx] = tx_rate;
2457 total_rate += tx_rate;
2461 if (total_rate > dev->data->dev_link.link_speed) {
2462 /* Reset stored TX rate of the VF if it causes exceed
2465 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2469 /* Set RTTBCNRC of each queue/pool for vf X */
2470 for (; queue_idx <= queue_end; queue_idx++) {
2472 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2480 * Configure device link speed and setup link.
2481 * It returns 0 on success.
2484 ixgbe_dev_start(struct rte_eth_dev *dev)
2486 struct ixgbe_hw *hw =
2487 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2488 struct ixgbe_vf_info *vfinfo =
2489 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2490 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2491 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2492 uint32_t intr_vector = 0;
2493 int err, link_up = 0, negotiate = 0;
2498 uint32_t *link_speeds;
2500 PMD_INIT_FUNC_TRACE();
2502 /* IXGBE devices don't support:
2503 * - half duplex (checked afterwards for valid speeds)
2504 * - fixed speed: TODO implement
2506 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2507 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2508 dev->data->port_id);
2512 /* disable uio/vfio intr/eventfd mapping */
2513 rte_intr_disable(intr_handle);
2516 hw->adapter_stopped = 0;
2517 ixgbe_stop_adapter(hw);
2519 /* reinitialize adapter
2520 * this calls reset and start
2522 status = ixgbe_pf_reset_hw(hw);
2525 hw->mac.ops.start_hw(hw);
2526 hw->mac.get_link_status = true;
2528 /* configure PF module if SRIOV enabled */
2529 ixgbe_pf_host_configure(dev);
2531 ixgbe_dev_phy_intr_setup(dev);
2533 /* check and configure queue intr-vector mapping */
2534 if ((rte_intr_cap_multiple(intr_handle) ||
2535 !RTE_ETH_DEV_SRIOV(dev).active) &&
2536 dev->data->dev_conf.intr_conf.rxq != 0) {
2537 intr_vector = dev->data->nb_rx_queues;
2538 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2539 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2540 IXGBE_MAX_INTR_QUEUE_NUM);
2543 if (rte_intr_efd_enable(intr_handle, intr_vector))
2547 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2548 intr_handle->intr_vec =
2549 rte_zmalloc("intr_vec",
2550 dev->data->nb_rx_queues * sizeof(int), 0);
2551 if (intr_handle->intr_vec == NULL) {
2552 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2553 " intr_vec", dev->data->nb_rx_queues);
2558 /* confiugre msix for sleep until rx interrupt */
2559 ixgbe_configure_msix(dev);
2561 /* initialize transmission unit */
2562 ixgbe_dev_tx_init(dev);
2564 /* This can fail when allocating mbufs for descriptor rings */
2565 err = ixgbe_dev_rx_init(dev);
2567 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2571 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2572 ETH_VLAN_EXTEND_MASK;
2573 ixgbe_vlan_offload_set(dev, mask);
2575 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2576 /* Enable vlan filtering for VMDq */
2577 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2580 /* Configure DCB hw */
2581 ixgbe_configure_dcb(dev);
2583 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2584 err = ixgbe_fdir_configure(dev);
2589 /* Restore vf rate limit */
2590 if (vfinfo != NULL) {
2591 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2592 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2593 if (vfinfo[vf].tx_rate[idx] != 0)
2594 ixgbe_set_vf_rate_limit(
2596 vfinfo[vf].tx_rate[idx],
2600 ixgbe_restore_statistics_mapping(dev);
2602 err = ixgbe_dev_rxtx_start(dev);
2604 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2608 /* Skip link setup if loopback mode is enabled for 82599. */
2609 if (hw->mac.type == ixgbe_mac_82599EB &&
2610 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2611 goto skip_link_setup;
2613 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2614 err = hw->mac.ops.setup_sfp(hw);
2619 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2620 /* Turn on the copper */
2621 ixgbe_set_phy_power(hw, true);
2623 /* Turn on the laser */
2624 ixgbe_enable_tx_laser(hw);
2627 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2630 dev->data->dev_link.link_status = link_up;
2632 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2636 link_speeds = &dev->data->dev_conf.link_speeds;
2637 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2638 ETH_LINK_SPEED_10G)) {
2639 PMD_INIT_LOG(ERR, "Invalid link setting");
2644 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2645 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2646 IXGBE_LINK_SPEED_82599_AUTONEG :
2647 IXGBE_LINK_SPEED_82598_AUTONEG;
2649 if (*link_speeds & ETH_LINK_SPEED_10G)
2650 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2651 if (*link_speeds & ETH_LINK_SPEED_1G)
2652 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2653 if (*link_speeds & ETH_LINK_SPEED_100M)
2654 speed |= IXGBE_LINK_SPEED_100_FULL;
2657 err = ixgbe_setup_link(hw, speed, link_up);
2663 if (rte_intr_allow_others(intr_handle)) {
2664 /* check if lsc interrupt is enabled */
2665 if (dev->data->dev_conf.intr_conf.lsc != 0)
2666 ixgbe_dev_lsc_interrupt_setup(dev);
2667 ixgbe_dev_macsec_interrupt_setup(dev);
2669 rte_intr_callback_unregister(intr_handle,
2670 ixgbe_dev_interrupt_handler, dev);
2671 if (dev->data->dev_conf.intr_conf.lsc != 0)
2672 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2673 " no intr multiplex");
2676 /* check if rxq interrupt is enabled */
2677 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2678 rte_intr_dp_is_en(intr_handle))
2679 ixgbe_dev_rxq_interrupt_setup(dev);
2681 /* enable uio/vfio intr/eventfd mapping */
2682 rte_intr_enable(intr_handle);
2684 /* resume enabled intr since hw reset */
2685 ixgbe_enable_intr(dev);
2686 ixgbe_l2_tunnel_conf(dev);
2687 ixgbe_filter_restore(dev);
2692 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2693 ixgbe_dev_clear_queues(dev);
2698 * Stop device: disable rx and tx functions to allow for reconfiguring.
2701 ixgbe_dev_stop(struct rte_eth_dev *dev)
2703 struct rte_eth_link link;
2704 struct ixgbe_hw *hw =
2705 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2706 struct ixgbe_vf_info *vfinfo =
2707 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2708 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2709 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2712 PMD_INIT_FUNC_TRACE();
2714 /* disable interrupts */
2715 ixgbe_disable_intr(hw);
2718 ixgbe_pf_reset_hw(hw);
2719 hw->adapter_stopped = 0;
2722 ixgbe_stop_adapter(hw);
2724 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2725 vfinfo[vf].clear_to_send = false;
2727 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2728 /* Turn off the copper */
2729 ixgbe_set_phy_power(hw, false);
2731 /* Turn off the laser */
2732 ixgbe_disable_tx_laser(hw);
2735 ixgbe_dev_clear_queues(dev);
2737 /* Clear stored conf */
2738 dev->data->scattered_rx = 0;
2741 /* Clear recorded link status */
2742 memset(&link, 0, sizeof(link));
2743 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2745 if (!rte_intr_allow_others(intr_handle))
2746 /* resume to the default handler */
2747 rte_intr_callback_register(intr_handle,
2748 ixgbe_dev_interrupt_handler,
2751 /* Clean datapath event and queue/vec mapping */
2752 rte_intr_efd_disable(intr_handle);
2753 if (intr_handle->intr_vec != NULL) {
2754 rte_free(intr_handle->intr_vec);
2755 intr_handle->intr_vec = NULL;
2760 * Set device link up: enable tx.
2763 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2765 struct ixgbe_hw *hw =
2766 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2767 if (hw->mac.type == ixgbe_mac_82599EB) {
2768 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2769 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2770 /* Not suported in bypass mode */
2771 PMD_INIT_LOG(ERR, "Set link up is not supported "
2772 "by device id 0x%x", hw->device_id);
2778 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2779 /* Turn on the copper */
2780 ixgbe_set_phy_power(hw, true);
2782 /* Turn on the laser */
2783 ixgbe_enable_tx_laser(hw);
2790 * Set device link down: disable tx.
2793 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2795 struct ixgbe_hw *hw =
2796 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2797 if (hw->mac.type == ixgbe_mac_82599EB) {
2798 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2799 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2800 /* Not suported in bypass mode */
2801 PMD_INIT_LOG(ERR, "Set link down is not supported "
2802 "by device id 0x%x", hw->device_id);
2808 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2809 /* Turn off the copper */
2810 ixgbe_set_phy_power(hw, false);
2812 /* Turn off the laser */
2813 ixgbe_disable_tx_laser(hw);
2820 * Reest and stop device.
2823 ixgbe_dev_close(struct rte_eth_dev *dev)
2825 struct ixgbe_hw *hw =
2826 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2828 PMD_INIT_FUNC_TRACE();
2830 ixgbe_pf_reset_hw(hw);
2832 ixgbe_dev_stop(dev);
2833 hw->adapter_stopped = 1;
2835 ixgbe_dev_free_queues(dev);
2837 ixgbe_disable_pcie_master(hw);
2839 /* reprogram the RAR[0] in case user changed it. */
2840 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2844 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2845 struct ixgbe_hw_stats *hw_stats,
2846 struct ixgbe_macsec_stats *macsec_stats,
2847 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2848 uint64_t *total_qprc, uint64_t *total_qprdc)
2850 uint32_t bprc, lxon, lxoff, total;
2851 uint32_t delta_gprc = 0;
2853 /* Workaround for RX byte count not including CRC bytes when CRC
2854 * strip is enabled. CRC bytes are removed from counters when crc_strip
2857 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2858 IXGBE_HLREG0_RXCRCSTRP);
2860 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2861 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2862 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2863 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2865 for (i = 0; i < 8; i++) {
2866 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2868 /* global total per queue */
2869 hw_stats->mpc[i] += mp;
2870 /* Running comprehensive total for stats display */
2871 *total_missed_rx += hw_stats->mpc[i];
2872 if (hw->mac.type == ixgbe_mac_82598EB) {
2873 hw_stats->rnbc[i] +=
2874 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2875 hw_stats->pxonrxc[i] +=
2876 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2877 hw_stats->pxoffrxc[i] +=
2878 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2880 hw_stats->pxonrxc[i] +=
2881 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2882 hw_stats->pxoffrxc[i] +=
2883 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2884 hw_stats->pxon2offc[i] +=
2885 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2887 hw_stats->pxontxc[i] +=
2888 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2889 hw_stats->pxofftxc[i] +=
2890 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2892 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2893 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2894 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2895 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2897 delta_gprc += delta_qprc;
2899 hw_stats->qprc[i] += delta_qprc;
2900 hw_stats->qptc[i] += delta_qptc;
2902 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2903 hw_stats->qbrc[i] +=
2904 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2906 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2908 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2909 hw_stats->qbtc[i] +=
2910 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2912 hw_stats->qprdc[i] += delta_qprdc;
2913 *total_qprdc += hw_stats->qprdc[i];
2915 *total_qprc += hw_stats->qprc[i];
2916 *total_qbrc += hw_stats->qbrc[i];
2918 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2919 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2920 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2923 * An errata states that gprc actually counts good + missed packets:
2924 * Workaround to set gprc to summated queue packet receives
2926 hw_stats->gprc = *total_qprc;
2928 if (hw->mac.type != ixgbe_mac_82598EB) {
2929 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2930 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2931 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2932 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2933 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2934 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2935 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2936 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2938 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2939 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2940 /* 82598 only has a counter in the high register */
2941 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2942 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2943 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2945 uint64_t old_tpr = hw_stats->tpr;
2947 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2948 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2951 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2953 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2954 hw_stats->gptc += delta_gptc;
2955 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2956 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2959 * Workaround: mprc hardware is incorrectly counting
2960 * broadcasts, so for now we subtract those.
2962 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2963 hw_stats->bprc += bprc;
2964 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2965 if (hw->mac.type == ixgbe_mac_82598EB)
2966 hw_stats->mprc -= bprc;
2968 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2969 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2970 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2971 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2972 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2973 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2975 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2976 hw_stats->lxontxc += lxon;
2977 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2978 hw_stats->lxofftxc += lxoff;
2979 total = lxon + lxoff;
2981 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2982 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2983 hw_stats->gptc -= total;
2984 hw_stats->mptc -= total;
2985 hw_stats->ptc64 -= total;
2986 hw_stats->gotc -= total * ETHER_MIN_LEN;
2988 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2989 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2990 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2991 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2992 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2993 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2994 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2995 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2996 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2997 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2998 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2999 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3000 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3001 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3002 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3003 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3004 /* Only read FCOE on 82599 */
3005 if (hw->mac.type != ixgbe_mac_82598EB) {
3006 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3007 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3008 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3009 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3010 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3013 /* Flow Director Stats registers */
3014 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3015 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3017 /* MACsec Stats registers */
3018 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3019 macsec_stats->out_pkts_encrypted +=
3020 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3021 macsec_stats->out_pkts_protected +=
3022 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3023 macsec_stats->out_octets_encrypted +=
3024 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3025 macsec_stats->out_octets_protected +=
3026 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3027 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3028 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3029 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3030 macsec_stats->in_pkts_unknownsci +=
3031 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3032 macsec_stats->in_octets_decrypted +=
3033 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3034 macsec_stats->in_octets_validated +=
3035 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3036 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3037 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3038 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3039 for (i = 0; i < 2; i++) {
3040 macsec_stats->in_pkts_ok +=
3041 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3042 macsec_stats->in_pkts_invalid +=
3043 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3044 macsec_stats->in_pkts_notvalid +=
3045 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3047 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3048 macsec_stats->in_pkts_notusingsa +=
3049 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3053 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3056 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3058 struct ixgbe_hw *hw =
3059 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3060 struct ixgbe_hw_stats *hw_stats =
3061 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3062 struct ixgbe_macsec_stats *macsec_stats =
3063 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3064 dev->data->dev_private);
3065 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3068 total_missed_rx = 0;
3073 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3074 &total_qbrc, &total_qprc, &total_qprdc);
3079 /* Fill out the rte_eth_stats statistics structure */
3080 stats->ipackets = total_qprc;
3081 stats->ibytes = total_qbrc;
3082 stats->opackets = hw_stats->gptc;
3083 stats->obytes = hw_stats->gotc;
3085 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3086 stats->q_ipackets[i] = hw_stats->qprc[i];
3087 stats->q_opackets[i] = hw_stats->qptc[i];
3088 stats->q_ibytes[i] = hw_stats->qbrc[i];
3089 stats->q_obytes[i] = hw_stats->qbtc[i];
3090 stats->q_errors[i] = hw_stats->qprdc[i];
3094 stats->imissed = total_missed_rx;
3095 stats->ierrors = hw_stats->crcerrs +
3111 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3113 struct ixgbe_hw_stats *stats =
3114 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3116 /* HW registers are cleared on read */
3117 ixgbe_dev_stats_get(dev, NULL);
3119 /* Reset software totals */
3120 memset(stats, 0, sizeof(*stats));
3123 /* This function calculates the number of xstats based on the current config */
3125 ixgbe_xstats_calc_num(void) {
3126 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3127 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3128 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3131 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3132 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3134 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3135 unsigned stat, i, count;
3137 if (xstats_names != NULL) {
3140 /* Note: limit >= cnt_stats checked upstream
3141 * in rte_eth_xstats_names()
3144 /* Extended stats from ixgbe_hw_stats */
3145 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3146 snprintf(xstats_names[count].name,
3147 sizeof(xstats_names[count].name),
3149 rte_ixgbe_stats_strings[i].name);
3154 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3155 snprintf(xstats_names[count].name,
3156 sizeof(xstats_names[count].name),
3158 rte_ixgbe_macsec_strings[i].name);
3162 /* RX Priority Stats */
3163 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3164 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3165 snprintf(xstats_names[count].name,
3166 sizeof(xstats_names[count].name),
3167 "rx_priority%u_%s", i,
3168 rte_ixgbe_rxq_strings[stat].name);
3173 /* TX Priority Stats */
3174 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3175 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3176 snprintf(xstats_names[count].name,
3177 sizeof(xstats_names[count].name),
3178 "tx_priority%u_%s", i,
3179 rte_ixgbe_txq_strings[stat].name);
3187 static int ixgbe_dev_xstats_get_names_by_id(
3188 struct rte_eth_dev *dev,
3189 struct rte_eth_xstat_name *xstats_names,
3190 const uint64_t *ids,
3194 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3195 unsigned int stat, i, count;
3197 if (xstats_names != NULL) {
3200 /* Note: limit >= cnt_stats checked upstream
3201 * in rte_eth_xstats_names()
3204 /* Extended stats from ixgbe_hw_stats */
3205 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3206 snprintf(xstats_names[count].name,
3207 sizeof(xstats_names[count].name),
3209 rte_ixgbe_stats_strings[i].name);
3214 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3215 snprintf(xstats_names[count].name,
3216 sizeof(xstats_names[count].name),
3218 rte_ixgbe_macsec_strings[i].name);
3222 /* RX Priority Stats */
3223 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3224 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3225 snprintf(xstats_names[count].name,
3226 sizeof(xstats_names[count].name),
3227 "rx_priority%u_%s", i,
3228 rte_ixgbe_rxq_strings[stat].name);
3233 /* TX Priority Stats */
3234 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3235 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3236 snprintf(xstats_names[count].name,
3237 sizeof(xstats_names[count].name),
3238 "tx_priority%u_%s", i,
3239 rte_ixgbe_txq_strings[stat].name);
3248 uint16_t size = ixgbe_xstats_calc_num();
3249 struct rte_eth_xstat_name xstats_names_copy[size];
3251 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3254 for (i = 0; i < limit; i++) {
3255 if (ids[i] >= size) {
3256 PMD_INIT_LOG(ERR, "id value isn't valid");
3259 strcpy(xstats_names[i].name,
3260 xstats_names_copy[ids[i]].name);
3265 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3266 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3270 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3273 if (xstats_names != NULL)
3274 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3275 snprintf(xstats_names[i].name,
3276 sizeof(xstats_names[i].name),
3277 "%s", rte_ixgbevf_stats_strings[i].name);
3278 return IXGBEVF_NB_XSTATS;
3282 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3285 struct ixgbe_hw *hw =
3286 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3287 struct ixgbe_hw_stats *hw_stats =
3288 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3289 struct ixgbe_macsec_stats *macsec_stats =
3290 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3291 dev->data->dev_private);
3292 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3293 unsigned i, stat, count = 0;
3295 count = ixgbe_xstats_calc_num();
3300 total_missed_rx = 0;
3305 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3306 &total_qbrc, &total_qprc, &total_qprdc);
3308 /* If this is a reset xstats is NULL, and we have cleared the
3309 * registers by reading them.
3314 /* Extended stats from ixgbe_hw_stats */
3316 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3317 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3318 rte_ixgbe_stats_strings[i].offset);
3319 xstats[count].id = count;
3324 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3325 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3326 rte_ixgbe_macsec_strings[i].offset);
3327 xstats[count].id = count;
3331 /* RX Priority Stats */
3332 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3333 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3334 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3335 rte_ixgbe_rxq_strings[stat].offset +
3336 (sizeof(uint64_t) * i));
3337 xstats[count].id = count;
3342 /* TX Priority Stats */
3343 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3344 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3345 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3346 rte_ixgbe_txq_strings[stat].offset +
3347 (sizeof(uint64_t) * i));
3348 xstats[count].id = count;
3356 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3357 uint64_t *values, unsigned int n)
3360 struct ixgbe_hw *hw =
3361 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3362 struct ixgbe_hw_stats *hw_stats =
3363 IXGBE_DEV_PRIVATE_TO_STATS(
3364 dev->data->dev_private);
3365 struct ixgbe_macsec_stats *macsec_stats =
3366 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3367 dev->data->dev_private);
3368 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3369 unsigned int i, stat, count = 0;
3371 count = ixgbe_xstats_calc_num();
3373 if (!ids && n < count)
3376 total_missed_rx = 0;
3381 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3382 &total_missed_rx, &total_qbrc, &total_qprc,
3385 /* If this is a reset xstats is NULL, and we have cleared the
3386 * registers by reading them.
3388 if (!ids && !values)
3391 /* Extended stats from ixgbe_hw_stats */
3393 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3394 values[count] = *(uint64_t *)(((char *)hw_stats) +
3395 rte_ixgbe_stats_strings[i].offset);
3400 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3401 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3402 rte_ixgbe_macsec_strings[i].offset);
3406 /* RX Priority Stats */
3407 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3408 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3410 *(uint64_t *)(((char *)hw_stats) +
3411 rte_ixgbe_rxq_strings[stat].offset +
3412 (sizeof(uint64_t) * i));
3417 /* TX Priority Stats */
3418 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3419 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3421 *(uint64_t *)(((char *)hw_stats) +
3422 rte_ixgbe_txq_strings[stat].offset +
3423 (sizeof(uint64_t) * i));
3431 uint16_t size = ixgbe_xstats_calc_num();
3432 uint64_t values_copy[size];
3434 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3436 for (i = 0; i < n; i++) {
3437 if (ids[i] >= size) {
3438 PMD_INIT_LOG(ERR, "id value isn't valid");
3441 values[i] = values_copy[ids[i]];
3447 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3449 struct ixgbe_hw_stats *stats =
3450 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3451 struct ixgbe_macsec_stats *macsec_stats =
3452 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3453 dev->data->dev_private);
3455 unsigned count = ixgbe_xstats_calc_num();
3457 /* HW registers are cleared on read */
3458 ixgbe_dev_xstats_get(dev, NULL, count);
3460 /* Reset software totals */
3461 memset(stats, 0, sizeof(*stats));
3462 memset(macsec_stats, 0, sizeof(*macsec_stats));
3466 ixgbevf_update_stats(struct rte_eth_dev *dev)
3468 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3470 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3472 /* Good Rx packet, include VF loopback */
3473 UPDATE_VF_STAT(IXGBE_VFGPRC,
3474 hw_stats->last_vfgprc, hw_stats->vfgprc);
3476 /* Good Rx octets, include VF loopback */
3477 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3478 hw_stats->last_vfgorc, hw_stats->vfgorc);
3480 /* Good Tx packet, include VF loopback */
3481 UPDATE_VF_STAT(IXGBE_VFGPTC,
3482 hw_stats->last_vfgptc, hw_stats->vfgptc);
3484 /* Good Tx octets, include VF loopback */
3485 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3486 hw_stats->last_vfgotc, hw_stats->vfgotc);
3488 /* Rx Multicst Packet */
3489 UPDATE_VF_STAT(IXGBE_VFMPRC,
3490 hw_stats->last_vfmprc, hw_stats->vfmprc);
3494 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3497 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3498 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3501 if (n < IXGBEVF_NB_XSTATS)
3502 return IXGBEVF_NB_XSTATS;
3504 ixgbevf_update_stats(dev);
3509 /* Extended stats */
3510 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3512 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3513 rte_ixgbevf_stats_strings[i].offset);
3516 return IXGBEVF_NB_XSTATS;
3520 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3522 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3523 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3525 ixgbevf_update_stats(dev);
3530 stats->ipackets = hw_stats->vfgprc;
3531 stats->ibytes = hw_stats->vfgorc;
3532 stats->opackets = hw_stats->vfgptc;
3533 stats->obytes = hw_stats->vfgotc;
3537 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3539 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3540 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3542 /* Sync HW register to the last stats */
3543 ixgbevf_dev_stats_get(dev, NULL);
3545 /* reset HW current stats*/
3546 hw_stats->vfgprc = 0;
3547 hw_stats->vfgorc = 0;
3548 hw_stats->vfgptc = 0;
3549 hw_stats->vfgotc = 0;
3553 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3555 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3556 u16 eeprom_verh, eeprom_verl;
3560 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3561 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3563 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3564 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3566 ret += 1; /* add the size of '\0' */
3567 if (fw_size < (u32)ret)
3574 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3576 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3577 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3580 dev_info->pci_dev = pci_dev;
3581 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3582 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3583 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3585 * When DCB/VT is off, maximum number of queues changes,
3586 * except for 82598EB, which remains constant.
3588 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3589 hw->mac.type != ixgbe_mac_82598EB)
3590 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3592 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3593 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3594 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3595 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3596 dev_info->max_vfs = pci_dev->max_vfs;
3597 if (hw->mac.type == ixgbe_mac_82598EB)
3598 dev_info->max_vmdq_pools = ETH_16_POOLS;
3600 dev_info->max_vmdq_pools = ETH_64_POOLS;
3601 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3602 dev_info->rx_offload_capa =
3603 DEV_RX_OFFLOAD_VLAN_STRIP |
3604 DEV_RX_OFFLOAD_IPV4_CKSUM |
3605 DEV_RX_OFFLOAD_UDP_CKSUM |
3606 DEV_RX_OFFLOAD_TCP_CKSUM;
3609 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3612 if ((hw->mac.type == ixgbe_mac_82599EB ||
3613 hw->mac.type == ixgbe_mac_X540) &&
3614 !RTE_ETH_DEV_SRIOV(dev).active)
3615 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3617 if (hw->mac.type == ixgbe_mac_82599EB ||
3618 hw->mac.type == ixgbe_mac_X540)
3619 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3621 if (hw->mac.type == ixgbe_mac_X550 ||
3622 hw->mac.type == ixgbe_mac_X550EM_x ||
3623 hw->mac.type == ixgbe_mac_X550EM_a)
3624 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3626 dev_info->tx_offload_capa =
3627 DEV_TX_OFFLOAD_VLAN_INSERT |
3628 DEV_TX_OFFLOAD_IPV4_CKSUM |
3629 DEV_TX_OFFLOAD_UDP_CKSUM |
3630 DEV_TX_OFFLOAD_TCP_CKSUM |
3631 DEV_TX_OFFLOAD_SCTP_CKSUM |
3632 DEV_TX_OFFLOAD_TCP_TSO;
3634 if (hw->mac.type == ixgbe_mac_82599EB ||
3635 hw->mac.type == ixgbe_mac_X540)
3636 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3638 if (hw->mac.type == ixgbe_mac_X550 ||
3639 hw->mac.type == ixgbe_mac_X550EM_x ||
3640 hw->mac.type == ixgbe_mac_X550EM_a)
3641 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3643 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3645 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3646 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3647 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3649 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3653 dev_info->default_txconf = (struct rte_eth_txconf) {
3655 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3656 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3657 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3659 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3660 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3661 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3662 ETH_TXQ_FLAGS_NOOFFLOADS,
3665 dev_info->rx_desc_lim = rx_desc_lim;
3666 dev_info->tx_desc_lim = tx_desc_lim;
3668 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3669 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3670 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3672 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3673 if (hw->mac.type == ixgbe_mac_X540 ||
3674 hw->mac.type == ixgbe_mac_X540_vf ||
3675 hw->mac.type == ixgbe_mac_X550 ||
3676 hw->mac.type == ixgbe_mac_X550_vf) {
3677 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3681 static const uint32_t *
3682 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3684 static const uint32_t ptypes[] = {
3685 /* For non-vec functions,
3686 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3687 * for vec functions,
3688 * refers to _recv_raw_pkts_vec().
3692 RTE_PTYPE_L3_IPV4_EXT,
3694 RTE_PTYPE_L3_IPV6_EXT,
3698 RTE_PTYPE_TUNNEL_IP,
3699 RTE_PTYPE_INNER_L3_IPV6,
3700 RTE_PTYPE_INNER_L3_IPV6_EXT,
3701 RTE_PTYPE_INNER_L4_TCP,
3702 RTE_PTYPE_INNER_L4_UDP,
3706 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3707 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3708 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3709 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3712 #if defined(RTE_ARCH_X86)
3713 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3714 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3721 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3722 struct rte_eth_dev_info *dev_info)
3724 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3725 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3727 dev_info->pci_dev = pci_dev;
3728 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3729 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3730 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3731 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3732 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3733 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3734 dev_info->max_vfs = pci_dev->max_vfs;
3735 if (hw->mac.type == ixgbe_mac_82598EB)
3736 dev_info->max_vmdq_pools = ETH_16_POOLS;
3738 dev_info->max_vmdq_pools = ETH_64_POOLS;
3739 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3740 DEV_RX_OFFLOAD_IPV4_CKSUM |
3741 DEV_RX_OFFLOAD_UDP_CKSUM |
3742 DEV_RX_OFFLOAD_TCP_CKSUM;
3743 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3744 DEV_TX_OFFLOAD_IPV4_CKSUM |
3745 DEV_TX_OFFLOAD_UDP_CKSUM |
3746 DEV_TX_OFFLOAD_TCP_CKSUM |
3747 DEV_TX_OFFLOAD_SCTP_CKSUM |
3748 DEV_TX_OFFLOAD_TCP_TSO;
3750 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3752 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3753 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3754 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3756 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3760 dev_info->default_txconf = (struct rte_eth_txconf) {
3762 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3763 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3764 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3766 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3767 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3768 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3769 ETH_TXQ_FLAGS_NOOFFLOADS,
3772 dev_info->rx_desc_lim = rx_desc_lim;
3773 dev_info->tx_desc_lim = tx_desc_lim;
3777 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3778 int *link_up, int wait_to_complete)
3781 * for a quick link status checking, wait_to_compelet == 0,
3782 * skip PF link status checking
3784 bool no_pflink_check = wait_to_complete == 0;
3785 struct ixgbe_mbx_info *mbx = &hw->mbx;
3786 struct ixgbe_mac_info *mac = &hw->mac;
3787 uint32_t links_reg, in_msg;
3790 /* If we were hit with a reset drop the link */
3791 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3792 mac->get_link_status = true;
3794 if (!mac->get_link_status)
3797 /* if link status is down no point in checking to see if pf is up */
3798 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3799 if (!(links_reg & IXGBE_LINKS_UP))
3802 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3803 * before the link status is correct
3805 if (mac->type == ixgbe_mac_82599_vf) {
3808 for (i = 0; i < 5; i++) {
3810 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3812 if (!(links_reg & IXGBE_LINKS_UP))
3817 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3818 case IXGBE_LINKS_SPEED_10G_82599:
3819 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3820 if (hw->mac.type >= ixgbe_mac_X550) {
3821 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3822 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3825 case IXGBE_LINKS_SPEED_1G_82599:
3826 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3828 case IXGBE_LINKS_SPEED_100_82599:
3829 *speed = IXGBE_LINK_SPEED_100_FULL;
3830 if (hw->mac.type == ixgbe_mac_X550) {
3831 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3832 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3835 case IXGBE_LINKS_SPEED_10_X550EM_A:
3836 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3837 /* Since Reserved in older MAC's */
3838 if (hw->mac.type >= ixgbe_mac_X550)
3839 *speed = IXGBE_LINK_SPEED_10_FULL;
3842 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3845 if (no_pflink_check) {
3846 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3847 mac->get_link_status = true;
3849 mac->get_link_status = false;
3853 /* if the read failed it could just be a mailbox collision, best wait
3854 * until we are called again and don't report an error
3856 if (mbx->ops.read(hw, &in_msg, 1, 0))
3859 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3860 /* msg is not CTS and is NACK we must have lost CTS status */
3861 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3866 /* the pf is talking, if we timed out in the past we reinit */
3867 if (!mbx->timeout) {
3872 /* if we passed all the tests above then the link is up and we no
3873 * longer need to check for link
3875 mac->get_link_status = false;
3878 *link_up = !mac->get_link_status;
3882 /* return 0 means link status changed, -1 means not changed */
3884 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3885 int wait_to_complete, int vf)
3887 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3888 struct rte_eth_link link, old;
3889 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3890 struct ixgbe_interrupt *intr =
3891 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3896 bool autoneg = false;
3898 link.link_status = ETH_LINK_DOWN;
3899 link.link_speed = 0;
3900 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3901 memset(&old, 0, sizeof(old));
3902 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3904 hw->mac.get_link_status = true;
3906 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3907 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3908 speed = hw->phy.autoneg_advertised;
3910 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3911 ixgbe_setup_link(hw, speed, true);
3914 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3915 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3919 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3921 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3924 link.link_speed = ETH_SPEED_NUM_100M;
3925 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3926 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3927 if (link.link_status == old.link_status)
3933 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3934 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3935 if (link.link_status == old.link_status)
3939 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3940 link.link_status = ETH_LINK_UP;
3941 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3943 switch (link_speed) {
3945 case IXGBE_LINK_SPEED_UNKNOWN:
3946 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3947 link.link_speed = ETH_SPEED_NUM_100M;
3950 case IXGBE_LINK_SPEED_100_FULL:
3951 link.link_speed = ETH_SPEED_NUM_100M;
3954 case IXGBE_LINK_SPEED_1GB_FULL:
3955 link.link_speed = ETH_SPEED_NUM_1G;
3958 case IXGBE_LINK_SPEED_10GB_FULL:
3959 link.link_speed = ETH_SPEED_NUM_10G;
3962 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3964 if (link.link_status == old.link_status)
3971 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3973 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3977 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3979 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3983 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3985 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3988 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3989 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3990 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3994 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3996 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3999 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4000 fctrl &= (~IXGBE_FCTRL_UPE);
4001 if (dev->data->all_multicast == 1)
4002 fctrl |= IXGBE_FCTRL_MPE;
4004 fctrl &= (~IXGBE_FCTRL_MPE);
4005 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4009 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4011 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4014 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4015 fctrl |= IXGBE_FCTRL_MPE;
4016 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4020 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4022 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4025 if (dev->data->promiscuous == 1)
4026 return; /* must remain in all_multicast mode */
4028 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4029 fctrl &= (~IXGBE_FCTRL_MPE);
4030 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4034 * It clears the interrupt causes and enables the interrupt.
4035 * It will be called once only during nic initialized.
4038 * Pointer to struct rte_eth_dev.
4041 * - On success, zero.
4042 * - On failure, a negative value.
4045 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
4047 struct ixgbe_interrupt *intr =
4048 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4050 ixgbe_dev_link_status_print(dev);
4051 intr->mask |= IXGBE_EICR_LSC;
4057 * It clears the interrupt causes and enables the interrupt.
4058 * It will be called once only during nic initialized.
4061 * Pointer to struct rte_eth_dev.
4064 * - On success, zero.
4065 * - On failure, a negative value.
4068 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4070 struct ixgbe_interrupt *intr =
4071 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4073 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4079 * It clears the interrupt causes and enables the interrupt.
4080 * It will be called once only during nic initialized.
4083 * Pointer to struct rte_eth_dev.
4086 * - On success, zero.
4087 * - On failure, a negative value.
4090 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4092 struct ixgbe_interrupt *intr =
4093 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4095 intr->mask |= IXGBE_EICR_LINKSEC;
4101 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4104 * Pointer to struct rte_eth_dev.
4107 * - On success, zero.
4108 * - On failure, a negative value.
4111 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4114 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4115 struct ixgbe_interrupt *intr =
4116 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4118 /* clear all cause mask */
4119 ixgbe_disable_intr(hw);
4121 /* read-on-clear nic registers here */
4122 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4123 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4127 /* set flag for async link update */
4128 if (eicr & IXGBE_EICR_LSC)
4129 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4131 if (eicr & IXGBE_EICR_MAILBOX)
4132 intr->flags |= IXGBE_FLAG_MAILBOX;
4134 if (eicr & IXGBE_EICR_LINKSEC)
4135 intr->flags |= IXGBE_FLAG_MACSEC;
4137 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4138 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4139 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4140 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4146 * It gets and then prints the link status.
4149 * Pointer to struct rte_eth_dev.
4152 * - On success, zero.
4153 * - On failure, a negative value.
4156 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4158 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4159 struct rte_eth_link link;
4161 memset(&link, 0, sizeof(link));
4162 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4163 if (link.link_status) {
4164 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4165 (int)(dev->data->port_id),
4166 (unsigned)link.link_speed,
4167 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4168 "full-duplex" : "half-duplex");
4170 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4171 (int)(dev->data->port_id));
4173 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4174 pci_dev->addr.domain,
4176 pci_dev->addr.devid,
4177 pci_dev->addr.function);
4181 * It executes link_update after knowing an interrupt occurred.
4184 * Pointer to struct rte_eth_dev.
4187 * - On success, zero.
4188 * - On failure, a negative value.
4191 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4192 struct rte_intr_handle *intr_handle)
4194 struct ixgbe_interrupt *intr =
4195 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4197 struct rte_eth_link link;
4198 struct ixgbe_hw *hw =
4199 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4203 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4204 ixgbe_pf_mbx_process(dev);
4205 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4208 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4209 ixgbe_handle_lasi(hw);
4210 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4213 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4214 /* get the link status before link update, for predicting later */
4215 memset(&link, 0, sizeof(link));
4216 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4218 ixgbe_dev_link_update(dev, 0);
4221 if (!link.link_status)
4222 /* handle it 1 sec later, wait it being stable */
4223 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4224 /* likely to down */
4226 /* handle it 4 sec later, wait it being stable */
4227 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4229 ixgbe_dev_link_status_print(dev);
4230 if (rte_eal_alarm_set(timeout * 1000,
4231 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4232 PMD_DRV_LOG(ERR, "Error setting alarm");
4234 /* remember original mask */
4235 intr->mask_original = intr->mask;
4236 /* only disable lsc interrupt */
4237 intr->mask &= ~IXGBE_EIMS_LSC;
4241 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4242 ixgbe_enable_intr(dev);
4243 rte_intr_enable(intr_handle);
4249 * Interrupt handler which shall be registered for alarm callback for delayed
4250 * handling specific interrupt to wait for the stable nic state. As the
4251 * NIC interrupt state is not stable for ixgbe after link is just down,
4252 * it needs to wait 4 seconds to get the stable status.
4255 * Pointer to interrupt handle.
4257 * The address of parameter (struct rte_eth_dev *) regsitered before.
4263 ixgbe_dev_interrupt_delayed_handler(void *param)
4265 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4266 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4267 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4268 struct ixgbe_interrupt *intr =
4269 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4270 struct ixgbe_hw *hw =
4271 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4274 ixgbe_disable_intr(hw);
4276 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4277 if (eicr & IXGBE_EICR_MAILBOX)
4278 ixgbe_pf_mbx_process(dev);
4280 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4281 ixgbe_handle_lasi(hw);
4282 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4285 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4286 ixgbe_dev_link_update(dev, 0);
4287 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4288 ixgbe_dev_link_status_print(dev);
4289 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4293 if (intr->flags & IXGBE_FLAG_MACSEC) {
4294 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4296 intr->flags &= ~IXGBE_FLAG_MACSEC;
4299 /* restore original mask */
4300 intr->mask = intr->mask_original;
4301 intr->mask_original = 0;
4303 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4304 ixgbe_enable_intr(dev);
4305 rte_intr_enable(intr_handle);
4309 * Interrupt handler triggered by NIC for handling
4310 * specific interrupt.
4313 * Pointer to interrupt handle.
4315 * The address of parameter (struct rte_eth_dev *) regsitered before.
4321 ixgbe_dev_interrupt_handler(void *param)
4323 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4325 ixgbe_dev_interrupt_get_status(dev);
4326 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4330 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4332 struct ixgbe_hw *hw;
4334 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4335 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4339 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4341 struct ixgbe_hw *hw;
4343 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4344 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4348 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4350 struct ixgbe_hw *hw;
4356 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358 fc_conf->pause_time = hw->fc.pause_time;
4359 fc_conf->high_water = hw->fc.high_water[0];
4360 fc_conf->low_water = hw->fc.low_water[0];
4361 fc_conf->send_xon = hw->fc.send_xon;
4362 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4365 * Return rx_pause status according to actual setting of
4368 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4369 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4375 * Return tx_pause status according to actual setting of
4378 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4379 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4384 if (rx_pause && tx_pause)
4385 fc_conf->mode = RTE_FC_FULL;
4387 fc_conf->mode = RTE_FC_RX_PAUSE;
4389 fc_conf->mode = RTE_FC_TX_PAUSE;
4391 fc_conf->mode = RTE_FC_NONE;
4397 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4399 struct ixgbe_hw *hw;
4401 uint32_t rx_buf_size;
4402 uint32_t max_high_water;
4404 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4411 PMD_INIT_FUNC_TRACE();
4413 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4414 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4415 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4418 * At least reserve one Ethernet frame for watermark
4419 * high_water/low_water in kilo bytes for ixgbe
4421 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4422 if ((fc_conf->high_water > max_high_water) ||
4423 (fc_conf->high_water < fc_conf->low_water)) {
4424 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4425 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4429 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4430 hw->fc.pause_time = fc_conf->pause_time;
4431 hw->fc.high_water[0] = fc_conf->high_water;
4432 hw->fc.low_water[0] = fc_conf->low_water;
4433 hw->fc.send_xon = fc_conf->send_xon;
4434 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4436 err = ixgbe_fc_enable(hw);
4438 /* Not negotiated is not an error case */
4439 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4441 /* check if we want to forward MAC frames - driver doesn't have native
4442 * capability to do that, so we'll write the registers ourselves */
4444 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4446 /* set or clear MFLCN.PMCF bit depending on configuration */
4447 if (fc_conf->mac_ctrl_frame_fwd != 0)
4448 mflcn |= IXGBE_MFLCN_PMCF;
4450 mflcn &= ~IXGBE_MFLCN_PMCF;
4452 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4453 IXGBE_WRITE_FLUSH(hw);
4458 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4463 * ixgbe_pfc_enable_generic - Enable flow control
4464 * @hw: pointer to hardware structure
4465 * @tc_num: traffic class number
4466 * Enable flow control according to the current settings.
4469 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4472 uint32_t mflcn_reg, fccfg_reg;
4474 uint32_t fcrtl, fcrth;
4478 /* Validate the water mark configuration */
4479 if (!hw->fc.pause_time) {
4480 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4484 /* Low water mark of zero causes XOFF floods */
4485 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4486 /* High/Low water can not be 0 */
4487 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4488 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4489 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4493 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4494 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4495 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4499 /* Negotiate the fc mode to use */
4500 ixgbe_fc_autoneg(hw);
4502 /* Disable any previous flow control settings */
4503 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4504 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4506 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4507 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4509 switch (hw->fc.current_mode) {
4512 * If the count of enabled RX Priority Flow control >1,
4513 * and the TX pause can not be disabled
4516 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4517 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4518 if (reg & IXGBE_FCRTH_FCEN)
4522 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4524 case ixgbe_fc_rx_pause:
4526 * Rx Flow control is enabled and Tx Flow control is
4527 * disabled by software override. Since there really
4528 * isn't a way to advertise that we are capable of RX
4529 * Pause ONLY, we will advertise that we support both
4530 * symmetric and asymmetric Rx PAUSE. Later, we will
4531 * disable the adapter's ability to send PAUSE frames.
4533 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4535 * If the count of enabled RX Priority Flow control >1,
4536 * and the TX pause can not be disabled
4539 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4540 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4541 if (reg & IXGBE_FCRTH_FCEN)
4545 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4547 case ixgbe_fc_tx_pause:
4549 * Tx Flow control is enabled, and Rx Flow control is
4550 * disabled by software override.
4552 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4555 /* Flow control (both Rx and Tx) is enabled by SW override. */
4556 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4557 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4560 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4561 ret_val = IXGBE_ERR_CONFIG;
4565 /* Set 802.3x based flow control settings. */
4566 mflcn_reg |= IXGBE_MFLCN_DPF;
4567 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4568 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4570 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4571 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4572 hw->fc.high_water[tc_num]) {
4573 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4574 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4575 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4577 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4579 * In order to prevent Tx hangs when the internal Tx
4580 * switch is enabled we must set the high water mark
4581 * to the maximum FCRTH value. This allows the Tx
4582 * switch to function even under heavy Rx workloads.
4584 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4586 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4588 /* Configure pause time (2 TCs per register) */
4589 reg = hw->fc.pause_time * 0x00010001;
4590 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4591 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4593 /* Configure flow control refresh threshold value */
4594 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4601 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4603 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4604 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4606 if (hw->mac.type != ixgbe_mac_82598EB) {
4607 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4613 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4616 uint32_t rx_buf_size;
4617 uint32_t max_high_water;
4619 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4620 struct ixgbe_hw *hw =
4621 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4622 struct ixgbe_dcb_config *dcb_config =
4623 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4625 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4632 PMD_INIT_FUNC_TRACE();
4634 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4635 tc_num = map[pfc_conf->priority];
4636 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4637 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4639 * At least reserve one Ethernet frame for watermark
4640 * high_water/low_water in kilo bytes for ixgbe
4642 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4643 if ((pfc_conf->fc.high_water > max_high_water) ||
4644 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4645 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4646 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4650 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4651 hw->fc.pause_time = pfc_conf->fc.pause_time;
4652 hw->fc.send_xon = pfc_conf->fc.send_xon;
4653 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4654 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4656 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4658 /* Not negotiated is not an error case */
4659 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4662 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4667 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4668 struct rte_eth_rss_reta_entry64 *reta_conf,
4671 uint16_t i, sp_reta_size;
4674 uint16_t idx, shift;
4675 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4678 PMD_INIT_FUNC_TRACE();
4680 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4681 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4686 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4687 if (reta_size != sp_reta_size) {
4688 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4689 "(%d) doesn't match the number hardware can supported "
4690 "(%d)", reta_size, sp_reta_size);
4694 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4695 idx = i / RTE_RETA_GROUP_SIZE;
4696 shift = i % RTE_RETA_GROUP_SIZE;
4697 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4701 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4702 if (mask == IXGBE_4_BIT_MASK)
4705 r = IXGBE_READ_REG(hw, reta_reg);
4706 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4707 if (mask & (0x1 << j))
4708 reta |= reta_conf[idx].reta[shift + j] <<
4711 reta |= r & (IXGBE_8_BIT_MASK <<
4714 IXGBE_WRITE_REG(hw, reta_reg, reta);
4721 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4722 struct rte_eth_rss_reta_entry64 *reta_conf,
4725 uint16_t i, sp_reta_size;
4728 uint16_t idx, shift;
4729 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4732 PMD_INIT_FUNC_TRACE();
4733 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4734 if (reta_size != sp_reta_size) {
4735 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4736 "(%d) doesn't match the number hardware can supported "
4737 "(%d)", reta_size, sp_reta_size);
4741 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4742 idx = i / RTE_RETA_GROUP_SIZE;
4743 shift = i % RTE_RETA_GROUP_SIZE;
4744 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4749 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4750 reta = IXGBE_READ_REG(hw, reta_reg);
4751 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4752 if (mask & (0x1 << j))
4753 reta_conf[idx].reta[shift + j] =
4754 ((reta >> (CHAR_BIT * j)) &
4763 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4764 uint32_t index, uint32_t pool)
4766 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4767 uint32_t enable_addr = 1;
4769 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4774 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4776 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4778 ixgbe_clear_rar(hw, index);
4782 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4784 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4786 ixgbe_remove_rar(dev, 0);
4788 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4792 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4794 if (strcmp(dev->device->driver->name, drv->driver.name))
4801 is_ixgbe_supported(struct rte_eth_dev *dev)
4803 return is_device_supported(dev, &rte_ixgbe_pmd);
4807 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4811 struct ixgbe_hw *hw;
4812 struct rte_eth_dev_info dev_info;
4813 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4814 struct rte_eth_dev_data *dev_data = dev->data;
4816 ixgbe_dev_info_get(dev, &dev_info);
4818 /* check that mtu is within the allowed range */
4819 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4822 /* If device is started, refuse mtu that requires the support of
4823 * scattered packets when this feature has not been enabled before.
4825 if (dev_data->dev_started && !dev_data->scattered_rx &&
4826 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4827 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4828 PMD_INIT_LOG(ERR, "Stop port first.");
4832 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4833 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4835 /* switch to jumbo mode if needed */
4836 if (frame_size > ETHER_MAX_LEN) {
4837 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4838 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4840 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4841 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4843 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4845 /* update max frame size */
4846 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4848 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4849 maxfrs &= 0x0000FFFF;
4850 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4851 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4857 * Virtual Function operations
4860 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4862 PMD_INIT_FUNC_TRACE();
4864 /* Clear interrupt mask to stop from interrupts being generated */
4865 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4867 IXGBE_WRITE_FLUSH(hw);
4871 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4873 PMD_INIT_FUNC_TRACE();
4875 /* VF enable interrupt autoclean */
4876 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4877 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4878 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4880 IXGBE_WRITE_FLUSH(hw);
4884 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4886 struct rte_eth_conf *conf = &dev->data->dev_conf;
4887 struct ixgbe_adapter *adapter =
4888 (struct ixgbe_adapter *)dev->data->dev_private;
4890 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4891 dev->data->port_id);
4894 * VF has no ability to enable/disable HW CRC
4895 * Keep the persistent behavior the same as Host PF
4897 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4898 if (!conf->rxmode.hw_strip_crc) {
4899 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4900 conf->rxmode.hw_strip_crc = 1;
4903 if (conf->rxmode.hw_strip_crc) {
4904 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4905 conf->rxmode.hw_strip_crc = 0;
4910 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4911 * allocation or vector Rx preconditions we will reset it.
4913 adapter->rx_bulk_alloc_allowed = true;
4914 adapter->rx_vec_allowed = true;
4920 ixgbevf_dev_start(struct rte_eth_dev *dev)
4922 struct ixgbe_hw *hw =
4923 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4924 uint32_t intr_vector = 0;
4925 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4926 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4930 PMD_INIT_FUNC_TRACE();
4932 hw->mac.ops.reset_hw(hw);
4933 hw->mac.get_link_status = true;
4935 /* negotiate mailbox API version to use with the PF. */
4936 ixgbevf_negotiate_api(hw);
4938 ixgbevf_dev_tx_init(dev);
4940 /* This can fail when allocating mbufs for descriptor rings */
4941 err = ixgbevf_dev_rx_init(dev);
4943 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4944 ixgbe_dev_clear_queues(dev);
4949 ixgbevf_set_vfta_all(dev, 1);
4952 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4953 ETH_VLAN_EXTEND_MASK;
4954 ixgbevf_vlan_offload_set(dev, mask);
4956 ixgbevf_dev_rxtx_start(dev);
4958 /* check and configure queue intr-vector mapping */
4959 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4960 intr_vector = dev->data->nb_rx_queues;
4961 if (rte_intr_efd_enable(intr_handle, intr_vector))
4965 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4966 intr_handle->intr_vec =
4967 rte_zmalloc("intr_vec",
4968 dev->data->nb_rx_queues * sizeof(int), 0);
4969 if (intr_handle->intr_vec == NULL) {
4970 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4971 " intr_vec", dev->data->nb_rx_queues);
4975 ixgbevf_configure_msix(dev);
4977 rte_intr_enable(intr_handle);
4979 /* Re-enable interrupt for VF */
4980 ixgbevf_intr_enable(hw);
4986 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4988 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4989 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4990 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4992 PMD_INIT_FUNC_TRACE();
4994 ixgbevf_intr_disable(hw);
4996 hw->adapter_stopped = 1;
4997 ixgbe_stop_adapter(hw);
5000 * Clear what we set, but we still keep shadow_vfta to
5001 * restore after device starts
5003 ixgbevf_set_vfta_all(dev, 0);
5005 /* Clear stored conf */
5006 dev->data->scattered_rx = 0;
5008 ixgbe_dev_clear_queues(dev);
5010 /* Clean datapath event and queue/vec mapping */
5011 rte_intr_efd_disable(intr_handle);
5012 if (intr_handle->intr_vec != NULL) {
5013 rte_free(intr_handle->intr_vec);
5014 intr_handle->intr_vec = NULL;
5019 ixgbevf_dev_close(struct rte_eth_dev *dev)
5021 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5023 PMD_INIT_FUNC_TRACE();
5027 ixgbevf_dev_stop(dev);
5029 ixgbe_dev_free_queues(dev);
5032 * Remove the VF MAC address ro ensure
5033 * that the VF traffic goes to the PF
5034 * after stop, close and detach of the VF
5036 ixgbevf_remove_mac_addr(dev, 0);
5039 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5041 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5042 struct ixgbe_vfta *shadow_vfta =
5043 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5044 int i = 0, j = 0, vfta = 0, mask = 1;
5046 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5047 vfta = shadow_vfta->vfta[i];
5050 for (j = 0; j < 32; j++) {
5052 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5062 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5064 struct ixgbe_hw *hw =
5065 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5066 struct ixgbe_vfta *shadow_vfta =
5067 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5068 uint32_t vid_idx = 0;
5069 uint32_t vid_bit = 0;
5072 PMD_INIT_FUNC_TRACE();
5074 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5075 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5077 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5080 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5081 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5083 /* Save what we set and retore it after device reset */
5085 shadow_vfta->vfta[vid_idx] |= vid_bit;
5087 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5093 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5095 struct ixgbe_hw *hw =
5096 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5099 PMD_INIT_FUNC_TRACE();
5101 if (queue >= hw->mac.max_rx_queues)
5104 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5106 ctrl |= IXGBE_RXDCTL_VME;
5108 ctrl &= ~IXGBE_RXDCTL_VME;
5109 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5111 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5115 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5117 struct ixgbe_hw *hw =
5118 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5122 /* VF function only support hw strip feature, others are not support */
5123 if (mask & ETH_VLAN_STRIP_MASK) {
5124 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5126 for (i = 0; i < hw->mac.max_rx_queues; i++)
5127 ixgbevf_vlan_strip_queue_set(dev, i, on);
5132 ixgbe_vt_check(struct ixgbe_hw *hw)
5136 /* if Virtualization Technology is enabled */
5137 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5138 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5139 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5147 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5149 uint32_t vector = 0;
5151 switch (hw->mac.mc_filter_type) {
5152 case 0: /* use bits [47:36] of the address */
5153 vector = ((uc_addr->addr_bytes[4] >> 4) |
5154 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5156 case 1: /* use bits [46:35] of the address */
5157 vector = ((uc_addr->addr_bytes[4] >> 3) |
5158 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5160 case 2: /* use bits [45:34] of the address */
5161 vector = ((uc_addr->addr_bytes[4] >> 2) |
5162 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5164 case 3: /* use bits [43:32] of the address */
5165 vector = ((uc_addr->addr_bytes[4]) |
5166 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5168 default: /* Invalid mc_filter_type */
5172 /* vector can only be 12-bits or boundary will be exceeded */
5178 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5186 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5187 const uint32_t ixgbe_uta_bit_shift = 5;
5188 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5189 const uint32_t bit1 = 0x1;
5191 struct ixgbe_hw *hw =
5192 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5193 struct ixgbe_uta_info *uta_info =
5194 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5196 /* The UTA table only exists on 82599 hardware and newer */
5197 if (hw->mac.type < ixgbe_mac_82599EB)
5200 vector = ixgbe_uta_vector(hw, mac_addr);
5201 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5202 uta_shift = vector & ixgbe_uta_bit_mask;
5204 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5208 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5210 uta_info->uta_in_use++;
5211 reg_val |= (bit1 << uta_shift);
5212 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5214 uta_info->uta_in_use--;
5215 reg_val &= ~(bit1 << uta_shift);
5216 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5219 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5221 if (uta_info->uta_in_use > 0)
5222 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5223 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5225 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5231 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5234 struct ixgbe_hw *hw =
5235 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5236 struct ixgbe_uta_info *uta_info =
5237 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5239 /* The UTA table only exists on 82599 hardware and newer */
5240 if (hw->mac.type < ixgbe_mac_82599EB)
5244 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5245 uta_info->uta_shadow[i] = ~0;
5246 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5249 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5250 uta_info->uta_shadow[i] = 0;
5251 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5259 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5261 uint32_t new_val = orig_val;
5263 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5264 new_val |= IXGBE_VMOLR_AUPE;
5265 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5266 new_val |= IXGBE_VMOLR_ROMPE;
5267 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5268 new_val |= IXGBE_VMOLR_ROPE;
5269 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5270 new_val |= IXGBE_VMOLR_BAM;
5271 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5272 new_val |= IXGBE_VMOLR_MPE;
5277 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5278 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5279 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5280 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5281 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5282 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5283 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5286 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5287 struct rte_eth_mirror_conf *mirror_conf,
5288 uint8_t rule_id, uint8_t on)
5290 uint32_t mr_ctl, vlvf;
5291 uint32_t mp_lsb = 0;
5292 uint32_t mv_msb = 0;
5293 uint32_t mv_lsb = 0;
5294 uint32_t mp_msb = 0;
5297 uint64_t vlan_mask = 0;
5299 const uint8_t pool_mask_offset = 32;
5300 const uint8_t vlan_mask_offset = 32;
5301 const uint8_t dst_pool_offset = 8;
5302 const uint8_t rule_mr_offset = 4;
5303 const uint8_t mirror_rule_mask = 0x0F;
5305 struct ixgbe_mirror_info *mr_info =
5306 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5307 struct ixgbe_hw *hw =
5308 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5309 uint8_t mirror_type = 0;
5311 if (ixgbe_vt_check(hw) < 0)
5314 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5317 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5318 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5319 mirror_conf->rule_type);
5323 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5324 mirror_type |= IXGBE_MRCTL_VLME;
5325 /* Check if vlan id is valid and find conresponding VLAN ID
5328 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5329 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5330 /* search vlan id related pool vlan filter
5333 reg_index = ixgbe_find_vlvf_slot(
5335 mirror_conf->vlan.vlan_id[i],
5339 vlvf = IXGBE_READ_REG(hw,
5340 IXGBE_VLVF(reg_index));
5341 if ((vlvf & IXGBE_VLVF_VIEN) &&
5342 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5343 mirror_conf->vlan.vlan_id[i]))
5344 vlan_mask |= (1ULL << reg_index);
5351 mv_lsb = vlan_mask & 0xFFFFFFFF;
5352 mv_msb = vlan_mask >> vlan_mask_offset;
5354 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5355 mirror_conf->vlan.vlan_mask;
5356 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5357 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5358 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5359 mirror_conf->vlan.vlan_id[i];
5364 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5365 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5366 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5371 * if enable pool mirror, write related pool mask register,if disable
5372 * pool mirror, clear PFMRVM register
5374 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5375 mirror_type |= IXGBE_MRCTL_VPME;
5377 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5378 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5379 mr_info->mr_conf[rule_id].pool_mask =
5380 mirror_conf->pool_mask;
5385 mr_info->mr_conf[rule_id].pool_mask = 0;
5388 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5389 mirror_type |= IXGBE_MRCTL_UPME;
5390 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5391 mirror_type |= IXGBE_MRCTL_DPME;
5393 /* read mirror control register and recalculate it */
5394 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5397 mr_ctl |= mirror_type;
5398 mr_ctl &= mirror_rule_mask;
5399 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5401 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5404 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5405 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5407 /* write mirrror control register */
5408 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5410 /* write pool mirrror control register */
5411 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5412 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5413 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5416 /* write VLAN mirrror control register */
5417 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5418 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5419 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5427 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5430 uint32_t lsb_val = 0;
5431 uint32_t msb_val = 0;
5432 const uint8_t rule_mr_offset = 4;
5434 struct ixgbe_hw *hw =
5435 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5436 struct ixgbe_mirror_info *mr_info =
5437 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5439 if (ixgbe_vt_check(hw) < 0)
5442 memset(&mr_info->mr_conf[rule_id], 0,
5443 sizeof(struct rte_eth_mirror_conf));
5445 /* clear PFVMCTL register */
5446 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5448 /* clear pool mask register */
5449 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5450 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5452 /* clear vlan mask register */
5453 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5454 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5460 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5462 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5463 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5465 struct ixgbe_hw *hw =
5466 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5468 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5469 mask |= (1 << IXGBE_MISC_VEC_ID);
5470 RTE_SET_USED(queue_id);
5471 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5473 rte_intr_enable(intr_handle);
5479 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5482 struct ixgbe_hw *hw =
5483 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5485 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5486 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5487 RTE_SET_USED(queue_id);
5488 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5494 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5496 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5497 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5499 struct ixgbe_hw *hw =
5500 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5501 struct ixgbe_interrupt *intr =
5502 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5504 if (queue_id < 16) {
5505 ixgbe_disable_intr(hw);
5506 intr->mask |= (1 << queue_id);
5507 ixgbe_enable_intr(dev);
5508 } else if (queue_id < 32) {
5509 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5510 mask &= (1 << queue_id);
5511 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5512 } else if (queue_id < 64) {
5513 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5514 mask &= (1 << (queue_id - 32));
5515 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5517 rte_intr_enable(intr_handle);
5523 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5526 struct ixgbe_hw *hw =
5527 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5528 struct ixgbe_interrupt *intr =
5529 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5531 if (queue_id < 16) {
5532 ixgbe_disable_intr(hw);
5533 intr->mask &= ~(1 << queue_id);
5534 ixgbe_enable_intr(dev);
5535 } else if (queue_id < 32) {
5536 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5537 mask &= ~(1 << queue_id);
5538 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5539 } else if (queue_id < 64) {
5540 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5541 mask &= ~(1 << (queue_id - 32));
5542 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5549 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5550 uint8_t queue, uint8_t msix_vector)
5554 if (direction == -1) {
5556 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5557 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5560 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5562 /* rx or tx cause */
5563 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5564 idx = ((16 * (queue & 1)) + (8 * direction));
5565 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5566 tmp &= ~(0xFF << idx);
5567 tmp |= (msix_vector << idx);
5568 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5573 * set the IVAR registers, mapping interrupt causes to vectors
5575 * pointer to ixgbe_hw struct
5577 * 0 for Rx, 1 for Tx, -1 for other causes
5579 * queue to map the corresponding interrupt to
5581 * the vector to map to the corresponding queue
5584 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5585 uint8_t queue, uint8_t msix_vector)
5589 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5590 if (hw->mac.type == ixgbe_mac_82598EB) {
5591 if (direction == -1)
5593 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5594 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5595 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5596 tmp |= (msix_vector << (8 * (queue & 0x3)));
5597 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5598 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5599 (hw->mac.type == ixgbe_mac_X540)) {
5600 if (direction == -1) {
5602 idx = ((queue & 1) * 8);
5603 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5604 tmp &= ~(0xFF << idx);
5605 tmp |= (msix_vector << idx);
5606 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5608 /* rx or tx causes */
5609 idx = ((16 * (queue & 1)) + (8 * direction));
5610 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5611 tmp &= ~(0xFF << idx);
5612 tmp |= (msix_vector << idx);
5613 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5619 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5621 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5622 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5623 struct ixgbe_hw *hw =
5624 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5626 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5628 /* Configure VF other cause ivar */
5629 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5631 /* won't configure msix register if no mapping is done
5632 * between intr vector and event fd.
5634 if (!rte_intr_dp_is_en(intr_handle))
5637 /* Configure all RX queues of VF */
5638 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5639 /* Force all queue use vector 0,
5640 * as IXGBE_VF_MAXMSIVECOTR = 1
5642 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5643 intr_handle->intr_vec[q_idx] = vector_idx;
5648 * Sets up the hardware to properly generate MSI-X interrupts
5650 * board private structure
5653 ixgbe_configure_msix(struct rte_eth_dev *dev)
5655 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5656 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5657 struct ixgbe_hw *hw =
5658 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5659 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5660 uint32_t vec = IXGBE_MISC_VEC_ID;
5664 /* won't configure msix register if no mapping is done
5665 * between intr vector and event fd
5667 if (!rte_intr_dp_is_en(intr_handle))
5670 if (rte_intr_allow_others(intr_handle))
5671 vec = base = IXGBE_RX_VEC_START;
5673 /* setup GPIE for MSI-x mode */
5674 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5675 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5676 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5677 /* auto clearing and auto setting corresponding bits in EIMS
5678 * when MSI-X interrupt is triggered
5680 if (hw->mac.type == ixgbe_mac_82598EB) {
5681 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5683 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5684 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5686 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5688 /* Populate the IVAR table and set the ITR values to the
5689 * corresponding register.
5691 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5693 /* by default, 1:1 mapping */
5694 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5695 intr_handle->intr_vec[queue_id] = vec;
5696 if (vec < base + intr_handle->nb_efd - 1)
5700 switch (hw->mac.type) {
5701 case ixgbe_mac_82598EB:
5702 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5705 case ixgbe_mac_82599EB:
5706 case ixgbe_mac_X540:
5707 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5712 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5713 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5715 /* set up to autoclear timer, and the vectors */
5716 mask = IXGBE_EIMS_ENABLE_MASK;
5717 mask &= ~(IXGBE_EIMS_OTHER |
5718 IXGBE_EIMS_MAILBOX |
5721 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5724 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5725 uint16_t queue_idx, uint16_t tx_rate)
5727 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5728 uint32_t rf_dec, rf_int;
5730 uint16_t link_speed = dev->data->dev_link.link_speed;
5732 if (queue_idx >= hw->mac.max_tx_queues)
5736 /* Calculate the rate factor values to set */
5737 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5738 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5739 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5741 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5742 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5743 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5744 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5750 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5751 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5754 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5755 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5756 IXGBE_MAX_JUMBO_FRAME_SIZE))
5757 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5758 IXGBE_MMW_SIZE_JUMBO_FRAME);
5760 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5761 IXGBE_MMW_SIZE_DEFAULT);
5763 /* Set RTTBCNRC of queue X */
5764 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5765 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5766 IXGBE_WRITE_FLUSH(hw);
5772 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5773 __attribute__((unused)) uint32_t index,
5774 __attribute__((unused)) uint32_t pool)
5776 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5780 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5781 * operation. Trap this case to avoid exhausting the [very limited]
5782 * set of PF resources used to store VF MAC addresses.
5784 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5786 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5788 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5789 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5790 mac_addr->addr_bytes[0],
5791 mac_addr->addr_bytes[1],
5792 mac_addr->addr_bytes[2],
5793 mac_addr->addr_bytes[3],
5794 mac_addr->addr_bytes[4],
5795 mac_addr->addr_bytes[5],
5801 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5803 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5804 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5805 struct ether_addr *mac_addr;
5810 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5811 * not support the deletion of a given MAC address.
5812 * Instead, it imposes to delete all MAC addresses, then to add again
5813 * all MAC addresses with the exception of the one to be deleted.
5815 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5818 * Add again all MAC addresses, with the exception of the deleted one
5819 * and of the permanent MAC address.
5821 for (i = 0, mac_addr = dev->data->mac_addrs;
5822 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5823 /* Skip the deleted MAC address */
5826 /* Skip NULL MAC addresses */
5827 if (is_zero_ether_addr(mac_addr))
5829 /* Skip the permanent MAC address */
5830 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5832 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5835 "Adding again MAC address "
5836 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5838 mac_addr->addr_bytes[0],
5839 mac_addr->addr_bytes[1],
5840 mac_addr->addr_bytes[2],
5841 mac_addr->addr_bytes[3],
5842 mac_addr->addr_bytes[4],
5843 mac_addr->addr_bytes[5],
5849 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5851 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5853 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5857 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5858 struct rte_eth_syn_filter *filter,
5861 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5862 struct ixgbe_filter_info *filter_info =
5863 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5867 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5870 syn_info = filter_info->syn_info;
5873 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5875 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5876 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5878 if (filter->hig_pri)
5879 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5881 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5883 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5884 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5886 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5889 filter_info->syn_info = synqf;
5890 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5891 IXGBE_WRITE_FLUSH(hw);
5896 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5897 struct rte_eth_syn_filter *filter)
5899 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5900 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5902 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5903 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5904 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5911 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5912 enum rte_filter_op filter_op,
5915 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5918 MAC_TYPE_FILTER_SUP(hw->mac.type);
5920 if (filter_op == RTE_ETH_FILTER_NOP)
5924 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5929 switch (filter_op) {
5930 case RTE_ETH_FILTER_ADD:
5931 ret = ixgbe_syn_filter_set(dev,
5932 (struct rte_eth_syn_filter *)arg,
5935 case RTE_ETH_FILTER_DELETE:
5936 ret = ixgbe_syn_filter_set(dev,
5937 (struct rte_eth_syn_filter *)arg,
5940 case RTE_ETH_FILTER_GET:
5941 ret = ixgbe_syn_filter_get(dev,
5942 (struct rte_eth_syn_filter *)arg);
5945 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5954 static inline enum ixgbe_5tuple_protocol
5955 convert_protocol_type(uint8_t protocol_value)
5957 if (protocol_value == IPPROTO_TCP)
5958 return IXGBE_FILTER_PROTOCOL_TCP;
5959 else if (protocol_value == IPPROTO_UDP)
5960 return IXGBE_FILTER_PROTOCOL_UDP;
5961 else if (protocol_value == IPPROTO_SCTP)
5962 return IXGBE_FILTER_PROTOCOL_SCTP;
5964 return IXGBE_FILTER_PROTOCOL_NONE;
5967 /* inject a 5-tuple filter to HW */
5969 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5970 struct ixgbe_5tuple_filter *filter)
5972 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5974 uint32_t ftqf, sdpqf;
5975 uint32_t l34timir = 0;
5976 uint8_t mask = 0xff;
5980 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5981 IXGBE_SDPQF_DSTPORT_SHIFT);
5982 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5984 ftqf = (uint32_t)(filter->filter_info.proto &
5985 IXGBE_FTQF_PROTOCOL_MASK);
5986 ftqf |= (uint32_t)((filter->filter_info.priority &
5987 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5988 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5989 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5990 if (filter->filter_info.dst_ip_mask == 0)
5991 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5992 if (filter->filter_info.src_port_mask == 0)
5993 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5994 if (filter->filter_info.dst_port_mask == 0)
5995 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5996 if (filter->filter_info.proto_mask == 0)
5997 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5998 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5999 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6000 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6002 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6003 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6004 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6005 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6007 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6008 l34timir |= (uint32_t)(filter->queue <<
6009 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6010 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6014 * add a 5tuple filter
6017 * dev: Pointer to struct rte_eth_dev.
6018 * index: the index the filter allocates.
6019 * filter: ponter to the filter that will be added.
6020 * rx_queue: the queue id the filter assigned to.
6023 * - On success, zero.
6024 * - On failure, a negative value.
6027 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6028 struct ixgbe_5tuple_filter *filter)
6030 struct ixgbe_filter_info *filter_info =
6031 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6035 * look for an unused 5tuple filter index,
6036 * and insert the filter to list.
6038 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6039 idx = i / (sizeof(uint32_t) * NBBY);
6040 shift = i % (sizeof(uint32_t) * NBBY);
6041 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6042 filter_info->fivetuple_mask[idx] |= 1 << shift;
6044 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6050 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6051 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6055 ixgbe_inject_5tuple_filter(dev, filter);
6061 * remove a 5tuple filter
6064 * dev: Pointer to struct rte_eth_dev.
6065 * filter: the pointer of the filter will be removed.
6068 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6069 struct ixgbe_5tuple_filter *filter)
6071 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6072 struct ixgbe_filter_info *filter_info =
6073 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6074 uint16_t index = filter->index;
6076 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6077 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6078 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6081 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6082 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6083 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6084 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6085 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6089 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6091 struct ixgbe_hw *hw;
6092 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6093 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6095 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6097 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6100 /* refuse mtu that requires the support of scattered packets when this
6101 * feature has not been enabled before.
6103 if (!rx_conf->enable_scatter &&
6104 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6105 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6109 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6110 * request of the version 2.0 of the mailbox API.
6111 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6112 * of the mailbox API.
6113 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6114 * prior to 3.11.33 which contains the following change:
6115 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6117 ixgbevf_rlpml_set_vf(hw, max_frame);
6119 /* update max frame size */
6120 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6124 static inline struct ixgbe_5tuple_filter *
6125 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6126 struct ixgbe_5tuple_filter_info *key)
6128 struct ixgbe_5tuple_filter *it;
6130 TAILQ_FOREACH(it, filter_list, entries) {
6131 if (memcmp(key, &it->filter_info,
6132 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6139 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6141 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6142 struct ixgbe_5tuple_filter_info *filter_info)
6144 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6145 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6146 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6149 switch (filter->dst_ip_mask) {
6151 filter_info->dst_ip_mask = 0;
6152 filter_info->dst_ip = filter->dst_ip;
6155 filter_info->dst_ip_mask = 1;
6158 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6162 switch (filter->src_ip_mask) {
6164 filter_info->src_ip_mask = 0;
6165 filter_info->src_ip = filter->src_ip;
6168 filter_info->src_ip_mask = 1;
6171 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6175 switch (filter->dst_port_mask) {
6177 filter_info->dst_port_mask = 0;
6178 filter_info->dst_port = filter->dst_port;
6181 filter_info->dst_port_mask = 1;
6184 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6188 switch (filter->src_port_mask) {
6190 filter_info->src_port_mask = 0;
6191 filter_info->src_port = filter->src_port;
6194 filter_info->src_port_mask = 1;
6197 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6201 switch (filter->proto_mask) {
6203 filter_info->proto_mask = 0;
6204 filter_info->proto =
6205 convert_protocol_type(filter->proto);
6208 filter_info->proto_mask = 1;
6211 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6215 filter_info->priority = (uint8_t)filter->priority;
6220 * add or delete a ntuple filter
6223 * dev: Pointer to struct rte_eth_dev.
6224 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6225 * add: if true, add filter, if false, remove filter
6228 * - On success, zero.
6229 * - On failure, a negative value.
6232 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6233 struct rte_eth_ntuple_filter *ntuple_filter,
6236 struct ixgbe_filter_info *filter_info =
6237 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6238 struct ixgbe_5tuple_filter_info filter_5tuple;
6239 struct ixgbe_5tuple_filter *filter;
6242 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6243 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6247 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6248 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6252 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6254 if (filter != NULL && add) {
6255 PMD_DRV_LOG(ERR, "filter exists.");
6258 if (filter == NULL && !add) {
6259 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6264 filter = rte_zmalloc("ixgbe_5tuple_filter",
6265 sizeof(struct ixgbe_5tuple_filter), 0);
6268 (void)rte_memcpy(&filter->filter_info,
6270 sizeof(struct ixgbe_5tuple_filter_info));
6271 filter->queue = ntuple_filter->queue;
6272 ret = ixgbe_add_5tuple_filter(dev, filter);
6278 ixgbe_remove_5tuple_filter(dev, filter);
6284 * get a ntuple filter
6287 * dev: Pointer to struct rte_eth_dev.
6288 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6291 * - On success, zero.
6292 * - On failure, a negative value.
6295 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6296 struct rte_eth_ntuple_filter *ntuple_filter)
6298 struct ixgbe_filter_info *filter_info =
6299 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6300 struct ixgbe_5tuple_filter_info filter_5tuple;
6301 struct ixgbe_5tuple_filter *filter;
6304 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6305 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6309 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6310 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6314 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6316 if (filter == NULL) {
6317 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6320 ntuple_filter->queue = filter->queue;
6325 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6326 * @dev: pointer to rte_eth_dev structure
6327 * @filter_op:operation will be taken.
6328 * @arg: a pointer to specific structure corresponding to the filter_op
6331 * - On success, zero.
6332 * - On failure, a negative value.
6335 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6336 enum rte_filter_op filter_op,
6339 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6342 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6344 if (filter_op == RTE_ETH_FILTER_NOP)
6348 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6353 switch (filter_op) {
6354 case RTE_ETH_FILTER_ADD:
6355 ret = ixgbe_add_del_ntuple_filter(dev,
6356 (struct rte_eth_ntuple_filter *)arg,
6359 case RTE_ETH_FILTER_DELETE:
6360 ret = ixgbe_add_del_ntuple_filter(dev,
6361 (struct rte_eth_ntuple_filter *)arg,
6364 case RTE_ETH_FILTER_GET:
6365 ret = ixgbe_get_ntuple_filter(dev,
6366 (struct rte_eth_ntuple_filter *)arg);
6369 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6377 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6378 struct rte_eth_ethertype_filter *filter,
6381 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6382 struct ixgbe_filter_info *filter_info =
6383 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6387 struct ixgbe_ethertype_filter ethertype_filter;
6389 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6392 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6393 filter->ether_type == ETHER_TYPE_IPv6) {
6394 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6395 " ethertype filter.", filter->ether_type);
6399 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6400 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6403 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6404 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6408 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6409 if (ret >= 0 && add) {
6410 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6411 filter->ether_type);
6414 if (ret < 0 && !add) {
6415 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6416 filter->ether_type);
6421 etqf = IXGBE_ETQF_FILTER_EN;
6422 etqf |= (uint32_t)filter->ether_type;
6423 etqs |= (uint32_t)((filter->queue <<
6424 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6425 IXGBE_ETQS_RX_QUEUE);
6426 etqs |= IXGBE_ETQS_QUEUE_EN;
6428 ethertype_filter.ethertype = filter->ether_type;
6429 ethertype_filter.etqf = etqf;
6430 ethertype_filter.etqs = etqs;
6431 ethertype_filter.conf = FALSE;
6432 ret = ixgbe_ethertype_filter_insert(filter_info,
6435 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6439 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6443 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6444 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6445 IXGBE_WRITE_FLUSH(hw);
6451 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6452 struct rte_eth_ethertype_filter *filter)
6454 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6455 struct ixgbe_filter_info *filter_info =
6456 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6457 uint32_t etqf, etqs;
6460 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6462 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6463 filter->ether_type);
6467 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6468 if (etqf & IXGBE_ETQF_FILTER_EN) {
6469 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6470 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6472 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6473 IXGBE_ETQS_RX_QUEUE_SHIFT;
6480 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6481 * @dev: pointer to rte_eth_dev structure
6482 * @filter_op:operation will be taken.
6483 * @arg: a pointer to specific structure corresponding to the filter_op
6486 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6487 enum rte_filter_op filter_op,
6490 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6493 MAC_TYPE_FILTER_SUP(hw->mac.type);
6495 if (filter_op == RTE_ETH_FILTER_NOP)
6499 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6504 switch (filter_op) {
6505 case RTE_ETH_FILTER_ADD:
6506 ret = ixgbe_add_del_ethertype_filter(dev,
6507 (struct rte_eth_ethertype_filter *)arg,
6510 case RTE_ETH_FILTER_DELETE:
6511 ret = ixgbe_add_del_ethertype_filter(dev,
6512 (struct rte_eth_ethertype_filter *)arg,
6515 case RTE_ETH_FILTER_GET:
6516 ret = ixgbe_get_ethertype_filter(dev,
6517 (struct rte_eth_ethertype_filter *)arg);
6520 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6528 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6529 enum rte_filter_type filter_type,
6530 enum rte_filter_op filter_op,
6535 switch (filter_type) {
6536 case RTE_ETH_FILTER_NTUPLE:
6537 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6539 case RTE_ETH_FILTER_ETHERTYPE:
6540 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6542 case RTE_ETH_FILTER_SYN:
6543 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6545 case RTE_ETH_FILTER_FDIR:
6546 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6548 case RTE_ETH_FILTER_L2_TUNNEL:
6549 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6551 case RTE_ETH_FILTER_GENERIC:
6552 if (filter_op != RTE_ETH_FILTER_GET)
6554 *(const void **)arg = &ixgbe_flow_ops;
6557 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6567 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6568 u8 **mc_addr_ptr, u32 *vmdq)
6573 mc_addr = *mc_addr_ptr;
6574 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6579 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6580 struct ether_addr *mc_addr_set,
6581 uint32_t nb_mc_addr)
6583 struct ixgbe_hw *hw;
6586 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6587 mc_addr_list = (u8 *)mc_addr_set;
6588 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6589 ixgbe_dev_addr_list_itr, TRUE);
6593 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6595 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6596 uint64_t systime_cycles;
6598 switch (hw->mac.type) {
6599 case ixgbe_mac_X550:
6600 case ixgbe_mac_X550EM_x:
6601 case ixgbe_mac_X550EM_a:
6602 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6603 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6604 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6608 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6609 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6613 return systime_cycles;
6617 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6619 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6620 uint64_t rx_tstamp_cycles;
6622 switch (hw->mac.type) {
6623 case ixgbe_mac_X550:
6624 case ixgbe_mac_X550EM_x:
6625 case ixgbe_mac_X550EM_a:
6626 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6627 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6628 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6632 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6633 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6634 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6638 return rx_tstamp_cycles;
6642 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6644 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6645 uint64_t tx_tstamp_cycles;
6647 switch (hw->mac.type) {
6648 case ixgbe_mac_X550:
6649 case ixgbe_mac_X550EM_x:
6650 case ixgbe_mac_X550EM_a:
6651 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6652 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6653 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6657 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6658 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6659 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6663 return tx_tstamp_cycles;
6667 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6669 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6670 struct ixgbe_adapter *adapter =
6671 (struct ixgbe_adapter *)dev->data->dev_private;
6672 struct rte_eth_link link;
6673 uint32_t incval = 0;
6676 /* Get current link speed. */
6677 memset(&link, 0, sizeof(link));
6678 ixgbe_dev_link_update(dev, 1);
6679 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6681 switch (link.link_speed) {
6682 case ETH_SPEED_NUM_100M:
6683 incval = IXGBE_INCVAL_100;
6684 shift = IXGBE_INCVAL_SHIFT_100;
6686 case ETH_SPEED_NUM_1G:
6687 incval = IXGBE_INCVAL_1GB;
6688 shift = IXGBE_INCVAL_SHIFT_1GB;
6690 case ETH_SPEED_NUM_10G:
6692 incval = IXGBE_INCVAL_10GB;
6693 shift = IXGBE_INCVAL_SHIFT_10GB;
6697 switch (hw->mac.type) {
6698 case ixgbe_mac_X550:
6699 case ixgbe_mac_X550EM_x:
6700 case ixgbe_mac_X550EM_a:
6701 /* Independent of link speed. */
6703 /* Cycles read will be interpreted as ns. */
6706 case ixgbe_mac_X540:
6707 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6709 case ixgbe_mac_82599EB:
6710 incval >>= IXGBE_INCVAL_SHIFT_82599;
6711 shift -= IXGBE_INCVAL_SHIFT_82599;
6712 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6713 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6716 /* Not supported. */
6720 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6721 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6722 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6724 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6725 adapter->systime_tc.cc_shift = shift;
6726 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6728 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6729 adapter->rx_tstamp_tc.cc_shift = shift;
6730 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6732 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6733 adapter->tx_tstamp_tc.cc_shift = shift;
6734 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6738 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6740 struct ixgbe_adapter *adapter =
6741 (struct ixgbe_adapter *)dev->data->dev_private;
6743 adapter->systime_tc.nsec += delta;
6744 adapter->rx_tstamp_tc.nsec += delta;
6745 adapter->tx_tstamp_tc.nsec += delta;
6751 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6754 struct ixgbe_adapter *adapter =
6755 (struct ixgbe_adapter *)dev->data->dev_private;
6757 ns = rte_timespec_to_ns(ts);
6758 /* Set the timecounters to a new value. */
6759 adapter->systime_tc.nsec = ns;
6760 adapter->rx_tstamp_tc.nsec = ns;
6761 adapter->tx_tstamp_tc.nsec = ns;
6767 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6769 uint64_t ns, systime_cycles;
6770 struct ixgbe_adapter *adapter =
6771 (struct ixgbe_adapter *)dev->data->dev_private;
6773 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6774 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6775 *ts = rte_ns_to_timespec(ns);
6781 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6783 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6787 /* Stop the timesync system time. */
6788 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6789 /* Reset the timesync system time value. */
6790 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6791 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6793 /* Enable system time for platforms where it isn't on by default. */
6794 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6795 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6796 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6798 ixgbe_start_timecounters(dev);
6800 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6801 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6803 IXGBE_ETQF_FILTER_EN |
6806 /* Enable timestamping of received PTP packets. */
6807 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6808 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6809 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6811 /* Enable timestamping of transmitted PTP packets. */
6812 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6813 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6814 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6816 IXGBE_WRITE_FLUSH(hw);
6822 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6824 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6827 /* Disable timestamping of transmitted PTP packets. */
6828 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6829 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6830 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6832 /* Disable timestamping of received PTP packets. */
6833 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6834 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6835 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6837 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6838 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6840 /* Stop incrementating the System Time registers. */
6841 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6847 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6848 struct timespec *timestamp,
6849 uint32_t flags __rte_unused)
6851 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6852 struct ixgbe_adapter *adapter =
6853 (struct ixgbe_adapter *)dev->data->dev_private;
6854 uint32_t tsync_rxctl;
6855 uint64_t rx_tstamp_cycles;
6858 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6859 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6862 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6863 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6864 *timestamp = rte_ns_to_timespec(ns);
6870 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6871 struct timespec *timestamp)
6873 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6874 struct ixgbe_adapter *adapter =
6875 (struct ixgbe_adapter *)dev->data->dev_private;
6876 uint32_t tsync_txctl;
6877 uint64_t tx_tstamp_cycles;
6880 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6881 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6884 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6885 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6886 *timestamp = rte_ns_to_timespec(ns);
6892 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6894 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6897 const struct reg_info *reg_group;
6898 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6899 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6901 while ((reg_group = reg_set[g_ind++]))
6902 count += ixgbe_regs_group_count(reg_group);
6908 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6912 const struct reg_info *reg_group;
6914 while ((reg_group = ixgbevf_regs[g_ind++]))
6915 count += ixgbe_regs_group_count(reg_group);
6921 ixgbe_get_regs(struct rte_eth_dev *dev,
6922 struct rte_dev_reg_info *regs)
6924 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6925 uint32_t *data = regs->data;
6928 const struct reg_info *reg_group;
6929 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6930 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6933 regs->length = ixgbe_get_reg_length(dev);
6934 regs->width = sizeof(uint32_t);
6938 /* Support only full register dump */
6939 if ((regs->length == 0) ||
6940 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6941 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6943 while ((reg_group = reg_set[g_ind++]))
6944 count += ixgbe_read_regs_group(dev, &data[count],
6953 ixgbevf_get_regs(struct rte_eth_dev *dev,
6954 struct rte_dev_reg_info *regs)
6956 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6957 uint32_t *data = regs->data;
6960 const struct reg_info *reg_group;
6963 regs->length = ixgbevf_get_reg_length(dev);
6964 regs->width = sizeof(uint32_t);
6968 /* Support only full register dump */
6969 if ((regs->length == 0) ||
6970 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6971 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6973 while ((reg_group = ixgbevf_regs[g_ind++]))
6974 count += ixgbe_read_regs_group(dev, &data[count],
6983 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6985 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6987 /* Return unit is byte count */
6988 return hw->eeprom.word_size * 2;
6992 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6993 struct rte_dev_eeprom_info *in_eeprom)
6995 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6996 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6997 uint16_t *data = in_eeprom->data;
7000 first = in_eeprom->offset >> 1;
7001 length = in_eeprom->length >> 1;
7002 if ((first > hw->eeprom.word_size) ||
7003 ((first + length) > hw->eeprom.word_size))
7006 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7008 return eeprom->ops.read_buffer(hw, first, length, data);
7012 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7013 struct rte_dev_eeprom_info *in_eeprom)
7015 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7016 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7017 uint16_t *data = in_eeprom->data;
7020 first = in_eeprom->offset >> 1;
7021 length = in_eeprom->length >> 1;
7022 if ((first > hw->eeprom.word_size) ||
7023 ((first + length) > hw->eeprom.word_size))
7026 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7028 return eeprom->ops.write_buffer(hw, first, length, data);
7032 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7034 case ixgbe_mac_X550:
7035 case ixgbe_mac_X550EM_x:
7036 case ixgbe_mac_X550EM_a:
7037 return ETH_RSS_RETA_SIZE_512;
7038 case ixgbe_mac_X550_vf:
7039 case ixgbe_mac_X550EM_x_vf:
7040 case ixgbe_mac_X550EM_a_vf:
7041 return ETH_RSS_RETA_SIZE_64;
7043 return ETH_RSS_RETA_SIZE_128;
7048 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7050 case ixgbe_mac_X550:
7051 case ixgbe_mac_X550EM_x:
7052 case ixgbe_mac_X550EM_a:
7053 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7054 return IXGBE_RETA(reta_idx >> 2);
7056 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7057 case ixgbe_mac_X550_vf:
7058 case ixgbe_mac_X550EM_x_vf:
7059 case ixgbe_mac_X550EM_a_vf:
7060 return IXGBE_VFRETA(reta_idx >> 2);
7062 return IXGBE_RETA(reta_idx >> 2);
7067 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7069 case ixgbe_mac_X550_vf:
7070 case ixgbe_mac_X550EM_x_vf:
7071 case ixgbe_mac_X550EM_a_vf:
7072 return IXGBE_VFMRQC;
7079 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7081 case ixgbe_mac_X550_vf:
7082 case ixgbe_mac_X550EM_x_vf:
7083 case ixgbe_mac_X550EM_a_vf:
7084 return IXGBE_VFRSSRK(i);
7086 return IXGBE_RSSRK(i);
7091 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7093 case ixgbe_mac_82599_vf:
7094 case ixgbe_mac_X540_vf:
7102 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7103 struct rte_eth_dcb_info *dcb_info)
7105 struct ixgbe_dcb_config *dcb_config =
7106 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7107 struct ixgbe_dcb_tc_config *tc;
7110 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7111 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7113 dcb_info->nb_tcs = 1;
7115 if (dcb_config->vt_mode) { /* vt is enabled*/
7116 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7117 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7118 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7119 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7120 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7121 for (j = 0; j < dcb_info->nb_tcs; j++) {
7122 dcb_info->tc_queue.tc_rxq[i][j].base =
7123 i * dcb_info->nb_tcs + j;
7124 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7125 dcb_info->tc_queue.tc_txq[i][j].base =
7126 i * dcb_info->nb_tcs + j;
7127 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7130 } else { /* vt is disabled*/
7131 struct rte_eth_dcb_rx_conf *rx_conf =
7132 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7133 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7134 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7135 if (dcb_info->nb_tcs == ETH_4_TCS) {
7136 for (i = 0; i < dcb_info->nb_tcs; i++) {
7137 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7138 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7140 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7141 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7142 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7143 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7144 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7145 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7146 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7147 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7148 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7149 for (i = 0; i < dcb_info->nb_tcs; i++) {
7150 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7151 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7153 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7154 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7155 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7156 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7157 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7158 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7159 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7160 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7161 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7162 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7163 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7164 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7165 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7166 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7167 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7168 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7171 for (i = 0; i < dcb_info->nb_tcs; i++) {
7172 tc = &dcb_config->tc_config[i];
7173 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7178 /* Update e-tag ether type */
7180 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7181 uint16_t ether_type)
7183 uint32_t etag_etype;
7185 if (hw->mac.type != ixgbe_mac_X550 &&
7186 hw->mac.type != ixgbe_mac_X550EM_x &&
7187 hw->mac.type != ixgbe_mac_X550EM_a) {
7191 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7192 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7193 etag_etype |= ether_type;
7194 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7195 IXGBE_WRITE_FLUSH(hw);
7200 /* Config l2 tunnel ether type */
7202 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7203 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7206 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7207 struct ixgbe_l2_tn_info *l2_tn_info =
7208 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7210 if (l2_tunnel == NULL)
7213 switch (l2_tunnel->l2_tunnel_type) {
7214 case RTE_L2_TUNNEL_TYPE_E_TAG:
7215 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7216 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7219 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7227 /* Enable e-tag tunnel */
7229 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7231 uint32_t etag_etype;
7233 if (hw->mac.type != ixgbe_mac_X550 &&
7234 hw->mac.type != ixgbe_mac_X550EM_x &&
7235 hw->mac.type != ixgbe_mac_X550EM_a) {
7239 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7240 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7241 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7242 IXGBE_WRITE_FLUSH(hw);
7247 /* Enable l2 tunnel */
7249 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7250 enum rte_eth_tunnel_type l2_tunnel_type)
7253 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7254 struct ixgbe_l2_tn_info *l2_tn_info =
7255 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7257 switch (l2_tunnel_type) {
7258 case RTE_L2_TUNNEL_TYPE_E_TAG:
7259 l2_tn_info->e_tag_en = TRUE;
7260 ret = ixgbe_e_tag_enable(hw);
7263 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7271 /* Disable e-tag tunnel */
7273 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7275 uint32_t etag_etype;
7277 if (hw->mac.type != ixgbe_mac_X550 &&
7278 hw->mac.type != ixgbe_mac_X550EM_x &&
7279 hw->mac.type != ixgbe_mac_X550EM_a) {
7283 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7284 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7285 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7286 IXGBE_WRITE_FLUSH(hw);
7291 /* Disable l2 tunnel */
7293 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7294 enum rte_eth_tunnel_type l2_tunnel_type)
7297 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7298 struct ixgbe_l2_tn_info *l2_tn_info =
7299 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7301 switch (l2_tunnel_type) {
7302 case RTE_L2_TUNNEL_TYPE_E_TAG:
7303 l2_tn_info->e_tag_en = FALSE;
7304 ret = ixgbe_e_tag_disable(hw);
7307 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7316 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7317 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7320 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7321 uint32_t i, rar_entries;
7322 uint32_t rar_low, rar_high;
7324 if (hw->mac.type != ixgbe_mac_X550 &&
7325 hw->mac.type != ixgbe_mac_X550EM_x &&
7326 hw->mac.type != ixgbe_mac_X550EM_a) {
7330 rar_entries = ixgbe_get_num_rx_addrs(hw);
7332 for (i = 1; i < rar_entries; i++) {
7333 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7334 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7335 if ((rar_high & IXGBE_RAH_AV) &&
7336 (rar_high & IXGBE_RAH_ADTYPE) &&
7337 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7338 l2_tunnel->tunnel_id)) {
7339 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7340 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7342 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7352 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7353 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7356 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7357 uint32_t i, rar_entries;
7358 uint32_t rar_low, rar_high;
7360 if (hw->mac.type != ixgbe_mac_X550 &&
7361 hw->mac.type != ixgbe_mac_X550EM_x &&
7362 hw->mac.type != ixgbe_mac_X550EM_a) {
7366 /* One entry for one tunnel. Try to remove potential existing entry. */
7367 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7369 rar_entries = ixgbe_get_num_rx_addrs(hw);
7371 for (i = 1; i < rar_entries; i++) {
7372 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7373 if (rar_high & IXGBE_RAH_AV) {
7376 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7377 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7378 rar_low = l2_tunnel->tunnel_id;
7380 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7381 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7387 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7388 " Please remove a rule before adding a new one.");
7392 static inline struct ixgbe_l2_tn_filter *
7393 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7394 struct ixgbe_l2_tn_key *key)
7398 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7402 return l2_tn_info->hash_map[ret];
7406 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7407 struct ixgbe_l2_tn_filter *l2_tn_filter)
7411 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7412 &l2_tn_filter->key);
7416 "Failed to insert L2 tunnel filter"
7417 " to hash table %d!",
7422 l2_tn_info->hash_map[ret] = l2_tn_filter;
7424 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7430 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7431 struct ixgbe_l2_tn_key *key)
7434 struct ixgbe_l2_tn_filter *l2_tn_filter;
7436 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7440 "No such L2 tunnel filter to delete %d!",
7445 l2_tn_filter = l2_tn_info->hash_map[ret];
7446 l2_tn_info->hash_map[ret] = NULL;
7448 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7449 rte_free(l2_tn_filter);
7454 /* Add l2 tunnel filter */
7456 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7457 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7461 struct ixgbe_l2_tn_info *l2_tn_info =
7462 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7463 struct ixgbe_l2_tn_key key;
7464 struct ixgbe_l2_tn_filter *node;
7467 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7468 key.tn_id = l2_tunnel->tunnel_id;
7470 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7474 "The L2 tunnel filter already exists!");
7478 node = rte_zmalloc("ixgbe_l2_tn",
7479 sizeof(struct ixgbe_l2_tn_filter),
7484 (void)rte_memcpy(&node->key,
7486 sizeof(struct ixgbe_l2_tn_key));
7487 node->pool = l2_tunnel->pool;
7488 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7495 switch (l2_tunnel->l2_tunnel_type) {
7496 case RTE_L2_TUNNEL_TYPE_E_TAG:
7497 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7500 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7505 if ((!restore) && (ret < 0))
7506 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7511 /* Delete l2 tunnel filter */
7513 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7514 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7517 struct ixgbe_l2_tn_info *l2_tn_info =
7518 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7519 struct ixgbe_l2_tn_key key;
7521 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7522 key.tn_id = l2_tunnel->tunnel_id;
7523 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7527 switch (l2_tunnel->l2_tunnel_type) {
7528 case RTE_L2_TUNNEL_TYPE_E_TAG:
7529 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7532 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7541 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7542 * @dev: pointer to rte_eth_dev structure
7543 * @filter_op:operation will be taken.
7544 * @arg: a pointer to specific structure corresponding to the filter_op
7547 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7548 enum rte_filter_op filter_op,
7553 if (filter_op == RTE_ETH_FILTER_NOP)
7557 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7562 switch (filter_op) {
7563 case RTE_ETH_FILTER_ADD:
7564 ret = ixgbe_dev_l2_tunnel_filter_add
7566 (struct rte_eth_l2_tunnel_conf *)arg,
7569 case RTE_ETH_FILTER_DELETE:
7570 ret = ixgbe_dev_l2_tunnel_filter_del
7572 (struct rte_eth_l2_tunnel_conf *)arg);
7575 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7583 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7587 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7589 if (hw->mac.type != ixgbe_mac_X550 &&
7590 hw->mac.type != ixgbe_mac_X550EM_x &&
7591 hw->mac.type != ixgbe_mac_X550EM_a) {
7595 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7596 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7598 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7599 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7604 /* Enable l2 tunnel forwarding */
7606 ixgbe_dev_l2_tunnel_forwarding_enable
7607 (struct rte_eth_dev *dev,
7608 enum rte_eth_tunnel_type l2_tunnel_type)
7610 struct ixgbe_l2_tn_info *l2_tn_info =
7611 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7614 switch (l2_tunnel_type) {
7615 case RTE_L2_TUNNEL_TYPE_E_TAG:
7616 l2_tn_info->e_tag_fwd_en = TRUE;
7617 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7620 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7628 /* Disable l2 tunnel forwarding */
7630 ixgbe_dev_l2_tunnel_forwarding_disable
7631 (struct rte_eth_dev *dev,
7632 enum rte_eth_tunnel_type l2_tunnel_type)
7634 struct ixgbe_l2_tn_info *l2_tn_info =
7635 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7638 switch (l2_tunnel_type) {
7639 case RTE_L2_TUNNEL_TYPE_E_TAG:
7640 l2_tn_info->e_tag_fwd_en = FALSE;
7641 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7644 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7653 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7654 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7657 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7659 uint32_t vmtir, vmvir;
7660 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7662 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7664 "VF id %u should be less than %u",
7670 if (hw->mac.type != ixgbe_mac_X550 &&
7671 hw->mac.type != ixgbe_mac_X550EM_x &&
7672 hw->mac.type != ixgbe_mac_X550EM_a) {
7677 vmtir = l2_tunnel->tunnel_id;
7681 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7683 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7684 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7686 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7687 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7692 /* Enable l2 tunnel tag insertion */
7694 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7695 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7699 switch (l2_tunnel->l2_tunnel_type) {
7700 case RTE_L2_TUNNEL_TYPE_E_TAG:
7701 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7704 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7712 /* Disable l2 tunnel tag insertion */
7714 ixgbe_dev_l2_tunnel_insertion_disable
7715 (struct rte_eth_dev *dev,
7716 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7720 switch (l2_tunnel->l2_tunnel_type) {
7721 case RTE_L2_TUNNEL_TYPE_E_TAG:
7722 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7725 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7734 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7739 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7741 if (hw->mac.type != ixgbe_mac_X550 &&
7742 hw->mac.type != ixgbe_mac_X550EM_x &&
7743 hw->mac.type != ixgbe_mac_X550EM_a) {
7747 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7749 qde |= IXGBE_QDE_STRIP_TAG;
7751 qde &= ~IXGBE_QDE_STRIP_TAG;
7752 qde &= ~IXGBE_QDE_READ;
7753 qde |= IXGBE_QDE_WRITE;
7754 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7759 /* Enable l2 tunnel tag stripping */
7761 ixgbe_dev_l2_tunnel_stripping_enable
7762 (struct rte_eth_dev *dev,
7763 enum rte_eth_tunnel_type l2_tunnel_type)
7767 switch (l2_tunnel_type) {
7768 case RTE_L2_TUNNEL_TYPE_E_TAG:
7769 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7772 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7780 /* Disable l2 tunnel tag stripping */
7782 ixgbe_dev_l2_tunnel_stripping_disable
7783 (struct rte_eth_dev *dev,
7784 enum rte_eth_tunnel_type l2_tunnel_type)
7788 switch (l2_tunnel_type) {
7789 case RTE_L2_TUNNEL_TYPE_E_TAG:
7790 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7793 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7801 /* Enable/disable l2 tunnel offload functions */
7803 ixgbe_dev_l2_tunnel_offload_set
7804 (struct rte_eth_dev *dev,
7805 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7811 if (l2_tunnel == NULL)
7815 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7817 ret = ixgbe_dev_l2_tunnel_enable(
7819 l2_tunnel->l2_tunnel_type);
7821 ret = ixgbe_dev_l2_tunnel_disable(
7823 l2_tunnel->l2_tunnel_type);
7826 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7828 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7832 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7837 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7839 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7841 l2_tunnel->l2_tunnel_type);
7843 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7845 l2_tunnel->l2_tunnel_type);
7848 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7850 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7852 l2_tunnel->l2_tunnel_type);
7854 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7856 l2_tunnel->l2_tunnel_type);
7863 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7866 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7867 IXGBE_WRITE_FLUSH(hw);
7872 /* There's only one register for VxLAN UDP port.
7873 * So, we cannot add several ports. Will update it.
7876 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7880 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7884 return ixgbe_update_vxlan_port(hw, port);
7887 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7888 * UDP port, it must have a value.
7889 * So, will reset it to the original value 0.
7892 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7897 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7899 if (cur_port != port) {
7900 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7904 return ixgbe_update_vxlan_port(hw, 0);
7907 /* Add UDP tunneling port */
7909 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7910 struct rte_eth_udp_tunnel *udp_tunnel)
7913 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7915 if (hw->mac.type != ixgbe_mac_X550 &&
7916 hw->mac.type != ixgbe_mac_X550EM_x &&
7917 hw->mac.type != ixgbe_mac_X550EM_a) {
7921 if (udp_tunnel == NULL)
7924 switch (udp_tunnel->prot_type) {
7925 case RTE_TUNNEL_TYPE_VXLAN:
7926 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7929 case RTE_TUNNEL_TYPE_GENEVE:
7930 case RTE_TUNNEL_TYPE_TEREDO:
7931 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7936 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7944 /* Remove UDP tunneling port */
7946 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7947 struct rte_eth_udp_tunnel *udp_tunnel)
7950 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7952 if (hw->mac.type != ixgbe_mac_X550 &&
7953 hw->mac.type != ixgbe_mac_X550EM_x &&
7954 hw->mac.type != ixgbe_mac_X550EM_a) {
7958 if (udp_tunnel == NULL)
7961 switch (udp_tunnel->prot_type) {
7962 case RTE_TUNNEL_TYPE_VXLAN:
7963 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7965 case RTE_TUNNEL_TYPE_GENEVE:
7966 case RTE_TUNNEL_TYPE_TEREDO:
7967 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7971 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7980 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7982 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7984 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7988 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7990 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7992 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
7995 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8000 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8003 /* PF reset VF event */
8004 if (in_msg == IXGBE_PF_CONTROL_MSG)
8005 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8010 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8013 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8014 struct ixgbe_interrupt *intr =
8015 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8016 ixgbevf_intr_disable(hw);
8018 /* read-on-clear nic registers here */
8019 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8022 /* only one misc vector supported - mailbox */
8023 eicr &= IXGBE_VTEICR_MASK;
8024 if (eicr == IXGBE_MISC_VEC_ID)
8025 intr->flags |= IXGBE_FLAG_MAILBOX;
8031 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8033 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8034 struct ixgbe_interrupt *intr =
8035 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8037 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8038 ixgbevf_mbx_process(dev);
8039 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8042 ixgbevf_intr_enable(hw);
8048 ixgbevf_dev_interrupt_handler(void *param)
8050 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8052 ixgbevf_dev_interrupt_get_status(dev);
8053 ixgbevf_dev_interrupt_action(dev);
8057 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8058 * @hw: pointer to hardware structure
8060 * Stops the transmit data path and waits for the HW to internally empty
8061 * the Tx security block
8063 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8065 #define IXGBE_MAX_SECTX_POLL 40
8070 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8071 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8072 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8073 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8074 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8075 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8077 /* Use interrupt-safe sleep just in case */
8081 /* For informational purposes only */
8082 if (i >= IXGBE_MAX_SECTX_POLL)
8083 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8084 "path fully disabled. Continuing with init.");
8086 return IXGBE_SUCCESS;
8090 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8091 * @hw: pointer to hardware structure
8093 * Enables the transmit data path.
8095 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8099 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8100 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8101 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8102 IXGBE_WRITE_FLUSH(hw);
8104 return IXGBE_SUCCESS;
8107 /* restore n-tuple filter */
8109 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8111 struct ixgbe_filter_info *filter_info =
8112 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8113 struct ixgbe_5tuple_filter *node;
8115 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8116 ixgbe_inject_5tuple_filter(dev, node);
8120 /* restore ethernet type filter */
8122 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8124 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8125 struct ixgbe_filter_info *filter_info =
8126 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8129 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8130 if (filter_info->ethertype_mask & (1 << i)) {
8131 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8132 filter_info->ethertype_filters[i].etqf);
8133 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8134 filter_info->ethertype_filters[i].etqs);
8135 IXGBE_WRITE_FLUSH(hw);
8140 /* restore SYN filter */
8142 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8144 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8145 struct ixgbe_filter_info *filter_info =
8146 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8149 synqf = filter_info->syn_info;
8151 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8152 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8153 IXGBE_WRITE_FLUSH(hw);
8157 /* restore L2 tunnel filter */
8159 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8161 struct ixgbe_l2_tn_info *l2_tn_info =
8162 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8163 struct ixgbe_l2_tn_filter *node;
8164 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8166 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8167 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8168 l2_tn_conf.tunnel_id = node->key.tn_id;
8169 l2_tn_conf.pool = node->pool;
8170 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8175 ixgbe_filter_restore(struct rte_eth_dev *dev)
8177 ixgbe_ntuple_filter_restore(dev);
8178 ixgbe_ethertype_filter_restore(dev);
8179 ixgbe_syn_filter_restore(dev);
8180 ixgbe_fdir_filter_restore(dev);
8181 ixgbe_l2_tn_filter_restore(dev);
8187 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8189 struct ixgbe_l2_tn_info *l2_tn_info =
8190 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8191 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8193 if (l2_tn_info->e_tag_en)
8194 (void)ixgbe_e_tag_enable(hw);
8196 if (l2_tn_info->e_tag_fwd_en)
8197 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8199 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8202 /* remove all the n-tuple filters */
8204 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8206 struct ixgbe_filter_info *filter_info =
8207 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8208 struct ixgbe_5tuple_filter *p_5tuple;
8210 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8211 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8214 /* remove all the ether type filters */
8216 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8218 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8219 struct ixgbe_filter_info *filter_info =
8220 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8223 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8224 if (filter_info->ethertype_mask & (1 << i) &&
8225 !filter_info->ethertype_filters[i].conf) {
8226 (void)ixgbe_ethertype_filter_remove(filter_info,
8228 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8229 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8230 IXGBE_WRITE_FLUSH(hw);
8235 /* remove the SYN filter */
8237 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8239 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8240 struct ixgbe_filter_info *filter_info =
8241 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8243 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8244 filter_info->syn_info = 0;
8246 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8247 IXGBE_WRITE_FLUSH(hw);
8251 /* remove all the L2 tunnel filters */
8253 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8255 struct ixgbe_l2_tn_info *l2_tn_info =
8256 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8257 struct ixgbe_l2_tn_filter *l2_tn_filter;
8258 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8261 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8262 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8263 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8264 l2_tn_conf.pool = l2_tn_filter->pool;
8265 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8273 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8274 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8275 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8276 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8277 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8278 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");