drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <rte_string_fns.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_kvargs.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <ethdev_driver.h>
  30 #include <ethdev_pci.h>
  31 #include <rte_malloc.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_hash_crc.h>
  35 #ifdef RTE_LIB_SECURITY
  36 #include <rte_security_driver.h>
  37 #endif
  38
  39 #include "ixgbe_logs.h"
  40 #include "base/ixgbe_api.h"
  41 #include "base/ixgbe_vf.h"
  42 #include "base/ixgbe_common.h"
  43 #include "ixgbe_ethdev.h"
  44 #include "ixgbe_bypass.h"
  45 #include "ixgbe_rxtx.h"
  46 #include "base/ixgbe_type.h"
  47 #include "base/ixgbe_phy.h"
  48 #include "base/ixgbe_osdep.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         const uint64_t *ids,
 177         struct rte_eth_xstat_name *xstats_names,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 285                                           uint16_t queue_id);
 286 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 287                                            uint16_t queue_id);
 288 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 289                                uint8_t queue, uint8_t msix_vector);
 290 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 291
 292 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 293                                 struct rte_ether_addr *mac_addr,
 294                                 uint32_t index, uint32_t pool);
 295 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 296 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 297                                              struct rte_ether_addr *mac_addr);
 298 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 301                         struct ixgbe_5tuple_filter *filter);
 302 static int ixgbe_dev_flow_ops_get(struct rte_eth_dev *dev,
 303                                   const struct rte_flow_ops **ops);
 304 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 305
 306 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 307                                       struct rte_ether_addr *mc_addr_set,
 308                                       uint32_t nb_mc_addr);
 309 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 310                                    struct rte_eth_dcb_info *dcb_info);
 311
 312 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 313 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 314                             struct rte_dev_reg_info *regs);
 315 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 316 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 317                                 struct rte_dev_eeprom_info *eeprom);
 318 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 319                                 struct rte_dev_eeprom_info *eeprom);
 320
 321 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 322                                  struct rte_eth_dev_module_info *modinfo);
 323 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 324                                    struct rte_dev_eeprom_info *info);
 325
 326 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 327 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 328                                 struct rte_dev_reg_info *regs);
 329
 330 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 331 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 332 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 333                                             struct timespec *timestamp,
 334                                             uint32_t flags);
 335 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 336                                             struct timespec *timestamp);
 337 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 338 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 339                                    struct timespec *timestamp);
 340 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 341                                    const struct timespec *timestamp);
 342 static void ixgbevf_dev_interrupt_handler(void *param);
 343
 344 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 345                                          struct rte_eth_udp_tunnel *udp_tunnel);
 346 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 347                                          struct rte_eth_udp_tunnel *udp_tunnel);
 348 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 349 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 350 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 351
 352 /*
 353  * Define VF Stats MACRO for Non "cleared on read" register
 354  */
 355 #define UPDATE_VF_STAT(reg, last, cur)                          \
 356 {                                                               \
 357         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 358         cur += (latest - last) & UINT_MAX;                      \
 359         last = latest;                                          \
 360 }
 361
 362 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 363 {                                                                \
 364         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 365         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 366         u64 latest = ((new_msb << 32) | new_lsb);                \
 367         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 368         last = latest;                                           \
 369 }
 370
 371 #define IXGBE_SET_HWSTRIP(h, q) do {\
 372                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 373                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 374                 (h)->bitmap[idx] |= 1 << bit;\
 375         } while (0)
 376
 377 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 378                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 379                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 380                 (h)->bitmap[idx] &= ~(1 << bit);\
 381         } while (0)
 382
 383 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 384                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 385                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 386                 (r) = (h)->bitmap[idx] >> bit & 1;\
 387         } while (0)
 388
 389 /*
 390  * The set of PCI devices this driver supports
 391  */
 392 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 393         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 394         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 395         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 396         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 397         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 398         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 399         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 400         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 401         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 402         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 403         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 404         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 405         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 406         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 407         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 408         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 441 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 443 #endif
 444         { .vendor_id = 0, /* sentinel */ },
 445 };
 446
 447 /*
 448  * The set of PCI devices this driver supports (for 82599 VF)
 449  */
 450 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 461         { .vendor_id = 0, /* sentinel */ },
 462 };
 463
 464 static const struct rte_eth_desc_lim rx_desc_lim = {
 465         .nb_max = IXGBE_MAX_RING_DESC,
 466         .nb_min = IXGBE_MIN_RING_DESC,
 467         .nb_align = IXGBE_RXD_ALIGN,
 468 };
 469
 470 static const struct rte_eth_desc_lim tx_desc_lim = {
 471         .nb_max = IXGBE_MAX_RING_DESC,
 472         .nb_min = IXGBE_MIN_RING_DESC,
 473         .nb_align = IXGBE_TXD_ALIGN,
 474         .nb_seg_max = IXGBE_TX_MAX_SEG,
 475         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 476 };
 477
 478 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 479         .dev_configure        = ixgbe_dev_configure,
 480         .dev_start            = ixgbe_dev_start,
 481         .dev_stop             = ixgbe_dev_stop,
 482         .dev_set_link_up    = ixgbe_dev_set_link_up,
 483         .dev_set_link_down  = ixgbe_dev_set_link_down,
 484         .dev_close            = ixgbe_dev_close,
 485         .dev_reset            = ixgbe_dev_reset,
 486         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 487         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 488         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 489         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 490         .link_update          = ixgbe_dev_link_update,
 491         .stats_get            = ixgbe_dev_stats_get,
 492         .xstats_get           = ixgbe_dev_xstats_get,
 493         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 494         .stats_reset          = ixgbe_dev_stats_reset,
 495         .xstats_reset         = ixgbe_dev_xstats_reset,
 496         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 497         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 498         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 499         .fw_version_get       = ixgbe_fw_version_get,
 500         .dev_infos_get        = ixgbe_dev_info_get,
 501         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 502         .mtu_set              = ixgbe_dev_mtu_set,
 503         .vlan_filter_set      = ixgbe_vlan_filter_set,
 504         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 505         .vlan_offload_set     = ixgbe_vlan_offload_set,
 506         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 507         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 508         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 509         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 510         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 511         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 512         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 513         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 514         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 515         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 516         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 517         .dev_led_on           = ixgbe_dev_led_on,
 518         .dev_led_off          = ixgbe_dev_led_off,
 519         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 520         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 521         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 522         .mac_addr_add         = ixgbe_add_rar,
 523         .mac_addr_remove      = ixgbe_remove_rar,
 524         .mac_addr_set         = ixgbe_set_default_mac_addr,
 525         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 526         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 527         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 528         .reta_update          = ixgbe_dev_rss_reta_update,
 529         .reta_query           = ixgbe_dev_rss_reta_query,
 530         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 531         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 532         .flow_ops_get         = ixgbe_dev_flow_ops_get,
 533         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 534         .rxq_info_get         = ixgbe_rxq_info_get,
 535         .txq_info_get         = ixgbe_txq_info_get,
 536         .timesync_enable      = ixgbe_timesync_enable,
 537         .timesync_disable     = ixgbe_timesync_disable,
 538         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 539         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 540         .get_reg              = ixgbe_get_regs,
 541         .get_eeprom_length    = ixgbe_get_eeprom_length,
 542         .get_eeprom           = ixgbe_get_eeprom,
 543         .set_eeprom           = ixgbe_set_eeprom,
 544         .get_module_info      = ixgbe_get_module_info,
 545         .get_module_eeprom    = ixgbe_get_module_eeprom,
 546         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 547         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 548         .timesync_read_time   = ixgbe_timesync_read_time,
 549         .timesync_write_time  = ixgbe_timesync_write_time,
 550         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 551         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 552         .tm_ops_get           = ixgbe_tm_ops_get,
 553         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 554         .get_monitor_addr     = ixgbe_get_monitor_addr,
 555 };
 556
 557 /*
 558  * dev_ops for virtual function, bare necessities for basic vf
 559  * operation have been implemented
 560  */
 561 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 562         .dev_configure        = ixgbevf_dev_configure,
 563         .dev_start            = ixgbevf_dev_start,
 564         .dev_stop             = ixgbevf_dev_stop,
 565         .link_update          = ixgbevf_dev_link_update,
 566         .stats_get            = ixgbevf_dev_stats_get,
 567         .xstats_get           = ixgbevf_dev_xstats_get,
 568         .stats_reset          = ixgbevf_dev_stats_reset,
 569         .xstats_reset         = ixgbevf_dev_stats_reset,
 570         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 571         .dev_close            = ixgbevf_dev_close,
 572         .dev_reset            = ixgbevf_dev_reset,
 573         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 574         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 575         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 576         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 577         .dev_infos_get        = ixgbevf_dev_info_get,
 578         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 579         .mtu_set              = ixgbevf_dev_set_mtu,
 580         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 581         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 582         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 583         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 584         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 585         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 586         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 587         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 588         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 589         .mac_addr_add         = ixgbevf_add_mac_addr,
 590         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 591         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 592         .rxq_info_get         = ixgbe_rxq_info_get,
 593         .txq_info_get         = ixgbe_txq_info_get,
 594         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 595         .get_reg              = ixgbevf_get_regs,
 596         .reta_update          = ixgbe_dev_rss_reta_update,
 597         .reta_query           = ixgbe_dev_rss_reta_query,
 598         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 599         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 600         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 601         .get_monitor_addr     = ixgbe_get_monitor_addr,
 602 };
 603
 604 /* store statistics names and its offset in stats structure */
 605 struct rte_ixgbe_xstats_name_off {
 606         char name[RTE_ETH_XSTATS_NAME_SIZE];
 607         unsigned offset;
 608 };
 609
 610 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 611         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 612         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 613         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 614         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 615         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 616         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 617         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 618         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 619         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 620         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 621         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 622         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 623         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 624         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 625         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 626                 prc1023)},
 627         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 628                 prc1522)},
 629         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 630         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 631         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 632         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 633         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 634         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 635         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 636         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 637         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 638         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 639         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 640         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 641         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 642         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 643         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 644         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 645         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 646                 ptc1023)},
 647         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 648                 ptc1522)},
 649         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 650         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 651         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 652         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 653
 654         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 655                 fdirustat_add)},
 656         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 657                 fdirustat_remove)},
 658         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 659                 fdirfstat_fadd)},
 660         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 661                 fdirfstat_fremove)},
 662         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 663                 fdirmatch)},
 664         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 665                 fdirmiss)},
 666
 667         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 668         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 669         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 670                 fclast)},
 671         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 672         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 673         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 674         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 675         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 676                 fcoe_noddp)},
 677         {"rx_fcoe_no_direct_data_placement_ext_buff",
 678                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 679
 680         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 681                 lxontxc)},
 682         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 683                 lxonrxc)},
 684         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 685                 lxofftxc)},
 686         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 687                 lxoffrxc)},
 688         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 689 };
 690
 691 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 692                            sizeof(rte_ixgbe_stats_strings[0]))
 693
 694 /* MACsec statistics */
 695 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 696         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 697                 out_pkts_untagged)},
 698         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 699                 out_pkts_encrypted)},
 700         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 701                 out_pkts_protected)},
 702         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 703                 out_octets_encrypted)},
 704         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 705                 out_octets_protected)},
 706         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 707                 in_pkts_untagged)},
 708         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 709                 in_pkts_badtag)},
 710         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 711                 in_pkts_nosci)},
 712         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 713                 in_pkts_unknownsci)},
 714         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 715                 in_octets_decrypted)},
 716         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 717                 in_octets_validated)},
 718         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 719                 in_pkts_unchecked)},
 720         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 721                 in_pkts_delayed)},
 722         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 723                 in_pkts_late)},
 724         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 725                 in_pkts_ok)},
 726         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_invalid)},
 728         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_notvalid)},
 730         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_unusedsa)},
 732         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_notusingsa)},
 734 };
 735
 736 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 737                            sizeof(rte_ixgbe_macsec_strings[0]))
 738
 739 /* Per-queue statistics */
 740 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 741         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 742         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 743         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 744         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 745 };
 746
 747 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 748                            sizeof(rte_ixgbe_rxq_strings[0]))
 749 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 750
 751 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 752         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 753         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 754         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 755                 pxon2offc)},
 756 };
 757
 758 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 759                            sizeof(rte_ixgbe_txq_strings[0]))
 760 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 761
 762 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 763         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 764 };
 765
 766 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 767                 sizeof(rte_ixgbevf_stats_strings[0]))
 768
 769 /*
 770  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 771  */
 772 static inline int
 773 ixgbe_is_sfp(struct ixgbe_hw *hw)
 774 {
 775         switch (hw->phy.type) {
 776         case ixgbe_phy_sfp_avago:
 777         case ixgbe_phy_sfp_ftl:
 778         case ixgbe_phy_sfp_intel:
 779         case ixgbe_phy_sfp_unknown:
 780         case ixgbe_phy_sfp_passive_tyco:
 781         case ixgbe_phy_sfp_passive_unknown:
 782                 return 1;
 783         default:
 784                 return 0;
 785         }
 786 }
 787
 788 static inline int32_t
 789 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 790 {
 791         uint32_t ctrl_ext;
 792         int32_t status;
 793
 794         status = ixgbe_reset_hw(hw);
 795
 796         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 797         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 798         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 799         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 800         IXGBE_WRITE_FLUSH(hw);
 801
 802         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 803                 status = IXGBE_SUCCESS;
 804         return status;
 805 }
 806
 807 static inline void
 808 ixgbe_enable_intr(struct rte_eth_dev *dev)
 809 {
 810         struct ixgbe_interrupt *intr =
 811                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 812         struct ixgbe_hw *hw =
 813                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 814
 815         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 816         IXGBE_WRITE_FLUSH(hw);
 817 }
 818
 819 /*
 820  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 821  */
 822 static void
 823 ixgbe_disable_intr(struct ixgbe_hw *hw)
 824 {
 825         PMD_INIT_FUNC_TRACE();
 826
 827         if (hw->mac.type == ixgbe_mac_82598EB) {
 828                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 829         } else {
 830                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 831                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 832                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 833         }
 834         IXGBE_WRITE_FLUSH(hw);
 835 }
 836
 837 /*
 838  * This function resets queue statistics mapping registers.
 839  * From Niantic datasheet, Initialization of Statistics section:
 840  * "...if software requires the queue counters, the RQSMR and TQSM registers
 841  * must be re-programmed following a device reset.
 842  */
 843 static void
 844 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 845 {
 846         uint32_t i;
 847
 848         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 849                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 850                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 851         }
 852 }
 853
 854
 855 static int
 856 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 857                                   uint16_t queue_id,
 858                                   uint8_t stat_idx,
 859                                   uint8_t is_rx)
 860 {
 861 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 862 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 863 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 864
 865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 866         struct ixgbe_stat_mapping_registers *stat_mappings =
 867                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 868         uint32_t qsmr_mask = 0;
 869         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 870         uint32_t q_map;
 871         uint8_t n, offset;
 872
 873         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 874                 (hw->mac.type != ixgbe_mac_X540) &&
 875                 (hw->mac.type != ixgbe_mac_X550) &&
 876                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 877                 (hw->mac.type != ixgbe_mac_X550EM_a))
 878                 return -ENOSYS;
 879
 880         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 881                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 882                      queue_id, stat_idx);
 883
 884         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 885         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 886                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 887                 return -EIO;
 888         }
 889         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 890
 891         /* Now clear any previous stat_idx set */
 892         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 893         if (!is_rx)
 894                 stat_mappings->tqsm[n] &= ~clearing_mask;
 895         else
 896                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 897
 898         q_map = (uint32_t)stat_idx;
 899         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 900         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 901         if (!is_rx)
 902                 stat_mappings->tqsm[n] |= qsmr_mask;
 903         else
 904                 stat_mappings->rqsmr[n] |= qsmr_mask;
 905
 906         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 907                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 908                      queue_id, stat_idx);
 909         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 910                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 911
 912         /* Now write the mapping in the appropriate register */
 913         if (is_rx) {
 914                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 915                              stat_mappings->rqsmr[n], n);
 916                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 917         } else {
 918                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 919                              stat_mappings->tqsm[n], n);
 920                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 921         }
 922         return 0;
 923 }
 924
 925 static void
 926 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 927 {
 928         struct ixgbe_stat_mapping_registers *stat_mappings =
 929                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 930         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 931         int i;
 932
 933         /* write whatever was in stat mapping table to the NIC */
 934         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 935                 /* rx */
 936                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 937
 938                 /* tx */
 939                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 940         }
 941 }
 942
 943 static void
 944 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 945 {
 946         uint8_t i;
 947         struct ixgbe_dcb_tc_config *tc;
 948         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 949
 950         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 951         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 952         for (i = 0; i < dcb_max_tc; i++) {
 953                 tc = &dcb_config->tc_config[i];
 954                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 955                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 956                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 957                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 958                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 959                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 960                 tc->pfc = ixgbe_dcb_pfc_disabled;
 961         }
 962
 963         /* Initialize default user to priority mapping, UPx->TC0 */
 964         tc = &dcb_config->tc_config[0];
 965         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 966         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 967         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 968                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 969                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 970         }
 971         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 972         dcb_config->pfc_mode_enable = false;
 973         dcb_config->vt_mode = true;
 974         dcb_config->round_robin_enable = false;
 975         /* support all DCB capabilities in 82599 */
 976         dcb_config->support.capabilities = 0xFF;
 977
 978         /*we only support 4 Tcs for X540, X550 */
 979         if (hw->mac.type == ixgbe_mac_X540 ||
 980                 hw->mac.type == ixgbe_mac_X550 ||
 981                 hw->mac.type == ixgbe_mac_X550EM_x ||
 982                 hw->mac.type == ixgbe_mac_X550EM_a) {
 983                 dcb_config->num_tcs.pg_tcs = 4;
 984                 dcb_config->num_tcs.pfc_tcs = 4;
 985         }
 986 }
 987
 988 /*
 989  * Ensure that all locks are released before first NVM or PHY access
 990  */
 991 static void
 992 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 993 {
 994         uint16_t mask;
 995
 996         /*
 997          * Phy lock should not fail in this early stage. If this is the case,
 998          * it is due to an improper exit of the application.
 999          * So force the release of the faulty lock. Release of common lock
1000          * is done automatically by swfw_sync function.
1001          */
1002         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1003         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1004                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1005         }
1006         ixgbe_release_swfw_semaphore(hw, mask);
1007
1008         /*
1009          * These ones are more tricky since they are common to all ports; but
1010          * swfw_sync retries last long enough (1s) to be almost sure that if
1011          * lock can not be taken it is due to an improper lock of the
1012          * semaphore.
1013          */
1014         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1015         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1016                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1017         }
1018         ixgbe_release_swfw_semaphore(hw, mask);
1019 }
1020
1021 /*
1022  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1023  * It returns 0 on success.
1024  */
1025 static int
1026 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1027 {
1028         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1029         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1030         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1031         struct ixgbe_hw *hw =
1032                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1033         struct ixgbe_vfta *shadow_vfta =
1034                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1035         struct ixgbe_hwstrip *hwstrip =
1036                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1037         struct ixgbe_dcb_config *dcb_config =
1038                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1039         struct ixgbe_filter_info *filter_info =
1040                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1041         struct ixgbe_bw_conf *bw_conf =
1042                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1043         uint32_t ctrl_ext;
1044         uint16_t csum;
1045         int diag, i, ret;
1046
1047         PMD_INIT_FUNC_TRACE();
1048
1049         ixgbe_dev_macsec_setting_reset(eth_dev);
1050
1051         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1052         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1053         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1054         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1055         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1056         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1057         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1058         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1059
1060         /*
1061          * For secondary processes, we don't initialise any further as primary
1062          * has already done this work. Only check we don't need a different
1063          * RX and TX function.
1064          */
1065         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1066                 struct ixgbe_tx_queue *txq;
1067                 /* TX queue function in primary, set by last queue initialized
1068                  * Tx queue may not initialized by primary process
1069                  */
1070                 if (eth_dev->data->tx_queues) {
1071                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1072                         ixgbe_set_tx_function(eth_dev, txq);
1073                 } else {
1074                         /* Use default TX function if we get here */
1075                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1076                                      "Using default TX function.");
1077                 }
1078
1079                 ixgbe_set_rx_function(eth_dev);
1080
1081                 return 0;
1082         }
1083
1084         rte_atomic32_clear(&ad->link_thread_running);
1085         rte_eth_copy_pci_info(eth_dev, pci_dev);
1086         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1087
1088         /* Vendor and Device ID need to be set before init of shared code */
1089         hw->device_id = pci_dev->id.device_id;
1090         hw->vendor_id = pci_dev->id.vendor_id;
1091         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1092         hw->allow_unsupported_sfp = 1;
1093
1094         /* Initialize the shared code (base driver) */
1095 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1096         diag = ixgbe_bypass_init_shared_code(hw);
1097 #else
1098         diag = ixgbe_init_shared_code(hw);
1099 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1100
1101         if (diag != IXGBE_SUCCESS) {
1102                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1103                 return -EIO;
1104         }
1105
1106         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1107                 PMD_INIT_LOG(ERR, "\nERROR: "
1108                         "Firmware recovery mode detected. Limiting functionality.\n"
1109                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1110                         "User Guide for details on firmware recovery mode.");
1111                 return -EIO;
1112         }
1113
1114         /* pick up the PCI bus settings for reporting later */
1115         ixgbe_get_bus_info(hw);
1116
1117         /* Unlock any pending hardware semaphore */
1118         ixgbe_swfw_lock_reset(hw);
1119
1120 #ifdef RTE_LIB_SECURITY
1121         /* Initialize security_ctx only for primary process*/
1122         if (ixgbe_ipsec_ctx_create(eth_dev))
1123                 return -ENOMEM;
1124 #endif
1125
1126         /* Initialize DCB configuration*/
1127         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1128         ixgbe_dcb_init(hw, dcb_config);
1129         /* Get Hardware Flow Control setting */
1130         hw->fc.requested_mode = ixgbe_fc_none;
1131         hw->fc.current_mode = ixgbe_fc_none;
1132         hw->fc.pause_time = IXGBE_FC_PAUSE;
1133         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1134                 hw->fc.low_water[i] = IXGBE_FC_LO;
1135                 hw->fc.high_water[i] = IXGBE_FC_HI;
1136         }
1137         hw->fc.send_xon = 1;
1138
1139         /* Make sure we have a good EEPROM before we read from it */
1140         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1141         if (diag != IXGBE_SUCCESS) {
1142                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1143                 return -EIO;
1144         }
1145
1146 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1147         diag = ixgbe_bypass_init_hw(hw);
1148 #else
1149         diag = ixgbe_init_hw(hw);
1150 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1151
1152         /*
1153          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1154          * is called too soon after the kernel driver unbinding/binding occurs.
1155          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1156          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1157          * also called. See ixgbe_identify_phy_82599(). The reason for the
1158          * failure is not known, and only occuts when virtualisation features
1159          * are disabled in the bios. A delay of 100ms  was found to be enough by
1160          * trial-and-error, and is doubled to be safe.
1161          */
1162         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1163                 rte_delay_ms(200);
1164                 diag = ixgbe_init_hw(hw);
1165         }
1166
1167         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1168                 diag = IXGBE_SUCCESS;
1169
1170         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1171                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1172                              "LOM.  Please be aware there may be issues associated "
1173                              "with your hardware.");
1174                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1175                              "please contact your Intel or hardware representative "
1176                              "who provided you with this hardware.");
1177         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1178                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1179         if (diag) {
1180                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1181                 return -EIO;
1182         }
1183
1184         /* Reset the hw statistics */
1185         ixgbe_dev_stats_reset(eth_dev);
1186
1187         /* disable interrupt */
1188         ixgbe_disable_intr(hw);
1189
1190         /* reset mappings for queue statistics hw counters*/
1191         ixgbe_reset_qstat_mappings(hw);
1192
1193         /* Allocate memory for storing MAC addresses */
1194         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1195                                                hw->mac.num_rar_entries, 0);
1196         if (eth_dev->data->mac_addrs == NULL) {
1197                 PMD_INIT_LOG(ERR,
1198                              "Failed to allocate %u bytes needed to store "
1199                              "MAC addresses",
1200                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1201                 return -ENOMEM;
1202         }
1203         /* Copy the permanent MAC address */
1204         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1205                         &eth_dev->data->mac_addrs[0]);
1206
1207         /* Allocate memory for storing hash filter MAC addresses */
1208         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1209                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1210         if (eth_dev->data->hash_mac_addrs == NULL) {
1211                 PMD_INIT_LOG(ERR,
1212                              "Failed to allocate %d bytes needed to store MAC addresses",
1213                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1214                 rte_free(eth_dev->data->mac_addrs);
1215                 eth_dev->data->mac_addrs = NULL;
1216                 return -ENOMEM;
1217         }
1218
1219         /* initialize the vfta */
1220         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1221
1222         /* initialize the hw strip bitmap*/
1223         memset(hwstrip, 0, sizeof(*hwstrip));
1224
1225         /* initialize PF if max_vfs not zero */
1226         ret = ixgbe_pf_host_init(eth_dev);
1227         if (ret) {
1228                 rte_free(eth_dev->data->mac_addrs);
1229                 eth_dev->data->mac_addrs = NULL;
1230                 rte_free(eth_dev->data->hash_mac_addrs);
1231                 eth_dev->data->hash_mac_addrs = NULL;
1232                 return ret;
1233         }
1234
1235         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1236         /* let hardware know driver is loaded */
1237         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1238         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1239         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1240         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1241         IXGBE_WRITE_FLUSH(hw);
1242
1243         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1244                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1245                              (int) hw->mac.type, (int) hw->phy.type,
1246                              (int) hw->phy.sfp_type);
1247         else
1248                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1249                              (int) hw->mac.type, (int) hw->phy.type);
1250
1251         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1252                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1253                      pci_dev->id.device_id);
1254
1255         rte_intr_callback_register(intr_handle,
1256                                    ixgbe_dev_interrupt_handler, eth_dev);
1257
1258         /* enable uio/vfio intr/eventfd mapping */
1259         rte_intr_enable(intr_handle);
1260
1261         /* enable support intr */
1262         ixgbe_enable_intr(eth_dev);
1263
1264         /* initialize filter info */
1265         memset(filter_info, 0,
1266                sizeof(struct ixgbe_filter_info));
1267
1268         /* initialize 5tuple filter list */
1269         TAILQ_INIT(&filter_info->fivetuple_list);
1270
1271         /* initialize flow director filter list & hash */
1272         ixgbe_fdir_filter_init(eth_dev);
1273
1274         /* initialize l2 tunnel filter list & hash */
1275         ixgbe_l2_tn_filter_init(eth_dev);
1276
1277         /* initialize flow filter lists */
1278         ixgbe_filterlist_init();
1279
1280         /* initialize bandwidth configuration info */
1281         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1282
1283         /* initialize Traffic Manager configuration */
1284         ixgbe_tm_conf_init(eth_dev);
1285
1286         return 0;
1287 }
1288
1289 static int
1290 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1291 {
1292         PMD_INIT_FUNC_TRACE();
1293
1294         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1295                 return 0;
1296
1297         ixgbe_dev_close(eth_dev);
1298
1299         return 0;
1300 }
1301
1302 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1303 {
1304         struct ixgbe_filter_info *filter_info =
1305                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1306         struct ixgbe_5tuple_filter *p_5tuple;
1307
1308         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1309                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1310                              p_5tuple,
1311                              entries);
1312                 rte_free(p_5tuple);
1313         }
1314         memset(filter_info->fivetuple_mask, 0,
1315                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1316
1317         return 0;
1318 }
1319
1320 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1321 {
1322         struct ixgbe_hw_fdir_info *fdir_info =
1323                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1324         struct ixgbe_fdir_filter *fdir_filter;
1325
1326                 if (fdir_info->hash_map)
1327                 rte_free(fdir_info->hash_map);
1328         if (fdir_info->hash_handle)
1329                 rte_hash_free(fdir_info->hash_handle);
1330
1331         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1332                 TAILQ_REMOVE(&fdir_info->fdir_list,
1333                              fdir_filter,
1334                              entries);
1335                 rte_free(fdir_filter);
1336         }
1337
1338         return 0;
1339 }
1340
1341 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1342 {
1343         struct ixgbe_l2_tn_info *l2_tn_info =
1344                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1345         struct ixgbe_l2_tn_filter *l2_tn_filter;
1346
1347         if (l2_tn_info->hash_map)
1348                 rte_free(l2_tn_info->hash_map);
1349         if (l2_tn_info->hash_handle)
1350                 rte_hash_free(l2_tn_info->hash_handle);
1351
1352         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1353                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1354                              l2_tn_filter,
1355                              entries);
1356                 rte_free(l2_tn_filter);
1357         }
1358
1359         return 0;
1360 }
1361
1362 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1363 {
1364         struct ixgbe_hw_fdir_info *fdir_info =
1365                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1366         char fdir_hash_name[RTE_HASH_NAMESIZE];
1367         struct rte_hash_parameters fdir_hash_params = {
1368                 .name = fdir_hash_name,
1369                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1370                 .key_len = sizeof(union ixgbe_atr_input),
1371                 .hash_func = rte_hash_crc,
1372                 .hash_func_init_val = 0,
1373                 .socket_id = rte_socket_id(),
1374         };
1375
1376         TAILQ_INIT(&fdir_info->fdir_list);
1377         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1378                  "fdir_%s", eth_dev->device->name);
1379         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1380         if (!fdir_info->hash_handle) {
1381                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1382                 return -EINVAL;
1383         }
1384         fdir_info->hash_map = rte_zmalloc("ixgbe",
1385                                           sizeof(struct ixgbe_fdir_filter *) *
1386                                           IXGBE_MAX_FDIR_FILTER_NUM,
1387                                           0);
1388         if (!fdir_info->hash_map) {
1389                 PMD_INIT_LOG(ERR,
1390                              "Failed to allocate memory for fdir hash map!");
1391                 rte_hash_free(fdir_info->hash_handle);
1392                 return -ENOMEM;
1393         }
1394         fdir_info->mask_added = FALSE;
1395
1396         return 0;
1397 }
1398
1399 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1400 {
1401         struct ixgbe_l2_tn_info *l2_tn_info =
1402                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1403         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1404         struct rte_hash_parameters l2_tn_hash_params = {
1405                 .name = l2_tn_hash_name,
1406                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1407                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1408                 .hash_func = rte_hash_crc,
1409                 .hash_func_init_val = 0,
1410                 .socket_id = rte_socket_id(),
1411         };
1412
1413         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1414         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1415                  "l2_tn_%s", eth_dev->device->name);
1416         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1417         if (!l2_tn_info->hash_handle) {
1418                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1419                 return -EINVAL;
1420         }
1421         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1422                                    sizeof(struct ixgbe_l2_tn_filter *) *
1423                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1424                                    0);
1425         if (!l2_tn_info->hash_map) {
1426                 PMD_INIT_LOG(ERR,
1427                         "Failed to allocate memory for L2 TN hash map!");
1428                 rte_hash_free(l2_tn_info->hash_handle);
1429                 return -ENOMEM;
1430         }
1431         l2_tn_info->e_tag_en = FALSE;
1432         l2_tn_info->e_tag_fwd_en = FALSE;
1433         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1434
1435         return 0;
1436 }
1437 /*
1438  * Negotiate mailbox API version with the PF.
1439  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1440  * Then we try to negotiate starting with the most recent one.
1441  * If all negotiation attempts fail, then we will proceed with
1442  * the default one (ixgbe_mbox_api_10).
1443  */
1444 static void
1445 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1446 {
1447         int32_t i;
1448
1449         /* start with highest supported, proceed down */
1450         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1451                 ixgbe_mbox_api_13,
1452                 ixgbe_mbox_api_12,
1453                 ixgbe_mbox_api_11,
1454                 ixgbe_mbox_api_10,
1455         };
1456
1457         for (i = 0;
1458                         i != RTE_DIM(sup_ver) &&
1459                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1460                         i++)
1461                 ;
1462 }
1463
1464 static void
1465 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1466 {
1467         uint64_t random;
1468
1469         /* Set Organizationally Unique Identifier (OUI) prefix. */
1470         mac_addr->addr_bytes[0] = 0x00;
1471         mac_addr->addr_bytes[1] = 0x09;
1472         mac_addr->addr_bytes[2] = 0xC0;
1473         /* Force indication of locally assigned MAC address. */
1474         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1475         /* Generate the last 3 bytes of the MAC address with a random number. */
1476         random = rte_rand();
1477         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1478 }
1479
1480 static int
1481 devarg_handle_int(__rte_unused const char *key, const char *value,
1482                   void *extra_args)
1483 {
1484         uint16_t *n = extra_args;
1485
1486         if (value == NULL || extra_args == NULL)
1487                 return -EINVAL;
1488
1489         *n = (uint16_t)strtoul(value, NULL, 0);
1490         if (*n == USHRT_MAX && errno == ERANGE)
1491                 return -1;
1492
1493         return 0;
1494 }
1495
1496 static void
1497 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1498                       struct rte_devargs *devargs)
1499 {
1500         struct rte_kvargs *kvlist;
1501         uint16_t pflink_fullchk;
1502
1503         if (devargs == NULL)
1504                 return;
1505
1506         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1507         if (kvlist == NULL)
1508                 return;
1509
1510         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1511             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1512                                devarg_handle_int, &pflink_fullchk) == 0 &&
1513             pflink_fullchk == 1)
1514                 adapter->pflink_fullchk = 1;
1515
1516         rte_kvargs_free(kvlist);
1517 }
1518
1519 /*
1520  * Virtual Function device init
1521  */
1522 static int
1523 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1524 {
1525         int diag;
1526         uint32_t tc, tcs;
1527         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1528         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1529         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1530         struct ixgbe_hw *hw =
1531                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1532         struct ixgbe_vfta *shadow_vfta =
1533                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1534         struct ixgbe_hwstrip *hwstrip =
1535                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1536         struct rte_ether_addr *perm_addr =
1537                 (struct rte_ether_addr *)hw->mac.perm_addr;
1538
1539         PMD_INIT_FUNC_TRACE();
1540
1541         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1542         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1543         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1544         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1545         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1546         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1547
1548         /* for secondary processes, we don't initialise any further as primary
1549          * has already done this work. Only check we don't need a different
1550          * RX function
1551          */
1552         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1553                 struct ixgbe_tx_queue *txq;
1554                 /* TX queue function in primary, set by last queue initialized
1555                  * Tx queue may not initialized by primary process
1556                  */
1557                 if (eth_dev->data->tx_queues) {
1558                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1559                         ixgbe_set_tx_function(eth_dev, txq);
1560                 } else {
1561                         /* Use default TX function if we get here */
1562                         PMD_INIT_LOG(NOTICE,
1563                                      "No TX queues configured yet. Using default TX function.");
1564                 }
1565
1566                 ixgbe_set_rx_function(eth_dev);
1567
1568                 return 0;
1569         }
1570
1571         rte_atomic32_clear(&ad->link_thread_running);
1572         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1573                               pci_dev->device.devargs);
1574
1575         rte_eth_copy_pci_info(eth_dev, pci_dev);
1576         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1577
1578         hw->device_id = pci_dev->id.device_id;
1579         hw->vendor_id = pci_dev->id.vendor_id;
1580         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1581
1582         /* initialize the vfta */
1583         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1584
1585         /* initialize the hw strip bitmap*/
1586         memset(hwstrip, 0, sizeof(*hwstrip));
1587
1588         /* Initialize the shared code (base driver) */
1589         diag = ixgbe_init_shared_code(hw);
1590         if (diag != IXGBE_SUCCESS) {
1591                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1592                 return -EIO;
1593         }
1594
1595         /* init_mailbox_params */
1596         hw->mbx.ops.init_params(hw);
1597
1598         /* Reset the hw statistics */
1599         ixgbevf_dev_stats_reset(eth_dev);
1600
1601         /* Disable the interrupts for VF */
1602         ixgbevf_intr_disable(eth_dev);
1603
1604         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1605         diag = hw->mac.ops.reset_hw(hw);
1606
1607         /*
1608          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1609          * the underlying PF driver has not assigned a MAC address to the VF.
1610          * In this case, assign a random MAC address.
1611          */
1612         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1613                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1614                 /*
1615                  * This error code will be propagated to the app by
1616                  * rte_eth_dev_reset, so use a public error code rather than
1617                  * the internal-only IXGBE_ERR_RESET_FAILED
1618                  */
1619                 return -EAGAIN;
1620         }
1621
1622         /* negotiate mailbox API version to use with the PF. */
1623         ixgbevf_negotiate_api(hw);
1624
1625         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1626         ixgbevf_get_queues(hw, &tcs, &tc);
1627
1628         /* Allocate memory for storing MAC addresses */
1629         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1630                                                hw->mac.num_rar_entries, 0);
1631         if (eth_dev->data->mac_addrs == NULL) {
1632                 PMD_INIT_LOG(ERR,
1633                              "Failed to allocate %u bytes needed to store "
1634                              "MAC addresses",
1635                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1636                 return -ENOMEM;
1637         }
1638
1639         /* Generate a random MAC address, if none was assigned by PF. */
1640         if (rte_is_zero_ether_addr(perm_addr)) {
1641                 generate_random_mac_addr(perm_addr);
1642                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1643                 if (diag) {
1644                         rte_free(eth_dev->data->mac_addrs);
1645                         eth_dev->data->mac_addrs = NULL;
1646                         return diag;
1647                 }
1648                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1649                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1650                              RTE_ETHER_ADDR_PRT_FMT,
1651                                  RTE_ETHER_ADDR_BYTES(perm_addr));
1652         }
1653
1654         /* Copy the permanent MAC address */
1655         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1656
1657         /* reset the hardware with the new settings */
1658         diag = hw->mac.ops.start_hw(hw);
1659         switch (diag) {
1660         case  0:
1661                 break;
1662
1663         default:
1664                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1665                 rte_free(eth_dev->data->mac_addrs);
1666                 eth_dev->data->mac_addrs = NULL;
1667                 return -EIO;
1668         }
1669
1670         rte_intr_callback_register(intr_handle,
1671                                    ixgbevf_dev_interrupt_handler, eth_dev);
1672         rte_intr_enable(intr_handle);
1673         ixgbevf_intr_enable(eth_dev);
1674
1675         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1676                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1677                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1678
1679         return 0;
1680 }
1681
1682 /* Virtual Function device uninit */
1683
1684 static int
1685 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1686 {
1687         PMD_INIT_FUNC_TRACE();
1688
1689         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1690                 return 0;
1691
1692         ixgbevf_dev_close(eth_dev);
1693
1694         return 0;
1695 }
1696
1697 static int
1698 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1699                 struct rte_pci_device *pci_dev)
1700 {
1701         char name[RTE_ETH_NAME_MAX_LEN];
1702         struct rte_eth_dev *pf_ethdev;
1703         struct rte_eth_devargs eth_da;
1704         int i, retval;
1705
1706         if (pci_dev->device.devargs) {
1707                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1708                                 &eth_da);
1709                 if (retval)
1710                         return retval;
1711         } else
1712                 memset(&eth_da, 0, sizeof(eth_da));
1713
1714         if (eth_da.nb_representor_ports > 0 &&
1715             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
1716                 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
1717                             pci_dev->device.devargs->args);
1718                 return -ENOTSUP;
1719         }
1720
1721         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1722                 sizeof(struct ixgbe_adapter),
1723                 eth_dev_pci_specific_init, pci_dev,
1724                 eth_ixgbe_dev_init, NULL);
1725
1726         if (retval || eth_da.nb_representor_ports < 1)
1727                 return retval;
1728
1729         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1730         if (pf_ethdev == NULL)
1731                 return -ENODEV;
1732
1733         /* probe VF representor ports */
1734         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1735                 struct ixgbe_vf_info *vfinfo;
1736                 struct ixgbe_vf_representor representor;
1737
1738                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1739                         pf_ethdev->data->dev_private);
1740                 if (vfinfo == NULL) {
1741                         PMD_DRV_LOG(ERR,
1742                                 "no virtual functions supported by PF");
1743                         break;
1744                 }
1745
1746                 representor.vf_id = eth_da.representor_ports[i];
1747                 representor.switch_domain_id = vfinfo->switch_domain_id;
1748                 representor.pf_ethdev = pf_ethdev;
1749
1750                 /* representor port net_bdf_port */
1751                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1752                         pci_dev->device.name,
1753                         eth_da.representor_ports[i]);
1754
1755                 retval = rte_eth_dev_create(&pci_dev->device, name,
1756                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1757                         ixgbe_vf_representor_init, &representor);
1758
1759                 if (retval)
1760                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1761                                 "representor %s.", name);
1762         }
1763
1764         return 0;
1765 }
1766
1767 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1768 {
1769         struct rte_eth_dev *ethdev;
1770
1771         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1772         if (!ethdev)
1773                 return 0;
1774
1775         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1776                 return rte_eth_dev_pci_generic_remove(pci_dev,
1777                                         ixgbe_vf_representor_uninit);
1778         else
1779                 return rte_eth_dev_pci_generic_remove(pci_dev,
1780                                                 eth_ixgbe_dev_uninit);
1781 }
1782
1783 static struct rte_pci_driver rte_ixgbe_pmd = {
1784         .id_table = pci_id_ixgbe_map,
1785         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1786         .probe = eth_ixgbe_pci_probe,
1787         .remove = eth_ixgbe_pci_remove,
1788 };
1789
1790 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1791         struct rte_pci_device *pci_dev)
1792 {
1793         return rte_eth_dev_pci_generic_probe(pci_dev,
1794                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1795 }
1796
1797 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1798 {
1799         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1800 }
1801
1802 /*
1803  * virtual function driver struct
1804  */
1805 static struct rte_pci_driver rte_ixgbevf_pmd = {
1806         .id_table = pci_id_ixgbevf_map,
1807         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1808         .probe = eth_ixgbevf_pci_probe,
1809         .remove = eth_ixgbevf_pci_remove,
1810 };
1811
1812 static int
1813 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1814 {
1815         struct ixgbe_hw *hw =
1816                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1817         struct ixgbe_vfta *shadow_vfta =
1818                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1819         uint32_t vfta;
1820         uint32_t vid_idx;
1821         uint32_t vid_bit;
1822
1823         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1824         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1825         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1826         if (on)
1827                 vfta |= vid_bit;
1828         else
1829                 vfta &= ~vid_bit;
1830         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1831
1832         /* update local VFTA copy */
1833         shadow_vfta->vfta[vid_idx] = vfta;
1834
1835         return 0;
1836 }
1837
1838 static void
1839 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1840 {
1841         if (on)
1842                 ixgbe_vlan_hw_strip_enable(dev, queue);
1843         else
1844                 ixgbe_vlan_hw_strip_disable(dev, queue);
1845 }
1846
1847 static int
1848 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1849                     enum rte_vlan_type vlan_type,
1850                     uint16_t tpid)
1851 {
1852         struct ixgbe_hw *hw =
1853                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1854         int ret = 0;
1855         uint32_t reg;
1856         uint32_t qinq;
1857
1858         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1859         qinq &= IXGBE_DMATXCTL_GDV;
1860
1861         switch (vlan_type) {
1862         case ETH_VLAN_TYPE_INNER:
1863                 if (qinq) {
1864                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1865                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1866                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1867                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1868                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1869                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1870                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1871                 } else {
1872                         ret = -ENOTSUP;
1873                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1874                                     " by single VLAN");
1875                 }
1876                 break;
1877         case ETH_VLAN_TYPE_OUTER:
1878                 if (qinq) {
1879                         /* Only the high 16-bits is valid */
1880                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1881                                         IXGBE_EXVET_VET_EXT_SHIFT);
1882                 } else {
1883                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1884                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1885                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1886                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1888                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1889                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1890                 }
1891
1892                 break;
1893         default:
1894                 ret = -EINVAL;
1895                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1896                 break;
1897         }
1898
1899         return ret;
1900 }
1901
1902 void
1903 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1904 {
1905         struct ixgbe_hw *hw =
1906                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1907         uint32_t vlnctrl;
1908
1909         PMD_INIT_FUNC_TRACE();
1910
1911         /* Filter Table Disable */
1912         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1913         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1914
1915         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1916 }
1917
1918 void
1919 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1920 {
1921         struct ixgbe_hw *hw =
1922                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923         struct ixgbe_vfta *shadow_vfta =
1924                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1925         uint32_t vlnctrl;
1926         uint16_t i;
1927
1928         PMD_INIT_FUNC_TRACE();
1929
1930         /* Filter Table Enable */
1931         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1932         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1933         vlnctrl |= IXGBE_VLNCTRL_VFE;
1934
1935         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1936
1937         /* write whatever is in local vfta copy */
1938         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1939                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1940 }
1941
1942 static void
1943 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1944 {
1945         struct ixgbe_hwstrip *hwstrip =
1946                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1947         struct ixgbe_rx_queue *rxq;
1948
1949         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1950                 return;
1951
1952         if (on)
1953                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1954         else
1955                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1956
1957         if (queue >= dev->data->nb_rx_queues)
1958                 return;
1959
1960         rxq = dev->data->rx_queues[queue];
1961
1962         if (on) {
1963                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1964                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1965         } else {
1966                 rxq->vlan_flags = PKT_RX_VLAN;
1967                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1968         }
1969 }
1970
1971 static void
1972 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1973 {
1974         struct ixgbe_hw *hw =
1975                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1976         uint32_t ctrl;
1977
1978         PMD_INIT_FUNC_TRACE();
1979
1980         if (hw->mac.type == ixgbe_mac_82598EB) {
1981                 /* No queue level support */
1982                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1983                 return;
1984         }
1985
1986         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1987         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1988         ctrl &= ~IXGBE_RXDCTL_VME;
1989         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1990
1991         /* record those setting for HW strip per queue */
1992         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1993 }
1994
1995 static void
1996 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1997 {
1998         struct ixgbe_hw *hw =
1999                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2000         uint32_t ctrl;
2001
2002         PMD_INIT_FUNC_TRACE();
2003
2004         if (hw->mac.type == ixgbe_mac_82598EB) {
2005                 /* No queue level supported */
2006                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2007                 return;
2008         }
2009
2010         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2011         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2012         ctrl |= IXGBE_RXDCTL_VME;
2013         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2014
2015         /* record those setting for HW strip per queue */
2016         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2017 }
2018
2019 static void
2020 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2021 {
2022         struct ixgbe_hw *hw =
2023                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024         uint32_t ctrl;
2025
2026         PMD_INIT_FUNC_TRACE();
2027
2028         /* DMATXCTRL: Geric Double VLAN Disable */
2029         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2030         ctrl &= ~IXGBE_DMATXCTL_GDV;
2031         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2032
2033         /* CTRL_EXT: Global Double VLAN Disable */
2034         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2035         ctrl &= ~IXGBE_EXTENDED_VLAN;
2036         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2037
2038 }
2039
2040 static void
2041 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2042 {
2043         struct ixgbe_hw *hw =
2044                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045         uint32_t ctrl;
2046
2047         PMD_INIT_FUNC_TRACE();
2048
2049         /* DMATXCTRL: Geric Double VLAN Enable */
2050         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2051         ctrl |= IXGBE_DMATXCTL_GDV;
2052         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2053
2054         /* CTRL_EXT: Global Double VLAN Enable */
2055         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2056         ctrl |= IXGBE_EXTENDED_VLAN;
2057         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2058
2059         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2060         if (hw->mac.type == ixgbe_mac_X550 ||
2061             hw->mac.type == ixgbe_mac_X550EM_x ||
2062             hw->mac.type == ixgbe_mac_X550EM_a) {
2063                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2064                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2065                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2066         }
2067
2068         /*
2069          * VET EXT field in the EXVET register = 0x8100 by default
2070          * So no need to change. Same to VT field of DMATXCTL register
2071          */
2072 }
2073
2074 void
2075 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2076 {
2077         struct ixgbe_hw *hw =
2078                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2080         uint32_t ctrl;
2081         uint16_t i;
2082         struct ixgbe_rx_queue *rxq;
2083         bool on;
2084
2085         PMD_INIT_FUNC_TRACE();
2086
2087         if (hw->mac.type == ixgbe_mac_82598EB) {
2088                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2089                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2090                         ctrl |= IXGBE_VLNCTRL_VME;
2091                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2092                 } else {
2093                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2094                         ctrl &= ~IXGBE_VLNCTRL_VME;
2095                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2096                 }
2097         } else {
2098                 /*
2099                  * Other 10G NIC, the VLAN strip can be setup
2100                  * per queue in RXDCTL
2101                  */
2102                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2103                         rxq = dev->data->rx_queues[i];
2104                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2105                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2106                                 ctrl |= IXGBE_RXDCTL_VME;
2107                                 on = TRUE;
2108                         } else {
2109                                 ctrl &= ~IXGBE_RXDCTL_VME;
2110                                 on = FALSE;
2111                         }
2112                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2113
2114                         /* record those setting for HW strip per queue */
2115                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2116                 }
2117         }
2118 }
2119
2120 static void
2121 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2122 {
2123         uint16_t i;
2124         struct rte_eth_rxmode *rxmode;
2125         struct ixgbe_rx_queue *rxq;
2126
2127         if (mask & ETH_VLAN_STRIP_MASK) {
2128                 rxmode = &dev->data->dev_conf.rxmode;
2129                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2130                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2131                                 rxq = dev->data->rx_queues[i];
2132                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2133                         }
2134                 else
2135                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2136                                 rxq = dev->data->rx_queues[i];
2137                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2138                         }
2139         }
2140 }
2141
2142 static int
2143 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2144 {
2145         struct rte_eth_rxmode *rxmode;
2146         rxmode = &dev->data->dev_conf.rxmode;
2147
2148         if (mask & ETH_VLAN_STRIP_MASK) {
2149                 ixgbe_vlan_hw_strip_config(dev);
2150         }
2151
2152         if (mask & ETH_VLAN_FILTER_MASK) {
2153                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2154                         ixgbe_vlan_hw_filter_enable(dev);
2155                 else
2156                         ixgbe_vlan_hw_filter_disable(dev);
2157         }
2158
2159         if (mask & ETH_VLAN_EXTEND_MASK) {
2160                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2161                         ixgbe_vlan_hw_extend_enable(dev);
2162                 else
2163                         ixgbe_vlan_hw_extend_disable(dev);
2164         }
2165
2166         return 0;
2167 }
2168
2169 static int
2170 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2171 {
2172         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2173
2174         ixgbe_vlan_offload_config(dev, mask);
2175
2176         return 0;
2177 }
2178
2179 static void
2180 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2181 {
2182         struct ixgbe_hw *hw =
2183                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2184         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2185         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2186
2187         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2188         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2189 }
2190
2191 static int
2192 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2193 {
2194         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2195
2196         switch (nb_rx_q) {
2197         case 1:
2198         case 2:
2199                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2200                 break;
2201         case 4:
2202                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2203                 break;
2204         default:
2205                 return -EINVAL;
2206         }
2207
2208         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2209                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2210         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2211                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2212         return 0;
2213 }
2214
2215 static int
2216 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2217 {
2218         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2219         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2221         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2222
2223         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2224                 /* check multi-queue mode */
2225                 switch (dev_conf->rxmode.mq_mode) {
2226                 case ETH_MQ_RX_VMDQ_DCB:
2227                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2228                         break;
2229                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2230                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2231                         PMD_INIT_LOG(ERR, "SRIOV active,"
2232                                         " unsupported mq_mode rx %d.",
2233                                         dev_conf->rxmode.mq_mode);
2234                         return -EINVAL;
2235                 case ETH_MQ_RX_RSS:
2236                 case ETH_MQ_RX_VMDQ_RSS:
2237                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2238                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2239                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2240                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2241                                                 " invalid queue number"
2242                                                 " for VMDQ RSS, allowed"
2243                                                 " value are 1, 2 or 4.");
2244                                         return -EINVAL;
2245                                 }
2246                         break;
2247                 case ETH_MQ_RX_VMDQ_ONLY:
2248                 case ETH_MQ_RX_NONE:
2249                         /* if nothing mq mode configure, use default scheme */
2250                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2251                         break;
2252                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2253                         /* SRIOV only works in VMDq enable mode */
2254                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2255                                         " wrong mq_mode rx %d.",
2256                                         dev_conf->rxmode.mq_mode);
2257                         return -EINVAL;
2258                 }
2259
2260                 switch (dev_conf->txmode.mq_mode) {
2261                 case ETH_MQ_TX_VMDQ_DCB:
2262                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2263                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2264                         break;
2265                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2266                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2267                         break;
2268                 }
2269
2270                 /* check valid queue number */
2271                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2272                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2273                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2274                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2275                                         " must be less than or equal to %d.",
2276                                         nb_rx_q, nb_tx_q,
2277                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2278                         return -EINVAL;
2279                 }
2280         } else {
2281                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2282                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2283                                           " not supported.");
2284                         return -EINVAL;
2285                 }
2286                 /* check configuration for vmdb+dcb mode */
2287                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2288                         const struct rte_eth_vmdq_dcb_conf *conf;
2289
2290                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2291                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2292                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2293                                 return -EINVAL;
2294                         }
2295                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2296                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2297                                conf->nb_queue_pools == ETH_32_POOLS)) {
2298                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2299                                                 " nb_queue_pools must be %d or %d.",
2300                                                 ETH_16_POOLS, ETH_32_POOLS);
2301                                 return -EINVAL;
2302                         }
2303                 }
2304                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2305                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2306
2307                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2308                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2309                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2310                                 return -EINVAL;
2311                         }
2312                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2313                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2314                                conf->nb_queue_pools == ETH_32_POOLS)) {
2315                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2316                                                 " nb_queue_pools != %d and"
2317                                                 " nb_queue_pools != %d.",
2318                                                 ETH_16_POOLS, ETH_32_POOLS);
2319                                 return -EINVAL;
2320                         }
2321                 }
2322
2323                 /* For DCB mode check our configuration before we go further */
2324                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2325                         const struct rte_eth_dcb_rx_conf *conf;
2326
2327                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2328                         if (!(conf->nb_tcs == ETH_4_TCS ||
2329                                conf->nb_tcs == ETH_8_TCS)) {
2330                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2331                                                 " and nb_tcs != %d.",
2332                                                 ETH_4_TCS, ETH_8_TCS);
2333                                 return -EINVAL;
2334                         }
2335                 }
2336
2337                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2338                         const struct rte_eth_dcb_tx_conf *conf;
2339
2340                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2341                         if (!(conf->nb_tcs == ETH_4_TCS ||
2342                                conf->nb_tcs == ETH_8_TCS)) {
2343                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2344                                                 " and nb_tcs != %d.",
2345                                                 ETH_4_TCS, ETH_8_TCS);
2346                                 return -EINVAL;
2347                         }
2348                 }
2349
2350                 /*
2351                  * When DCB/VT is off, maximum number of queues changes,
2352                  * except for 82598EB, which remains constant.
2353                  */
2354                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2355                                 hw->mac.type != ixgbe_mac_82598EB) {
2356                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2357                                 PMD_INIT_LOG(ERR,
2358                                              "Neither VT nor DCB are enabled, "
2359                                              "nb_tx_q > %d.",
2360                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2361                                 return -EINVAL;
2362                         }
2363                 }
2364         }
2365         return 0;
2366 }
2367
2368 static int
2369 ixgbe_dev_configure(struct rte_eth_dev *dev)
2370 {
2371         struct ixgbe_interrupt *intr =
2372                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2373         struct ixgbe_adapter *adapter = dev->data->dev_private;
2374         int ret;
2375
2376         PMD_INIT_FUNC_TRACE();
2377
2378         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2379                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2380
2381         /* multipe queue mode checking */
2382         ret  = ixgbe_check_mq_mode(dev);
2383         if (ret != 0) {
2384                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2385                             ret);
2386                 return ret;
2387         }
2388
2389         /* set flag to update link status after init */
2390         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2391
2392         /*
2393          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2394          * allocation or vector Rx preconditions we will reset it.
2395          */
2396         adapter->rx_bulk_alloc_allowed = true;
2397         adapter->rx_vec_allowed = true;
2398
2399         return 0;
2400 }
2401
2402 static void
2403 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2404 {
2405         struct ixgbe_hw *hw =
2406                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407         struct ixgbe_interrupt *intr =
2408                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2409         uint32_t gpie;
2410
2411         /* only set up it on X550EM_X */
2412         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2413                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2414                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2415                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2416                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2417                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2418         }
2419 }
2420
2421 int
2422 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2423                         uint16_t tx_rate, uint64_t q_msk)
2424 {
2425         struct ixgbe_hw *hw;
2426         struct ixgbe_vf_info *vfinfo;
2427         struct rte_eth_link link;
2428         uint8_t  nb_q_per_pool;
2429         uint32_t queue_stride;
2430         uint32_t queue_idx, idx = 0, vf_idx;
2431         uint32_t queue_end;
2432         uint16_t total_rate = 0;
2433         struct rte_pci_device *pci_dev;
2434         int ret;
2435
2436         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2437         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2438         if (ret < 0)
2439                 return ret;
2440
2441         if (vf >= pci_dev->max_vfs)
2442                 return -EINVAL;
2443
2444         if (tx_rate > link.link_speed)
2445                 return -EINVAL;
2446
2447         if (q_msk == 0)
2448                 return 0;
2449
2450         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2451         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2452         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2453         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2454         queue_idx = vf * queue_stride;
2455         queue_end = queue_idx + nb_q_per_pool - 1;
2456         if (queue_end >= hw->mac.max_tx_queues)
2457                 return -EINVAL;
2458
2459         if (vfinfo) {
2460                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2461                         if (vf_idx == vf)
2462                                 continue;
2463                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2464                                 idx++)
2465                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2466                 }
2467         } else {
2468                 return -EINVAL;
2469         }
2470
2471         /* Store tx_rate for this vf. */
2472         for (idx = 0; idx < nb_q_per_pool; idx++) {
2473                 if (((uint64_t)0x1 << idx) & q_msk) {
2474                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2475                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2476                         total_rate += tx_rate;
2477                 }
2478         }
2479
2480         if (total_rate > dev->data->dev_link.link_speed) {
2481                 /* Reset stored TX rate of the VF if it causes exceed
2482                  * link speed.
2483                  */
2484                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2485                 return -EINVAL;
2486         }
2487
2488         /* Set RTTBCNRC of each queue/pool for vf X  */
2489         for (; queue_idx <= queue_end; queue_idx++) {
2490                 if (0x1 & q_msk)
2491                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2492                 q_msk = q_msk >> 1;
2493         }
2494
2495         return 0;
2496 }
2497
2498 static int
2499 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2500 {
2501         struct ixgbe_adapter *adapter = dev->data->dev_private;
2502         int err;
2503         uint32_t mflcn;
2504
2505         ixgbe_setup_fc(hw);
2506
2507         err = ixgbe_fc_enable(hw);
2508
2509         /* Not negotiated is not an error case */
2510         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2511                 /*
2512                  *check if we want to forward MAC frames - driver doesn't
2513                  *have native capability to do that,
2514                  *so we'll write the registers ourselves
2515                  */
2516
2517                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2518
2519                 /* set or clear MFLCN.PMCF bit depending on configuration */
2520                 if (adapter->mac_ctrl_frame_fwd != 0)
2521                         mflcn |= IXGBE_MFLCN_PMCF;
2522                 else
2523                         mflcn &= ~IXGBE_MFLCN_PMCF;
2524
2525                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2526                 IXGBE_WRITE_FLUSH(hw);
2527
2528                 return 0;
2529         }
2530         return err;
2531 }
2532
2533 /*
2534  * Configure device link speed and setup link.
2535  * It returns 0 on success.
2536  */
2537 static int
2538 ixgbe_dev_start(struct rte_eth_dev *dev)
2539 {
2540         struct ixgbe_hw *hw =
2541                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2542         struct ixgbe_vf_info *vfinfo =
2543                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2546         uint32_t intr_vector = 0;
2547         int err;
2548         bool link_up = false, negotiate = 0;
2549         uint32_t speed = 0;
2550         uint32_t allowed_speeds = 0;
2551         int mask = 0;
2552         int status;
2553         uint16_t vf, idx;
2554         uint32_t *link_speeds;
2555         struct ixgbe_tm_conf *tm_conf =
2556                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2557         struct ixgbe_macsec_setting *macsec_setting =
2558                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2559
2560         PMD_INIT_FUNC_TRACE();
2561
2562         /* Stop the link setup handler before resetting the HW. */
2563         ixgbe_dev_wait_setup_link_complete(dev, 0);
2564
2565         /* disable uio/vfio intr/eventfd mapping */
2566         rte_intr_disable(intr_handle);
2567
2568         /* stop adapter */
2569         hw->adapter_stopped = 0;
2570         ixgbe_stop_adapter(hw);
2571
2572         /* reinitialize adapter
2573          * this calls reset and start
2574          */
2575         status = ixgbe_pf_reset_hw(hw);
2576         if (status != 0)
2577                 return -1;
2578         hw->mac.ops.start_hw(hw);
2579         hw->mac.get_link_status = true;
2580
2581         /* configure PF module if SRIOV enabled */
2582         ixgbe_pf_host_configure(dev);
2583
2584         ixgbe_dev_phy_intr_setup(dev);
2585
2586         /* check and configure queue intr-vector mapping */
2587         if ((rte_intr_cap_multiple(intr_handle) ||
2588              !RTE_ETH_DEV_SRIOV(dev).active) &&
2589             dev->data->dev_conf.intr_conf.rxq != 0) {
2590                 intr_vector = dev->data->nb_rx_queues;
2591                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2592                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2593                                         IXGBE_MAX_INTR_QUEUE_NUM);
2594                         return -ENOTSUP;
2595                 }
2596                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2597                         return -1;
2598         }
2599
2600         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2601                 intr_handle->intr_vec =
2602                         rte_zmalloc("intr_vec",
2603                                     dev->data->nb_rx_queues * sizeof(int), 0);
2604                 if (intr_handle->intr_vec == NULL) {
2605                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2606                                      " intr_vec", dev->data->nb_rx_queues);
2607                         return -ENOMEM;
2608                 }
2609         }
2610
2611         /* confiugre msix for sleep until rx interrupt */
2612         ixgbe_configure_msix(dev);
2613
2614         /* initialize transmission unit */
2615         ixgbe_dev_tx_init(dev);
2616
2617         /* This can fail when allocating mbufs for descriptor rings */
2618         err = ixgbe_dev_rx_init(dev);
2619         if (err) {
2620                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2621                 goto error;
2622         }
2623
2624         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2625                 ETH_VLAN_EXTEND_MASK;
2626         err = ixgbe_vlan_offload_config(dev, mask);
2627         if (err) {
2628                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2629                 goto error;
2630         }
2631
2632         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2633                 /* Enable vlan filtering for VMDq */
2634                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2635         }
2636
2637         /* Configure DCB hw */
2638         ixgbe_configure_dcb(dev);
2639
2640         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2641                 err = ixgbe_fdir_configure(dev);
2642                 if (err)
2643                         goto error;
2644         }
2645
2646         /* Restore vf rate limit */
2647         if (vfinfo != NULL) {
2648                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2649                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2650                                 if (vfinfo[vf].tx_rate[idx] != 0)
2651                                         ixgbe_set_vf_rate_limit(
2652                                                 dev, vf,
2653                                                 vfinfo[vf].tx_rate[idx],
2654                                                 1 << idx);
2655         }
2656
2657         ixgbe_restore_statistics_mapping(dev);
2658
2659         err = ixgbe_flow_ctrl_enable(dev, hw);
2660         if (err < 0) {
2661                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2662                 goto error;
2663         }
2664
2665         err = ixgbe_dev_rxtx_start(dev);
2666         if (err < 0) {
2667                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2668                 goto error;
2669         }
2670
2671         /* Skip link setup if loopback mode is enabled. */
2672         if (dev->data->dev_conf.lpbk_mode != 0) {
2673                 err = ixgbe_check_supported_loopback_mode(dev);
2674                 if (err < 0) {
2675                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2676                         goto error;
2677                 } else {
2678                         goto skip_link_setup;
2679                 }
2680         }
2681
2682         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2683                 err = hw->mac.ops.setup_sfp(hw);
2684                 if (err)
2685                         goto error;
2686         }
2687
2688         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2689                 /* Turn on the copper */
2690                 ixgbe_set_phy_power(hw, true);
2691         } else {
2692                 /* Turn on the laser */
2693                 ixgbe_enable_tx_laser(hw);
2694         }
2695
2696         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2697         if (err)
2698                 goto error;
2699         dev->data->dev_link.link_status = link_up;
2700
2701         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2702         if (err)
2703                 goto error;
2704
2705         switch (hw->mac.type) {
2706         case ixgbe_mac_X550:
2707         case ixgbe_mac_X550EM_x:
2708         case ixgbe_mac_X550EM_a:
2709                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2710                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2711                         ETH_LINK_SPEED_10G;
2712                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2713                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2714                         allowed_speeds = ETH_LINK_SPEED_10M |
2715                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2716                 break;
2717         default:
2718                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2719                         ETH_LINK_SPEED_10G;
2720         }
2721
2722         link_speeds = &dev->data->dev_conf.link_speeds;
2723
2724         /* Ignore autoneg flag bit and check the validity of
2725          * link_speed
2726          */
2727         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2728                 PMD_INIT_LOG(ERR, "Invalid link setting");
2729                 goto error;
2730         }
2731
2732         speed = 0x0;
2733         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2734                 switch (hw->mac.type) {
2735                 case ixgbe_mac_82598EB:
2736                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2737                         break;
2738                 case ixgbe_mac_82599EB:
2739                 case ixgbe_mac_X540:
2740                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2741                         break;
2742                 case ixgbe_mac_X550:
2743                 case ixgbe_mac_X550EM_x:
2744                 case ixgbe_mac_X550EM_a:
2745                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2746                         break;
2747                 default:
2748                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2749                 }
2750         } else {
2751                 if (*link_speeds & ETH_LINK_SPEED_10G)
2752                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2753                 if (*link_speeds & ETH_LINK_SPEED_5G)
2754                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2755                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2756                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2757                 if (*link_speeds & ETH_LINK_SPEED_1G)
2758                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2759                 if (*link_speeds & ETH_LINK_SPEED_100M)
2760                         speed |= IXGBE_LINK_SPEED_100_FULL;
2761                 if (*link_speeds & ETH_LINK_SPEED_10M)
2762                         speed |= IXGBE_LINK_SPEED_10_FULL;
2763         }
2764
2765         err = ixgbe_setup_link(hw, speed, link_up);
2766         if (err)
2767                 goto error;
2768
2769 skip_link_setup:
2770
2771         if (rte_intr_allow_others(intr_handle)) {
2772                 /* check if lsc interrupt is enabled */
2773                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2774                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2775                 else
2776                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2777                 ixgbe_dev_macsec_interrupt_setup(dev);
2778         } else {
2779                 rte_intr_callback_unregister(intr_handle,
2780                                              ixgbe_dev_interrupt_handler, dev);
2781                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2782                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2783                                      " no intr multiplex");
2784         }
2785
2786         /* check if rxq interrupt is enabled */
2787         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2788             rte_intr_dp_is_en(intr_handle))
2789                 ixgbe_dev_rxq_interrupt_setup(dev);
2790
2791         /* enable uio/vfio intr/eventfd mapping */
2792         rte_intr_enable(intr_handle);
2793
2794         /* resume enabled intr since hw reset */
2795         ixgbe_enable_intr(dev);
2796         ixgbe_l2_tunnel_conf(dev);
2797         ixgbe_filter_restore(dev);
2798
2799         if (tm_conf->root && !tm_conf->committed)
2800                 PMD_DRV_LOG(WARNING,
2801                             "please call hierarchy_commit() "
2802                             "before starting the port");
2803
2804         /* wait for the controller to acquire link */
2805         err = ixgbe_wait_for_link_up(hw);
2806         if (err)
2807                 goto error;
2808
2809         /*
2810          * Update link status right before return, because it may
2811          * start link configuration process in a separate thread.
2812          */
2813         ixgbe_dev_link_update(dev, 0);
2814
2815         /* setup the macsec setting register */
2816         if (macsec_setting->offload_en)
2817                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2818
2819         return 0;
2820
2821 error:
2822         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2823         ixgbe_dev_clear_queues(dev);
2824         return -EIO;
2825 }
2826
2827 /*
2828  * Stop device: disable rx and tx functions to allow for reconfiguring.
2829  */
2830 static int
2831 ixgbe_dev_stop(struct rte_eth_dev *dev)
2832 {
2833         struct rte_eth_link link;
2834         struct ixgbe_adapter *adapter = dev->data->dev_private;
2835         struct ixgbe_hw *hw =
2836                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2837         struct ixgbe_vf_info *vfinfo =
2838                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2839         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2840         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2841         int vf;
2842         struct ixgbe_tm_conf *tm_conf =
2843                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2844
2845         if (hw->adapter_stopped)
2846                 return 0;
2847
2848         PMD_INIT_FUNC_TRACE();
2849
2850         ixgbe_dev_wait_setup_link_complete(dev, 0);
2851
2852         /* disable interrupts */
2853         ixgbe_disable_intr(hw);
2854
2855         /* reset the NIC */
2856         ixgbe_pf_reset_hw(hw);
2857         hw->adapter_stopped = 0;
2858
2859         /* stop adapter */
2860         ixgbe_stop_adapter(hw);
2861
2862         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2863                 vfinfo[vf].clear_to_send = false;
2864
2865         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2866                 /* Turn off the copper */
2867                 ixgbe_set_phy_power(hw, false);
2868         } else {
2869                 /* Turn off the laser */
2870                 ixgbe_disable_tx_laser(hw);
2871         }
2872
2873         ixgbe_dev_clear_queues(dev);
2874
2875         /* Clear stored conf */
2876         dev->data->scattered_rx = 0;
2877         dev->data->lro = 0;
2878
2879         /* Clear recorded link status */
2880         memset(&link, 0, sizeof(link));
2881         rte_eth_linkstatus_set(dev, &link);
2882
2883         if (!rte_intr_allow_others(intr_handle))
2884                 /* resume to the default handler */
2885                 rte_intr_callback_register(intr_handle,
2886                                            ixgbe_dev_interrupt_handler,
2887                                            (void *)dev);
2888
2889         /* Clean datapath event and queue/vec mapping */
2890         rte_intr_efd_disable(intr_handle);
2891         if (intr_handle->intr_vec != NULL) {
2892                 rte_free(intr_handle->intr_vec);
2893                 intr_handle->intr_vec = NULL;
2894         }
2895
2896         /* reset hierarchy commit */
2897         tm_conf->committed = false;
2898
2899         adapter->rss_reta_updated = 0;
2900
2901         hw->adapter_stopped = true;
2902         dev->data->dev_started = 0;
2903
2904         return 0;
2905 }
2906
2907 /*
2908  * Set device link up: enable tx.
2909  */
2910 static int
2911 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2912 {
2913         struct ixgbe_hw *hw =
2914                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2915         if (hw->mac.type == ixgbe_mac_82599EB) {
2916 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2917                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2918                         /* Not suported in bypass mode */
2919                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2920                                      "by device id 0x%x", hw->device_id);
2921                         return -ENOTSUP;
2922                 }
2923 #endif
2924         }
2925
2926         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2927                 /* Turn on the copper */
2928                 ixgbe_set_phy_power(hw, true);
2929         } else {
2930                 /* Turn on the laser */
2931                 ixgbe_enable_tx_laser(hw);
2932                 ixgbe_dev_link_update(dev, 0);
2933         }
2934
2935         return 0;
2936 }
2937
2938 /*
2939  * Set device link down: disable tx.
2940  */
2941 static int
2942 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2943 {
2944         struct ixgbe_hw *hw =
2945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2946         if (hw->mac.type == ixgbe_mac_82599EB) {
2947 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2948                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2949                         /* Not suported in bypass mode */
2950                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2951                                      "by device id 0x%x", hw->device_id);
2952                         return -ENOTSUP;
2953                 }
2954 #endif
2955         }
2956
2957         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2958                 /* Turn off the copper */
2959                 ixgbe_set_phy_power(hw, false);
2960         } else {
2961                 /* Turn off the laser */
2962                 ixgbe_disable_tx_laser(hw);
2963                 ixgbe_dev_link_update(dev, 0);
2964         }
2965
2966         return 0;
2967 }
2968
2969 /*
2970  * Reset and stop device.
2971  */
2972 static int
2973 ixgbe_dev_close(struct rte_eth_dev *dev)
2974 {
2975         struct ixgbe_hw *hw =
2976                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2977         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2978         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2979         int retries = 0;
2980         int ret;
2981
2982         PMD_INIT_FUNC_TRACE();
2983         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2984                 return 0;
2985
2986         ixgbe_pf_reset_hw(hw);
2987
2988         ret = ixgbe_dev_stop(dev);
2989
2990         ixgbe_dev_free_queues(dev);
2991
2992         ixgbe_disable_pcie_master(hw);
2993
2994         /* reprogram the RAR[0] in case user changed it. */
2995         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2996
2997         /* Unlock any pending hardware semaphore */
2998         ixgbe_swfw_lock_reset(hw);
2999
3000         /* disable uio intr before callback unregister */
3001         rte_intr_disable(intr_handle);
3002
3003         do {
3004                 ret = rte_intr_callback_unregister(intr_handle,
3005                                 ixgbe_dev_interrupt_handler, dev);
3006                 if (ret >= 0 || ret == -ENOENT) {
3007                         break;
3008                 } else if (ret != -EAGAIN) {
3009                         PMD_INIT_LOG(ERR,
3010                                 "intr callback unregister failed: %d",
3011                                 ret);
3012                 }
3013                 rte_delay_ms(100);
3014         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3015
3016         /* cancel the delay handler before remove dev */
3017         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3018
3019         /* uninitialize PF if max_vfs not zero */
3020         ixgbe_pf_host_uninit(dev);
3021
3022         /* remove all the fdir filters & hash */
3023         ixgbe_fdir_filter_uninit(dev);
3024
3025         /* remove all the L2 tunnel filters & hash */
3026         ixgbe_l2_tn_filter_uninit(dev);
3027
3028         /* Remove all ntuple filters of the device */
3029         ixgbe_ntuple_filter_uninit(dev);
3030
3031         /* clear all the filters list */
3032         ixgbe_filterlist_flush();
3033
3034         /* Remove all Traffic Manager configuration */
3035         ixgbe_tm_conf_uninit(dev);
3036
3037 #ifdef RTE_LIB_SECURITY
3038         rte_free(dev->security_ctx);
3039 #endif
3040
3041         return ret;
3042 }
3043
3044 /*
3045  * Reset PF device.
3046  */
3047 static int
3048 ixgbe_dev_reset(struct rte_eth_dev *dev)
3049 {
3050         int ret;
3051
3052         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3053          * its VF to make them align with it. The detailed notification
3054          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3055          * To avoid unexpected behavior in VF, currently reset of PF with
3056          * SR-IOV activation is not supported. It might be supported later.
3057          */
3058         if (dev->data->sriov.active)
3059                 return -ENOTSUP;
3060
3061         ret = eth_ixgbe_dev_uninit(dev);
3062         if (ret)
3063                 return ret;
3064
3065         ret = eth_ixgbe_dev_init(dev, NULL);
3066
3067         return ret;
3068 }
3069
3070 static void
3071 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3072                            struct ixgbe_hw_stats *hw_stats,
3073                            struct ixgbe_macsec_stats *macsec_stats,
3074                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3075                            uint64_t *total_qprc, uint64_t *total_qprdc)
3076 {
3077         uint32_t bprc, lxon, lxoff, total;
3078         uint32_t delta_gprc = 0;
3079         unsigned i;
3080         /* Workaround for RX byte count not including CRC bytes when CRC
3081          * strip is enabled. CRC bytes are removed from counters when crc_strip
3082          * is disabled.
3083          */
3084         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3085                         IXGBE_HLREG0_RXCRCSTRP);
3086
3087         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3088         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3089         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3090         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3091
3092         for (i = 0; i < 8; i++) {
3093                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3094
3095                 /* global total per queue */
3096                 hw_stats->mpc[i] += mp;
3097                 /* Running comprehensive total for stats display */
3098                 *total_missed_rx += hw_stats->mpc[i];
3099                 if (hw->mac.type == ixgbe_mac_82598EB) {
3100                         hw_stats->rnbc[i] +=
3101                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3102                         hw_stats->pxonrxc[i] +=
3103                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3104                         hw_stats->pxoffrxc[i] +=
3105                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3106                 } else {
3107                         hw_stats->pxonrxc[i] +=
3108                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3109                         hw_stats->pxoffrxc[i] +=
3110                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3111                         hw_stats->pxon2offc[i] +=
3112                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3113                 }
3114                 hw_stats->pxontxc[i] +=
3115                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3116                 hw_stats->pxofftxc[i] +=
3117                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3118         }
3119         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3120                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3121                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3122                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3123
3124                 delta_gprc += delta_qprc;
3125
3126                 hw_stats->qprc[i] += delta_qprc;
3127                 hw_stats->qptc[i] += delta_qptc;
3128
3129                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3130                 hw_stats->qbrc[i] +=
3131                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3132                 if (crc_strip == 0)
3133                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3134
3135                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3136                 hw_stats->qbtc[i] +=
3137                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3138
3139                 hw_stats->qprdc[i] += delta_qprdc;
3140                 *total_qprdc += hw_stats->qprdc[i];
3141
3142                 *total_qprc += hw_stats->qprc[i];
3143                 *total_qbrc += hw_stats->qbrc[i];
3144         }
3145         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3146         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3147         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3148
3149         /*
3150          * An errata states that gprc actually counts good + missed packets:
3151          * Workaround to set gprc to summated queue packet receives
3152          */
3153         hw_stats->gprc = *total_qprc;
3154
3155         if (hw->mac.type != ixgbe_mac_82598EB) {
3156                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3157                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3158                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3159                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3160                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3161                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3162                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3163                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3164         } else {
3165                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3166                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3167                 /* 82598 only has a counter in the high register */
3168                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3169                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3170                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3171         }
3172         uint64_t old_tpr = hw_stats->tpr;
3173
3174         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3175         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3176
3177         if (crc_strip == 0)
3178                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3179
3180         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3181         hw_stats->gptc += delta_gptc;
3182         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3183         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3184
3185         /*
3186          * Workaround: mprc hardware is incorrectly counting
3187          * broadcasts, so for now we subtract those.
3188          */
3189         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3190         hw_stats->bprc += bprc;
3191         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3192         if (hw->mac.type == ixgbe_mac_82598EB)
3193                 hw_stats->mprc -= bprc;
3194
3195         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3196         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3197         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3198         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3199         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3200         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3201
3202         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3203         hw_stats->lxontxc += lxon;
3204         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3205         hw_stats->lxofftxc += lxoff;
3206         total = lxon + lxoff;
3207
3208         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3209         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3210         hw_stats->gptc -= total;
3211         hw_stats->mptc -= total;
3212         hw_stats->ptc64 -= total;
3213         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3214
3215         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3216         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3217         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3218         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3219         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3220         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3221         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3222         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3223         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3224         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3225         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3226         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3227         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3228         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3229         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3230         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3231         /* Only read FCOE on 82599 */
3232         if (hw->mac.type != ixgbe_mac_82598EB) {
3233                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3234                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3235                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3236                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3237                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3238         }
3239
3240         /* Flow Director Stats registers */
3241         if (hw->mac.type != ixgbe_mac_82598EB) {
3242                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3243                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3244                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3245                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3246                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3247                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3248                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3249                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3250                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3251                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3252         }
3253         /* MACsec Stats registers */
3254         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3255         macsec_stats->out_pkts_encrypted +=
3256                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3257         macsec_stats->out_pkts_protected +=
3258                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3259         macsec_stats->out_octets_encrypted +=
3260                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3261         macsec_stats->out_octets_protected +=
3262                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3263         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3264         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3265         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3266         macsec_stats->in_pkts_unknownsci +=
3267                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3268         macsec_stats->in_octets_decrypted +=
3269                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3270         macsec_stats->in_octets_validated +=
3271                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3272         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3273         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3274         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3275         for (i = 0; i < 2; i++) {
3276                 macsec_stats->in_pkts_ok +=
3277                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3278                 macsec_stats->in_pkts_invalid +=
3279                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3280                 macsec_stats->in_pkts_notvalid +=
3281                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3282         }
3283         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3284         macsec_stats->in_pkts_notusingsa +=
3285                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3286 }
3287
3288 /*
3289  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3290  */
3291 static int
3292 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3293 {
3294         struct ixgbe_hw *hw =
3295                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296         struct ixgbe_hw_stats *hw_stats =
3297                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3298         struct ixgbe_macsec_stats *macsec_stats =
3299                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3300                                 dev->data->dev_private);
3301         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3302         unsigned i;
3303
3304         total_missed_rx = 0;
3305         total_qbrc = 0;
3306         total_qprc = 0;
3307         total_qprdc = 0;
3308
3309         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3310                         &total_qbrc, &total_qprc, &total_qprdc);
3311
3312         if (stats == NULL)
3313                 return -EINVAL;
3314
3315         /* Fill out the rte_eth_stats statistics structure */
3316         stats->ipackets = total_qprc;
3317         stats->ibytes = total_qbrc;
3318         stats->opackets = hw_stats->gptc;
3319         stats->obytes = hw_stats->gotc;
3320
3321         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3322                 stats->q_ipackets[i] = hw_stats->qprc[i];
3323                 stats->q_opackets[i] = hw_stats->qptc[i];
3324                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3325                 stats->q_obytes[i] = hw_stats->qbtc[i];
3326                 stats->q_errors[i] = hw_stats->qprdc[i];
3327         }
3328
3329         /* Rx Errors */
3330         stats->imissed  = total_missed_rx;
3331         stats->ierrors  = hw_stats->crcerrs +
3332                           hw_stats->mspdc +
3333                           hw_stats->rlec +
3334                           hw_stats->ruc +
3335                           hw_stats->roc +
3336                           hw_stats->illerrc +
3337                           hw_stats->errbc +
3338                           hw_stats->rfc +
3339                           hw_stats->fccrc +
3340                           hw_stats->fclast;
3341
3342         /*
3343          * 82599 errata, UDP frames with a 0 checksum can be marked as checksum
3344          * errors.
3345          */
3346         if (hw->mac.type != ixgbe_mac_82599EB)
3347                 stats->ierrors += hw_stats->xec;
3348
3349         /* Tx Errors */
3350         stats->oerrors  = 0;
3351         return 0;
3352 }
3353
3354 static int
3355 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3356 {
3357         struct ixgbe_hw_stats *stats =
3358                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3359
3360         /* HW registers are cleared on read */
3361         ixgbe_dev_stats_get(dev, NULL);
3362
3363         /* Reset software totals */
3364         memset(stats, 0, sizeof(*stats));
3365
3366         return 0;
3367 }
3368
3369 /* This function calculates the number of xstats based on the current config */
3370 static unsigned
3371 ixgbe_xstats_calc_num(void) {
3372         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3373                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3374                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3375 }
3376
3377 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3378         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3379 {
3380         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3381         unsigned stat, i, count;
3382
3383         if (xstats_names != NULL) {
3384                 count = 0;
3385
3386                 /* Note: limit >= cnt_stats checked upstream
3387                  * in rte_eth_xstats_names()
3388                  */
3389
3390                 /* Extended stats from ixgbe_hw_stats */
3391                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3392                         strlcpy(xstats_names[count].name,
3393                                 rte_ixgbe_stats_strings[i].name,
3394                                 sizeof(xstats_names[count].name));
3395                         count++;
3396                 }
3397
3398                 /* MACsec Stats */
3399                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3400                         strlcpy(xstats_names[count].name,
3401                                 rte_ixgbe_macsec_strings[i].name,
3402                                 sizeof(xstats_names[count].name));
3403                         count++;
3404                 }
3405
3406                 /* RX Priority Stats */
3407                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3408                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3409                                 snprintf(xstats_names[count].name,
3410                                         sizeof(xstats_names[count].name),
3411                                         "rx_priority%u_%s", i,
3412                                         rte_ixgbe_rxq_strings[stat].name);
3413                                 count++;
3414                         }
3415                 }
3416
3417                 /* TX Priority Stats */
3418                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3419                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3420                                 snprintf(xstats_names[count].name,
3421                                         sizeof(xstats_names[count].name),
3422                                         "tx_priority%u_%s", i,
3423                                         rte_ixgbe_txq_strings[stat].name);
3424                                 count++;
3425                         }
3426                 }
3427         }
3428         return cnt_stats;
3429 }
3430
3431 static int ixgbe_dev_xstats_get_names_by_id(
3432         struct rte_eth_dev *dev,
3433         const uint64_t *ids,
3434         struct rte_eth_xstat_name *xstats_names,
3435         unsigned int limit)
3436 {
3437         if (!ids) {
3438                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3439                 unsigned int stat, i, count;
3440
3441                 if (xstats_names != NULL) {
3442                         count = 0;
3443
3444                         /* Note: limit >= cnt_stats checked upstream
3445                          * in rte_eth_xstats_names()
3446                          */
3447
3448                         /* Extended stats from ixgbe_hw_stats */
3449                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3450                                 strlcpy(xstats_names[count].name,
3451                                         rte_ixgbe_stats_strings[i].name,
3452                                         sizeof(xstats_names[count].name));
3453                                 count++;
3454                         }
3455
3456                         /* MACsec Stats */
3457                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3458                                 strlcpy(xstats_names[count].name,
3459                                         rte_ixgbe_macsec_strings[i].name,
3460                                         sizeof(xstats_names[count].name));
3461                                 count++;
3462                         }
3463
3464                         /* RX Priority Stats */
3465                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3466                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3467                                         snprintf(xstats_names[count].name,
3468                                             sizeof(xstats_names[count].name),
3469                                             "rx_priority%u_%s", i,
3470                                             rte_ixgbe_rxq_strings[stat].name);
3471                                         count++;
3472                                 }
3473                         }
3474
3475                         /* TX Priority Stats */
3476                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3477                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3478                                         snprintf(xstats_names[count].name,
3479                                             sizeof(xstats_names[count].name),
3480                                             "tx_priority%u_%s", i,
3481                                             rte_ixgbe_txq_strings[stat].name);
3482                                         count++;
3483                                 }
3484                         }
3485                 }
3486                 return cnt_stats;
3487         }
3488
3489         uint16_t i;
3490         uint16_t size = ixgbe_xstats_calc_num();
3491         struct rte_eth_xstat_name xstats_names_copy[size];
3492
3493         ixgbe_dev_xstats_get_names_by_id(dev, NULL, xstats_names_copy,
3494                         size);
3495
3496         for (i = 0; i < limit; i++) {
3497                 if (ids[i] >= size) {
3498                         PMD_INIT_LOG(ERR, "id value isn't valid");
3499                         return -1;
3500                 }
3501                 strcpy(xstats_names[i].name,
3502                                 xstats_names_copy[ids[i]].name);
3503         }
3504         return limit;
3505 }
3506
3507 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3508         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3509 {
3510         unsigned i;
3511
3512         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3513                 return -ENOMEM;
3514
3515         if (xstats_names != NULL)
3516                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3517                         strlcpy(xstats_names[i].name,
3518                                 rte_ixgbevf_stats_strings[i].name,
3519                                 sizeof(xstats_names[i].name));
3520         return IXGBEVF_NB_XSTATS;
3521 }
3522
3523 static int
3524 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3525                                          unsigned n)
3526 {
3527         struct ixgbe_hw *hw =
3528                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3529         struct ixgbe_hw_stats *hw_stats =
3530                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3531         struct ixgbe_macsec_stats *macsec_stats =
3532                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3533                                 dev->data->dev_private);
3534         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3535         unsigned i, stat, count = 0;
3536
3537         count = ixgbe_xstats_calc_num();
3538
3539         if (n < count)
3540                 return count;
3541
3542         total_missed_rx = 0;
3543         total_qbrc = 0;
3544         total_qprc = 0;
3545         total_qprdc = 0;
3546
3547         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3548                         &total_qbrc, &total_qprc, &total_qprdc);
3549
3550         /* If this is a reset xstats is NULL, and we have cleared the
3551          * registers by reading them.
3552          */
3553         if (!xstats)
3554                 return 0;
3555
3556         /* Extended stats from ixgbe_hw_stats */
3557         count = 0;
3558         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3559                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3560                                 rte_ixgbe_stats_strings[i].offset);
3561                 xstats[count].id = count;
3562                 count++;
3563         }
3564
3565         /* MACsec Stats */
3566         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3567                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3568                                 rte_ixgbe_macsec_strings[i].offset);
3569                 xstats[count].id = count;
3570                 count++;
3571         }
3572
3573         /* RX Priority Stats */
3574         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3575                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3576                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3577                                         rte_ixgbe_rxq_strings[stat].offset +
3578                                         (sizeof(uint64_t) * i));
3579                         xstats[count].id = count;
3580                         count++;
3581                 }
3582         }
3583
3584         /* TX Priority Stats */
3585         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3586                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3587                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3588                                         rte_ixgbe_txq_strings[stat].offset +
3589                                         (sizeof(uint64_t) * i));
3590                         xstats[count].id = count;
3591                         count++;
3592                 }
3593         }
3594         return count;
3595 }
3596
3597 static int
3598 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3599                 uint64_t *values, unsigned int n)
3600 {
3601         if (!ids) {
3602                 struct ixgbe_hw *hw =
3603                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3604                 struct ixgbe_hw_stats *hw_stats =
3605                                 IXGBE_DEV_PRIVATE_TO_STATS(
3606                                                 dev->data->dev_private);
3607                 struct ixgbe_macsec_stats *macsec_stats =
3608                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3609                                         dev->data->dev_private);
3610                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3611                 unsigned int i, stat, count = 0;
3612
3613                 count = ixgbe_xstats_calc_num();
3614
3615                 if (!ids && n < count)
3616                         return count;
3617
3618                 total_missed_rx = 0;
3619                 total_qbrc = 0;
3620                 total_qprc = 0;
3621                 total_qprdc = 0;
3622
3623                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3624                                 &total_missed_rx, &total_qbrc, &total_qprc,
3625                                 &total_qprdc);
3626
3627                 /* If this is a reset xstats is NULL, and we have cleared the
3628                  * registers by reading them.
3629                  */
3630                 if (!ids && !values)
3631                         return 0;
3632
3633                 /* Extended stats from ixgbe_hw_stats */
3634                 count = 0;
3635                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3636                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3637                                         rte_ixgbe_stats_strings[i].offset);
3638                         count++;
3639                 }
3640
3641                 /* MACsec Stats */
3642                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3643                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3644                                         rte_ixgbe_macsec_strings[i].offset);
3645                         count++;
3646                 }
3647
3648                 /* RX Priority Stats */
3649                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3650                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3651                                 values[count] =
3652                                         *(uint64_t *)(((char *)hw_stats) +
3653                                         rte_ixgbe_rxq_strings[stat].offset +
3654                                         (sizeof(uint64_t) * i));
3655                                 count++;
3656                         }
3657                 }
3658
3659                 /* TX Priority Stats */
3660                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3661                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3662                                 values[count] =
3663                                         *(uint64_t *)(((char *)hw_stats) +
3664                                         rte_ixgbe_txq_strings[stat].offset +
3665                                         (sizeof(uint64_t) * i));
3666                                 count++;
3667                         }
3668                 }
3669                 return count;
3670         }
3671
3672         uint16_t i;
3673         uint16_t size = ixgbe_xstats_calc_num();
3674         uint64_t values_copy[size];
3675
3676         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3677
3678         for (i = 0; i < n; i++) {
3679                 if (ids[i] >= size) {
3680                         PMD_INIT_LOG(ERR, "id value isn't valid");
3681                         return -1;
3682                 }
3683                 values[i] = values_copy[ids[i]];
3684         }
3685         return n;
3686 }
3687
3688 static int
3689 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3690 {
3691         struct ixgbe_hw_stats *stats =
3692                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3693         struct ixgbe_macsec_stats *macsec_stats =
3694                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3695                                 dev->data->dev_private);
3696
3697         unsigned count = ixgbe_xstats_calc_num();
3698
3699         /* HW registers are cleared on read */
3700         ixgbe_dev_xstats_get(dev, NULL, count);
3701
3702         /* Reset software totals */
3703         memset(stats, 0, sizeof(*stats));
3704         memset(macsec_stats, 0, sizeof(*macsec_stats));
3705
3706         return 0;
3707 }
3708
3709 static void
3710 ixgbevf_update_stats(struct rte_eth_dev *dev)
3711 {
3712         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3713         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3714                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3715
3716         /* Good Rx packet, include VF loopback */
3717         UPDATE_VF_STAT(IXGBE_VFGPRC,
3718             hw_stats->last_vfgprc, hw_stats->vfgprc);
3719
3720         /* Good Rx octets, include VF loopback */
3721         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3722             hw_stats->last_vfgorc, hw_stats->vfgorc);
3723
3724         /* Good Tx packet, include VF loopback */
3725         UPDATE_VF_STAT(IXGBE_VFGPTC,
3726             hw_stats->last_vfgptc, hw_stats->vfgptc);
3727
3728         /* Good Tx octets, include VF loopback */
3729         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3730             hw_stats->last_vfgotc, hw_stats->vfgotc);
3731
3732         /* Rx Multicst Packet */
3733         UPDATE_VF_STAT(IXGBE_VFMPRC,
3734             hw_stats->last_vfmprc, hw_stats->vfmprc);
3735 }
3736
3737 static int
3738 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3739                        unsigned n)
3740 {
3741         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3742                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3743         unsigned i;
3744
3745         if (n < IXGBEVF_NB_XSTATS)
3746                 return IXGBEVF_NB_XSTATS;
3747
3748         ixgbevf_update_stats(dev);
3749
3750         if (!xstats)
3751                 return 0;
3752
3753         /* Extended stats */
3754         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3755                 xstats[i].id = i;
3756                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3757                         rte_ixgbevf_stats_strings[i].offset);
3758         }
3759
3760         return IXGBEVF_NB_XSTATS;
3761 }
3762
3763 static int
3764 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3765 {
3766         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3767                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3768
3769         ixgbevf_update_stats(dev);
3770
3771         if (stats == NULL)
3772                 return -EINVAL;
3773
3774         stats->ipackets = hw_stats->vfgprc;
3775         stats->ibytes = hw_stats->vfgorc;
3776         stats->opackets = hw_stats->vfgptc;
3777         stats->obytes = hw_stats->vfgotc;
3778         return 0;
3779 }
3780
3781 static int
3782 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3783 {
3784         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3785                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3786
3787         /* Sync HW register to the last stats */
3788         ixgbevf_dev_stats_get(dev, NULL);
3789
3790         /* reset HW current stats*/
3791         hw_stats->vfgprc = 0;
3792         hw_stats->vfgorc = 0;
3793         hw_stats->vfgptc = 0;
3794         hw_stats->vfgotc = 0;
3795         hw_stats->vfmprc = 0;
3796
3797         return 0;
3798 }
3799
3800 static int
3801 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3802 {
3803         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3804         u16 eeprom_verh, eeprom_verl;
3805         u32 etrack_id;
3806         int ret;
3807
3808         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3809         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3810
3811         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3812         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3813         if (ret < 0)
3814                 return -EINVAL;
3815
3816         ret += 1; /* add the size of '\0' */
3817         if (fw_size < (size_t)ret)
3818                 return ret;
3819         else
3820                 return 0;
3821 }
3822
3823 static int
3824 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3825 {
3826         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3827         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3828         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3829
3830         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3831         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3832         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3833                 /*
3834                  * When DCB/VT is off, maximum number of queues changes,
3835                  * except for 82598EB, which remains constant.
3836                  */
3837                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3838                                 hw->mac.type != ixgbe_mac_82598EB)
3839                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3840         }
3841         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3842         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3843         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3844         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3845         dev_info->max_vfs = pci_dev->max_vfs;
3846         if (hw->mac.type == ixgbe_mac_82598EB)
3847                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3848         else
3849                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3850         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3851         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3852         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3853         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3854         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3855                                      dev_info->rx_queue_offload_capa);
3856         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3857         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3858
3859         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3860                 .rx_thresh = {
3861                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3862                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3863                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3864                 },
3865                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3866                 .rx_drop_en = 0,
3867                 .offloads = 0,
3868         };
3869
3870         dev_info->default_txconf = (struct rte_eth_txconf) {
3871                 .tx_thresh = {
3872                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3873                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3874                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3875                 },
3876                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3877                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3878                 .offloads = 0,
3879         };
3880
3881         dev_info->rx_desc_lim = rx_desc_lim;
3882         dev_info->tx_desc_lim = tx_desc_lim;
3883
3884         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3885         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3886         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3887
3888         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3889         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3890                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3891                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3892                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3893
3894         if (hw->mac.type == ixgbe_mac_X540 ||
3895             hw->mac.type == ixgbe_mac_X540_vf ||
3896             hw->mac.type == ixgbe_mac_X550 ||
3897             hw->mac.type == ixgbe_mac_X550_vf) {
3898                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3899         }
3900         if (hw->mac.type == ixgbe_mac_X550) {
3901                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3902                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3903         }
3904
3905         /* Driver-preferred Rx/Tx parameters */
3906         dev_info->default_rxportconf.burst_size = 32;
3907         dev_info->default_txportconf.burst_size = 32;
3908         dev_info->default_rxportconf.nb_queues = 1;
3909         dev_info->default_txportconf.nb_queues = 1;
3910         dev_info->default_rxportconf.ring_size = 256;
3911         dev_info->default_txportconf.ring_size = 256;
3912
3913         return 0;
3914 }
3915
3916 static const uint32_t *
3917 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3918 {
3919         static const uint32_t ptypes[] = {
3920                 /* For non-vec functions,
3921                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3922                  * for vec functions,
3923                  * refers to _recv_raw_pkts_vec().
3924                  */
3925                 RTE_PTYPE_L2_ETHER,
3926                 RTE_PTYPE_L3_IPV4,
3927                 RTE_PTYPE_L3_IPV4_EXT,
3928                 RTE_PTYPE_L3_IPV6,
3929                 RTE_PTYPE_L3_IPV6_EXT,
3930                 RTE_PTYPE_L4_SCTP,
3931                 RTE_PTYPE_L4_TCP,
3932                 RTE_PTYPE_L4_UDP,
3933                 RTE_PTYPE_TUNNEL_IP,
3934                 RTE_PTYPE_INNER_L3_IPV6,
3935                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3936                 RTE_PTYPE_INNER_L4_TCP,
3937                 RTE_PTYPE_INNER_L4_UDP,
3938                 RTE_PTYPE_UNKNOWN
3939         };
3940
3941         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3942             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3943             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3944             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3945                 return ptypes;
3946
3947 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3948         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3949             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3950                 return ptypes;
3951 #endif
3952         return NULL;
3953 }
3954
3955 static int
3956 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3957                      struct rte_eth_dev_info *dev_info)
3958 {
3959         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3961
3962         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3963         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3964         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3965         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3966         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3967         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3968         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3969         dev_info->max_vfs = pci_dev->max_vfs;
3970         if (hw->mac.type == ixgbe_mac_82598EB)
3971                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3972         else
3973                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3974         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3975         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3976                                      dev_info->rx_queue_offload_capa);
3977         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3978         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3979         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3980         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3981         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3982
3983         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3984                 .rx_thresh = {
3985                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3986                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3987                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3988                 },
3989                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3990                 .rx_drop_en = 0,
3991                 .offloads = 0,
3992         };
3993
3994         dev_info->default_txconf = (struct rte_eth_txconf) {
3995                 .tx_thresh = {
3996                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3997                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3998                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3999                 },
4000                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4001                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4002                 .offloads = 0,
4003         };
4004
4005         dev_info->rx_desc_lim = rx_desc_lim;
4006         dev_info->tx_desc_lim = tx_desc_lim;
4007
4008         return 0;
4009 }
4010
4011 static int
4012 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4013                    bool *link_up, int wait_to_complete)
4014 {
4015         struct ixgbe_adapter *adapter = container_of(hw,
4016                                                      struct ixgbe_adapter, hw);
4017         struct ixgbe_mbx_info *mbx = &hw->mbx;
4018         struct ixgbe_mac_info *mac = &hw->mac;
4019         uint32_t links_reg, in_msg;
4020         int ret_val = 0;
4021
4022         /* If we were hit with a reset drop the link */
4023         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4024                 mac->get_link_status = true;
4025
4026         if (!mac->get_link_status)
4027                 goto out;
4028
4029         /* if link status is down no point in checking to see if pf is up */
4030         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4031         if (!(links_reg & IXGBE_LINKS_UP))
4032                 goto out;
4033
4034         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4035          * before the link status is correct
4036          */
4037         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4038                 int i;
4039
4040                 for (i = 0; i < 5; i++) {
4041                         rte_delay_us(100);
4042                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4043
4044                         if (!(links_reg & IXGBE_LINKS_UP))
4045                                 goto out;
4046                 }
4047         }
4048
4049         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4050         case IXGBE_LINKS_SPEED_10G_82599:
4051                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4052                 if (hw->mac.type >= ixgbe_mac_X550) {
4053                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4054                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4055                 }
4056                 break;
4057         case IXGBE_LINKS_SPEED_1G_82599:
4058                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4059                 break;
4060         case IXGBE_LINKS_SPEED_100_82599:
4061                 *speed = IXGBE_LINK_SPEED_100_FULL;
4062                 if (hw->mac.type == ixgbe_mac_X550) {
4063                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4064                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4065                 }
4066                 break;
4067         case IXGBE_LINKS_SPEED_10_X550EM_A:
4068                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4069                 /* Since Reserved in older MAC's */
4070                 if (hw->mac.type >= ixgbe_mac_X550)
4071                         *speed = IXGBE_LINK_SPEED_10_FULL;
4072                 break;
4073         default:
4074                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4075         }
4076
4077         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4078                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4079                         mac->get_link_status = true;
4080                 else
4081                         mac->get_link_status = false;
4082
4083                 goto out;
4084         }
4085
4086         /* if the read failed it could just be a mailbox collision, best wait
4087          * until we are called again and don't report an error
4088          */
4089         if (mbx->ops.read(hw, &in_msg, 1, 0))
4090                 goto out;
4091
4092         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4093                 /* msg is not CTS and is NACK we must have lost CTS status */
4094                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4095                         mac->get_link_status = false;
4096                 goto out;
4097         }
4098
4099         /* the pf is talking, if we timed out in the past we reinit */
4100         if (!mbx->timeout) {
4101                 ret_val = -1;
4102                 goto out;
4103         }
4104
4105         /* if we passed all the tests above then the link is up and we no
4106          * longer need to check for link
4107          */
4108         mac->get_link_status = false;
4109
4110 out:
4111         *link_up = !mac->get_link_status;
4112         return ret_val;
4113 }
4114
4115 /*
4116  * If @timeout_ms was 0, it means that it will not return until link complete.
4117  * It returns 1 on complete, return 0 on timeout.
4118  */
4119 static int
4120 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4121 {
4122 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4123         struct ixgbe_adapter *ad = dev->data->dev_private;
4124         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4125
4126         while (rte_atomic32_read(&ad->link_thread_running)) {
4127                 msec_delay(1);
4128                 timeout--;
4129
4130                 if (timeout_ms) {
4131                         if (!timeout)
4132                                 return 0;
4133                 } else if (!timeout) {
4134                         /* It will not return until link complete */
4135                         timeout = WARNING_TIMEOUT;
4136                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4137                 }
4138         }
4139
4140         return 1;
4141 }
4142
4143 static void *
4144 ixgbe_dev_setup_link_thread_handler(void *param)
4145 {
4146         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4147         struct ixgbe_adapter *ad = dev->data->dev_private;
4148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4149         struct ixgbe_interrupt *intr =
4150                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4151         u32 speed;
4152         bool autoneg = false;
4153
4154         pthread_detach(pthread_self());
4155         speed = hw->phy.autoneg_advertised;
4156         if (!speed)
4157                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4158
4159         ixgbe_setup_link(hw, speed, true);
4160
4161         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4162         rte_atomic32_clear(&ad->link_thread_running);
4163         return NULL;
4164 }
4165
4166 /*
4167  * In freebsd environment, nic_uio drivers do not support interrupts,
4168  * rte_intr_callback_register() will fail to register interrupts.
4169  * We can not make link status to change from down to up by interrupt
4170  * callback. So we need to wait for the controller to acquire link
4171  * when ports start.
4172  * It returns 0 on link up.
4173  */
4174 static int
4175 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4176 {
4177 #ifdef RTE_EXEC_ENV_FREEBSD
4178         int err, i;
4179         bool link_up = false;
4180         uint32_t speed = 0;
4181         const int nb_iter = 25;
4182
4183         for (i = 0; i < nb_iter; i++) {
4184                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4185                 if (err)
4186                         return err;
4187                 if (link_up)
4188                         return 0;
4189                 msec_delay(200);
4190         }
4191
4192         return 0;
4193 #else
4194         RTE_SET_USED(hw);
4195         return 0;
4196 #endif
4197 }
4198
4199 /* return 0 means link status changed, -1 means not changed */
4200 int
4201 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4202                             int wait_to_complete, int vf)
4203 {
4204         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4205         struct ixgbe_adapter *ad = dev->data->dev_private;
4206         struct rte_eth_link link;
4207         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4208         struct ixgbe_interrupt *intr =
4209                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4210         bool link_up;
4211         int diag;
4212         int wait = 1;
4213         u32 esdp_reg;
4214
4215         memset(&link, 0, sizeof(link));
4216         link.link_status = ETH_LINK_DOWN;
4217         link.link_speed = ETH_SPEED_NUM_NONE;
4218         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4219         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4220                         ETH_LINK_SPEED_FIXED);
4221
4222         hw->mac.get_link_status = true;
4223
4224         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4225                 return rte_eth_linkstatus_set(dev, &link);
4226
4227         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4228         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4229                 wait = 0;
4230
4231 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4232 #ifdef RTE_EXEC_ENV_FREEBSD
4233         wait = 1;
4234 #endif
4235
4236         if (vf)
4237                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4238         else
4239                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4240
4241         if (diag != 0) {
4242                 link.link_speed = ETH_SPEED_NUM_100M;
4243                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4244                 return rte_eth_linkstatus_set(dev, &link);
4245         }
4246
4247         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4248                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4249                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4250                         link_up = 0;
4251         }
4252
4253         if (link_up == 0) {
4254                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4255                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4256                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4257                                 /* To avoid race condition between threads, set
4258                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4259                                  * when there is no link thread running.
4260                                  */
4261                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4262                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4263                                         "ixgbe-link-handler",
4264                                         NULL,
4265                                         ixgbe_dev_setup_link_thread_handler,
4266                                         dev) < 0) {
4267                                         PMD_DRV_LOG(ERR,
4268                                                 "Create link thread failed!");
4269                                         rte_atomic32_clear(&ad->link_thread_running);
4270                                 }
4271                         } else {
4272                                 PMD_DRV_LOG(ERR,
4273                                         "Other link thread is running now!");
4274                         }
4275                 }
4276                 return rte_eth_linkstatus_set(dev, &link);
4277         }
4278
4279         link.link_status = ETH_LINK_UP;
4280         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4281
4282         switch (link_speed) {
4283         default:
4284         case IXGBE_LINK_SPEED_UNKNOWN:
4285                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4286                 break;
4287
4288         case IXGBE_LINK_SPEED_10_FULL:
4289                 link.link_speed = ETH_SPEED_NUM_10M;
4290                 break;
4291
4292         case IXGBE_LINK_SPEED_100_FULL:
4293                 link.link_speed = ETH_SPEED_NUM_100M;
4294                 break;
4295
4296         case IXGBE_LINK_SPEED_1GB_FULL:
4297                 link.link_speed = ETH_SPEED_NUM_1G;
4298                 break;
4299
4300         case IXGBE_LINK_SPEED_2_5GB_FULL:
4301                 link.link_speed = ETH_SPEED_NUM_2_5G;
4302                 break;
4303
4304         case IXGBE_LINK_SPEED_5GB_FULL:
4305                 link.link_speed = ETH_SPEED_NUM_5G;
4306                 break;
4307
4308         case IXGBE_LINK_SPEED_10GB_FULL:
4309                 link.link_speed = ETH_SPEED_NUM_10G;
4310                 break;
4311         }
4312
4313         return rte_eth_linkstatus_set(dev, &link);
4314 }
4315
4316 static int
4317 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4318 {
4319         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4320 }
4321
4322 static int
4323 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4324 {
4325         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4326 }
4327
4328 static int
4329 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4330 {
4331         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4332         uint32_t fctrl;
4333
4334         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4335         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4336         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4337
4338         return 0;
4339 }
4340
4341 static int
4342 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4343 {
4344         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4345         uint32_t fctrl;
4346
4347         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4348         fctrl &= (~IXGBE_FCTRL_UPE);
4349         if (dev->data->all_multicast == 1)
4350                 fctrl |= IXGBE_FCTRL_MPE;
4351         else
4352                 fctrl &= (~IXGBE_FCTRL_MPE);
4353         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4354
4355         return 0;
4356 }
4357
4358 static int
4359 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4360 {
4361         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362         uint32_t fctrl;
4363
4364         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4365         fctrl |= IXGBE_FCTRL_MPE;
4366         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4367
4368         return 0;
4369 }
4370
4371 static int
4372 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4373 {
4374         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4375         uint32_t fctrl;
4376
4377         if (dev->data->promiscuous == 1)
4378                 return 0; /* must remain in all_multicast mode */
4379
4380         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4381         fctrl &= (~IXGBE_FCTRL_MPE);
4382         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4383
4384         return 0;
4385 }
4386
4387 /**
4388  * It clears the interrupt causes and enables the interrupt.
4389  * It will be called once only during nic initialized.
4390  *
4391  * @param dev
4392  *  Pointer to struct rte_eth_dev.
4393  * @param on
4394  *  Enable or Disable.
4395  *
4396  * @return
4397  *  - On success, zero.
4398  *  - On failure, a negative value.
4399  */
4400 static int
4401 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4402 {
4403         struct ixgbe_interrupt *intr =
4404                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4405
4406         ixgbe_dev_link_status_print(dev);
4407         if (on)
4408                 intr->mask |= IXGBE_EICR_LSC;
4409         else
4410                 intr->mask &= ~IXGBE_EICR_LSC;
4411
4412         return 0;
4413 }
4414
4415 /**
4416  * It clears the interrupt causes and enables the interrupt.
4417  * It will be called once only during nic initialized.
4418  *
4419  * @param dev
4420  *  Pointer to struct rte_eth_dev.
4421  *
4422  * @return
4423  *  - On success, zero.
4424  *  - On failure, a negative value.
4425  */
4426 static int
4427 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4428 {
4429         struct ixgbe_interrupt *intr =
4430                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4431
4432         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4433
4434         return 0;
4435 }
4436
4437 /**
4438  * It clears the interrupt causes and enables the interrupt.
4439  * It will be called once only during nic initialized.
4440  *
4441  * @param dev
4442  *  Pointer to struct rte_eth_dev.
4443  *
4444  * @return
4445  *  - On success, zero.
4446  *  - On failure, a negative value.
4447  */
4448 static int
4449 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4450 {
4451         struct ixgbe_interrupt *intr =
4452                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4453
4454         intr->mask |= IXGBE_EICR_LINKSEC;
4455
4456         return 0;
4457 }
4458
4459 /*
4460  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4461  *
4462  * @param dev
4463  *  Pointer to struct rte_eth_dev.
4464  *
4465  * @return
4466  *  - On success, zero.
4467  *  - On failure, a negative value.
4468  */
4469 static int
4470 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4471 {
4472         uint32_t eicr;
4473         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4474         struct ixgbe_interrupt *intr =
4475                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4476
4477         /* clear all cause mask */
4478         ixgbe_disable_intr(hw);
4479
4480         /* read-on-clear nic registers here */
4481         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4482         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4483
4484         intr->flags = 0;
4485
4486         /* set flag for async link update */
4487         if (eicr & IXGBE_EICR_LSC)
4488                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4489
4490         if (eicr & IXGBE_EICR_MAILBOX)
4491                 intr->flags |= IXGBE_FLAG_MAILBOX;
4492
4493         if (eicr & IXGBE_EICR_LINKSEC)
4494                 intr->flags |= IXGBE_FLAG_MACSEC;
4495
4496         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4497             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4498             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4499                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4500
4501         return 0;
4502 }
4503
4504 /**
4505  * It gets and then prints the link status.
4506  *
4507  * @param dev
4508  *  Pointer to struct rte_eth_dev.
4509  *
4510  * @return
4511  *  - On success, zero.
4512  *  - On failure, a negative value.
4513  */
4514 static void
4515 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4516 {
4517         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4518         struct rte_eth_link link;
4519
4520         rte_eth_linkstatus_get(dev, &link);
4521
4522         if (link.link_status) {
4523                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4524                                         (int)(dev->data->port_id),
4525                                         (unsigned)link.link_speed,
4526                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4527                                         "full-duplex" : "half-duplex");
4528         } else {
4529                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4530                                 (int)(dev->data->port_id));
4531         }
4532         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4533                                 pci_dev->addr.domain,
4534                                 pci_dev->addr.bus,
4535                                 pci_dev->addr.devid,
4536                                 pci_dev->addr.function);
4537 }
4538
4539 /*
4540  * It executes link_update after knowing an interrupt occurred.
4541  *
4542  * @param dev
4543  *  Pointer to struct rte_eth_dev.
4544  *
4545  * @return
4546  *  - On success, zero.
4547  *  - On failure, a negative value.
4548  */
4549 static int
4550 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4551 {
4552         struct ixgbe_interrupt *intr =
4553                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4554         int64_t timeout;
4555         struct ixgbe_hw *hw =
4556                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4557
4558         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4559
4560         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4561                 ixgbe_pf_mbx_process(dev);
4562                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4563         }
4564
4565         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4566                 ixgbe_handle_lasi(hw);
4567                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4568         }
4569
4570         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4571                 struct rte_eth_link link;
4572
4573                 /* get the link status before link update, for predicting later */
4574                 rte_eth_linkstatus_get(dev, &link);
4575
4576                 ixgbe_dev_link_update(dev, 0);
4577
4578                 /* likely to up */
4579                 if (!link.link_status)
4580                         /* handle it 1 sec later, wait it being stable */
4581                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4582                 /* likely to down */
4583                 else
4584                         /* handle it 4 sec later, wait it being stable */
4585                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4586
4587                 ixgbe_dev_link_status_print(dev);
4588                 if (rte_eal_alarm_set(timeout * 1000,
4589                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4590                         PMD_DRV_LOG(ERR, "Error setting alarm");
4591                 else {
4592                         /* remember original mask */
4593                         intr->mask_original = intr->mask;
4594                         /* only disable lsc interrupt */
4595                         intr->mask &= ~IXGBE_EIMS_LSC;
4596                 }
4597         }
4598
4599         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4600         ixgbe_enable_intr(dev);
4601
4602         return 0;
4603 }
4604
4605 /**
4606  * Interrupt handler which shall be registered for alarm callback for delayed
4607  * handling specific interrupt to wait for the stable nic state. As the
4608  * NIC interrupt state is not stable for ixgbe after link is just down,
4609  * it needs to wait 4 seconds to get the stable status.
4610  *
4611  * @param handle
4612  *  Pointer to interrupt handle.
4613  * @param param
4614  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4615  *
4616  * @return
4617  *  void
4618  */
4619 static void
4620 ixgbe_dev_interrupt_delayed_handler(void *param)
4621 {
4622         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4623         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4624         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4625         struct ixgbe_interrupt *intr =
4626                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4627         struct ixgbe_hw *hw =
4628                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629         uint32_t eicr;
4630
4631         ixgbe_disable_intr(hw);
4632
4633         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4634         if (eicr & IXGBE_EICR_MAILBOX)
4635                 ixgbe_pf_mbx_process(dev);
4636
4637         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4638                 ixgbe_handle_lasi(hw);
4639                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4640         }
4641
4642         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4643                 ixgbe_dev_link_update(dev, 0);
4644                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4645                 ixgbe_dev_link_status_print(dev);
4646                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4647         }
4648
4649         if (intr->flags & IXGBE_FLAG_MACSEC) {
4650                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4651                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4652         }
4653
4654         /* restore original mask */
4655         intr->mask = intr->mask_original;
4656         intr->mask_original = 0;
4657
4658         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4659         ixgbe_enable_intr(dev);
4660         rte_intr_ack(intr_handle);
4661 }
4662
4663 /**
4664  * Interrupt handler triggered by NIC  for handling
4665  * specific interrupt.
4666  *
4667  * @param handle
4668  *  Pointer to interrupt handle.
4669  * @param param
4670  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4671  *
4672  * @return
4673  *  void
4674  */
4675 static void
4676 ixgbe_dev_interrupt_handler(void *param)
4677 {
4678         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4679
4680         ixgbe_dev_interrupt_get_status(dev);
4681         ixgbe_dev_interrupt_action(dev);
4682 }
4683
4684 static int
4685 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4686 {
4687         struct ixgbe_hw *hw;
4688
4689         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4690         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4691 }
4692
4693 static int
4694 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4695 {
4696         struct ixgbe_hw *hw;
4697
4698         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4699         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4700 }
4701
4702 static int
4703 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4704 {
4705         struct ixgbe_hw *hw;
4706         uint32_t mflcn_reg;
4707         uint32_t fccfg_reg;
4708         int rx_pause;
4709         int tx_pause;
4710
4711         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4712
4713         fc_conf->pause_time = hw->fc.pause_time;
4714         fc_conf->high_water = hw->fc.high_water[0];
4715         fc_conf->low_water = hw->fc.low_water[0];
4716         fc_conf->send_xon = hw->fc.send_xon;
4717         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4718
4719         /*
4720          * Return rx_pause status according to actual setting of
4721          * MFLCN register.
4722          */
4723         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4724         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4725                 fc_conf->mac_ctrl_frame_fwd = 1;
4726         else
4727                 fc_conf->mac_ctrl_frame_fwd = 0;
4728
4729         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4730                 rx_pause = 1;
4731         else
4732                 rx_pause = 0;
4733
4734         /*
4735          * Return tx_pause status according to actual setting of
4736          * FCCFG register.
4737          */
4738         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4739         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4740                 tx_pause = 1;
4741         else
4742                 tx_pause = 0;
4743
4744         if (rx_pause && tx_pause)
4745                 fc_conf->mode = RTE_FC_FULL;
4746         else if (rx_pause)
4747                 fc_conf->mode = RTE_FC_RX_PAUSE;
4748         else if (tx_pause)
4749                 fc_conf->mode = RTE_FC_TX_PAUSE;
4750         else
4751                 fc_conf->mode = RTE_FC_NONE;
4752
4753         return 0;
4754 }
4755
4756 static int
4757 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4758 {
4759         struct ixgbe_hw *hw;
4760         struct ixgbe_adapter *adapter = dev->data->dev_private;
4761         int err;
4762         uint32_t rx_buf_size;
4763         uint32_t max_high_water;
4764         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4765                 ixgbe_fc_none,
4766                 ixgbe_fc_rx_pause,
4767                 ixgbe_fc_tx_pause,
4768                 ixgbe_fc_full
4769         };
4770
4771         PMD_INIT_FUNC_TRACE();
4772
4773         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4774         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4775         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4776
4777         /*
4778          * At least reserve one Ethernet frame for watermark
4779          * high_water/low_water in kilo bytes for ixgbe
4780          */
4781         max_high_water = (rx_buf_size -
4782                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4783         if ((fc_conf->high_water > max_high_water) ||
4784                 (fc_conf->high_water < fc_conf->low_water)) {
4785                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4786                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4787                 return -EINVAL;
4788         }
4789
4790         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4791         hw->fc.pause_time     = fc_conf->pause_time;
4792         hw->fc.high_water[0]  = fc_conf->high_water;
4793         hw->fc.low_water[0]   = fc_conf->low_water;
4794         hw->fc.send_xon       = fc_conf->send_xon;
4795         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4796         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4797
4798         err = ixgbe_flow_ctrl_enable(dev, hw);
4799         if (err < 0) {
4800                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4801                 return -EIO;
4802         }
4803         return err;
4804 }
4805
4806 /**
4807  *  ixgbe_pfc_enable_generic - Enable flow control
4808  *  @hw: pointer to hardware structure
4809  *  @tc_num: traffic class number
4810  *  Enable flow control according to the current settings.
4811  */
4812 static int
4813 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4814 {
4815         int ret_val = 0;
4816         uint32_t mflcn_reg, fccfg_reg;
4817         uint32_t reg;
4818         uint32_t fcrtl, fcrth;
4819         uint8_t i;
4820         uint8_t nb_rx_en;
4821
4822         /* Validate the water mark configuration */
4823         if (!hw->fc.pause_time) {
4824                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4825                 goto out;
4826         }
4827
4828         /* Low water mark of zero causes XOFF floods */
4829         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4830                  /* High/Low water can not be 0 */
4831                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4832                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4833                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4834                         goto out;
4835                 }
4836
4837                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4838                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4839                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4840                         goto out;
4841                 }
4842         }
4843         /* Negotiate the fc mode to use */
4844         ixgbe_fc_autoneg(hw);
4845
4846         /* Disable any previous flow control settings */
4847         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4848         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4849
4850         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4851         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4852
4853         switch (hw->fc.current_mode) {
4854         case ixgbe_fc_none:
4855                 /*
4856                  * If the count of enabled RX Priority Flow control >1,
4857                  * and the TX pause can not be disabled
4858                  */
4859                 nb_rx_en = 0;
4860                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4861                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4862                         if (reg & IXGBE_FCRTH_FCEN)
4863                                 nb_rx_en++;
4864                 }
4865                 if (nb_rx_en > 1)
4866                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4867                 break;
4868         case ixgbe_fc_rx_pause:
4869                 /*
4870                  * Rx Flow control is enabled and Tx Flow control is
4871                  * disabled by software override. Since there really
4872                  * isn't a way to advertise that we are capable of RX
4873                  * Pause ONLY, we will advertise that we support both
4874                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4875                  * disable the adapter's ability to send PAUSE frames.
4876                  */
4877                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4878                 /*
4879                  * If the count of enabled RX Priority Flow control >1,
4880                  * and the TX pause can not be disabled
4881                  */
4882                 nb_rx_en = 0;
4883                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4884                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4885                         if (reg & IXGBE_FCRTH_FCEN)
4886                                 nb_rx_en++;
4887                 }
4888                 if (nb_rx_en > 1)
4889                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4890                 break;
4891         case ixgbe_fc_tx_pause:
4892                 /*
4893                  * Tx Flow control is enabled, and Rx Flow control is
4894                  * disabled by software override.
4895                  */
4896                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4897                 break;
4898         case ixgbe_fc_full:
4899                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4900                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4901                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4902                 break;
4903         default:
4904                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4905                 ret_val = IXGBE_ERR_CONFIG;
4906                 goto out;
4907         }
4908
4909         /* Set 802.3x based flow control settings. */
4910         mflcn_reg |= IXGBE_MFLCN_DPF;
4911         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4912         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4913
4914         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4915         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4916                 hw->fc.high_water[tc_num]) {
4917                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4918                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4919                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4920         } else {
4921                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4922                 /*
4923                  * In order to prevent Tx hangs when the internal Tx
4924                  * switch is enabled we must set the high water mark
4925                  * to the maximum FCRTH value.  This allows the Tx
4926                  * switch to function even under heavy Rx workloads.
4927                  */
4928                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4929         }
4930         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4931
4932         /* Configure pause time (2 TCs per register) */
4933         reg = hw->fc.pause_time * 0x00010001;
4934         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4935                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4936
4937         /* Configure flow control refresh threshold value */
4938         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4939
4940 out:
4941         return ret_val;
4942 }
4943
4944 static int
4945 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4946 {
4947         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4948         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4949
4950         if (hw->mac.type != ixgbe_mac_82598EB) {
4951                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4952         }
4953         return ret_val;
4954 }
4955
4956 static int
4957 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4958 {
4959         int err;
4960         uint32_t rx_buf_size;
4961         uint32_t max_high_water;
4962         uint8_t tc_num;
4963         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4964         struct ixgbe_hw *hw =
4965                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4966         struct ixgbe_dcb_config *dcb_config =
4967                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4968
4969         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4970                 ixgbe_fc_none,
4971                 ixgbe_fc_rx_pause,
4972                 ixgbe_fc_tx_pause,
4973                 ixgbe_fc_full
4974         };
4975
4976         PMD_INIT_FUNC_TRACE();
4977
4978         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4979         tc_num = map[pfc_conf->priority];
4980         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4981         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4982         /*
4983          * At least reserve one Ethernet frame for watermark
4984          * high_water/low_water in kilo bytes for ixgbe
4985          */
4986         max_high_water = (rx_buf_size -
4987                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4988         if ((pfc_conf->fc.high_water > max_high_water) ||
4989             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4990                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4991                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4992                 return -EINVAL;
4993         }
4994
4995         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4996         hw->fc.pause_time = pfc_conf->fc.pause_time;
4997         hw->fc.send_xon = pfc_conf->fc.send_xon;
4998         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4999         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5000
5001         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5002
5003         /* Not negotiated is not an error case */
5004         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5005                 return 0;
5006
5007         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5008         return -EIO;
5009 }
5010
5011 static int
5012 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5013                           struct rte_eth_rss_reta_entry64 *reta_conf,
5014                           uint16_t reta_size)
5015 {
5016         uint16_t i, sp_reta_size;
5017         uint8_t j, mask;
5018         uint32_t reta, r;
5019         uint16_t idx, shift;
5020         struct ixgbe_adapter *adapter = dev->data->dev_private;
5021         struct rte_eth_dev_data *dev_data = dev->data;
5022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5023         uint32_t reta_reg;
5024
5025         PMD_INIT_FUNC_TRACE();
5026
5027         if (!dev_data->dev_started) {
5028                 PMD_DRV_LOG(ERR,
5029                         "port %d must be started before rss reta update",
5030                          dev_data->port_id);
5031                 return -EIO;
5032         }
5033
5034         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5035                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5036                         "NIC.");
5037                 return -ENOTSUP;
5038         }
5039
5040         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5041         if (reta_size != sp_reta_size) {
5042                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5043                         "(%d) doesn't match the number hardware can supported "
5044                         "(%d)", reta_size, sp_reta_size);
5045                 return -EINVAL;
5046         }
5047
5048         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5049                 idx = i / RTE_RETA_GROUP_SIZE;
5050                 shift = i % RTE_RETA_GROUP_SIZE;
5051                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5052                                                 IXGBE_4_BIT_MASK);
5053                 if (!mask)
5054                         continue;
5055                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5056                 if (mask == IXGBE_4_BIT_MASK)
5057                         r = 0;
5058                 else
5059                         r = IXGBE_READ_REG(hw, reta_reg);
5060                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5061                         if (mask & (0x1 << j))
5062                                 reta |= reta_conf[idx].reta[shift + j] <<
5063                                                         (CHAR_BIT * j);
5064                         else
5065                                 reta |= r & (IXGBE_8_BIT_MASK <<
5066                                                 (CHAR_BIT * j));
5067                 }
5068                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5069         }
5070         adapter->rss_reta_updated = 1;
5071
5072         return 0;
5073 }
5074
5075 static int
5076 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5077                          struct rte_eth_rss_reta_entry64 *reta_conf,
5078                          uint16_t reta_size)
5079 {
5080         uint16_t i, sp_reta_size;
5081         uint8_t j, mask;
5082         uint32_t reta;
5083         uint16_t idx, shift;
5084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5085         uint32_t reta_reg;
5086
5087         PMD_INIT_FUNC_TRACE();
5088         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5089         if (reta_size != sp_reta_size) {
5090                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5091                         "(%d) doesn't match the number hardware can supported "
5092                         "(%d)", reta_size, sp_reta_size);
5093                 return -EINVAL;
5094         }
5095
5096         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5097                 idx = i / RTE_RETA_GROUP_SIZE;
5098                 shift = i % RTE_RETA_GROUP_SIZE;
5099                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5100                                                 IXGBE_4_BIT_MASK);
5101                 if (!mask)
5102                         continue;
5103
5104                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5105                 reta = IXGBE_READ_REG(hw, reta_reg);
5106                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5107                         if (mask & (0x1 << j))
5108                                 reta_conf[idx].reta[shift + j] =
5109                                         ((reta >> (CHAR_BIT * j)) &
5110                                                 IXGBE_8_BIT_MASK);
5111                 }
5112         }
5113
5114         return 0;
5115 }
5116
5117 static int
5118 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5119                                 uint32_t index, uint32_t pool)
5120 {
5121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5122         uint32_t enable_addr = 1;
5123
5124         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5125                              pool, enable_addr);
5126 }
5127
5128 static void
5129 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5130 {
5131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5132
5133         ixgbe_clear_rar(hw, index);
5134 }
5135
5136 static int
5137 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5138 {
5139         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5140
5141         ixgbe_remove_rar(dev, 0);
5142         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5143
5144         return 0;
5145 }
5146
5147 static bool
5148 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5149 {
5150         if (strcmp(dev->device->driver->name, drv->driver.name))
5151                 return false;
5152
5153         return true;
5154 }
5155
5156 bool
5157 is_ixgbe_supported(struct rte_eth_dev *dev)
5158 {
5159         return is_device_supported(dev, &rte_ixgbe_pmd);
5160 }
5161
5162 static int
5163 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5164 {
5165         uint32_t hlreg0;
5166         uint32_t maxfrs;
5167         struct ixgbe_hw *hw;
5168         struct rte_eth_dev_info dev_info;
5169         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5170         struct rte_eth_dev_data *dev_data = dev->data;
5171         int ret;
5172
5173         ret = ixgbe_dev_info_get(dev, &dev_info);
5174         if (ret != 0)
5175                 return ret;
5176
5177         /* check that mtu is within the allowed range */
5178         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5179                 return -EINVAL;
5180
5181         /* If device is started, refuse mtu that requires the support of
5182          * scattered packets when this feature has not been enabled before.
5183          */
5184         if (dev_data->dev_started && !dev_data->scattered_rx &&
5185             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5186              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5187                 PMD_INIT_LOG(ERR, "Stop port first.");
5188                 return -EINVAL;
5189         }
5190
5191         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5192         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5193
5194         /* switch to jumbo mode if needed */
5195         if (frame_size > IXGBE_ETH_MAX_LEN) {
5196                 dev->data->dev_conf.rxmode.offloads |=
5197                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5198                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5199         } else {
5200                 dev->data->dev_conf.rxmode.offloads &=
5201                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5202                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5203         }
5204         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5205
5206         /* update max frame size */
5207         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5208
5209         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5210         maxfrs &= 0x0000FFFF;
5211         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5212         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5213
5214         return 0;
5215 }
5216
5217 /*
5218  * Virtual Function operations
5219  */
5220 static void
5221 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5222 {
5223         struct ixgbe_interrupt *intr =
5224                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5225         struct ixgbe_hw *hw =
5226                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5227
5228         PMD_INIT_FUNC_TRACE();
5229
5230         /* Clear interrupt mask to stop from interrupts being generated */
5231         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5232
5233         IXGBE_WRITE_FLUSH(hw);
5234
5235         /* Clear mask value. */
5236         intr->mask = 0;
5237 }
5238
5239 static void
5240 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5241 {
5242         struct ixgbe_interrupt *intr =
5243                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5244         struct ixgbe_hw *hw =
5245                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5246
5247         PMD_INIT_FUNC_TRACE();
5248
5249         /* VF enable interrupt autoclean */
5250         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5251         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5252         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5253
5254         IXGBE_WRITE_FLUSH(hw);
5255
5256         /* Save IXGBE_VTEIMS value to mask. */
5257         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5258 }
5259
5260 static int
5261 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5262 {
5263         struct rte_eth_conf *conf = &dev->data->dev_conf;
5264         struct ixgbe_adapter *adapter = dev->data->dev_private;
5265
5266         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5267                      dev->data->port_id);
5268
5269         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5270                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5271
5272         /*
5273          * VF has no ability to enable/disable HW CRC
5274          * Keep the persistent behavior the same as Host PF
5275          */
5276 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5277         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5278                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5279                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5280         }
5281 #else
5282         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5283                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5284                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5285         }
5286 #endif
5287
5288         /*
5289          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5290          * allocation or vector Rx preconditions we will reset it.
5291          */
5292         adapter->rx_bulk_alloc_allowed = true;
5293         adapter->rx_vec_allowed = true;
5294
5295         return 0;
5296 }
5297
5298 static int
5299 ixgbevf_dev_start(struct rte_eth_dev *dev)
5300 {
5301         struct ixgbe_hw *hw =
5302                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303         uint32_t intr_vector = 0;
5304         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5305         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5306
5307         int err, mask = 0;
5308
5309         PMD_INIT_FUNC_TRACE();
5310
5311         /* Stop the link setup handler before resetting the HW. */
5312         ixgbe_dev_wait_setup_link_complete(dev, 0);
5313
5314         err = hw->mac.ops.reset_hw(hw);
5315
5316         /**
5317          * In this case, reuses the MAC address assigned by VF
5318          * initialization.
5319          */
5320         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5321                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5322                 return err;
5323         }
5324
5325         hw->mac.get_link_status = true;
5326
5327         /* negotiate mailbox API version to use with the PF. */
5328         ixgbevf_negotiate_api(hw);
5329
5330         ixgbevf_dev_tx_init(dev);
5331
5332         /* This can fail when allocating mbufs for descriptor rings */
5333         err = ixgbevf_dev_rx_init(dev);
5334         if (err) {
5335                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5336                 ixgbe_dev_clear_queues(dev);
5337                 return err;
5338         }
5339
5340         /* Set vfta */
5341         ixgbevf_set_vfta_all(dev, 1);
5342
5343         /* Set HW strip */
5344         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5345                 ETH_VLAN_EXTEND_MASK;
5346         err = ixgbevf_vlan_offload_config(dev, mask);
5347         if (err) {
5348                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5349                 ixgbe_dev_clear_queues(dev);
5350                 return err;
5351         }
5352
5353         ixgbevf_dev_rxtx_start(dev);
5354
5355         /* check and configure queue intr-vector mapping */
5356         if (rte_intr_cap_multiple(intr_handle) &&
5357             dev->data->dev_conf.intr_conf.rxq) {
5358                 /* According to datasheet, only vector 0/1/2 can be used,
5359                  * now only one vector is used for Rx queue
5360                  */
5361                 intr_vector = 1;
5362                 if (rte_intr_efd_enable(intr_handle, intr_vector)) {
5363                         ixgbe_dev_clear_queues(dev);
5364                         return -1;
5365                 }
5366         }
5367
5368         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5369                 intr_handle->intr_vec =
5370                         rte_zmalloc("intr_vec",
5371                                     dev->data->nb_rx_queues * sizeof(int), 0);
5372                 if (intr_handle->intr_vec == NULL) {
5373                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5374                                      " intr_vec", dev->data->nb_rx_queues);
5375                         ixgbe_dev_clear_queues(dev);
5376                         return -ENOMEM;
5377                 }
5378         }
5379         ixgbevf_configure_msix(dev);
5380
5381         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5382          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5383          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5384          * is not cleared, it will fail when following rte_intr_enable( ) tries
5385          * to map Rx queue interrupt to other VFIO vectors.
5386          * So clear uio/vfio intr/evevnfd first to avoid failure.
5387          */
5388         rte_intr_disable(intr_handle);
5389
5390         rte_intr_enable(intr_handle);
5391
5392         /* Re-enable interrupt for VF */
5393         ixgbevf_intr_enable(dev);
5394
5395         /*
5396          * Update link status right before return, because it may
5397          * start link configuration process in a separate thread.
5398          */
5399         ixgbevf_dev_link_update(dev, 0);
5400
5401         hw->adapter_stopped = false;
5402
5403         return 0;
5404 }
5405
5406 static int
5407 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5408 {
5409         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5410         struct ixgbe_adapter *adapter = dev->data->dev_private;
5411         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5412         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5413
5414         if (hw->adapter_stopped)
5415                 return 0;
5416
5417         PMD_INIT_FUNC_TRACE();
5418
5419         ixgbe_dev_wait_setup_link_complete(dev, 0);
5420
5421         ixgbevf_intr_disable(dev);
5422
5423         dev->data->dev_started = 0;
5424         hw->adapter_stopped = 1;
5425         ixgbe_stop_adapter(hw);
5426
5427         /*
5428           * Clear what we set, but we still keep shadow_vfta to
5429           * restore after device starts
5430           */
5431         ixgbevf_set_vfta_all(dev, 0);
5432
5433         /* Clear stored conf */
5434         dev->data->scattered_rx = 0;
5435
5436         ixgbe_dev_clear_queues(dev);
5437
5438         /* Clean datapath event and queue/vec mapping */
5439         rte_intr_efd_disable(intr_handle);
5440         if (intr_handle->intr_vec != NULL) {
5441                 rte_free(intr_handle->intr_vec);
5442                 intr_handle->intr_vec = NULL;
5443         }
5444
5445         adapter->rss_reta_updated = 0;
5446
5447         return 0;
5448 }
5449
5450 static int
5451 ixgbevf_dev_close(struct rte_eth_dev *dev)
5452 {
5453         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5454         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5455         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5456         int ret;
5457
5458         PMD_INIT_FUNC_TRACE();
5459         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5460                 return 0;
5461
5462         ixgbe_reset_hw(hw);
5463
5464         ret = ixgbevf_dev_stop(dev);
5465
5466         ixgbe_dev_free_queues(dev);
5467
5468         /**
5469          * Remove the VF MAC address ro ensure
5470          * that the VF traffic goes to the PF
5471          * after stop, close and detach of the VF
5472          **/
5473         ixgbevf_remove_mac_addr(dev, 0);
5474
5475         rte_intr_disable(intr_handle);
5476         rte_intr_callback_unregister(intr_handle,
5477                                      ixgbevf_dev_interrupt_handler, dev);
5478
5479         return ret;
5480 }
5481
5482 /*
5483  * Reset VF device
5484  */
5485 static int
5486 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5487 {
5488         int ret;
5489
5490         ret = eth_ixgbevf_dev_uninit(dev);
5491         if (ret)
5492                 return ret;
5493
5494         ret = eth_ixgbevf_dev_init(dev);
5495
5496         return ret;
5497 }
5498
5499 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5500 {
5501         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5502         struct ixgbe_vfta *shadow_vfta =
5503                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5504         int i = 0, j = 0, vfta = 0, mask = 1;
5505
5506         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5507                 vfta = shadow_vfta->vfta[i];
5508                 if (vfta) {
5509                         mask = 1;
5510                         for (j = 0; j < 32; j++) {
5511                                 if (vfta & mask)
5512                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5513                                                        on, false);
5514                                 mask <<= 1;
5515                         }
5516                 }
5517         }
5518
5519 }
5520
5521 static int
5522 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5523 {
5524         struct ixgbe_hw *hw =
5525                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5526         struct ixgbe_vfta *shadow_vfta =
5527                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5528         uint32_t vid_idx = 0;
5529         uint32_t vid_bit = 0;
5530         int ret = 0;
5531
5532         PMD_INIT_FUNC_TRACE();
5533
5534         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5535         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5536         if (ret) {
5537                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5538                 return ret;
5539         }
5540         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5541         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5542
5543         /* Save what we set and retore it after device reset */
5544         if (on)
5545                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5546         else
5547                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5548
5549         return 0;
5550 }
5551
5552 static void
5553 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5554 {
5555         struct ixgbe_hw *hw =
5556                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5557         uint32_t ctrl;
5558
5559         PMD_INIT_FUNC_TRACE();
5560
5561         if (queue >= hw->mac.max_rx_queues)
5562                 return;
5563
5564         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5565         if (on)
5566                 ctrl |= IXGBE_RXDCTL_VME;
5567         else
5568                 ctrl &= ~IXGBE_RXDCTL_VME;
5569         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5570
5571         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5572 }
5573
5574 static int
5575 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5576 {
5577         struct ixgbe_rx_queue *rxq;
5578         uint16_t i;
5579         int on = 0;
5580
5581         /* VF function only support hw strip feature, others are not support */
5582         if (mask & ETH_VLAN_STRIP_MASK) {
5583                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5584                         rxq = dev->data->rx_queues[i];
5585                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5586                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5587                 }
5588         }
5589
5590         return 0;
5591 }
5592
5593 static int
5594 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5595 {
5596         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5597
5598         ixgbevf_vlan_offload_config(dev, mask);
5599
5600         return 0;
5601 }
5602
5603 int
5604 ixgbe_vt_check(struct ixgbe_hw *hw)
5605 {
5606         uint32_t reg_val;
5607
5608         /* if Virtualization Technology is enabled */
5609         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5610         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5611                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5612                 return -1;
5613         }
5614
5615         return 0;
5616 }
5617
5618 static uint32_t
5619 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5620 {
5621         uint32_t vector = 0;
5622
5623         switch (hw->mac.mc_filter_type) {
5624         case 0:   /* use bits [47:36] of the address */
5625                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5626                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5627                 break;
5628         case 1:   /* use bits [46:35] of the address */
5629                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5630                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5631                 break;
5632         case 2:   /* use bits [45:34] of the address */
5633                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5634                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5635                 break;
5636         case 3:   /* use bits [43:32] of the address */
5637                 vector = ((uc_addr->addr_bytes[4]) |
5638                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5639                 break;
5640         default:  /* Invalid mc_filter_type */
5641                 break;
5642         }
5643
5644         /* vector can only be 12-bits or boundary will be exceeded */
5645         vector &= 0xFFF;
5646         return vector;
5647 }
5648
5649 static int
5650 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5651                         struct rte_ether_addr *mac_addr, uint8_t on)
5652 {
5653         uint32_t vector;
5654         uint32_t uta_idx;
5655         uint32_t reg_val;
5656         uint32_t uta_shift;
5657         uint32_t rc;
5658         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5659         const uint32_t ixgbe_uta_bit_shift = 5;
5660         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5661         const uint32_t bit1 = 0x1;
5662
5663         struct ixgbe_hw *hw =
5664                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5665         struct ixgbe_uta_info *uta_info =
5666                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5667
5668         /* The UTA table only exists on 82599 hardware and newer */
5669         if (hw->mac.type < ixgbe_mac_82599EB)
5670                 return -ENOTSUP;
5671
5672         vector = ixgbe_uta_vector(hw, mac_addr);
5673         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5674         uta_shift = vector & ixgbe_uta_bit_mask;
5675
5676         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5677         if (rc == on)
5678                 return 0;
5679
5680         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5681         if (on) {
5682                 uta_info->uta_in_use++;
5683                 reg_val |= (bit1 << uta_shift);
5684                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5685         } else {
5686                 uta_info->uta_in_use--;
5687                 reg_val &= ~(bit1 << uta_shift);
5688                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5689         }
5690
5691         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5692
5693         if (uta_info->uta_in_use > 0)
5694                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5695                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5696         else
5697                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5698
5699         return 0;
5700 }
5701
5702 static int
5703 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5704 {
5705         int i;
5706         struct ixgbe_hw *hw =
5707                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5708         struct ixgbe_uta_info *uta_info =
5709                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5710
5711         /* The UTA table only exists on 82599 hardware and newer */
5712         if (hw->mac.type < ixgbe_mac_82599EB)
5713                 return -ENOTSUP;
5714
5715         if (on) {
5716                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5717                         uta_info->uta_shadow[i] = ~0;
5718                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5719                 }
5720         } else {
5721                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5722                         uta_info->uta_shadow[i] = 0;
5723                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5724                 }
5725         }
5726         return 0;
5727
5728 }
5729
5730 uint32_t
5731 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5732 {
5733         uint32_t new_val = orig_val;
5734
5735         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5736                 new_val |= IXGBE_VMOLR_AUPE;
5737         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5738                 new_val |= IXGBE_VMOLR_ROMPE;
5739         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5740                 new_val |= IXGBE_VMOLR_ROPE;
5741         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5742                 new_val |= IXGBE_VMOLR_BAM;
5743         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5744                 new_val |= IXGBE_VMOLR_MPE;
5745
5746         return new_val;
5747 }
5748
5749 static int
5750 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5751 {
5752         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5753         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5754         struct ixgbe_interrupt *intr =
5755                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5756         struct ixgbe_hw *hw =
5757                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5758         uint32_t vec = IXGBE_MISC_VEC_ID;
5759
5760         if (rte_intr_allow_others(intr_handle))
5761                 vec = IXGBE_RX_VEC_START;
5762         intr->mask |= (1 << vec);
5763         RTE_SET_USED(queue_id);
5764         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5765
5766         rte_intr_ack(intr_handle);
5767
5768         return 0;
5769 }
5770
5771 static int
5772 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5773 {
5774         struct ixgbe_interrupt *intr =
5775                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5776         struct ixgbe_hw *hw =
5777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5778         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5779         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5780         uint32_t vec = IXGBE_MISC_VEC_ID;
5781
5782         if (rte_intr_allow_others(intr_handle))
5783                 vec = IXGBE_RX_VEC_START;
5784         intr->mask &= ~(1 << vec);
5785         RTE_SET_USED(queue_id);
5786         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5787
5788         return 0;
5789 }
5790
5791 static int
5792 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5793 {
5794         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5795         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5796         uint32_t mask;
5797         struct ixgbe_hw *hw =
5798                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5799         struct ixgbe_interrupt *intr =
5800                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5801
5802         if (queue_id < 16) {
5803                 ixgbe_disable_intr(hw);
5804                 intr->mask |= (1 << queue_id);
5805                 ixgbe_enable_intr(dev);
5806         } else if (queue_id < 32) {
5807                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5808                 mask &= (1 << queue_id);
5809                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5810         } else if (queue_id < 64) {
5811                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5812                 mask &= (1 << (queue_id - 32));
5813                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5814         }
5815         rte_intr_ack(intr_handle);
5816
5817         return 0;
5818 }
5819
5820 static int
5821 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5822 {
5823         uint32_t mask;
5824         struct ixgbe_hw *hw =
5825                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5826         struct ixgbe_interrupt *intr =
5827                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5828
5829         if (queue_id < 16) {
5830                 ixgbe_disable_intr(hw);
5831                 intr->mask &= ~(1 << queue_id);
5832                 ixgbe_enable_intr(dev);
5833         } else if (queue_id < 32) {
5834                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5835                 mask &= ~(1 << queue_id);
5836                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5837         } else if (queue_id < 64) {
5838                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5839                 mask &= ~(1 << (queue_id - 32));
5840                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5841         }
5842
5843         return 0;
5844 }
5845
5846 static void
5847 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5848                      uint8_t queue, uint8_t msix_vector)
5849 {
5850         uint32_t tmp, idx;
5851
5852         if (direction == -1) {
5853                 /* other causes */
5854                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5855                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5856                 tmp &= ~0xFF;
5857                 tmp |= msix_vector;
5858                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5859         } else {
5860                 /* rx or tx cause */
5861                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5862                 idx = ((16 * (queue & 1)) + (8 * direction));
5863                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5864                 tmp &= ~(0xFF << idx);
5865                 tmp |= (msix_vector << idx);
5866                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5867         }
5868 }
5869
5870 /**
5871  * set the IVAR registers, mapping interrupt causes to vectors
5872  * @param hw
5873  *  pointer to ixgbe_hw struct
5874  * @direction
5875  *  0 for Rx, 1 for Tx, -1 for other causes
5876  * @queue
5877  *  queue to map the corresponding interrupt to
5878  * @msix_vector
5879  *  the vector to map to the corresponding queue
5880  */
5881 static void
5882 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5883                    uint8_t queue, uint8_t msix_vector)
5884 {
5885         uint32_t tmp, idx;
5886
5887         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5888         if (hw->mac.type == ixgbe_mac_82598EB) {
5889                 if (direction == -1)
5890                         direction = 0;
5891                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5892                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5893                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5894                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5895                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5896         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5897                         (hw->mac.type == ixgbe_mac_X540) ||
5898                         (hw->mac.type == ixgbe_mac_X550) ||
5899                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
5900                 if (direction == -1) {
5901                         /* other causes */
5902                         idx = ((queue & 1) * 8);
5903                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5904                         tmp &= ~(0xFF << idx);
5905                         tmp |= (msix_vector << idx);
5906                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5907                 } else {
5908                         /* rx or tx causes */
5909                         idx = ((16 * (queue & 1)) + (8 * direction));
5910                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5911                         tmp &= ~(0xFF << idx);
5912                         tmp |= (msix_vector << idx);
5913                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5914                 }
5915         }
5916 }
5917
5918 static void
5919 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5920 {
5921         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5922         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5923         struct ixgbe_hw *hw =
5924                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5925         uint32_t q_idx;
5926         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5927         uint32_t base = IXGBE_MISC_VEC_ID;
5928
5929         /* Configure VF other cause ivar */
5930         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5931
5932         /* won't configure msix register if no mapping is done
5933          * between intr vector and event fd.
5934          */
5935         if (!rte_intr_dp_is_en(intr_handle))
5936                 return;
5937
5938         if (rte_intr_allow_others(intr_handle)) {
5939                 base = IXGBE_RX_VEC_START;
5940                 vector_idx = IXGBE_RX_VEC_START;
5941         }
5942
5943         /* Configure all RX queues of VF */
5944         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5945                 /* Force all queue use vector 0,
5946                  * as IXGBE_VF_MAXMSIVECOTR = 1
5947                  */
5948                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5949                 intr_handle->intr_vec[q_idx] = vector_idx;
5950                 if (vector_idx < base + intr_handle->nb_efd - 1)
5951                         vector_idx++;
5952         }
5953
5954         /* As RX queue setting above show, all queues use the vector 0.
5955          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5956          */
5957         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5958                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5959                         | IXGBE_EITR_CNT_WDIS);
5960 }
5961
5962 /**
5963  * Sets up the hardware to properly generate MSI-X interrupts
5964  * @hw
5965  *  board private structure
5966  */
5967 static void
5968 ixgbe_configure_msix(struct rte_eth_dev *dev)
5969 {
5970         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5971         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5972         struct ixgbe_hw *hw =
5973                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5974         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5975         uint32_t vec = IXGBE_MISC_VEC_ID;
5976         uint32_t mask;
5977         uint32_t gpie;
5978
5979         /* won't configure msix register if no mapping is done
5980          * between intr vector and event fd
5981          * but if misx has been enabled already, need to configure
5982          * auto clean, auto mask and throttling.
5983          */
5984         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5985         if (!rte_intr_dp_is_en(intr_handle) &&
5986             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5987                 return;
5988
5989         if (rte_intr_allow_others(intr_handle))
5990                 vec = base = IXGBE_RX_VEC_START;
5991
5992         /* setup GPIE for MSI-x mode */
5993         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5994         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5995                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5996         /* auto clearing and auto setting corresponding bits in EIMS
5997          * when MSI-X interrupt is triggered
5998          */
5999         if (hw->mac.type == ixgbe_mac_82598EB) {
6000                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6001         } else {
6002                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6003                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6004         }
6005         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6006
6007         /* Populate the IVAR table and set the ITR values to the
6008          * corresponding register.
6009          */
6010         if (rte_intr_dp_is_en(intr_handle)) {
6011                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6012                         queue_id++) {
6013                         /* by default, 1:1 mapping */
6014                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6015                         intr_handle->intr_vec[queue_id] = vec;
6016                         if (vec < base + intr_handle->nb_efd - 1)
6017                                 vec++;
6018                 }
6019
6020                 switch (hw->mac.type) {
6021                 case ixgbe_mac_82598EB:
6022                         ixgbe_set_ivar_map(hw, -1,
6023                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6024                                            IXGBE_MISC_VEC_ID);
6025                         break;
6026                 case ixgbe_mac_82599EB:
6027                 case ixgbe_mac_X540:
6028                 case ixgbe_mac_X550:
6029                 case ixgbe_mac_X550EM_x:
6030                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6031                         break;
6032                 default:
6033                         break;
6034                 }
6035         }
6036         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6037                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6038                         | IXGBE_EITR_CNT_WDIS);
6039
6040         /* set up to autoclear timer, and the vectors */
6041         mask = IXGBE_EIMS_ENABLE_MASK;
6042         mask &= ~(IXGBE_EIMS_OTHER |
6043                   IXGBE_EIMS_MAILBOX |
6044                   IXGBE_EIMS_LSC);
6045
6046         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6047 }
6048
6049 int
6050 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6051                            uint16_t queue_idx, uint16_t tx_rate)
6052 {
6053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6054         struct rte_eth_rxmode *rxmode;
6055         uint32_t rf_dec, rf_int;
6056         uint32_t bcnrc_val;
6057         uint16_t link_speed = dev->data->dev_link.link_speed;
6058
6059         if (queue_idx >= hw->mac.max_tx_queues)
6060                 return -EINVAL;
6061
6062         if (tx_rate != 0) {
6063                 /* Calculate the rate factor values to set */
6064                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6065                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6066                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6067
6068                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6069                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6070                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6071                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6072         } else {
6073                 bcnrc_val = 0;
6074         }
6075
6076         rxmode = &dev->data->dev_conf.rxmode;
6077         /*
6078          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6079          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6080          * set as 0x4.
6081          */
6082         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6083             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6084                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6085                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6086         else
6087                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6088                         IXGBE_MMW_SIZE_DEFAULT);
6089
6090         /* Set RTTBCNRC of queue X */
6091         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6092         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6093         IXGBE_WRITE_FLUSH(hw);
6094
6095         return 0;
6096 }
6097
6098 static int
6099 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6100                      __rte_unused uint32_t index,
6101                      __rte_unused uint32_t pool)
6102 {
6103         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6104         int diag;
6105
6106         /*
6107          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6108          * operation. Trap this case to avoid exhausting the [very limited]
6109          * set of PF resources used to store VF MAC addresses.
6110          */
6111         if (memcmp(hw->mac.perm_addr, mac_addr,
6112                         sizeof(struct rte_ether_addr)) == 0)
6113                 return -1;
6114         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6115         if (diag != 0)
6116                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6117                             RTE_ETHER_ADDR_PRT_FMT " - diag=%d",
6118                             RTE_ETHER_ADDR_BYTES(mac_addr), diag);
6119         return diag;
6120 }
6121
6122 static void
6123 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6124 {
6125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6126         struct rte_ether_addr *perm_addr =
6127                 (struct rte_ether_addr *)hw->mac.perm_addr;
6128         struct rte_ether_addr *mac_addr;
6129         uint32_t i;
6130         int diag;
6131
6132         /*
6133          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6134          * not support the deletion of a given MAC address.
6135          * Instead, it imposes to delete all MAC addresses, then to add again
6136          * all MAC addresses with the exception of the one to be deleted.
6137          */
6138         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6139
6140         /*
6141          * Add again all MAC addresses, with the exception of the deleted one
6142          * and of the permanent MAC address.
6143          */
6144         for (i = 0, mac_addr = dev->data->mac_addrs;
6145              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6146                 /* Skip the deleted MAC address */
6147                 if (i == index)
6148                         continue;
6149                 /* Skip NULL MAC addresses */
6150                 if (rte_is_zero_ether_addr(mac_addr))
6151                         continue;
6152                 /* Skip the permanent MAC address */
6153                 if (memcmp(perm_addr, mac_addr,
6154                                 sizeof(struct rte_ether_addr)) == 0)
6155                         continue;
6156                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6157                 if (diag != 0)
6158                         PMD_DRV_LOG(ERR,
6159                                     "Adding again MAC address "
6160                                      RTE_ETHER_ADDR_PRT_FMT " failed "
6161                                     "diag=%d", RTE_ETHER_ADDR_BYTES(mac_addr),
6162                                     diag);
6163         }
6164 }
6165
6166 static int
6167 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6168                         struct rte_ether_addr *addr)
6169 {
6170         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6171
6172         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6173
6174         return 0;
6175 }
6176
6177 int
6178 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6179                         struct rte_eth_syn_filter *filter,
6180                         bool add)
6181 {
6182         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6183         struct ixgbe_filter_info *filter_info =
6184                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6185         uint32_t syn_info;
6186         uint32_t synqf;
6187
6188         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6189                 return -EINVAL;
6190
6191         syn_info = filter_info->syn_info;
6192
6193         if (add) {
6194                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6195                         return -EINVAL;
6196                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6197                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6198
6199                 if (filter->hig_pri)
6200                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6201                 else
6202                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6203         } else {
6204                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6205                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6206                         return -ENOENT;
6207                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6208         }
6209
6210         filter_info->syn_info = synqf;
6211         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6212         IXGBE_WRITE_FLUSH(hw);
6213         return 0;
6214 }
6215
6216
6217 static inline enum ixgbe_5tuple_protocol
6218 convert_protocol_type(uint8_t protocol_value)
6219 {
6220         if (protocol_value == IPPROTO_TCP)
6221                 return IXGBE_FILTER_PROTOCOL_TCP;
6222         else if (protocol_value == IPPROTO_UDP)
6223                 return IXGBE_FILTER_PROTOCOL_UDP;
6224         else if (protocol_value == IPPROTO_SCTP)
6225                 return IXGBE_FILTER_PROTOCOL_SCTP;
6226         else
6227                 return IXGBE_FILTER_PROTOCOL_NONE;
6228 }
6229
6230 /* inject a 5-tuple filter to HW */
6231 static inline void
6232 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6233                            struct ixgbe_5tuple_filter *filter)
6234 {
6235         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6236         int i;
6237         uint32_t ftqf, sdpqf;
6238         uint32_t l34timir = 0;
6239         uint8_t mask = 0xff;
6240
6241         i = filter->index;
6242
6243         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6244                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6245         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6246
6247         ftqf = (uint32_t)(filter->filter_info.proto &
6248                 IXGBE_FTQF_PROTOCOL_MASK);
6249         ftqf |= (uint32_t)((filter->filter_info.priority &
6250                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6251         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6252                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6253         if (filter->filter_info.dst_ip_mask == 0)
6254                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6255         if (filter->filter_info.src_port_mask == 0)
6256                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6257         if (filter->filter_info.dst_port_mask == 0)
6258                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6259         if (filter->filter_info.proto_mask == 0)
6260                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6261         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6262         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6263         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6264
6265         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6266         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6267         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6268         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6269
6270         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6271         l34timir |= (uint32_t)(filter->queue <<
6272                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6273         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6274 }
6275
6276 /*
6277  * add a 5tuple filter
6278  *
6279  * @param
6280  * dev: Pointer to struct rte_eth_dev.
6281  * index: the index the filter allocates.
6282  * filter: ponter to the filter that will be added.
6283  * rx_queue: the queue id the filter assigned to.
6284  *
6285  * @return
6286  *    - On success, zero.
6287  *    - On failure, a negative value.
6288  */
6289 static int
6290 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6291                         struct ixgbe_5tuple_filter *filter)
6292 {
6293         struct ixgbe_filter_info *filter_info =
6294                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6295         int i, idx, shift;
6296
6297         /*
6298          * look for an unused 5tuple filter index,
6299          * and insert the filter to list.
6300          */
6301         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6302                 idx = i / (sizeof(uint32_t) * NBBY);
6303                 shift = i % (sizeof(uint32_t) * NBBY);
6304                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6305                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6306                         filter->index = i;
6307                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6308                                           filter,
6309                                           entries);
6310                         break;
6311                 }
6312         }
6313         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6314                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6315                 return -ENOSYS;
6316         }
6317
6318         ixgbe_inject_5tuple_filter(dev, filter);
6319
6320         return 0;
6321 }
6322
6323 /*
6324  * remove a 5tuple filter
6325  *
6326  * @param
6327  * dev: Pointer to struct rte_eth_dev.
6328  * filter: the pointer of the filter will be removed.
6329  */
6330 static void
6331 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6332                         struct ixgbe_5tuple_filter *filter)
6333 {
6334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6335         struct ixgbe_filter_info *filter_info =
6336                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6337         uint16_t index = filter->index;
6338
6339         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6340                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6341         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6342         rte_free(filter);
6343
6344         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6345         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6346         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6347         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6348         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6349 }
6350
6351 static int
6352 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6353 {
6354         struct ixgbe_hw *hw;
6355         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6356         struct rte_eth_dev_data *dev_data = dev->data;
6357
6358         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6359
6360         if (mtu < RTE_ETHER_MIN_MTU ||
6361                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6362                 return -EINVAL;
6363
6364         /* If device is started, refuse mtu that requires the support of
6365          * scattered packets when this feature has not been enabled before.
6366          */
6367         if (dev_data->dev_started && !dev_data->scattered_rx &&
6368             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6369              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6370                 PMD_INIT_LOG(ERR, "Stop port first.");
6371                 return -EINVAL;
6372         }
6373
6374         /*
6375          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6376          * request of the version 2.0 of the mailbox API.
6377          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6378          * of the mailbox API.
6379          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6380          * prior to 3.11.33 which contains the following change:
6381          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6382          */
6383         if (ixgbevf_rlpml_set_vf(hw, max_frame))
6384                 return -EINVAL;
6385
6386         /* update max frame size */
6387         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6388         return 0;
6389 }
6390
6391 static inline struct ixgbe_5tuple_filter *
6392 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6393                         struct ixgbe_5tuple_filter_info *key)
6394 {
6395         struct ixgbe_5tuple_filter *it;
6396
6397         TAILQ_FOREACH(it, filter_list, entries) {
6398                 if (memcmp(key, &it->filter_info,
6399                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6400                         return it;
6401                 }
6402         }
6403         return NULL;
6404 }
6405
6406 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6407 static inline int
6408 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6409                         struct ixgbe_5tuple_filter_info *filter_info)
6410 {
6411         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6412                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6413                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6414                 return -EINVAL;
6415
6416         switch (filter->dst_ip_mask) {
6417         case UINT32_MAX:
6418                 filter_info->dst_ip_mask = 0;
6419                 filter_info->dst_ip = filter->dst_ip;
6420                 break;
6421         case 0:
6422                 filter_info->dst_ip_mask = 1;
6423                 break;
6424         default:
6425                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6426                 return -EINVAL;
6427         }
6428
6429         switch (filter->src_ip_mask) {
6430         case UINT32_MAX:
6431                 filter_info->src_ip_mask = 0;
6432                 filter_info->src_ip = filter->src_ip;
6433                 break;
6434         case 0:
6435                 filter_info->src_ip_mask = 1;
6436                 break;
6437         default:
6438                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6439                 return -EINVAL;
6440         }
6441
6442         switch (filter->dst_port_mask) {
6443         case UINT16_MAX:
6444                 filter_info->dst_port_mask = 0;
6445                 filter_info->dst_port = filter->dst_port;
6446                 break;
6447         case 0:
6448                 filter_info->dst_port_mask = 1;
6449                 break;
6450         default:
6451                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6452                 return -EINVAL;
6453         }
6454
6455         switch (filter->src_port_mask) {
6456         case UINT16_MAX:
6457                 filter_info->src_port_mask = 0;
6458                 filter_info->src_port = filter->src_port;
6459                 break;
6460         case 0:
6461                 filter_info->src_port_mask = 1;
6462                 break;
6463         default:
6464                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6465                 return -EINVAL;
6466         }
6467
6468         switch (filter->proto_mask) {
6469         case UINT8_MAX:
6470                 filter_info->proto_mask = 0;
6471                 filter_info->proto =
6472                         convert_protocol_type(filter->proto);
6473                 break;
6474         case 0:
6475                 filter_info->proto_mask = 1;
6476                 break;
6477         default:
6478                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6479                 return -EINVAL;
6480         }
6481
6482         filter_info->priority = (uint8_t)filter->priority;
6483         return 0;
6484 }
6485
6486 /*
6487  * add or delete a ntuple filter
6488  *
6489  * @param
6490  * dev: Pointer to struct rte_eth_dev.
6491  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6492  * add: if true, add filter, if false, remove filter
6493  *
6494  * @return
6495  *    - On success, zero.
6496  *    - On failure, a negative value.
6497  */
6498 int
6499 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6500                         struct rte_eth_ntuple_filter *ntuple_filter,
6501                         bool add)
6502 {
6503         struct ixgbe_filter_info *filter_info =
6504                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6505         struct ixgbe_5tuple_filter_info filter_5tuple;
6506         struct ixgbe_5tuple_filter *filter;
6507         int ret;
6508
6509         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6510                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6511                 return -EINVAL;
6512         }
6513
6514         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6515         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6516         if (ret < 0)
6517                 return ret;
6518
6519         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6520                                          &filter_5tuple);
6521         if (filter != NULL && add) {
6522                 PMD_DRV_LOG(ERR, "filter exists.");
6523                 return -EEXIST;
6524         }
6525         if (filter == NULL && !add) {
6526                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6527                 return -ENOENT;
6528         }
6529
6530         if (add) {
6531                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6532                                 sizeof(struct ixgbe_5tuple_filter), 0);
6533                 if (filter == NULL)
6534                         return -ENOMEM;
6535                 rte_memcpy(&filter->filter_info,
6536                                  &filter_5tuple,
6537                                  sizeof(struct ixgbe_5tuple_filter_info));
6538                 filter->queue = ntuple_filter->queue;
6539                 ret = ixgbe_add_5tuple_filter(dev, filter);
6540                 if (ret < 0) {
6541                         rte_free(filter);
6542                         return ret;
6543                 }
6544         } else
6545                 ixgbe_remove_5tuple_filter(dev, filter);
6546
6547         return 0;
6548 }
6549
6550 int
6551 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6552                         struct rte_eth_ethertype_filter *filter,
6553                         bool add)
6554 {
6555         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6556         struct ixgbe_filter_info *filter_info =
6557                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6558         uint32_t etqf = 0;
6559         uint32_t etqs = 0;
6560         int ret;
6561         struct ixgbe_ethertype_filter ethertype_filter;
6562
6563         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6564                 return -EINVAL;
6565
6566         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6567                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6568                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6569                         " ethertype filter.", filter->ether_type);
6570                 return -EINVAL;
6571         }
6572
6573         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6574                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6575                 return -EINVAL;
6576         }
6577         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6578                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6579                 return -EINVAL;
6580         }
6581
6582         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6583         if (ret >= 0 && add) {
6584                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6585                             filter->ether_type);
6586                 return -EEXIST;
6587         }
6588         if (ret < 0 && !add) {
6589                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6590                             filter->ether_type);
6591                 return -ENOENT;
6592         }
6593
6594         if (add) {
6595                 etqf = IXGBE_ETQF_FILTER_EN;
6596                 etqf |= (uint32_t)filter->ether_type;
6597                 etqs |= (uint32_t)((filter->queue <<
6598                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6599                                     IXGBE_ETQS_RX_QUEUE);
6600                 etqs |= IXGBE_ETQS_QUEUE_EN;
6601
6602                 ethertype_filter.ethertype = filter->ether_type;
6603                 ethertype_filter.etqf = etqf;
6604                 ethertype_filter.etqs = etqs;
6605                 ethertype_filter.conf = FALSE;
6606                 ret = ixgbe_ethertype_filter_insert(filter_info,
6607                                                     &ethertype_filter);
6608                 if (ret < 0) {
6609                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6610                         return -ENOSPC;
6611                 }
6612         } else {
6613                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6614                 if (ret < 0)
6615                         return -ENOSYS;
6616         }
6617         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6618         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6619         IXGBE_WRITE_FLUSH(hw);
6620
6621         return 0;
6622 }
6623
6624 static int
6625 ixgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
6626                        const struct rte_flow_ops **ops)
6627 {
6628         *ops = &ixgbe_flow_ops;
6629         return 0;
6630 }
6631
6632 static u8 *
6633 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6634                         u8 **mc_addr_ptr, u32 *vmdq)
6635 {
6636         u8 *mc_addr;
6637
6638         *vmdq = 0;
6639         mc_addr = *mc_addr_ptr;
6640         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6641         return mc_addr;
6642 }
6643
6644 static int
6645 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6646                           struct rte_ether_addr *mc_addr_set,
6647                           uint32_t nb_mc_addr)
6648 {
6649         struct ixgbe_hw *hw;
6650         u8 *mc_addr_list;
6651
6652         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6653         mc_addr_list = (u8 *)mc_addr_set;
6654         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6655                                          ixgbe_dev_addr_list_itr, TRUE);
6656 }
6657
6658 static uint64_t
6659 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6660 {
6661         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6662         uint64_t systime_cycles;
6663
6664         switch (hw->mac.type) {
6665         case ixgbe_mac_X550:
6666         case ixgbe_mac_X550EM_x:
6667         case ixgbe_mac_X550EM_a:
6668                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6669                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6670                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6671                                 * NSEC_PER_SEC;
6672                 break;
6673         default:
6674                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6675                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6676                                 << 32;
6677         }
6678
6679         return systime_cycles;
6680 }
6681
6682 static uint64_t
6683 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6684 {
6685         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6686         uint64_t rx_tstamp_cycles;
6687
6688         switch (hw->mac.type) {
6689         case ixgbe_mac_X550:
6690         case ixgbe_mac_X550EM_x:
6691         case ixgbe_mac_X550EM_a:
6692                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6693                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6694                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6695                                 * NSEC_PER_SEC;
6696                 break;
6697         default:
6698                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6699                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6700                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6701                                 << 32;
6702         }
6703
6704         return rx_tstamp_cycles;
6705 }
6706
6707 static uint64_t
6708 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6709 {
6710         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6711         uint64_t tx_tstamp_cycles;
6712
6713         switch (hw->mac.type) {
6714         case ixgbe_mac_X550:
6715         case ixgbe_mac_X550EM_x:
6716         case ixgbe_mac_X550EM_a:
6717                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6718                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6719                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6720                                 * NSEC_PER_SEC;
6721                 break;
6722         default:
6723                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6724                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6725                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6726                                 << 32;
6727         }
6728
6729         return tx_tstamp_cycles;
6730 }
6731
6732 static void
6733 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6734 {
6735         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6736         struct ixgbe_adapter *adapter = dev->data->dev_private;
6737         struct rte_eth_link link;
6738         uint32_t incval = 0;
6739         uint32_t shift = 0;
6740
6741         /* Get current link speed. */
6742         ixgbe_dev_link_update(dev, 1);
6743         rte_eth_linkstatus_get(dev, &link);
6744
6745         switch (link.link_speed) {
6746         case ETH_SPEED_NUM_100M:
6747                 incval = IXGBE_INCVAL_100;
6748                 shift = IXGBE_INCVAL_SHIFT_100;
6749                 break;
6750         case ETH_SPEED_NUM_1G:
6751                 incval = IXGBE_INCVAL_1GB;
6752                 shift = IXGBE_INCVAL_SHIFT_1GB;
6753                 break;
6754         case ETH_SPEED_NUM_10G:
6755         default:
6756                 incval = IXGBE_INCVAL_10GB;
6757                 shift = IXGBE_INCVAL_SHIFT_10GB;
6758                 break;
6759         }
6760
6761         switch (hw->mac.type) {
6762         case ixgbe_mac_X550:
6763         case ixgbe_mac_X550EM_x:
6764         case ixgbe_mac_X550EM_a:
6765                 /* Independent of link speed. */
6766                 incval = 1;
6767                 /* Cycles read will be interpreted as ns. */
6768                 shift = 0;
6769                 /* Fall-through */
6770         case ixgbe_mac_X540:
6771                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6772                 break;
6773         case ixgbe_mac_82599EB:
6774                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6775                 shift -= IXGBE_INCVAL_SHIFT_82599;
6776                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6777                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6778                 break;
6779         default:
6780                 /* Not supported. */
6781                 return;
6782         }
6783
6784         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6785         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6786         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6787
6788         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6789         adapter->systime_tc.cc_shift = shift;
6790         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6791
6792         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6793         adapter->rx_tstamp_tc.cc_shift = shift;
6794         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6795
6796         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6797         adapter->tx_tstamp_tc.cc_shift = shift;
6798         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6799 }
6800
6801 static int
6802 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6803 {
6804         struct ixgbe_adapter *adapter = dev->data->dev_private;
6805
6806         adapter->systime_tc.nsec += delta;
6807         adapter->rx_tstamp_tc.nsec += delta;
6808         adapter->tx_tstamp_tc.nsec += delta;
6809
6810         return 0;
6811 }
6812
6813 static int
6814 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6815 {
6816         uint64_t ns;
6817         struct ixgbe_adapter *adapter = dev->data->dev_private;
6818
6819         ns = rte_timespec_to_ns(ts);
6820         /* Set the timecounters to a new value. */
6821         adapter->systime_tc.nsec = ns;
6822         adapter->rx_tstamp_tc.nsec = ns;
6823         adapter->tx_tstamp_tc.nsec = ns;
6824
6825         return 0;
6826 }
6827
6828 static int
6829 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6830 {
6831         uint64_t ns, systime_cycles;
6832         struct ixgbe_adapter *adapter = dev->data->dev_private;
6833
6834         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6835         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6836         *ts = rte_ns_to_timespec(ns);
6837
6838         return 0;
6839 }
6840
6841 static int
6842 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6843 {
6844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6845         uint32_t tsync_ctl;
6846         uint32_t tsauxc;
6847
6848         /* Stop the timesync system time. */
6849         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6850         /* Reset the timesync system time value. */
6851         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6852         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6853
6854         /* Enable system time for platforms where it isn't on by default. */
6855         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6856         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6857         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6858
6859         ixgbe_start_timecounters(dev);
6860
6861         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6862         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6863                         (RTE_ETHER_TYPE_1588 |
6864                          IXGBE_ETQF_FILTER_EN |
6865                          IXGBE_ETQF_1588));
6866
6867         /* Enable timestamping of received PTP packets. */
6868         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6869         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6870         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6871
6872         /* Enable timestamping of transmitted PTP packets. */
6873         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6874         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6875         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6876
6877         IXGBE_WRITE_FLUSH(hw);
6878
6879         return 0;
6880 }
6881
6882 static int
6883 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6884 {
6885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6886         uint32_t tsync_ctl;
6887
6888         /* Disable timestamping of transmitted PTP packets. */
6889         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6890         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6891         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6892
6893         /* Disable timestamping of received PTP packets. */
6894         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6895         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6896         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6897
6898         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6899         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6900
6901         /* Stop incrementating the System Time registers. */
6902         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6903
6904         return 0;
6905 }
6906
6907 static int
6908 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6909                                  struct timespec *timestamp,
6910                                  uint32_t flags __rte_unused)
6911 {
6912         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6913         struct ixgbe_adapter *adapter = dev->data->dev_private;
6914         uint32_t tsync_rxctl;
6915         uint64_t rx_tstamp_cycles;
6916         uint64_t ns;
6917
6918         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6919         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6920                 return -EINVAL;
6921
6922         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6923         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6924         *timestamp = rte_ns_to_timespec(ns);
6925
6926         return  0;
6927 }
6928
6929 static int
6930 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6931                                  struct timespec *timestamp)
6932 {
6933         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6934         struct ixgbe_adapter *adapter = dev->data->dev_private;
6935         uint32_t tsync_txctl;
6936         uint64_t tx_tstamp_cycles;
6937         uint64_t ns;
6938
6939         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6940         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6941                 return -EINVAL;
6942
6943         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6944         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6945         *timestamp = rte_ns_to_timespec(ns);
6946
6947         return 0;
6948 }
6949
6950 static int
6951 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6952 {
6953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6954         int count = 0;
6955         int g_ind = 0;
6956         const struct reg_info *reg_group;
6957         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6958                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6959
6960         while ((reg_group = reg_set[g_ind++]))
6961                 count += ixgbe_regs_group_count(reg_group);
6962
6963         return count;
6964 }
6965
6966 static int
6967 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6968 {
6969         int count = 0;
6970         int g_ind = 0;
6971         const struct reg_info *reg_group;
6972
6973         while ((reg_group = ixgbevf_regs[g_ind++]))
6974                 count += ixgbe_regs_group_count(reg_group);
6975
6976         return count;
6977 }
6978
6979 static int
6980 ixgbe_get_regs(struct rte_eth_dev *dev,
6981               struct rte_dev_reg_info *regs)
6982 {
6983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6984         uint32_t *data = regs->data;
6985         int g_ind = 0;
6986         int count = 0;
6987         const struct reg_info *reg_group;
6988         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6989                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6990
6991         if (data == NULL) {
6992                 regs->length = ixgbe_get_reg_length(dev);
6993                 regs->width = sizeof(uint32_t);
6994                 return 0;
6995         }
6996
6997         /* Support only full register dump */
6998         if ((regs->length == 0) ||
6999             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7000                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7001                         hw->device_id;
7002                 while ((reg_group = reg_set[g_ind++]))
7003                         count += ixgbe_read_regs_group(dev, &data[count],
7004                                 reg_group);
7005                 return 0;
7006         }
7007
7008         return -ENOTSUP;
7009 }
7010
7011 static int
7012 ixgbevf_get_regs(struct rte_eth_dev *dev,
7013                 struct rte_dev_reg_info *regs)
7014 {
7015         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7016         uint32_t *data = regs->data;
7017         int g_ind = 0;
7018         int count = 0;
7019         const struct reg_info *reg_group;
7020
7021         if (data == NULL) {
7022                 regs->length = ixgbevf_get_reg_length(dev);
7023                 regs->width = sizeof(uint32_t);
7024                 return 0;
7025         }
7026
7027         /* Support only full register dump */
7028         if ((regs->length == 0) ||
7029             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7030                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7031                         hw->device_id;
7032                 while ((reg_group = ixgbevf_regs[g_ind++]))
7033                         count += ixgbe_read_regs_group(dev, &data[count],
7034                                                       reg_group);
7035                 return 0;
7036         }
7037
7038         return -ENOTSUP;
7039 }
7040
7041 static int
7042 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7043 {
7044         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7045
7046         /* Return unit is byte count */
7047         return hw->eeprom.word_size * 2;
7048 }
7049
7050 static int
7051 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7052                 struct rte_dev_eeprom_info *in_eeprom)
7053 {
7054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7055         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7056         uint16_t *data = in_eeprom->data;
7057         int first, length;
7058
7059         first = in_eeprom->offset >> 1;
7060         length = in_eeprom->length >> 1;
7061         if ((first > hw->eeprom.word_size) ||
7062             ((first + length) > hw->eeprom.word_size))
7063                 return -EINVAL;
7064
7065         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7066
7067         return eeprom->ops.read_buffer(hw, first, length, data);
7068 }
7069
7070 static int
7071 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7072                 struct rte_dev_eeprom_info *in_eeprom)
7073 {
7074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7075         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7076         uint16_t *data = in_eeprom->data;
7077         int first, length;
7078
7079         first = in_eeprom->offset >> 1;
7080         length = in_eeprom->length >> 1;
7081         if ((first > hw->eeprom.word_size) ||
7082             ((first + length) > hw->eeprom.word_size))
7083                 return -EINVAL;
7084
7085         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7086
7087         return eeprom->ops.write_buffer(hw,  first, length, data);
7088 }
7089
7090 static int
7091 ixgbe_get_module_info(struct rte_eth_dev *dev,
7092                       struct rte_eth_dev_module_info *modinfo)
7093 {
7094         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7095         uint32_t status;
7096         uint8_t sff8472_rev, addr_mode;
7097         bool page_swap = false;
7098
7099         /* Check whether we support SFF-8472 or not */
7100         status = hw->phy.ops.read_i2c_eeprom(hw,
7101                                              IXGBE_SFF_SFF_8472_COMP,
7102                                              &sff8472_rev);
7103         if (status != 0)
7104                 return -EIO;
7105
7106         /* addressing mode is not supported */
7107         status = hw->phy.ops.read_i2c_eeprom(hw,
7108                                              IXGBE_SFF_SFF_8472_SWAP,
7109                                              &addr_mode);
7110         if (status != 0)
7111                 return -EIO;
7112
7113         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7114                 PMD_DRV_LOG(ERR,
7115                             "Address change required to access page 0xA2, "
7116                             "but not supported. Please report the module "
7117                             "type to the driver maintainers.");
7118                 page_swap = true;
7119         }
7120
7121         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7122                 /* We have a SFP, but it does not support SFF-8472 */
7123                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7124                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7125         } else {
7126                 /* We have a SFP which supports a revision of SFF-8472. */
7127                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7128                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7129         }
7130
7131         return 0;
7132 }
7133
7134 static int
7135 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7136                         struct rte_dev_eeprom_info *info)
7137 {
7138         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7139         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7140         uint8_t databyte = 0xFF;
7141         uint8_t *data = info->data;
7142         uint32_t i = 0;
7143
7144         for (i = info->offset; i < info->offset + info->length; i++) {
7145                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7146                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7147                 else
7148                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7149
7150                 if (status != 0)
7151                         return -EIO;
7152
7153                 data[i - info->offset] = databyte;
7154         }
7155
7156         return 0;
7157 }
7158
7159 uint16_t
7160 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7161         switch (mac_type) {
7162         case ixgbe_mac_X550:
7163         case ixgbe_mac_X550EM_x:
7164         case ixgbe_mac_X550EM_a:
7165                 return ETH_RSS_RETA_SIZE_512;
7166         case ixgbe_mac_X550_vf:
7167         case ixgbe_mac_X550EM_x_vf:
7168         case ixgbe_mac_X550EM_a_vf:
7169                 return ETH_RSS_RETA_SIZE_64;
7170         case ixgbe_mac_X540_vf:
7171         case ixgbe_mac_82599_vf:
7172                 return 0;
7173         default:
7174                 return ETH_RSS_RETA_SIZE_128;
7175         }
7176 }
7177
7178 uint32_t
7179 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7180         switch (mac_type) {
7181         case ixgbe_mac_X550:
7182         case ixgbe_mac_X550EM_x:
7183         case ixgbe_mac_X550EM_a:
7184                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7185                         return IXGBE_RETA(reta_idx >> 2);
7186                 else
7187                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7188         case ixgbe_mac_X550_vf:
7189         case ixgbe_mac_X550EM_x_vf:
7190         case ixgbe_mac_X550EM_a_vf:
7191                 return IXGBE_VFRETA(reta_idx >> 2);
7192         default:
7193                 return IXGBE_RETA(reta_idx >> 2);
7194         }
7195 }
7196
7197 uint32_t
7198 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7199         switch (mac_type) {
7200         case ixgbe_mac_X550_vf:
7201         case ixgbe_mac_X550EM_x_vf:
7202         case ixgbe_mac_X550EM_a_vf:
7203                 return IXGBE_VFMRQC;
7204         default:
7205                 return IXGBE_MRQC;
7206         }
7207 }
7208
7209 uint32_t
7210 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7211         switch (mac_type) {
7212         case ixgbe_mac_X550_vf:
7213         case ixgbe_mac_X550EM_x_vf:
7214         case ixgbe_mac_X550EM_a_vf:
7215                 return IXGBE_VFRSSRK(i);
7216         default:
7217                 return IXGBE_RSSRK(i);
7218         }
7219 }
7220
7221 bool
7222 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7223         switch (mac_type) {
7224         case ixgbe_mac_82599_vf:
7225         case ixgbe_mac_X540_vf:
7226                 return 0;
7227         default:
7228                 return 1;
7229         }
7230 }
7231
7232 static int
7233 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7234                         struct rte_eth_dcb_info *dcb_info)
7235 {
7236         struct ixgbe_dcb_config *dcb_config =
7237                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7238         struct ixgbe_dcb_tc_config *tc;
7239         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7240         uint8_t nb_tcs;
7241         uint8_t i, j;
7242
7243         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7244                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7245         else
7246                 dcb_info->nb_tcs = 1;
7247
7248         tc_queue = &dcb_info->tc_queue;
7249         nb_tcs = dcb_info->nb_tcs;
7250
7251         if (dcb_config->vt_mode) { /* vt is enabled*/
7252                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7253                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7254                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7255                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7256                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7257                         for (j = 0; j < nb_tcs; j++) {
7258                                 tc_queue->tc_rxq[0][j].base = j;
7259                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7260                                 tc_queue->tc_txq[0][j].base = j;
7261                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7262                         }
7263                 } else {
7264                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7265                                 for (j = 0; j < nb_tcs; j++) {
7266                                         tc_queue->tc_rxq[i][j].base =
7267                                                 i * nb_tcs + j;
7268                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7269                                         tc_queue->tc_txq[i][j].base =
7270                                                 i * nb_tcs + j;
7271                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7272                                 }
7273                         }
7274                 }
7275         } else { /* vt is disabled*/
7276                 struct rte_eth_dcb_rx_conf *rx_conf =
7277                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7278                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7279                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7280                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7281                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7282                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7283                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7284                         }
7285                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7286                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7287                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7288                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7289                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7290                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7291                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7292                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7293                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7294                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7295                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7296                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7297                         }
7298                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7299                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7300                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7301                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7302                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7303                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7304                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7305                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7306                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7307                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7308                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7309                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7310                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7311                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7312                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7313                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7314                 }
7315         }
7316         for (i = 0; i < dcb_info->nb_tcs; i++) {
7317                 tc = &dcb_config->tc_config[i];
7318                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7319         }
7320         return 0;
7321 }
7322
7323 /* Update e-tag ether type */
7324 static int
7325 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7326                             uint16_t ether_type)
7327 {
7328         uint32_t etag_etype;
7329
7330         if (hw->mac.type != ixgbe_mac_X550 &&
7331             hw->mac.type != ixgbe_mac_X550EM_x &&
7332             hw->mac.type != ixgbe_mac_X550EM_a) {
7333                 return -ENOTSUP;
7334         }
7335
7336         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7337         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7338         etag_etype |= ether_type;
7339         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7340         IXGBE_WRITE_FLUSH(hw);
7341
7342         return 0;
7343 }
7344
7345 /* Enable e-tag tunnel */
7346 static int
7347 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7348 {
7349         uint32_t etag_etype;
7350
7351         if (hw->mac.type != ixgbe_mac_X550 &&
7352             hw->mac.type != ixgbe_mac_X550EM_x &&
7353             hw->mac.type != ixgbe_mac_X550EM_a) {
7354                 return -ENOTSUP;
7355         }
7356
7357         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7358         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7359         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7360         IXGBE_WRITE_FLUSH(hw);
7361
7362         return 0;
7363 }
7364
7365 static int
7366 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7367                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7368 {
7369         int ret = 0;
7370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7371         uint32_t i, rar_entries;
7372         uint32_t rar_low, rar_high;
7373
7374         if (hw->mac.type != ixgbe_mac_X550 &&
7375             hw->mac.type != ixgbe_mac_X550EM_x &&
7376             hw->mac.type != ixgbe_mac_X550EM_a) {
7377                 return -ENOTSUP;
7378         }
7379
7380         rar_entries = ixgbe_get_num_rx_addrs(hw);
7381
7382         for (i = 1; i < rar_entries; i++) {
7383                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7384                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7385                 if ((rar_high & IXGBE_RAH_AV) &&
7386                     (rar_high & IXGBE_RAH_ADTYPE) &&
7387                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7388                      l2_tunnel->tunnel_id)) {
7389                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7390                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7391
7392                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7393
7394                         return ret;
7395                 }
7396         }
7397
7398         return ret;
7399 }
7400
7401 static int
7402 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7403                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7404 {
7405         int ret = 0;
7406         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7407         uint32_t i, rar_entries;
7408         uint32_t rar_low, rar_high;
7409
7410         if (hw->mac.type != ixgbe_mac_X550 &&
7411             hw->mac.type != ixgbe_mac_X550EM_x &&
7412             hw->mac.type != ixgbe_mac_X550EM_a) {
7413                 return -ENOTSUP;
7414         }
7415
7416         /* One entry for one tunnel. Try to remove potential existing entry. */
7417         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7418
7419         rar_entries = ixgbe_get_num_rx_addrs(hw);
7420
7421         for (i = 1; i < rar_entries; i++) {
7422                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7423                 if (rar_high & IXGBE_RAH_AV) {
7424                         continue;
7425                 } else {
7426                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7427                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7428                         rar_low = l2_tunnel->tunnel_id;
7429
7430                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7431                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7432
7433                         return ret;
7434                 }
7435         }
7436
7437         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7438                      " Please remove a rule before adding a new one.");
7439         return -EINVAL;
7440 }
7441
7442 static inline struct ixgbe_l2_tn_filter *
7443 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7444                           struct ixgbe_l2_tn_key *key)
7445 {
7446         int ret;
7447
7448         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7449         if (ret < 0)
7450                 return NULL;
7451
7452         return l2_tn_info->hash_map[ret];
7453 }
7454
7455 static inline int
7456 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7457                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7458 {
7459         int ret;
7460
7461         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7462                                &l2_tn_filter->key);
7463
7464         if (ret < 0) {
7465                 PMD_DRV_LOG(ERR,
7466                             "Failed to insert L2 tunnel filter"
7467                             " to hash table %d!",
7468                             ret);
7469                 return ret;
7470         }
7471
7472         l2_tn_info->hash_map[ret] = l2_tn_filter;
7473
7474         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7475
7476         return 0;
7477 }
7478
7479 static inline int
7480 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7481                           struct ixgbe_l2_tn_key *key)
7482 {
7483         int ret;
7484         struct ixgbe_l2_tn_filter *l2_tn_filter;
7485
7486         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7487
7488         if (ret < 0) {
7489                 PMD_DRV_LOG(ERR,
7490                             "No such L2 tunnel filter to delete %d!",
7491                             ret);
7492                 return ret;
7493         }
7494
7495         l2_tn_filter = l2_tn_info->hash_map[ret];
7496         l2_tn_info->hash_map[ret] = NULL;
7497
7498         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7499         rte_free(l2_tn_filter);
7500
7501         return 0;
7502 }
7503
7504 /* Add l2 tunnel filter */
7505 int
7506 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7507                                struct ixgbe_l2_tunnel_conf *l2_tunnel,
7508                                bool restore)
7509 {
7510         int ret;
7511         struct ixgbe_l2_tn_info *l2_tn_info =
7512                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7513         struct ixgbe_l2_tn_key key;
7514         struct ixgbe_l2_tn_filter *node;
7515
7516         if (!restore) {
7517                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7518                 key.tn_id = l2_tunnel->tunnel_id;
7519
7520                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7521
7522                 if (node) {
7523                         PMD_DRV_LOG(ERR,
7524                                     "The L2 tunnel filter already exists!");
7525                         return -EINVAL;
7526                 }
7527
7528                 node = rte_zmalloc("ixgbe_l2_tn",
7529                                    sizeof(struct ixgbe_l2_tn_filter),
7530                                    0);
7531                 if (!node)
7532                         return -ENOMEM;
7533
7534                 rte_memcpy(&node->key,
7535                                  &key,
7536                                  sizeof(struct ixgbe_l2_tn_key));
7537                 node->pool = l2_tunnel->pool;
7538                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7539                 if (ret < 0) {
7540                         rte_free(node);
7541                         return ret;
7542                 }
7543         }
7544
7545         switch (l2_tunnel->l2_tunnel_type) {
7546         case RTE_L2_TUNNEL_TYPE_E_TAG:
7547                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7548                 break;
7549         default:
7550                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7551                 ret = -EINVAL;
7552                 break;
7553         }
7554
7555         if ((!restore) && (ret < 0))
7556                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7557
7558         return ret;
7559 }
7560
7561 /* Delete l2 tunnel filter */
7562 int
7563 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7564                                struct ixgbe_l2_tunnel_conf *l2_tunnel)
7565 {
7566         int ret;
7567         struct ixgbe_l2_tn_info *l2_tn_info =
7568                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7569         struct ixgbe_l2_tn_key key;
7570
7571         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7572         key.tn_id = l2_tunnel->tunnel_id;
7573         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7574         if (ret < 0)
7575                 return ret;
7576
7577         switch (l2_tunnel->l2_tunnel_type) {
7578         case RTE_L2_TUNNEL_TYPE_E_TAG:
7579                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7580                 break;
7581         default:
7582                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7583                 ret = -EINVAL;
7584                 break;
7585         }
7586
7587         return ret;
7588 }
7589
7590 static int
7591 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7592 {
7593         int ret = 0;
7594         uint32_t ctrl;
7595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7596
7597         if (hw->mac.type != ixgbe_mac_X550 &&
7598             hw->mac.type != ixgbe_mac_X550EM_x &&
7599             hw->mac.type != ixgbe_mac_X550EM_a) {
7600                 return -ENOTSUP;
7601         }
7602
7603         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7604         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7605         if (en)
7606                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7607         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7608
7609         return ret;
7610 }
7611
7612 static int
7613 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7614                         uint16_t port)
7615 {
7616         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7617         IXGBE_WRITE_FLUSH(hw);
7618
7619         return 0;
7620 }
7621
7622 /* There's only one register for VxLAN UDP port.
7623  * So, we cannot add several ports. Will update it.
7624  */
7625 static int
7626 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7627                      uint16_t port)
7628 {
7629         if (port == 0) {
7630                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7631                 return -EINVAL;
7632         }
7633
7634         return ixgbe_update_vxlan_port(hw, port);
7635 }
7636
7637 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7638  * UDP port, it must have a value.
7639  * So, will reset it to the original value 0.
7640  */
7641 static int
7642 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7643                      uint16_t port)
7644 {
7645         uint16_t cur_port;
7646
7647         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7648
7649         if (cur_port != port) {
7650                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7651                 return -EINVAL;
7652         }
7653
7654         return ixgbe_update_vxlan_port(hw, 0);
7655 }
7656
7657 /* Add UDP tunneling port */
7658 static int
7659 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7660                               struct rte_eth_udp_tunnel *udp_tunnel)
7661 {
7662         int ret = 0;
7663         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7664
7665         if (hw->mac.type != ixgbe_mac_X550 &&
7666             hw->mac.type != ixgbe_mac_X550EM_x &&
7667             hw->mac.type != ixgbe_mac_X550EM_a) {
7668                 return -ENOTSUP;
7669         }
7670
7671         if (udp_tunnel == NULL)
7672                 return -EINVAL;
7673
7674         switch (udp_tunnel->prot_type) {
7675         case RTE_TUNNEL_TYPE_VXLAN:
7676                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7677                 break;
7678
7679         case RTE_TUNNEL_TYPE_GENEVE:
7680         case RTE_TUNNEL_TYPE_TEREDO:
7681                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7682                 ret = -EINVAL;
7683                 break;
7684
7685         default:
7686                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7687                 ret = -EINVAL;
7688                 break;
7689         }
7690
7691         return ret;
7692 }
7693
7694 /* Remove UDP tunneling port */
7695 static int
7696 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7697                               struct rte_eth_udp_tunnel *udp_tunnel)
7698 {
7699         int ret = 0;
7700         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7701
7702         if (hw->mac.type != ixgbe_mac_X550 &&
7703             hw->mac.type != ixgbe_mac_X550EM_x &&
7704             hw->mac.type != ixgbe_mac_X550EM_a) {
7705                 return -ENOTSUP;
7706         }
7707
7708         if (udp_tunnel == NULL)
7709                 return -EINVAL;
7710
7711         switch (udp_tunnel->prot_type) {
7712         case RTE_TUNNEL_TYPE_VXLAN:
7713                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7714                 break;
7715         case RTE_TUNNEL_TYPE_GENEVE:
7716         case RTE_TUNNEL_TYPE_TEREDO:
7717                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7718                 ret = -EINVAL;
7719                 break;
7720         default:
7721                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7722                 ret = -EINVAL;
7723                 break;
7724         }
7725
7726         return ret;
7727 }
7728
7729 static int
7730 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
7731 {
7732         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7733         int ret;
7734
7735         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
7736         case IXGBE_SUCCESS:
7737                 ret = 0;
7738                 break;
7739         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7740                 ret = -ENOTSUP;
7741                 break;
7742         default:
7743                 ret = -EAGAIN;
7744                 break;
7745         }
7746
7747         return ret;
7748 }
7749
7750 static int
7751 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
7752 {
7753         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7754         int ret;
7755
7756         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
7757         case IXGBE_SUCCESS:
7758                 ret = 0;
7759                 break;
7760         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7761                 ret = -ENOTSUP;
7762                 break;
7763         default:
7764                 ret = -EAGAIN;
7765                 break;
7766         }
7767
7768         return ret;
7769 }
7770
7771 static int
7772 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7773 {
7774         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7775         int ret;
7776         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
7777
7778         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
7779         case IXGBE_SUCCESS:
7780                 ret = 0;
7781                 break;
7782         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7783                 ret = -ENOTSUP;
7784                 break;
7785         default:
7786                 ret = -EAGAIN;
7787                 break;
7788         }
7789
7790         return ret;
7791 }
7792
7793 static int
7794 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7795 {
7796         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7797         int ret;
7798
7799         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
7800         case IXGBE_SUCCESS:
7801                 ret = 0;
7802                 break;
7803         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7804                 ret = -ENOTSUP;
7805                 break;
7806         default:
7807                 ret = -EAGAIN;
7808                 break;
7809         }
7810
7811         return ret;
7812 }
7813
7814 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7815 {
7816         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7817         u32 in_msg = 0;
7818
7819         /* peek the message first */
7820         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
7821
7822         /* PF reset VF event */
7823         if (in_msg == IXGBE_PF_CONTROL_MSG) {
7824                 /* dummy mbx read to ack pf */
7825                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7826                         return;
7827                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
7828                                              NULL);
7829         }
7830 }
7831
7832 static int
7833 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7834 {
7835         uint32_t eicr;
7836         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7837         struct ixgbe_interrupt *intr =
7838                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7839         ixgbevf_intr_disable(dev);
7840
7841         /* read-on-clear nic registers here */
7842         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7843         intr->flags = 0;
7844
7845         /* only one misc vector supported - mailbox */
7846         eicr &= IXGBE_VTEICR_MASK;
7847         if (eicr == IXGBE_MISC_VEC_ID)
7848                 intr->flags |= IXGBE_FLAG_MAILBOX;
7849
7850         return 0;
7851 }
7852
7853 static int
7854 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7855 {
7856         struct ixgbe_interrupt *intr =
7857                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7858
7859         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7860                 ixgbevf_mbx_process(dev);
7861                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7862         }
7863
7864         ixgbevf_intr_enable(dev);
7865
7866         return 0;
7867 }
7868
7869 static void
7870 ixgbevf_dev_interrupt_handler(void *param)
7871 {
7872         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7873
7874         ixgbevf_dev_interrupt_get_status(dev);
7875         ixgbevf_dev_interrupt_action(dev);
7876 }
7877
7878 /**
7879  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7880  *  @hw: pointer to hardware structure
7881  *
7882  *  Stops the transmit data path and waits for the HW to internally empty
7883  *  the Tx security block
7884  **/
7885 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7886 {
7887 #define IXGBE_MAX_SECTX_POLL 40
7888
7889         int i;
7890         int sectxreg;
7891
7892         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7893         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7894         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7895         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7896                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7897                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7898                         break;
7899                 /* Use interrupt-safe sleep just in case */
7900                 usec_delay(1000);
7901         }
7902
7903         /* For informational purposes only */
7904         if (i >= IXGBE_MAX_SECTX_POLL)
7905                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7906                          "path fully disabled.  Continuing with init.");
7907
7908         return IXGBE_SUCCESS;
7909 }
7910
7911 /**
7912  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7913  *  @hw: pointer to hardware structure
7914  *
7915  *  Enables the transmit data path.
7916  **/
7917 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7918 {
7919         uint32_t sectxreg;
7920
7921         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7922         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7923         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7924         IXGBE_WRITE_FLUSH(hw);
7925
7926         return IXGBE_SUCCESS;
7927 }
7928
7929 /* restore n-tuple filter */
7930 static inline void
7931 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
7932 {
7933         struct ixgbe_filter_info *filter_info =
7934                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7935         struct ixgbe_5tuple_filter *node;
7936
7937         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
7938                 ixgbe_inject_5tuple_filter(dev, node);
7939         }
7940 }
7941
7942 /* restore ethernet type filter */
7943 static inline void
7944 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
7945 {
7946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7947         struct ixgbe_filter_info *filter_info =
7948                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7949         int i;
7950
7951         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
7952                 if (filter_info->ethertype_mask & (1 << i)) {
7953                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
7954                                         filter_info->ethertype_filters[i].etqf);
7955                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
7956                                         filter_info->ethertype_filters[i].etqs);
7957                         IXGBE_WRITE_FLUSH(hw);
7958                 }
7959         }
7960 }
7961
7962 /* restore SYN filter */
7963 static inline void
7964 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
7965 {
7966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7967         struct ixgbe_filter_info *filter_info =
7968                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7969         uint32_t synqf;
7970
7971         synqf = filter_info->syn_info;
7972
7973         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
7974                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
7975                 IXGBE_WRITE_FLUSH(hw);
7976         }
7977 }
7978
7979 /* restore L2 tunnel filter */
7980 static inline void
7981 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
7982 {
7983         struct ixgbe_l2_tn_info *l2_tn_info =
7984                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7985         struct ixgbe_l2_tn_filter *node;
7986         struct ixgbe_l2_tunnel_conf l2_tn_conf;
7987
7988         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
7989                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
7990                 l2_tn_conf.tunnel_id      = node->key.tn_id;
7991                 l2_tn_conf.pool           = node->pool;
7992                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
7993         }
7994 }
7995
7996 /* restore rss filter */
7997 static inline void
7998 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
7999 {
8000         struct ixgbe_filter_info *filter_info =
8001                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8002
8003         if (filter_info->rss_info.conf.queue_num)
8004                 ixgbe_config_rss_filter(dev,
8005                         &filter_info->rss_info, TRUE);
8006 }
8007
8008 static int
8009 ixgbe_filter_restore(struct rte_eth_dev *dev)
8010 {
8011         ixgbe_ntuple_filter_restore(dev);
8012         ixgbe_ethertype_filter_restore(dev);
8013         ixgbe_syn_filter_restore(dev);
8014         ixgbe_fdir_filter_restore(dev);
8015         ixgbe_l2_tn_filter_restore(dev);
8016         ixgbe_rss_filter_restore(dev);
8017
8018         return 0;
8019 }
8020
8021 static void
8022 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8023 {
8024         struct ixgbe_l2_tn_info *l2_tn_info =
8025                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8027
8028         if (l2_tn_info->e_tag_en)
8029                 (void)ixgbe_e_tag_enable(hw);
8030
8031         if (l2_tn_info->e_tag_fwd_en)
8032                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8033
8034         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8035 }
8036
8037 /* remove all the n-tuple filters */
8038 void
8039 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8040 {
8041         struct ixgbe_filter_info *filter_info =
8042                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8043         struct ixgbe_5tuple_filter *p_5tuple;
8044
8045         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8046                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8047 }
8048
8049 /* remove all the ether type filters */
8050 void
8051 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8052 {
8053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8054         struct ixgbe_filter_info *filter_info =
8055                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8056         int i;
8057
8058         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8059                 if (filter_info->ethertype_mask & (1 << i) &&
8060                     !filter_info->ethertype_filters[i].conf) {
8061                         (void)ixgbe_ethertype_filter_remove(filter_info,
8062                                                             (uint8_t)i);
8063                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8064                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8065                         IXGBE_WRITE_FLUSH(hw);
8066                 }
8067         }
8068 }
8069
8070 /* remove the SYN filter */
8071 void
8072 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8073 {
8074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8075         struct ixgbe_filter_info *filter_info =
8076                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8077
8078         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8079                 filter_info->syn_info = 0;
8080
8081                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8082                 IXGBE_WRITE_FLUSH(hw);
8083         }
8084 }
8085
8086 /* remove all the L2 tunnel filters */
8087 int
8088 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8089 {
8090         struct ixgbe_l2_tn_info *l2_tn_info =
8091                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8092         struct ixgbe_l2_tn_filter *l2_tn_filter;
8093         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8094         int ret = 0;
8095
8096         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8097                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8098                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8099                 l2_tn_conf.pool           = l2_tn_filter->pool;
8100                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8101                 if (ret < 0)
8102                         return ret;
8103         }
8104
8105         return 0;
8106 }
8107
8108 void
8109 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8110                                 struct ixgbe_macsec_setting *macsec_setting)
8111 {
8112         struct ixgbe_macsec_setting *macsec =
8113                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8114
8115         macsec->offload_en = macsec_setting->offload_en;
8116         macsec->encrypt_en = macsec_setting->encrypt_en;
8117         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8118 }
8119
8120 void
8121 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8122 {
8123         struct ixgbe_macsec_setting *macsec =
8124                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8125
8126         macsec->offload_en = 0;
8127         macsec->encrypt_en = 0;
8128         macsec->replayprotect_en = 0;
8129 }
8130
8131 void
8132 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8133                                 struct ixgbe_macsec_setting *macsec_setting)
8134 {
8135         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8136         uint32_t ctrl;
8137         uint8_t en = macsec_setting->encrypt_en;
8138         uint8_t rp = macsec_setting->replayprotect_en;
8139
8140         /**
8141          * Workaround:
8142          * As no ixgbe_disable_sec_rx_path equivalent is
8143          * implemented for tx in the base code, and we are
8144          * not allowed to modify the base code in DPDK, so
8145          * just call the hand-written one directly for now.
8146          * The hardware support has been checked by
8147          * ixgbe_disable_sec_rx_path().
8148          */
8149         ixgbe_disable_sec_tx_path_generic(hw);
8150
8151         /* Enable Ethernet CRC (required by MACsec offload) */
8152         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8153         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8154         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8155
8156         /* Enable the TX and RX crypto engines */
8157         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8158         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8159         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8160
8161         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8162         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8163         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8164
8165         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8166         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8167         ctrl |= 0x3;
8168         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8169
8170         /* Enable SA lookup */
8171         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8172         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8173         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8174                      IXGBE_LSECTXCTRL_AUTH;
8175         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8176         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8177         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8178         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8179
8180         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8181         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8182         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8183         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8184         if (rp)
8185                 ctrl |= IXGBE_LSECRXCTRL_RP;
8186         else
8187                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8188         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8189
8190         /* Start the data paths */
8191         ixgbe_enable_sec_rx_path(hw);
8192         /**
8193          * Workaround:
8194          * As no ixgbe_enable_sec_rx_path equivalent is
8195          * implemented for tx in the base code, and we are
8196          * not allowed to modify the base code in DPDK, so
8197          * just call the hand-written one directly for now.
8198          */
8199         ixgbe_enable_sec_tx_path_generic(hw);
8200 }
8201
8202 void
8203 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8204 {
8205         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8206         uint32_t ctrl;
8207
8208         /**
8209          * Workaround:
8210          * As no ixgbe_disable_sec_rx_path equivalent is
8211          * implemented for tx in the base code, and we are
8212          * not allowed to modify the base code in DPDK, so
8213          * just call the hand-written one directly for now.
8214          * The hardware support has been checked by
8215          * ixgbe_disable_sec_rx_path().
8216          */
8217         ixgbe_disable_sec_tx_path_generic(hw);
8218
8219         /* Disable the TX and RX crypto engines */
8220         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8221         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8222         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8223
8224         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8225         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8226         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8227
8228         /* Disable SA lookup */
8229         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8230         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8231         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8232         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8233
8234         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8235         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8236         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8237         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8238
8239         /* Start the data paths */
8240         ixgbe_enable_sec_rx_path(hw);
8241         /**
8242          * Workaround:
8243          * As no ixgbe_enable_sec_rx_path equivalent is
8244          * implemented for tx in the base code, and we are
8245          * not allowed to modify the base code in DPDK, so
8246          * just call the hand-written one directly for now.
8247          */
8248         ixgbe_enable_sec_tx_path_generic(hw);
8249 }
8250
8251 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8252 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8253 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8254 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8255 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8256 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8257 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8258                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8259
8260 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_init, init, NOTICE);
8261 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_driver, driver, NOTICE);
8262
8263 #ifdef RTE_ETHDEV_DEBUG_RX
8264 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_rx, rx, DEBUG);
8265 #endif
8266 #ifdef RTE_ETHDEV_DEBUG_TX
8267 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_tx, tx, DEBUG);
8268 #endif