drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 enum ixgbevf_xcast_modes {
 158         IXGBEVF_XCAST_MODE_NONE = 0,
 159         IXGBEVF_XCAST_MODE_MULTI,
 160         IXGBEVF_XCAST_MODE_ALLMULTI,
 161 };
 162
 163 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 164 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 165
 166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 197                                  size_t fw_size);
 198 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 199                                struct rte_eth_dev_info *dev_info);
 200 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 201 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 202                                  struct rte_eth_dev_info *dev_info);
 203 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 204
 205 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 206                 uint16_t vlan_id, int on);
 207 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 208                                enum rte_vlan_type vlan_type,
 209                                uint16_t tpid_id);
 210 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 211                 uint16_t queue, bool on);
 212 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 213                 int on);
 214 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 215 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 216 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 217 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 218 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 219
 220 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 222 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 225                                struct rte_eth_fc_conf *fc_conf);
 226 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 227                 struct rte_eth_pfc_conf *pfc_conf);
 228 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 229                         struct rte_eth_rss_reta_entry64 *reta_conf,
 230                         uint16_t reta_size);
 231 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 232                         struct rte_eth_rss_reta_entry64 *reta_conf,
 233                         uint16_t reta_size);
 234 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 240                                       struct rte_intr_handle *handle);
 241 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 242                 void *param);
 243 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 244 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 245                 uint32_t index, uint32_t pool);
 246 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 247 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 248                                            struct ether_addr *mac_addr);
 249 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 250 static int is_ixgbe_pmd(const char *driver_name);
 251
 252 /* For Virtual Function support */
 253 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 254 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 255 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 256 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 257 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 258 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 259 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 260 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 261 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 262                 struct rte_eth_stats *stats);
 263 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 264 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 265                 uint16_t vlan_id, int on);
 266 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 267                 uint16_t queue, int on);
 268 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 269 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 270 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 271                                             uint16_t queue_id);
 272 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 273                                              uint16_t queue_id);
 274 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 275                                  uint8_t queue, uint8_t msix_vector);
 276 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 277 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 298                 uint16_t queue_idx, uint16_t tx_rate);
 299
 300 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 301                                  struct ether_addr *mac_addr,
 302                                  uint32_t index, uint32_t pool);
 303 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 304 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 305                                              struct ether_addr *mac_addr);
 306 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 307                         struct rte_eth_syn_filter *filter,
 308                         bool add);
 309 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 310                         struct rte_eth_syn_filter *filter);
 311 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 312                         enum rte_filter_op filter_op,
 313                         void *arg);
 314 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 315                         struct ixgbe_5tuple_filter *filter);
 316 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 317                         struct ixgbe_5tuple_filter *filter);
 318 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ntuple_filter *filter,
 320                         bool add);
 321 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ntuple_filter *filter);
 326 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ethertype_filter *filter,
 328                         bool add);
 329 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 330                                 enum rte_filter_op filter_op,
 331                                 void *arg);
 332 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 333                         struct rte_eth_ethertype_filter *filter);
 334 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 335                      enum rte_filter_type filter_type,
 336                      enum rte_filter_op filter_op,
 337                      void *arg);
 338 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 339
 340 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 341                                       struct ether_addr *mc_addr_set,
 342                                       uint32_t nb_mc_addr);
 343 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 344                                    struct rte_eth_dcb_info *dcb_info);
 345
 346 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 348                             struct rte_dev_reg_info *regs);
 349 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 350 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 351                                 struct rte_dev_eeprom_info *eeprom);
 352 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 353                                 struct rte_dev_eeprom_info *eeprom);
 354
 355 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 356 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 357                                 struct rte_dev_reg_info *regs);
 358
 359 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 361 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 362                                             struct timespec *timestamp,
 363                                             uint32_t flags);
 364 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 365                                             struct timespec *timestamp);
 366 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 367 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 368                                    struct timespec *timestamp);
 369 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 370                                    const struct timespec *timestamp);
 371 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 372                                           void *param);
 373
 374 static int ixgbe_dev_l2_tunnel_eth_type_conf
 375         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 376 static int ixgbe_dev_l2_tunnel_offload_set
 377         (struct rte_eth_dev *dev,
 378          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 379          uint32_t mask,
 380          uint8_t en);
 381 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 382                                              enum rte_filter_op filter_op,
 383                                              void *arg);
 384
 385 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 386                                          struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 388                                          struct rte_eth_udp_tunnel *udp_tunnel);
 389
 390 /*
 391  * Define VF Stats MACRO for Non "cleared on read" register
 392  */
 393 #define UPDATE_VF_STAT(reg, last, cur)                          \
 394 {                                                               \
 395         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 396         cur += (latest - last) & UINT_MAX;                      \
 397         last = latest;                                          \
 398 }
 399
 400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 401 {                                                                \
 402         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 403         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 404         u64 latest = ((new_msb << 32) | new_lsb);                \
 405         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 406         last = latest;                                           \
 407 }
 408
 409 #define IXGBE_SET_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] |= 1 << bit;\
 413         } while (0)
 414
 415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (h)->bitmap[idx] &= ~(1 << bit);\
 419         } while (0)
 420
 421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 422                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 423                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 424                 (r) = (h)->bitmap[idx] >> bit & 1;\
 425         } while (0)
 426
 427 /*
 428  * The set of PCI devices this driver supports
 429  */
 430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 484 #ifdef RTE_NIC_BYPASS
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 486 #endif
 487         { .vendor_id = 0, /* sentinel */ },
 488 };
 489
 490 /*
 491  * The set of PCI devices this driver supports (for 82599 VF)
 492  */
 493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 504         { .vendor_id = 0, /* sentinel */ },
 505 };
 506
 507 static const struct rte_eth_desc_lim rx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_RXD_ALIGN,
 511 };
 512
 513 static const struct rte_eth_desc_lim tx_desc_lim = {
 514         .nb_max = IXGBE_MAX_RING_DESC,
 515         .nb_min = IXGBE_MIN_RING_DESC,
 516         .nb_align = IXGBE_TXD_ALIGN,
 517         .nb_seg_max = IXGBE_TX_MAX_SEG,
 518         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 519 };
 520
 521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 522         .dev_configure        = ixgbe_dev_configure,
 523         .dev_start            = ixgbe_dev_start,
 524         .dev_stop             = ixgbe_dev_stop,
 525         .dev_set_link_up    = ixgbe_dev_set_link_up,
 526         .dev_set_link_down  = ixgbe_dev_set_link_down,
 527         .dev_close            = ixgbe_dev_close,
 528         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 529         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 530         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 531         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 532         .link_update          = ixgbe_dev_link_update,
 533         .stats_get            = ixgbe_dev_stats_get,
 534         .xstats_get           = ixgbe_dev_xstats_get,
 535         .stats_reset          = ixgbe_dev_stats_reset,
 536         .xstats_reset         = ixgbe_dev_xstats_reset,
 537         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 538         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 539         .fw_version_get       = ixgbe_fw_version_get,
 540         .dev_infos_get        = ixgbe_dev_info_get,
 541         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 542         .mtu_set              = ixgbe_dev_mtu_set,
 543         .vlan_filter_set      = ixgbe_vlan_filter_set,
 544         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 545         .vlan_offload_set     = ixgbe_vlan_offload_set,
 546         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 547         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 548         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 549         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 550         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 551         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 552         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 553         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 554         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 555         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 556         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 557         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 558         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 559         .dev_led_on           = ixgbe_dev_led_on,
 560         .dev_led_off          = ixgbe_dev_led_off,
 561         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 562         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 563         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 564         .mac_addr_add         = ixgbe_add_rar,
 565         .mac_addr_remove      = ixgbe_remove_rar,
 566         .mac_addr_set         = ixgbe_set_default_mac_addr,
 567         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 568         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 569         .mirror_rule_set      = ixgbe_mirror_rule_set,
 570         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 571         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 572         .reta_update          = ixgbe_dev_rss_reta_update,
 573         .reta_query           = ixgbe_dev_rss_reta_query,
 574 #ifdef RTE_NIC_BYPASS
 575         .bypass_init          = ixgbe_bypass_init,
 576         .bypass_state_set     = ixgbe_bypass_state_store,
 577         .bypass_state_show    = ixgbe_bypass_state_show,
 578         .bypass_event_set     = ixgbe_bypass_event_store,
 579         .bypass_event_show    = ixgbe_bypass_event_show,
 580         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 581         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 582         .bypass_ver_show      = ixgbe_bypass_ver_show,
 583         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 584 #endif /* RTE_NIC_BYPASS */
 585         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 586         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 587         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 588         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 589         .rxq_info_get         = ixgbe_rxq_info_get,
 590         .txq_info_get         = ixgbe_txq_info_get,
 591         .timesync_enable      = ixgbe_timesync_enable,
 592         .timesync_disable     = ixgbe_timesync_disable,
 593         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 594         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 595         .get_reg              = ixgbe_get_regs,
 596         .get_eeprom_length    = ixgbe_get_eeprom_length,
 597         .get_eeprom           = ixgbe_get_eeprom,
 598         .set_eeprom           = ixgbe_set_eeprom,
 599         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 600         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 601         .timesync_read_time   = ixgbe_timesync_read_time,
 602         .timesync_write_time  = ixgbe_timesync_write_time,
 603         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 604         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 605         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 606         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 607 };
 608
 609 /*
 610  * dev_ops for virtual function, bare necessities for basic vf
 611  * operation have been implemented
 612  */
 613 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 614         .dev_configure        = ixgbevf_dev_configure,
 615         .dev_start            = ixgbevf_dev_start,
 616         .dev_stop             = ixgbevf_dev_stop,
 617         .link_update          = ixgbe_dev_link_update,
 618         .stats_get            = ixgbevf_dev_stats_get,
 619         .xstats_get           = ixgbevf_dev_xstats_get,
 620         .stats_reset          = ixgbevf_dev_stats_reset,
 621         .xstats_reset         = ixgbevf_dev_stats_reset,
 622         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 623         .dev_close            = ixgbevf_dev_close,
 624         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 625         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 626         .dev_infos_get        = ixgbevf_dev_info_get,
 627         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 628         .mtu_set              = ixgbevf_dev_set_mtu,
 629         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 630         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 631         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 632         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 633         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 634         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 635         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 636         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 637         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 638         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 639         .mac_addr_add         = ixgbevf_add_mac_addr,
 640         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 641         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 642         .rxq_info_get         = ixgbe_rxq_info_get,
 643         .txq_info_get         = ixgbe_txq_info_get,
 644         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 645         .get_reg              = ixgbevf_get_regs,
 646         .reta_update          = ixgbe_dev_rss_reta_update,
 647         .reta_query           = ixgbe_dev_rss_reta_query,
 648         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 649         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 650 };
 651
 652 /* store statistics names and its offset in stats structure */
 653 struct rte_ixgbe_xstats_name_off {
 654         char name[RTE_ETH_XSTATS_NAME_SIZE];
 655         unsigned offset;
 656 };
 657
 658 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 659         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 660         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 661         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 662         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 663         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 664         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 665         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 666         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 667         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 668         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 669         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 670         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 671         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 672         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 673         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 674                 prc1023)},
 675         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 676                 prc1522)},
 677         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 678         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 679         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 680         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 681         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 682         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 683         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 684         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 685         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 686         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 687         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 688         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 689         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 690         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 691         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 692         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 693         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 694                 ptc1023)},
 695         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 696                 ptc1522)},
 697         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 698         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 699         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 700         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 701
 702         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 703                 fdirustat_add)},
 704         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirustat_remove)},
 706         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 707                 fdirfstat_fadd)},
 708         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 709                 fdirfstat_fremove)},
 710         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirmatch)},
 712         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 713                 fdirmiss)},
 714
 715         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 716         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 717         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 718                 fclast)},
 719         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 720         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 721         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 722         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 723         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 724                 fcoe_noddp)},
 725         {"rx_fcoe_no_direct_data_placement_ext_buff",
 726                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 727
 728         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 729                 lxontxc)},
 730         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 731                 lxonrxc)},
 732         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 733                 lxofftxc)},
 734         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 735                 lxoffrxc)},
 736         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 737 };
 738
 739 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 740                            sizeof(rte_ixgbe_stats_strings[0]))
 741
 742 /* MACsec statistics */
 743 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 744         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 745                 out_pkts_untagged)},
 746         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 747                 out_pkts_encrypted)},
 748         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 749                 out_pkts_protected)},
 750         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 751                 out_octets_encrypted)},
 752         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 753                 out_octets_protected)},
 754         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_untagged)},
 756         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_badtag)},
 758         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_nosci)},
 760         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_unknownsci)},
 762         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 763                 in_octets_decrypted)},
 764         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 765                 in_octets_validated)},
 766         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_unchecked)},
 768         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_delayed)},
 770         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_late)},
 772         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_ok)},
 774         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_invalid)},
 776         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_notvalid)},
 778         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_unusedsa)},
 780         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 781                 in_pkts_notusingsa)},
 782 };
 783
 784 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 785                            sizeof(rte_ixgbe_macsec_strings[0]))
 786
 787 /* Per-queue statistics */
 788 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 789         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 790         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 791         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 792         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 793 };
 794
 795 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 796                            sizeof(rte_ixgbe_rxq_strings[0]))
 797 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 798
 799 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 800         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 801         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 802         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 803                 pxon2offc)},
 804 };
 805
 806 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 807                            sizeof(rte_ixgbe_txq_strings[0]))
 808 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 809
 810 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 811         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 812 };
 813
 814 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 815                 sizeof(rte_ixgbevf_stats_strings[0]))
 816
 817 /**
 818  * Atomically reads the link status information from global
 819  * structure rte_eth_dev.
 820  *
 821  * @param dev
 822  *   - Pointer to the structure rte_eth_dev to read from.
 823  *   - Pointer to the buffer to be saved with the link status.
 824  *
 825  * @return
 826  *   - On success, zero.
 827  *   - On failure, negative value.
 828  */
 829 static inline int
 830 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 831                                 struct rte_eth_link *link)
 832 {
 833         struct rte_eth_link *dst = link;
 834         struct rte_eth_link *src = &(dev->data->dev_link);
 835
 836         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 837                                         *(uint64_t *)src) == 0)
 838                 return -1;
 839
 840         return 0;
 841 }
 842
 843 /**
 844  * Atomically writes the link status information into global
 845  * structure rte_eth_dev.
 846  *
 847  * @param dev
 848  *   - Pointer to the structure rte_eth_dev to read from.
 849  *   - Pointer to the buffer to be saved with the link status.
 850  *
 851  * @return
 852  *   - On success, zero.
 853  *   - On failure, negative value.
 854  */
 855 static inline int
 856 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 857                                 struct rte_eth_link *link)
 858 {
 859         struct rte_eth_link *dst = &(dev->data->dev_link);
 860         struct rte_eth_link *src = link;
 861
 862         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 863                                         *(uint64_t *)src) == 0)
 864                 return -1;
 865
 866         return 0;
 867 }
 868
 869 /*
 870  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 871  */
 872 static inline int
 873 ixgbe_is_sfp(struct ixgbe_hw *hw)
 874 {
 875         switch (hw->phy.type) {
 876         case ixgbe_phy_sfp_avago:
 877         case ixgbe_phy_sfp_ftl:
 878         case ixgbe_phy_sfp_intel:
 879         case ixgbe_phy_sfp_unknown:
 880         case ixgbe_phy_sfp_passive_tyco:
 881         case ixgbe_phy_sfp_passive_unknown:
 882                 return 1;
 883         default:
 884                 return 0;
 885         }
 886 }
 887
 888 static inline int32_t
 889 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 890 {
 891         uint32_t ctrl_ext;
 892         int32_t status;
 893
 894         status = ixgbe_reset_hw(hw);
 895
 896         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 897         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 898         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 899         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 900         IXGBE_WRITE_FLUSH(hw);
 901
 902         return status;
 903 }
 904
 905 static inline void
 906 ixgbe_enable_intr(struct rte_eth_dev *dev)
 907 {
 908         struct ixgbe_interrupt *intr =
 909                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 910         struct ixgbe_hw *hw =
 911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 912
 913         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 914         IXGBE_WRITE_FLUSH(hw);
 915 }
 916
 917 /*
 918  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 919  */
 920 static void
 921 ixgbe_disable_intr(struct ixgbe_hw *hw)
 922 {
 923         PMD_INIT_FUNC_TRACE();
 924
 925         if (hw->mac.type == ixgbe_mac_82598EB) {
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 927         } else {
 928                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 930                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 931         }
 932         IXGBE_WRITE_FLUSH(hw);
 933 }
 934
 935 /*
 936  * This function resets queue statistics mapping registers.
 937  * From Niantic datasheet, Initialization of Statistics section:
 938  * "...if software requires the queue counters, the RQSMR and TQSM registers
 939  * must be re-programmed following a device reset.
 940  */
 941 static void
 942 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 943 {
 944         uint32_t i;
 945
 946         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 947                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 948                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 949         }
 950 }
 951
 952
 953 static int
 954 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 955                                   uint16_t queue_id,
 956                                   uint8_t stat_idx,
 957                                   uint8_t is_rx)
 958 {
 959 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 960 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 961 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 962
 963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 964         struct ixgbe_stat_mapping_registers *stat_mappings =
 965                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 966         uint32_t qsmr_mask = 0;
 967         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 968         uint32_t q_map;
 969         uint8_t n, offset;
 970
 971         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 972                 (hw->mac.type != ixgbe_mac_X540) &&
 973                 (hw->mac.type != ixgbe_mac_X550) &&
 974                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 975                 (hw->mac.type != ixgbe_mac_X550EM_a))
 976                 return -ENOSYS;
 977
 978         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 979                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 980                      queue_id, stat_idx);
 981
 982         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 983         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 984                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 985                 return -EIO;
 986         }
 987         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 988
 989         /* Now clear any previous stat_idx set */
 990         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 991         if (!is_rx)
 992                 stat_mappings->tqsm[n] &= ~clearing_mask;
 993         else
 994                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 995
 996         q_map = (uint32_t)stat_idx;
 997         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 998         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 999         if (!is_rx)
1000                 stat_mappings->tqsm[n] |= qsmr_mask;
1001         else
1002                 stat_mappings->rqsmr[n] |= qsmr_mask;
1003
1004         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1005                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1006                      queue_id, stat_idx);
1007         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1008                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1009
1010         /* Now write the mapping in the appropriate register */
1011         if (is_rx) {
1012                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1013                              stat_mappings->rqsmr[n], n);
1014                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1015         } else {
1016                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1017                              stat_mappings->tqsm[n], n);
1018                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1019         }
1020         return 0;
1021 }
1022
1023 static void
1024 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1025 {
1026         struct ixgbe_stat_mapping_registers *stat_mappings =
1027                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1029         int i;
1030
1031         /* write whatever was in stat mapping table to the NIC */
1032         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1033                 /* rx */
1034                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1035
1036                 /* tx */
1037                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1038         }
1039 }
1040
1041 static void
1042 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1043 {
1044         uint8_t i;
1045         struct ixgbe_dcb_tc_config *tc;
1046         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1047
1048         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1049         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1050         for (i = 0; i < dcb_max_tc; i++) {
1051                 tc = &dcb_config->tc_config[i];
1052                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1053                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1054                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1055                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1056                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1057                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1058                 tc->pfc = ixgbe_dcb_pfc_disabled;
1059         }
1060
1061         /* Initialize default user to priority mapping, UPx->TC0 */
1062         tc = &dcb_config->tc_config[0];
1063         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1064         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1065         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1066                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1067                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1068         }
1069         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1070         dcb_config->pfc_mode_enable = false;
1071         dcb_config->vt_mode = true;
1072         dcb_config->round_robin_enable = false;
1073         /* support all DCB capabilities in 82599 */
1074         dcb_config->support.capabilities = 0xFF;
1075
1076         /*we only support 4 Tcs for X540, X550 */
1077         if (hw->mac.type == ixgbe_mac_X540 ||
1078                 hw->mac.type == ixgbe_mac_X550 ||
1079                 hw->mac.type == ixgbe_mac_X550EM_x ||
1080                 hw->mac.type == ixgbe_mac_X550EM_a) {
1081                 dcb_config->num_tcs.pg_tcs = 4;
1082                 dcb_config->num_tcs.pfc_tcs = 4;
1083         }
1084 }
1085
1086 /*
1087  * Ensure that all locks are released before first NVM or PHY access
1088  */
1089 static void
1090 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1091 {
1092         uint16_t mask;
1093
1094         /*
1095          * Phy lock should not fail in this early stage. If this is the case,
1096          * it is due to an improper exit of the application.
1097          * So force the release of the faulty lock. Release of common lock
1098          * is done automatically by swfw_sync function.
1099          */
1100         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1101         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1102                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1103         }
1104         ixgbe_release_swfw_semaphore(hw, mask);
1105
1106         /*
1107          * These ones are more tricky since they are common to all ports; but
1108          * swfw_sync retries last long enough (1s) to be almost sure that if
1109          * lock can not be taken it is due to an improper lock of the
1110          * semaphore.
1111          */
1112         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1113         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1114                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1115         }
1116         ixgbe_release_swfw_semaphore(hw, mask);
1117 }
1118
1119 /*
1120  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1121  * It returns 0 on success.
1122  */
1123 static int
1124 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1125 {
1126         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1127         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1128         struct ixgbe_hw *hw =
1129                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1130         struct ixgbe_vfta *shadow_vfta =
1131                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1132         struct ixgbe_hwstrip *hwstrip =
1133                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1134         struct ixgbe_dcb_config *dcb_config =
1135                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1136         struct ixgbe_filter_info *filter_info =
1137                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1138         uint32_t ctrl_ext;
1139         uint16_t csum;
1140         int diag, i;
1141
1142         PMD_INIT_FUNC_TRACE();
1143
1144         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1145         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1146         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1147         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1148
1149         /*
1150          * For secondary processes, we don't initialise any further as primary
1151          * has already done this work. Only check we don't need a different
1152          * RX and TX function.
1153          */
1154         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1155                 struct ixgbe_tx_queue *txq;
1156                 /* TX queue function in primary, set by last queue initialized
1157                  * Tx queue may not initialized by primary process
1158                  */
1159                 if (eth_dev->data->tx_queues) {
1160                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1161                         ixgbe_set_tx_function(eth_dev, txq);
1162                 } else {
1163                         /* Use default TX function if we get here */
1164                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1165                                      "Using default TX function.");
1166                 }
1167
1168                 ixgbe_set_rx_function(eth_dev);
1169
1170                 return 0;
1171         }
1172
1173         rte_eth_copy_pci_info(eth_dev, pci_dev);
1174         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1175
1176         /* Vendor and Device ID need to be set before init of shared code */
1177         hw->device_id = pci_dev->id.device_id;
1178         hw->vendor_id = pci_dev->id.vendor_id;
1179         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1180         hw->allow_unsupported_sfp = 1;
1181
1182         /* Initialize the shared code (base driver) */
1183 #ifdef RTE_NIC_BYPASS
1184         diag = ixgbe_bypass_init_shared_code(hw);
1185 #else
1186         diag = ixgbe_init_shared_code(hw);
1187 #endif /* RTE_NIC_BYPASS */
1188
1189         if (diag != IXGBE_SUCCESS) {
1190                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1191                 return -EIO;
1192         }
1193
1194         /* pick up the PCI bus settings for reporting later */
1195         ixgbe_get_bus_info(hw);
1196
1197         /* Unlock any pending hardware semaphore */
1198         ixgbe_swfw_lock_reset(hw);
1199
1200         /* Initialize DCB configuration*/
1201         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1202         ixgbe_dcb_init(hw, dcb_config);
1203         /* Get Hardware Flow Control setting */
1204         hw->fc.requested_mode = ixgbe_fc_full;
1205         hw->fc.current_mode = ixgbe_fc_full;
1206         hw->fc.pause_time = IXGBE_FC_PAUSE;
1207         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1208                 hw->fc.low_water[i] = IXGBE_FC_LO;
1209                 hw->fc.high_water[i] = IXGBE_FC_HI;
1210         }
1211         hw->fc.send_xon = 1;
1212
1213         /* Make sure we have a good EEPROM before we read from it */
1214         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1215         if (diag != IXGBE_SUCCESS) {
1216                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1217                 return -EIO;
1218         }
1219
1220 #ifdef RTE_NIC_BYPASS
1221         diag = ixgbe_bypass_init_hw(hw);
1222 #else
1223         diag = ixgbe_init_hw(hw);
1224 #endif /* RTE_NIC_BYPASS */
1225
1226         /*
1227          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1228          * is called too soon after the kernel driver unbinding/binding occurs.
1229          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1230          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1231          * also called. See ixgbe_identify_phy_82599(). The reason for the
1232          * failure is not known, and only occuts when virtualisation features
1233          * are disabled in the bios. A delay of 100ms  was found to be enough by
1234          * trial-and-error, and is doubled to be safe.
1235          */
1236         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1237                 rte_delay_ms(200);
1238                 diag = ixgbe_init_hw(hw);
1239         }
1240
1241         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1242                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1243                              "LOM.  Please be aware there may be issues associated "
1244                              "with your hardware.");
1245                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1246                              "please contact your Intel or hardware representative "
1247                              "who provided you with this hardware.");
1248         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1249                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1250         if (diag) {
1251                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1252                 return -EIO;
1253         }
1254
1255         /* Reset the hw statistics */
1256         ixgbe_dev_stats_reset(eth_dev);
1257
1258         /* disable interrupt */
1259         ixgbe_disable_intr(hw);
1260
1261         /* reset mappings for queue statistics hw counters*/
1262         ixgbe_reset_qstat_mappings(hw);
1263
1264         /* Allocate memory for storing MAC addresses */
1265         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1266                                                hw->mac.num_rar_entries, 0);
1267         if (eth_dev->data->mac_addrs == NULL) {
1268                 PMD_INIT_LOG(ERR,
1269                              "Failed to allocate %u bytes needed to store "
1270                              "MAC addresses",
1271                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1272                 return -ENOMEM;
1273         }
1274         /* Copy the permanent MAC address */
1275         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1276                         &eth_dev->data->mac_addrs[0]);
1277
1278         /* Allocate memory for storing hash filter MAC addresses */
1279         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1280                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1281         if (eth_dev->data->hash_mac_addrs == NULL) {
1282                 PMD_INIT_LOG(ERR,
1283                              "Failed to allocate %d bytes needed to store MAC addresses",
1284                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1285                 return -ENOMEM;
1286         }
1287
1288         /* initialize the vfta */
1289         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1290
1291         /* initialize the hw strip bitmap*/
1292         memset(hwstrip, 0, sizeof(*hwstrip));
1293
1294         /* initialize PF if max_vfs not zero */
1295         ixgbe_pf_host_init(eth_dev);
1296
1297         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1298         /* let hardware know driver is loaded */
1299         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1300         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1301         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1302         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1303         IXGBE_WRITE_FLUSH(hw);
1304
1305         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1306                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1307                              (int) hw->mac.type, (int) hw->phy.type,
1308                              (int) hw->phy.sfp_type);
1309         else
1310                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1311                              (int) hw->mac.type, (int) hw->phy.type);
1312
1313         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1314                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1315                      pci_dev->id.device_id);
1316
1317         rte_intr_callback_register(intr_handle,
1318                                    ixgbe_dev_interrupt_handler, eth_dev);
1319
1320         /* enable uio/vfio intr/eventfd mapping */
1321         rte_intr_enable(intr_handle);
1322
1323         /* enable support intr */
1324         ixgbe_enable_intr(eth_dev);
1325
1326         /* initialize 5tuple filter list */
1327         TAILQ_INIT(&filter_info->fivetuple_list);
1328         memset(filter_info->fivetuple_mask, 0,
1329                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1330
1331         return 0;
1332 }
1333
1334 static int
1335 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1336 {
1337         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1338         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1339         struct ixgbe_hw *hw;
1340
1341         PMD_INIT_FUNC_TRACE();
1342
1343         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1344                 return -EPERM;
1345
1346         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1347
1348         if (hw->adapter_stopped == 0)
1349                 ixgbe_dev_close(eth_dev);
1350
1351         eth_dev->dev_ops = NULL;
1352         eth_dev->rx_pkt_burst = NULL;
1353         eth_dev->tx_pkt_burst = NULL;
1354
1355         /* Unlock any pending hardware semaphore */
1356         ixgbe_swfw_lock_reset(hw);
1357
1358         /* disable uio intr before callback unregister */
1359         rte_intr_disable(intr_handle);
1360         rte_intr_callback_unregister(intr_handle,
1361                                      ixgbe_dev_interrupt_handler, eth_dev);
1362
1363         /* uninitialize PF if max_vfs not zero */
1364         ixgbe_pf_host_uninit(eth_dev);
1365
1366         rte_free(eth_dev->data->mac_addrs);
1367         eth_dev->data->mac_addrs = NULL;
1368
1369         rte_free(eth_dev->data->hash_mac_addrs);
1370         eth_dev->data->hash_mac_addrs = NULL;
1371
1372         return 0;
1373 }
1374
1375 /*
1376  * Negotiate mailbox API version with the PF.
1377  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1378  * Then we try to negotiate starting with the most recent one.
1379  * If all negotiation attempts fail, then we will proceed with
1380  * the default one (ixgbe_mbox_api_10).
1381  */
1382 static void
1383 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1384 {
1385         int32_t i;
1386
1387         /* start with highest supported, proceed down */
1388         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1389                 ixgbe_mbox_api_12,
1390                 ixgbe_mbox_api_11,
1391                 ixgbe_mbox_api_10,
1392         };
1393
1394         for (i = 0;
1395                         i != RTE_DIM(sup_ver) &&
1396                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1397                         i++)
1398                 ;
1399 }
1400
1401 static void
1402 generate_random_mac_addr(struct ether_addr *mac_addr)
1403 {
1404         uint64_t random;
1405
1406         /* Set Organizationally Unique Identifier (OUI) prefix. */
1407         mac_addr->addr_bytes[0] = 0x00;
1408         mac_addr->addr_bytes[1] = 0x09;
1409         mac_addr->addr_bytes[2] = 0xC0;
1410         /* Force indication of locally assigned MAC address. */
1411         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1412         /* Generate the last 3 bytes of the MAC address with a random number. */
1413         random = rte_rand();
1414         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1415 }
1416
1417 /*
1418  * Virtual Function device init
1419  */
1420 static int
1421 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1422 {
1423         int diag;
1424         uint32_t tc, tcs;
1425         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1426         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1427         struct ixgbe_hw *hw =
1428                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1429         struct ixgbe_vfta *shadow_vfta =
1430                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1431         struct ixgbe_hwstrip *hwstrip =
1432                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1433         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1434
1435         PMD_INIT_FUNC_TRACE();
1436
1437         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1438         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1439         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1440
1441         /* for secondary processes, we don't initialise any further as primary
1442          * has already done this work. Only check we don't need a different
1443          * RX function
1444          */
1445         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1446                 struct ixgbe_tx_queue *txq;
1447                 /* TX queue function in primary, set by last queue initialized
1448                  * Tx queue may not initialized by primary process
1449                  */
1450                 if (eth_dev->data->tx_queues) {
1451                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1452                         ixgbe_set_tx_function(eth_dev, txq);
1453                 } else {
1454                         /* Use default TX function if we get here */
1455                         PMD_INIT_LOG(NOTICE,
1456                                      "No TX queues configured yet. Using default TX function.");
1457                 }
1458
1459                 ixgbe_set_rx_function(eth_dev);
1460
1461                 return 0;
1462         }
1463
1464         rte_eth_copy_pci_info(eth_dev, pci_dev);
1465         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1466
1467         hw->device_id = pci_dev->id.device_id;
1468         hw->vendor_id = pci_dev->id.vendor_id;
1469         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1470
1471         /* initialize the vfta */
1472         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1473
1474         /* initialize the hw strip bitmap*/
1475         memset(hwstrip, 0, sizeof(*hwstrip));
1476
1477         /* Initialize the shared code (base driver) */
1478         diag = ixgbe_init_shared_code(hw);
1479         if (diag != IXGBE_SUCCESS) {
1480                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1481                 return -EIO;
1482         }
1483
1484         /* init_mailbox_params */
1485         hw->mbx.ops.init_params(hw);
1486
1487         /* Reset the hw statistics */
1488         ixgbevf_dev_stats_reset(eth_dev);
1489
1490         /* Disable the interrupts for VF */
1491         ixgbevf_intr_disable(hw);
1492
1493         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1494         diag = hw->mac.ops.reset_hw(hw);
1495
1496         /*
1497          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1498          * the underlying PF driver has not assigned a MAC address to the VF.
1499          * In this case, assign a random MAC address.
1500          */
1501         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1502                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1503                 return diag;
1504         }
1505
1506         /* negotiate mailbox API version to use with the PF. */
1507         ixgbevf_negotiate_api(hw);
1508
1509         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1510         ixgbevf_get_queues(hw, &tcs, &tc);
1511
1512         /* Allocate memory for storing MAC addresses */
1513         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1514                                                hw->mac.num_rar_entries, 0);
1515         if (eth_dev->data->mac_addrs == NULL) {
1516                 PMD_INIT_LOG(ERR,
1517                              "Failed to allocate %u bytes needed to store "
1518                              "MAC addresses",
1519                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1520                 return -ENOMEM;
1521         }
1522
1523         /* Generate a random MAC address, if none was assigned by PF. */
1524         if (is_zero_ether_addr(perm_addr)) {
1525                 generate_random_mac_addr(perm_addr);
1526                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1527                 if (diag) {
1528                         rte_free(eth_dev->data->mac_addrs);
1529                         eth_dev->data->mac_addrs = NULL;
1530                         return diag;
1531                 }
1532                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1533                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1534                              "%02x:%02x:%02x:%02x:%02x:%02x",
1535                              perm_addr->addr_bytes[0],
1536                              perm_addr->addr_bytes[1],
1537                              perm_addr->addr_bytes[2],
1538                              perm_addr->addr_bytes[3],
1539                              perm_addr->addr_bytes[4],
1540                              perm_addr->addr_bytes[5]);
1541         }
1542
1543         /* Copy the permanent MAC address */
1544         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1545
1546         /* reset the hardware with the new settings */
1547         diag = hw->mac.ops.start_hw(hw);
1548         switch (diag) {
1549         case  0:
1550                 break;
1551
1552         default:
1553                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1554                 return -EIO;
1555         }
1556
1557         rte_intr_callback_register(intr_handle,
1558                                    ixgbevf_dev_interrupt_handler, eth_dev);
1559         rte_intr_enable(intr_handle);
1560         ixgbevf_intr_enable(hw);
1561
1562         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1563                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1564                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1565
1566         return 0;
1567 }
1568
1569 /* Virtual Function device uninit */
1570
1571 static int
1572 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1573 {
1574         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1575         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1576         struct ixgbe_hw *hw;
1577
1578         PMD_INIT_FUNC_TRACE();
1579
1580         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1581                 return -EPERM;
1582
1583         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1584
1585         if (hw->adapter_stopped == 0)
1586                 ixgbevf_dev_close(eth_dev);
1587
1588         eth_dev->dev_ops = NULL;
1589         eth_dev->rx_pkt_burst = NULL;
1590         eth_dev->tx_pkt_burst = NULL;
1591
1592         /* Disable the interrupts for VF */
1593         ixgbevf_intr_disable(hw);
1594
1595         rte_free(eth_dev->data->mac_addrs);
1596         eth_dev->data->mac_addrs = NULL;
1597
1598         rte_intr_disable(intr_handle);
1599         rte_intr_callback_unregister(intr_handle,
1600                                      ixgbevf_dev_interrupt_handler, eth_dev);
1601
1602         return 0;
1603 }
1604
1605 static struct eth_driver rte_ixgbe_pmd = {
1606         .pci_drv = {
1607                 .id_table = pci_id_ixgbe_map,
1608                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1609                 .probe = rte_eth_dev_pci_probe,
1610                 .remove = rte_eth_dev_pci_remove,
1611         },
1612         .eth_dev_init = eth_ixgbe_dev_init,
1613         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1614         .dev_private_size = sizeof(struct ixgbe_adapter),
1615 };
1616
1617 /*
1618  * virtual function driver struct
1619  */
1620 static struct eth_driver rte_ixgbevf_pmd = {
1621         .pci_drv = {
1622                 .id_table = pci_id_ixgbevf_map,
1623                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1624                 .probe = rte_eth_dev_pci_probe,
1625                 .remove = rte_eth_dev_pci_remove,
1626         },
1627         .eth_dev_init = eth_ixgbevf_dev_init,
1628         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1629         .dev_private_size = sizeof(struct ixgbe_adapter),
1630 };
1631
1632 static int
1633 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1634 {
1635         struct ixgbe_hw *hw =
1636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         struct ixgbe_vfta *shadow_vfta =
1638                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1639         uint32_t vfta;
1640         uint32_t vid_idx;
1641         uint32_t vid_bit;
1642
1643         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1644         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1645         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1646         if (on)
1647                 vfta |= vid_bit;
1648         else
1649                 vfta &= ~vid_bit;
1650         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1651
1652         /* update local VFTA copy */
1653         shadow_vfta->vfta[vid_idx] = vfta;
1654
1655         return 0;
1656 }
1657
1658 static void
1659 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1660 {
1661         if (on)
1662                 ixgbe_vlan_hw_strip_enable(dev, queue);
1663         else
1664                 ixgbe_vlan_hw_strip_disable(dev, queue);
1665 }
1666
1667 static int
1668 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1669                     enum rte_vlan_type vlan_type,
1670                     uint16_t tpid)
1671 {
1672         struct ixgbe_hw *hw =
1673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         int ret = 0;
1675         uint32_t reg;
1676         uint32_t qinq;
1677
1678         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1679         qinq &= IXGBE_DMATXCTL_GDV;
1680
1681         switch (vlan_type) {
1682         case ETH_VLAN_TYPE_INNER:
1683                 if (qinq) {
1684                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1685                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1686                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1687                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1688                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1689                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1690                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1691                 } else {
1692                         ret = -ENOTSUP;
1693                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1694                                     " by single VLAN");
1695                 }
1696                 break;
1697         case ETH_VLAN_TYPE_OUTER:
1698                 if (qinq) {
1699                         /* Only the high 16-bits is valid */
1700                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1701                                         IXGBE_EXVET_VET_EXT_SHIFT);
1702                 } else {
1703                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1704                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1705                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1706                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1707                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1708                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1709                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1710                 }
1711
1712                 break;
1713         default:
1714                 ret = -EINVAL;
1715                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1716                 break;
1717         }
1718
1719         return ret;
1720 }
1721
1722 void
1723 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1724 {
1725         struct ixgbe_hw *hw =
1726                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727         uint32_t vlnctrl;
1728
1729         PMD_INIT_FUNC_TRACE();
1730
1731         /* Filter Table Disable */
1732         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1733         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1734
1735         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1736 }
1737
1738 void
1739 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1740 {
1741         struct ixgbe_hw *hw =
1742                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1743         struct ixgbe_vfta *shadow_vfta =
1744                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1745         uint32_t vlnctrl;
1746         uint16_t i;
1747
1748         PMD_INIT_FUNC_TRACE();
1749
1750         /* Filter Table Enable */
1751         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1752         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1753         vlnctrl |= IXGBE_VLNCTRL_VFE;
1754
1755         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1756
1757         /* write whatever is in local vfta copy */
1758         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1759                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1760 }
1761
1762 static void
1763 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1764 {
1765         struct ixgbe_hwstrip *hwstrip =
1766                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1767         struct ixgbe_rx_queue *rxq;
1768
1769         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1770                 return;
1771
1772         if (on)
1773                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1774         else
1775                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1776
1777         if (queue >= dev->data->nb_rx_queues)
1778                 return;
1779
1780         rxq = dev->data->rx_queues[queue];
1781
1782         if (on)
1783                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1784         else
1785                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1786 }
1787
1788 static void
1789 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1790 {
1791         struct ixgbe_hw *hw =
1792                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1793         uint32_t ctrl;
1794
1795         PMD_INIT_FUNC_TRACE();
1796
1797         if (hw->mac.type == ixgbe_mac_82598EB) {
1798                 /* No queue level support */
1799                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1800                 return;
1801         }
1802
1803         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1804         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1805         ctrl &= ~IXGBE_RXDCTL_VME;
1806         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1807
1808         /* record those setting for HW strip per queue */
1809         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1810 }
1811
1812 static void
1813 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1814 {
1815         struct ixgbe_hw *hw =
1816                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1817         uint32_t ctrl;
1818
1819         PMD_INIT_FUNC_TRACE();
1820
1821         if (hw->mac.type == ixgbe_mac_82598EB) {
1822                 /* No queue level supported */
1823                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1824                 return;
1825         }
1826
1827         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1828         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1829         ctrl |= IXGBE_RXDCTL_VME;
1830         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1831
1832         /* record those setting for HW strip per queue */
1833         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1834 }
1835
1836 void
1837 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1838 {
1839         struct ixgbe_hw *hw =
1840                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1841         uint32_t ctrl;
1842         uint16_t i;
1843         struct ixgbe_rx_queue *rxq;
1844
1845         PMD_INIT_FUNC_TRACE();
1846
1847         if (hw->mac.type == ixgbe_mac_82598EB) {
1848                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1849                 ctrl &= ~IXGBE_VLNCTRL_VME;
1850                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1851         } else {
1852                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1853                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1854                         rxq = dev->data->rx_queues[i];
1855                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1856                         ctrl &= ~IXGBE_RXDCTL_VME;
1857                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1858
1859                         /* record those setting for HW strip per queue */
1860                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1861                 }
1862         }
1863 }
1864
1865 void
1866 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1867 {
1868         struct ixgbe_hw *hw =
1869                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870         uint32_t ctrl;
1871         uint16_t i;
1872         struct ixgbe_rx_queue *rxq;
1873
1874         PMD_INIT_FUNC_TRACE();
1875
1876         if (hw->mac.type == ixgbe_mac_82598EB) {
1877                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1878                 ctrl |= IXGBE_VLNCTRL_VME;
1879                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1880         } else {
1881                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1882                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1883                         rxq = dev->data->rx_queues[i];
1884                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1885                         ctrl |= IXGBE_RXDCTL_VME;
1886                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1887
1888                         /* record those setting for HW strip per queue */
1889                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1890                 }
1891         }
1892 }
1893
1894 static void
1895 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1896 {
1897         struct ixgbe_hw *hw =
1898                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1899         uint32_t ctrl;
1900
1901         PMD_INIT_FUNC_TRACE();
1902
1903         /* DMATXCTRL: Geric Double VLAN Disable */
1904         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1905         ctrl &= ~IXGBE_DMATXCTL_GDV;
1906         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1907
1908         /* CTRL_EXT: Global Double VLAN Disable */
1909         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1910         ctrl &= ~IXGBE_EXTENDED_VLAN;
1911         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1912
1913 }
1914
1915 static void
1916 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1917 {
1918         struct ixgbe_hw *hw =
1919                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1920         uint32_t ctrl;
1921
1922         PMD_INIT_FUNC_TRACE();
1923
1924         /* DMATXCTRL: Geric Double VLAN Enable */
1925         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1926         ctrl |= IXGBE_DMATXCTL_GDV;
1927         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1928
1929         /* CTRL_EXT: Global Double VLAN Enable */
1930         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1931         ctrl |= IXGBE_EXTENDED_VLAN;
1932         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1933
1934         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1935         if (hw->mac.type == ixgbe_mac_X550 ||
1936             hw->mac.type == ixgbe_mac_X550EM_x ||
1937             hw->mac.type == ixgbe_mac_X550EM_a) {
1938                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1939                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1940                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1941         }
1942
1943         /*
1944          * VET EXT field in the EXVET register = 0x8100 by default
1945          * So no need to change. Same to VT field of DMATXCTL register
1946          */
1947 }
1948
1949 static void
1950 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1951 {
1952         if (mask & ETH_VLAN_STRIP_MASK) {
1953                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1954                         ixgbe_vlan_hw_strip_enable_all(dev);
1955                 else
1956                         ixgbe_vlan_hw_strip_disable_all(dev);
1957         }
1958
1959         if (mask & ETH_VLAN_FILTER_MASK) {
1960                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1961                         ixgbe_vlan_hw_filter_enable(dev);
1962                 else
1963                         ixgbe_vlan_hw_filter_disable(dev);
1964         }
1965
1966         if (mask & ETH_VLAN_EXTEND_MASK) {
1967                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1968                         ixgbe_vlan_hw_extend_enable(dev);
1969                 else
1970                         ixgbe_vlan_hw_extend_disable(dev);
1971         }
1972 }
1973
1974 static void
1975 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1976 {
1977         struct ixgbe_hw *hw =
1978                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1980         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1981
1982         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1983         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1984 }
1985
1986 static int
1987 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1988 {
1989         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
1990
1991         switch (nb_rx_q) {
1992         case 1:
1993         case 2:
1994                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1995                 break;
1996         case 4:
1997                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1998                 break;
1999         default:
2000                 return -EINVAL;
2001         }
2002
2003         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2004         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2005
2006         return 0;
2007 }
2008
2009 static int
2010 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2011 {
2012         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2015         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2016
2017         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2018                 /* check multi-queue mode */
2019                 switch (dev_conf->rxmode.mq_mode) {
2020                 case ETH_MQ_RX_VMDQ_DCB:
2021                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2022                         break;
2023                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2024                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2025                         PMD_INIT_LOG(ERR, "SRIOV active,"
2026                                         " unsupported mq_mode rx %d.",
2027                                         dev_conf->rxmode.mq_mode);
2028                         return -EINVAL;
2029                 case ETH_MQ_RX_RSS:
2030                 case ETH_MQ_RX_VMDQ_RSS:
2031                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2032                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2033                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2034                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2035                                                 " invalid queue number"
2036                                                 " for VMDQ RSS, allowed"
2037                                                 " value are 1, 2 or 4.");
2038                                         return -EINVAL;
2039                                 }
2040                         break;
2041                 case ETH_MQ_RX_VMDQ_ONLY:
2042                 case ETH_MQ_RX_NONE:
2043                         /* if nothing mq mode configure, use default scheme */
2044                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2045                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2046                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2047                         break;
2048                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2049                         /* SRIOV only works in VMDq enable mode */
2050                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2051                                         " wrong mq_mode rx %d.",
2052                                         dev_conf->rxmode.mq_mode);
2053                         return -EINVAL;
2054                 }
2055
2056                 switch (dev_conf->txmode.mq_mode) {
2057                 case ETH_MQ_TX_VMDQ_DCB:
2058                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2059                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2060                         break;
2061                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2062                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2063                         break;
2064                 }
2065
2066                 /* check valid queue number */
2067                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2068                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2069                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2070                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2071                                         " must be less than or equal to %d.",
2072                                         nb_rx_q, nb_tx_q,
2073                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2074                         return -EINVAL;
2075                 }
2076         } else {
2077                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2078                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2079                                           " not supported.");
2080                         return -EINVAL;
2081                 }
2082                 /* check configuration for vmdb+dcb mode */
2083                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2084                         const struct rte_eth_vmdq_dcb_conf *conf;
2085
2086                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2087                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2088                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2089                                 return -EINVAL;
2090                         }
2091                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2092                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2093                                conf->nb_queue_pools == ETH_32_POOLS)) {
2094                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2095                                                 " nb_queue_pools must be %d or %d.",
2096                                                 ETH_16_POOLS, ETH_32_POOLS);
2097                                 return -EINVAL;
2098                         }
2099                 }
2100                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2101                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2102
2103                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2104                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2105                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2106                                 return -EINVAL;
2107                         }
2108                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2109                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2110                                conf->nb_queue_pools == ETH_32_POOLS)) {
2111                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2112                                                 " nb_queue_pools != %d and"
2113                                                 " nb_queue_pools != %d.",
2114                                                 ETH_16_POOLS, ETH_32_POOLS);
2115                                 return -EINVAL;
2116                         }
2117                 }
2118
2119                 /* For DCB mode check our configuration before we go further */
2120                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2121                         const struct rte_eth_dcb_rx_conf *conf;
2122
2123                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2124                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2125                                                  IXGBE_DCB_NB_QUEUES);
2126                                 return -EINVAL;
2127                         }
2128                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2129                         if (!(conf->nb_tcs == ETH_4_TCS ||
2130                                conf->nb_tcs == ETH_8_TCS)) {
2131                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2132                                                 " and nb_tcs != %d.",
2133                                                 ETH_4_TCS, ETH_8_TCS);
2134                                 return -EINVAL;
2135                         }
2136                 }
2137
2138                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2139                         const struct rte_eth_dcb_tx_conf *conf;
2140
2141                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2142                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2143                                                  IXGBE_DCB_NB_QUEUES);
2144                                 return -EINVAL;
2145                         }
2146                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2147                         if (!(conf->nb_tcs == ETH_4_TCS ||
2148                                conf->nb_tcs == ETH_8_TCS)) {
2149                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2150                                                 " and nb_tcs != %d.",
2151                                                 ETH_4_TCS, ETH_8_TCS);
2152                                 return -EINVAL;
2153                         }
2154                 }
2155
2156                 /*
2157                  * When DCB/VT is off, maximum number of queues changes,
2158                  * except for 82598EB, which remains constant.
2159                  */
2160                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2161                                 hw->mac.type != ixgbe_mac_82598EB) {
2162                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2163                                 PMD_INIT_LOG(ERR,
2164                                              "Neither VT nor DCB are enabled, "
2165                                              "nb_tx_q > %d.",
2166                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2167                                 return -EINVAL;
2168                         }
2169                 }
2170         }
2171         return 0;
2172 }
2173
2174 static int
2175 ixgbe_dev_configure(struct rte_eth_dev *dev)
2176 {
2177         struct ixgbe_interrupt *intr =
2178                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2179         struct ixgbe_adapter *adapter =
2180                 (struct ixgbe_adapter *)dev->data->dev_private;
2181         int ret;
2182
2183         PMD_INIT_FUNC_TRACE();
2184         /* multipe queue mode checking */
2185         ret  = ixgbe_check_mq_mode(dev);
2186         if (ret != 0) {
2187                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2188                             ret);
2189                 return ret;
2190         }
2191
2192         /* set flag to update link status after init */
2193         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2194
2195         /*
2196          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2197          * allocation or vector Rx preconditions we will reset it.
2198          */
2199         adapter->rx_bulk_alloc_allowed = true;
2200         adapter->rx_vec_allowed = true;
2201
2202         return 0;
2203 }
2204
2205 static void
2206 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2207 {
2208         struct ixgbe_hw *hw =
2209                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2210         struct ixgbe_interrupt *intr =
2211                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2212         uint32_t gpie;
2213
2214         /* only set up it on X550EM_X */
2215         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2216                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2217                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2218                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2219                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2220                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2221         }
2222 }
2223
2224 /*
2225  * Configure device link speed and setup link.
2226  * It returns 0 on success.
2227  */
2228 static int
2229 ixgbe_dev_start(struct rte_eth_dev *dev)
2230 {
2231         struct ixgbe_hw *hw =
2232                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2233         struct ixgbe_vf_info *vfinfo =
2234                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2235         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2236         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2237         uint32_t intr_vector = 0;
2238         int err, link_up = 0, negotiate = 0;
2239         uint32_t speed = 0;
2240         int mask = 0;
2241         int status;
2242         uint16_t vf, idx;
2243         uint32_t *link_speeds;
2244
2245         PMD_INIT_FUNC_TRACE();
2246
2247         /* IXGBE devices don't support:
2248         *    - half duplex (checked afterwards for valid speeds)
2249         *    - fixed speed: TODO implement
2250         */
2251         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2252                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2253                              dev->data->port_id);
2254                 return -EINVAL;
2255         }
2256
2257         /* disable uio/vfio intr/eventfd mapping */
2258         rte_intr_disable(intr_handle);
2259
2260         /* stop adapter */
2261         hw->adapter_stopped = 0;
2262         ixgbe_stop_adapter(hw);
2263
2264         /* reinitialize adapter
2265          * this calls reset and start
2266          */
2267         status = ixgbe_pf_reset_hw(hw);
2268         if (status != 0)
2269                 return -1;
2270         hw->mac.ops.start_hw(hw);
2271         hw->mac.get_link_status = true;
2272
2273         /* configure PF module if SRIOV enabled */
2274         ixgbe_pf_host_configure(dev);
2275
2276         ixgbe_dev_phy_intr_setup(dev);
2277
2278         /* check and configure queue intr-vector mapping */
2279         if ((rte_intr_cap_multiple(intr_handle) ||
2280              !RTE_ETH_DEV_SRIOV(dev).active) &&
2281             dev->data->dev_conf.intr_conf.rxq != 0) {
2282                 intr_vector = dev->data->nb_rx_queues;
2283                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2284                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2285                                         IXGBE_MAX_INTR_QUEUE_NUM);
2286                         return -ENOTSUP;
2287                 }
2288                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2289                         return -1;
2290         }
2291
2292         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2293                 intr_handle->intr_vec =
2294                         rte_zmalloc("intr_vec",
2295                                     dev->data->nb_rx_queues * sizeof(int), 0);
2296                 if (intr_handle->intr_vec == NULL) {
2297                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2298                                      " intr_vec\n", dev->data->nb_rx_queues);
2299                         return -ENOMEM;
2300                 }
2301         }
2302
2303         /* confiugre msix for sleep until rx interrupt */
2304         ixgbe_configure_msix(dev);
2305
2306         /* initialize transmission unit */
2307         ixgbe_dev_tx_init(dev);
2308
2309         /* This can fail when allocating mbufs for descriptor rings */
2310         err = ixgbe_dev_rx_init(dev);
2311         if (err) {
2312                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2313                 goto error;
2314         }
2315
2316     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2317                 ETH_VLAN_EXTEND_MASK;
2318         ixgbe_vlan_offload_set(dev, mask);
2319
2320         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2321                 /* Enable vlan filtering for VMDq */
2322                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2323         }
2324
2325         /* Configure DCB hw */
2326         ixgbe_configure_dcb(dev);
2327
2328         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2329                 err = ixgbe_fdir_configure(dev);
2330                 if (err)
2331                         goto error;
2332         }
2333
2334         /* Restore vf rate limit */
2335         if (vfinfo != NULL) {
2336                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2337                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2338                                 if (vfinfo[vf].tx_rate[idx] != 0)
2339                                         rte_pmd_ixgbe_set_vf_rate_limit(
2340                                                 dev->data->port_id, vf,
2341                                                 vfinfo[vf].tx_rate[idx],
2342                                                 1 << idx);
2343         }
2344
2345         ixgbe_restore_statistics_mapping(dev);
2346
2347         err = ixgbe_dev_rxtx_start(dev);
2348         if (err < 0) {
2349                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2350                 goto error;
2351         }
2352
2353         /* Skip link setup if loopback mode is enabled for 82599. */
2354         if (hw->mac.type == ixgbe_mac_82599EB &&
2355                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2356                 goto skip_link_setup;
2357
2358         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2359                 err = hw->mac.ops.setup_sfp(hw);
2360                 if (err)
2361                         goto error;
2362         }
2363
2364         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2365                 /* Turn on the copper */
2366                 ixgbe_set_phy_power(hw, true);
2367         } else {
2368                 /* Turn on the laser */
2369                 ixgbe_enable_tx_laser(hw);
2370         }
2371
2372         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2373         if (err)
2374                 goto error;
2375         dev->data->dev_link.link_status = link_up;
2376
2377         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2378         if (err)
2379                 goto error;
2380
2381         link_speeds = &dev->data->dev_conf.link_speeds;
2382         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2383                         ETH_LINK_SPEED_10G)) {
2384                 PMD_INIT_LOG(ERR, "Invalid link setting");
2385                 goto error;
2386         }
2387
2388         speed = 0x0;
2389         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2390                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2391                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2392                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2393         } else {
2394                 if (*link_speeds & ETH_LINK_SPEED_10G)
2395                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2396                 if (*link_speeds & ETH_LINK_SPEED_1G)
2397                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2398                 if (*link_speeds & ETH_LINK_SPEED_100M)
2399                         speed |= IXGBE_LINK_SPEED_100_FULL;
2400         }
2401
2402         err = ixgbe_setup_link(hw, speed, link_up);
2403         if (err)
2404                 goto error;
2405
2406 skip_link_setup:
2407
2408         if (rte_intr_allow_others(intr_handle)) {
2409                 /* check if lsc interrupt is enabled */
2410                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2411                         ixgbe_dev_lsc_interrupt_setup(dev);
2412                 ixgbe_dev_macsec_interrupt_setup(dev);
2413         } else {
2414                 rte_intr_callback_unregister(intr_handle,
2415                                              ixgbe_dev_interrupt_handler, dev);
2416                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2417                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2418                                      " no intr multiplex\n");
2419         }
2420
2421         /* check if rxq interrupt is enabled */
2422         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2423             rte_intr_dp_is_en(intr_handle))
2424                 ixgbe_dev_rxq_interrupt_setup(dev);
2425
2426         /* enable uio/vfio intr/eventfd mapping */
2427         rte_intr_enable(intr_handle);
2428
2429         /* resume enabled intr since hw reset */
2430         ixgbe_enable_intr(dev);
2431
2432         return 0;
2433
2434 error:
2435         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2436         ixgbe_dev_clear_queues(dev);
2437         return -EIO;
2438 }
2439
2440 /*
2441  * Stop device: disable rx and tx functions to allow for reconfiguring.
2442  */
2443 static void
2444 ixgbe_dev_stop(struct rte_eth_dev *dev)
2445 {
2446         struct rte_eth_link link;
2447         struct ixgbe_hw *hw =
2448                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2449         struct ixgbe_vf_info *vfinfo =
2450                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2451         struct ixgbe_filter_info *filter_info =
2452                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2453         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2454         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2455         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2456         int vf;
2457
2458         PMD_INIT_FUNC_TRACE();
2459
2460         /* disable interrupts */
2461         ixgbe_disable_intr(hw);
2462
2463         /* reset the NIC */
2464         ixgbe_pf_reset_hw(hw);
2465         hw->adapter_stopped = 0;
2466
2467         /* stop adapter */
2468         ixgbe_stop_adapter(hw);
2469
2470         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2471                 vfinfo[vf].clear_to_send = false;
2472
2473         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2474                 /* Turn off the copper */
2475                 ixgbe_set_phy_power(hw, false);
2476         } else {
2477                 /* Turn off the laser */
2478                 ixgbe_disable_tx_laser(hw);
2479         }
2480
2481         ixgbe_dev_clear_queues(dev);
2482
2483         /* Clear stored conf */
2484         dev->data->scattered_rx = 0;
2485         dev->data->lro = 0;
2486
2487         /* Clear recorded link status */
2488         memset(&link, 0, sizeof(link));
2489         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2490
2491         /* Remove all ntuple filters of the device */
2492         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2493              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2494                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2495                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2496                              p_5tuple, entries);
2497                 rte_free(p_5tuple);
2498         }
2499         memset(filter_info->fivetuple_mask, 0,
2500                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2501
2502         if (!rte_intr_allow_others(intr_handle))
2503                 /* resume to the default handler */
2504                 rte_intr_callback_register(intr_handle,
2505                                            ixgbe_dev_interrupt_handler,
2506                                            (void *)dev);
2507
2508         /* Clean datapath event and queue/vec mapping */
2509         rte_intr_efd_disable(intr_handle);
2510         if (intr_handle->intr_vec != NULL) {
2511                 rte_free(intr_handle->intr_vec);
2512                 intr_handle->intr_vec = NULL;
2513         }
2514 }
2515
2516 /*
2517  * Set device link up: enable tx.
2518  */
2519 static int
2520 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2521 {
2522         struct ixgbe_hw *hw =
2523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2524         if (hw->mac.type == ixgbe_mac_82599EB) {
2525 #ifdef RTE_NIC_BYPASS
2526                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2527                         /* Not suported in bypass mode */
2528                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2529                                      "by device id 0x%x", hw->device_id);
2530                         return -ENOTSUP;
2531                 }
2532 #endif
2533         }
2534
2535         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2536                 /* Turn on the copper */
2537                 ixgbe_set_phy_power(hw, true);
2538         } else {
2539                 /* Turn on the laser */
2540                 ixgbe_enable_tx_laser(hw);
2541         }
2542
2543         return 0;
2544 }
2545
2546 /*
2547  * Set device link down: disable tx.
2548  */
2549 static int
2550 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2551 {
2552         struct ixgbe_hw *hw =
2553                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2554         if (hw->mac.type == ixgbe_mac_82599EB) {
2555 #ifdef RTE_NIC_BYPASS
2556                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2557                         /* Not suported in bypass mode */
2558                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2559                                      "by device id 0x%x", hw->device_id);
2560                         return -ENOTSUP;
2561                 }
2562 #endif
2563         }
2564
2565         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2566                 /* Turn off the copper */
2567                 ixgbe_set_phy_power(hw, false);
2568         } else {
2569                 /* Turn off the laser */
2570                 ixgbe_disable_tx_laser(hw);
2571         }
2572
2573         return 0;
2574 }
2575
2576 /*
2577  * Reest and stop device.
2578  */
2579 static void
2580 ixgbe_dev_close(struct rte_eth_dev *dev)
2581 {
2582         struct ixgbe_hw *hw =
2583                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584
2585         PMD_INIT_FUNC_TRACE();
2586
2587         ixgbe_pf_reset_hw(hw);
2588
2589         ixgbe_dev_stop(dev);
2590         hw->adapter_stopped = 1;
2591
2592         ixgbe_dev_free_queues(dev);
2593
2594         ixgbe_disable_pcie_master(hw);
2595
2596         /* reprogram the RAR[0] in case user changed it. */
2597         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2598 }
2599
2600 static void
2601 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2602                            struct ixgbe_hw_stats *hw_stats,
2603                            struct ixgbe_macsec_stats *macsec_stats,
2604                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2605                            uint64_t *total_qprc, uint64_t *total_qprdc)
2606 {
2607         uint32_t bprc, lxon, lxoff, total;
2608         uint32_t delta_gprc = 0;
2609         unsigned i;
2610         /* Workaround for RX byte count not including CRC bytes when CRC
2611          * strip is enabled. CRC bytes are removed from counters when crc_strip
2612          * is disabled.
2613          */
2614         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2615                         IXGBE_HLREG0_RXCRCSTRP);
2616
2617         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2618         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2619         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2620         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2621
2622         for (i = 0; i < 8; i++) {
2623                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2624
2625                 /* global total per queue */
2626                 hw_stats->mpc[i] += mp;
2627                 /* Running comprehensive total for stats display */
2628                 *total_missed_rx += hw_stats->mpc[i];
2629                 if (hw->mac.type == ixgbe_mac_82598EB) {
2630                         hw_stats->rnbc[i] +=
2631                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2632                         hw_stats->pxonrxc[i] +=
2633                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2634                         hw_stats->pxoffrxc[i] +=
2635                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2636                 } else {
2637                         hw_stats->pxonrxc[i] +=
2638                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2639                         hw_stats->pxoffrxc[i] +=
2640                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2641                         hw_stats->pxon2offc[i] +=
2642                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2643                 }
2644                 hw_stats->pxontxc[i] +=
2645                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2646                 hw_stats->pxofftxc[i] +=
2647                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2648         }
2649         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2650                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2651                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2652                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2653
2654                 delta_gprc += delta_qprc;
2655
2656                 hw_stats->qprc[i] += delta_qprc;
2657                 hw_stats->qptc[i] += delta_qptc;
2658
2659                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2660                 hw_stats->qbrc[i] +=
2661                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2662                 if (crc_strip == 0)
2663                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2664
2665                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2666                 hw_stats->qbtc[i] +=
2667                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2668
2669                 hw_stats->qprdc[i] += delta_qprdc;
2670                 *total_qprdc += hw_stats->qprdc[i];
2671
2672                 *total_qprc += hw_stats->qprc[i];
2673                 *total_qbrc += hw_stats->qbrc[i];
2674         }
2675         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2676         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2677         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2678
2679         /*
2680          * An errata states that gprc actually counts good + missed packets:
2681          * Workaround to set gprc to summated queue packet receives
2682          */
2683         hw_stats->gprc = *total_qprc;
2684
2685         if (hw->mac.type != ixgbe_mac_82598EB) {
2686                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2687                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2688                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2689                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2690                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2691                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2692                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2693                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2694         } else {
2695                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2696                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2697                 /* 82598 only has a counter in the high register */
2698                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2699                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2700                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2701         }
2702         uint64_t old_tpr = hw_stats->tpr;
2703
2704         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2705         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2706
2707         if (crc_strip == 0)
2708                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2709
2710         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2711         hw_stats->gptc += delta_gptc;
2712         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2713         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2714
2715         /*
2716          * Workaround: mprc hardware is incorrectly counting
2717          * broadcasts, so for now we subtract those.
2718          */
2719         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2720         hw_stats->bprc += bprc;
2721         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2722         if (hw->mac.type == ixgbe_mac_82598EB)
2723                 hw_stats->mprc -= bprc;
2724
2725         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2726         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2727         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2728         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2729         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2730         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2731
2732         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2733         hw_stats->lxontxc += lxon;
2734         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2735         hw_stats->lxofftxc += lxoff;
2736         total = lxon + lxoff;
2737
2738         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2739         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2740         hw_stats->gptc -= total;
2741         hw_stats->mptc -= total;
2742         hw_stats->ptc64 -= total;
2743         hw_stats->gotc -= total * ETHER_MIN_LEN;
2744
2745         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2746         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2747         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2748         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2749         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2750         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2751         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2752         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2753         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2754         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2755         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2756         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2757         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2758         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2759         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2760         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2761         /* Only read FCOE on 82599 */
2762         if (hw->mac.type != ixgbe_mac_82598EB) {
2763                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2764                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2765                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2766                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2767                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2768         }
2769
2770         /* Flow Director Stats registers */
2771         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2772         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2773
2774         /* MACsec Stats registers */
2775         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2776         macsec_stats->out_pkts_encrypted +=
2777                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2778         macsec_stats->out_pkts_protected +=
2779                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2780         macsec_stats->out_octets_encrypted +=
2781                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2782         macsec_stats->out_octets_protected +=
2783                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2784         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2785         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2786         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2787         macsec_stats->in_pkts_unknownsci +=
2788                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2789         macsec_stats->in_octets_decrypted +=
2790                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2791         macsec_stats->in_octets_validated +=
2792                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2793         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2794         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2795         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2796         for (i = 0; i < 2; i++) {
2797                 macsec_stats->in_pkts_ok +=
2798                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2799                 macsec_stats->in_pkts_invalid +=
2800                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2801                 macsec_stats->in_pkts_notvalid +=
2802                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2803         }
2804         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2805         macsec_stats->in_pkts_notusingsa +=
2806                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2807 }
2808
2809 /*
2810  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2811  */
2812 static void
2813 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2814 {
2815         struct ixgbe_hw *hw =
2816                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817         struct ixgbe_hw_stats *hw_stats =
2818                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2819         struct ixgbe_macsec_stats *macsec_stats =
2820                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2821                                 dev->data->dev_private);
2822         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2823         unsigned i;
2824
2825         total_missed_rx = 0;
2826         total_qbrc = 0;
2827         total_qprc = 0;
2828         total_qprdc = 0;
2829
2830         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2831                         &total_qbrc, &total_qprc, &total_qprdc);
2832
2833         if (stats == NULL)
2834                 return;
2835
2836         /* Fill out the rte_eth_stats statistics structure */
2837         stats->ipackets = total_qprc;
2838         stats->ibytes = total_qbrc;
2839         stats->opackets = hw_stats->gptc;
2840         stats->obytes = hw_stats->gotc;
2841
2842         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2843                 stats->q_ipackets[i] = hw_stats->qprc[i];
2844                 stats->q_opackets[i] = hw_stats->qptc[i];
2845                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2846                 stats->q_obytes[i] = hw_stats->qbtc[i];
2847                 stats->q_errors[i] = hw_stats->qprdc[i];
2848         }
2849
2850         /* Rx Errors */
2851         stats->imissed  = total_missed_rx;
2852         stats->ierrors  = hw_stats->crcerrs +
2853                           hw_stats->mspdc +
2854                           hw_stats->rlec +
2855                           hw_stats->ruc +
2856                           hw_stats->roc +
2857                           hw_stats->illerrc +
2858                           hw_stats->errbc +
2859                           hw_stats->rfc +
2860                           hw_stats->fccrc +
2861                           hw_stats->fclast;
2862
2863         /* Tx Errors */
2864         stats->oerrors  = 0;
2865 }
2866
2867 static void
2868 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2869 {
2870         struct ixgbe_hw_stats *stats =
2871                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2872
2873         /* HW registers are cleared on read */
2874         ixgbe_dev_stats_get(dev, NULL);
2875
2876         /* Reset software totals */
2877         memset(stats, 0, sizeof(*stats));
2878 }
2879
2880 /* This function calculates the number of xstats based on the current config */
2881 static unsigned
2882 ixgbe_xstats_calc_num(void) {
2883         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
2884                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2885                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2886 }
2887
2888 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2889         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2890 {
2891         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2892         unsigned stat, i, count;
2893
2894         if (xstats_names != NULL) {
2895                 count = 0;
2896
2897                 /* Note: limit >= cnt_stats checked upstream
2898                  * in rte_eth_xstats_names()
2899                  */
2900
2901                 /* Extended stats from ixgbe_hw_stats */
2902                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2903                         snprintf(xstats_names[count].name,
2904                                 sizeof(xstats_names[count].name),
2905                                 "%s",
2906                                 rte_ixgbe_stats_strings[i].name);
2907                         count++;
2908                 }
2909
2910                 /* MACsec Stats */
2911                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
2912                         snprintf(xstats_names[count].name,
2913                                 sizeof(xstats_names[count].name),
2914                                 "%s",
2915                                 rte_ixgbe_macsec_strings[i].name);
2916                         count++;
2917                 }
2918
2919                 /* RX Priority Stats */
2920                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2921                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2922                                 snprintf(xstats_names[count].name,
2923                                         sizeof(xstats_names[count].name),
2924                                         "rx_priority%u_%s", i,
2925                                         rte_ixgbe_rxq_strings[stat].name);
2926                                 count++;
2927                         }
2928                 }
2929
2930                 /* TX Priority Stats */
2931                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2932                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2933                                 snprintf(xstats_names[count].name,
2934                                         sizeof(xstats_names[count].name),
2935                                         "tx_priority%u_%s", i,
2936                                         rte_ixgbe_txq_strings[stat].name);
2937                                 count++;
2938                         }
2939                 }
2940         }
2941         return cnt_stats;
2942 }
2943
2944 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2945         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2946 {
2947         unsigned i;
2948
2949         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2950                 return -ENOMEM;
2951
2952         if (xstats_names != NULL)
2953                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2954                         snprintf(xstats_names[i].name,
2955                                 sizeof(xstats_names[i].name),
2956                                 "%s", rte_ixgbevf_stats_strings[i].name);
2957         return IXGBEVF_NB_XSTATS;
2958 }
2959
2960 static int
2961 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2962                                          unsigned n)
2963 {
2964         struct ixgbe_hw *hw =
2965                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2966         struct ixgbe_hw_stats *hw_stats =
2967                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2968         struct ixgbe_macsec_stats *macsec_stats =
2969                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2970                                 dev->data->dev_private);
2971         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2972         unsigned i, stat, count = 0;
2973
2974         count = ixgbe_xstats_calc_num();
2975
2976         if (n < count)
2977                 return count;
2978
2979         total_missed_rx = 0;
2980         total_qbrc = 0;
2981         total_qprc = 0;
2982         total_qprdc = 0;
2983
2984         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2985                         &total_qbrc, &total_qprc, &total_qprdc);
2986
2987         /* If this is a reset xstats is NULL, and we have cleared the
2988          * registers by reading them.
2989          */
2990         if (!xstats)
2991                 return 0;
2992
2993         /* Extended stats from ixgbe_hw_stats */
2994         count = 0;
2995         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2996                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2997                                 rte_ixgbe_stats_strings[i].offset);
2998                 xstats[count].id = count;
2999                 count++;
3000         }
3001
3002         /* MACsec Stats */
3003         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3004                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3005                                 rte_ixgbe_macsec_strings[i].offset);
3006                 xstats[count].id = count;
3007                 count++;
3008         }
3009
3010         /* RX Priority Stats */
3011         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3012                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3013                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3014                                         rte_ixgbe_rxq_strings[stat].offset +
3015                                         (sizeof(uint64_t) * i));
3016                         xstats[count].id = count;
3017                         count++;
3018                 }
3019         }
3020
3021         /* TX Priority Stats */
3022         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3023                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3024                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3025                                         rte_ixgbe_txq_strings[stat].offset +
3026                                         (sizeof(uint64_t) * i));
3027                         xstats[count].id = count;
3028                         count++;
3029                 }
3030         }
3031         return count;
3032 }
3033
3034 static void
3035 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3036 {
3037         struct ixgbe_hw_stats *stats =
3038                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3039         struct ixgbe_macsec_stats *macsec_stats =
3040                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3041                                 dev->data->dev_private);
3042
3043         unsigned count = ixgbe_xstats_calc_num();
3044
3045         /* HW registers are cleared on read */
3046         ixgbe_dev_xstats_get(dev, NULL, count);
3047
3048         /* Reset software totals */
3049         memset(stats, 0, sizeof(*stats));
3050         memset(macsec_stats, 0, sizeof(*macsec_stats));
3051 }
3052
3053 static void
3054 ixgbevf_update_stats(struct rte_eth_dev *dev)
3055 {
3056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3057         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3058                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3059
3060         /* Good Rx packet, include VF loopback */
3061         UPDATE_VF_STAT(IXGBE_VFGPRC,
3062             hw_stats->last_vfgprc, hw_stats->vfgprc);
3063
3064         /* Good Rx octets, include VF loopback */
3065         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3066             hw_stats->last_vfgorc, hw_stats->vfgorc);
3067
3068         /* Good Tx packet, include VF loopback */
3069         UPDATE_VF_STAT(IXGBE_VFGPTC,
3070             hw_stats->last_vfgptc, hw_stats->vfgptc);
3071
3072         /* Good Tx octets, include VF loopback */
3073         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3074             hw_stats->last_vfgotc, hw_stats->vfgotc);
3075
3076         /* Rx Multicst Packet */
3077         UPDATE_VF_STAT(IXGBE_VFMPRC,
3078             hw_stats->last_vfmprc, hw_stats->vfmprc);
3079 }
3080
3081 static int
3082 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3083                        unsigned n)
3084 {
3085         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3086                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3087         unsigned i;
3088
3089         if (n < IXGBEVF_NB_XSTATS)
3090                 return IXGBEVF_NB_XSTATS;
3091
3092         ixgbevf_update_stats(dev);
3093
3094         if (!xstats)
3095                 return 0;
3096
3097         /* Extended stats */
3098         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3099                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3100                         rte_ixgbevf_stats_strings[i].offset);
3101         }
3102
3103         return IXGBEVF_NB_XSTATS;
3104 }
3105
3106 static void
3107 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3108 {
3109         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3110                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3111
3112         ixgbevf_update_stats(dev);
3113
3114         if (stats == NULL)
3115                 return;
3116
3117         stats->ipackets = hw_stats->vfgprc;
3118         stats->ibytes = hw_stats->vfgorc;
3119         stats->opackets = hw_stats->vfgptc;
3120         stats->obytes = hw_stats->vfgotc;
3121 }
3122
3123 static void
3124 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3125 {
3126         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3127                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3128
3129         /* Sync HW register to the last stats */
3130         ixgbevf_dev_stats_get(dev, NULL);
3131
3132         /* reset HW current stats*/
3133         hw_stats->vfgprc = 0;
3134         hw_stats->vfgorc = 0;
3135         hw_stats->vfgptc = 0;
3136         hw_stats->vfgotc = 0;
3137 }
3138
3139 static int
3140 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3141 {
3142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3143         u16 eeprom_verh, eeprom_verl;
3144         u32 etrack_id;
3145         int ret;
3146
3147         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3148         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3149
3150         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3151         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3152
3153         ret += 1; /* add the size of '\0' */
3154         if (fw_size < (u32)ret)
3155                 return ret;
3156         else
3157                 return 0;
3158 }
3159
3160 static void
3161 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3162 {
3163         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3164         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3165         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3166
3167         dev_info->pci_dev = pci_dev;
3168         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3169         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3170         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3171                 /*
3172                  * When DCB/VT is off, maximum number of queues changes,
3173                  * except for 82598EB, which remains constant.
3174                  */
3175                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3176                                 hw->mac.type != ixgbe_mac_82598EB)
3177                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3178         }
3179         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3180         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3181         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3182         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3183         dev_info->max_vfs = pci_dev->max_vfs;
3184         if (hw->mac.type == ixgbe_mac_82598EB)
3185                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3186         else
3187                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3188         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3189         dev_info->rx_offload_capa =
3190                 DEV_RX_OFFLOAD_VLAN_STRIP |
3191                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3192                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3193                 DEV_RX_OFFLOAD_TCP_CKSUM;
3194
3195         /*
3196          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3197          * mode.
3198          */
3199         if ((hw->mac.type == ixgbe_mac_82599EB ||
3200              hw->mac.type == ixgbe_mac_X540) &&
3201             !RTE_ETH_DEV_SRIOV(dev).active)
3202                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3203
3204         if (hw->mac.type == ixgbe_mac_82599EB ||
3205             hw->mac.type == ixgbe_mac_X540)
3206                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3207
3208         if (hw->mac.type == ixgbe_mac_X550 ||
3209             hw->mac.type == ixgbe_mac_X550EM_x ||
3210             hw->mac.type == ixgbe_mac_X550EM_a)
3211                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3212
3213         dev_info->tx_offload_capa =
3214                 DEV_TX_OFFLOAD_VLAN_INSERT |
3215                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3216                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3217                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3218                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3219                 DEV_TX_OFFLOAD_TCP_TSO;
3220
3221         if (hw->mac.type == ixgbe_mac_82599EB ||
3222             hw->mac.type == ixgbe_mac_X540)
3223                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3224
3225         if (hw->mac.type == ixgbe_mac_X550 ||
3226             hw->mac.type == ixgbe_mac_X550EM_x ||
3227             hw->mac.type == ixgbe_mac_X550EM_a)
3228                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3229
3230         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3231                 .rx_thresh = {
3232                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3233                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3234                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3235                 },
3236                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3237                 .rx_drop_en = 0,
3238         };
3239
3240         dev_info->default_txconf = (struct rte_eth_txconf) {
3241                 .tx_thresh = {
3242                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3243                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3244                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3245                 },
3246                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3247                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3248                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3249                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3250         };
3251
3252         dev_info->rx_desc_lim = rx_desc_lim;
3253         dev_info->tx_desc_lim = tx_desc_lim;
3254
3255         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3256         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3257         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3258
3259         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3260         if (hw->mac.type == ixgbe_mac_X540 ||
3261             hw->mac.type == ixgbe_mac_X540_vf ||
3262             hw->mac.type == ixgbe_mac_X550 ||
3263             hw->mac.type == ixgbe_mac_X550_vf) {
3264                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3265         }
3266 }
3267
3268 static const uint32_t *
3269 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3270 {
3271         static const uint32_t ptypes[] = {
3272                 /* For non-vec functions,
3273                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3274                  * for vec functions,
3275                  * refers to _recv_raw_pkts_vec().
3276                  */
3277                 RTE_PTYPE_L2_ETHER,
3278                 RTE_PTYPE_L3_IPV4,
3279                 RTE_PTYPE_L3_IPV4_EXT,
3280                 RTE_PTYPE_L3_IPV6,
3281                 RTE_PTYPE_L3_IPV6_EXT,
3282                 RTE_PTYPE_L4_SCTP,
3283                 RTE_PTYPE_L4_TCP,
3284                 RTE_PTYPE_L4_UDP,
3285                 RTE_PTYPE_TUNNEL_IP,
3286                 RTE_PTYPE_INNER_L3_IPV6,
3287                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3288                 RTE_PTYPE_INNER_L4_TCP,
3289                 RTE_PTYPE_INNER_L4_UDP,
3290                 RTE_PTYPE_UNKNOWN
3291         };
3292
3293         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3294             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3295             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3296             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3297                 return ptypes;
3298         return NULL;
3299 }
3300
3301 static void
3302 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3303                      struct rte_eth_dev_info *dev_info)
3304 {
3305         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307
3308         dev_info->pci_dev = pci_dev;
3309         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3310         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3311         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3312         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3313         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3314         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3315         dev_info->max_vfs = pci_dev->max_vfs;
3316         if (hw->mac.type == ixgbe_mac_82598EB)
3317                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3318         else
3319                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3320         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3321                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3322                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3323                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3324         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3325                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3326                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3327                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3328                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3329                                 DEV_TX_OFFLOAD_TCP_TSO;
3330
3331         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3332                 .rx_thresh = {
3333                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3334                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3335                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3336                 },
3337                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3338                 .rx_drop_en = 0,
3339         };
3340
3341         dev_info->default_txconf = (struct rte_eth_txconf) {
3342                 .tx_thresh = {
3343                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3344                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3345                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3346                 },
3347                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3348                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3349                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3350                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3351         };
3352
3353         dev_info->rx_desc_lim = rx_desc_lim;
3354         dev_info->tx_desc_lim = tx_desc_lim;
3355 }
3356
3357 /* return 0 means link status changed, -1 means not changed */
3358 static int
3359 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3360 {
3361         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3362         struct rte_eth_link link, old;
3363         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3364         int link_up;
3365         int diag;
3366
3367         link.link_status = ETH_LINK_DOWN;
3368         link.link_speed = 0;
3369         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3370         memset(&old, 0, sizeof(old));
3371         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3372
3373         hw->mac.get_link_status = true;
3374
3375         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3376         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3377                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3378         else
3379                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3380
3381         if (diag != 0) {
3382                 link.link_speed = ETH_SPEED_NUM_100M;
3383                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3384                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3385                 if (link.link_status == old.link_status)
3386                         return -1;
3387                 return 0;
3388         }
3389
3390         if (link_up == 0) {
3391                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3392                 if (link.link_status == old.link_status)
3393                         return -1;
3394                 return 0;
3395         }
3396         link.link_status = ETH_LINK_UP;
3397         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3398
3399         switch (link_speed) {
3400         default:
3401         case IXGBE_LINK_SPEED_UNKNOWN:
3402                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3403                 link.link_speed = ETH_SPEED_NUM_100M;
3404                 break;
3405
3406         case IXGBE_LINK_SPEED_100_FULL:
3407                 link.link_speed = ETH_SPEED_NUM_100M;
3408                 break;
3409
3410         case IXGBE_LINK_SPEED_1GB_FULL:
3411                 link.link_speed = ETH_SPEED_NUM_1G;
3412                 break;
3413
3414         case IXGBE_LINK_SPEED_10GB_FULL:
3415                 link.link_speed = ETH_SPEED_NUM_10G;
3416                 break;
3417         }
3418         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3419
3420         if (link.link_status == old.link_status)
3421                 return -1;
3422
3423         return 0;
3424 }
3425
3426 static void
3427 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3428 {
3429         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3430         uint32_t fctrl;
3431
3432         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3433         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3434         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3435 }
3436
3437 static void
3438 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3439 {
3440         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3441         uint32_t fctrl;
3442
3443         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3444         fctrl &= (~IXGBE_FCTRL_UPE);
3445         if (dev->data->all_multicast == 1)
3446                 fctrl |= IXGBE_FCTRL_MPE;
3447         else
3448                 fctrl &= (~IXGBE_FCTRL_MPE);
3449         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3450 }
3451
3452 static void
3453 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3454 {
3455         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3456         uint32_t fctrl;
3457
3458         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3459         fctrl |= IXGBE_FCTRL_MPE;
3460         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3461 }
3462
3463 static void
3464 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3465 {
3466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3467         uint32_t fctrl;
3468
3469         if (dev->data->promiscuous == 1)
3470                 return; /* must remain in all_multicast mode */
3471
3472         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3473         fctrl &= (~IXGBE_FCTRL_MPE);
3474         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3475 }
3476
3477 /**
3478  * It clears the interrupt causes and enables the interrupt.
3479  * It will be called once only during nic initialized.
3480  *
3481  * @param dev
3482  *  Pointer to struct rte_eth_dev.
3483  *
3484  * @return
3485  *  - On success, zero.
3486  *  - On failure, a negative value.
3487  */
3488 static int
3489 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3490 {
3491         struct ixgbe_interrupt *intr =
3492                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3493
3494         ixgbe_dev_link_status_print(dev);
3495         intr->mask |= IXGBE_EICR_LSC;
3496
3497         return 0;
3498 }
3499
3500 /**
3501  * It clears the interrupt causes and enables the interrupt.
3502  * It will be called once only during nic initialized.
3503  *
3504  * @param dev
3505  *  Pointer to struct rte_eth_dev.
3506  *
3507  * @return
3508  *  - On success, zero.
3509  *  - On failure, a negative value.
3510  */
3511 static int
3512 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3513 {
3514         struct ixgbe_interrupt *intr =
3515                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3516
3517         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3518
3519         return 0;
3520 }
3521
3522 /**
3523  * It clears the interrupt causes and enables the interrupt.
3524  * It will be called once only during nic initialized.
3525  *
3526  * @param dev
3527  *  Pointer to struct rte_eth_dev.
3528  *
3529  * @return
3530  *  - On success, zero.
3531  *  - On failure, a negative value.
3532  */
3533 static int
3534 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3535 {
3536         struct ixgbe_interrupt *intr =
3537                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3538
3539         intr->mask |= IXGBE_EICR_LINKSEC;
3540
3541         return 0;
3542 }
3543
3544 /*
3545  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3546  *
3547  * @param dev
3548  *  Pointer to struct rte_eth_dev.
3549  *
3550  * @return
3551  *  - On success, zero.
3552  *  - On failure, a negative value.
3553  */
3554 static int
3555 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3556 {
3557         uint32_t eicr;
3558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3559         struct ixgbe_interrupt *intr =
3560                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3561
3562         /* clear all cause mask */
3563         ixgbe_disable_intr(hw);
3564
3565         /* read-on-clear nic registers here */
3566         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3567         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3568
3569         intr->flags = 0;
3570
3571         /* set flag for async link update */
3572         if (eicr & IXGBE_EICR_LSC)
3573                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3574
3575         if (eicr & IXGBE_EICR_MAILBOX)
3576                 intr->flags |= IXGBE_FLAG_MAILBOX;
3577
3578         if (eicr & IXGBE_EICR_LINKSEC)
3579                 intr->flags |= IXGBE_FLAG_MACSEC;
3580
3581         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3582             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3583             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3584                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3585
3586         return 0;
3587 }
3588
3589 /**
3590  * It gets and then prints the link status.
3591  *
3592  * @param dev
3593  *  Pointer to struct rte_eth_dev.
3594  *
3595  * @return
3596  *  - On success, zero.
3597  *  - On failure, a negative value.
3598  */
3599 static void
3600 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3601 {
3602         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3603         struct rte_eth_link link;
3604
3605         memset(&link, 0, sizeof(link));
3606         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3607         if (link.link_status) {
3608                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3609                                         (int)(dev->data->port_id),
3610                                         (unsigned)link.link_speed,
3611                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3612                                         "full-duplex" : "half-duplex");
3613         } else {
3614                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3615                                 (int)(dev->data->port_id));
3616         }
3617         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3618                                 pci_dev->addr.domain,
3619                                 pci_dev->addr.bus,
3620                                 pci_dev->addr.devid,
3621                                 pci_dev->addr.function);
3622 }
3623
3624 /*
3625  * It executes link_update after knowing an interrupt occurred.
3626  *
3627  * @param dev
3628  *  Pointer to struct rte_eth_dev.
3629  *
3630  * @return
3631  *  - On success, zero.
3632  *  - On failure, a negative value.
3633  */
3634 static int
3635 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3636                            struct rte_intr_handle *intr_handle)
3637 {
3638         struct ixgbe_interrupt *intr =
3639                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3640         int64_t timeout;
3641         struct rte_eth_link link;
3642         int intr_enable_delay = false;
3643         struct ixgbe_hw *hw =
3644                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3645
3646         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3647
3648         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3649                 ixgbe_pf_mbx_process(dev);
3650                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3651         }
3652
3653         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3654                 ixgbe_handle_lasi(hw);
3655                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3656         }
3657
3658         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3659                 /* get the link status before link update, for predicting later */
3660                 memset(&link, 0, sizeof(link));
3661                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3662
3663                 ixgbe_dev_link_update(dev, 0);
3664
3665                 /* likely to up */
3666                 if (!link.link_status)
3667                         /* handle it 1 sec later, wait it being stable */
3668                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3669                 /* likely to down */
3670                 else
3671                         /* handle it 4 sec later, wait it being stable */
3672                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3673
3674                 ixgbe_dev_link_status_print(dev);
3675
3676                 intr_enable_delay = true;
3677         }
3678
3679         if (intr_enable_delay) {
3680                 if (rte_eal_alarm_set(timeout * 1000,
3681                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3682                         PMD_DRV_LOG(ERR, "Error setting alarm");
3683         } else {
3684                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3685                 ixgbe_enable_intr(dev);
3686                 rte_intr_enable(intr_handle);
3687         }
3688
3689
3690         return 0;
3691 }
3692
3693 /**
3694  * Interrupt handler which shall be registered for alarm callback for delayed
3695  * handling specific interrupt to wait for the stable nic state. As the
3696  * NIC interrupt state is not stable for ixgbe after link is just down,
3697  * it needs to wait 4 seconds to get the stable status.
3698  *
3699  * @param handle
3700  *  Pointer to interrupt handle.
3701  * @param param
3702  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3703  *
3704  * @return
3705  *  void
3706  */
3707 static void
3708 ixgbe_dev_interrupt_delayed_handler(void *param)
3709 {
3710         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3711         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3712         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3713         struct ixgbe_interrupt *intr =
3714                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3715         struct ixgbe_hw *hw =
3716                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3717         uint32_t eicr;
3718
3719         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3720         if (eicr & IXGBE_EICR_MAILBOX)
3721                 ixgbe_pf_mbx_process(dev);
3722
3723         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3724                 ixgbe_handle_lasi(hw);
3725                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3726         }
3727
3728         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3729                 ixgbe_dev_link_update(dev, 0);
3730                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3731                 ixgbe_dev_link_status_print(dev);
3732                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3733         }
3734
3735         if (intr->flags & IXGBE_FLAG_MACSEC) {
3736                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3737                                               NULL);
3738                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3739         }
3740
3741         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3742         ixgbe_enable_intr(dev);
3743         rte_intr_enable(intr_handle);
3744 }
3745
3746 /**
3747  * Interrupt handler triggered by NIC  for handling
3748  * specific interrupt.
3749  *
3750  * @param handle
3751  *  Pointer to interrupt handle.
3752  * @param param
3753  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3754  *
3755  * @return
3756  *  void
3757  */
3758 static void
3759 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3760                             void *param)
3761 {
3762         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3763
3764         ixgbe_dev_interrupt_get_status(dev);
3765         ixgbe_dev_interrupt_action(dev, handle);
3766 }
3767
3768 static int
3769 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3770 {
3771         struct ixgbe_hw *hw;
3772
3773         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3774         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3775 }
3776
3777 static int
3778 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3779 {
3780         struct ixgbe_hw *hw;
3781
3782         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3783         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3784 }
3785
3786 static int
3787 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3788 {
3789         struct ixgbe_hw *hw;
3790         uint32_t mflcn_reg;
3791         uint32_t fccfg_reg;
3792         int rx_pause;
3793         int tx_pause;
3794
3795         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796
3797         fc_conf->pause_time = hw->fc.pause_time;
3798         fc_conf->high_water = hw->fc.high_water[0];
3799         fc_conf->low_water = hw->fc.low_water[0];
3800         fc_conf->send_xon = hw->fc.send_xon;
3801         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3802
3803         /*
3804          * Return rx_pause status according to actual setting of
3805          * MFLCN register.
3806          */
3807         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3808         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3809                 rx_pause = 1;
3810         else
3811                 rx_pause = 0;
3812
3813         /*
3814          * Return tx_pause status according to actual setting of
3815          * FCCFG register.
3816          */
3817         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3818         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3819                 tx_pause = 1;
3820         else
3821                 tx_pause = 0;
3822
3823         if (rx_pause && tx_pause)
3824                 fc_conf->mode = RTE_FC_FULL;
3825         else if (rx_pause)
3826                 fc_conf->mode = RTE_FC_RX_PAUSE;
3827         else if (tx_pause)
3828                 fc_conf->mode = RTE_FC_TX_PAUSE;
3829         else
3830                 fc_conf->mode = RTE_FC_NONE;
3831
3832         return 0;
3833 }
3834
3835 static int
3836 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3837 {
3838         struct ixgbe_hw *hw;
3839         int err;
3840         uint32_t rx_buf_size;
3841         uint32_t max_high_water;
3842         uint32_t mflcn;
3843         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3844                 ixgbe_fc_none,
3845                 ixgbe_fc_rx_pause,
3846                 ixgbe_fc_tx_pause,
3847                 ixgbe_fc_full
3848         };
3849
3850         PMD_INIT_FUNC_TRACE();
3851
3852         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3853         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3854         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3855
3856         /*
3857          * At least reserve one Ethernet frame for watermark
3858          * high_water/low_water in kilo bytes for ixgbe
3859          */
3860         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3861         if ((fc_conf->high_water > max_high_water) ||
3862                 (fc_conf->high_water < fc_conf->low_water)) {
3863                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3864                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3865                 return -EINVAL;
3866         }
3867
3868         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3869         hw->fc.pause_time     = fc_conf->pause_time;
3870         hw->fc.high_water[0]  = fc_conf->high_water;
3871         hw->fc.low_water[0]   = fc_conf->low_water;
3872         hw->fc.send_xon       = fc_conf->send_xon;
3873         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3874
3875         err = ixgbe_fc_enable(hw);
3876
3877         /* Not negotiated is not an error case */
3878         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3879
3880                 /* check if we want to forward MAC frames - driver doesn't have native
3881                  * capability to do that, so we'll write the registers ourselves */
3882
3883                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3884
3885                 /* set or clear MFLCN.PMCF bit depending on configuration */
3886                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3887                         mflcn |= IXGBE_MFLCN_PMCF;
3888                 else
3889                         mflcn &= ~IXGBE_MFLCN_PMCF;
3890
3891                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3892                 IXGBE_WRITE_FLUSH(hw);
3893
3894                 return 0;
3895         }
3896
3897         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3898         return -EIO;
3899 }
3900
3901 /**
3902  *  ixgbe_pfc_enable_generic - Enable flow control
3903  *  @hw: pointer to hardware structure
3904  *  @tc_num: traffic class number
3905  *  Enable flow control according to the current settings.
3906  */
3907 static int
3908 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3909 {
3910         int ret_val = 0;
3911         uint32_t mflcn_reg, fccfg_reg;
3912         uint32_t reg;
3913         uint32_t fcrtl, fcrth;
3914         uint8_t i;
3915         uint8_t nb_rx_en;
3916
3917         /* Validate the water mark configuration */
3918         if (!hw->fc.pause_time) {
3919                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3920                 goto out;
3921         }
3922
3923         /* Low water mark of zero causes XOFF floods */
3924         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3925                  /* High/Low water can not be 0 */
3926                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3927                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3928                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3929                         goto out;
3930                 }
3931
3932                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3933                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3934                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3935                         goto out;
3936                 }
3937         }
3938         /* Negotiate the fc mode to use */
3939         ixgbe_fc_autoneg(hw);
3940
3941         /* Disable any previous flow control settings */
3942         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3943         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3944
3945         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3946         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3947
3948         switch (hw->fc.current_mode) {
3949         case ixgbe_fc_none:
3950                 /*
3951                  * If the count of enabled RX Priority Flow control >1,
3952                  * and the TX pause can not be disabled
3953                  */
3954                 nb_rx_en = 0;
3955                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3956                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3957                         if (reg & IXGBE_FCRTH_FCEN)
3958                                 nb_rx_en++;
3959                 }
3960                 if (nb_rx_en > 1)
3961                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3962                 break;
3963         case ixgbe_fc_rx_pause:
3964                 /*
3965                  * Rx Flow control is enabled and Tx Flow control is
3966                  * disabled by software override. Since there really
3967                  * isn't a way to advertise that we are capable of RX
3968                  * Pause ONLY, we will advertise that we support both
3969                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3970                  * disable the adapter's ability to send PAUSE frames.
3971                  */
3972                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3973                 /*
3974                  * If the count of enabled RX Priority Flow control >1,
3975                  * and the TX pause can not be disabled
3976                  */
3977                 nb_rx_en = 0;
3978                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3979                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3980                         if (reg & IXGBE_FCRTH_FCEN)
3981                                 nb_rx_en++;
3982                 }
3983                 if (nb_rx_en > 1)
3984                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3985                 break;
3986         case ixgbe_fc_tx_pause:
3987                 /*
3988                  * Tx Flow control is enabled, and Rx Flow control is
3989                  * disabled by software override.
3990                  */
3991                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3992                 break;
3993         case ixgbe_fc_full:
3994                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3995                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3996                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3997                 break;
3998         default:
3999                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4000                 ret_val = IXGBE_ERR_CONFIG;
4001                 goto out;
4002         }
4003
4004         /* Set 802.3x based flow control settings. */
4005         mflcn_reg |= IXGBE_MFLCN_DPF;
4006         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4007         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4008
4009         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4010         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4011                 hw->fc.high_water[tc_num]) {
4012                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4013                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4014                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4015         } else {
4016                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4017                 /*
4018                  * In order to prevent Tx hangs when the internal Tx
4019                  * switch is enabled we must set the high water mark
4020                  * to the maximum FCRTH value.  This allows the Tx
4021                  * switch to function even under heavy Rx workloads.
4022                  */
4023                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4024         }
4025         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4026
4027         /* Configure pause time (2 TCs per register) */
4028         reg = hw->fc.pause_time * 0x00010001;
4029         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4030                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4031
4032         /* Configure flow control refresh threshold value */
4033         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4034
4035 out:
4036         return ret_val;
4037 }
4038
4039 static int
4040 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4041 {
4042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4043         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4044
4045         if (hw->mac.type != ixgbe_mac_82598EB) {
4046                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4047         }
4048         return ret_val;
4049 }
4050
4051 static int
4052 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4053 {
4054         int err;
4055         uint32_t rx_buf_size;
4056         uint32_t max_high_water;
4057         uint8_t tc_num;
4058         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4059         struct ixgbe_hw *hw =
4060                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4061         struct ixgbe_dcb_config *dcb_config =
4062                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4063
4064         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4065                 ixgbe_fc_none,
4066                 ixgbe_fc_rx_pause,
4067                 ixgbe_fc_tx_pause,
4068                 ixgbe_fc_full
4069         };
4070
4071         PMD_INIT_FUNC_TRACE();
4072
4073         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4074         tc_num = map[pfc_conf->priority];
4075         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4076         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4077         /*
4078          * At least reserve one Ethernet frame for watermark
4079          * high_water/low_water in kilo bytes for ixgbe
4080          */
4081         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4082         if ((pfc_conf->fc.high_water > max_high_water) ||
4083             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4084                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4085                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4086                 return -EINVAL;
4087         }
4088
4089         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4090         hw->fc.pause_time = pfc_conf->fc.pause_time;
4091         hw->fc.send_xon = pfc_conf->fc.send_xon;
4092         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4093         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4094
4095         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4096
4097         /* Not negotiated is not an error case */
4098         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4099                 return 0;
4100
4101         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4102         return -EIO;
4103 }
4104
4105 static int
4106 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4107                           struct rte_eth_rss_reta_entry64 *reta_conf,
4108                           uint16_t reta_size)
4109 {
4110         uint16_t i, sp_reta_size;
4111         uint8_t j, mask;
4112         uint32_t reta, r;
4113         uint16_t idx, shift;
4114         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4115         uint32_t reta_reg;
4116
4117         PMD_INIT_FUNC_TRACE();
4118
4119         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4120                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4121                         "NIC.");
4122                 return -ENOTSUP;
4123         }
4124
4125         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4126         if (reta_size != sp_reta_size) {
4127                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4128                         "(%d) doesn't match the number hardware can supported "
4129                         "(%d)\n", reta_size, sp_reta_size);
4130                 return -EINVAL;
4131         }
4132
4133         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4134                 idx = i / RTE_RETA_GROUP_SIZE;
4135                 shift = i % RTE_RETA_GROUP_SIZE;
4136                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4137                                                 IXGBE_4_BIT_MASK);
4138                 if (!mask)
4139                         continue;
4140                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4141                 if (mask == IXGBE_4_BIT_MASK)
4142                         r = 0;
4143                 else
4144                         r = IXGBE_READ_REG(hw, reta_reg);
4145                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4146                         if (mask & (0x1 << j))
4147                                 reta |= reta_conf[idx].reta[shift + j] <<
4148                                                         (CHAR_BIT * j);
4149                         else
4150                                 reta |= r & (IXGBE_8_BIT_MASK <<
4151                                                 (CHAR_BIT * j));
4152                 }
4153                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4154         }
4155
4156         return 0;
4157 }
4158
4159 static int
4160 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4161                          struct rte_eth_rss_reta_entry64 *reta_conf,
4162                          uint16_t reta_size)
4163 {
4164         uint16_t i, sp_reta_size;
4165         uint8_t j, mask;
4166         uint32_t reta;
4167         uint16_t idx, shift;
4168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4169         uint32_t reta_reg;
4170
4171         PMD_INIT_FUNC_TRACE();
4172         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4173         if (reta_size != sp_reta_size) {
4174                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4175                         "(%d) doesn't match the number hardware can supported "
4176                         "(%d)\n", reta_size, sp_reta_size);
4177                 return -EINVAL;
4178         }
4179
4180         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4181                 idx = i / RTE_RETA_GROUP_SIZE;
4182                 shift = i % RTE_RETA_GROUP_SIZE;
4183                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4184                                                 IXGBE_4_BIT_MASK);
4185                 if (!mask)
4186                         continue;
4187
4188                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4189                 reta = IXGBE_READ_REG(hw, reta_reg);
4190                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4191                         if (mask & (0x1 << j))
4192                                 reta_conf[idx].reta[shift + j] =
4193                                         ((reta >> (CHAR_BIT * j)) &
4194                                                 IXGBE_8_BIT_MASK);
4195                 }
4196         }
4197
4198         return 0;
4199 }
4200
4201 static void
4202 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4203                                 uint32_t index, uint32_t pool)
4204 {
4205         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4206         uint32_t enable_addr = 1;
4207
4208         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4209 }
4210
4211 static void
4212 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4213 {
4214         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4215
4216         ixgbe_clear_rar(hw, index);
4217 }
4218
4219 static void
4220 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4221 {
4222         ixgbe_remove_rar(dev, 0);
4223
4224         ixgbe_add_rar(dev, addr, 0, 0);
4225 }
4226
4227 static int
4228 is_ixgbe_pmd(const char *driver_name)
4229 {
4230         if (!strstr(driver_name, "ixgbe"))
4231                 return -ENOTSUP;
4232
4233         if (strstr(driver_name, "ixgbe_vf"))
4234                 return -ENOTSUP;
4235
4236         return 0;
4237 }
4238
4239 int
4240 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4241                 struct ether_addr *mac_addr)
4242 {
4243         struct ixgbe_hw *hw;
4244         struct ixgbe_vf_info *vfinfo;
4245         int rar_entry;
4246         uint8_t *new_mac = (uint8_t *)(mac_addr);
4247         struct rte_eth_dev *dev;
4248         struct rte_eth_dev_info dev_info;
4249
4250         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4251
4252         dev = &rte_eth_devices[port];
4253         rte_eth_dev_info_get(port, &dev_info);
4254
4255         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4256                 return -ENOTSUP;
4257
4258         if (vf >= dev_info.max_vfs)
4259                 return -EINVAL;
4260
4261         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4262         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4263         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4264
4265         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4266                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4267                                 ETHER_ADDR_LEN);
4268                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4269                                 IXGBE_RAH_AV);
4270         }
4271         return -EINVAL;
4272 }
4273
4274 static int
4275 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4276 {
4277         uint32_t hlreg0;
4278         uint32_t maxfrs;
4279         struct ixgbe_hw *hw;
4280         struct rte_eth_dev_info dev_info;
4281         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4282
4283         ixgbe_dev_info_get(dev, &dev_info);
4284
4285         /* check that mtu is within the allowed range */
4286         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4287                 return -EINVAL;
4288
4289         /* refuse mtu that requires the support of scattered packets when this
4290          * feature has not been enabled before.
4291          */
4292         if (!dev->data->scattered_rx &&
4293             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4294              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4295                 return -EINVAL;
4296
4297         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4298         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4299
4300         /* switch to jumbo mode if needed */
4301         if (frame_size > ETHER_MAX_LEN) {
4302                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4303                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4304         } else {
4305                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4306                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4307         }
4308         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4309
4310         /* update max frame size */
4311         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4312
4313         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4314         maxfrs &= 0x0000FFFF;
4315         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4316         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4317
4318         return 0;
4319 }
4320
4321 /*
4322  * Virtual Function operations
4323  */
4324 static void
4325 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4326 {
4327         PMD_INIT_FUNC_TRACE();
4328
4329         /* Clear interrupt mask to stop from interrupts being generated */
4330         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4331
4332         IXGBE_WRITE_FLUSH(hw);
4333 }
4334
4335 static void
4336 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4337 {
4338         PMD_INIT_FUNC_TRACE();
4339
4340         /* VF enable interrupt autoclean */
4341         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4342         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4343         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4344
4345         IXGBE_WRITE_FLUSH(hw);
4346 }
4347
4348 static int
4349 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4350 {
4351         struct rte_eth_conf *conf = &dev->data->dev_conf;
4352         struct ixgbe_adapter *adapter =
4353                         (struct ixgbe_adapter *)dev->data->dev_private;
4354
4355         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4356                      dev->data->port_id);
4357
4358         /*
4359          * VF has no ability to enable/disable HW CRC
4360          * Keep the persistent behavior the same as Host PF
4361          */
4362 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4363         if (!conf->rxmode.hw_strip_crc) {
4364                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4365                 conf->rxmode.hw_strip_crc = 1;
4366         }
4367 #else
4368         if (conf->rxmode.hw_strip_crc) {
4369                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4370                 conf->rxmode.hw_strip_crc = 0;
4371         }
4372 #endif
4373
4374         /*
4375          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4376          * allocation or vector Rx preconditions we will reset it.
4377          */
4378         adapter->rx_bulk_alloc_allowed = true;
4379         adapter->rx_vec_allowed = true;
4380
4381         return 0;
4382 }
4383
4384 static int
4385 ixgbevf_dev_start(struct rte_eth_dev *dev)
4386 {
4387         struct ixgbe_hw *hw =
4388                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4389         uint32_t intr_vector = 0;
4390         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4391         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4392
4393         int err, mask = 0;
4394
4395         PMD_INIT_FUNC_TRACE();
4396
4397         hw->mac.ops.reset_hw(hw);
4398         hw->mac.get_link_status = true;
4399
4400         /* negotiate mailbox API version to use with the PF. */
4401         ixgbevf_negotiate_api(hw);
4402
4403         ixgbevf_dev_tx_init(dev);
4404
4405         /* This can fail when allocating mbufs for descriptor rings */
4406         err = ixgbevf_dev_rx_init(dev);
4407         if (err) {
4408                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4409                 ixgbe_dev_clear_queues(dev);
4410                 return err;
4411         }
4412
4413         /* Set vfta */
4414         ixgbevf_set_vfta_all(dev, 1);
4415
4416         /* Set HW strip */
4417         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4418                 ETH_VLAN_EXTEND_MASK;
4419         ixgbevf_vlan_offload_set(dev, mask);
4420
4421         ixgbevf_dev_rxtx_start(dev);
4422
4423         /* check and configure queue intr-vector mapping */
4424         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4425                 intr_vector = dev->data->nb_rx_queues;
4426                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4427                         return -1;
4428         }
4429
4430         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4431                 intr_handle->intr_vec =
4432                         rte_zmalloc("intr_vec",
4433                                     dev->data->nb_rx_queues * sizeof(int), 0);
4434                 if (intr_handle->intr_vec == NULL) {
4435                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4436                                      " intr_vec\n", dev->data->nb_rx_queues);
4437                         return -ENOMEM;
4438                 }
4439         }
4440         ixgbevf_configure_msix(dev);
4441
4442         rte_intr_enable(intr_handle);
4443
4444         /* Re-enable interrupt for VF */
4445         ixgbevf_intr_enable(hw);
4446
4447         return 0;
4448 }
4449
4450 static void
4451 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4452 {
4453         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4454         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4455         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4456
4457         PMD_INIT_FUNC_TRACE();
4458
4459         ixgbevf_intr_disable(hw);
4460
4461         hw->adapter_stopped = 1;
4462         ixgbe_stop_adapter(hw);
4463
4464         /*
4465           * Clear what we set, but we still keep shadow_vfta to
4466           * restore after device starts
4467           */
4468         ixgbevf_set_vfta_all(dev, 0);
4469
4470         /* Clear stored conf */
4471         dev->data->scattered_rx = 0;
4472
4473         ixgbe_dev_clear_queues(dev);
4474
4475         /* Clean datapath event and queue/vec mapping */
4476         rte_intr_efd_disable(intr_handle);
4477         if (intr_handle->intr_vec != NULL) {
4478                 rte_free(intr_handle->intr_vec);
4479                 intr_handle->intr_vec = NULL;
4480         }
4481 }
4482
4483 static void
4484 ixgbevf_dev_close(struct rte_eth_dev *dev)
4485 {
4486         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4487
4488         PMD_INIT_FUNC_TRACE();
4489
4490         ixgbe_reset_hw(hw);
4491
4492         ixgbevf_dev_stop(dev);
4493
4494         ixgbe_dev_free_queues(dev);
4495
4496         /**
4497          * Remove the VF MAC address ro ensure
4498          * that the VF traffic goes to the PF
4499          * after stop, close and detach of the VF
4500          **/
4501         ixgbevf_remove_mac_addr(dev, 0);
4502 }
4503
4504 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4505 {
4506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4507         struct ixgbe_vfta *shadow_vfta =
4508                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4509         int i = 0, j = 0, vfta = 0, mask = 1;
4510
4511         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4512                 vfta = shadow_vfta->vfta[i];
4513                 if (vfta) {
4514                         mask = 1;
4515                         for (j = 0; j < 32; j++) {
4516                                 if (vfta & mask)
4517                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4518                                                        on, false);
4519                                 mask <<= 1;
4520                         }
4521                 }
4522         }
4523
4524 }
4525
4526 static int
4527 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4528 {
4529         struct ixgbe_hw *hw =
4530                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4531         struct ixgbe_vfta *shadow_vfta =
4532                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4533         uint32_t vid_idx = 0;
4534         uint32_t vid_bit = 0;
4535         int ret = 0;
4536
4537         PMD_INIT_FUNC_TRACE();
4538
4539         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4540         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4541         if (ret) {
4542                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4543                 return ret;
4544         }
4545         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4546         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4547
4548         /* Save what we set and retore it after device reset */
4549         if (on)
4550                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4551         else
4552                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4553
4554         return 0;
4555 }
4556
4557 static void
4558 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4559 {
4560         struct ixgbe_hw *hw =
4561                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4562         uint32_t ctrl;
4563
4564         PMD_INIT_FUNC_TRACE();
4565
4566         if (queue >= hw->mac.max_rx_queues)
4567                 return;
4568
4569         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4570         if (on)
4571                 ctrl |= IXGBE_RXDCTL_VME;
4572         else
4573                 ctrl &= ~IXGBE_RXDCTL_VME;
4574         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4575
4576         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4577 }
4578
4579 static void
4580 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4581 {
4582         struct ixgbe_hw *hw =
4583                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4584         uint16_t i;
4585         int on = 0;
4586
4587         /* VF function only support hw strip feature, others are not support */
4588         if (mask & ETH_VLAN_STRIP_MASK) {
4589                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4590
4591                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4592                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4593         }
4594 }
4595
4596 static int
4597 ixgbe_vt_check(struct ixgbe_hw *hw)
4598 {
4599         uint32_t reg_val;
4600
4601         /* if Virtualization Technology is enabled */
4602         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4603         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4604                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4605                 return -1;
4606         }
4607
4608         return 0;
4609 }
4610
4611 static uint32_t
4612 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4613 {
4614         uint32_t vector = 0;
4615
4616         switch (hw->mac.mc_filter_type) {
4617         case 0:   /* use bits [47:36] of the address */
4618                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4619                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4620                 break;
4621         case 1:   /* use bits [46:35] of the address */
4622                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4623                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4624                 break;
4625         case 2:   /* use bits [45:34] of the address */
4626                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4627                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4628                 break;
4629         case 3:   /* use bits [43:32] of the address */
4630                 vector = ((uc_addr->addr_bytes[4]) |
4631                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4632                 break;
4633         default:  /* Invalid mc_filter_type */
4634                 break;
4635         }
4636
4637         /* vector can only be 12-bits or boundary will be exceeded */
4638         vector &= 0xFFF;
4639         return vector;
4640 }
4641
4642 static int
4643 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4644                         uint8_t on)
4645 {
4646         uint32_t vector;
4647         uint32_t uta_idx;
4648         uint32_t reg_val;
4649         uint32_t uta_shift;
4650         uint32_t rc;
4651         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4652         const uint32_t ixgbe_uta_bit_shift = 5;
4653         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4654         const uint32_t bit1 = 0x1;
4655
4656         struct ixgbe_hw *hw =
4657                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4658         struct ixgbe_uta_info *uta_info =
4659                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4660
4661         /* The UTA table only exists on 82599 hardware and newer */
4662         if (hw->mac.type < ixgbe_mac_82599EB)
4663                 return -ENOTSUP;
4664
4665         vector = ixgbe_uta_vector(hw, mac_addr);
4666         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4667         uta_shift = vector & ixgbe_uta_bit_mask;
4668
4669         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4670         if (rc == on)
4671                 return 0;
4672
4673         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4674         if (on) {
4675                 uta_info->uta_in_use++;
4676                 reg_val |= (bit1 << uta_shift);
4677                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4678         } else {
4679                 uta_info->uta_in_use--;
4680                 reg_val &= ~(bit1 << uta_shift);
4681                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4682         }
4683
4684         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4685
4686         if (uta_info->uta_in_use > 0)
4687                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4688                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4689         else
4690                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4691
4692         return 0;
4693 }
4694
4695 static int
4696 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4697 {
4698         int i;
4699         struct ixgbe_hw *hw =
4700                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4701         struct ixgbe_uta_info *uta_info =
4702                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4703
4704         /* The UTA table only exists on 82599 hardware and newer */
4705         if (hw->mac.type < ixgbe_mac_82599EB)
4706                 return -ENOTSUP;
4707
4708         if (on) {
4709                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4710                         uta_info->uta_shadow[i] = ~0;
4711                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4712                 }
4713         } else {
4714                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4715                         uta_info->uta_shadow[i] = 0;
4716                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4717                 }
4718         }
4719         return 0;
4720
4721 }
4722
4723 uint32_t
4724 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4725 {
4726         uint32_t new_val = orig_val;
4727
4728         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4729                 new_val |= IXGBE_VMOLR_AUPE;
4730         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4731                 new_val |= IXGBE_VMOLR_ROMPE;
4732         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4733                 new_val |= IXGBE_VMOLR_ROPE;
4734         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4735                 new_val |= IXGBE_VMOLR_BAM;
4736         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4737                 new_val |= IXGBE_VMOLR_MPE;
4738
4739         return new_val;
4740 }
4741
4742
4743 int
4744 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4745 {
4746         struct ixgbe_hw *hw;
4747         struct ixgbe_mac_info *mac;
4748         struct rte_eth_dev *dev;
4749         struct rte_eth_dev_info dev_info;
4750
4751         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4752
4753         dev = &rte_eth_devices[port];
4754         rte_eth_dev_info_get(port, &dev_info);
4755
4756         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4757                 return -ENOTSUP;
4758
4759         if (vf >= dev_info.max_vfs)
4760                 return -EINVAL;
4761
4762         if (on > 1)
4763                 return -EINVAL;
4764
4765         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4766         mac = &hw->mac;
4767
4768         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4769
4770         return 0;
4771 }
4772
4773 int
4774 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4775 {
4776         struct ixgbe_hw *hw;
4777         struct ixgbe_mac_info *mac;
4778         struct rte_eth_dev *dev;
4779         struct rte_eth_dev_info dev_info;
4780
4781         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4782
4783         dev = &rte_eth_devices[port];
4784         rte_eth_dev_info_get(port, &dev_info);
4785
4786         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4787                 return -ENOTSUP;
4788
4789         if (vf >= dev_info.max_vfs)
4790                 return -EINVAL;
4791
4792         if (on > 1)
4793                 return -EINVAL;
4794
4795         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4796         mac = &hw->mac;
4797         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4798
4799         return 0;
4800 }
4801
4802 int
4803 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4804 {
4805         struct ixgbe_hw *hw;
4806         uint32_t ctrl;
4807         struct rte_eth_dev *dev;
4808         struct rte_eth_dev_info dev_info;
4809
4810         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4811
4812         dev = &rte_eth_devices[port];
4813         rte_eth_dev_info_get(port, &dev_info);
4814
4815         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4816                 return -ENOTSUP;
4817
4818         if (vf >= dev_info.max_vfs)
4819                 return -EINVAL;
4820
4821         if (vlan_id > ETHER_MAX_VLAN_ID)
4822                 return -EINVAL;
4823
4824         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4825         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4826         if (vlan_id) {
4827                 ctrl = vlan_id;
4828                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4829         } else {
4830                 ctrl = 0;
4831         }
4832
4833         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4834
4835         return 0;
4836 }
4837
4838 int
4839 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4840 {
4841         struct ixgbe_hw *hw;
4842         uint32_t ctrl;
4843         struct rte_eth_dev *dev;
4844         struct rte_eth_dev_info dev_info;
4845
4846         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4847
4848         dev = &rte_eth_devices[port];
4849         rte_eth_dev_info_get(port, &dev_info);
4850
4851         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4852                 return -ENOTSUP;
4853
4854         if (on > 1)
4855                 return -EINVAL;
4856
4857         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4858         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4859         /* enable or disable VMDQ loopback */
4860         if (on)
4861                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4862         else
4863                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4864
4865         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4866
4867         return 0;
4868 }
4869
4870 int
4871 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4872 {
4873         struct ixgbe_hw *hw;
4874         uint32_t reg_value;
4875         int i;
4876         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4877         struct rte_eth_dev *dev;
4878         struct rte_eth_dev_info dev_info;
4879
4880         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4881
4882         dev = &rte_eth_devices[port];
4883         rte_eth_dev_info_get(port, &dev_info);
4884
4885         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4886                 return -ENOTSUP;
4887
4888         if (on > 1)
4889                 return -EINVAL;
4890
4891         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4892         for (i = 0; i <= num_queues; i++) {
4893                 reg_value = IXGBE_QDE_WRITE |
4894                                 (i << IXGBE_QDE_IDX_SHIFT) |
4895                                 (on & IXGBE_QDE_ENABLE);
4896                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4897         }
4898
4899         return 0;
4900 }
4901
4902 int
4903 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4904 {
4905         struct ixgbe_hw *hw;
4906         uint32_t reg_value;
4907         struct rte_eth_dev *dev;
4908         struct rte_eth_dev_info dev_info;
4909
4910         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4911
4912         dev = &rte_eth_devices[port];
4913         rte_eth_dev_info_get(port, &dev_info);
4914
4915         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4916                 return -ENOTSUP;
4917
4918         /* only support VF's 0 to 63 */
4919         if ((vf >= dev_info.max_vfs) || (vf > 63))
4920                 return -EINVAL;
4921
4922         if (on > 1)
4923                 return -EINVAL;
4924
4925         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4926         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4927         if (on)
4928                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4929         else
4930                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4931
4932         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4933
4934         return 0;
4935 }
4936
4937 int
4938 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4939 {
4940         struct rte_eth_dev *dev;
4941         struct rte_eth_dev_info dev_info;
4942         uint16_t queues_per_pool;
4943         uint32_t q;
4944
4945         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4946
4947         dev = &rte_eth_devices[port];
4948         rte_eth_dev_info_get(port, &dev_info);
4949
4950         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4951                 return -ENOTSUP;
4952
4953         if (vf >= dev_info.max_vfs)
4954                 return -EINVAL;
4955
4956         if (on > 1)
4957                 return -EINVAL;
4958
4959         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
4960
4961         /* The PF has 128 queue pairs and in SRIOV configuration
4962          * those queues will be assigned to VF's, so RXDCTL
4963          * registers will be dealing with queues which will be
4964          * assigned to VF's.
4965          * Let's say we have SRIOV configured with 31 VF's then the
4966          * first 124 queues 0-123 will be allocated to VF's and only
4967          * the last 4 queues 123-127 will be assigned to the PF.
4968          */
4969
4970         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
4971
4972         for (q = 0; q < queues_per_pool; q++)
4973                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
4974                                 q + vf * queues_per_pool, on);
4975         return 0;
4976 }
4977
4978 int
4979 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
4980 {
4981         int val = 0;
4982         struct rte_eth_dev *dev;
4983         struct rte_eth_dev_info dev_info;
4984         struct ixgbe_hw *hw;
4985         uint32_t vmolr;
4986
4987         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4988
4989         dev = &rte_eth_devices[port];
4990         rte_eth_dev_info_get(port, &dev_info);
4991
4992         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4993                 return -ENOTSUP;
4994
4995         if (vf >= dev_info.max_vfs)
4996                 return -EINVAL;
4997
4998         if (on > 1)
4999                 return -EINVAL;
5000
5001         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5002         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5003
5004         if (hw->mac.type == ixgbe_mac_82598EB) {
5005                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5006                              " on 82599 hardware and newer");
5007                 return -ENOTSUP;
5008         }
5009         if (ixgbe_vt_check(hw) < 0)
5010                 return -ENOTSUP;
5011
5012         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5013
5014         if (on)
5015                 vmolr |= val;
5016         else
5017                 vmolr &= ~val;
5018
5019         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5020
5021         return 0;
5022 }
5023
5024 int
5025 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5026 {
5027         struct rte_eth_dev *dev;
5028         struct rte_eth_dev_info dev_info;
5029         uint32_t reg, addr;
5030         uint32_t val;
5031         const uint8_t bit1 = 0x1;
5032         struct ixgbe_hw *hw;
5033
5034         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5035
5036         dev = &rte_eth_devices[port];
5037         rte_eth_dev_info_get(port, &dev_info);
5038
5039         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5040                 return -ENOTSUP;
5041
5042         if (vf >= dev_info.max_vfs)
5043                 return -EINVAL;
5044
5045         if (on > 1)
5046                 return -EINVAL;
5047
5048         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5049
5050         if (ixgbe_vt_check(hw) < 0)
5051                 return -ENOTSUP;
5052
5053         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5054         if (vf >= 32) {
5055                 addr = IXGBE_VFRE(1);
5056                 val = bit1 << (vf - 32);
5057         } else {
5058                 addr = IXGBE_VFRE(0);
5059                 val = bit1 << vf;
5060         }
5061
5062         reg = IXGBE_READ_REG(hw, addr);
5063
5064         if (on)
5065                 reg |= val;
5066         else
5067                 reg &= ~val;
5068
5069         IXGBE_WRITE_REG(hw, addr, reg);
5070
5071         return 0;
5072 }
5073
5074 int
5075 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5076 {
5077         struct rte_eth_dev *dev;
5078         struct rte_eth_dev_info dev_info;
5079         uint32_t reg, addr;
5080         uint32_t val;
5081         const uint8_t bit1 = 0x1;
5082
5083         struct ixgbe_hw *hw;
5084
5085         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5086
5087         dev = &rte_eth_devices[port];
5088         rte_eth_dev_info_get(port, &dev_info);
5089
5090         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5091                 return -ENOTSUP;
5092
5093         if (vf >= dev_info.max_vfs)
5094                 return -EINVAL;
5095
5096         if (on > 1)
5097                 return -EINVAL;
5098
5099         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5100         if (ixgbe_vt_check(hw) < 0)
5101                 return -ENOTSUP;
5102
5103         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5104         if (vf >= 32) {
5105                 addr = IXGBE_VFTE(1);
5106                 val = bit1 << (vf - 32);
5107         } else {
5108                 addr = IXGBE_VFTE(0);
5109                 val = bit1 << vf;
5110         }
5111
5112         reg = IXGBE_READ_REG(hw, addr);
5113
5114         if (on)
5115                 reg |= val;
5116         else
5117                 reg &= ~val;
5118
5119         IXGBE_WRITE_REG(hw, addr, reg);
5120
5121         return 0;
5122 }
5123
5124 int
5125 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5126                         uint64_t vf_mask, uint8_t vlan_on)
5127 {
5128         struct rte_eth_dev *dev;
5129         struct rte_eth_dev_info dev_info;
5130         int ret = 0;
5131         uint16_t vf_idx;
5132         struct ixgbe_hw *hw;
5133
5134         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5135
5136         dev = &rte_eth_devices[port];
5137         rte_eth_dev_info_get(port, &dev_info);
5138
5139         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5140                 return -ENOTSUP;
5141
5142         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5143                 return -EINVAL;
5144
5145         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5146         if (ixgbe_vt_check(hw) < 0)
5147                 return -ENOTSUP;
5148
5149         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5150                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5151                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5152                                                    vlan_on, false);
5153                         if (ret < 0)
5154                                 return ret;
5155                 }
5156         }
5157
5158         return ret;
5159 }
5160
5161 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5162         uint16_t tx_rate, uint64_t q_msk)
5163 {
5164         struct rte_eth_dev *dev;
5165         struct rte_eth_dev_info dev_info;
5166         struct ixgbe_hw *hw;
5167         struct ixgbe_vf_info *vfinfo;
5168         struct rte_eth_link link;
5169         uint8_t  nb_q_per_pool;
5170         uint32_t queue_stride;
5171         uint32_t queue_idx, idx = 0, vf_idx;
5172         uint32_t queue_end;
5173         uint16_t total_rate = 0;
5174         struct rte_pci_device *pci_dev;
5175
5176         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5177
5178         dev = &rte_eth_devices[port];
5179         rte_eth_dev_info_get(port, &dev_info);
5180         rte_eth_link_get_nowait(port, &link);
5181
5182         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5183                 return -ENOTSUP;
5184
5185         if (vf >= dev_info.max_vfs)
5186                 return -EINVAL;
5187
5188         if (tx_rate > link.link_speed)
5189                 return -EINVAL;
5190
5191         if (q_msk == 0)
5192                 return 0;
5193
5194         pci_dev = IXGBE_DEV_TO_PCI(dev);
5195         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5196         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5197         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5198         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5199         queue_idx = vf * queue_stride;
5200         queue_end = queue_idx + nb_q_per_pool - 1;
5201         if (queue_end >= hw->mac.max_tx_queues)
5202                 return -EINVAL;
5203
5204         if (vfinfo) {
5205                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5206                         if (vf_idx == vf)
5207                                 continue;
5208                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5209                                 idx++)
5210                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5211                 }
5212         } else {
5213                 return -EINVAL;
5214         }
5215
5216         /* Store tx_rate for this vf. */
5217         for (idx = 0; idx < nb_q_per_pool; idx++) {
5218                 if (((uint64_t)0x1 << idx) & q_msk) {
5219                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5220                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5221                         total_rate += tx_rate;
5222                 }
5223         }
5224
5225         if (total_rate > dev->data->dev_link.link_speed) {
5226                 /* Reset stored TX rate of the VF if it causes exceed
5227                  * link speed.
5228                  */
5229                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5230                 return -EINVAL;
5231         }
5232
5233         /* Set RTTBCNRC of each queue/pool for vf X  */
5234         for (; queue_idx <= queue_end; queue_idx++) {
5235                 if (0x1 & q_msk)
5236                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5237                 q_msk = q_msk >> 1;
5238         }
5239
5240         return 0;
5241 }
5242
5243 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5244 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5245 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5246 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5247 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5248         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5249         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5250
5251 static int
5252 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5253                         struct rte_eth_mirror_conf *mirror_conf,
5254                         uint8_t rule_id, uint8_t on)
5255 {
5256         uint32_t mr_ctl, vlvf;
5257         uint32_t mp_lsb = 0;
5258         uint32_t mv_msb = 0;
5259         uint32_t mv_lsb = 0;
5260         uint32_t mp_msb = 0;
5261         uint8_t i = 0;
5262         int reg_index = 0;
5263         uint64_t vlan_mask = 0;
5264
5265         const uint8_t pool_mask_offset = 32;
5266         const uint8_t vlan_mask_offset = 32;
5267         const uint8_t dst_pool_offset = 8;
5268         const uint8_t rule_mr_offset  = 4;
5269         const uint8_t mirror_rule_mask = 0x0F;
5270
5271         struct ixgbe_mirror_info *mr_info =
5272                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5273         struct ixgbe_hw *hw =
5274                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5275         uint8_t mirror_type = 0;
5276
5277         if (ixgbe_vt_check(hw) < 0)
5278                 return -ENOTSUP;
5279
5280         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5281                 return -EINVAL;
5282
5283         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5284                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5285                         mirror_conf->rule_type);
5286                 return -EINVAL;
5287         }
5288
5289         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5290                 mirror_type |= IXGBE_MRCTL_VLME;
5291                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5292                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5293                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5294                                 /* search vlan id related pool vlan filter index */
5295                                 reg_index = ixgbe_find_vlvf_slot(hw,
5296                                                  mirror_conf->vlan.vlan_id[i],
5297                                                  false);
5298                                 if (reg_index < 0)
5299                                         return -EINVAL;
5300                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5301                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5302                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5303                                       mirror_conf->vlan.vlan_id[i]))
5304                                         vlan_mask |= (1ULL << reg_index);
5305                                 else
5306                                         return -EINVAL;
5307                         }
5308                 }
5309
5310                 if (on) {
5311                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5312                         mv_msb = vlan_mask >> vlan_mask_offset;
5313
5314                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5315                                                 mirror_conf->vlan.vlan_mask;
5316                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5317                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5318                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5319                                                 mirror_conf->vlan.vlan_id[i];
5320                         }
5321                 } else {
5322                         mv_lsb = 0;
5323                         mv_msb = 0;
5324                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5325                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5326                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5327                 }
5328         }
5329
5330         /*
5331          * if enable pool mirror, write related pool mask register,if disable
5332          * pool mirror, clear PFMRVM register
5333          */
5334         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5335                 mirror_type |= IXGBE_MRCTL_VPME;
5336                 if (on) {
5337                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5338                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5339                         mr_info->mr_conf[rule_id].pool_mask =
5340                                         mirror_conf->pool_mask;
5341
5342                 } else {
5343                         mp_lsb = 0;
5344                         mp_msb = 0;
5345                         mr_info->mr_conf[rule_id].pool_mask = 0;
5346                 }
5347         }
5348         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5349                 mirror_type |= IXGBE_MRCTL_UPME;
5350         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5351                 mirror_type |= IXGBE_MRCTL_DPME;
5352
5353         /* read  mirror control register and recalculate it */
5354         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5355
5356         if (on) {
5357                 mr_ctl |= mirror_type;
5358                 mr_ctl &= mirror_rule_mask;
5359                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5360         } else
5361                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5362
5363         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5364         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5365
5366         /* write mirrror control  register */
5367         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5368
5369         /* write pool mirrror control  register */
5370         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5371                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5372                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5373                                 mp_msb);
5374         }
5375         /* write VLAN mirrror control  register */
5376         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5377                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5378                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5379                                 mv_msb);
5380         }
5381
5382         return 0;
5383 }
5384
5385 static int
5386 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5387 {
5388         int mr_ctl = 0;
5389         uint32_t lsb_val = 0;
5390         uint32_t msb_val = 0;
5391         const uint8_t rule_mr_offset = 4;
5392
5393         struct ixgbe_hw *hw =
5394                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5395         struct ixgbe_mirror_info *mr_info =
5396                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5397
5398         if (ixgbe_vt_check(hw) < 0)
5399                 return -ENOTSUP;
5400
5401         memset(&mr_info->mr_conf[rule_id], 0,
5402                 sizeof(struct rte_eth_mirror_conf));
5403
5404         /* clear PFVMCTL register */
5405         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5406
5407         /* clear pool mask register */
5408         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5409         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5410
5411         /* clear vlan mask register */
5412         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5413         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5414
5415         return 0;
5416 }
5417
5418 static int
5419 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5420 {
5421         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5422         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5423         uint32_t mask;
5424         struct ixgbe_hw *hw =
5425                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5426
5427         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5428         mask |= (1 << IXGBE_MISC_VEC_ID);
5429         RTE_SET_USED(queue_id);
5430         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5431
5432         rte_intr_enable(intr_handle);
5433
5434         return 0;
5435 }
5436
5437 static int
5438 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5439 {
5440         uint32_t mask;
5441         struct ixgbe_hw *hw =
5442                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5443
5444         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5445         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5446         RTE_SET_USED(queue_id);
5447         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5448
5449         return 0;
5450 }
5451
5452 static int
5453 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5454 {
5455         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5456         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5457         uint32_t mask;
5458         struct ixgbe_hw *hw =
5459                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5460         struct ixgbe_interrupt *intr =
5461                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5462
5463         if (queue_id < 16) {
5464                 ixgbe_disable_intr(hw);
5465                 intr->mask |= (1 << queue_id);
5466                 ixgbe_enable_intr(dev);
5467         } else if (queue_id < 32) {
5468                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5469                 mask &= (1 << queue_id);
5470                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5471         } else if (queue_id < 64) {
5472                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5473                 mask &= (1 << (queue_id - 32));
5474                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5475         }
5476         rte_intr_enable(intr_handle);
5477
5478         return 0;
5479 }
5480
5481 static int
5482 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5483 {
5484         uint32_t mask;
5485         struct ixgbe_hw *hw =
5486                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5487         struct ixgbe_interrupt *intr =
5488                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5489
5490         if (queue_id < 16) {
5491                 ixgbe_disable_intr(hw);
5492                 intr->mask &= ~(1 << queue_id);
5493                 ixgbe_enable_intr(dev);
5494         } else if (queue_id < 32) {
5495                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5496                 mask &= ~(1 << queue_id);
5497                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5498         } else if (queue_id < 64) {
5499                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5500                 mask &= ~(1 << (queue_id - 32));
5501                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5502         }
5503
5504         return 0;
5505 }
5506
5507 static void
5508 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5509                      uint8_t queue, uint8_t msix_vector)
5510 {
5511         uint32_t tmp, idx;
5512
5513         if (direction == -1) {
5514                 /* other causes */
5515                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5516                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5517                 tmp &= ~0xFF;
5518                 tmp |= msix_vector;
5519                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5520         } else {
5521                 /* rx or tx cause */
5522                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5523                 idx = ((16 * (queue & 1)) + (8 * direction));
5524                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5525                 tmp &= ~(0xFF << idx);
5526                 tmp |= (msix_vector << idx);
5527                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5528         }
5529 }
5530
5531 /**
5532  * set the IVAR registers, mapping interrupt causes to vectors
5533  * @param hw
5534  *  pointer to ixgbe_hw struct
5535  * @direction
5536  *  0 for Rx, 1 for Tx, -1 for other causes
5537  * @queue
5538  *  queue to map the corresponding interrupt to
5539  * @msix_vector
5540  *  the vector to map to the corresponding queue
5541  */
5542 static void
5543 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5544                    uint8_t queue, uint8_t msix_vector)
5545 {
5546         uint32_t tmp, idx;
5547
5548         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5549         if (hw->mac.type == ixgbe_mac_82598EB) {
5550                 if (direction == -1)
5551                         direction = 0;
5552                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5553                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5554                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5555                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5556                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5557         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5558                         (hw->mac.type == ixgbe_mac_X540)) {
5559                 if (direction == -1) {
5560                         /* other causes */
5561                         idx = ((queue & 1) * 8);
5562                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5563                         tmp &= ~(0xFF << idx);
5564                         tmp |= (msix_vector << idx);
5565                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5566                 } else {
5567                         /* rx or tx causes */
5568                         idx = ((16 * (queue & 1)) + (8 * direction));
5569                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5570                         tmp &= ~(0xFF << idx);
5571                         tmp |= (msix_vector << idx);
5572                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5573                 }
5574         }
5575 }
5576
5577 static void
5578 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5579 {
5580         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5581         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5582         struct ixgbe_hw *hw =
5583                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5584         uint32_t q_idx;
5585         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5586
5587         /* Configure VF other cause ivar */
5588         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5589
5590         /* won't configure msix register if no mapping is done
5591          * between intr vector and event fd.
5592          */
5593         if (!rte_intr_dp_is_en(intr_handle))
5594                 return;
5595
5596         /* Configure all RX queues of VF */
5597         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5598                 /* Force all queue use vector 0,
5599                  * as IXGBE_VF_MAXMSIVECOTR = 1
5600                  */
5601                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5602                 intr_handle->intr_vec[q_idx] = vector_idx;
5603         }
5604 }
5605
5606 /**
5607  * Sets up the hardware to properly generate MSI-X interrupts
5608  * @hw
5609  *  board private structure
5610  */
5611 static void
5612 ixgbe_configure_msix(struct rte_eth_dev *dev)
5613 {
5614         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5615         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5616         struct ixgbe_hw *hw =
5617                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5618         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5619         uint32_t vec = IXGBE_MISC_VEC_ID;
5620         uint32_t mask;
5621         uint32_t gpie;
5622
5623         /* won't configure msix register if no mapping is done
5624          * between intr vector and event fd
5625          */
5626         if (!rte_intr_dp_is_en(intr_handle))
5627                 return;
5628
5629         if (rte_intr_allow_others(intr_handle))
5630                 vec = base = IXGBE_RX_VEC_START;
5631
5632         /* setup GPIE for MSI-x mode */
5633         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5634         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5635                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5636         /* auto clearing and auto setting corresponding bits in EIMS
5637          * when MSI-X interrupt is triggered
5638          */
5639         if (hw->mac.type == ixgbe_mac_82598EB) {
5640                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5641         } else {
5642                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5643                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5644         }
5645         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5646
5647         /* Populate the IVAR table and set the ITR values to the
5648          * corresponding register.
5649          */
5650         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5651              queue_id++) {
5652                 /* by default, 1:1 mapping */
5653                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5654                 intr_handle->intr_vec[queue_id] = vec;
5655                 if (vec < base + intr_handle->nb_efd - 1)
5656                         vec++;
5657         }
5658
5659         switch (hw->mac.type) {
5660         case ixgbe_mac_82598EB:
5661                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5662                                    IXGBE_MISC_VEC_ID);
5663                 break;
5664         case ixgbe_mac_82599EB:
5665         case ixgbe_mac_X540:
5666                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5667                 break;
5668         default:
5669                 break;
5670         }
5671         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5672                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5673
5674         /* set up to autoclear timer, and the vectors */
5675         mask = IXGBE_EIMS_ENABLE_MASK;
5676         mask &= ~(IXGBE_EIMS_OTHER |
5677                   IXGBE_EIMS_MAILBOX |
5678                   IXGBE_EIMS_LSC);
5679
5680         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5681 }
5682
5683 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5684         uint16_t queue_idx, uint16_t tx_rate)
5685 {
5686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5687         uint32_t rf_dec, rf_int;
5688         uint32_t bcnrc_val;
5689         uint16_t link_speed = dev->data->dev_link.link_speed;
5690
5691         if (queue_idx >= hw->mac.max_tx_queues)
5692                 return -EINVAL;
5693
5694         if (tx_rate != 0) {
5695                 /* Calculate the rate factor values to set */
5696                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5697                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5698                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5699
5700                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5701                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5702                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5703                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5704         } else {
5705                 bcnrc_val = 0;
5706         }
5707
5708         /*
5709          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5710          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5711          * set as 0x4.
5712          */
5713         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5714                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5715                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5716                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5717                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5718         else
5719                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5720                         IXGBE_MMW_SIZE_DEFAULT);
5721
5722         /* Set RTTBCNRC of queue X */
5723         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5724         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5725         IXGBE_WRITE_FLUSH(hw);
5726
5727         return 0;
5728 }
5729
5730 static void
5731 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5732                      __attribute__((unused)) uint32_t index,
5733                      __attribute__((unused)) uint32_t pool)
5734 {
5735         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5736         int diag;
5737
5738         /*
5739          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5740          * operation. Trap this case to avoid exhausting the [very limited]
5741          * set of PF resources used to store VF MAC addresses.
5742          */
5743         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5744                 return;
5745         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5746         if (diag == 0)
5747                 return;
5748         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5749 }
5750
5751 static void
5752 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5753 {
5754         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5755         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5756         struct ether_addr *mac_addr;
5757         uint32_t i;
5758         int diag;
5759
5760         /*
5761          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5762          * not support the deletion of a given MAC address.
5763          * Instead, it imposes to delete all MAC addresses, then to add again
5764          * all MAC addresses with the exception of the one to be deleted.
5765          */
5766         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5767
5768         /*
5769          * Add again all MAC addresses, with the exception of the deleted one
5770          * and of the permanent MAC address.
5771          */
5772         for (i = 0, mac_addr = dev->data->mac_addrs;
5773              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5774                 /* Skip the deleted MAC address */
5775                 if (i == index)
5776                         continue;
5777                 /* Skip NULL MAC addresses */
5778                 if (is_zero_ether_addr(mac_addr))
5779                         continue;
5780                 /* Skip the permanent MAC address */
5781                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5782                         continue;
5783                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5784                 if (diag != 0)
5785                         PMD_DRV_LOG(ERR,
5786                                     "Adding again MAC address "
5787                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5788                                     "diag=%d",
5789                                     mac_addr->addr_bytes[0],
5790                                     mac_addr->addr_bytes[1],
5791                                     mac_addr->addr_bytes[2],
5792                                     mac_addr->addr_bytes[3],
5793                                     mac_addr->addr_bytes[4],
5794                                     mac_addr->addr_bytes[5],
5795                                     diag);
5796         }
5797 }
5798
5799 static void
5800 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5801 {
5802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5803
5804         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5805 }
5806
5807 #define MAC_TYPE_FILTER_SUP(type)    do {\
5808         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5809                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5810                 (type) != ixgbe_mac_X550EM_a)\
5811                 return -ENOTSUP;\
5812 } while (0)
5813
5814 static int
5815 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5816                         struct rte_eth_syn_filter *filter,
5817                         bool add)
5818 {
5819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5820         uint32_t synqf;
5821
5822         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5823                 return -EINVAL;
5824
5825         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5826
5827         if (add) {
5828                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5829                         return -EINVAL;
5830                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5831                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5832
5833                 if (filter->hig_pri)
5834                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5835                 else
5836                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5837         } else {
5838                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5839                         return -ENOENT;
5840                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5841         }
5842         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5843         IXGBE_WRITE_FLUSH(hw);
5844         return 0;
5845 }
5846
5847 static int
5848 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5849                         struct rte_eth_syn_filter *filter)
5850 {
5851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5852         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5853
5854         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5855                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5856                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5857                 return 0;
5858         }
5859         return -ENOENT;
5860 }
5861
5862 static int
5863 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5864                         enum rte_filter_op filter_op,
5865                         void *arg)
5866 {
5867         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5868         int ret;
5869
5870         MAC_TYPE_FILTER_SUP(hw->mac.type);
5871
5872         if (filter_op == RTE_ETH_FILTER_NOP)
5873                 return 0;
5874
5875         if (arg == NULL) {
5876                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5877                             filter_op);
5878                 return -EINVAL;
5879         }
5880
5881         switch (filter_op) {
5882         case RTE_ETH_FILTER_ADD:
5883                 ret = ixgbe_syn_filter_set(dev,
5884                                 (struct rte_eth_syn_filter *)arg,
5885                                 TRUE);
5886                 break;
5887         case RTE_ETH_FILTER_DELETE:
5888                 ret = ixgbe_syn_filter_set(dev,
5889                                 (struct rte_eth_syn_filter *)arg,
5890                                 FALSE);
5891                 break;
5892         case RTE_ETH_FILTER_GET:
5893                 ret = ixgbe_syn_filter_get(dev,
5894                                 (struct rte_eth_syn_filter *)arg);
5895                 break;
5896         default:
5897                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5898                 ret = -EINVAL;
5899                 break;
5900         }
5901
5902         return ret;
5903 }
5904
5905
5906 static inline enum ixgbe_5tuple_protocol
5907 convert_protocol_type(uint8_t protocol_value)
5908 {
5909         if (protocol_value == IPPROTO_TCP)
5910                 return IXGBE_FILTER_PROTOCOL_TCP;
5911         else if (protocol_value == IPPROTO_UDP)
5912                 return IXGBE_FILTER_PROTOCOL_UDP;
5913         else if (protocol_value == IPPROTO_SCTP)
5914                 return IXGBE_FILTER_PROTOCOL_SCTP;
5915         else
5916                 return IXGBE_FILTER_PROTOCOL_NONE;
5917 }
5918
5919 /*
5920  * add a 5tuple filter
5921  *
5922  * @param
5923  * dev: Pointer to struct rte_eth_dev.
5924  * index: the index the filter allocates.
5925  * filter: ponter to the filter that will be added.
5926  * rx_queue: the queue id the filter assigned to.
5927  *
5928  * @return
5929  *    - On success, zero.
5930  *    - On failure, a negative value.
5931  */
5932 static int
5933 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5934                         struct ixgbe_5tuple_filter *filter)
5935 {
5936         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5937         struct ixgbe_filter_info *filter_info =
5938                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5939         int i, idx, shift;
5940         uint32_t ftqf, sdpqf;
5941         uint32_t l34timir = 0;
5942         uint8_t mask = 0xff;
5943
5944         /*
5945          * look for an unused 5tuple filter index,
5946          * and insert the filter to list.
5947          */
5948         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5949                 idx = i / (sizeof(uint32_t) * NBBY);
5950                 shift = i % (sizeof(uint32_t) * NBBY);
5951                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5952                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5953                         filter->index = i;
5954                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5955                                           filter,
5956                                           entries);
5957                         break;
5958                 }
5959         }
5960         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5961                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5962                 return -ENOSYS;
5963         }
5964
5965         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5966                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5967         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5968
5969         ftqf = (uint32_t)(filter->filter_info.proto &
5970                 IXGBE_FTQF_PROTOCOL_MASK);
5971         ftqf |= (uint32_t)((filter->filter_info.priority &
5972                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5973         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5974                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5975         if (filter->filter_info.dst_ip_mask == 0)
5976                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5977         if (filter->filter_info.src_port_mask == 0)
5978                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5979         if (filter->filter_info.dst_port_mask == 0)
5980                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5981         if (filter->filter_info.proto_mask == 0)
5982                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5983         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5984         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5985         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5986
5987         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5988         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5989         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5990         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5991
5992         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5993         l34timir |= (uint32_t)(filter->queue <<
5994                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5995         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5996         return 0;
5997 }
5998
5999 /*
6000  * remove a 5tuple filter
6001  *
6002  * @param
6003  * dev: Pointer to struct rte_eth_dev.
6004  * filter: the pointer of the filter will be removed.
6005  */
6006 static void
6007 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6008                         struct ixgbe_5tuple_filter *filter)
6009 {
6010         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6011         struct ixgbe_filter_info *filter_info =
6012                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6013         uint16_t index = filter->index;
6014
6015         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6016                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6017         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6018         rte_free(filter);
6019
6020         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6021         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6022         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6023         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6024         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6025 }
6026
6027 static int
6028 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6029 {
6030         struct ixgbe_hw *hw;
6031         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6032
6033         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6034
6035         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6036                 return -EINVAL;
6037
6038         /* refuse mtu that requires the support of scattered packets when this
6039          * feature has not been enabled before.
6040          */
6041         if (!dev->data->scattered_rx &&
6042             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6043              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6044                 return -EINVAL;
6045
6046         /*
6047          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6048          * request of the version 2.0 of the mailbox API.
6049          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6050          * of the mailbox API.
6051          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6052          * prior to 3.11.33 which contains the following change:
6053          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6054          */
6055         ixgbevf_rlpml_set_vf(hw, max_frame);
6056
6057         /* update max frame size */
6058         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6059         return 0;
6060 }
6061
6062 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
6063         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6064                 return -ENOTSUP;\
6065 } while (0)
6066
6067 static inline struct ixgbe_5tuple_filter *
6068 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6069                         struct ixgbe_5tuple_filter_info *key)
6070 {
6071         struct ixgbe_5tuple_filter *it;
6072
6073         TAILQ_FOREACH(it, filter_list, entries) {
6074                 if (memcmp(key, &it->filter_info,
6075                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6076                         return it;
6077                 }
6078         }
6079         return NULL;
6080 }
6081
6082 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6083 static inline int
6084 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6085                         struct ixgbe_5tuple_filter_info *filter_info)
6086 {
6087         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6088                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6089                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6090                 return -EINVAL;
6091
6092         switch (filter->dst_ip_mask) {
6093         case UINT32_MAX:
6094                 filter_info->dst_ip_mask = 0;
6095                 filter_info->dst_ip = filter->dst_ip;
6096                 break;
6097         case 0:
6098                 filter_info->dst_ip_mask = 1;
6099                 break;
6100         default:
6101                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6102                 return -EINVAL;
6103         }
6104
6105         switch (filter->src_ip_mask) {
6106         case UINT32_MAX:
6107                 filter_info->src_ip_mask = 0;
6108                 filter_info->src_ip = filter->src_ip;
6109                 break;
6110         case 0:
6111                 filter_info->src_ip_mask = 1;
6112                 break;
6113         default:
6114                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6115                 return -EINVAL;
6116         }
6117
6118         switch (filter->dst_port_mask) {
6119         case UINT16_MAX:
6120                 filter_info->dst_port_mask = 0;
6121                 filter_info->dst_port = filter->dst_port;
6122                 break;
6123         case 0:
6124                 filter_info->dst_port_mask = 1;
6125                 break;
6126         default:
6127                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6128                 return -EINVAL;
6129         }
6130
6131         switch (filter->src_port_mask) {
6132         case UINT16_MAX:
6133                 filter_info->src_port_mask = 0;
6134                 filter_info->src_port = filter->src_port;
6135                 break;
6136         case 0:
6137                 filter_info->src_port_mask = 1;
6138                 break;
6139         default:
6140                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6141                 return -EINVAL;
6142         }
6143
6144         switch (filter->proto_mask) {
6145         case UINT8_MAX:
6146                 filter_info->proto_mask = 0;
6147                 filter_info->proto =
6148                         convert_protocol_type(filter->proto);
6149                 break;
6150         case 0:
6151                 filter_info->proto_mask = 1;
6152                 break;
6153         default:
6154                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6155                 return -EINVAL;
6156         }
6157
6158         filter_info->priority = (uint8_t)filter->priority;
6159         return 0;
6160 }
6161
6162 /*
6163  * add or delete a ntuple filter
6164  *
6165  * @param
6166  * dev: Pointer to struct rte_eth_dev.
6167  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6168  * add: if true, add filter, if false, remove filter
6169  *
6170  * @return
6171  *    - On success, zero.
6172  *    - On failure, a negative value.
6173  */
6174 static int
6175 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6176                         struct rte_eth_ntuple_filter *ntuple_filter,
6177                         bool add)
6178 {
6179         struct ixgbe_filter_info *filter_info =
6180                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6181         struct ixgbe_5tuple_filter_info filter_5tuple;
6182         struct ixgbe_5tuple_filter *filter;
6183         int ret;
6184
6185         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6186                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6187                 return -EINVAL;
6188         }
6189
6190         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6191         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6192         if (ret < 0)
6193                 return ret;
6194
6195         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6196                                          &filter_5tuple);
6197         if (filter != NULL && add) {
6198                 PMD_DRV_LOG(ERR, "filter exists.");
6199                 return -EEXIST;
6200         }
6201         if (filter == NULL && !add) {
6202                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6203                 return -ENOENT;
6204         }
6205
6206         if (add) {
6207                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6208                                 sizeof(struct ixgbe_5tuple_filter), 0);
6209                 if (filter == NULL)
6210                         return -ENOMEM;
6211                 (void)rte_memcpy(&filter->filter_info,
6212                                  &filter_5tuple,
6213                                  sizeof(struct ixgbe_5tuple_filter_info));
6214                 filter->queue = ntuple_filter->queue;
6215                 ret = ixgbe_add_5tuple_filter(dev, filter);
6216                 if (ret < 0) {
6217                         rte_free(filter);
6218                         return ret;
6219                 }
6220         } else
6221                 ixgbe_remove_5tuple_filter(dev, filter);
6222
6223         return 0;
6224 }
6225
6226 /*
6227  * get a ntuple filter
6228  *
6229  * @param
6230  * dev: Pointer to struct rte_eth_dev.
6231  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6232  *
6233  * @return
6234  *    - On success, zero.
6235  *    - On failure, a negative value.
6236  */
6237 static int
6238 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6239                         struct rte_eth_ntuple_filter *ntuple_filter)
6240 {
6241         struct ixgbe_filter_info *filter_info =
6242                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6243         struct ixgbe_5tuple_filter_info filter_5tuple;
6244         struct ixgbe_5tuple_filter *filter;
6245         int ret;
6246
6247         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6248                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6249                 return -EINVAL;
6250         }
6251
6252         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6253         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6254         if (ret < 0)
6255                 return ret;
6256
6257         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6258                                          &filter_5tuple);
6259         if (filter == NULL) {
6260                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6261                 return -ENOENT;
6262         }
6263         ntuple_filter->queue = filter->queue;
6264         return 0;
6265 }
6266
6267 /*
6268  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6269  * @dev: pointer to rte_eth_dev structure
6270  * @filter_op:operation will be taken.
6271  * @arg: a pointer to specific structure corresponding to the filter_op
6272  *
6273  * @return
6274  *    - On success, zero.
6275  *    - On failure, a negative value.
6276  */
6277 static int
6278 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6279                                 enum rte_filter_op filter_op,
6280                                 void *arg)
6281 {
6282         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6283         int ret;
6284
6285         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6286
6287         if (filter_op == RTE_ETH_FILTER_NOP)
6288                 return 0;
6289
6290         if (arg == NULL) {
6291                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6292                             filter_op);
6293                 return -EINVAL;
6294         }
6295
6296         switch (filter_op) {
6297         case RTE_ETH_FILTER_ADD:
6298                 ret = ixgbe_add_del_ntuple_filter(dev,
6299                         (struct rte_eth_ntuple_filter *)arg,
6300                         TRUE);
6301                 break;
6302         case RTE_ETH_FILTER_DELETE:
6303                 ret = ixgbe_add_del_ntuple_filter(dev,
6304                         (struct rte_eth_ntuple_filter *)arg,
6305                         FALSE);
6306                 break;
6307         case RTE_ETH_FILTER_GET:
6308                 ret = ixgbe_get_ntuple_filter(dev,
6309                         (struct rte_eth_ntuple_filter *)arg);
6310                 break;
6311         default:
6312                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6313                 ret = -EINVAL;
6314                 break;
6315         }
6316         return ret;
6317 }
6318
6319 static inline int
6320 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6321                         uint16_t ethertype)
6322 {
6323         int i;
6324
6325         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6326                 if (filter_info->ethertype_filters[i] == ethertype &&
6327                     (filter_info->ethertype_mask & (1 << i)))
6328                         return i;
6329         }
6330         return -1;
6331 }
6332
6333 static inline int
6334 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6335                         uint16_t ethertype)
6336 {
6337         int i;
6338
6339         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6340                 if (!(filter_info->ethertype_mask & (1 << i))) {
6341                         filter_info->ethertype_mask |= 1 << i;
6342                         filter_info->ethertype_filters[i] = ethertype;
6343                         return i;
6344                 }
6345         }
6346         return -1;
6347 }
6348
6349 static inline int
6350 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6351                         uint8_t idx)
6352 {
6353         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6354                 return -1;
6355         filter_info->ethertype_mask &= ~(1 << idx);
6356         filter_info->ethertype_filters[idx] = 0;
6357         return idx;
6358 }
6359
6360 static int
6361 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6362                         struct rte_eth_ethertype_filter *filter,
6363                         bool add)
6364 {
6365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6366         struct ixgbe_filter_info *filter_info =
6367                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6368         uint32_t etqf = 0;
6369         uint32_t etqs = 0;
6370         int ret;
6371
6372         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6373                 return -EINVAL;
6374
6375         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6376                 filter->ether_type == ETHER_TYPE_IPv6) {
6377                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6378                         " ethertype filter.", filter->ether_type);
6379                 return -EINVAL;
6380         }
6381
6382         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6383                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6384                 return -EINVAL;
6385         }
6386         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6387                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6388                 return -EINVAL;
6389         }
6390
6391         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6392         if (ret >= 0 && add) {
6393                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6394                             filter->ether_type);
6395                 return -EEXIST;
6396         }
6397         if (ret < 0 && !add) {
6398                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6399                             filter->ether_type);
6400                 return -ENOENT;
6401         }
6402
6403         if (add) {
6404                 ret = ixgbe_ethertype_filter_insert(filter_info,
6405                         filter->ether_type);
6406                 if (ret < 0) {
6407                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6408                         return -ENOSYS;
6409                 }
6410                 etqf = IXGBE_ETQF_FILTER_EN;
6411                 etqf |= (uint32_t)filter->ether_type;
6412                 etqs |= (uint32_t)((filter->queue <<
6413                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6414                                     IXGBE_ETQS_RX_QUEUE);
6415                 etqs |= IXGBE_ETQS_QUEUE_EN;
6416         } else {
6417                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6418                 if (ret < 0)
6419                         return -ENOSYS;
6420         }
6421         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6422         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6423         IXGBE_WRITE_FLUSH(hw);
6424
6425         return 0;
6426 }
6427
6428 static int
6429 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6430                         struct rte_eth_ethertype_filter *filter)
6431 {
6432         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6433         struct ixgbe_filter_info *filter_info =
6434                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6435         uint32_t etqf, etqs;
6436         int ret;
6437
6438         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6439         if (ret < 0) {
6440                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6441                             filter->ether_type);
6442                 return -ENOENT;
6443         }
6444
6445         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6446         if (etqf & IXGBE_ETQF_FILTER_EN) {
6447                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6448                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6449                 filter->flags = 0;
6450                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6451                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6452                 return 0;
6453         }
6454         return -ENOENT;
6455 }
6456
6457 /*
6458  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6459  * @dev: pointer to rte_eth_dev structure
6460  * @filter_op:operation will be taken.
6461  * @arg: a pointer to specific structure corresponding to the filter_op
6462  */
6463 static int
6464 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6465                                 enum rte_filter_op filter_op,
6466                                 void *arg)
6467 {
6468         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6469         int ret;
6470
6471         MAC_TYPE_FILTER_SUP(hw->mac.type);
6472
6473         if (filter_op == RTE_ETH_FILTER_NOP)
6474                 return 0;
6475
6476         if (arg == NULL) {
6477                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6478                             filter_op);
6479                 return -EINVAL;
6480         }
6481
6482         switch (filter_op) {
6483         case RTE_ETH_FILTER_ADD:
6484                 ret = ixgbe_add_del_ethertype_filter(dev,
6485                         (struct rte_eth_ethertype_filter *)arg,
6486                         TRUE);
6487                 break;
6488         case RTE_ETH_FILTER_DELETE:
6489                 ret = ixgbe_add_del_ethertype_filter(dev,
6490                         (struct rte_eth_ethertype_filter *)arg,
6491                         FALSE);
6492                 break;
6493         case RTE_ETH_FILTER_GET:
6494                 ret = ixgbe_get_ethertype_filter(dev,
6495                         (struct rte_eth_ethertype_filter *)arg);
6496                 break;
6497         default:
6498                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6499                 ret = -EINVAL;
6500                 break;
6501         }
6502         return ret;
6503 }
6504
6505 static int
6506 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6507                      enum rte_filter_type filter_type,
6508                      enum rte_filter_op filter_op,
6509                      void *arg)
6510 {
6511         int ret = -EINVAL;
6512
6513         switch (filter_type) {
6514         case RTE_ETH_FILTER_NTUPLE:
6515                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6516                 break;
6517         case RTE_ETH_FILTER_ETHERTYPE:
6518                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6519                 break;
6520         case RTE_ETH_FILTER_SYN:
6521                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6522                 break;
6523         case RTE_ETH_FILTER_FDIR:
6524                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6525                 break;
6526         case RTE_ETH_FILTER_L2_TUNNEL:
6527                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6528                 break;
6529         default:
6530                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6531                                                         filter_type);
6532                 break;
6533         }
6534
6535         return ret;
6536 }
6537
6538 static u8 *
6539 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6540                         u8 **mc_addr_ptr, u32 *vmdq)
6541 {
6542         u8 *mc_addr;
6543
6544         *vmdq = 0;
6545         mc_addr = *mc_addr_ptr;
6546         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6547         return mc_addr;
6548 }
6549
6550 static int
6551 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6552                           struct ether_addr *mc_addr_set,
6553                           uint32_t nb_mc_addr)
6554 {
6555         struct ixgbe_hw *hw;
6556         u8 *mc_addr_list;
6557
6558         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6559         mc_addr_list = (u8 *)mc_addr_set;
6560         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6561                                          ixgbe_dev_addr_list_itr, TRUE);
6562 }
6563
6564 static uint64_t
6565 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6566 {
6567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6568         uint64_t systime_cycles;
6569
6570         switch (hw->mac.type) {
6571         case ixgbe_mac_X550:
6572         case ixgbe_mac_X550EM_x:
6573         case ixgbe_mac_X550EM_a:
6574                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6575                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6576                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6577                                 * NSEC_PER_SEC;
6578                 break;
6579         default:
6580                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6581                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6582                                 << 32;
6583         }
6584
6585         return systime_cycles;
6586 }
6587
6588 static uint64_t
6589 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6590 {
6591         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6592         uint64_t rx_tstamp_cycles;
6593
6594         switch (hw->mac.type) {
6595         case ixgbe_mac_X550:
6596         case ixgbe_mac_X550EM_x:
6597         case ixgbe_mac_X550EM_a:
6598                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6599                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6600                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6601                                 * NSEC_PER_SEC;
6602                 break;
6603         default:
6604                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6605                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6606                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6607                                 << 32;
6608         }
6609
6610         return rx_tstamp_cycles;
6611 }
6612
6613 static uint64_t
6614 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6615 {
6616         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6617         uint64_t tx_tstamp_cycles;
6618
6619         switch (hw->mac.type) {
6620         case ixgbe_mac_X550:
6621         case ixgbe_mac_X550EM_x:
6622         case ixgbe_mac_X550EM_a:
6623                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6624                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6625                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6626                                 * NSEC_PER_SEC;
6627                 break;
6628         default:
6629                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6630                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6631                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6632                                 << 32;
6633         }
6634
6635         return tx_tstamp_cycles;
6636 }
6637
6638 static void
6639 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6640 {
6641         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6642         struct ixgbe_adapter *adapter =
6643                 (struct ixgbe_adapter *)dev->data->dev_private;
6644         struct rte_eth_link link;
6645         uint32_t incval = 0;
6646         uint32_t shift = 0;
6647
6648         /* Get current link speed. */
6649         memset(&link, 0, sizeof(link));
6650         ixgbe_dev_link_update(dev, 1);
6651         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6652
6653         switch (link.link_speed) {
6654         case ETH_SPEED_NUM_100M:
6655                 incval = IXGBE_INCVAL_100;
6656                 shift = IXGBE_INCVAL_SHIFT_100;
6657                 break;
6658         case ETH_SPEED_NUM_1G:
6659                 incval = IXGBE_INCVAL_1GB;
6660                 shift = IXGBE_INCVAL_SHIFT_1GB;
6661                 break;
6662         case ETH_SPEED_NUM_10G:
6663         default:
6664                 incval = IXGBE_INCVAL_10GB;
6665                 shift = IXGBE_INCVAL_SHIFT_10GB;
6666                 break;
6667         }
6668
6669         switch (hw->mac.type) {
6670         case ixgbe_mac_X550:
6671         case ixgbe_mac_X550EM_x:
6672         case ixgbe_mac_X550EM_a:
6673                 /* Independent of link speed. */
6674                 incval = 1;
6675                 /* Cycles read will be interpreted as ns. */
6676                 shift = 0;
6677                 /* Fall-through */
6678         case ixgbe_mac_X540:
6679                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6680                 break;
6681         case ixgbe_mac_82599EB:
6682                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6683                 shift -= IXGBE_INCVAL_SHIFT_82599;
6684                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6685                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6686                 break;
6687         default:
6688                 /* Not supported. */
6689                 return;
6690         }
6691
6692         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6693         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6694         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6695
6696         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6697         adapter->systime_tc.cc_shift = shift;
6698         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6699
6700         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6701         adapter->rx_tstamp_tc.cc_shift = shift;
6702         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6703
6704         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6705         adapter->tx_tstamp_tc.cc_shift = shift;
6706         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6707 }
6708
6709 static int
6710 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6711 {
6712         struct ixgbe_adapter *adapter =
6713                         (struct ixgbe_adapter *)dev->data->dev_private;
6714
6715         adapter->systime_tc.nsec += delta;
6716         adapter->rx_tstamp_tc.nsec += delta;
6717         adapter->tx_tstamp_tc.nsec += delta;
6718
6719         return 0;
6720 }
6721
6722 static int
6723 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6724 {
6725         uint64_t ns;
6726         struct ixgbe_adapter *adapter =
6727                         (struct ixgbe_adapter *)dev->data->dev_private;
6728
6729         ns = rte_timespec_to_ns(ts);
6730         /* Set the timecounters to a new value. */
6731         adapter->systime_tc.nsec = ns;
6732         adapter->rx_tstamp_tc.nsec = ns;
6733         adapter->tx_tstamp_tc.nsec = ns;
6734
6735         return 0;
6736 }
6737
6738 static int
6739 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6740 {
6741         uint64_t ns, systime_cycles;
6742         struct ixgbe_adapter *adapter =
6743                         (struct ixgbe_adapter *)dev->data->dev_private;
6744
6745         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6746         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6747         *ts = rte_ns_to_timespec(ns);
6748
6749         return 0;
6750 }
6751
6752 static int
6753 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6754 {
6755         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6756         uint32_t tsync_ctl;
6757         uint32_t tsauxc;
6758
6759         /* Stop the timesync system time. */
6760         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6761         /* Reset the timesync system time value. */
6762         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6763         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6764
6765         /* Enable system time for platforms where it isn't on by default. */
6766         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6767         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6768         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6769
6770         ixgbe_start_timecounters(dev);
6771
6772         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6773         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6774                         (ETHER_TYPE_1588 |
6775                          IXGBE_ETQF_FILTER_EN |
6776                          IXGBE_ETQF_1588));
6777
6778         /* Enable timestamping of received PTP packets. */
6779         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6780         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6781         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6782
6783         /* Enable timestamping of transmitted PTP packets. */
6784         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6785         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6786         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6787
6788         IXGBE_WRITE_FLUSH(hw);
6789
6790         return 0;
6791 }
6792
6793 static int
6794 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6795 {
6796         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6797         uint32_t tsync_ctl;
6798
6799         /* Disable timestamping of transmitted PTP packets. */
6800         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6801         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6802         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6803
6804         /* Disable timestamping of received PTP packets. */
6805         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6806         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6807         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6808
6809         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6810         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6811
6812         /* Stop incrementating the System Time registers. */
6813         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6814
6815         return 0;
6816 }
6817
6818 static int
6819 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6820                                  struct timespec *timestamp,
6821                                  uint32_t flags __rte_unused)
6822 {
6823         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6824         struct ixgbe_adapter *adapter =
6825                 (struct ixgbe_adapter *)dev->data->dev_private;
6826         uint32_t tsync_rxctl;
6827         uint64_t rx_tstamp_cycles;
6828         uint64_t ns;
6829
6830         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6831         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6832                 return -EINVAL;
6833
6834         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6835         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6836         *timestamp = rte_ns_to_timespec(ns);
6837
6838         return  0;
6839 }
6840
6841 static int
6842 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6843                                  struct timespec *timestamp)
6844 {
6845         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6846         struct ixgbe_adapter *adapter =
6847                 (struct ixgbe_adapter *)dev->data->dev_private;
6848         uint32_t tsync_txctl;
6849         uint64_t tx_tstamp_cycles;
6850         uint64_t ns;
6851
6852         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6853         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6854                 return -EINVAL;
6855
6856         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6857         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6858         *timestamp = rte_ns_to_timespec(ns);
6859
6860         return 0;
6861 }
6862
6863 static int
6864 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6865 {
6866         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6867         int count = 0;
6868         int g_ind = 0;
6869         const struct reg_info *reg_group;
6870         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6871                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6872
6873         while ((reg_group = reg_set[g_ind++]))
6874                 count += ixgbe_regs_group_count(reg_group);
6875
6876         return count;
6877 }
6878
6879 static int
6880 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6881 {
6882         int count = 0;
6883         int g_ind = 0;
6884         const struct reg_info *reg_group;
6885
6886         while ((reg_group = ixgbevf_regs[g_ind++]))
6887                 count += ixgbe_regs_group_count(reg_group);
6888
6889         return count;
6890 }
6891
6892 static int
6893 ixgbe_get_regs(struct rte_eth_dev *dev,
6894               struct rte_dev_reg_info *regs)
6895 {
6896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6897         uint32_t *data = regs->data;
6898         int g_ind = 0;
6899         int count = 0;
6900         const struct reg_info *reg_group;
6901         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6902                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6903
6904         if (data == NULL) {
6905                 regs->length = ixgbe_get_reg_length(dev);
6906                 regs->width = sizeof(uint32_t);
6907                 return 0;
6908         }
6909
6910         /* Support only full register dump */
6911         if ((regs->length == 0) ||
6912             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6913                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6914                         hw->device_id;
6915                 while ((reg_group = reg_set[g_ind++]))
6916                         count += ixgbe_read_regs_group(dev, &data[count],
6917                                 reg_group);
6918                 return 0;
6919         }
6920
6921         return -ENOTSUP;
6922 }
6923
6924 static int
6925 ixgbevf_get_regs(struct rte_eth_dev *dev,
6926                 struct rte_dev_reg_info *regs)
6927 {
6928         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6929         uint32_t *data = regs->data;
6930         int g_ind = 0;
6931         int count = 0;
6932         const struct reg_info *reg_group;
6933
6934         if (data == NULL) {
6935                 regs->length = ixgbevf_get_reg_length(dev);
6936                 regs->width = sizeof(uint32_t);
6937                 return 0;
6938         }
6939
6940         /* Support only full register dump */
6941         if ((regs->length == 0) ||
6942             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6943                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6944                         hw->device_id;
6945                 while ((reg_group = ixgbevf_regs[g_ind++]))
6946                         count += ixgbe_read_regs_group(dev, &data[count],
6947                                                       reg_group);
6948                 return 0;
6949         }
6950
6951         return -ENOTSUP;
6952 }
6953
6954 static int
6955 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6956 {
6957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6958
6959         /* Return unit is byte count */
6960         return hw->eeprom.word_size * 2;
6961 }
6962
6963 static int
6964 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6965                 struct rte_dev_eeprom_info *in_eeprom)
6966 {
6967         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6968         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6969         uint16_t *data = in_eeprom->data;
6970         int first, length;
6971
6972         first = in_eeprom->offset >> 1;
6973         length = in_eeprom->length >> 1;
6974         if ((first > hw->eeprom.word_size) ||
6975             ((first + length) > hw->eeprom.word_size))
6976                 return -EINVAL;
6977
6978         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6979
6980         return eeprom->ops.read_buffer(hw, first, length, data);
6981 }
6982
6983 static int
6984 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6985                 struct rte_dev_eeprom_info *in_eeprom)
6986 {
6987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6988         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6989         uint16_t *data = in_eeprom->data;
6990         int first, length;
6991
6992         first = in_eeprom->offset >> 1;
6993         length = in_eeprom->length >> 1;
6994         if ((first > hw->eeprom.word_size) ||
6995             ((first + length) > hw->eeprom.word_size))
6996                 return -EINVAL;
6997
6998         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6999
7000         return eeprom->ops.write_buffer(hw,  first, length, data);
7001 }
7002
7003 uint16_t
7004 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7005         switch (mac_type) {
7006         case ixgbe_mac_X550:
7007         case ixgbe_mac_X550EM_x:
7008         case ixgbe_mac_X550EM_a:
7009                 return ETH_RSS_RETA_SIZE_512;
7010         case ixgbe_mac_X550_vf:
7011         case ixgbe_mac_X550EM_x_vf:
7012         case ixgbe_mac_X550EM_a_vf:
7013                 return ETH_RSS_RETA_SIZE_64;
7014         default:
7015                 return ETH_RSS_RETA_SIZE_128;
7016         }
7017 }
7018
7019 uint32_t
7020 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7021         switch (mac_type) {
7022         case ixgbe_mac_X550:
7023         case ixgbe_mac_X550EM_x:
7024         case ixgbe_mac_X550EM_a:
7025                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7026                         return IXGBE_RETA(reta_idx >> 2);
7027                 else
7028                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7029         case ixgbe_mac_X550_vf:
7030         case ixgbe_mac_X550EM_x_vf:
7031         case ixgbe_mac_X550EM_a_vf:
7032                 return IXGBE_VFRETA(reta_idx >> 2);
7033         default:
7034                 return IXGBE_RETA(reta_idx >> 2);
7035         }
7036 }
7037
7038 uint32_t
7039 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7040         switch (mac_type) {
7041         case ixgbe_mac_X550_vf:
7042         case ixgbe_mac_X550EM_x_vf:
7043         case ixgbe_mac_X550EM_a_vf:
7044                 return IXGBE_VFMRQC;
7045         default:
7046                 return IXGBE_MRQC;
7047         }
7048 }
7049
7050 uint32_t
7051 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7052         switch (mac_type) {
7053         case ixgbe_mac_X550_vf:
7054         case ixgbe_mac_X550EM_x_vf:
7055         case ixgbe_mac_X550EM_a_vf:
7056                 return IXGBE_VFRSSRK(i);
7057         default:
7058                 return IXGBE_RSSRK(i);
7059         }
7060 }
7061
7062 bool
7063 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7064         switch (mac_type) {
7065         case ixgbe_mac_82599_vf:
7066         case ixgbe_mac_X540_vf:
7067                 return 0;
7068         default:
7069                 return 1;
7070         }
7071 }
7072
7073 static int
7074 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7075                         struct rte_eth_dcb_info *dcb_info)
7076 {
7077         struct ixgbe_dcb_config *dcb_config =
7078                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7079         struct ixgbe_dcb_tc_config *tc;
7080         uint8_t i, j;
7081
7082         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7083                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7084         else
7085                 dcb_info->nb_tcs = 1;
7086
7087         if (dcb_config->vt_mode) { /* vt is enabled*/
7088                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7089                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7090                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7091                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7092                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7093                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7094                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7095                                                 i * dcb_info->nb_tcs + j;
7096                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7097                                 dcb_info->tc_queue.tc_txq[i][j].base =
7098                                                 i * dcb_info->nb_tcs + j;
7099                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7100                         }
7101                 }
7102         } else { /* vt is disabled*/
7103                 struct rte_eth_dcb_rx_conf *rx_conf =
7104                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7105                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7106                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7107                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7108                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7109                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7110                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7111                         }
7112                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7113                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7114                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7115                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7116                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7117                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7118                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7119                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7120                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7121                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7122                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7123                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7124                         }
7125                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7126                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7127                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7128                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7129                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7130                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7131                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7132                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7133                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7134                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7135                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7136                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7137                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7138                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7139                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7140                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7141                 }
7142         }
7143         for (i = 0; i < dcb_info->nb_tcs; i++) {
7144                 tc = &dcb_config->tc_config[i];
7145                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7146         }
7147         return 0;
7148 }
7149
7150 /* Update e-tag ether type */
7151 static int
7152 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7153                             uint16_t ether_type)
7154 {
7155         uint32_t etag_etype;
7156
7157         if (hw->mac.type != ixgbe_mac_X550 &&
7158             hw->mac.type != ixgbe_mac_X550EM_x &&
7159             hw->mac.type != ixgbe_mac_X550EM_a) {
7160                 return -ENOTSUP;
7161         }
7162
7163         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7164         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7165         etag_etype |= ether_type;
7166         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7167         IXGBE_WRITE_FLUSH(hw);
7168
7169         return 0;
7170 }
7171
7172 /* Config l2 tunnel ether type */
7173 static int
7174 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7175                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7176 {
7177         int ret = 0;
7178         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7179
7180         if (l2_tunnel == NULL)
7181                 return -EINVAL;
7182
7183         switch (l2_tunnel->l2_tunnel_type) {
7184         case RTE_L2_TUNNEL_TYPE_E_TAG:
7185                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7186                 break;
7187         default:
7188                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7189                 ret = -EINVAL;
7190                 break;
7191         }
7192
7193         return ret;
7194 }
7195
7196 /* Enable e-tag tunnel */
7197 static int
7198 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7199 {
7200         uint32_t etag_etype;
7201
7202         if (hw->mac.type != ixgbe_mac_X550 &&
7203             hw->mac.type != ixgbe_mac_X550EM_x &&
7204             hw->mac.type != ixgbe_mac_X550EM_a) {
7205                 return -ENOTSUP;
7206         }
7207
7208         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7209         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7210         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7211         IXGBE_WRITE_FLUSH(hw);
7212
7213         return 0;
7214 }
7215
7216 /* Enable l2 tunnel */
7217 static int
7218 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7219                            enum rte_eth_tunnel_type l2_tunnel_type)
7220 {
7221         int ret = 0;
7222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7223
7224         switch (l2_tunnel_type) {
7225         case RTE_L2_TUNNEL_TYPE_E_TAG:
7226                 ret = ixgbe_e_tag_enable(hw);
7227                 break;
7228         default:
7229                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7230                 ret = -EINVAL;
7231                 break;
7232         }
7233
7234         return ret;
7235 }
7236
7237 /* Disable e-tag tunnel */
7238 static int
7239 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7240 {
7241         uint32_t etag_etype;
7242
7243         if (hw->mac.type != ixgbe_mac_X550 &&
7244             hw->mac.type != ixgbe_mac_X550EM_x &&
7245             hw->mac.type != ixgbe_mac_X550EM_a) {
7246                 return -ENOTSUP;
7247         }
7248
7249         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7250         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7251         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7252         IXGBE_WRITE_FLUSH(hw);
7253
7254         return 0;
7255 }
7256
7257 /* Disable l2 tunnel */
7258 static int
7259 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7260                             enum rte_eth_tunnel_type l2_tunnel_type)
7261 {
7262         int ret = 0;
7263         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7264
7265         switch (l2_tunnel_type) {
7266         case RTE_L2_TUNNEL_TYPE_E_TAG:
7267                 ret = ixgbe_e_tag_disable(hw);
7268                 break;
7269         default:
7270                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7271                 ret = -EINVAL;
7272                 break;
7273         }
7274
7275         return ret;
7276 }
7277
7278 static int
7279 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7280                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7281 {
7282         int ret = 0;
7283         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7284         uint32_t i, rar_entries;
7285         uint32_t rar_low, rar_high;
7286
7287         if (hw->mac.type != ixgbe_mac_X550 &&
7288             hw->mac.type != ixgbe_mac_X550EM_x &&
7289             hw->mac.type != ixgbe_mac_X550EM_a) {
7290                 return -ENOTSUP;
7291         }
7292
7293         rar_entries = ixgbe_get_num_rx_addrs(hw);
7294
7295         for (i = 1; i < rar_entries; i++) {
7296                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7297                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7298                 if ((rar_high & IXGBE_RAH_AV) &&
7299                     (rar_high & IXGBE_RAH_ADTYPE) &&
7300                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7301                      l2_tunnel->tunnel_id)) {
7302                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7303                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7304
7305                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7306
7307                         return ret;
7308                 }
7309         }
7310
7311         return ret;
7312 }
7313
7314 static int
7315 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7316                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7317 {
7318         int ret = 0;
7319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7320         uint32_t i, rar_entries;
7321         uint32_t rar_low, rar_high;
7322
7323         if (hw->mac.type != ixgbe_mac_X550 &&
7324             hw->mac.type != ixgbe_mac_X550EM_x &&
7325             hw->mac.type != ixgbe_mac_X550EM_a) {
7326                 return -ENOTSUP;
7327         }
7328
7329         /* One entry for one tunnel. Try to remove potential existing entry. */
7330         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7331
7332         rar_entries = ixgbe_get_num_rx_addrs(hw);
7333
7334         for (i = 1; i < rar_entries; i++) {
7335                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7336                 if (rar_high & IXGBE_RAH_AV) {
7337                         continue;
7338                 } else {
7339                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7340                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7341                         rar_low = l2_tunnel->tunnel_id;
7342
7343                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7344                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7345
7346                         return ret;
7347                 }
7348         }
7349
7350         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7351                      " Please remove a rule before adding a new one.");
7352         return -EINVAL;
7353 }
7354
7355 /* Add l2 tunnel filter */
7356 static int
7357 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7358                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7359 {
7360         int ret = 0;
7361
7362         switch (l2_tunnel->l2_tunnel_type) {
7363         case RTE_L2_TUNNEL_TYPE_E_TAG:
7364                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7365                 break;
7366         default:
7367                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7368                 ret = -EINVAL;
7369                 break;
7370         }
7371
7372         return ret;
7373 }
7374
7375 /* Delete l2 tunnel filter */
7376 static int
7377 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7378                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7379 {
7380         int ret = 0;
7381
7382         switch (l2_tunnel->l2_tunnel_type) {
7383         case RTE_L2_TUNNEL_TYPE_E_TAG:
7384                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7385                 break;
7386         default:
7387                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7388                 ret = -EINVAL;
7389                 break;
7390         }
7391
7392         return ret;
7393 }
7394
7395 /**
7396  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7397  * @dev: pointer to rte_eth_dev structure
7398  * @filter_op:operation will be taken.
7399  * @arg: a pointer to specific structure corresponding to the filter_op
7400  */
7401 static int
7402 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7403                                   enum rte_filter_op filter_op,
7404                                   void *arg)
7405 {
7406         int ret = 0;
7407
7408         if (filter_op == RTE_ETH_FILTER_NOP)
7409                 return 0;
7410
7411         if (arg == NULL) {
7412                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7413                             filter_op);
7414                 return -EINVAL;
7415         }
7416
7417         switch (filter_op) {
7418         case RTE_ETH_FILTER_ADD:
7419                 ret = ixgbe_dev_l2_tunnel_filter_add
7420                         (dev,
7421                          (struct rte_eth_l2_tunnel_conf *)arg);
7422                 break;
7423         case RTE_ETH_FILTER_DELETE:
7424                 ret = ixgbe_dev_l2_tunnel_filter_del
7425                         (dev,
7426                          (struct rte_eth_l2_tunnel_conf *)arg);
7427                 break;
7428         default:
7429                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7430                 ret = -EINVAL;
7431                 break;
7432         }
7433         return ret;
7434 }
7435
7436 static int
7437 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7438 {
7439         int ret = 0;
7440         uint32_t ctrl;
7441         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7442
7443         if (hw->mac.type != ixgbe_mac_X550 &&
7444             hw->mac.type != ixgbe_mac_X550EM_x &&
7445             hw->mac.type != ixgbe_mac_X550EM_a) {
7446                 return -ENOTSUP;
7447         }
7448
7449         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7450         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7451         if (en)
7452                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7453         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7454
7455         return ret;
7456 }
7457
7458 /* Enable l2 tunnel forwarding */
7459 static int
7460 ixgbe_dev_l2_tunnel_forwarding_enable
7461         (struct rte_eth_dev *dev,
7462          enum rte_eth_tunnel_type l2_tunnel_type)
7463 {
7464         int ret = 0;
7465
7466         switch (l2_tunnel_type) {
7467         case RTE_L2_TUNNEL_TYPE_E_TAG:
7468                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7469                 break;
7470         default:
7471                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7472                 ret = -EINVAL;
7473                 break;
7474         }
7475
7476         return ret;
7477 }
7478
7479 /* Disable l2 tunnel forwarding */
7480 static int
7481 ixgbe_dev_l2_tunnel_forwarding_disable
7482         (struct rte_eth_dev *dev,
7483          enum rte_eth_tunnel_type l2_tunnel_type)
7484 {
7485         int ret = 0;
7486
7487         switch (l2_tunnel_type) {
7488         case RTE_L2_TUNNEL_TYPE_E_TAG:
7489                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7490                 break;
7491         default:
7492                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7493                 ret = -EINVAL;
7494                 break;
7495         }
7496
7497         return ret;
7498 }
7499
7500 static int
7501 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7502                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7503                              bool en)
7504 {
7505         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7506         int ret = 0;
7507         uint32_t vmtir, vmvir;
7508         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7509
7510         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7511                 PMD_DRV_LOG(ERR,
7512                             "VF id %u should be less than %u",
7513                             l2_tunnel->vf_id,
7514                             pci_dev->max_vfs);
7515                 return -EINVAL;
7516         }
7517
7518         if (hw->mac.type != ixgbe_mac_X550 &&
7519             hw->mac.type != ixgbe_mac_X550EM_x &&
7520             hw->mac.type != ixgbe_mac_X550EM_a) {
7521                 return -ENOTSUP;
7522         }
7523
7524         if (en)
7525                 vmtir = l2_tunnel->tunnel_id;
7526         else
7527                 vmtir = 0;
7528
7529         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7530
7531         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7532         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7533         if (en)
7534                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7535         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7536
7537         return ret;
7538 }
7539
7540 /* Enable l2 tunnel tag insertion */
7541 static int
7542 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7543                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7544 {
7545         int ret = 0;
7546
7547         switch (l2_tunnel->l2_tunnel_type) {
7548         case RTE_L2_TUNNEL_TYPE_E_TAG:
7549                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7550                 break;
7551         default:
7552                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7553                 ret = -EINVAL;
7554                 break;
7555         }
7556
7557         return ret;
7558 }
7559
7560 /* Disable l2 tunnel tag insertion */
7561 static int
7562 ixgbe_dev_l2_tunnel_insertion_disable
7563         (struct rte_eth_dev *dev,
7564          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7565 {
7566         int ret = 0;
7567
7568         switch (l2_tunnel->l2_tunnel_type) {
7569         case RTE_L2_TUNNEL_TYPE_E_TAG:
7570                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7571                 break;
7572         default:
7573                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7574                 ret = -EINVAL;
7575                 break;
7576         }
7577
7578         return ret;
7579 }
7580
7581 static int
7582 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7583                              bool en)
7584 {
7585         int ret = 0;
7586         uint32_t qde;
7587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7588
7589         if (hw->mac.type != ixgbe_mac_X550 &&
7590             hw->mac.type != ixgbe_mac_X550EM_x &&
7591             hw->mac.type != ixgbe_mac_X550EM_a) {
7592                 return -ENOTSUP;
7593         }
7594
7595         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7596         if (en)
7597                 qde |= IXGBE_QDE_STRIP_TAG;
7598         else
7599                 qde &= ~IXGBE_QDE_STRIP_TAG;
7600         qde &= ~IXGBE_QDE_READ;
7601         qde |= IXGBE_QDE_WRITE;
7602         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7603
7604         return ret;
7605 }
7606
7607 /* Enable l2 tunnel tag stripping */
7608 static int
7609 ixgbe_dev_l2_tunnel_stripping_enable
7610         (struct rte_eth_dev *dev,
7611          enum rte_eth_tunnel_type l2_tunnel_type)
7612 {
7613         int ret = 0;
7614
7615         switch (l2_tunnel_type) {
7616         case RTE_L2_TUNNEL_TYPE_E_TAG:
7617                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7618                 break;
7619         default:
7620                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7621                 ret = -EINVAL;
7622                 break;
7623         }
7624
7625         return ret;
7626 }
7627
7628 /* Disable l2 tunnel tag stripping */
7629 static int
7630 ixgbe_dev_l2_tunnel_stripping_disable
7631         (struct rte_eth_dev *dev,
7632          enum rte_eth_tunnel_type l2_tunnel_type)
7633 {
7634         int ret = 0;
7635
7636         switch (l2_tunnel_type) {
7637         case RTE_L2_TUNNEL_TYPE_E_TAG:
7638                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7639                 break;
7640         default:
7641                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7642                 ret = -EINVAL;
7643                 break;
7644         }
7645
7646         return ret;
7647 }
7648
7649 /* Enable/disable l2 tunnel offload functions */
7650 static int
7651 ixgbe_dev_l2_tunnel_offload_set
7652         (struct rte_eth_dev *dev,
7653          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7654          uint32_t mask,
7655          uint8_t en)
7656 {
7657         int ret = 0;
7658
7659         if (l2_tunnel == NULL)
7660                 return -EINVAL;
7661
7662         ret = -EINVAL;
7663         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7664                 if (en)
7665                         ret = ixgbe_dev_l2_tunnel_enable(
7666                                 dev,
7667                                 l2_tunnel->l2_tunnel_type);
7668                 else
7669                         ret = ixgbe_dev_l2_tunnel_disable(
7670                                 dev,
7671                                 l2_tunnel->l2_tunnel_type);
7672         }
7673
7674         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7675                 if (en)
7676                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7677                                 dev,
7678                                 l2_tunnel);
7679                 else
7680                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7681                                 dev,
7682                                 l2_tunnel);
7683         }
7684
7685         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7686                 if (en)
7687                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7688                                 dev,
7689                                 l2_tunnel->l2_tunnel_type);
7690                 else
7691                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7692                                 dev,
7693                                 l2_tunnel->l2_tunnel_type);
7694         }
7695
7696         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7697                 if (en)
7698                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7699                                 dev,
7700                                 l2_tunnel->l2_tunnel_type);
7701                 else
7702                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7703                                 dev,
7704                                 l2_tunnel->l2_tunnel_type);
7705         }
7706
7707         return ret;
7708 }
7709
7710 static int
7711 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7712                         uint16_t port)
7713 {
7714         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7715         IXGBE_WRITE_FLUSH(hw);
7716
7717         return 0;
7718 }
7719
7720 /* There's only one register for VxLAN UDP port.
7721  * So, we cannot add several ports. Will update it.
7722  */
7723 static int
7724 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7725                      uint16_t port)
7726 {
7727         if (port == 0) {
7728                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7729                 return -EINVAL;
7730         }
7731
7732         return ixgbe_update_vxlan_port(hw, port);
7733 }
7734
7735 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7736  * UDP port, it must have a value.
7737  * So, will reset it to the original value 0.
7738  */
7739 static int
7740 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7741                      uint16_t port)
7742 {
7743         uint16_t cur_port;
7744
7745         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7746
7747         if (cur_port != port) {
7748                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7749                 return -EINVAL;
7750         }
7751
7752         return ixgbe_update_vxlan_port(hw, 0);
7753 }
7754
7755 /* Add UDP tunneling port */
7756 static int
7757 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7758                               struct rte_eth_udp_tunnel *udp_tunnel)
7759 {
7760         int ret = 0;
7761         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7762
7763         if (hw->mac.type != ixgbe_mac_X550 &&
7764             hw->mac.type != ixgbe_mac_X550EM_x &&
7765             hw->mac.type != ixgbe_mac_X550EM_a) {
7766                 return -ENOTSUP;
7767         }
7768
7769         if (udp_tunnel == NULL)
7770                 return -EINVAL;
7771
7772         switch (udp_tunnel->prot_type) {
7773         case RTE_TUNNEL_TYPE_VXLAN:
7774                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7775                 break;
7776
7777         case RTE_TUNNEL_TYPE_GENEVE:
7778         case RTE_TUNNEL_TYPE_TEREDO:
7779                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7780                 ret = -EINVAL;
7781                 break;
7782
7783         default:
7784                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7785                 ret = -EINVAL;
7786                 break;
7787         }
7788
7789         return ret;
7790 }
7791
7792 /* Remove UDP tunneling port */
7793 static int
7794 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7795                               struct rte_eth_udp_tunnel *udp_tunnel)
7796 {
7797         int ret = 0;
7798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7799
7800         if (hw->mac.type != ixgbe_mac_X550 &&
7801             hw->mac.type != ixgbe_mac_X550EM_x &&
7802             hw->mac.type != ixgbe_mac_X550EM_a) {
7803                 return -ENOTSUP;
7804         }
7805
7806         if (udp_tunnel == NULL)
7807                 return -EINVAL;
7808
7809         switch (udp_tunnel->prot_type) {
7810         case RTE_TUNNEL_TYPE_VXLAN:
7811                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7812                 break;
7813         case RTE_TUNNEL_TYPE_GENEVE:
7814         case RTE_TUNNEL_TYPE_TEREDO:
7815                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7816                 ret = -EINVAL;
7817                 break;
7818         default:
7819                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7820                 ret = -EINVAL;
7821                 break;
7822         }
7823
7824         return ret;
7825 }
7826
7827 static void
7828 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7829 {
7830         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7831
7832         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7833 }
7834
7835 static void
7836 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7837 {
7838         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7839
7840         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7841 }
7842
7843 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7844 {
7845         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7846         u32 in_msg = 0;
7847
7848         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7849                 return;
7850
7851         /* PF reset VF event */
7852         if (in_msg == IXGBE_PF_CONTROL_MSG)
7853                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7854 }
7855
7856 static int
7857 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7858 {
7859         uint32_t eicr;
7860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7861         struct ixgbe_interrupt *intr =
7862                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7863         ixgbevf_intr_disable(hw);
7864
7865         /* read-on-clear nic registers here */
7866         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7867         intr->flags = 0;
7868
7869         /* only one misc vector supported - mailbox */
7870         eicr &= IXGBE_VTEICR_MASK;
7871         if (eicr == IXGBE_MISC_VEC_ID)
7872                 intr->flags |= IXGBE_FLAG_MAILBOX;
7873
7874         return 0;
7875 }
7876
7877 static int
7878 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7879 {
7880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7881         struct ixgbe_interrupt *intr =
7882                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7883
7884         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7885                 ixgbevf_mbx_process(dev);
7886                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7887         }
7888
7889         ixgbevf_intr_enable(hw);
7890
7891         return 0;
7892 }
7893
7894 static void
7895 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7896                               void *param)
7897 {
7898         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7899
7900         ixgbevf_dev_interrupt_get_status(dev);
7901         ixgbevf_dev_interrupt_action(dev);
7902 }
7903
7904 /**
7905  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7906  *  @hw: pointer to hardware structure
7907  *
7908  *  Stops the transmit data path and waits for the HW to internally empty
7909  *  the Tx security block
7910  **/
7911 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7912 {
7913 #define IXGBE_MAX_SECTX_POLL 40
7914
7915         int i;
7916         int sectxreg;
7917
7918         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7919         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7920         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7921         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7922                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7923                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7924                         break;
7925                 /* Use interrupt-safe sleep just in case */
7926                 usec_delay(1000);
7927         }
7928
7929         /* For informational purposes only */
7930         if (i >= IXGBE_MAX_SECTX_POLL)
7931                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7932                          "path fully disabled.  Continuing with init.\n");
7933
7934         return IXGBE_SUCCESS;
7935 }
7936
7937 /**
7938  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7939  *  @hw: pointer to hardware structure
7940  *
7941  *  Enables the transmit data path.
7942  **/
7943 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7944 {
7945         uint32_t sectxreg;
7946
7947         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7948         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7949         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7950         IXGBE_WRITE_FLUSH(hw);
7951
7952         return IXGBE_SUCCESS;
7953 }
7954
7955 int
7956 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
7957 {
7958         struct ixgbe_hw *hw;
7959         struct rte_eth_dev *dev;
7960         uint32_t ctrl;
7961
7962         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
7963
7964         dev = &rte_eth_devices[port];
7965         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7966
7967         /* Stop the data paths */
7968         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
7969                 return -ENOTSUP;
7970         /*
7971          * Workaround:
7972          * As no ixgbe_disable_sec_rx_path equivalent is
7973          * implemented for tx in the base code, and we are
7974          * not allowed to modify the base code in DPDK, so
7975          * just call the hand-written one directly for now.
7976          * The hardware support has been checked by
7977          * ixgbe_disable_sec_rx_path().
7978          */
7979         ixgbe_disable_sec_tx_path_generic(hw);
7980
7981         /* Enable Ethernet CRC (required by MACsec offload) */
7982         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
7983         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
7984         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
7985
7986         /* Enable the TX and RX crypto engines */
7987         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7988         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
7989         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
7990
7991         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
7992         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
7993         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
7994
7995         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
7996         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
7997         ctrl |= 0x3;
7998         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
7999
8000         /* Enable SA lookup */
8001         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8002         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8003         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8004                      IXGBE_LSECTXCTRL_AUTH;
8005         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8006         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8007         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8008         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8009
8010         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8011         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8012         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8013         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8014         if (rp)
8015                 ctrl |= IXGBE_LSECRXCTRL_RP;
8016         else
8017                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8018         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8019
8020         /* Start the data paths */
8021         ixgbe_enable_sec_rx_path(hw);
8022         /*
8023          * Workaround:
8024          * As no ixgbe_enable_sec_rx_path equivalent is
8025          * implemented for tx in the base code, and we are
8026          * not allowed to modify the base code in DPDK, so
8027          * just call the hand-written one directly for now.
8028          */
8029         ixgbe_enable_sec_tx_path_generic(hw);
8030
8031         return 0;
8032 }
8033
8034 int
8035 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8036 {
8037         struct ixgbe_hw *hw;
8038         struct rte_eth_dev *dev;
8039         uint32_t ctrl;
8040
8041         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8042
8043         dev = &rte_eth_devices[port];
8044         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8045
8046         /* Stop the data paths */
8047         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8048                 return -ENOTSUP;
8049         /*
8050          * Workaround:
8051          * As no ixgbe_disable_sec_rx_path equivalent is
8052          * implemented for tx in the base code, and we are
8053          * not allowed to modify the base code in DPDK, so
8054          * just call the hand-written one directly for now.
8055          * The hardware support has been checked by
8056          * ixgbe_disable_sec_rx_path().
8057          */
8058         ixgbe_disable_sec_tx_path_generic(hw);
8059
8060         /* Disable the TX and RX crypto engines */
8061         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8062         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8063         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8064
8065         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8066         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8067         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8068
8069         /* Disable SA lookup */
8070         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8071         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8072         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8073         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8074
8075         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8076         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8077         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8078         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8079
8080         /* Start the data paths */
8081         ixgbe_enable_sec_rx_path(hw);
8082         /*
8083          * Workaround:
8084          * As no ixgbe_enable_sec_rx_path equivalent is
8085          * implemented for tx in the base code, and we are
8086          * not allowed to modify the base code in DPDK, so
8087          * just call the hand-written one directly for now.
8088          */
8089         ixgbe_enable_sec_tx_path_generic(hw);
8090
8091         return 0;
8092 }
8093
8094 int
8095 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8096 {
8097         struct ixgbe_hw *hw;
8098         struct rte_eth_dev *dev;
8099         uint32_t ctrl;
8100
8101         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8102
8103         dev = &rte_eth_devices[port];
8104         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8105
8106         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8107         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8108
8109         ctrl = mac[4] | (mac[5] << 8);
8110         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8111
8112         return 0;
8113 }
8114
8115 int
8116 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8117 {
8118         struct ixgbe_hw *hw;
8119         struct rte_eth_dev *dev;
8120         uint32_t ctrl;
8121
8122         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8123
8124         dev = &rte_eth_devices[port];
8125         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8126
8127         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8128         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8129
8130         pi = rte_cpu_to_be_16(pi);
8131         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8132         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8133
8134         return 0;
8135 }
8136
8137 int
8138 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8139                                  uint32_t pn, uint8_t *key)
8140 {
8141         struct ixgbe_hw *hw;
8142         struct rte_eth_dev *dev;
8143         uint32_t ctrl, i;
8144
8145         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8146
8147         dev = &rte_eth_devices[port];
8148         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8149
8150         if (idx != 0 && idx != 1)
8151                 return -EINVAL;
8152
8153         if (an >= 4)
8154                 return -EINVAL;
8155
8156         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8157
8158         /* Set the PN and key */
8159         pn = rte_cpu_to_be_32(pn);
8160         if (idx == 0) {
8161                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8162
8163                 for (i = 0; i < 4; i++) {
8164                         ctrl = (key[i * 4 + 0] <<  0) |
8165                                (key[i * 4 + 1] <<  8) |
8166                                (key[i * 4 + 2] << 16) |
8167                                (key[i * 4 + 3] << 24);
8168                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8169                 }
8170         } else {
8171                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8172
8173                 for (i = 0; i < 4; i++) {
8174                         ctrl = (key[i * 4 + 0] <<  0) |
8175                                (key[i * 4 + 1] <<  8) |
8176                                (key[i * 4 + 2] << 16) |
8177                                (key[i * 4 + 3] << 24);
8178                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8179                 }
8180         }
8181
8182         /* Set AN and select the SA */
8183         ctrl = (an << idx * 2) | (idx << 4);
8184         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8185
8186         return 0;
8187 }
8188
8189 int
8190 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8191                                  uint32_t pn, uint8_t *key)
8192 {
8193         struct ixgbe_hw *hw;
8194         struct rte_eth_dev *dev;
8195         uint32_t ctrl, i;
8196
8197         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8198
8199         dev = &rte_eth_devices[port];
8200         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8201
8202         if (idx != 0 && idx != 1)
8203                 return -EINVAL;
8204
8205         if (an >= 4)
8206                 return -EINVAL;
8207
8208         /* Set the PN */
8209         pn = rte_cpu_to_be_32(pn);
8210         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8211
8212         /* Set the key */
8213         for (i = 0; i < 4; i++) {
8214                 ctrl = (key[i * 4 + 0] <<  0) |
8215                        (key[i * 4 + 1] <<  8) |
8216                        (key[i * 4 + 2] << 16) |
8217                        (key[i * 4 + 3] << 24);
8218                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8219         }
8220
8221         /* Set the AN and validate the SA */
8222         ctrl = an | (1 << 2);
8223         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8224
8225         return 0;
8226 }
8227
8228 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8229 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8230 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8231 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8232 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8233 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");