1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_kvargs.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_hash_crc.h>
36 #ifdef RTE_LIBRTE_SECURITY
37 #include <rte_security_driver.h>
40 #include "ixgbe_logs.h"
41 #include "base/ixgbe_api.h"
42 #include "base/ixgbe_vf.h"
43 #include "base/ixgbe_common.h"
44 #include "ixgbe_ethdev.h"
45 #include "ixgbe_bypass.h"
46 #include "ixgbe_rxtx.h"
47 #include "base/ixgbe_type.h"
48 #include "base/ixgbe_phy.h"
49 #include "ixgbe_regs.h"
52 * High threshold controlling when to start sending XOFF frames. Must be at
53 * least 8 bytes less than receive packet buffer size. This value is in units
56 #define IXGBE_FC_HI 0x80
59 * Low threshold controlling when to start sending XON frames. This value is
60 * in units of 1024 bytes.
62 #define IXGBE_FC_LO 0x40
64 /* Timer value included in XOFF frames. */
65 #define IXGBE_FC_PAUSE 0x680
67 /*Default value of Max Rx Queue*/
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
74 #define IXGBE_MMW_SIZE_DEFAULT 0x4
75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
79 * Default values for RX/TX configuration
81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
82 #define IXGBE_DEFAULT_RX_PTHRESH 8
83 #define IXGBE_DEFAULT_RX_HTHRESH 8
84 #define IXGBE_DEFAULT_RX_WTHRESH 0
86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
87 #define IXGBE_DEFAULT_TX_PTHRESH 32
88 #define IXGBE_DEFAULT_TX_HTHRESH 0
89 #define IXGBE_DEFAULT_TX_WTHRESH 0
90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
95 #define IXGBE_8_BIT_WIDTH CHAR_BIT
96 #define IXGBE_8_BIT_MASK UINT8_MAX
98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
102 /* Additional timesync values. */
103 #define NSEC_PER_SEC 1000000000L
104 #define IXGBE_INCVAL_10GB 0x66666666
105 #define IXGBE_INCVAL_1GB 0x40000000
106 #define IXGBE_INCVAL_100 0x50000000
107 #define IXGBE_INCVAL_SHIFT_10GB 28
108 #define IXGBE_INCVAL_SHIFT_1GB 24
109 #define IXGBE_INCVAL_SHIFT_100 21
110 #define IXGBE_INCVAL_SHIFT_82599 7
111 #define IXGBE_INCPER_SHIFT_82599 24
113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
117 #define IXGBE_ETAG_ETYPE 0x00005084
118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
120 #define IXGBE_RAH_ADTYPE 0x40000000
121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
125 #define IXGBE_QDE_STRIP_TAG 0x00000004
126 #define IXGBE_VTEICR_MASK 0x07
128 #define IXGBE_EXVET_VET_EXT_SHIFT 16
129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk"
133 static const char * const ixgbevf_valid_arguments[] = {
134 IXGBEVF_DEVARG_PFLINK_FULLCHK,
138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
157 int wait_to_complete);
158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
166 uint64_t *values, unsigned int n);
167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names, unsigned limit);
174 static int ixgbe_dev_xstats_get_names_by_id(
175 struct rte_eth_dev *dev,
176 struct rte_eth_xstat_name *xstats_names,
179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_fc_conf *fc_conf);
216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
217 struct rte_eth_pfc_conf *pfc_conf);
218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
222 struct rte_eth_rss_reta_entry64 *reta_conf,
224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
230 static void ixgbe_dev_interrupt_handler(void *param);
231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
234 uint32_t timeout_ms);
236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
237 struct rte_ether_addr *mac_addr,
238 uint32_t index, uint32_t pool);
239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
241 struct rte_ether_addr *mac_addr);
242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
243 static bool is_device_supported(struct rte_eth_dev *dev,
244 struct rte_pci_driver *drv);
246 /* For Virtual Function support */
247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
250 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
252 int wait_to_complete);
253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
254 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
255 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
262 uint16_t vlan_id, int on);
263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
264 uint16_t queue, int on);
265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
273 uint8_t queue, uint8_t msix_vector);
274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
280 /* For Eth VMDQ APIs support */
281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
282 rte_ether_addr * mac_addr, uint8_t on);
283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
285 struct rte_eth_mirror_conf *mirror_conf,
286 uint8_t rule_id, uint8_t on);
287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
294 uint8_t queue, uint8_t msix_vector);
295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
298 struct rte_ether_addr *mac_addr,
299 uint32_t index, uint32_t pool);
300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
302 struct rte_ether_addr *mac_addr);
303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
304 struct rte_eth_syn_filter *filter);
305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
306 enum rte_filter_op filter_op,
308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
309 struct ixgbe_5tuple_filter *filter);
310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
311 struct ixgbe_5tuple_filter *filter);
312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
313 enum rte_filter_op filter_op,
315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
316 struct rte_eth_ntuple_filter *filter);
317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
318 enum rte_filter_op filter_op,
320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
321 struct rte_eth_ethertype_filter *filter);
322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
323 enum rte_filter_type filter_type,
324 enum rte_filter_op filter_op,
326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
329 struct rte_ether_addr *mc_addr_set,
330 uint32_t nb_mc_addr);
331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
332 struct rte_eth_dcb_info *dcb_info);
334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
336 struct rte_dev_reg_info *regs);
337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
339 struct rte_dev_eeprom_info *eeprom);
340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
341 struct rte_dev_eeprom_info *eeprom);
343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
344 struct rte_eth_dev_module_info *modinfo);
345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
346 struct rte_dev_eeprom_info *info);
348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
350 struct rte_dev_reg_info *regs);
352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
355 struct timespec *timestamp,
357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
358 struct timespec *timestamp);
359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
361 struct timespec *timestamp);
362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
363 const struct timespec *timestamp);
364 static void ixgbevf_dev_interrupt_handler(void *param);
366 static int ixgbe_dev_l2_tunnel_eth_type_conf
367 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
368 static int ixgbe_dev_l2_tunnel_offload_set
369 (struct rte_eth_dev *dev,
370 struct rte_eth_l2_tunnel_conf *l2_tunnel,
373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
374 enum rte_filter_op filter_op,
377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
378 struct rte_eth_udp_tunnel *udp_tunnel);
379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
380 struct rte_eth_udp_tunnel *udp_tunnel);
381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
386 * Define VF Stats MACRO for Non "cleared on read" register
388 #define UPDATE_VF_STAT(reg, last, cur) \
390 uint32_t latest = IXGBE_READ_REG(hw, reg); \
391 cur += (latest - last) & UINT_MAX; \
395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
397 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
398 u64 new_msb = IXGBE_READ_REG(hw, msb); \
399 u64 latest = ((new_msb << 32) | new_lsb); \
400 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
404 #define IXGBE_SET_HWSTRIP(h, q) do {\
405 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
406 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
407 (h)->bitmap[idx] |= 1 << bit;\
410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
411 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
412 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
413 (h)->bitmap[idx] &= ~(1 << bit);\
416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
417 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
418 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
419 (r) = (h)->bitmap[idx] >> bit & 1;\
422 int ixgbe_logtype_init;
423 int ixgbe_logtype_driver;
425 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
426 int ixgbe_logtype_rx;
428 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
429 int ixgbe_logtype_tx;
431 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
432 int ixgbe_logtype_tx_free;
436 * The set of PCI devices this driver supports
438 static const struct rte_pci_id pci_id_ixgbe_map[] = {
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
487 #ifdef RTE_LIBRTE_IXGBE_BYPASS
488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
490 { .vendor_id = 0, /* sentinel */ },
494 * The set of PCI devices this driver supports (for 82599 VF)
496 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
504 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
505 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
506 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
507 { .vendor_id = 0, /* sentinel */ },
510 static const struct rte_eth_desc_lim rx_desc_lim = {
511 .nb_max = IXGBE_MAX_RING_DESC,
512 .nb_min = IXGBE_MIN_RING_DESC,
513 .nb_align = IXGBE_RXD_ALIGN,
516 static const struct rte_eth_desc_lim tx_desc_lim = {
517 .nb_max = IXGBE_MAX_RING_DESC,
518 .nb_min = IXGBE_MIN_RING_DESC,
519 .nb_align = IXGBE_TXD_ALIGN,
520 .nb_seg_max = IXGBE_TX_MAX_SEG,
521 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
524 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
525 .dev_configure = ixgbe_dev_configure,
526 .dev_start = ixgbe_dev_start,
527 .dev_stop = ixgbe_dev_stop,
528 .dev_set_link_up = ixgbe_dev_set_link_up,
529 .dev_set_link_down = ixgbe_dev_set_link_down,
530 .dev_close = ixgbe_dev_close,
531 .dev_reset = ixgbe_dev_reset,
532 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
533 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
534 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
535 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
536 .link_update = ixgbe_dev_link_update,
537 .stats_get = ixgbe_dev_stats_get,
538 .xstats_get = ixgbe_dev_xstats_get,
539 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
540 .stats_reset = ixgbe_dev_stats_reset,
541 .xstats_reset = ixgbe_dev_xstats_reset,
542 .xstats_get_names = ixgbe_dev_xstats_get_names,
543 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
544 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
545 .fw_version_get = ixgbe_fw_version_get,
546 .dev_infos_get = ixgbe_dev_info_get,
547 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
548 .mtu_set = ixgbe_dev_mtu_set,
549 .vlan_filter_set = ixgbe_vlan_filter_set,
550 .vlan_tpid_set = ixgbe_vlan_tpid_set,
551 .vlan_offload_set = ixgbe_vlan_offload_set,
552 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
553 .rx_queue_start = ixgbe_dev_rx_queue_start,
554 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
555 .tx_queue_start = ixgbe_dev_tx_queue_start,
556 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
557 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
558 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
559 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
560 .rx_queue_release = ixgbe_dev_rx_queue_release,
561 .rx_queue_count = ixgbe_dev_rx_queue_count,
562 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
563 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
564 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
565 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
566 .tx_queue_release = ixgbe_dev_tx_queue_release,
567 .dev_led_on = ixgbe_dev_led_on,
568 .dev_led_off = ixgbe_dev_led_off,
569 .flow_ctrl_get = ixgbe_flow_ctrl_get,
570 .flow_ctrl_set = ixgbe_flow_ctrl_set,
571 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
572 .mac_addr_add = ixgbe_add_rar,
573 .mac_addr_remove = ixgbe_remove_rar,
574 .mac_addr_set = ixgbe_set_default_mac_addr,
575 .uc_hash_table_set = ixgbe_uc_hash_table_set,
576 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
577 .mirror_rule_set = ixgbe_mirror_rule_set,
578 .mirror_rule_reset = ixgbe_mirror_rule_reset,
579 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
580 .reta_update = ixgbe_dev_rss_reta_update,
581 .reta_query = ixgbe_dev_rss_reta_query,
582 .rss_hash_update = ixgbe_dev_rss_hash_update,
583 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
584 .filter_ctrl = ixgbe_dev_filter_ctrl,
585 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
586 .rxq_info_get = ixgbe_rxq_info_get,
587 .txq_info_get = ixgbe_txq_info_get,
588 .timesync_enable = ixgbe_timesync_enable,
589 .timesync_disable = ixgbe_timesync_disable,
590 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
591 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
592 .get_reg = ixgbe_get_regs,
593 .get_eeprom_length = ixgbe_get_eeprom_length,
594 .get_eeprom = ixgbe_get_eeprom,
595 .set_eeprom = ixgbe_set_eeprom,
596 .get_module_info = ixgbe_get_module_info,
597 .get_module_eeprom = ixgbe_get_module_eeprom,
598 .get_dcb_info = ixgbe_dev_get_dcb_info,
599 .timesync_adjust_time = ixgbe_timesync_adjust_time,
600 .timesync_read_time = ixgbe_timesync_read_time,
601 .timesync_write_time = ixgbe_timesync_write_time,
602 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
603 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
604 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
605 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
606 .tm_ops_get = ixgbe_tm_ops_get,
607 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
611 * dev_ops for virtual function, bare necessities for basic vf
612 * operation have been implemented
614 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
615 .dev_configure = ixgbevf_dev_configure,
616 .dev_start = ixgbevf_dev_start,
617 .dev_stop = ixgbevf_dev_stop,
618 .link_update = ixgbevf_dev_link_update,
619 .stats_get = ixgbevf_dev_stats_get,
620 .xstats_get = ixgbevf_dev_xstats_get,
621 .stats_reset = ixgbevf_dev_stats_reset,
622 .xstats_reset = ixgbevf_dev_stats_reset,
623 .xstats_get_names = ixgbevf_dev_xstats_get_names,
624 .dev_close = ixgbevf_dev_close,
625 .dev_reset = ixgbevf_dev_reset,
626 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
627 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
628 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
629 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
630 .dev_infos_get = ixgbevf_dev_info_get,
631 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
632 .mtu_set = ixgbevf_dev_set_mtu,
633 .vlan_filter_set = ixgbevf_vlan_filter_set,
634 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
635 .vlan_offload_set = ixgbevf_vlan_offload_set,
636 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
637 .rx_queue_release = ixgbe_dev_rx_queue_release,
638 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
639 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
640 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
641 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
642 .tx_queue_release = ixgbe_dev_tx_queue_release,
643 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
644 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
645 .mac_addr_add = ixgbevf_add_mac_addr,
646 .mac_addr_remove = ixgbevf_remove_mac_addr,
647 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
648 .rxq_info_get = ixgbe_rxq_info_get,
649 .txq_info_get = ixgbe_txq_info_get,
650 .mac_addr_set = ixgbevf_set_default_mac_addr,
651 .get_reg = ixgbevf_get_regs,
652 .reta_update = ixgbe_dev_rss_reta_update,
653 .reta_query = ixgbe_dev_rss_reta_query,
654 .rss_hash_update = ixgbe_dev_rss_hash_update,
655 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
656 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
659 /* store statistics names and its offset in stats structure */
660 struct rte_ixgbe_xstats_name_off {
661 char name[RTE_ETH_XSTATS_NAME_SIZE];
665 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
666 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
667 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
668 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
669 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
670 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
671 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
672 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
673 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
674 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
675 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
676 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
677 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
678 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
679 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
680 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
682 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
684 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
685 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
686 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
687 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
688 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
689 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
690 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
691 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
692 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
693 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
694 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
695 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
696 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
697 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
698 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
699 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
700 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
702 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
704 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
705 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
706 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
707 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
709 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
711 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
713 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
715 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
717 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
719 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
722 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
723 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
724 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
726 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
727 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
728 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
729 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
730 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
732 {"rx_fcoe_no_direct_data_placement_ext_buff",
733 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
735 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
737 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
739 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
741 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
743 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
746 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
747 sizeof(rte_ixgbe_stats_strings[0]))
749 /* MACsec statistics */
750 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
751 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
753 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
754 out_pkts_encrypted)},
755 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
756 out_pkts_protected)},
757 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
758 out_octets_encrypted)},
759 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
760 out_octets_protected)},
761 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
763 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
765 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
768 in_pkts_unknownsci)},
769 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
770 in_octets_decrypted)},
771 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
772 in_octets_validated)},
773 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
775 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
777 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
779 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
781 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
783 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
785 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
787 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
788 in_pkts_notusingsa)},
791 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
792 sizeof(rte_ixgbe_macsec_strings[0]))
794 /* Per-queue statistics */
795 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
796 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
797 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
798 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
799 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
802 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
803 sizeof(rte_ixgbe_rxq_strings[0]))
804 #define IXGBE_NB_RXQ_PRIO_VALUES 8
806 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
807 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
808 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
809 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
813 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
814 sizeof(rte_ixgbe_txq_strings[0]))
815 #define IXGBE_NB_TXQ_PRIO_VALUES 8
817 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
818 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
821 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
822 sizeof(rte_ixgbevf_stats_strings[0]))
825 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
828 ixgbe_is_sfp(struct ixgbe_hw *hw)
830 switch (hw->phy.type) {
831 case ixgbe_phy_sfp_avago:
832 case ixgbe_phy_sfp_ftl:
833 case ixgbe_phy_sfp_intel:
834 case ixgbe_phy_sfp_unknown:
835 case ixgbe_phy_sfp_passive_tyco:
836 case ixgbe_phy_sfp_passive_unknown:
843 static inline int32_t
844 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
849 status = ixgbe_reset_hw(hw);
851 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
852 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
853 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
854 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
855 IXGBE_WRITE_FLUSH(hw);
857 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
858 status = IXGBE_SUCCESS;
863 ixgbe_enable_intr(struct rte_eth_dev *dev)
865 struct ixgbe_interrupt *intr =
866 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
867 struct ixgbe_hw *hw =
868 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
870 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
871 IXGBE_WRITE_FLUSH(hw);
875 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
878 ixgbe_disable_intr(struct ixgbe_hw *hw)
880 PMD_INIT_FUNC_TRACE();
882 if (hw->mac.type == ixgbe_mac_82598EB) {
883 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
885 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
886 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
887 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
889 IXGBE_WRITE_FLUSH(hw);
893 * This function resets queue statistics mapping registers.
894 * From Niantic datasheet, Initialization of Statistics section:
895 * "...if software requires the queue counters, the RQSMR and TQSM registers
896 * must be re-programmed following a device reset.
899 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
903 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
904 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
905 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
911 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
916 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
917 #define NB_QMAP_FIELDS_PER_QSM_REG 4
918 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
920 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
921 struct ixgbe_stat_mapping_registers *stat_mappings =
922 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
923 uint32_t qsmr_mask = 0;
924 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
928 if ((hw->mac.type != ixgbe_mac_82599EB) &&
929 (hw->mac.type != ixgbe_mac_X540) &&
930 (hw->mac.type != ixgbe_mac_X550) &&
931 (hw->mac.type != ixgbe_mac_X550EM_x) &&
932 (hw->mac.type != ixgbe_mac_X550EM_a))
935 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
936 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
939 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
940 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
941 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
944 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
946 /* Now clear any previous stat_idx set */
947 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
949 stat_mappings->tqsm[n] &= ~clearing_mask;
951 stat_mappings->rqsmr[n] &= ~clearing_mask;
953 q_map = (uint32_t)stat_idx;
954 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
955 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
957 stat_mappings->tqsm[n] |= qsmr_mask;
959 stat_mappings->rqsmr[n] |= qsmr_mask;
961 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
962 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
964 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
965 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
967 /* Now write the mapping in the appropriate register */
969 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
970 stat_mappings->rqsmr[n], n);
971 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
973 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
974 stat_mappings->tqsm[n], n);
975 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
981 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
983 struct ixgbe_stat_mapping_registers *stat_mappings =
984 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
985 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
988 /* write whatever was in stat mapping table to the NIC */
989 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
991 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
994 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
999 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1002 struct ixgbe_dcb_tc_config *tc;
1003 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1005 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1006 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1007 for (i = 0; i < dcb_max_tc; i++) {
1008 tc = &dcb_config->tc_config[i];
1009 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1010 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1011 (uint8_t)(100/dcb_max_tc + (i & 1));
1012 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1013 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1014 (uint8_t)(100/dcb_max_tc + (i & 1));
1015 tc->pfc = ixgbe_dcb_pfc_disabled;
1018 /* Initialize default user to priority mapping, UPx->TC0 */
1019 tc = &dcb_config->tc_config[0];
1020 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1021 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1022 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1023 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1024 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1026 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1027 dcb_config->pfc_mode_enable = false;
1028 dcb_config->vt_mode = true;
1029 dcb_config->round_robin_enable = false;
1030 /* support all DCB capabilities in 82599 */
1031 dcb_config->support.capabilities = 0xFF;
1033 /*we only support 4 Tcs for X540, X550 */
1034 if (hw->mac.type == ixgbe_mac_X540 ||
1035 hw->mac.type == ixgbe_mac_X550 ||
1036 hw->mac.type == ixgbe_mac_X550EM_x ||
1037 hw->mac.type == ixgbe_mac_X550EM_a) {
1038 dcb_config->num_tcs.pg_tcs = 4;
1039 dcb_config->num_tcs.pfc_tcs = 4;
1044 * Ensure that all locks are released before first NVM or PHY access
1047 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1052 * Phy lock should not fail in this early stage. If this is the case,
1053 * it is due to an improper exit of the application.
1054 * So force the release of the faulty lock. Release of common lock
1055 * is done automatically by swfw_sync function.
1057 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1058 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1059 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1061 ixgbe_release_swfw_semaphore(hw, mask);
1064 * These ones are more tricky since they are common to all ports; but
1065 * swfw_sync retries last long enough (1s) to be almost sure that if
1066 * lock can not be taken it is due to an improper lock of the
1069 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1070 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1071 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1073 ixgbe_release_swfw_semaphore(hw, mask);
1077 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1078 * It returns 0 on success.
1081 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1083 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1084 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1085 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1086 struct ixgbe_hw *hw =
1087 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1088 struct ixgbe_vfta *shadow_vfta =
1089 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1090 struct ixgbe_hwstrip *hwstrip =
1091 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1092 struct ixgbe_dcb_config *dcb_config =
1093 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1094 struct ixgbe_filter_info *filter_info =
1095 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1096 struct ixgbe_bw_conf *bw_conf =
1097 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1102 PMD_INIT_FUNC_TRACE();
1104 ixgbe_dev_macsec_setting_reset(eth_dev);
1106 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1107 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1108 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1109 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1112 * For secondary processes, we don't initialise any further as primary
1113 * has already done this work. Only check we don't need a different
1114 * RX and TX function.
1116 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1117 struct ixgbe_tx_queue *txq;
1118 /* TX queue function in primary, set by last queue initialized
1119 * Tx queue may not initialized by primary process
1121 if (eth_dev->data->tx_queues) {
1122 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1123 ixgbe_set_tx_function(eth_dev, txq);
1125 /* Use default TX function if we get here */
1126 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1127 "Using default TX function.");
1130 ixgbe_set_rx_function(eth_dev);
1135 rte_atomic32_clear(&ad->link_thread_running);
1136 rte_eth_copy_pci_info(eth_dev, pci_dev);
1138 /* Vendor and Device ID need to be set before init of shared code */
1139 hw->device_id = pci_dev->id.device_id;
1140 hw->vendor_id = pci_dev->id.vendor_id;
1141 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1142 hw->allow_unsupported_sfp = 1;
1144 /* Initialize the shared code (base driver) */
1145 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1146 diag = ixgbe_bypass_init_shared_code(hw);
1148 diag = ixgbe_init_shared_code(hw);
1149 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1151 if (diag != IXGBE_SUCCESS) {
1152 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1156 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1157 PMD_INIT_LOG(ERR, "\nERROR: "
1158 "Firmware recovery mode detected. Limiting functionality.\n"
1159 "Refer to the Intel(R) Ethernet Adapters and Devices "
1160 "User Guide for details on firmware recovery mode.");
1164 /* pick up the PCI bus settings for reporting later */
1165 ixgbe_get_bus_info(hw);
1167 /* Unlock any pending hardware semaphore */
1168 ixgbe_swfw_lock_reset(hw);
1170 #ifdef RTE_LIBRTE_SECURITY
1171 /* Initialize security_ctx only for primary process*/
1172 if (ixgbe_ipsec_ctx_create(eth_dev))
1176 /* Initialize DCB configuration*/
1177 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1178 ixgbe_dcb_init(hw, dcb_config);
1179 /* Get Hardware Flow Control setting */
1180 hw->fc.requested_mode = ixgbe_fc_none;
1181 hw->fc.current_mode = ixgbe_fc_none;
1182 hw->fc.pause_time = IXGBE_FC_PAUSE;
1183 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1184 hw->fc.low_water[i] = IXGBE_FC_LO;
1185 hw->fc.high_water[i] = IXGBE_FC_HI;
1187 hw->fc.send_xon = 1;
1189 /* Make sure we have a good EEPROM before we read from it */
1190 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1191 if (diag != IXGBE_SUCCESS) {
1192 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1196 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1197 diag = ixgbe_bypass_init_hw(hw);
1199 diag = ixgbe_init_hw(hw);
1200 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1203 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1204 * is called too soon after the kernel driver unbinding/binding occurs.
1205 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1206 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1207 * also called. See ixgbe_identify_phy_82599(). The reason for the
1208 * failure is not known, and only occuts when virtualisation features
1209 * are disabled in the bios. A delay of 100ms was found to be enough by
1210 * trial-and-error, and is doubled to be safe.
1212 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1214 diag = ixgbe_init_hw(hw);
1217 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1218 diag = IXGBE_SUCCESS;
1220 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1221 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1222 "LOM. Please be aware there may be issues associated "
1223 "with your hardware.");
1224 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1225 "please contact your Intel or hardware representative "
1226 "who provided you with this hardware.");
1227 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1228 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1230 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1234 /* Reset the hw statistics */
1235 ixgbe_dev_stats_reset(eth_dev);
1237 /* disable interrupt */
1238 ixgbe_disable_intr(hw);
1240 /* reset mappings for queue statistics hw counters*/
1241 ixgbe_reset_qstat_mappings(hw);
1243 /* Allocate memory for storing MAC addresses */
1244 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1245 hw->mac.num_rar_entries, 0);
1246 if (eth_dev->data->mac_addrs == NULL) {
1248 "Failed to allocate %u bytes needed to store "
1250 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1253 /* Copy the permanent MAC address */
1254 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1255 ð_dev->data->mac_addrs[0]);
1257 /* Allocate memory for storing hash filter MAC addresses */
1258 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1259 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1260 if (eth_dev->data->hash_mac_addrs == NULL) {
1262 "Failed to allocate %d bytes needed to store MAC addresses",
1263 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1267 /* Pass the information to the rte_eth_dev_close() that it should also
1268 * release the private port resources.
1270 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1272 /* initialize the vfta */
1273 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1275 /* initialize the hw strip bitmap*/
1276 memset(hwstrip, 0, sizeof(*hwstrip));
1278 /* initialize PF if max_vfs not zero */
1279 ixgbe_pf_host_init(eth_dev);
1281 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1282 /* let hardware know driver is loaded */
1283 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1284 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1285 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1286 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1287 IXGBE_WRITE_FLUSH(hw);
1289 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1290 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1291 (int) hw->mac.type, (int) hw->phy.type,
1292 (int) hw->phy.sfp_type);
1294 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1295 (int) hw->mac.type, (int) hw->phy.type);
1297 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1298 eth_dev->data->port_id, pci_dev->id.vendor_id,
1299 pci_dev->id.device_id);
1301 rte_intr_callback_register(intr_handle,
1302 ixgbe_dev_interrupt_handler, eth_dev);
1304 /* enable uio/vfio intr/eventfd mapping */
1305 rte_intr_enable(intr_handle);
1307 /* enable support intr */
1308 ixgbe_enable_intr(eth_dev);
1310 /* initialize filter info */
1311 memset(filter_info, 0,
1312 sizeof(struct ixgbe_filter_info));
1314 /* initialize 5tuple filter list */
1315 TAILQ_INIT(&filter_info->fivetuple_list);
1317 /* initialize flow director filter list & hash */
1318 ixgbe_fdir_filter_init(eth_dev);
1320 /* initialize l2 tunnel filter list & hash */
1321 ixgbe_l2_tn_filter_init(eth_dev);
1323 /* initialize flow filter lists */
1324 ixgbe_filterlist_init();
1326 /* initialize bandwidth configuration info */
1327 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1329 /* initialize Traffic Manager configuration */
1330 ixgbe_tm_conf_init(eth_dev);
1336 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1338 PMD_INIT_FUNC_TRACE();
1340 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1343 ixgbe_dev_close(eth_dev);
1348 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1350 struct ixgbe_filter_info *filter_info =
1351 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1352 struct ixgbe_5tuple_filter *p_5tuple;
1354 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1355 TAILQ_REMOVE(&filter_info->fivetuple_list,
1360 memset(filter_info->fivetuple_mask, 0,
1361 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1366 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1368 struct ixgbe_hw_fdir_info *fdir_info =
1369 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1370 struct ixgbe_fdir_filter *fdir_filter;
1372 if (fdir_info->hash_map)
1373 rte_free(fdir_info->hash_map);
1374 if (fdir_info->hash_handle)
1375 rte_hash_free(fdir_info->hash_handle);
1377 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1378 TAILQ_REMOVE(&fdir_info->fdir_list,
1381 rte_free(fdir_filter);
1387 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1389 struct ixgbe_l2_tn_info *l2_tn_info =
1390 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1391 struct ixgbe_l2_tn_filter *l2_tn_filter;
1393 if (l2_tn_info->hash_map)
1394 rte_free(l2_tn_info->hash_map);
1395 if (l2_tn_info->hash_handle)
1396 rte_hash_free(l2_tn_info->hash_handle);
1398 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1399 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1402 rte_free(l2_tn_filter);
1408 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1410 struct ixgbe_hw_fdir_info *fdir_info =
1411 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1412 char fdir_hash_name[RTE_HASH_NAMESIZE];
1413 struct rte_hash_parameters fdir_hash_params = {
1414 .name = fdir_hash_name,
1415 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1416 .key_len = sizeof(union ixgbe_atr_input),
1417 .hash_func = rte_hash_crc,
1418 .hash_func_init_val = 0,
1419 .socket_id = rte_socket_id(),
1422 TAILQ_INIT(&fdir_info->fdir_list);
1423 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1424 "fdir_%s", eth_dev->device->name);
1425 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1426 if (!fdir_info->hash_handle) {
1427 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1430 fdir_info->hash_map = rte_zmalloc("ixgbe",
1431 sizeof(struct ixgbe_fdir_filter *) *
1432 IXGBE_MAX_FDIR_FILTER_NUM,
1434 if (!fdir_info->hash_map) {
1436 "Failed to allocate memory for fdir hash map!");
1439 fdir_info->mask_added = FALSE;
1444 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1446 struct ixgbe_l2_tn_info *l2_tn_info =
1447 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1448 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1449 struct rte_hash_parameters l2_tn_hash_params = {
1450 .name = l2_tn_hash_name,
1451 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1452 .key_len = sizeof(struct ixgbe_l2_tn_key),
1453 .hash_func = rte_hash_crc,
1454 .hash_func_init_val = 0,
1455 .socket_id = rte_socket_id(),
1458 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1459 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1460 "l2_tn_%s", eth_dev->device->name);
1461 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1462 if (!l2_tn_info->hash_handle) {
1463 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1466 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1467 sizeof(struct ixgbe_l2_tn_filter *) *
1468 IXGBE_MAX_L2_TN_FILTER_NUM,
1470 if (!l2_tn_info->hash_map) {
1472 "Failed to allocate memory for L2 TN hash map!");
1475 l2_tn_info->e_tag_en = FALSE;
1476 l2_tn_info->e_tag_fwd_en = FALSE;
1477 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1482 * Negotiate mailbox API version with the PF.
1483 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1484 * Then we try to negotiate starting with the most recent one.
1485 * If all negotiation attempts fail, then we will proceed with
1486 * the default one (ixgbe_mbox_api_10).
1489 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1493 /* start with highest supported, proceed down */
1494 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1502 i != RTE_DIM(sup_ver) &&
1503 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1509 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1513 /* Set Organizationally Unique Identifier (OUI) prefix. */
1514 mac_addr->addr_bytes[0] = 0x00;
1515 mac_addr->addr_bytes[1] = 0x09;
1516 mac_addr->addr_bytes[2] = 0xC0;
1517 /* Force indication of locally assigned MAC address. */
1518 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1519 /* Generate the last 3 bytes of the MAC address with a random number. */
1520 random = rte_rand();
1521 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1525 devarg_handle_int(__rte_unused const char *key, const char *value,
1528 uint16_t *n = extra_args;
1530 if (value == NULL || extra_args == NULL)
1533 *n = (uint16_t)strtoul(value, NULL, 0);
1534 if (*n == USHRT_MAX && errno == ERANGE)
1541 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1542 struct rte_devargs *devargs)
1544 struct rte_kvargs *kvlist;
1545 uint16_t pflink_fullchk;
1547 if (devargs == NULL)
1550 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1554 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1555 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1556 devarg_handle_int, &pflink_fullchk) == 0 &&
1557 pflink_fullchk == 1)
1558 adapter->pflink_fullchk = 1;
1560 rte_kvargs_free(kvlist);
1564 * Virtual Function device init
1567 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1571 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1572 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1573 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1574 struct ixgbe_hw *hw =
1575 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1576 struct ixgbe_vfta *shadow_vfta =
1577 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1578 struct ixgbe_hwstrip *hwstrip =
1579 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1580 struct rte_ether_addr *perm_addr =
1581 (struct rte_ether_addr *)hw->mac.perm_addr;
1583 PMD_INIT_FUNC_TRACE();
1585 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1586 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1587 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1589 /* for secondary processes, we don't initialise any further as primary
1590 * has already done this work. Only check we don't need a different
1593 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1594 struct ixgbe_tx_queue *txq;
1595 /* TX queue function in primary, set by last queue initialized
1596 * Tx queue may not initialized by primary process
1598 if (eth_dev->data->tx_queues) {
1599 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1600 ixgbe_set_tx_function(eth_dev, txq);
1602 /* Use default TX function if we get here */
1603 PMD_INIT_LOG(NOTICE,
1604 "No TX queues configured yet. Using default TX function.");
1607 ixgbe_set_rx_function(eth_dev);
1612 rte_atomic32_clear(&ad->link_thread_running);
1613 ixgbevf_parse_devargs(eth_dev->data->dev_private,
1614 pci_dev->device.devargs);
1616 rte_eth_copy_pci_info(eth_dev, pci_dev);
1618 hw->device_id = pci_dev->id.device_id;
1619 hw->vendor_id = pci_dev->id.vendor_id;
1620 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1622 /* initialize the vfta */
1623 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1625 /* initialize the hw strip bitmap*/
1626 memset(hwstrip, 0, sizeof(*hwstrip));
1628 /* Initialize the shared code (base driver) */
1629 diag = ixgbe_init_shared_code(hw);
1630 if (diag != IXGBE_SUCCESS) {
1631 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1635 /* init_mailbox_params */
1636 hw->mbx.ops.init_params(hw);
1638 /* Reset the hw statistics */
1639 ixgbevf_dev_stats_reset(eth_dev);
1641 /* Disable the interrupts for VF */
1642 ixgbevf_intr_disable(eth_dev);
1644 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1645 diag = hw->mac.ops.reset_hw(hw);
1648 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1649 * the underlying PF driver has not assigned a MAC address to the VF.
1650 * In this case, assign a random MAC address.
1652 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1653 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1655 * This error code will be propagated to the app by
1656 * rte_eth_dev_reset, so use a public error code rather than
1657 * the internal-only IXGBE_ERR_RESET_FAILED
1662 /* negotiate mailbox API version to use with the PF. */
1663 ixgbevf_negotiate_api(hw);
1665 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1666 ixgbevf_get_queues(hw, &tcs, &tc);
1668 /* Allocate memory for storing MAC addresses */
1669 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1670 hw->mac.num_rar_entries, 0);
1671 if (eth_dev->data->mac_addrs == NULL) {
1673 "Failed to allocate %u bytes needed to store "
1675 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1679 /* Pass the information to the rte_eth_dev_close() that it should also
1680 * release the private port resources.
1682 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1684 /* Generate a random MAC address, if none was assigned by PF. */
1685 if (rte_is_zero_ether_addr(perm_addr)) {
1686 generate_random_mac_addr(perm_addr);
1687 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1689 rte_free(eth_dev->data->mac_addrs);
1690 eth_dev->data->mac_addrs = NULL;
1693 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1694 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1695 "%02x:%02x:%02x:%02x:%02x:%02x",
1696 perm_addr->addr_bytes[0],
1697 perm_addr->addr_bytes[1],
1698 perm_addr->addr_bytes[2],
1699 perm_addr->addr_bytes[3],
1700 perm_addr->addr_bytes[4],
1701 perm_addr->addr_bytes[5]);
1704 /* Copy the permanent MAC address */
1705 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1707 /* reset the hardware with the new settings */
1708 diag = hw->mac.ops.start_hw(hw);
1714 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1718 rte_intr_callback_register(intr_handle,
1719 ixgbevf_dev_interrupt_handler, eth_dev);
1720 rte_intr_enable(intr_handle);
1721 ixgbevf_intr_enable(eth_dev);
1723 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1724 eth_dev->data->port_id, pci_dev->id.vendor_id,
1725 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1730 /* Virtual Function device uninit */
1733 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1735 PMD_INIT_FUNC_TRACE();
1737 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1740 ixgbevf_dev_close(eth_dev);
1746 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1747 struct rte_pci_device *pci_dev)
1749 char name[RTE_ETH_NAME_MAX_LEN];
1750 struct rte_eth_dev *pf_ethdev;
1751 struct rte_eth_devargs eth_da;
1754 if (pci_dev->device.devargs) {
1755 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1760 memset(ð_da, 0, sizeof(eth_da));
1762 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1763 sizeof(struct ixgbe_adapter),
1764 eth_dev_pci_specific_init, pci_dev,
1765 eth_ixgbe_dev_init, NULL);
1767 if (retval || eth_da.nb_representor_ports < 1)
1770 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1771 if (pf_ethdev == NULL)
1774 /* probe VF representor ports */
1775 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1776 struct ixgbe_vf_info *vfinfo;
1777 struct ixgbe_vf_representor representor;
1779 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1780 pf_ethdev->data->dev_private);
1781 if (vfinfo == NULL) {
1783 "no virtual functions supported by PF");
1787 representor.vf_id = eth_da.representor_ports[i];
1788 representor.switch_domain_id = vfinfo->switch_domain_id;
1789 representor.pf_ethdev = pf_ethdev;
1791 /* representor port net_bdf_port */
1792 snprintf(name, sizeof(name), "net_%s_representor_%d",
1793 pci_dev->device.name,
1794 eth_da.representor_ports[i]);
1796 retval = rte_eth_dev_create(&pci_dev->device, name,
1797 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1798 ixgbe_vf_representor_init, &representor);
1801 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1802 "representor %s.", name);
1808 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1810 struct rte_eth_dev *ethdev;
1812 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1816 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1817 return rte_eth_dev_pci_generic_remove(pci_dev,
1818 ixgbe_vf_representor_uninit);
1820 return rte_eth_dev_pci_generic_remove(pci_dev,
1821 eth_ixgbe_dev_uninit);
1824 static struct rte_pci_driver rte_ixgbe_pmd = {
1825 .id_table = pci_id_ixgbe_map,
1826 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1827 .probe = eth_ixgbe_pci_probe,
1828 .remove = eth_ixgbe_pci_remove,
1831 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1832 struct rte_pci_device *pci_dev)
1834 return rte_eth_dev_pci_generic_probe(pci_dev,
1835 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1838 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1840 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1844 * virtual function driver struct
1846 static struct rte_pci_driver rte_ixgbevf_pmd = {
1847 .id_table = pci_id_ixgbevf_map,
1848 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1849 .probe = eth_ixgbevf_pci_probe,
1850 .remove = eth_ixgbevf_pci_remove,
1854 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1856 struct ixgbe_hw *hw =
1857 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858 struct ixgbe_vfta *shadow_vfta =
1859 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1864 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1865 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1866 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1871 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1873 /* update local VFTA copy */
1874 shadow_vfta->vfta[vid_idx] = vfta;
1880 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1883 ixgbe_vlan_hw_strip_enable(dev, queue);
1885 ixgbe_vlan_hw_strip_disable(dev, queue);
1889 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1890 enum rte_vlan_type vlan_type,
1893 struct ixgbe_hw *hw =
1894 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1899 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1900 qinq &= IXGBE_DMATXCTL_GDV;
1902 switch (vlan_type) {
1903 case ETH_VLAN_TYPE_INNER:
1905 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1906 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1907 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1908 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1909 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1910 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1911 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1914 PMD_DRV_LOG(ERR, "Inner type is not supported"
1918 case ETH_VLAN_TYPE_OUTER:
1920 /* Only the high 16-bits is valid */
1921 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1922 IXGBE_EXVET_VET_EXT_SHIFT);
1924 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1925 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1926 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1927 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1928 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1929 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1930 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1936 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1944 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1946 struct ixgbe_hw *hw =
1947 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950 PMD_INIT_FUNC_TRACE();
1952 /* Filter Table Disable */
1953 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1954 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1956 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1960 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1962 struct ixgbe_hw *hw =
1963 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964 struct ixgbe_vfta *shadow_vfta =
1965 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1969 PMD_INIT_FUNC_TRACE();
1971 /* Filter Table Enable */
1972 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1973 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1974 vlnctrl |= IXGBE_VLNCTRL_VFE;
1976 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1978 /* write whatever is in local vfta copy */
1979 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1980 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1984 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1986 struct ixgbe_hwstrip *hwstrip =
1987 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1988 struct ixgbe_rx_queue *rxq;
1990 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1994 IXGBE_SET_HWSTRIP(hwstrip, queue);
1996 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1998 if (queue >= dev->data->nb_rx_queues)
2001 rxq = dev->data->rx_queues[queue];
2004 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2005 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2007 rxq->vlan_flags = PKT_RX_VLAN;
2008 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2013 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2015 struct ixgbe_hw *hw =
2016 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2019 PMD_INIT_FUNC_TRACE();
2021 if (hw->mac.type == ixgbe_mac_82598EB) {
2022 /* No queue level support */
2023 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2027 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2028 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2029 ctrl &= ~IXGBE_RXDCTL_VME;
2030 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2032 /* record those setting for HW strip per queue */
2033 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2037 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2039 struct ixgbe_hw *hw =
2040 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2043 PMD_INIT_FUNC_TRACE();
2045 if (hw->mac.type == ixgbe_mac_82598EB) {
2046 /* No queue level supported */
2047 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2051 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2052 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2053 ctrl |= IXGBE_RXDCTL_VME;
2054 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2056 /* record those setting for HW strip per queue */
2057 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2061 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2063 struct ixgbe_hw *hw =
2064 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067 PMD_INIT_FUNC_TRACE();
2069 /* DMATXCTRL: Geric Double VLAN Disable */
2070 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2071 ctrl &= ~IXGBE_DMATXCTL_GDV;
2072 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2074 /* CTRL_EXT: Global Double VLAN Disable */
2075 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2076 ctrl &= ~IXGBE_EXTENDED_VLAN;
2077 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2082 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2084 struct ixgbe_hw *hw =
2085 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088 PMD_INIT_FUNC_TRACE();
2090 /* DMATXCTRL: Geric Double VLAN Enable */
2091 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2092 ctrl |= IXGBE_DMATXCTL_GDV;
2093 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2095 /* CTRL_EXT: Global Double VLAN Enable */
2096 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2097 ctrl |= IXGBE_EXTENDED_VLAN;
2098 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2100 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2101 if (hw->mac.type == ixgbe_mac_X550 ||
2102 hw->mac.type == ixgbe_mac_X550EM_x ||
2103 hw->mac.type == ixgbe_mac_X550EM_a) {
2104 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2105 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2106 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2110 * VET EXT field in the EXVET register = 0x8100 by default
2111 * So no need to change. Same to VT field of DMATXCTL register
2116 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2118 struct ixgbe_hw *hw =
2119 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2123 struct ixgbe_rx_queue *rxq;
2126 PMD_INIT_FUNC_TRACE();
2128 if (hw->mac.type == ixgbe_mac_82598EB) {
2129 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2130 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2131 ctrl |= IXGBE_VLNCTRL_VME;
2132 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2134 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2135 ctrl &= ~IXGBE_VLNCTRL_VME;
2136 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2140 * Other 10G NIC, the VLAN strip can be setup
2141 * per queue in RXDCTL
2143 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2144 rxq = dev->data->rx_queues[i];
2145 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2146 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2147 ctrl |= IXGBE_RXDCTL_VME;
2150 ctrl &= ~IXGBE_RXDCTL_VME;
2153 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2155 /* record those setting for HW strip per queue */
2156 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2162 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2165 struct rte_eth_rxmode *rxmode;
2166 struct ixgbe_rx_queue *rxq;
2168 if (mask & ETH_VLAN_STRIP_MASK) {
2169 rxmode = &dev->data->dev_conf.rxmode;
2170 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2171 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2172 rxq = dev->data->rx_queues[i];
2173 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2176 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2177 rxq = dev->data->rx_queues[i];
2178 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2184 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2186 struct rte_eth_rxmode *rxmode;
2187 rxmode = &dev->data->dev_conf.rxmode;
2189 if (mask & ETH_VLAN_STRIP_MASK) {
2190 ixgbe_vlan_hw_strip_config(dev);
2193 if (mask & ETH_VLAN_FILTER_MASK) {
2194 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2195 ixgbe_vlan_hw_filter_enable(dev);
2197 ixgbe_vlan_hw_filter_disable(dev);
2200 if (mask & ETH_VLAN_EXTEND_MASK) {
2201 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2202 ixgbe_vlan_hw_extend_enable(dev);
2204 ixgbe_vlan_hw_extend_disable(dev);
2211 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2213 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2215 ixgbe_vlan_offload_config(dev, mask);
2221 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2223 struct ixgbe_hw *hw =
2224 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2225 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2226 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2228 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2229 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2233 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2235 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2240 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2243 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2249 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2250 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2251 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2252 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2257 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2259 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2260 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2261 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2262 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2264 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2265 /* check multi-queue mode */
2266 switch (dev_conf->rxmode.mq_mode) {
2267 case ETH_MQ_RX_VMDQ_DCB:
2268 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2270 case ETH_MQ_RX_VMDQ_DCB_RSS:
2271 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2272 PMD_INIT_LOG(ERR, "SRIOV active,"
2273 " unsupported mq_mode rx %d.",
2274 dev_conf->rxmode.mq_mode);
2277 case ETH_MQ_RX_VMDQ_RSS:
2278 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2279 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2280 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2281 PMD_INIT_LOG(ERR, "SRIOV is active,"
2282 " invalid queue number"
2283 " for VMDQ RSS, allowed"
2284 " value are 1, 2 or 4.");
2288 case ETH_MQ_RX_VMDQ_ONLY:
2289 case ETH_MQ_RX_NONE:
2290 /* if nothing mq mode configure, use default scheme */
2291 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2293 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2294 /* SRIOV only works in VMDq enable mode */
2295 PMD_INIT_LOG(ERR, "SRIOV is active,"
2296 " wrong mq_mode rx %d.",
2297 dev_conf->rxmode.mq_mode);
2301 switch (dev_conf->txmode.mq_mode) {
2302 case ETH_MQ_TX_VMDQ_DCB:
2303 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2304 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2306 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2307 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2311 /* check valid queue number */
2312 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2313 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2314 PMD_INIT_LOG(ERR, "SRIOV is active,"
2315 " nb_rx_q=%d nb_tx_q=%d queue number"
2316 " must be less than or equal to %d.",
2318 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2322 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2323 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2327 /* check configuration for vmdb+dcb mode */
2328 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2329 const struct rte_eth_vmdq_dcb_conf *conf;
2331 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2332 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2333 IXGBE_VMDQ_DCB_NB_QUEUES);
2336 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2337 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2338 conf->nb_queue_pools == ETH_32_POOLS)) {
2339 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2340 " nb_queue_pools must be %d or %d.",
2341 ETH_16_POOLS, ETH_32_POOLS);
2345 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2346 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2348 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2349 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2350 IXGBE_VMDQ_DCB_NB_QUEUES);
2353 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2354 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2355 conf->nb_queue_pools == ETH_32_POOLS)) {
2356 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2357 " nb_queue_pools != %d and"
2358 " nb_queue_pools != %d.",
2359 ETH_16_POOLS, ETH_32_POOLS);
2364 /* For DCB mode check our configuration before we go further */
2365 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2366 const struct rte_eth_dcb_rx_conf *conf;
2368 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2369 if (!(conf->nb_tcs == ETH_4_TCS ||
2370 conf->nb_tcs == ETH_8_TCS)) {
2371 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2372 " and nb_tcs != %d.",
2373 ETH_4_TCS, ETH_8_TCS);
2378 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2379 const struct rte_eth_dcb_tx_conf *conf;
2381 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2382 if (!(conf->nb_tcs == ETH_4_TCS ||
2383 conf->nb_tcs == ETH_8_TCS)) {
2384 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2385 " and nb_tcs != %d.",
2386 ETH_4_TCS, ETH_8_TCS);
2392 * When DCB/VT is off, maximum number of queues changes,
2393 * except for 82598EB, which remains constant.
2395 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2396 hw->mac.type != ixgbe_mac_82598EB) {
2397 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2399 "Neither VT nor DCB are enabled, "
2401 IXGBE_NONE_MODE_TX_NB_QUEUES);
2410 ixgbe_dev_configure(struct rte_eth_dev *dev)
2412 struct ixgbe_interrupt *intr =
2413 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2414 struct ixgbe_adapter *adapter = dev->data->dev_private;
2417 PMD_INIT_FUNC_TRACE();
2419 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2420 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2422 /* multipe queue mode checking */
2423 ret = ixgbe_check_mq_mode(dev);
2425 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2430 /* set flag to update link status after init */
2431 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2434 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2435 * allocation or vector Rx preconditions we will reset it.
2437 adapter->rx_bulk_alloc_allowed = true;
2438 adapter->rx_vec_allowed = true;
2444 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2446 struct ixgbe_hw *hw =
2447 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2448 struct ixgbe_interrupt *intr =
2449 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2452 /* only set up it on X550EM_X */
2453 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2454 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2455 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2456 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2457 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2458 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2463 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2464 uint16_t tx_rate, uint64_t q_msk)
2466 struct ixgbe_hw *hw;
2467 struct ixgbe_vf_info *vfinfo;
2468 struct rte_eth_link link;
2469 uint8_t nb_q_per_pool;
2470 uint32_t queue_stride;
2471 uint32_t queue_idx, idx = 0, vf_idx;
2473 uint16_t total_rate = 0;
2474 struct rte_pci_device *pci_dev;
2477 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2478 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2482 if (vf >= pci_dev->max_vfs)
2485 if (tx_rate > link.link_speed)
2491 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2493 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2494 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2495 queue_idx = vf * queue_stride;
2496 queue_end = queue_idx + nb_q_per_pool - 1;
2497 if (queue_end >= hw->mac.max_tx_queues)
2501 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2504 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2506 total_rate += vfinfo[vf_idx].tx_rate[idx];
2512 /* Store tx_rate for this vf. */
2513 for (idx = 0; idx < nb_q_per_pool; idx++) {
2514 if (((uint64_t)0x1 << idx) & q_msk) {
2515 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2516 vfinfo[vf].tx_rate[idx] = tx_rate;
2517 total_rate += tx_rate;
2521 if (total_rate > dev->data->dev_link.link_speed) {
2522 /* Reset stored TX rate of the VF if it causes exceed
2525 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2529 /* Set RTTBCNRC of each queue/pool for vf X */
2530 for (; queue_idx <= queue_end; queue_idx++) {
2532 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2540 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2542 struct ixgbe_adapter *adapter = dev->data->dev_private;
2546 err = ixgbe_fc_enable(hw);
2548 /* Not negotiated is not an error case */
2549 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2551 *check if we want to forward MAC frames - driver doesn't
2552 *have native capability to do that,
2553 *so we'll write the registers ourselves
2556 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2558 /* set or clear MFLCN.PMCF bit depending on configuration */
2559 if (adapter->mac_ctrl_frame_fwd != 0)
2560 mflcn |= IXGBE_MFLCN_PMCF;
2562 mflcn &= ~IXGBE_MFLCN_PMCF;
2564 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2565 IXGBE_WRITE_FLUSH(hw);
2573 * Configure device link speed and setup link.
2574 * It returns 0 on success.
2577 ixgbe_dev_start(struct rte_eth_dev *dev)
2579 struct ixgbe_hw *hw =
2580 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581 struct ixgbe_vf_info *vfinfo =
2582 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2583 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2584 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2585 uint32_t intr_vector = 0;
2587 bool link_up = false, negotiate = 0;
2589 uint32_t allowed_speeds = 0;
2593 uint32_t *link_speeds;
2594 struct ixgbe_tm_conf *tm_conf =
2595 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2596 struct ixgbe_macsec_setting *macsec_setting =
2597 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2599 PMD_INIT_FUNC_TRACE();
2601 /* Stop the link setup handler before resetting the HW. */
2602 ixgbe_dev_wait_setup_link_complete(dev, 0);
2604 /* disable uio/vfio intr/eventfd mapping */
2605 rte_intr_disable(intr_handle);
2608 hw->adapter_stopped = 0;
2609 ixgbe_stop_adapter(hw);
2611 /* reinitialize adapter
2612 * this calls reset and start
2614 status = ixgbe_pf_reset_hw(hw);
2617 hw->mac.ops.start_hw(hw);
2618 hw->mac.get_link_status = true;
2620 /* configure PF module if SRIOV enabled */
2621 ixgbe_pf_host_configure(dev);
2623 ixgbe_dev_phy_intr_setup(dev);
2625 /* check and configure queue intr-vector mapping */
2626 if ((rte_intr_cap_multiple(intr_handle) ||
2627 !RTE_ETH_DEV_SRIOV(dev).active) &&
2628 dev->data->dev_conf.intr_conf.rxq != 0) {
2629 intr_vector = dev->data->nb_rx_queues;
2630 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2631 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2632 IXGBE_MAX_INTR_QUEUE_NUM);
2635 if (rte_intr_efd_enable(intr_handle, intr_vector))
2639 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2640 intr_handle->intr_vec =
2641 rte_zmalloc("intr_vec",
2642 dev->data->nb_rx_queues * sizeof(int), 0);
2643 if (intr_handle->intr_vec == NULL) {
2644 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2645 " intr_vec", dev->data->nb_rx_queues);
2650 /* confiugre msix for sleep until rx interrupt */
2651 ixgbe_configure_msix(dev);
2653 /* initialize transmission unit */
2654 ixgbe_dev_tx_init(dev);
2656 /* This can fail when allocating mbufs for descriptor rings */
2657 err = ixgbe_dev_rx_init(dev);
2659 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2663 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2664 ETH_VLAN_EXTEND_MASK;
2665 err = ixgbe_vlan_offload_config(dev, mask);
2667 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2671 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2672 /* Enable vlan filtering for VMDq */
2673 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2676 /* Configure DCB hw */
2677 ixgbe_configure_dcb(dev);
2679 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2680 err = ixgbe_fdir_configure(dev);
2685 /* Restore vf rate limit */
2686 if (vfinfo != NULL) {
2687 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2688 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2689 if (vfinfo[vf].tx_rate[idx] != 0)
2690 ixgbe_set_vf_rate_limit(
2692 vfinfo[vf].tx_rate[idx],
2696 ixgbe_restore_statistics_mapping(dev);
2698 err = ixgbe_flow_ctrl_enable(dev, hw);
2700 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2704 err = ixgbe_dev_rxtx_start(dev);
2706 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2710 /* Skip link setup if loopback mode is enabled. */
2711 if (dev->data->dev_conf.lpbk_mode != 0) {
2712 err = ixgbe_check_supported_loopback_mode(dev);
2714 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2717 goto skip_link_setup;
2721 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2722 err = hw->mac.ops.setup_sfp(hw);
2727 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2728 /* Turn on the copper */
2729 ixgbe_set_phy_power(hw, true);
2731 /* Turn on the laser */
2732 ixgbe_enable_tx_laser(hw);
2735 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2738 dev->data->dev_link.link_status = link_up;
2740 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2744 switch (hw->mac.type) {
2745 case ixgbe_mac_X550:
2746 case ixgbe_mac_X550EM_x:
2747 case ixgbe_mac_X550EM_a:
2748 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2749 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2751 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2752 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2753 allowed_speeds = ETH_LINK_SPEED_10M |
2754 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2757 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2761 link_speeds = &dev->data->dev_conf.link_speeds;
2763 /* Ignore autoneg flag bit and check the validity ofÂ
2766 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2767 PMD_INIT_LOG(ERR, "Invalid link setting");
2772 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2773 switch (hw->mac.type) {
2774 case ixgbe_mac_82598EB:
2775 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2777 case ixgbe_mac_82599EB:
2778 case ixgbe_mac_X540:
2779 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2781 case ixgbe_mac_X550:
2782 case ixgbe_mac_X550EM_x:
2783 case ixgbe_mac_X550EM_a:
2784 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2787 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2790 if (*link_speeds & ETH_LINK_SPEED_10G)
2791 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2792 if (*link_speeds & ETH_LINK_SPEED_5G)
2793 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2794 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2795 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2796 if (*link_speeds & ETH_LINK_SPEED_1G)
2797 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2798 if (*link_speeds & ETH_LINK_SPEED_100M)
2799 speed |= IXGBE_LINK_SPEED_100_FULL;
2800 if (*link_speeds & ETH_LINK_SPEED_10M)
2801 speed |= IXGBE_LINK_SPEED_10_FULL;
2804 err = ixgbe_setup_link(hw, speed, link_up);
2810 if (rte_intr_allow_others(intr_handle)) {
2811 /* check if lsc interrupt is enabled */
2812 if (dev->data->dev_conf.intr_conf.lsc != 0)
2813 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2815 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2816 ixgbe_dev_macsec_interrupt_setup(dev);
2818 rte_intr_callback_unregister(intr_handle,
2819 ixgbe_dev_interrupt_handler, dev);
2820 if (dev->data->dev_conf.intr_conf.lsc != 0)
2821 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2822 " no intr multiplex");
2825 /* check if rxq interrupt is enabled */
2826 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2827 rte_intr_dp_is_en(intr_handle))
2828 ixgbe_dev_rxq_interrupt_setup(dev);
2830 /* enable uio/vfio intr/eventfd mapping */
2831 rte_intr_enable(intr_handle);
2833 /* resume enabled intr since hw reset */
2834 ixgbe_enable_intr(dev);
2835 ixgbe_l2_tunnel_conf(dev);
2836 ixgbe_filter_restore(dev);
2838 if (tm_conf->root && !tm_conf->committed)
2839 PMD_DRV_LOG(WARNING,
2840 "please call hierarchy_commit() "
2841 "before starting the port");
2843 /* wait for the controller to acquire link */
2844 err = ixgbe_wait_for_link_up(hw);
2849 * Update link status right before return, because it may
2850 * start link configuration process in a separate thread.
2852 ixgbe_dev_link_update(dev, 0);
2854 /* setup the macsec setting register */
2855 if (macsec_setting->offload_en)
2856 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2861 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2862 ixgbe_dev_clear_queues(dev);
2867 * Stop device: disable rx and tx functions to allow for reconfiguring.
2870 ixgbe_dev_stop(struct rte_eth_dev *dev)
2872 struct rte_eth_link link;
2873 struct ixgbe_adapter *adapter = dev->data->dev_private;
2874 struct ixgbe_hw *hw =
2875 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876 struct ixgbe_vf_info *vfinfo =
2877 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2878 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2879 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2881 struct ixgbe_tm_conf *tm_conf =
2882 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2884 if (hw->adapter_stopped)
2887 PMD_INIT_FUNC_TRACE();
2889 ixgbe_dev_wait_setup_link_complete(dev, 0);
2891 /* disable interrupts */
2892 ixgbe_disable_intr(hw);
2895 ixgbe_pf_reset_hw(hw);
2896 hw->adapter_stopped = 0;
2899 ixgbe_stop_adapter(hw);
2901 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2902 vfinfo[vf].clear_to_send = false;
2904 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2905 /* Turn off the copper */
2906 ixgbe_set_phy_power(hw, false);
2908 /* Turn off the laser */
2909 ixgbe_disable_tx_laser(hw);
2912 ixgbe_dev_clear_queues(dev);
2914 /* Clear stored conf */
2915 dev->data->scattered_rx = 0;
2918 /* Clear recorded link status */
2919 memset(&link, 0, sizeof(link));
2920 rte_eth_linkstatus_set(dev, &link);
2922 if (!rte_intr_allow_others(intr_handle))
2923 /* resume to the default handler */
2924 rte_intr_callback_register(intr_handle,
2925 ixgbe_dev_interrupt_handler,
2928 /* Clean datapath event and queue/vec mapping */
2929 rte_intr_efd_disable(intr_handle);
2930 if (intr_handle->intr_vec != NULL) {
2931 rte_free(intr_handle->intr_vec);
2932 intr_handle->intr_vec = NULL;
2935 /* reset hierarchy commit */
2936 tm_conf->committed = false;
2938 adapter->rss_reta_updated = 0;
2940 adapter->mac_ctrl_frame_fwd = 0;
2942 hw->adapter_stopped = true;
2946 * Set device link up: enable tx.
2949 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2951 struct ixgbe_hw *hw =
2952 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2953 if (hw->mac.type == ixgbe_mac_82599EB) {
2954 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2955 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2956 /* Not suported in bypass mode */
2957 PMD_INIT_LOG(ERR, "Set link up is not supported "
2958 "by device id 0x%x", hw->device_id);
2964 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2965 /* Turn on the copper */
2966 ixgbe_set_phy_power(hw, true);
2968 /* Turn on the laser */
2969 ixgbe_enable_tx_laser(hw);
2970 ixgbe_dev_link_update(dev, 0);
2977 * Set device link down: disable tx.
2980 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2982 struct ixgbe_hw *hw =
2983 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2984 if (hw->mac.type == ixgbe_mac_82599EB) {
2985 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2986 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2987 /* Not suported in bypass mode */
2988 PMD_INIT_LOG(ERR, "Set link down is not supported "
2989 "by device id 0x%x", hw->device_id);
2995 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2996 /* Turn off the copper */
2997 ixgbe_set_phy_power(hw, false);
2999 /* Turn off the laser */
3000 ixgbe_disable_tx_laser(hw);
3001 ixgbe_dev_link_update(dev, 0);
3008 * Reset and stop device.
3011 ixgbe_dev_close(struct rte_eth_dev *dev)
3013 struct ixgbe_hw *hw =
3014 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3016 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3020 PMD_INIT_FUNC_TRACE();
3022 ixgbe_pf_reset_hw(hw);
3024 ixgbe_dev_stop(dev);
3026 ixgbe_dev_free_queues(dev);
3028 ixgbe_disable_pcie_master(hw);
3030 /* reprogram the RAR[0] in case user changed it. */
3031 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3033 dev->dev_ops = NULL;
3034 dev->rx_pkt_burst = NULL;
3035 dev->tx_pkt_burst = NULL;
3037 /* Unlock any pending hardware semaphore */
3038 ixgbe_swfw_lock_reset(hw);
3040 /* disable uio intr before callback unregister */
3041 rte_intr_disable(intr_handle);
3044 ret = rte_intr_callback_unregister(intr_handle,
3045 ixgbe_dev_interrupt_handler, dev);
3046 if (ret >= 0 || ret == -ENOENT) {
3048 } else if (ret != -EAGAIN) {
3050 "intr callback unregister failed: %d",
3054 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3056 /* cancel the delay handler before remove dev */
3057 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3059 /* uninitialize PF if max_vfs not zero */
3060 ixgbe_pf_host_uninit(dev);
3062 /* remove all the fdir filters & hash */
3063 ixgbe_fdir_filter_uninit(dev);
3065 /* remove all the L2 tunnel filters & hash */
3066 ixgbe_l2_tn_filter_uninit(dev);
3068 /* Remove all ntuple filters of the device */
3069 ixgbe_ntuple_filter_uninit(dev);
3071 /* clear all the filters list */
3072 ixgbe_filterlist_flush();
3074 /* Remove all Traffic Manager configuration */
3075 ixgbe_tm_conf_uninit(dev);
3077 #ifdef RTE_LIBRTE_SECURITY
3078 rte_free(dev->security_ctx);
3087 ixgbe_dev_reset(struct rte_eth_dev *dev)
3091 /* When a DPDK PMD PF begin to reset PF port, it should notify all
3092 * its VF to make them align with it. The detailed notification
3093 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3094 * To avoid unexpected behavior in VF, currently reset of PF with
3095 * SR-IOV activation is not supported. It might be supported later.
3097 if (dev->data->sriov.active)
3100 ret = eth_ixgbe_dev_uninit(dev);
3104 ret = eth_ixgbe_dev_init(dev, NULL);
3110 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3111 struct ixgbe_hw_stats *hw_stats,
3112 struct ixgbe_macsec_stats *macsec_stats,
3113 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3114 uint64_t *total_qprc, uint64_t *total_qprdc)
3116 uint32_t bprc, lxon, lxoff, total;
3117 uint32_t delta_gprc = 0;
3119 /* Workaround for RX byte count not including CRC bytes when CRC
3120 * strip is enabled. CRC bytes are removed from counters when crc_strip
3123 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3124 IXGBE_HLREG0_RXCRCSTRP);
3126 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3127 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3128 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3129 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3131 for (i = 0; i < 8; i++) {
3132 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3134 /* global total per queue */
3135 hw_stats->mpc[i] += mp;
3136 /* Running comprehensive total for stats display */
3137 *total_missed_rx += hw_stats->mpc[i];
3138 if (hw->mac.type == ixgbe_mac_82598EB) {
3139 hw_stats->rnbc[i] +=
3140 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3141 hw_stats->pxonrxc[i] +=
3142 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3143 hw_stats->pxoffrxc[i] +=
3144 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3146 hw_stats->pxonrxc[i] +=
3147 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3148 hw_stats->pxoffrxc[i] +=
3149 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3150 hw_stats->pxon2offc[i] +=
3151 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3153 hw_stats->pxontxc[i] +=
3154 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3155 hw_stats->pxofftxc[i] +=
3156 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3158 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3159 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3160 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3161 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3163 delta_gprc += delta_qprc;
3165 hw_stats->qprc[i] += delta_qprc;
3166 hw_stats->qptc[i] += delta_qptc;
3168 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3169 hw_stats->qbrc[i] +=
3170 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3172 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3174 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3175 hw_stats->qbtc[i] +=
3176 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3178 hw_stats->qprdc[i] += delta_qprdc;
3179 *total_qprdc += hw_stats->qprdc[i];
3181 *total_qprc += hw_stats->qprc[i];
3182 *total_qbrc += hw_stats->qbrc[i];
3184 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3185 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3186 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3189 * An errata states that gprc actually counts good + missed packets:
3190 * Workaround to set gprc to summated queue packet receives
3192 hw_stats->gprc = *total_qprc;
3194 if (hw->mac.type != ixgbe_mac_82598EB) {
3195 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3196 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3197 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3198 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3199 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3200 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3201 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3202 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3204 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3205 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3206 /* 82598 only has a counter in the high register */
3207 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3208 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3209 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3211 uint64_t old_tpr = hw_stats->tpr;
3213 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3214 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3217 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3219 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3220 hw_stats->gptc += delta_gptc;
3221 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3222 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3225 * Workaround: mprc hardware is incorrectly counting
3226 * broadcasts, so for now we subtract those.
3228 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3229 hw_stats->bprc += bprc;
3230 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3231 if (hw->mac.type == ixgbe_mac_82598EB)
3232 hw_stats->mprc -= bprc;
3234 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3235 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3236 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3237 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3238 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3239 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3241 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3242 hw_stats->lxontxc += lxon;
3243 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3244 hw_stats->lxofftxc += lxoff;
3245 total = lxon + lxoff;
3247 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3248 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3249 hw_stats->gptc -= total;
3250 hw_stats->mptc -= total;
3251 hw_stats->ptc64 -= total;
3252 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3254 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3255 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3256 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3257 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3258 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3259 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3260 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3261 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3262 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3263 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3264 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3265 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3266 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3267 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3268 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3269 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3270 /* Only read FCOE on 82599 */
3271 if (hw->mac.type != ixgbe_mac_82598EB) {
3272 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3273 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3274 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3275 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3276 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3279 /* Flow Director Stats registers */
3280 if (hw->mac.type != ixgbe_mac_82598EB) {
3281 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3282 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3283 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3284 IXGBE_FDIRUSTAT) & 0xFFFF;
3285 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3286 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3287 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3288 IXGBE_FDIRFSTAT) & 0xFFFF;
3289 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3290 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3292 /* MACsec Stats registers */
3293 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3294 macsec_stats->out_pkts_encrypted +=
3295 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3296 macsec_stats->out_pkts_protected +=
3297 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3298 macsec_stats->out_octets_encrypted +=
3299 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3300 macsec_stats->out_octets_protected +=
3301 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3302 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3303 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3304 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3305 macsec_stats->in_pkts_unknownsci +=
3306 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3307 macsec_stats->in_octets_decrypted +=
3308 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3309 macsec_stats->in_octets_validated +=
3310 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3311 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3312 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3313 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3314 for (i = 0; i < 2; i++) {
3315 macsec_stats->in_pkts_ok +=
3316 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3317 macsec_stats->in_pkts_invalid +=
3318 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3319 macsec_stats->in_pkts_notvalid +=
3320 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3322 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3323 macsec_stats->in_pkts_notusingsa +=
3324 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3328 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3331 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3333 struct ixgbe_hw *hw =
3334 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3335 struct ixgbe_hw_stats *hw_stats =
3336 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3337 struct ixgbe_macsec_stats *macsec_stats =
3338 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3339 dev->data->dev_private);
3340 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3343 total_missed_rx = 0;
3348 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3349 &total_qbrc, &total_qprc, &total_qprdc);
3354 /* Fill out the rte_eth_stats statistics structure */
3355 stats->ipackets = total_qprc;
3356 stats->ibytes = total_qbrc;
3357 stats->opackets = hw_stats->gptc;
3358 stats->obytes = hw_stats->gotc;
3360 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3361 stats->q_ipackets[i] = hw_stats->qprc[i];
3362 stats->q_opackets[i] = hw_stats->qptc[i];
3363 stats->q_ibytes[i] = hw_stats->qbrc[i];
3364 stats->q_obytes[i] = hw_stats->qbtc[i];
3365 stats->q_errors[i] = hw_stats->qprdc[i];
3369 stats->imissed = total_missed_rx;
3370 stats->ierrors = hw_stats->crcerrs +
3387 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3389 struct ixgbe_hw_stats *stats =
3390 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3392 /* HW registers are cleared on read */
3393 ixgbe_dev_stats_get(dev, NULL);
3395 /* Reset software totals */
3396 memset(stats, 0, sizeof(*stats));
3401 /* This function calculates the number of xstats based on the current config */
3403 ixgbe_xstats_calc_num(void) {
3404 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3405 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3406 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3409 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3410 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3412 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3413 unsigned stat, i, count;
3415 if (xstats_names != NULL) {
3418 /* Note: limit >= cnt_stats checked upstream
3419 * in rte_eth_xstats_names()
3422 /* Extended stats from ixgbe_hw_stats */
3423 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3424 strlcpy(xstats_names[count].name,
3425 rte_ixgbe_stats_strings[i].name,
3426 sizeof(xstats_names[count].name));
3431 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3432 strlcpy(xstats_names[count].name,
3433 rte_ixgbe_macsec_strings[i].name,
3434 sizeof(xstats_names[count].name));
3438 /* RX Priority Stats */
3439 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3440 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3441 snprintf(xstats_names[count].name,
3442 sizeof(xstats_names[count].name),
3443 "rx_priority%u_%s", i,
3444 rte_ixgbe_rxq_strings[stat].name);
3449 /* TX Priority Stats */
3450 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3451 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3452 snprintf(xstats_names[count].name,
3453 sizeof(xstats_names[count].name),
3454 "tx_priority%u_%s", i,
3455 rte_ixgbe_txq_strings[stat].name);
3463 static int ixgbe_dev_xstats_get_names_by_id(
3464 struct rte_eth_dev *dev,
3465 struct rte_eth_xstat_name *xstats_names,
3466 const uint64_t *ids,
3470 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3471 unsigned int stat, i, count;
3473 if (xstats_names != NULL) {
3476 /* Note: limit >= cnt_stats checked upstream
3477 * in rte_eth_xstats_names()
3480 /* Extended stats from ixgbe_hw_stats */
3481 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3482 strlcpy(xstats_names[count].name,
3483 rte_ixgbe_stats_strings[i].name,
3484 sizeof(xstats_names[count].name));
3489 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3490 strlcpy(xstats_names[count].name,
3491 rte_ixgbe_macsec_strings[i].name,
3492 sizeof(xstats_names[count].name));
3496 /* RX Priority Stats */
3497 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3498 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3499 snprintf(xstats_names[count].name,
3500 sizeof(xstats_names[count].name),
3501 "rx_priority%u_%s", i,
3502 rte_ixgbe_rxq_strings[stat].name);
3507 /* TX Priority Stats */
3508 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3509 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3510 snprintf(xstats_names[count].name,
3511 sizeof(xstats_names[count].name),
3512 "tx_priority%u_%s", i,
3513 rte_ixgbe_txq_strings[stat].name);
3522 uint16_t size = ixgbe_xstats_calc_num();
3523 struct rte_eth_xstat_name xstats_names_copy[size];
3525 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3528 for (i = 0; i < limit; i++) {
3529 if (ids[i] >= size) {
3530 PMD_INIT_LOG(ERR, "id value isn't valid");
3533 strcpy(xstats_names[i].name,
3534 xstats_names_copy[ids[i]].name);
3539 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3540 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3544 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3547 if (xstats_names != NULL)
3548 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3549 strlcpy(xstats_names[i].name,
3550 rte_ixgbevf_stats_strings[i].name,
3551 sizeof(xstats_names[i].name));
3552 return IXGBEVF_NB_XSTATS;
3556 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3559 struct ixgbe_hw *hw =
3560 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3561 struct ixgbe_hw_stats *hw_stats =
3562 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3563 struct ixgbe_macsec_stats *macsec_stats =
3564 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3565 dev->data->dev_private);
3566 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3567 unsigned i, stat, count = 0;
3569 count = ixgbe_xstats_calc_num();
3574 total_missed_rx = 0;
3579 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3580 &total_qbrc, &total_qprc, &total_qprdc);
3582 /* If this is a reset xstats is NULL, and we have cleared the
3583 * registers by reading them.
3588 /* Extended stats from ixgbe_hw_stats */
3590 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3591 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3592 rte_ixgbe_stats_strings[i].offset);
3593 xstats[count].id = count;
3598 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3599 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3600 rte_ixgbe_macsec_strings[i].offset);
3601 xstats[count].id = count;
3605 /* RX Priority Stats */
3606 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3607 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3608 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3609 rte_ixgbe_rxq_strings[stat].offset +
3610 (sizeof(uint64_t) * i));
3611 xstats[count].id = count;
3616 /* TX Priority Stats */
3617 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3618 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3619 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3620 rte_ixgbe_txq_strings[stat].offset +
3621 (sizeof(uint64_t) * i));
3622 xstats[count].id = count;
3630 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3631 uint64_t *values, unsigned int n)
3634 struct ixgbe_hw *hw =
3635 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3636 struct ixgbe_hw_stats *hw_stats =
3637 IXGBE_DEV_PRIVATE_TO_STATS(
3638 dev->data->dev_private);
3639 struct ixgbe_macsec_stats *macsec_stats =
3640 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3641 dev->data->dev_private);
3642 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3643 unsigned int i, stat, count = 0;
3645 count = ixgbe_xstats_calc_num();
3647 if (!ids && n < count)
3650 total_missed_rx = 0;
3655 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3656 &total_missed_rx, &total_qbrc, &total_qprc,
3659 /* If this is a reset xstats is NULL, and we have cleared the
3660 * registers by reading them.
3662 if (!ids && !values)
3665 /* Extended stats from ixgbe_hw_stats */
3667 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3668 values[count] = *(uint64_t *)(((char *)hw_stats) +
3669 rte_ixgbe_stats_strings[i].offset);
3674 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3675 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3676 rte_ixgbe_macsec_strings[i].offset);
3680 /* RX Priority Stats */
3681 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3682 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3684 *(uint64_t *)(((char *)hw_stats) +
3685 rte_ixgbe_rxq_strings[stat].offset +
3686 (sizeof(uint64_t) * i));
3691 /* TX Priority Stats */
3692 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3693 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3695 *(uint64_t *)(((char *)hw_stats) +
3696 rte_ixgbe_txq_strings[stat].offset +
3697 (sizeof(uint64_t) * i));
3705 uint16_t size = ixgbe_xstats_calc_num();
3706 uint64_t values_copy[size];
3708 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3710 for (i = 0; i < n; i++) {
3711 if (ids[i] >= size) {
3712 PMD_INIT_LOG(ERR, "id value isn't valid");
3715 values[i] = values_copy[ids[i]];
3721 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3723 struct ixgbe_hw_stats *stats =
3724 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3725 struct ixgbe_macsec_stats *macsec_stats =
3726 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3727 dev->data->dev_private);
3729 unsigned count = ixgbe_xstats_calc_num();
3731 /* HW registers are cleared on read */
3732 ixgbe_dev_xstats_get(dev, NULL, count);
3734 /* Reset software totals */
3735 memset(stats, 0, sizeof(*stats));
3736 memset(macsec_stats, 0, sizeof(*macsec_stats));
3742 ixgbevf_update_stats(struct rte_eth_dev *dev)
3744 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3745 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3746 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3748 /* Good Rx packet, include VF loopback */
3749 UPDATE_VF_STAT(IXGBE_VFGPRC,
3750 hw_stats->last_vfgprc, hw_stats->vfgprc);
3752 /* Good Rx octets, include VF loopback */
3753 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3754 hw_stats->last_vfgorc, hw_stats->vfgorc);
3756 /* Good Tx packet, include VF loopback */
3757 UPDATE_VF_STAT(IXGBE_VFGPTC,
3758 hw_stats->last_vfgptc, hw_stats->vfgptc);
3760 /* Good Tx octets, include VF loopback */
3761 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3762 hw_stats->last_vfgotc, hw_stats->vfgotc);
3764 /* Rx Multicst Packet */
3765 UPDATE_VF_STAT(IXGBE_VFMPRC,
3766 hw_stats->last_vfmprc, hw_stats->vfmprc);
3770 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3773 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3774 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3777 if (n < IXGBEVF_NB_XSTATS)
3778 return IXGBEVF_NB_XSTATS;
3780 ixgbevf_update_stats(dev);
3785 /* Extended stats */
3786 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3788 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3789 rte_ixgbevf_stats_strings[i].offset);
3792 return IXGBEVF_NB_XSTATS;
3796 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3798 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3799 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3801 ixgbevf_update_stats(dev);
3806 stats->ipackets = hw_stats->vfgprc;
3807 stats->ibytes = hw_stats->vfgorc;
3808 stats->opackets = hw_stats->vfgptc;
3809 stats->obytes = hw_stats->vfgotc;
3814 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3816 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3817 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3819 /* Sync HW register to the last stats */
3820 ixgbevf_dev_stats_get(dev, NULL);
3822 /* reset HW current stats*/
3823 hw_stats->vfgprc = 0;
3824 hw_stats->vfgorc = 0;
3825 hw_stats->vfgptc = 0;
3826 hw_stats->vfgotc = 0;
3832 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3834 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3835 u16 eeprom_verh, eeprom_verl;
3839 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3840 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3842 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3843 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3845 ret += 1; /* add the size of '\0' */
3846 if (fw_size < (u32)ret)
3853 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3855 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3856 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3857 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3859 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3860 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3861 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3863 * When DCB/VT is off, maximum number of queues changes,
3864 * except for 82598EB, which remains constant.
3866 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3867 hw->mac.type != ixgbe_mac_82598EB)
3868 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3870 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3871 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3872 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3873 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3874 dev_info->max_vfs = pci_dev->max_vfs;
3875 if (hw->mac.type == ixgbe_mac_82598EB)
3876 dev_info->max_vmdq_pools = ETH_16_POOLS;
3878 dev_info->max_vmdq_pools = ETH_64_POOLS;
3879 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3880 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3881 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3882 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3883 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3884 dev_info->rx_queue_offload_capa);
3885 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3886 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3888 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3890 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3891 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3892 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3894 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3899 dev_info->default_txconf = (struct rte_eth_txconf) {
3901 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3902 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3903 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3905 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3906 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3910 dev_info->rx_desc_lim = rx_desc_lim;
3911 dev_info->tx_desc_lim = tx_desc_lim;
3913 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3914 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3915 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3917 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3918 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3919 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3920 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3921 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3923 if (hw->mac.type == ixgbe_mac_X540 ||
3924 hw->mac.type == ixgbe_mac_X540_vf ||
3925 hw->mac.type == ixgbe_mac_X550 ||
3926 hw->mac.type == ixgbe_mac_X550_vf) {
3927 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3929 if (hw->mac.type == ixgbe_mac_X550) {
3930 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3931 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3934 /* Driver-preferred Rx/Tx parameters */
3935 dev_info->default_rxportconf.burst_size = 32;
3936 dev_info->default_txportconf.burst_size = 32;
3937 dev_info->default_rxportconf.nb_queues = 1;
3938 dev_info->default_txportconf.nb_queues = 1;
3939 dev_info->default_rxportconf.ring_size = 256;
3940 dev_info->default_txportconf.ring_size = 256;
3945 static const uint32_t *
3946 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3948 static const uint32_t ptypes[] = {
3949 /* For non-vec functions,
3950 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3951 * for vec functions,
3952 * refers to _recv_raw_pkts_vec().
3956 RTE_PTYPE_L3_IPV4_EXT,
3958 RTE_PTYPE_L3_IPV6_EXT,
3962 RTE_PTYPE_TUNNEL_IP,
3963 RTE_PTYPE_INNER_L3_IPV6,
3964 RTE_PTYPE_INNER_L3_IPV6_EXT,
3965 RTE_PTYPE_INNER_L4_TCP,
3966 RTE_PTYPE_INNER_L4_UDP,
3970 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3971 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3972 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3973 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3976 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3977 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3978 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3985 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3986 struct rte_eth_dev_info *dev_info)
3988 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3989 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3991 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3992 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3993 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3994 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3995 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3996 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3997 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3998 dev_info->max_vfs = pci_dev->max_vfs;
3999 if (hw->mac.type == ixgbe_mac_82598EB)
4000 dev_info->max_vmdq_pools = ETH_16_POOLS;
4002 dev_info->max_vmdq_pools = ETH_64_POOLS;
4003 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
4004 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
4005 dev_info->rx_queue_offload_capa);
4006 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
4007 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
4008 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
4009 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
4010 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
4012 dev_info->default_rxconf = (struct rte_eth_rxconf) {
4014 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
4015 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
4016 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
4018 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4023 dev_info->default_txconf = (struct rte_eth_txconf) {
4025 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4026 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4027 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4029 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4030 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4034 dev_info->rx_desc_lim = rx_desc_lim;
4035 dev_info->tx_desc_lim = tx_desc_lim;
4041 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4042 bool *link_up, int wait_to_complete)
4044 struct ixgbe_adapter *adapter = container_of(hw,
4045 struct ixgbe_adapter, hw);
4046 struct ixgbe_mbx_info *mbx = &hw->mbx;
4047 struct ixgbe_mac_info *mac = &hw->mac;
4048 uint32_t links_reg, in_msg;
4051 /* If we were hit with a reset drop the link */
4052 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4053 mac->get_link_status = true;
4055 if (!mac->get_link_status)
4058 /* if link status is down no point in checking to see if pf is up */
4059 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4060 if (!(links_reg & IXGBE_LINKS_UP))
4063 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4064 * before the link status is correct
4066 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4069 for (i = 0; i < 5; i++) {
4071 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4073 if (!(links_reg & IXGBE_LINKS_UP))
4078 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4079 case IXGBE_LINKS_SPEED_10G_82599:
4080 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4081 if (hw->mac.type >= ixgbe_mac_X550) {
4082 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4083 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4086 case IXGBE_LINKS_SPEED_1G_82599:
4087 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4089 case IXGBE_LINKS_SPEED_100_82599:
4090 *speed = IXGBE_LINK_SPEED_100_FULL;
4091 if (hw->mac.type == ixgbe_mac_X550) {
4092 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4093 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4096 case IXGBE_LINKS_SPEED_10_X550EM_A:
4097 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4098 /* Since Reserved in older MAC's */
4099 if (hw->mac.type >= ixgbe_mac_X550)
4100 *speed = IXGBE_LINK_SPEED_10_FULL;
4103 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4106 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4107 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4108 mac->get_link_status = true;
4110 mac->get_link_status = false;
4115 /* if the read failed it could just be a mailbox collision, best wait
4116 * until we are called again and don't report an error
4118 if (mbx->ops.read(hw, &in_msg, 1, 0))
4121 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4122 /* msg is not CTS and is NACK we must have lost CTS status */
4123 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4124 mac->get_link_status = false;
4128 /* the pf is talking, if we timed out in the past we reinit */
4129 if (!mbx->timeout) {
4134 /* if we passed all the tests above then the link is up and we no
4135 * longer need to check for link
4137 mac->get_link_status = false;
4140 *link_up = !mac->get_link_status;
4145 * If @timeout_ms was 0, it means that it will not return until link complete.
4146 * It returns 1 on complete, return 0 on timeout.
4149 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4151 #define WARNING_TIMEOUT 9000 /* 9s in total */
4152 struct ixgbe_adapter *ad = dev->data->dev_private;
4153 uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4155 while (rte_atomic32_read(&ad->link_thread_running)) {
4162 } else if (!timeout) {
4163 /* It will not return until link complete */
4164 timeout = WARNING_TIMEOUT;
4165 PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4173 ixgbe_dev_setup_link_thread_handler(void *param)
4175 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4176 struct ixgbe_adapter *ad = dev->data->dev_private;
4177 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4178 struct ixgbe_interrupt *intr =
4179 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4181 bool autoneg = false;
4183 pthread_detach(pthread_self());
4184 speed = hw->phy.autoneg_advertised;
4186 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4188 ixgbe_setup_link(hw, speed, true);
4190 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4191 rte_atomic32_clear(&ad->link_thread_running);
4196 * In freebsd environment, nic_uio drivers do not support interrupts,
4197 * rte_intr_callback_register() will fail to register interrupts.
4198 * We can not make link status to change from down to up by interrupt
4199 * callback. So we need to wait for the controller to acquire link
4201 * It returns 0 on link up.
4204 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4206 #ifdef RTE_EXEC_ENV_FREEBSD
4208 bool link_up = false;
4210 const int nb_iter = 25;
4212 for (i = 0; i < nb_iter; i++) {
4213 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4228 /* return 0 means link status changed, -1 means not changed */
4230 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4231 int wait_to_complete, int vf)
4233 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4234 struct ixgbe_adapter *ad = dev->data->dev_private;
4235 struct rte_eth_link link;
4236 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4237 struct ixgbe_interrupt *intr =
4238 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4244 memset(&link, 0, sizeof(link));
4245 link.link_status = ETH_LINK_DOWN;
4246 link.link_speed = ETH_SPEED_NUM_NONE;
4247 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4248 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4249 ETH_LINK_SPEED_FIXED);
4251 hw->mac.get_link_status = true;
4253 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4254 return rte_eth_linkstatus_set(dev, &link);
4256 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4257 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4260 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4261 #ifdef RTE_EXEC_ENV_FREEBSD
4266 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4268 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4271 link.link_speed = ETH_SPEED_NUM_100M;
4272 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4273 return rte_eth_linkstatus_set(dev, &link);
4276 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4277 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4278 if ((esdp_reg & IXGBE_ESDP_SDP3))
4283 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4284 ixgbe_dev_wait_setup_link_complete(dev, 0);
4285 if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4286 /* To avoid race condition between threads, set
4287 * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4288 * when there is no link thread running.
4290 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4291 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4292 "ixgbe-link-handler",
4294 ixgbe_dev_setup_link_thread_handler,
4297 "Create link thread failed!");
4298 rte_atomic32_clear(&ad->link_thread_running);
4302 "Other link thread is running now!");
4305 return rte_eth_linkstatus_set(dev, &link);
4308 link.link_status = ETH_LINK_UP;
4309 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4311 switch (link_speed) {
4313 case IXGBE_LINK_SPEED_UNKNOWN:
4314 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4315 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4316 link.link_speed = ETH_SPEED_NUM_10M;
4318 link.link_speed = ETH_SPEED_NUM_100M;
4321 case IXGBE_LINK_SPEED_100_FULL:
4322 link.link_speed = ETH_SPEED_NUM_100M;
4325 case IXGBE_LINK_SPEED_1GB_FULL:
4326 link.link_speed = ETH_SPEED_NUM_1G;
4329 case IXGBE_LINK_SPEED_2_5GB_FULL:
4330 link.link_speed = ETH_SPEED_NUM_2_5G;
4333 case IXGBE_LINK_SPEED_5GB_FULL:
4334 link.link_speed = ETH_SPEED_NUM_5G;
4337 case IXGBE_LINK_SPEED_10GB_FULL:
4338 link.link_speed = ETH_SPEED_NUM_10G;
4342 return rte_eth_linkstatus_set(dev, &link);
4346 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4348 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4352 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4354 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4358 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4360 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4363 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4364 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4365 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4371 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4373 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4376 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4377 fctrl &= (~IXGBE_FCTRL_UPE);
4378 if (dev->data->all_multicast == 1)
4379 fctrl |= IXGBE_FCTRL_MPE;
4381 fctrl &= (~IXGBE_FCTRL_MPE);
4382 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4388 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4390 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4393 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4394 fctrl |= IXGBE_FCTRL_MPE;
4395 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4401 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4403 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4406 if (dev->data->promiscuous == 1)
4407 return 0; /* must remain in all_multicast mode */
4409 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4410 fctrl &= (~IXGBE_FCTRL_MPE);
4411 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4417 * It clears the interrupt causes and enables the interrupt.
4418 * It will be called once only during nic initialized.
4421 * Pointer to struct rte_eth_dev.
4423 * Enable or Disable.
4426 * - On success, zero.
4427 * - On failure, a negative value.
4430 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4432 struct ixgbe_interrupt *intr =
4433 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4435 ixgbe_dev_link_status_print(dev);
4437 intr->mask |= IXGBE_EICR_LSC;
4439 intr->mask &= ~IXGBE_EICR_LSC;
4445 * It clears the interrupt causes and enables the interrupt.
4446 * It will be called once only during nic initialized.
4449 * Pointer to struct rte_eth_dev.
4452 * - On success, zero.
4453 * - On failure, a negative value.
4456 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4458 struct ixgbe_interrupt *intr =
4459 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4461 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4467 * It clears the interrupt causes and enables the interrupt.
4468 * It will be called once only during nic initialized.
4471 * Pointer to struct rte_eth_dev.
4474 * - On success, zero.
4475 * - On failure, a negative value.
4478 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4480 struct ixgbe_interrupt *intr =
4481 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4483 intr->mask |= IXGBE_EICR_LINKSEC;
4489 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4492 * Pointer to struct rte_eth_dev.
4495 * - On success, zero.
4496 * - On failure, a negative value.
4499 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4502 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4503 struct ixgbe_interrupt *intr =
4504 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4506 /* clear all cause mask */
4507 ixgbe_disable_intr(hw);
4509 /* read-on-clear nic registers here */
4510 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4511 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4515 /* set flag for async link update */
4516 if (eicr & IXGBE_EICR_LSC)
4517 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4519 if (eicr & IXGBE_EICR_MAILBOX)
4520 intr->flags |= IXGBE_FLAG_MAILBOX;
4522 if (eicr & IXGBE_EICR_LINKSEC)
4523 intr->flags |= IXGBE_FLAG_MACSEC;
4525 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4526 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4527 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4528 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4534 * It gets and then prints the link status.
4537 * Pointer to struct rte_eth_dev.
4540 * - On success, zero.
4541 * - On failure, a negative value.
4544 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4546 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4547 struct rte_eth_link link;
4549 rte_eth_linkstatus_get(dev, &link);
4551 if (link.link_status) {
4552 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4553 (int)(dev->data->port_id),
4554 (unsigned)link.link_speed,
4555 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4556 "full-duplex" : "half-duplex");
4558 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4559 (int)(dev->data->port_id));
4561 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4562 pci_dev->addr.domain,
4564 pci_dev->addr.devid,
4565 pci_dev->addr.function);
4569 * It executes link_update after knowing an interrupt occurred.
4572 * Pointer to struct rte_eth_dev.
4575 * - On success, zero.
4576 * - On failure, a negative value.
4579 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4581 struct ixgbe_interrupt *intr =
4582 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4584 struct ixgbe_hw *hw =
4585 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4587 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4589 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4590 ixgbe_pf_mbx_process(dev);
4591 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4594 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4595 ixgbe_handle_lasi(hw);
4596 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4599 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4600 struct rte_eth_link link;
4602 /* get the link status before link update, for predicting later */
4603 rte_eth_linkstatus_get(dev, &link);
4605 ixgbe_dev_link_update(dev, 0);
4608 if (!link.link_status)
4609 /* handle it 1 sec later, wait it being stable */
4610 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4611 /* likely to down */
4613 /* handle it 4 sec later, wait it being stable */
4614 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4616 ixgbe_dev_link_status_print(dev);
4617 if (rte_eal_alarm_set(timeout * 1000,
4618 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4619 PMD_DRV_LOG(ERR, "Error setting alarm");
4621 /* remember original mask */
4622 intr->mask_original = intr->mask;
4623 /* only disable lsc interrupt */
4624 intr->mask &= ~IXGBE_EIMS_LSC;
4628 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4629 ixgbe_enable_intr(dev);
4635 * Interrupt handler which shall be registered for alarm callback for delayed
4636 * handling specific interrupt to wait for the stable nic state. As the
4637 * NIC interrupt state is not stable for ixgbe after link is just down,
4638 * it needs to wait 4 seconds to get the stable status.
4641 * Pointer to interrupt handle.
4643 * The address of parameter (struct rte_eth_dev *) regsitered before.
4649 ixgbe_dev_interrupt_delayed_handler(void *param)
4651 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4652 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4653 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4654 struct ixgbe_interrupt *intr =
4655 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4656 struct ixgbe_hw *hw =
4657 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4660 ixgbe_disable_intr(hw);
4662 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4663 if (eicr & IXGBE_EICR_MAILBOX)
4664 ixgbe_pf_mbx_process(dev);
4666 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4667 ixgbe_handle_lasi(hw);
4668 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4671 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4672 ixgbe_dev_link_update(dev, 0);
4673 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4674 ixgbe_dev_link_status_print(dev);
4675 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4679 if (intr->flags & IXGBE_FLAG_MACSEC) {
4680 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4682 intr->flags &= ~IXGBE_FLAG_MACSEC;
4685 /* restore original mask */
4686 intr->mask = intr->mask_original;
4687 intr->mask_original = 0;
4689 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4690 ixgbe_enable_intr(dev);
4691 rte_intr_ack(intr_handle);
4695 * Interrupt handler triggered by NIC for handling
4696 * specific interrupt.
4699 * Pointer to interrupt handle.
4701 * The address of parameter (struct rte_eth_dev *) regsitered before.
4707 ixgbe_dev_interrupt_handler(void *param)
4709 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4711 ixgbe_dev_interrupt_get_status(dev);
4712 ixgbe_dev_interrupt_action(dev);
4716 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4718 struct ixgbe_hw *hw;
4720 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4721 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4725 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4727 struct ixgbe_hw *hw;
4729 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4730 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4734 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4736 struct ixgbe_hw *hw;
4742 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4744 fc_conf->pause_time = hw->fc.pause_time;
4745 fc_conf->high_water = hw->fc.high_water[0];
4746 fc_conf->low_water = hw->fc.low_water[0];
4747 fc_conf->send_xon = hw->fc.send_xon;
4748 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4751 * Return rx_pause status according to actual setting of
4754 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4755 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4761 * Return tx_pause status according to actual setting of
4764 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4765 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4770 if (rx_pause && tx_pause)
4771 fc_conf->mode = RTE_FC_FULL;
4773 fc_conf->mode = RTE_FC_RX_PAUSE;
4775 fc_conf->mode = RTE_FC_TX_PAUSE;
4777 fc_conf->mode = RTE_FC_NONE;
4783 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4785 struct ixgbe_hw *hw;
4786 struct ixgbe_adapter *adapter = dev->data->dev_private;
4788 uint32_t rx_buf_size;
4789 uint32_t max_high_water;
4790 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4797 PMD_INIT_FUNC_TRACE();
4799 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4800 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4801 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4804 * At least reserve one Ethernet frame for watermark
4805 * high_water/low_water in kilo bytes for ixgbe
4807 max_high_water = (rx_buf_size -
4808 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4809 if ((fc_conf->high_water > max_high_water) ||
4810 (fc_conf->high_water < fc_conf->low_water)) {
4811 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4812 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4816 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4817 hw->fc.pause_time = fc_conf->pause_time;
4818 hw->fc.high_water[0] = fc_conf->high_water;
4819 hw->fc.low_water[0] = fc_conf->low_water;
4820 hw->fc.send_xon = fc_conf->send_xon;
4821 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4822 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4824 err = ixgbe_flow_ctrl_enable(dev, hw);
4826 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4833 * ixgbe_pfc_enable_generic - Enable flow control
4834 * @hw: pointer to hardware structure
4835 * @tc_num: traffic class number
4836 * Enable flow control according to the current settings.
4839 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4842 uint32_t mflcn_reg, fccfg_reg;
4844 uint32_t fcrtl, fcrth;
4848 /* Validate the water mark configuration */
4849 if (!hw->fc.pause_time) {
4850 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4854 /* Low water mark of zero causes XOFF floods */
4855 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4856 /* High/Low water can not be 0 */
4857 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4858 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4859 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4863 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4864 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4865 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4869 /* Negotiate the fc mode to use */
4870 ixgbe_fc_autoneg(hw);
4872 /* Disable any previous flow control settings */
4873 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4874 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4876 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4877 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4879 switch (hw->fc.current_mode) {
4882 * If the count of enabled RX Priority Flow control >1,
4883 * and the TX pause can not be disabled
4886 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4887 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4888 if (reg & IXGBE_FCRTH_FCEN)
4892 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4894 case ixgbe_fc_rx_pause:
4896 * Rx Flow control is enabled and Tx Flow control is
4897 * disabled by software override. Since there really
4898 * isn't a way to advertise that we are capable of RX
4899 * Pause ONLY, we will advertise that we support both
4900 * symmetric and asymmetric Rx PAUSE. Later, we will
4901 * disable the adapter's ability to send PAUSE frames.
4903 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4905 * If the count of enabled RX Priority Flow control >1,
4906 * and the TX pause can not be disabled
4909 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4910 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4911 if (reg & IXGBE_FCRTH_FCEN)
4915 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4917 case ixgbe_fc_tx_pause:
4919 * Tx Flow control is enabled, and Rx Flow control is
4920 * disabled by software override.
4922 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4925 /* Flow control (both Rx and Tx) is enabled by SW override. */
4926 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4927 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4930 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4931 ret_val = IXGBE_ERR_CONFIG;
4935 /* Set 802.3x based flow control settings. */
4936 mflcn_reg |= IXGBE_MFLCN_DPF;
4937 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4938 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4940 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4941 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4942 hw->fc.high_water[tc_num]) {
4943 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4944 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4945 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4947 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4949 * In order to prevent Tx hangs when the internal Tx
4950 * switch is enabled we must set the high water mark
4951 * to the maximum FCRTH value. This allows the Tx
4952 * switch to function even under heavy Rx workloads.
4954 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4956 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4958 /* Configure pause time (2 TCs per register) */
4959 reg = hw->fc.pause_time * 0x00010001;
4960 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4961 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4963 /* Configure flow control refresh threshold value */
4964 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4971 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4973 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4974 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4976 if (hw->mac.type != ixgbe_mac_82598EB) {
4977 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4983 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4986 uint32_t rx_buf_size;
4987 uint32_t max_high_water;
4989 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4990 struct ixgbe_hw *hw =
4991 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992 struct ixgbe_dcb_config *dcb_config =
4993 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4995 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
5002 PMD_INIT_FUNC_TRACE();
5004 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
5005 tc_num = map[pfc_conf->priority];
5006 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
5007 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
5009 * At least reserve one Ethernet frame for watermark
5010 * high_water/low_water in kilo bytes for ixgbe
5012 max_high_water = (rx_buf_size -
5013 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
5014 if ((pfc_conf->fc.high_water > max_high_water) ||
5015 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5016 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5017 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5021 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5022 hw->fc.pause_time = pfc_conf->fc.pause_time;
5023 hw->fc.send_xon = pfc_conf->fc.send_xon;
5024 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
5025 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5027 err = ixgbe_dcb_pfc_enable(dev, tc_num);
5029 /* Not negotiated is not an error case */
5030 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5033 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5038 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5039 struct rte_eth_rss_reta_entry64 *reta_conf,
5042 uint16_t i, sp_reta_size;
5045 uint16_t idx, shift;
5046 struct ixgbe_adapter *adapter = dev->data->dev_private;
5047 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5050 PMD_INIT_FUNC_TRACE();
5052 if (!ixgbe_rss_update_sp(hw->mac.type)) {
5053 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5058 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5059 if (reta_size != sp_reta_size) {
5060 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5061 "(%d) doesn't match the number hardware can supported "
5062 "(%d)", reta_size, sp_reta_size);
5066 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5067 idx = i / RTE_RETA_GROUP_SIZE;
5068 shift = i % RTE_RETA_GROUP_SIZE;
5069 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5073 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5074 if (mask == IXGBE_4_BIT_MASK)
5077 r = IXGBE_READ_REG(hw, reta_reg);
5078 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5079 if (mask & (0x1 << j))
5080 reta |= reta_conf[idx].reta[shift + j] <<
5083 reta |= r & (IXGBE_8_BIT_MASK <<
5086 IXGBE_WRITE_REG(hw, reta_reg, reta);
5088 adapter->rss_reta_updated = 1;
5094 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5095 struct rte_eth_rss_reta_entry64 *reta_conf,
5098 uint16_t i, sp_reta_size;
5101 uint16_t idx, shift;
5102 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5105 PMD_INIT_FUNC_TRACE();
5106 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5107 if (reta_size != sp_reta_size) {
5108 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5109 "(%d) doesn't match the number hardware can supported "
5110 "(%d)", reta_size, sp_reta_size);
5114 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5115 idx = i / RTE_RETA_GROUP_SIZE;
5116 shift = i % RTE_RETA_GROUP_SIZE;
5117 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5122 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5123 reta = IXGBE_READ_REG(hw, reta_reg);
5124 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5125 if (mask & (0x1 << j))
5126 reta_conf[idx].reta[shift + j] =
5127 ((reta >> (CHAR_BIT * j)) &
5136 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5137 uint32_t index, uint32_t pool)
5139 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140 uint32_t enable_addr = 1;
5142 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5147 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5149 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5151 ixgbe_clear_rar(hw, index);
5155 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5157 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5159 ixgbe_remove_rar(dev, 0);
5160 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5166 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5168 if (strcmp(dev->device->driver->name, drv->driver.name))
5175 is_ixgbe_supported(struct rte_eth_dev *dev)
5177 return is_device_supported(dev, &rte_ixgbe_pmd);
5181 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5185 struct ixgbe_hw *hw;
5186 struct rte_eth_dev_info dev_info;
5187 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5188 struct rte_eth_dev_data *dev_data = dev->data;
5191 ret = ixgbe_dev_info_get(dev, &dev_info);
5195 /* check that mtu is within the allowed range */
5196 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5199 /* If device is started, refuse mtu that requires the support of
5200 * scattered packets when this feature has not been enabled before.
5202 if (dev_data->dev_started && !dev_data->scattered_rx &&
5203 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5204 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5205 PMD_INIT_LOG(ERR, "Stop port first.");
5209 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5210 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5212 /* switch to jumbo mode if needed */
5213 if (frame_size > RTE_ETHER_MAX_LEN) {
5214 dev->data->dev_conf.rxmode.offloads |=
5215 DEV_RX_OFFLOAD_JUMBO_FRAME;
5216 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5218 dev->data->dev_conf.rxmode.offloads &=
5219 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5220 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5222 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5224 /* update max frame size */
5225 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5227 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5228 maxfrs &= 0x0000FFFF;
5229 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5230 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5236 * Virtual Function operations
5239 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5241 struct ixgbe_interrupt *intr =
5242 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5243 struct ixgbe_hw *hw =
5244 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5246 PMD_INIT_FUNC_TRACE();
5248 /* Clear interrupt mask to stop from interrupts being generated */
5249 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5251 IXGBE_WRITE_FLUSH(hw);
5253 /* Clear mask value. */
5258 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5260 struct ixgbe_interrupt *intr =
5261 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5262 struct ixgbe_hw *hw =
5263 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5265 PMD_INIT_FUNC_TRACE();
5267 /* VF enable interrupt autoclean */
5268 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5269 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5270 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5272 IXGBE_WRITE_FLUSH(hw);
5274 /* Save IXGBE_VTEIMS value to mask. */
5275 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5279 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5281 struct rte_eth_conf *conf = &dev->data->dev_conf;
5282 struct ixgbe_adapter *adapter = dev->data->dev_private;
5284 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5285 dev->data->port_id);
5287 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5288 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5291 * VF has no ability to enable/disable HW CRC
5292 * Keep the persistent behavior the same as Host PF
5294 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5295 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5296 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5297 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5300 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5301 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5302 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5307 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5308 * allocation or vector Rx preconditions we will reset it.
5310 adapter->rx_bulk_alloc_allowed = true;
5311 adapter->rx_vec_allowed = true;
5317 ixgbevf_dev_start(struct rte_eth_dev *dev)
5319 struct ixgbe_hw *hw =
5320 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5321 uint32_t intr_vector = 0;
5322 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5323 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5327 PMD_INIT_FUNC_TRACE();
5329 /* Stop the link setup handler before resetting the HW. */
5330 ixgbe_dev_wait_setup_link_complete(dev, 0);
5332 err = hw->mac.ops.reset_hw(hw);
5334 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5337 hw->mac.get_link_status = true;
5339 /* negotiate mailbox API version to use with the PF. */
5340 ixgbevf_negotiate_api(hw);
5342 ixgbevf_dev_tx_init(dev);
5344 /* This can fail when allocating mbufs for descriptor rings */
5345 err = ixgbevf_dev_rx_init(dev);
5347 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5348 ixgbe_dev_clear_queues(dev);
5353 ixgbevf_set_vfta_all(dev, 1);
5356 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5357 ETH_VLAN_EXTEND_MASK;
5358 err = ixgbevf_vlan_offload_config(dev, mask);
5360 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5361 ixgbe_dev_clear_queues(dev);
5365 ixgbevf_dev_rxtx_start(dev);
5367 /* check and configure queue intr-vector mapping */
5368 if (rte_intr_cap_multiple(intr_handle) &&
5369 dev->data->dev_conf.intr_conf.rxq) {
5370 /* According to datasheet, only vector 0/1/2 can be used,
5371 * now only one vector is used for Rx queue
5374 if (rte_intr_efd_enable(intr_handle, intr_vector))
5378 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5379 intr_handle->intr_vec =
5380 rte_zmalloc("intr_vec",
5381 dev->data->nb_rx_queues * sizeof(int), 0);
5382 if (intr_handle->intr_vec == NULL) {
5383 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5384 " intr_vec", dev->data->nb_rx_queues);
5388 ixgbevf_configure_msix(dev);
5390 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5391 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5392 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5393 * is not cleared, it will fail when following rte_intr_enable( ) tries
5394 * to map Rx queue interrupt to other VFIO vectors.
5395 * So clear uio/vfio intr/evevnfd first to avoid failure.
5397 rte_intr_disable(intr_handle);
5399 rte_intr_enable(intr_handle);
5401 /* Re-enable interrupt for VF */
5402 ixgbevf_intr_enable(dev);
5405 * Update link status right before return, because it may
5406 * start link configuration process in a separate thread.
5408 ixgbevf_dev_link_update(dev, 0);
5410 hw->adapter_stopped = false;
5416 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5418 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5419 struct ixgbe_adapter *adapter = dev->data->dev_private;
5420 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5421 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5423 if (hw->adapter_stopped)
5426 PMD_INIT_FUNC_TRACE();
5428 ixgbe_dev_wait_setup_link_complete(dev, 0);
5430 ixgbevf_intr_disable(dev);
5432 hw->adapter_stopped = 1;
5433 ixgbe_stop_adapter(hw);
5436 * Clear what we set, but we still keep shadow_vfta to
5437 * restore after device starts
5439 ixgbevf_set_vfta_all(dev, 0);
5441 /* Clear stored conf */
5442 dev->data->scattered_rx = 0;
5444 ixgbe_dev_clear_queues(dev);
5446 /* Clean datapath event and queue/vec mapping */
5447 rte_intr_efd_disable(intr_handle);
5448 if (intr_handle->intr_vec != NULL) {
5449 rte_free(intr_handle->intr_vec);
5450 intr_handle->intr_vec = NULL;
5453 adapter->rss_reta_updated = 0;
5457 ixgbevf_dev_close(struct rte_eth_dev *dev)
5459 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5460 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5461 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5463 PMD_INIT_FUNC_TRACE();
5467 ixgbevf_dev_stop(dev);
5469 ixgbe_dev_free_queues(dev);
5472 * Remove the VF MAC address ro ensure
5473 * that the VF traffic goes to the PF
5474 * after stop, close and detach of the VF
5476 ixgbevf_remove_mac_addr(dev, 0);
5478 dev->dev_ops = NULL;
5479 dev->rx_pkt_burst = NULL;
5480 dev->tx_pkt_burst = NULL;
5482 rte_intr_disable(intr_handle);
5483 rte_intr_callback_unregister(intr_handle,
5484 ixgbevf_dev_interrupt_handler, dev);
5491 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5495 ret = eth_ixgbevf_dev_uninit(dev);
5499 ret = eth_ixgbevf_dev_init(dev);
5504 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5506 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5507 struct ixgbe_vfta *shadow_vfta =
5508 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5509 int i = 0, j = 0, vfta = 0, mask = 1;
5511 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5512 vfta = shadow_vfta->vfta[i];
5515 for (j = 0; j < 32; j++) {
5517 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5527 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5529 struct ixgbe_hw *hw =
5530 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5531 struct ixgbe_vfta *shadow_vfta =
5532 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5533 uint32_t vid_idx = 0;
5534 uint32_t vid_bit = 0;
5537 PMD_INIT_FUNC_TRACE();
5539 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5540 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5542 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5545 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5546 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5548 /* Save what we set and retore it after device reset */
5550 shadow_vfta->vfta[vid_idx] |= vid_bit;
5552 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5558 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5560 struct ixgbe_hw *hw =
5561 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5564 PMD_INIT_FUNC_TRACE();
5566 if (queue >= hw->mac.max_rx_queues)
5569 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5571 ctrl |= IXGBE_RXDCTL_VME;
5573 ctrl &= ~IXGBE_RXDCTL_VME;
5574 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5576 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5580 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5582 struct ixgbe_rx_queue *rxq;
5586 /* VF function only support hw strip feature, others are not support */
5587 if (mask & ETH_VLAN_STRIP_MASK) {
5588 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5589 rxq = dev->data->rx_queues[i];
5590 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5591 ixgbevf_vlan_strip_queue_set(dev, i, on);
5599 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5601 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5603 ixgbevf_vlan_offload_config(dev, mask);
5609 ixgbe_vt_check(struct ixgbe_hw *hw)
5613 /* if Virtualization Technology is enabled */
5614 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5615 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5616 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5624 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5626 uint32_t vector = 0;
5628 switch (hw->mac.mc_filter_type) {
5629 case 0: /* use bits [47:36] of the address */
5630 vector = ((uc_addr->addr_bytes[4] >> 4) |
5631 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5633 case 1: /* use bits [46:35] of the address */
5634 vector = ((uc_addr->addr_bytes[4] >> 3) |
5635 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5637 case 2: /* use bits [45:34] of the address */
5638 vector = ((uc_addr->addr_bytes[4] >> 2) |
5639 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5641 case 3: /* use bits [43:32] of the address */
5642 vector = ((uc_addr->addr_bytes[4]) |
5643 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5645 default: /* Invalid mc_filter_type */
5649 /* vector can only be 12-bits or boundary will be exceeded */
5655 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5656 struct rte_ether_addr *mac_addr, uint8_t on)
5663 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5664 const uint32_t ixgbe_uta_bit_shift = 5;
5665 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5666 const uint32_t bit1 = 0x1;
5668 struct ixgbe_hw *hw =
5669 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5670 struct ixgbe_uta_info *uta_info =
5671 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5673 /* The UTA table only exists on 82599 hardware and newer */
5674 if (hw->mac.type < ixgbe_mac_82599EB)
5677 vector = ixgbe_uta_vector(hw, mac_addr);
5678 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5679 uta_shift = vector & ixgbe_uta_bit_mask;
5681 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5685 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5687 uta_info->uta_in_use++;
5688 reg_val |= (bit1 << uta_shift);
5689 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5691 uta_info->uta_in_use--;
5692 reg_val &= ~(bit1 << uta_shift);
5693 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5696 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5698 if (uta_info->uta_in_use > 0)
5699 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5700 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5702 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5708 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5711 struct ixgbe_hw *hw =
5712 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5713 struct ixgbe_uta_info *uta_info =
5714 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5716 /* The UTA table only exists on 82599 hardware and newer */
5717 if (hw->mac.type < ixgbe_mac_82599EB)
5721 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5722 uta_info->uta_shadow[i] = ~0;
5723 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5726 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5727 uta_info->uta_shadow[i] = 0;
5728 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5736 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5738 uint32_t new_val = orig_val;
5740 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5741 new_val |= IXGBE_VMOLR_AUPE;
5742 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5743 new_val |= IXGBE_VMOLR_ROMPE;
5744 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5745 new_val |= IXGBE_VMOLR_ROPE;
5746 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5747 new_val |= IXGBE_VMOLR_BAM;
5748 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5749 new_val |= IXGBE_VMOLR_MPE;
5754 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5755 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5756 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5757 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5758 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5759 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5760 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5763 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5764 struct rte_eth_mirror_conf *mirror_conf,
5765 uint8_t rule_id, uint8_t on)
5767 uint32_t mr_ctl, vlvf;
5768 uint32_t mp_lsb = 0;
5769 uint32_t mv_msb = 0;
5770 uint32_t mv_lsb = 0;
5771 uint32_t mp_msb = 0;
5774 uint64_t vlan_mask = 0;
5776 const uint8_t pool_mask_offset = 32;
5777 const uint8_t vlan_mask_offset = 32;
5778 const uint8_t dst_pool_offset = 8;
5779 const uint8_t rule_mr_offset = 4;
5780 const uint8_t mirror_rule_mask = 0x0F;
5782 struct ixgbe_mirror_info *mr_info =
5783 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5784 struct ixgbe_hw *hw =
5785 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5786 uint8_t mirror_type = 0;
5788 if (ixgbe_vt_check(hw) < 0)
5791 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5794 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5795 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5796 mirror_conf->rule_type);
5800 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5801 mirror_type |= IXGBE_MRCTL_VLME;
5802 /* Check if vlan id is valid and find conresponding VLAN ID
5805 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5806 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5807 /* search vlan id related pool vlan filter
5810 reg_index = ixgbe_find_vlvf_slot(
5812 mirror_conf->vlan.vlan_id[i],
5816 vlvf = IXGBE_READ_REG(hw,
5817 IXGBE_VLVF(reg_index));
5818 if ((vlvf & IXGBE_VLVF_VIEN) &&
5819 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5820 mirror_conf->vlan.vlan_id[i]))
5821 vlan_mask |= (1ULL << reg_index);
5828 mv_lsb = vlan_mask & 0xFFFFFFFF;
5829 mv_msb = vlan_mask >> vlan_mask_offset;
5831 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5832 mirror_conf->vlan.vlan_mask;
5833 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5834 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5835 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5836 mirror_conf->vlan.vlan_id[i];
5841 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5842 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5843 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5848 * if enable pool mirror, write related pool mask register,if disable
5849 * pool mirror, clear PFMRVM register
5851 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5852 mirror_type |= IXGBE_MRCTL_VPME;
5854 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5855 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5856 mr_info->mr_conf[rule_id].pool_mask =
5857 mirror_conf->pool_mask;
5862 mr_info->mr_conf[rule_id].pool_mask = 0;
5865 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5866 mirror_type |= IXGBE_MRCTL_UPME;
5867 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5868 mirror_type |= IXGBE_MRCTL_DPME;
5870 /* read mirror control register and recalculate it */
5871 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5874 mr_ctl |= mirror_type;
5875 mr_ctl &= mirror_rule_mask;
5876 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5878 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5881 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5882 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5884 /* write mirrror control register */
5885 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5887 /* write pool mirrror control register */
5888 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5889 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5890 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5893 /* write VLAN mirrror control register */
5894 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5895 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5896 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5904 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5907 uint32_t lsb_val = 0;
5908 uint32_t msb_val = 0;
5909 const uint8_t rule_mr_offset = 4;
5911 struct ixgbe_hw *hw =
5912 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5913 struct ixgbe_mirror_info *mr_info =
5914 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5916 if (ixgbe_vt_check(hw) < 0)
5919 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5922 memset(&mr_info->mr_conf[rule_id], 0,
5923 sizeof(struct rte_eth_mirror_conf));
5925 /* clear PFVMCTL register */
5926 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5928 /* clear pool mask register */
5929 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5930 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5932 /* clear vlan mask register */
5933 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5934 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5940 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5942 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5943 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5944 struct ixgbe_interrupt *intr =
5945 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5946 struct ixgbe_hw *hw =
5947 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5948 uint32_t vec = IXGBE_MISC_VEC_ID;
5950 if (rte_intr_allow_others(intr_handle))
5951 vec = IXGBE_RX_VEC_START;
5952 intr->mask |= (1 << vec);
5953 RTE_SET_USED(queue_id);
5954 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5956 rte_intr_ack(intr_handle);
5962 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5964 struct ixgbe_interrupt *intr =
5965 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5966 struct ixgbe_hw *hw =
5967 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5968 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5969 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5970 uint32_t vec = IXGBE_MISC_VEC_ID;
5972 if (rte_intr_allow_others(intr_handle))
5973 vec = IXGBE_RX_VEC_START;
5974 intr->mask &= ~(1 << vec);
5975 RTE_SET_USED(queue_id);
5976 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5982 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5984 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5985 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5987 struct ixgbe_hw *hw =
5988 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5989 struct ixgbe_interrupt *intr =
5990 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5992 if (queue_id < 16) {
5993 ixgbe_disable_intr(hw);
5994 intr->mask |= (1 << queue_id);
5995 ixgbe_enable_intr(dev);
5996 } else if (queue_id < 32) {
5997 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5998 mask &= (1 << queue_id);
5999 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6000 } else if (queue_id < 64) {
6001 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6002 mask &= (1 << (queue_id - 32));
6003 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6005 rte_intr_ack(intr_handle);
6011 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6014 struct ixgbe_hw *hw =
6015 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6016 struct ixgbe_interrupt *intr =
6017 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6019 if (queue_id < 16) {
6020 ixgbe_disable_intr(hw);
6021 intr->mask &= ~(1 << queue_id);
6022 ixgbe_enable_intr(dev);
6023 } else if (queue_id < 32) {
6024 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6025 mask &= ~(1 << queue_id);
6026 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6027 } else if (queue_id < 64) {
6028 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6029 mask &= ~(1 << (queue_id - 32));
6030 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6037 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6038 uint8_t queue, uint8_t msix_vector)
6042 if (direction == -1) {
6044 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6045 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6048 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6050 /* rx or tx cause */
6051 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6052 idx = ((16 * (queue & 1)) + (8 * direction));
6053 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6054 tmp &= ~(0xFF << idx);
6055 tmp |= (msix_vector << idx);
6056 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6061 * set the IVAR registers, mapping interrupt causes to vectors
6063 * pointer to ixgbe_hw struct
6065 * 0 for Rx, 1 for Tx, -1 for other causes
6067 * queue to map the corresponding interrupt to
6069 * the vector to map to the corresponding queue
6072 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6073 uint8_t queue, uint8_t msix_vector)
6077 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6078 if (hw->mac.type == ixgbe_mac_82598EB) {
6079 if (direction == -1)
6081 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6082 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6083 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6084 tmp |= (msix_vector << (8 * (queue & 0x3)));
6085 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6086 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6087 (hw->mac.type == ixgbe_mac_X540) ||
6088 (hw->mac.type == ixgbe_mac_X550) ||
6089 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6090 if (direction == -1) {
6092 idx = ((queue & 1) * 8);
6093 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6094 tmp &= ~(0xFF << idx);
6095 tmp |= (msix_vector << idx);
6096 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6098 /* rx or tx causes */
6099 idx = ((16 * (queue & 1)) + (8 * direction));
6100 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6101 tmp &= ~(0xFF << idx);
6102 tmp |= (msix_vector << idx);
6103 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6109 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6111 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6112 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6113 struct ixgbe_hw *hw =
6114 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6116 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6117 uint32_t base = IXGBE_MISC_VEC_ID;
6119 /* Configure VF other cause ivar */
6120 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6122 /* won't configure msix register if no mapping is done
6123 * between intr vector and event fd.
6125 if (!rte_intr_dp_is_en(intr_handle))
6128 if (rte_intr_allow_others(intr_handle)) {
6129 base = IXGBE_RX_VEC_START;
6130 vector_idx = IXGBE_RX_VEC_START;
6133 /* Configure all RX queues of VF */
6134 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6135 /* Force all queue use vector 0,
6136 * as IXGBE_VF_MAXMSIVECOTR = 1
6138 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6139 intr_handle->intr_vec[q_idx] = vector_idx;
6140 if (vector_idx < base + intr_handle->nb_efd - 1)
6144 /* As RX queue setting above show, all queues use the vector 0.
6145 * Set only the ITR value of IXGBE_MISC_VEC_ID.
6147 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6148 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6149 | IXGBE_EITR_CNT_WDIS);
6153 * Sets up the hardware to properly generate MSI-X interrupts
6155 * board private structure
6158 ixgbe_configure_msix(struct rte_eth_dev *dev)
6160 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6161 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6162 struct ixgbe_hw *hw =
6163 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6164 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6165 uint32_t vec = IXGBE_MISC_VEC_ID;
6169 /* won't configure msix register if no mapping is done
6170 * between intr vector and event fd
6171 * but if misx has been enabled already, need to configure
6172 * auto clean, auto mask and throttling.
6174 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6175 if (!rte_intr_dp_is_en(intr_handle) &&
6176 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6179 if (rte_intr_allow_others(intr_handle))
6180 vec = base = IXGBE_RX_VEC_START;
6182 /* setup GPIE for MSI-x mode */
6183 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6184 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6185 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6186 /* auto clearing and auto setting corresponding bits in EIMS
6187 * when MSI-X interrupt is triggered
6189 if (hw->mac.type == ixgbe_mac_82598EB) {
6190 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6192 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6193 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6195 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6197 /* Populate the IVAR table and set the ITR values to the
6198 * corresponding register.
6200 if (rte_intr_dp_is_en(intr_handle)) {
6201 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6203 /* by default, 1:1 mapping */
6204 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6205 intr_handle->intr_vec[queue_id] = vec;
6206 if (vec < base + intr_handle->nb_efd - 1)
6210 switch (hw->mac.type) {
6211 case ixgbe_mac_82598EB:
6212 ixgbe_set_ivar_map(hw, -1,
6213 IXGBE_IVAR_OTHER_CAUSES_INDEX,
6216 case ixgbe_mac_82599EB:
6217 case ixgbe_mac_X540:
6218 case ixgbe_mac_X550:
6219 case ixgbe_mac_X550EM_x:
6220 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6226 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6227 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6228 | IXGBE_EITR_CNT_WDIS);
6230 /* set up to autoclear timer, and the vectors */
6231 mask = IXGBE_EIMS_ENABLE_MASK;
6232 mask &= ~(IXGBE_EIMS_OTHER |
6233 IXGBE_EIMS_MAILBOX |
6236 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6240 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6241 uint16_t queue_idx, uint16_t tx_rate)
6243 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6244 struct rte_eth_rxmode *rxmode;
6245 uint32_t rf_dec, rf_int;
6247 uint16_t link_speed = dev->data->dev_link.link_speed;
6249 if (queue_idx >= hw->mac.max_tx_queues)
6253 /* Calculate the rate factor values to set */
6254 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6255 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6256 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6258 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6259 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6260 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6261 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6266 rxmode = &dev->data->dev_conf.rxmode;
6268 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6269 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6272 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6273 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6274 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6275 IXGBE_MMW_SIZE_JUMBO_FRAME);
6277 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6278 IXGBE_MMW_SIZE_DEFAULT);
6280 /* Set RTTBCNRC of queue X */
6281 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6282 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6283 IXGBE_WRITE_FLUSH(hw);
6289 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6290 __rte_unused uint32_t index,
6291 __rte_unused uint32_t pool)
6293 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6297 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6298 * operation. Trap this case to avoid exhausting the [very limited]
6299 * set of PF resources used to store VF MAC addresses.
6301 if (memcmp(hw->mac.perm_addr, mac_addr,
6302 sizeof(struct rte_ether_addr)) == 0)
6304 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6306 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6307 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6308 mac_addr->addr_bytes[0],
6309 mac_addr->addr_bytes[1],
6310 mac_addr->addr_bytes[2],
6311 mac_addr->addr_bytes[3],
6312 mac_addr->addr_bytes[4],
6313 mac_addr->addr_bytes[5],
6319 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6321 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6322 struct rte_ether_addr *perm_addr =
6323 (struct rte_ether_addr *)hw->mac.perm_addr;
6324 struct rte_ether_addr *mac_addr;
6329 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6330 * not support the deletion of a given MAC address.
6331 * Instead, it imposes to delete all MAC addresses, then to add again
6332 * all MAC addresses with the exception of the one to be deleted.
6334 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6337 * Add again all MAC addresses, with the exception of the deleted one
6338 * and of the permanent MAC address.
6340 for (i = 0, mac_addr = dev->data->mac_addrs;
6341 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6342 /* Skip the deleted MAC address */
6345 /* Skip NULL MAC addresses */
6346 if (rte_is_zero_ether_addr(mac_addr))
6348 /* Skip the permanent MAC address */
6349 if (memcmp(perm_addr, mac_addr,
6350 sizeof(struct rte_ether_addr)) == 0)
6352 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6355 "Adding again MAC address "
6356 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6358 mac_addr->addr_bytes[0],
6359 mac_addr->addr_bytes[1],
6360 mac_addr->addr_bytes[2],
6361 mac_addr->addr_bytes[3],
6362 mac_addr->addr_bytes[4],
6363 mac_addr->addr_bytes[5],
6369 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6370 struct rte_ether_addr *addr)
6372 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6374 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6380 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6381 struct rte_eth_syn_filter *filter,
6384 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6385 struct ixgbe_filter_info *filter_info =
6386 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6390 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6393 syn_info = filter_info->syn_info;
6396 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6398 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6399 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6401 if (filter->hig_pri)
6402 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6404 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6406 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6407 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6409 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6412 filter_info->syn_info = synqf;
6413 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6414 IXGBE_WRITE_FLUSH(hw);
6419 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6420 struct rte_eth_syn_filter *filter)
6422 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6423 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6425 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6426 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6427 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6434 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6435 enum rte_filter_op filter_op,
6438 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6441 MAC_TYPE_FILTER_SUP(hw->mac.type);
6443 if (filter_op == RTE_ETH_FILTER_NOP)
6447 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6452 switch (filter_op) {
6453 case RTE_ETH_FILTER_ADD:
6454 ret = ixgbe_syn_filter_set(dev,
6455 (struct rte_eth_syn_filter *)arg,
6458 case RTE_ETH_FILTER_DELETE:
6459 ret = ixgbe_syn_filter_set(dev,
6460 (struct rte_eth_syn_filter *)arg,
6463 case RTE_ETH_FILTER_GET:
6464 ret = ixgbe_syn_filter_get(dev,
6465 (struct rte_eth_syn_filter *)arg);
6468 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6477 static inline enum ixgbe_5tuple_protocol
6478 convert_protocol_type(uint8_t protocol_value)
6480 if (protocol_value == IPPROTO_TCP)
6481 return IXGBE_FILTER_PROTOCOL_TCP;
6482 else if (protocol_value == IPPROTO_UDP)
6483 return IXGBE_FILTER_PROTOCOL_UDP;
6484 else if (protocol_value == IPPROTO_SCTP)
6485 return IXGBE_FILTER_PROTOCOL_SCTP;
6487 return IXGBE_FILTER_PROTOCOL_NONE;
6490 /* inject a 5-tuple filter to HW */
6492 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6493 struct ixgbe_5tuple_filter *filter)
6495 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6497 uint32_t ftqf, sdpqf;
6498 uint32_t l34timir = 0;
6499 uint8_t mask = 0xff;
6503 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6504 IXGBE_SDPQF_DSTPORT_SHIFT);
6505 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6507 ftqf = (uint32_t)(filter->filter_info.proto &
6508 IXGBE_FTQF_PROTOCOL_MASK);
6509 ftqf |= (uint32_t)((filter->filter_info.priority &
6510 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6511 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6512 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6513 if (filter->filter_info.dst_ip_mask == 0)
6514 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6515 if (filter->filter_info.src_port_mask == 0)
6516 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6517 if (filter->filter_info.dst_port_mask == 0)
6518 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6519 if (filter->filter_info.proto_mask == 0)
6520 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6521 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6522 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6523 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6525 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6526 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6527 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6528 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6530 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6531 l34timir |= (uint32_t)(filter->queue <<
6532 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6533 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6537 * add a 5tuple filter
6540 * dev: Pointer to struct rte_eth_dev.
6541 * index: the index the filter allocates.
6542 * filter: ponter to the filter that will be added.
6543 * rx_queue: the queue id the filter assigned to.
6546 * - On success, zero.
6547 * - On failure, a negative value.
6550 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6551 struct ixgbe_5tuple_filter *filter)
6553 struct ixgbe_filter_info *filter_info =
6554 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6558 * look for an unused 5tuple filter index,
6559 * and insert the filter to list.
6561 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6562 idx = i / (sizeof(uint32_t) * NBBY);
6563 shift = i % (sizeof(uint32_t) * NBBY);
6564 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6565 filter_info->fivetuple_mask[idx] |= 1 << shift;
6567 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6573 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6574 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6578 ixgbe_inject_5tuple_filter(dev, filter);
6584 * remove a 5tuple filter
6587 * dev: Pointer to struct rte_eth_dev.
6588 * filter: the pointer of the filter will be removed.
6591 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6592 struct ixgbe_5tuple_filter *filter)
6594 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6595 struct ixgbe_filter_info *filter_info =
6596 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6597 uint16_t index = filter->index;
6599 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6600 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6601 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6604 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6605 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6606 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6607 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6608 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6612 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6614 struct ixgbe_hw *hw;
6615 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6616 struct rte_eth_dev_data *dev_data = dev->data;
6618 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6620 if (mtu < RTE_ETHER_MIN_MTU ||
6621 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6624 /* If device is started, refuse mtu that requires the support of
6625 * scattered packets when this feature has not been enabled before.
6627 if (dev_data->dev_started && !dev_data->scattered_rx &&
6628 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6629 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6630 PMD_INIT_LOG(ERR, "Stop port first.");
6635 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6636 * request of the version 2.0 of the mailbox API.
6637 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6638 * of the mailbox API.
6639 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6640 * prior to 3.11.33 which contains the following change:
6641 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6643 ixgbevf_rlpml_set_vf(hw, max_frame);
6645 /* update max frame size */
6646 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6650 static inline struct ixgbe_5tuple_filter *
6651 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6652 struct ixgbe_5tuple_filter_info *key)
6654 struct ixgbe_5tuple_filter *it;
6656 TAILQ_FOREACH(it, filter_list, entries) {
6657 if (memcmp(key, &it->filter_info,
6658 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6665 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6667 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6668 struct ixgbe_5tuple_filter_info *filter_info)
6670 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6671 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6672 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6675 switch (filter->dst_ip_mask) {
6677 filter_info->dst_ip_mask = 0;
6678 filter_info->dst_ip = filter->dst_ip;
6681 filter_info->dst_ip_mask = 1;
6684 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6688 switch (filter->src_ip_mask) {
6690 filter_info->src_ip_mask = 0;
6691 filter_info->src_ip = filter->src_ip;
6694 filter_info->src_ip_mask = 1;
6697 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6701 switch (filter->dst_port_mask) {
6703 filter_info->dst_port_mask = 0;
6704 filter_info->dst_port = filter->dst_port;
6707 filter_info->dst_port_mask = 1;
6710 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6714 switch (filter->src_port_mask) {
6716 filter_info->src_port_mask = 0;
6717 filter_info->src_port = filter->src_port;
6720 filter_info->src_port_mask = 1;
6723 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6727 switch (filter->proto_mask) {
6729 filter_info->proto_mask = 0;
6730 filter_info->proto =
6731 convert_protocol_type(filter->proto);
6734 filter_info->proto_mask = 1;
6737 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6741 filter_info->priority = (uint8_t)filter->priority;
6746 * add or delete a ntuple filter
6749 * dev: Pointer to struct rte_eth_dev.
6750 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6751 * add: if true, add filter, if false, remove filter
6754 * - On success, zero.
6755 * - On failure, a negative value.
6758 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6759 struct rte_eth_ntuple_filter *ntuple_filter,
6762 struct ixgbe_filter_info *filter_info =
6763 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6764 struct ixgbe_5tuple_filter_info filter_5tuple;
6765 struct ixgbe_5tuple_filter *filter;
6768 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6769 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6773 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6774 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6778 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6780 if (filter != NULL && add) {
6781 PMD_DRV_LOG(ERR, "filter exists.");
6784 if (filter == NULL && !add) {
6785 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6790 filter = rte_zmalloc("ixgbe_5tuple_filter",
6791 sizeof(struct ixgbe_5tuple_filter), 0);
6794 rte_memcpy(&filter->filter_info,
6796 sizeof(struct ixgbe_5tuple_filter_info));
6797 filter->queue = ntuple_filter->queue;
6798 ret = ixgbe_add_5tuple_filter(dev, filter);
6804 ixgbe_remove_5tuple_filter(dev, filter);
6810 * get a ntuple filter
6813 * dev: Pointer to struct rte_eth_dev.
6814 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6817 * - On success, zero.
6818 * - On failure, a negative value.
6821 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6822 struct rte_eth_ntuple_filter *ntuple_filter)
6824 struct ixgbe_filter_info *filter_info =
6825 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6826 struct ixgbe_5tuple_filter_info filter_5tuple;
6827 struct ixgbe_5tuple_filter *filter;
6830 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6831 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6835 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6836 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6840 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6842 if (filter == NULL) {
6843 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6846 ntuple_filter->queue = filter->queue;
6851 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6852 * @dev: pointer to rte_eth_dev structure
6853 * @filter_op:operation will be taken.
6854 * @arg: a pointer to specific structure corresponding to the filter_op
6857 * - On success, zero.
6858 * - On failure, a negative value.
6861 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6862 enum rte_filter_op filter_op,
6865 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6868 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6870 if (filter_op == RTE_ETH_FILTER_NOP)
6874 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6879 switch (filter_op) {
6880 case RTE_ETH_FILTER_ADD:
6881 ret = ixgbe_add_del_ntuple_filter(dev,
6882 (struct rte_eth_ntuple_filter *)arg,
6885 case RTE_ETH_FILTER_DELETE:
6886 ret = ixgbe_add_del_ntuple_filter(dev,
6887 (struct rte_eth_ntuple_filter *)arg,
6890 case RTE_ETH_FILTER_GET:
6891 ret = ixgbe_get_ntuple_filter(dev,
6892 (struct rte_eth_ntuple_filter *)arg);
6895 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6903 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6904 struct rte_eth_ethertype_filter *filter,
6907 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6908 struct ixgbe_filter_info *filter_info =
6909 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6913 struct ixgbe_ethertype_filter ethertype_filter;
6915 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6918 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6919 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6920 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6921 " ethertype filter.", filter->ether_type);
6925 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6926 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6929 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6930 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6934 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6935 if (ret >= 0 && add) {
6936 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6937 filter->ether_type);
6940 if (ret < 0 && !add) {
6941 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6942 filter->ether_type);
6947 etqf = IXGBE_ETQF_FILTER_EN;
6948 etqf |= (uint32_t)filter->ether_type;
6949 etqs |= (uint32_t)((filter->queue <<
6950 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6951 IXGBE_ETQS_RX_QUEUE);
6952 etqs |= IXGBE_ETQS_QUEUE_EN;
6954 ethertype_filter.ethertype = filter->ether_type;
6955 ethertype_filter.etqf = etqf;
6956 ethertype_filter.etqs = etqs;
6957 ethertype_filter.conf = FALSE;
6958 ret = ixgbe_ethertype_filter_insert(filter_info,
6961 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6965 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6969 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6970 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6971 IXGBE_WRITE_FLUSH(hw);
6977 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6978 struct rte_eth_ethertype_filter *filter)
6980 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6981 struct ixgbe_filter_info *filter_info =
6982 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6983 uint32_t etqf, etqs;
6986 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6988 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6989 filter->ether_type);
6993 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6994 if (etqf & IXGBE_ETQF_FILTER_EN) {
6995 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6996 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6998 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6999 IXGBE_ETQS_RX_QUEUE_SHIFT;
7006 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
7007 * @dev: pointer to rte_eth_dev structure
7008 * @filter_op:operation will be taken.
7009 * @arg: a pointer to specific structure corresponding to the filter_op
7012 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7013 enum rte_filter_op filter_op,
7016 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7019 MAC_TYPE_FILTER_SUP(hw->mac.type);
7021 if (filter_op == RTE_ETH_FILTER_NOP)
7025 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7030 switch (filter_op) {
7031 case RTE_ETH_FILTER_ADD:
7032 ret = ixgbe_add_del_ethertype_filter(dev,
7033 (struct rte_eth_ethertype_filter *)arg,
7036 case RTE_ETH_FILTER_DELETE:
7037 ret = ixgbe_add_del_ethertype_filter(dev,
7038 (struct rte_eth_ethertype_filter *)arg,
7041 case RTE_ETH_FILTER_GET:
7042 ret = ixgbe_get_ethertype_filter(dev,
7043 (struct rte_eth_ethertype_filter *)arg);
7046 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7054 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7055 enum rte_filter_type filter_type,
7056 enum rte_filter_op filter_op,
7061 switch (filter_type) {
7062 case RTE_ETH_FILTER_NTUPLE:
7063 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7065 case RTE_ETH_FILTER_ETHERTYPE:
7066 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7068 case RTE_ETH_FILTER_SYN:
7069 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7071 case RTE_ETH_FILTER_FDIR:
7072 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7074 case RTE_ETH_FILTER_L2_TUNNEL:
7075 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7077 case RTE_ETH_FILTER_GENERIC:
7078 if (filter_op != RTE_ETH_FILTER_GET)
7080 *(const void **)arg = &ixgbe_flow_ops;
7083 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7093 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7094 u8 **mc_addr_ptr, u32 *vmdq)
7099 mc_addr = *mc_addr_ptr;
7100 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7105 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7106 struct rte_ether_addr *mc_addr_set,
7107 uint32_t nb_mc_addr)
7109 struct ixgbe_hw *hw;
7112 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7113 mc_addr_list = (u8 *)mc_addr_set;
7114 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7115 ixgbe_dev_addr_list_itr, TRUE);
7119 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122 uint64_t systime_cycles;
7124 switch (hw->mac.type) {
7125 case ixgbe_mac_X550:
7126 case ixgbe_mac_X550EM_x:
7127 case ixgbe_mac_X550EM_a:
7128 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7129 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7130 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7134 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7135 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7139 return systime_cycles;
7143 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7145 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7146 uint64_t rx_tstamp_cycles;
7148 switch (hw->mac.type) {
7149 case ixgbe_mac_X550:
7150 case ixgbe_mac_X550EM_x:
7151 case ixgbe_mac_X550EM_a:
7152 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7153 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7154 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7158 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7159 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7160 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7164 return rx_tstamp_cycles;
7168 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7170 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7171 uint64_t tx_tstamp_cycles;
7173 switch (hw->mac.type) {
7174 case ixgbe_mac_X550:
7175 case ixgbe_mac_X550EM_x:
7176 case ixgbe_mac_X550EM_a:
7177 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7178 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7179 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7183 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7184 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7185 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7189 return tx_tstamp_cycles;
7193 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7195 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7196 struct ixgbe_adapter *adapter = dev->data->dev_private;
7197 struct rte_eth_link link;
7198 uint32_t incval = 0;
7201 /* Get current link speed. */
7202 ixgbe_dev_link_update(dev, 1);
7203 rte_eth_linkstatus_get(dev, &link);
7205 switch (link.link_speed) {
7206 case ETH_SPEED_NUM_100M:
7207 incval = IXGBE_INCVAL_100;
7208 shift = IXGBE_INCVAL_SHIFT_100;
7210 case ETH_SPEED_NUM_1G:
7211 incval = IXGBE_INCVAL_1GB;
7212 shift = IXGBE_INCVAL_SHIFT_1GB;
7214 case ETH_SPEED_NUM_10G:
7216 incval = IXGBE_INCVAL_10GB;
7217 shift = IXGBE_INCVAL_SHIFT_10GB;
7221 switch (hw->mac.type) {
7222 case ixgbe_mac_X550:
7223 case ixgbe_mac_X550EM_x:
7224 case ixgbe_mac_X550EM_a:
7225 /* Independent of link speed. */
7227 /* Cycles read will be interpreted as ns. */
7230 case ixgbe_mac_X540:
7231 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7233 case ixgbe_mac_82599EB:
7234 incval >>= IXGBE_INCVAL_SHIFT_82599;
7235 shift -= IXGBE_INCVAL_SHIFT_82599;
7236 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7237 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7240 /* Not supported. */
7244 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7245 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7246 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7248 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7249 adapter->systime_tc.cc_shift = shift;
7250 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7252 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7253 adapter->rx_tstamp_tc.cc_shift = shift;
7254 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7256 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7257 adapter->tx_tstamp_tc.cc_shift = shift;
7258 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7262 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7264 struct ixgbe_adapter *adapter = dev->data->dev_private;
7266 adapter->systime_tc.nsec += delta;
7267 adapter->rx_tstamp_tc.nsec += delta;
7268 adapter->tx_tstamp_tc.nsec += delta;
7274 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7277 struct ixgbe_adapter *adapter = dev->data->dev_private;
7279 ns = rte_timespec_to_ns(ts);
7280 /* Set the timecounters to a new value. */
7281 adapter->systime_tc.nsec = ns;
7282 adapter->rx_tstamp_tc.nsec = ns;
7283 adapter->tx_tstamp_tc.nsec = ns;
7289 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7291 uint64_t ns, systime_cycles;
7292 struct ixgbe_adapter *adapter = dev->data->dev_private;
7294 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7295 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7296 *ts = rte_ns_to_timespec(ns);
7302 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7304 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7308 /* Stop the timesync system time. */
7309 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7310 /* Reset the timesync system time value. */
7311 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7312 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7314 /* Enable system time for platforms where it isn't on by default. */
7315 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7316 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7317 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7319 ixgbe_start_timecounters(dev);
7321 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7322 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7323 (RTE_ETHER_TYPE_1588 |
7324 IXGBE_ETQF_FILTER_EN |
7327 /* Enable timestamping of received PTP packets. */
7328 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7329 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7330 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7332 /* Enable timestamping of transmitted PTP packets. */
7333 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7334 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7335 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7337 IXGBE_WRITE_FLUSH(hw);
7343 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7345 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7348 /* Disable timestamping of transmitted PTP packets. */
7349 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7350 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7351 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7353 /* Disable timestamping of received PTP packets. */
7354 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7355 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7356 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7358 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7359 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7361 /* Stop incrementating the System Time registers. */
7362 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7368 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7369 struct timespec *timestamp,
7370 uint32_t flags __rte_unused)
7372 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7373 struct ixgbe_adapter *adapter = dev->data->dev_private;
7374 uint32_t tsync_rxctl;
7375 uint64_t rx_tstamp_cycles;
7378 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7379 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7382 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7383 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7384 *timestamp = rte_ns_to_timespec(ns);
7390 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7391 struct timespec *timestamp)
7393 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7394 struct ixgbe_adapter *adapter = dev->data->dev_private;
7395 uint32_t tsync_txctl;
7396 uint64_t tx_tstamp_cycles;
7399 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7400 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7403 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7404 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7405 *timestamp = rte_ns_to_timespec(ns);
7411 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7413 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7416 const struct reg_info *reg_group;
7417 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7418 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7420 while ((reg_group = reg_set[g_ind++]))
7421 count += ixgbe_regs_group_count(reg_group);
7427 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7431 const struct reg_info *reg_group;
7433 while ((reg_group = ixgbevf_regs[g_ind++]))
7434 count += ixgbe_regs_group_count(reg_group);
7440 ixgbe_get_regs(struct rte_eth_dev *dev,
7441 struct rte_dev_reg_info *regs)
7443 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7444 uint32_t *data = regs->data;
7447 const struct reg_info *reg_group;
7448 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7449 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7452 regs->length = ixgbe_get_reg_length(dev);
7453 regs->width = sizeof(uint32_t);
7457 /* Support only full register dump */
7458 if ((regs->length == 0) ||
7459 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7460 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7462 while ((reg_group = reg_set[g_ind++]))
7463 count += ixgbe_read_regs_group(dev, &data[count],
7472 ixgbevf_get_regs(struct rte_eth_dev *dev,
7473 struct rte_dev_reg_info *regs)
7475 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7476 uint32_t *data = regs->data;
7479 const struct reg_info *reg_group;
7482 regs->length = ixgbevf_get_reg_length(dev);
7483 regs->width = sizeof(uint32_t);
7487 /* Support only full register dump */
7488 if ((regs->length == 0) ||
7489 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7490 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7492 while ((reg_group = ixgbevf_regs[g_ind++]))
7493 count += ixgbe_read_regs_group(dev, &data[count],
7502 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7504 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7506 /* Return unit is byte count */
7507 return hw->eeprom.word_size * 2;
7511 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7512 struct rte_dev_eeprom_info *in_eeprom)
7514 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7515 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7516 uint16_t *data = in_eeprom->data;
7519 first = in_eeprom->offset >> 1;
7520 length = in_eeprom->length >> 1;
7521 if ((first > hw->eeprom.word_size) ||
7522 ((first + length) > hw->eeprom.word_size))
7525 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7527 return eeprom->ops.read_buffer(hw, first, length, data);
7531 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7532 struct rte_dev_eeprom_info *in_eeprom)
7534 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7535 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7536 uint16_t *data = in_eeprom->data;
7539 first = in_eeprom->offset >> 1;
7540 length = in_eeprom->length >> 1;
7541 if ((first > hw->eeprom.word_size) ||
7542 ((first + length) > hw->eeprom.word_size))
7545 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7547 return eeprom->ops.write_buffer(hw, first, length, data);
7551 ixgbe_get_module_info(struct rte_eth_dev *dev,
7552 struct rte_eth_dev_module_info *modinfo)
7554 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7556 uint8_t sff8472_rev, addr_mode;
7557 bool page_swap = false;
7559 /* Check whether we support SFF-8472 or not */
7560 status = hw->phy.ops.read_i2c_eeprom(hw,
7561 IXGBE_SFF_SFF_8472_COMP,
7566 /* addressing mode is not supported */
7567 status = hw->phy.ops.read_i2c_eeprom(hw,
7568 IXGBE_SFF_SFF_8472_SWAP,
7573 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7575 "Address change required to access page 0xA2, "
7576 "but not supported. Please report the module "
7577 "type to the driver maintainers.");
7581 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7582 /* We have a SFP, but it does not support SFF-8472 */
7583 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7584 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7586 /* We have a SFP which supports a revision of SFF-8472. */
7587 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7588 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7595 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7596 struct rte_dev_eeprom_info *info)
7598 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7599 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7600 uint8_t databyte = 0xFF;
7601 uint8_t *data = info->data;
7604 if (info->length == 0)
7607 for (i = info->offset; i < info->offset + info->length; i++) {
7608 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7609 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7611 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7616 data[i - info->offset] = databyte;
7623 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7625 case ixgbe_mac_X550:
7626 case ixgbe_mac_X550EM_x:
7627 case ixgbe_mac_X550EM_a:
7628 return ETH_RSS_RETA_SIZE_512;
7629 case ixgbe_mac_X550_vf:
7630 case ixgbe_mac_X550EM_x_vf:
7631 case ixgbe_mac_X550EM_a_vf:
7632 return ETH_RSS_RETA_SIZE_64;
7633 case ixgbe_mac_X540_vf:
7634 case ixgbe_mac_82599_vf:
7637 return ETH_RSS_RETA_SIZE_128;
7642 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7644 case ixgbe_mac_X550:
7645 case ixgbe_mac_X550EM_x:
7646 case ixgbe_mac_X550EM_a:
7647 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7648 return IXGBE_RETA(reta_idx >> 2);
7650 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7651 case ixgbe_mac_X550_vf:
7652 case ixgbe_mac_X550EM_x_vf:
7653 case ixgbe_mac_X550EM_a_vf:
7654 return IXGBE_VFRETA(reta_idx >> 2);
7656 return IXGBE_RETA(reta_idx >> 2);
7661 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7663 case ixgbe_mac_X550_vf:
7664 case ixgbe_mac_X550EM_x_vf:
7665 case ixgbe_mac_X550EM_a_vf:
7666 return IXGBE_VFMRQC;
7673 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7675 case ixgbe_mac_X550_vf:
7676 case ixgbe_mac_X550EM_x_vf:
7677 case ixgbe_mac_X550EM_a_vf:
7678 return IXGBE_VFRSSRK(i);
7680 return IXGBE_RSSRK(i);
7685 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7687 case ixgbe_mac_82599_vf:
7688 case ixgbe_mac_X540_vf:
7696 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7697 struct rte_eth_dcb_info *dcb_info)
7699 struct ixgbe_dcb_config *dcb_config =
7700 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7701 struct ixgbe_dcb_tc_config *tc;
7702 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7706 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7707 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7709 dcb_info->nb_tcs = 1;
7711 tc_queue = &dcb_info->tc_queue;
7712 nb_tcs = dcb_info->nb_tcs;
7714 if (dcb_config->vt_mode) { /* vt is enabled*/
7715 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7716 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7717 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7718 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7719 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7720 for (j = 0; j < nb_tcs; j++) {
7721 tc_queue->tc_rxq[0][j].base = j;
7722 tc_queue->tc_rxq[0][j].nb_queue = 1;
7723 tc_queue->tc_txq[0][j].base = j;
7724 tc_queue->tc_txq[0][j].nb_queue = 1;
7727 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7728 for (j = 0; j < nb_tcs; j++) {
7729 tc_queue->tc_rxq[i][j].base =
7731 tc_queue->tc_rxq[i][j].nb_queue = 1;
7732 tc_queue->tc_txq[i][j].base =
7734 tc_queue->tc_txq[i][j].nb_queue = 1;
7738 } else { /* vt is disabled*/
7739 struct rte_eth_dcb_rx_conf *rx_conf =
7740 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7741 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7742 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7743 if (dcb_info->nb_tcs == ETH_4_TCS) {
7744 for (i = 0; i < dcb_info->nb_tcs; i++) {
7745 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7746 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7748 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7749 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7750 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7751 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7752 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7753 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7754 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7755 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7756 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7757 for (i = 0; i < dcb_info->nb_tcs; i++) {
7758 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7759 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7761 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7762 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7763 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7764 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7765 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7766 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7767 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7768 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7769 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7770 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7771 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7772 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7773 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7774 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7775 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7776 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7779 for (i = 0; i < dcb_info->nb_tcs; i++) {
7780 tc = &dcb_config->tc_config[i];
7781 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7786 /* Update e-tag ether type */
7788 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7789 uint16_t ether_type)
7791 uint32_t etag_etype;
7793 if (hw->mac.type != ixgbe_mac_X550 &&
7794 hw->mac.type != ixgbe_mac_X550EM_x &&
7795 hw->mac.type != ixgbe_mac_X550EM_a) {
7799 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7800 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7801 etag_etype |= ether_type;
7802 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7803 IXGBE_WRITE_FLUSH(hw);
7808 /* Config l2 tunnel ether type */
7810 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7811 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7814 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7815 struct ixgbe_l2_tn_info *l2_tn_info =
7816 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7818 if (l2_tunnel == NULL)
7821 switch (l2_tunnel->l2_tunnel_type) {
7822 case RTE_L2_TUNNEL_TYPE_E_TAG:
7823 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7824 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7827 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7835 /* Enable e-tag tunnel */
7837 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7839 uint32_t etag_etype;
7841 if (hw->mac.type != ixgbe_mac_X550 &&
7842 hw->mac.type != ixgbe_mac_X550EM_x &&
7843 hw->mac.type != ixgbe_mac_X550EM_a) {
7847 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7848 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7849 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7850 IXGBE_WRITE_FLUSH(hw);
7855 /* Enable l2 tunnel */
7857 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7858 enum rte_eth_tunnel_type l2_tunnel_type)
7861 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7862 struct ixgbe_l2_tn_info *l2_tn_info =
7863 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7865 switch (l2_tunnel_type) {
7866 case RTE_L2_TUNNEL_TYPE_E_TAG:
7867 l2_tn_info->e_tag_en = TRUE;
7868 ret = ixgbe_e_tag_enable(hw);
7871 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7879 /* Disable e-tag tunnel */
7881 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7883 uint32_t etag_etype;
7885 if (hw->mac.type != ixgbe_mac_X550 &&
7886 hw->mac.type != ixgbe_mac_X550EM_x &&
7887 hw->mac.type != ixgbe_mac_X550EM_a) {
7891 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7892 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7893 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7894 IXGBE_WRITE_FLUSH(hw);
7899 /* Disable l2 tunnel */
7901 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7902 enum rte_eth_tunnel_type l2_tunnel_type)
7905 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7906 struct ixgbe_l2_tn_info *l2_tn_info =
7907 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7909 switch (l2_tunnel_type) {
7910 case RTE_L2_TUNNEL_TYPE_E_TAG:
7911 l2_tn_info->e_tag_en = FALSE;
7912 ret = ixgbe_e_tag_disable(hw);
7915 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7924 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7925 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7928 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7929 uint32_t i, rar_entries;
7930 uint32_t rar_low, rar_high;
7932 if (hw->mac.type != ixgbe_mac_X550 &&
7933 hw->mac.type != ixgbe_mac_X550EM_x &&
7934 hw->mac.type != ixgbe_mac_X550EM_a) {
7938 rar_entries = ixgbe_get_num_rx_addrs(hw);
7940 for (i = 1; i < rar_entries; i++) {
7941 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7942 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7943 if ((rar_high & IXGBE_RAH_AV) &&
7944 (rar_high & IXGBE_RAH_ADTYPE) &&
7945 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7946 l2_tunnel->tunnel_id)) {
7947 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7948 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7950 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7960 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7961 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7964 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7965 uint32_t i, rar_entries;
7966 uint32_t rar_low, rar_high;
7968 if (hw->mac.type != ixgbe_mac_X550 &&
7969 hw->mac.type != ixgbe_mac_X550EM_x &&
7970 hw->mac.type != ixgbe_mac_X550EM_a) {
7974 /* One entry for one tunnel. Try to remove potential existing entry. */
7975 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7977 rar_entries = ixgbe_get_num_rx_addrs(hw);
7979 for (i = 1; i < rar_entries; i++) {
7980 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7981 if (rar_high & IXGBE_RAH_AV) {
7984 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7985 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7986 rar_low = l2_tunnel->tunnel_id;
7988 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7989 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7995 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7996 " Please remove a rule before adding a new one.");
8000 static inline struct ixgbe_l2_tn_filter *
8001 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
8002 struct ixgbe_l2_tn_key *key)
8006 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
8010 return l2_tn_info->hash_map[ret];
8014 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8015 struct ixgbe_l2_tn_filter *l2_tn_filter)
8019 ret = rte_hash_add_key(l2_tn_info->hash_handle,
8020 &l2_tn_filter->key);
8024 "Failed to insert L2 tunnel filter"
8025 " to hash table %d!",
8030 l2_tn_info->hash_map[ret] = l2_tn_filter;
8032 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8038 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8039 struct ixgbe_l2_tn_key *key)
8042 struct ixgbe_l2_tn_filter *l2_tn_filter;
8044 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8048 "No such L2 tunnel filter to delete %d!",
8053 l2_tn_filter = l2_tn_info->hash_map[ret];
8054 l2_tn_info->hash_map[ret] = NULL;
8056 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8057 rte_free(l2_tn_filter);
8062 /* Add l2 tunnel filter */
8064 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8065 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8069 struct ixgbe_l2_tn_info *l2_tn_info =
8070 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8071 struct ixgbe_l2_tn_key key;
8072 struct ixgbe_l2_tn_filter *node;
8075 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8076 key.tn_id = l2_tunnel->tunnel_id;
8078 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8082 "The L2 tunnel filter already exists!");
8086 node = rte_zmalloc("ixgbe_l2_tn",
8087 sizeof(struct ixgbe_l2_tn_filter),
8092 rte_memcpy(&node->key,
8094 sizeof(struct ixgbe_l2_tn_key));
8095 node->pool = l2_tunnel->pool;
8096 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8103 switch (l2_tunnel->l2_tunnel_type) {
8104 case RTE_L2_TUNNEL_TYPE_E_TAG:
8105 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8108 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8113 if ((!restore) && (ret < 0))
8114 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8119 /* Delete l2 tunnel filter */
8121 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8122 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8125 struct ixgbe_l2_tn_info *l2_tn_info =
8126 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8127 struct ixgbe_l2_tn_key key;
8129 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8130 key.tn_id = l2_tunnel->tunnel_id;
8131 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8135 switch (l2_tunnel->l2_tunnel_type) {
8136 case RTE_L2_TUNNEL_TYPE_E_TAG:
8137 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8140 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8149 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8150 * @dev: pointer to rte_eth_dev structure
8151 * @filter_op:operation will be taken.
8152 * @arg: a pointer to specific structure corresponding to the filter_op
8155 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8156 enum rte_filter_op filter_op,
8161 if (filter_op == RTE_ETH_FILTER_NOP)
8165 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8170 switch (filter_op) {
8171 case RTE_ETH_FILTER_ADD:
8172 ret = ixgbe_dev_l2_tunnel_filter_add
8174 (struct rte_eth_l2_tunnel_conf *)arg,
8177 case RTE_ETH_FILTER_DELETE:
8178 ret = ixgbe_dev_l2_tunnel_filter_del
8180 (struct rte_eth_l2_tunnel_conf *)arg);
8183 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8191 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8195 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8197 if (hw->mac.type != ixgbe_mac_X550 &&
8198 hw->mac.type != ixgbe_mac_X550EM_x &&
8199 hw->mac.type != ixgbe_mac_X550EM_a) {
8203 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8204 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8206 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8207 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8212 /* Enable l2 tunnel forwarding */
8214 ixgbe_dev_l2_tunnel_forwarding_enable
8215 (struct rte_eth_dev *dev,
8216 enum rte_eth_tunnel_type l2_tunnel_type)
8218 struct ixgbe_l2_tn_info *l2_tn_info =
8219 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8222 switch (l2_tunnel_type) {
8223 case RTE_L2_TUNNEL_TYPE_E_TAG:
8224 l2_tn_info->e_tag_fwd_en = TRUE;
8225 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8228 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8236 /* Disable l2 tunnel forwarding */
8238 ixgbe_dev_l2_tunnel_forwarding_disable
8239 (struct rte_eth_dev *dev,
8240 enum rte_eth_tunnel_type l2_tunnel_type)
8242 struct ixgbe_l2_tn_info *l2_tn_info =
8243 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8246 switch (l2_tunnel_type) {
8247 case RTE_L2_TUNNEL_TYPE_E_TAG:
8248 l2_tn_info->e_tag_fwd_en = FALSE;
8249 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8252 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8261 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8262 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8265 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8267 uint32_t vmtir, vmvir;
8268 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8270 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8272 "VF id %u should be less than %u",
8278 if (hw->mac.type != ixgbe_mac_X550 &&
8279 hw->mac.type != ixgbe_mac_X550EM_x &&
8280 hw->mac.type != ixgbe_mac_X550EM_a) {
8285 vmtir = l2_tunnel->tunnel_id;
8289 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8291 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8292 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8294 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8295 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8300 /* Enable l2 tunnel tag insertion */
8302 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8303 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8307 switch (l2_tunnel->l2_tunnel_type) {
8308 case RTE_L2_TUNNEL_TYPE_E_TAG:
8309 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8312 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8320 /* Disable l2 tunnel tag insertion */
8322 ixgbe_dev_l2_tunnel_insertion_disable
8323 (struct rte_eth_dev *dev,
8324 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8328 switch (l2_tunnel->l2_tunnel_type) {
8329 case RTE_L2_TUNNEL_TYPE_E_TAG:
8330 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8333 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8342 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8347 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8349 if (hw->mac.type != ixgbe_mac_X550 &&
8350 hw->mac.type != ixgbe_mac_X550EM_x &&
8351 hw->mac.type != ixgbe_mac_X550EM_a) {
8355 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8357 qde |= IXGBE_QDE_STRIP_TAG;
8359 qde &= ~IXGBE_QDE_STRIP_TAG;
8360 qde &= ~IXGBE_QDE_READ;
8361 qde |= IXGBE_QDE_WRITE;
8362 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8367 /* Enable l2 tunnel tag stripping */
8369 ixgbe_dev_l2_tunnel_stripping_enable
8370 (struct rte_eth_dev *dev,
8371 enum rte_eth_tunnel_type l2_tunnel_type)
8375 switch (l2_tunnel_type) {
8376 case RTE_L2_TUNNEL_TYPE_E_TAG:
8377 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8380 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8388 /* Disable l2 tunnel tag stripping */
8390 ixgbe_dev_l2_tunnel_stripping_disable
8391 (struct rte_eth_dev *dev,
8392 enum rte_eth_tunnel_type l2_tunnel_type)
8396 switch (l2_tunnel_type) {
8397 case RTE_L2_TUNNEL_TYPE_E_TAG:
8398 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8401 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8409 /* Enable/disable l2 tunnel offload functions */
8411 ixgbe_dev_l2_tunnel_offload_set
8412 (struct rte_eth_dev *dev,
8413 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8419 if (l2_tunnel == NULL)
8423 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8425 ret = ixgbe_dev_l2_tunnel_enable(
8427 l2_tunnel->l2_tunnel_type);
8429 ret = ixgbe_dev_l2_tunnel_disable(
8431 l2_tunnel->l2_tunnel_type);
8434 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8436 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8440 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8445 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8447 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8449 l2_tunnel->l2_tunnel_type);
8451 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8453 l2_tunnel->l2_tunnel_type);
8456 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8458 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8460 l2_tunnel->l2_tunnel_type);
8462 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8464 l2_tunnel->l2_tunnel_type);
8471 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8474 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8475 IXGBE_WRITE_FLUSH(hw);
8480 /* There's only one register for VxLAN UDP port.
8481 * So, we cannot add several ports. Will update it.
8484 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8488 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8492 return ixgbe_update_vxlan_port(hw, port);
8495 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8496 * UDP port, it must have a value.
8497 * So, will reset it to the original value 0.
8500 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8505 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8507 if (cur_port != port) {
8508 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8512 return ixgbe_update_vxlan_port(hw, 0);
8515 /* Add UDP tunneling port */
8517 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8518 struct rte_eth_udp_tunnel *udp_tunnel)
8521 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8523 if (hw->mac.type != ixgbe_mac_X550 &&
8524 hw->mac.type != ixgbe_mac_X550EM_x &&
8525 hw->mac.type != ixgbe_mac_X550EM_a) {
8529 if (udp_tunnel == NULL)
8532 switch (udp_tunnel->prot_type) {
8533 case RTE_TUNNEL_TYPE_VXLAN:
8534 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8537 case RTE_TUNNEL_TYPE_GENEVE:
8538 case RTE_TUNNEL_TYPE_TEREDO:
8539 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8544 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8552 /* Remove UDP tunneling port */
8554 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8555 struct rte_eth_udp_tunnel *udp_tunnel)
8558 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8560 if (hw->mac.type != ixgbe_mac_X550 &&
8561 hw->mac.type != ixgbe_mac_X550EM_x &&
8562 hw->mac.type != ixgbe_mac_X550EM_a) {
8566 if (udp_tunnel == NULL)
8569 switch (udp_tunnel->prot_type) {
8570 case RTE_TUNNEL_TYPE_VXLAN:
8571 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8573 case RTE_TUNNEL_TYPE_GENEVE:
8574 case RTE_TUNNEL_TYPE_TEREDO:
8575 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8579 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8588 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8590 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8593 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8597 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8609 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8611 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8614 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8618 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8630 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8632 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8634 int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8636 switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8640 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8652 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8654 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8657 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8661 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8672 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8674 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8677 /* peek the message first */
8678 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8680 /* PF reset VF event */
8681 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8682 /* dummy mbx read to ack pf */
8683 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8685 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8691 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8694 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8695 struct ixgbe_interrupt *intr =
8696 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8697 ixgbevf_intr_disable(dev);
8699 /* read-on-clear nic registers here */
8700 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8703 /* only one misc vector supported - mailbox */
8704 eicr &= IXGBE_VTEICR_MASK;
8705 if (eicr == IXGBE_MISC_VEC_ID)
8706 intr->flags |= IXGBE_FLAG_MAILBOX;
8712 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8714 struct ixgbe_interrupt *intr =
8715 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8717 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8718 ixgbevf_mbx_process(dev);
8719 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8722 ixgbevf_intr_enable(dev);
8728 ixgbevf_dev_interrupt_handler(void *param)
8730 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8732 ixgbevf_dev_interrupt_get_status(dev);
8733 ixgbevf_dev_interrupt_action(dev);
8737 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8738 * @hw: pointer to hardware structure
8740 * Stops the transmit data path and waits for the HW to internally empty
8741 * the Tx security block
8743 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8745 #define IXGBE_MAX_SECTX_POLL 40
8750 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8751 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8752 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8753 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8754 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8755 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8757 /* Use interrupt-safe sleep just in case */
8761 /* For informational purposes only */
8762 if (i >= IXGBE_MAX_SECTX_POLL)
8763 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8764 "path fully disabled. Continuing with init.");
8766 return IXGBE_SUCCESS;
8770 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8771 * @hw: pointer to hardware structure
8773 * Enables the transmit data path.
8775 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8779 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8780 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8781 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8782 IXGBE_WRITE_FLUSH(hw);
8784 return IXGBE_SUCCESS;
8787 /* restore n-tuple filter */
8789 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8791 struct ixgbe_filter_info *filter_info =
8792 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8793 struct ixgbe_5tuple_filter *node;
8795 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8796 ixgbe_inject_5tuple_filter(dev, node);
8800 /* restore ethernet type filter */
8802 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8804 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8805 struct ixgbe_filter_info *filter_info =
8806 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8809 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8810 if (filter_info->ethertype_mask & (1 << i)) {
8811 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8812 filter_info->ethertype_filters[i].etqf);
8813 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8814 filter_info->ethertype_filters[i].etqs);
8815 IXGBE_WRITE_FLUSH(hw);
8820 /* restore SYN filter */
8822 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8824 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8825 struct ixgbe_filter_info *filter_info =
8826 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8829 synqf = filter_info->syn_info;
8831 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8832 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8833 IXGBE_WRITE_FLUSH(hw);
8837 /* restore L2 tunnel filter */
8839 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8841 struct ixgbe_l2_tn_info *l2_tn_info =
8842 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8843 struct ixgbe_l2_tn_filter *node;
8844 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8846 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8847 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8848 l2_tn_conf.tunnel_id = node->key.tn_id;
8849 l2_tn_conf.pool = node->pool;
8850 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8854 /* restore rss filter */
8856 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8858 struct ixgbe_filter_info *filter_info =
8859 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8861 if (filter_info->rss_info.conf.queue_num)
8862 ixgbe_config_rss_filter(dev,
8863 &filter_info->rss_info, TRUE);
8867 ixgbe_filter_restore(struct rte_eth_dev *dev)
8869 ixgbe_ntuple_filter_restore(dev);
8870 ixgbe_ethertype_filter_restore(dev);
8871 ixgbe_syn_filter_restore(dev);
8872 ixgbe_fdir_filter_restore(dev);
8873 ixgbe_l2_tn_filter_restore(dev);
8874 ixgbe_rss_filter_restore(dev);
8880 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8882 struct ixgbe_l2_tn_info *l2_tn_info =
8883 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8884 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8886 if (l2_tn_info->e_tag_en)
8887 (void)ixgbe_e_tag_enable(hw);
8889 if (l2_tn_info->e_tag_fwd_en)
8890 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8892 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8895 /* remove all the n-tuple filters */
8897 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8899 struct ixgbe_filter_info *filter_info =
8900 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8901 struct ixgbe_5tuple_filter *p_5tuple;
8903 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8904 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8907 /* remove all the ether type filters */
8909 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8911 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8912 struct ixgbe_filter_info *filter_info =
8913 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8916 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8917 if (filter_info->ethertype_mask & (1 << i) &&
8918 !filter_info->ethertype_filters[i].conf) {
8919 (void)ixgbe_ethertype_filter_remove(filter_info,
8921 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8922 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8923 IXGBE_WRITE_FLUSH(hw);
8928 /* remove the SYN filter */
8930 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8932 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8933 struct ixgbe_filter_info *filter_info =
8934 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8936 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8937 filter_info->syn_info = 0;
8939 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8940 IXGBE_WRITE_FLUSH(hw);
8944 /* remove all the L2 tunnel filters */
8946 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8948 struct ixgbe_l2_tn_info *l2_tn_info =
8949 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8950 struct ixgbe_l2_tn_filter *l2_tn_filter;
8951 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8954 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8955 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8956 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8957 l2_tn_conf.pool = l2_tn_filter->pool;
8958 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8967 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8968 struct ixgbe_macsec_setting *macsec_setting)
8970 struct ixgbe_macsec_setting *macsec =
8971 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8973 macsec->offload_en = macsec_setting->offload_en;
8974 macsec->encrypt_en = macsec_setting->encrypt_en;
8975 macsec->replayprotect_en = macsec_setting->replayprotect_en;
8979 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8981 struct ixgbe_macsec_setting *macsec =
8982 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8984 macsec->offload_en = 0;
8985 macsec->encrypt_en = 0;
8986 macsec->replayprotect_en = 0;
8990 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8991 struct ixgbe_macsec_setting *macsec_setting)
8993 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8995 uint8_t en = macsec_setting->encrypt_en;
8996 uint8_t rp = macsec_setting->replayprotect_en;
9000 * As no ixgbe_disable_sec_rx_path equivalent is
9001 * implemented for tx in the base code, and we are
9002 * not allowed to modify the base code in DPDK, so
9003 * just call the hand-written one directly for now.
9004 * The hardware support has been checked by
9005 * ixgbe_disable_sec_rx_path().
9007 ixgbe_disable_sec_tx_path_generic(hw);
9009 /* Enable Ethernet CRC (required by MACsec offload) */
9010 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9011 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9012 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9014 /* Enable the TX and RX crypto engines */
9015 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9016 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9017 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9019 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9020 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9021 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9023 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9024 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9026 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9028 /* Enable SA lookup */
9029 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9030 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9031 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9032 IXGBE_LSECTXCTRL_AUTH;
9033 ctrl |= IXGBE_LSECTXCTRL_AISCI;
9034 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9035 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9036 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9038 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9039 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9040 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9041 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9043 ctrl |= IXGBE_LSECRXCTRL_RP;
9045 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9046 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9048 /* Start the data paths */
9049 ixgbe_enable_sec_rx_path(hw);
9052 * As no ixgbe_enable_sec_rx_path equivalent is
9053 * implemented for tx in the base code, and we are
9054 * not allowed to modify the base code in DPDK, so
9055 * just call the hand-written one directly for now.
9057 ixgbe_enable_sec_tx_path_generic(hw);
9061 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9063 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9068 * As no ixgbe_disable_sec_rx_path equivalent is
9069 * implemented for tx in the base code, and we are
9070 * not allowed to modify the base code in DPDK, so
9071 * just call the hand-written one directly for now.
9072 * The hardware support has been checked by
9073 * ixgbe_disable_sec_rx_path().
9075 ixgbe_disable_sec_tx_path_generic(hw);
9077 /* Disable the TX and RX crypto engines */
9078 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9079 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9080 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9082 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9083 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9084 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9086 /* Disable SA lookup */
9087 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9088 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9089 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9090 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9092 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9093 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9094 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9095 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9097 /* Start the data paths */
9098 ixgbe_enable_sec_rx_path(hw);
9101 * As no ixgbe_enable_sec_rx_path equivalent is
9102 * implemented for tx in the base code, and we are
9103 * not allowed to modify the base code in DPDK, so
9104 * just call the hand-written one directly for now.
9106 ixgbe_enable_sec_tx_path_generic(hw);
9109 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9110 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9111 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9112 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9113 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9114 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9115 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9116 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9118 RTE_INIT(ixgbe_init_log)
9120 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
9121 if (ixgbe_logtype_init >= 0)
9122 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
9123 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
9124 if (ixgbe_logtype_driver >= 0)
9125 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
9126 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9127 ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
9128 if (ixgbe_logtype_rx >= 0)
9129 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
9132 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9133 ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9134 if (ixgbe_logtype_tx >= 0)
9135 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9138 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9139 ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9140 if (ixgbe_logtype_tx_free >= 0)
9141 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);