4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
65 #include "ixgbe_logs.h"
66 #include "base/ixgbe_api.h"
67 #include "base/ixgbe_vf.h"
68 #include "base/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
72 #include "base/ixgbe_type.h"
73 #include "base/ixgbe_phy.h"
74 #include "ixgbe_regs.h"
76 #include "rte_pmd_ixgbe.h"
79 * High threshold controlling when to start sending XOFF frames. Must be at
80 * least 8 bytes less than receive packet buffer size. This value is in units
83 #define IXGBE_FC_HI 0x80
86 * Low threshold controlling when to start sending XON frames. This value is
87 * in units of 1024 bytes.
89 #define IXGBE_FC_LO 0x40
91 /* Default minimum inter-interrupt interval for EITR configuration */
92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
94 /* Timer value included in XOFF frames. */
95 #define IXGBE_FC_PAUSE 0x680
97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
98 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
99 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
101 #define IXGBE_MMW_SIZE_DEFAULT 0x4
102 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
103 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
106 * Default values for RX/TX configuration
108 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
109 #define IXGBE_DEFAULT_RX_PTHRESH 8
110 #define IXGBE_DEFAULT_RX_HTHRESH 8
111 #define IXGBE_DEFAULT_RX_WTHRESH 0
113 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
114 #define IXGBE_DEFAULT_TX_PTHRESH 32
115 #define IXGBE_DEFAULT_TX_HTHRESH 0
116 #define IXGBE_DEFAULT_TX_WTHRESH 0
117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
119 /* Bit shift and mask */
120 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
121 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
122 #define IXGBE_8_BIT_WIDTH CHAR_BIT
123 #define IXGBE_8_BIT_MASK UINT8_MAX
125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
129 #define IXGBE_HKEY_MAX_INDEX 10
131 /* Additional timesync values. */
132 #define NSEC_PER_SEC 1000000000L
133 #define IXGBE_INCVAL_10GB 0x66666666
134 #define IXGBE_INCVAL_1GB 0x40000000
135 #define IXGBE_INCVAL_100 0x50000000
136 #define IXGBE_INCVAL_SHIFT_10GB 28
137 #define IXGBE_INCVAL_SHIFT_1GB 24
138 #define IXGBE_INCVAL_SHIFT_100 21
139 #define IXGBE_INCVAL_SHIFT_82599 7
140 #define IXGBE_INCPER_SHIFT_82599 24
142 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
144 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
146 #define DEFAULT_ETAG_ETYPE 0x893f
147 #define IXGBE_ETAG_ETYPE 0x00005084
148 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
149 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
150 #define IXGBE_RAH_ADTYPE 0x40000000
151 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
152 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
155 #define IXGBE_QDE_STRIP_TAG 0x00000004
156 #define IXGBE_VTEICR_MASK 0x07
158 enum ixgbevf_xcast_modes {
159 IXGBEVF_XCAST_MODE_NONE = 0,
160 IXGBEVF_XCAST_MODE_MULTI,
161 IXGBEVF_XCAST_MODE_ALLMULTI,
164 #define IXGBE_EXVET_VET_EXT_SHIFT 16
165 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
167 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
168 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
169 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
170 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
171 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
172 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
173 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
174 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
175 static int ixgbe_dev_start(struct rte_eth_dev *dev);
176 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
177 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
178 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
179 static void ixgbe_dev_close(struct rte_eth_dev *dev);
180 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
181 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
182 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
183 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
184 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
185 int wait_to_complete);
186 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
187 struct rte_eth_stats *stats);
188 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
189 struct rte_eth_xstat *xstats, unsigned n);
190 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
191 struct rte_eth_xstat *xstats, unsigned n);
192 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
193 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
194 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
195 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
196 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
197 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
198 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
202 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
204 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
205 struct rte_eth_dev_info *dev_info);
206 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
207 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
208 struct rte_eth_dev_info *dev_info);
209 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
211 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
212 uint16_t vlan_id, int on);
213 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
214 enum rte_vlan_type vlan_type,
216 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
217 uint16_t queue, bool on);
218 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
220 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
221 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
222 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
223 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
224 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
226 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
227 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
228 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
229 struct rte_eth_fc_conf *fc_conf);
230 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
231 struct rte_eth_fc_conf *fc_conf);
232 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
233 struct rte_eth_pfc_conf *pfc_conf);
234 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
235 struct rte_eth_rss_reta_entry64 *reta_conf,
237 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
238 struct rte_eth_rss_reta_entry64 *reta_conf,
240 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
241 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
242 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
243 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
244 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
245 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
246 struct rte_intr_handle *handle);
247 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
250 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
251 uint32_t index, uint32_t pool);
252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
254 struct ether_addr *mac_addr);
255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
256 static int is_ixgbe_pmd(const char *driver_name);
258 /* For Virtual Function support */
259 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
260 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
261 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
262 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
263 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
264 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
265 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
266 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
267 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
268 struct rte_eth_stats *stats);
269 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
270 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
271 uint16_t vlan_id, int on);
272 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
273 uint16_t queue, int on);
274 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
275 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
276 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
278 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
280 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
281 uint8_t queue, uint8_t msix_vector);
282 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
283 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
284 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
286 /* For Eth VMDQ APIs support */
287 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
288 ether_addr * mac_addr, uint8_t on);
289 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
291 struct rte_eth_mirror_conf *mirror_conf,
292 uint8_t rule_id, uint8_t on);
293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
300 uint8_t queue, uint8_t msix_vector);
301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
304 uint16_t queue_idx, uint16_t tx_rate);
306 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
307 struct ether_addr *mac_addr,
308 uint32_t index, uint32_t pool);
309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
311 struct ether_addr *mac_addr);
312 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
313 struct rte_eth_syn_filter *filter,
315 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
316 struct rte_eth_syn_filter *filter);
317 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
318 enum rte_filter_op filter_op,
320 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
321 struct ixgbe_5tuple_filter *filter);
322 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
323 struct ixgbe_5tuple_filter *filter);
324 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
325 struct rte_eth_ntuple_filter *filter,
327 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
328 enum rte_filter_op filter_op,
330 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
331 struct rte_eth_ntuple_filter *filter);
332 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
333 struct rte_eth_ethertype_filter *filter,
335 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
336 enum rte_filter_op filter_op,
338 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
339 struct rte_eth_ethertype_filter *filter);
340 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
341 enum rte_filter_type filter_type,
342 enum rte_filter_op filter_op,
344 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
346 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
347 struct ether_addr *mc_addr_set,
348 uint32_t nb_mc_addr);
349 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
350 struct rte_eth_dcb_info *dcb_info);
352 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
353 static int ixgbe_get_regs(struct rte_eth_dev *dev,
354 struct rte_dev_reg_info *regs);
355 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
356 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
357 struct rte_dev_eeprom_info *eeprom);
358 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
359 struct rte_dev_eeprom_info *eeprom);
361 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
362 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
363 struct rte_dev_reg_info *regs);
365 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
366 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
367 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
368 struct timespec *timestamp,
370 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
371 struct timespec *timestamp);
372 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
373 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
374 struct timespec *timestamp);
375 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
376 const struct timespec *timestamp);
377 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
380 static int ixgbe_dev_l2_tunnel_eth_type_conf
381 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
382 static int ixgbe_dev_l2_tunnel_offload_set
383 (struct rte_eth_dev *dev,
384 struct rte_eth_l2_tunnel_conf *l2_tunnel,
387 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
388 enum rte_filter_op filter_op,
391 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
392 struct rte_eth_udp_tunnel *udp_tunnel);
393 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
394 struct rte_eth_udp_tunnel *udp_tunnel);
395 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
398 * Define VF Stats MACRO for Non "cleared on read" register
400 #define UPDATE_VF_STAT(reg, last, cur) \
402 uint32_t latest = IXGBE_READ_REG(hw, reg); \
403 cur += (latest - last) & UINT_MAX; \
407 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
409 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
410 u64 new_msb = IXGBE_READ_REG(hw, msb); \
411 u64 latest = ((new_msb << 32) | new_lsb); \
412 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
416 #define IXGBE_SET_HWSTRIP(h, q) do {\
417 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
418 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
419 (h)->bitmap[idx] |= 1 << bit;\
422 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
423 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
424 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
425 (h)->bitmap[idx] &= ~(1 << bit);\
428 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
429 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
430 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
431 (r) = (h)->bitmap[idx] >> bit & 1;\
435 * The set of PCI devices this driver supports
437 static const struct rte_pci_id pci_id_ixgbe_map[] = {
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
491 #ifdef RTE_NIC_BYPASS
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
494 { .vendor_id = 0, /* sentinel */ },
498 * The set of PCI devices this driver supports (for 82599 VF)
500 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
504 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
505 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
506 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
507 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
508 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
509 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
510 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
511 { .vendor_id = 0, /* sentinel */ },
514 static const struct rte_eth_desc_lim rx_desc_lim = {
515 .nb_max = IXGBE_MAX_RING_DESC,
516 .nb_min = IXGBE_MIN_RING_DESC,
517 .nb_align = IXGBE_RXD_ALIGN,
520 static const struct rte_eth_desc_lim tx_desc_lim = {
521 .nb_max = IXGBE_MAX_RING_DESC,
522 .nb_min = IXGBE_MIN_RING_DESC,
523 .nb_align = IXGBE_TXD_ALIGN,
524 .nb_seg_max = IXGBE_TX_MAX_SEG,
525 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
528 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
529 .dev_configure = ixgbe_dev_configure,
530 .dev_start = ixgbe_dev_start,
531 .dev_stop = ixgbe_dev_stop,
532 .dev_set_link_up = ixgbe_dev_set_link_up,
533 .dev_set_link_down = ixgbe_dev_set_link_down,
534 .dev_close = ixgbe_dev_close,
535 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
536 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
537 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
538 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
539 .link_update = ixgbe_dev_link_update,
540 .stats_get = ixgbe_dev_stats_get,
541 .xstats_get = ixgbe_dev_xstats_get,
542 .stats_reset = ixgbe_dev_stats_reset,
543 .xstats_reset = ixgbe_dev_xstats_reset,
544 .xstats_get_names = ixgbe_dev_xstats_get_names,
545 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
546 .fw_version_get = ixgbe_fw_version_get,
547 .dev_infos_get = ixgbe_dev_info_get,
548 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
549 .mtu_set = ixgbe_dev_mtu_set,
550 .vlan_filter_set = ixgbe_vlan_filter_set,
551 .vlan_tpid_set = ixgbe_vlan_tpid_set,
552 .vlan_offload_set = ixgbe_vlan_offload_set,
553 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
554 .rx_queue_start = ixgbe_dev_rx_queue_start,
555 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
556 .tx_queue_start = ixgbe_dev_tx_queue_start,
557 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
558 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
559 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
560 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
561 .rx_queue_release = ixgbe_dev_rx_queue_release,
562 .rx_queue_count = ixgbe_dev_rx_queue_count,
563 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
564 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
565 .tx_queue_release = ixgbe_dev_tx_queue_release,
566 .dev_led_on = ixgbe_dev_led_on,
567 .dev_led_off = ixgbe_dev_led_off,
568 .flow_ctrl_get = ixgbe_flow_ctrl_get,
569 .flow_ctrl_set = ixgbe_flow_ctrl_set,
570 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
571 .mac_addr_add = ixgbe_add_rar,
572 .mac_addr_remove = ixgbe_remove_rar,
573 .mac_addr_set = ixgbe_set_default_mac_addr,
574 .uc_hash_table_set = ixgbe_uc_hash_table_set,
575 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
576 .mirror_rule_set = ixgbe_mirror_rule_set,
577 .mirror_rule_reset = ixgbe_mirror_rule_reset,
578 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
579 .reta_update = ixgbe_dev_rss_reta_update,
580 .reta_query = ixgbe_dev_rss_reta_query,
581 #ifdef RTE_NIC_BYPASS
582 .bypass_init = ixgbe_bypass_init,
583 .bypass_state_set = ixgbe_bypass_state_store,
584 .bypass_state_show = ixgbe_bypass_state_show,
585 .bypass_event_set = ixgbe_bypass_event_store,
586 .bypass_event_show = ixgbe_bypass_event_show,
587 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
588 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
589 .bypass_ver_show = ixgbe_bypass_ver_show,
590 .bypass_wd_reset = ixgbe_bypass_wd_reset,
591 #endif /* RTE_NIC_BYPASS */
592 .rss_hash_update = ixgbe_dev_rss_hash_update,
593 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
594 .filter_ctrl = ixgbe_dev_filter_ctrl,
595 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
596 .rxq_info_get = ixgbe_rxq_info_get,
597 .txq_info_get = ixgbe_txq_info_get,
598 .timesync_enable = ixgbe_timesync_enable,
599 .timesync_disable = ixgbe_timesync_disable,
600 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
601 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
602 .get_reg = ixgbe_get_regs,
603 .get_eeprom_length = ixgbe_get_eeprom_length,
604 .get_eeprom = ixgbe_get_eeprom,
605 .set_eeprom = ixgbe_set_eeprom,
606 .get_dcb_info = ixgbe_dev_get_dcb_info,
607 .timesync_adjust_time = ixgbe_timesync_adjust_time,
608 .timesync_read_time = ixgbe_timesync_read_time,
609 .timesync_write_time = ixgbe_timesync_write_time,
610 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
611 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
612 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
613 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
617 * dev_ops for virtual function, bare necessities for basic vf
618 * operation have been implemented
620 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
621 .dev_configure = ixgbevf_dev_configure,
622 .dev_start = ixgbevf_dev_start,
623 .dev_stop = ixgbevf_dev_stop,
624 .link_update = ixgbe_dev_link_update,
625 .stats_get = ixgbevf_dev_stats_get,
626 .xstats_get = ixgbevf_dev_xstats_get,
627 .stats_reset = ixgbevf_dev_stats_reset,
628 .xstats_reset = ixgbevf_dev_stats_reset,
629 .xstats_get_names = ixgbevf_dev_xstats_get_names,
630 .dev_close = ixgbevf_dev_close,
631 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
632 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
633 .dev_infos_get = ixgbevf_dev_info_get,
634 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
635 .mtu_set = ixgbevf_dev_set_mtu,
636 .vlan_filter_set = ixgbevf_vlan_filter_set,
637 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
638 .vlan_offload_set = ixgbevf_vlan_offload_set,
639 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
640 .rx_queue_release = ixgbe_dev_rx_queue_release,
641 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
642 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
643 .tx_queue_release = ixgbe_dev_tx_queue_release,
644 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
645 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
646 .mac_addr_add = ixgbevf_add_mac_addr,
647 .mac_addr_remove = ixgbevf_remove_mac_addr,
648 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
649 .rxq_info_get = ixgbe_rxq_info_get,
650 .txq_info_get = ixgbe_txq_info_get,
651 .mac_addr_set = ixgbevf_set_default_mac_addr,
652 .get_reg = ixgbevf_get_regs,
653 .reta_update = ixgbe_dev_rss_reta_update,
654 .reta_query = ixgbe_dev_rss_reta_query,
655 .rss_hash_update = ixgbe_dev_rss_hash_update,
656 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
659 /* store statistics names and its offset in stats structure */
660 struct rte_ixgbe_xstats_name_off {
661 char name[RTE_ETH_XSTATS_NAME_SIZE];
665 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
666 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
667 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
668 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
669 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
670 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
671 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
672 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
673 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
674 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
675 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
676 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
677 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
678 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
679 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
680 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
682 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
684 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
685 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
686 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
687 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
688 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
689 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
690 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
691 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
692 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
693 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
694 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
695 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
696 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
697 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
698 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
699 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
700 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
702 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
704 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
705 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
706 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
707 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
709 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
711 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
713 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
715 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
717 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
719 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
722 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
723 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
724 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
726 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
727 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
728 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
729 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
730 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
732 {"rx_fcoe_no_direct_data_placement_ext_buff",
733 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
735 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
737 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
739 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
741 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
743 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
746 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
747 sizeof(rte_ixgbe_stats_strings[0]))
749 /* MACsec statistics */
750 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
751 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
753 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
754 out_pkts_encrypted)},
755 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
756 out_pkts_protected)},
757 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
758 out_octets_encrypted)},
759 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
760 out_octets_protected)},
761 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
763 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
765 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
768 in_pkts_unknownsci)},
769 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
770 in_octets_decrypted)},
771 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
772 in_octets_validated)},
773 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
775 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
777 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
779 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
781 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
783 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
785 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
787 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
788 in_pkts_notusingsa)},
791 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
792 sizeof(rte_ixgbe_macsec_strings[0]))
794 /* Per-queue statistics */
795 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
796 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
797 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
798 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
799 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
802 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
803 sizeof(rte_ixgbe_rxq_strings[0]))
804 #define IXGBE_NB_RXQ_PRIO_VALUES 8
806 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
807 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
808 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
809 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
813 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
814 sizeof(rte_ixgbe_txq_strings[0]))
815 #define IXGBE_NB_TXQ_PRIO_VALUES 8
817 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
818 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
821 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
822 sizeof(rte_ixgbevf_stats_strings[0]))
825 * Atomically reads the link status information from global
826 * structure rte_eth_dev.
829 * - Pointer to the structure rte_eth_dev to read from.
830 * - Pointer to the buffer to be saved with the link status.
833 * - On success, zero.
834 * - On failure, negative value.
837 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
838 struct rte_eth_link *link)
840 struct rte_eth_link *dst = link;
841 struct rte_eth_link *src = &(dev->data->dev_link);
843 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
844 *(uint64_t *)src) == 0)
851 * Atomically writes the link status information into global
852 * structure rte_eth_dev.
855 * - Pointer to the structure rte_eth_dev to read from.
856 * - Pointer to the buffer to be saved with the link status.
859 * - On success, zero.
860 * - On failure, negative value.
863 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
864 struct rte_eth_link *link)
866 struct rte_eth_link *dst = &(dev->data->dev_link);
867 struct rte_eth_link *src = link;
869 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
870 *(uint64_t *)src) == 0)
877 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
880 ixgbe_is_sfp(struct ixgbe_hw *hw)
882 switch (hw->phy.type) {
883 case ixgbe_phy_sfp_avago:
884 case ixgbe_phy_sfp_ftl:
885 case ixgbe_phy_sfp_intel:
886 case ixgbe_phy_sfp_unknown:
887 case ixgbe_phy_sfp_passive_tyco:
888 case ixgbe_phy_sfp_passive_unknown:
895 static inline int32_t
896 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
901 status = ixgbe_reset_hw(hw);
903 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
904 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
905 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
906 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
907 IXGBE_WRITE_FLUSH(hw);
913 ixgbe_enable_intr(struct rte_eth_dev *dev)
915 struct ixgbe_interrupt *intr =
916 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
917 struct ixgbe_hw *hw =
918 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
920 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
921 IXGBE_WRITE_FLUSH(hw);
925 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
928 ixgbe_disable_intr(struct ixgbe_hw *hw)
930 PMD_INIT_FUNC_TRACE();
932 if (hw->mac.type == ixgbe_mac_82598EB) {
933 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
935 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
936 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
937 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
939 IXGBE_WRITE_FLUSH(hw);
943 * This function resets queue statistics mapping registers.
944 * From Niantic datasheet, Initialization of Statistics section:
945 * "...if software requires the queue counters, the RQSMR and TQSM registers
946 * must be re-programmed following a device reset.
949 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
953 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
954 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
955 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
961 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
966 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
967 #define NB_QMAP_FIELDS_PER_QSM_REG 4
968 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
970 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
971 struct ixgbe_stat_mapping_registers *stat_mappings =
972 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
973 uint32_t qsmr_mask = 0;
974 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
978 if ((hw->mac.type != ixgbe_mac_82599EB) &&
979 (hw->mac.type != ixgbe_mac_X540) &&
980 (hw->mac.type != ixgbe_mac_X550) &&
981 (hw->mac.type != ixgbe_mac_X550EM_x) &&
982 (hw->mac.type != ixgbe_mac_X550EM_a))
985 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
986 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
989 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
990 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
991 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
994 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
996 /* Now clear any previous stat_idx set */
997 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
999 stat_mappings->tqsm[n] &= ~clearing_mask;
1001 stat_mappings->rqsmr[n] &= ~clearing_mask;
1003 q_map = (uint32_t)stat_idx;
1004 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1005 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1007 stat_mappings->tqsm[n] |= qsmr_mask;
1009 stat_mappings->rqsmr[n] |= qsmr_mask;
1011 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1012 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1013 queue_id, stat_idx);
1014 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1015 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1017 /* Now write the mapping in the appropriate register */
1019 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1020 stat_mappings->rqsmr[n], n);
1021 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1023 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1024 stat_mappings->tqsm[n], n);
1025 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1031 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1033 struct ixgbe_stat_mapping_registers *stat_mappings =
1034 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1035 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038 /* write whatever was in stat mapping table to the NIC */
1039 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1041 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1044 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1049 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1052 struct ixgbe_dcb_tc_config *tc;
1053 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1055 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1056 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1057 for (i = 0; i < dcb_max_tc; i++) {
1058 tc = &dcb_config->tc_config[i];
1059 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1060 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1061 (uint8_t)(100/dcb_max_tc + (i & 1));
1062 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1063 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1064 (uint8_t)(100/dcb_max_tc + (i & 1));
1065 tc->pfc = ixgbe_dcb_pfc_disabled;
1068 /* Initialize default user to priority mapping, UPx->TC0 */
1069 tc = &dcb_config->tc_config[0];
1070 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1071 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1072 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1073 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1074 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1076 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1077 dcb_config->pfc_mode_enable = false;
1078 dcb_config->vt_mode = true;
1079 dcb_config->round_robin_enable = false;
1080 /* support all DCB capabilities in 82599 */
1081 dcb_config->support.capabilities = 0xFF;
1083 /*we only support 4 Tcs for X540, X550 */
1084 if (hw->mac.type == ixgbe_mac_X540 ||
1085 hw->mac.type == ixgbe_mac_X550 ||
1086 hw->mac.type == ixgbe_mac_X550EM_x ||
1087 hw->mac.type == ixgbe_mac_X550EM_a) {
1088 dcb_config->num_tcs.pg_tcs = 4;
1089 dcb_config->num_tcs.pfc_tcs = 4;
1094 * Ensure that all locks are released before first NVM or PHY access
1097 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1102 * Phy lock should not fail in this early stage. If this is the case,
1103 * it is due to an improper exit of the application.
1104 * So force the release of the faulty lock. Release of common lock
1105 * is done automatically by swfw_sync function.
1107 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1108 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1109 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1111 ixgbe_release_swfw_semaphore(hw, mask);
1114 * These ones are more tricky since they are common to all ports; but
1115 * swfw_sync retries last long enough (1s) to be almost sure that if
1116 * lock can not be taken it is due to an improper lock of the
1119 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1120 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1121 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1123 ixgbe_release_swfw_semaphore(hw, mask);
1127 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1128 * It returns 0 on success.
1131 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1133 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1134 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1135 struct ixgbe_hw *hw =
1136 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1137 struct ixgbe_vfta *shadow_vfta =
1138 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1139 struct ixgbe_hwstrip *hwstrip =
1140 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1141 struct ixgbe_dcb_config *dcb_config =
1142 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1143 struct ixgbe_filter_info *filter_info =
1144 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1149 PMD_INIT_FUNC_TRACE();
1151 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1152 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1153 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1154 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1157 * For secondary processes, we don't initialise any further as primary
1158 * has already done this work. Only check we don't need a different
1159 * RX and TX function.
1161 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1162 struct ixgbe_tx_queue *txq;
1163 /* TX queue function in primary, set by last queue initialized
1164 * Tx queue may not initialized by primary process
1166 if (eth_dev->data->tx_queues) {
1167 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1168 ixgbe_set_tx_function(eth_dev, txq);
1170 /* Use default TX function if we get here */
1171 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1172 "Using default TX function.");
1175 ixgbe_set_rx_function(eth_dev);
1180 rte_eth_copy_pci_info(eth_dev, pci_dev);
1181 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1183 /* Vendor and Device ID need to be set before init of shared code */
1184 hw->device_id = pci_dev->id.device_id;
1185 hw->vendor_id = pci_dev->id.vendor_id;
1186 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1187 hw->allow_unsupported_sfp = 1;
1189 /* Initialize the shared code (base driver) */
1190 #ifdef RTE_NIC_BYPASS
1191 diag = ixgbe_bypass_init_shared_code(hw);
1193 diag = ixgbe_init_shared_code(hw);
1194 #endif /* RTE_NIC_BYPASS */
1196 if (diag != IXGBE_SUCCESS) {
1197 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1201 /* pick up the PCI bus settings for reporting later */
1202 ixgbe_get_bus_info(hw);
1204 /* Unlock any pending hardware semaphore */
1205 ixgbe_swfw_lock_reset(hw);
1207 /* Initialize DCB configuration*/
1208 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1209 ixgbe_dcb_init(hw, dcb_config);
1210 /* Get Hardware Flow Control setting */
1211 hw->fc.requested_mode = ixgbe_fc_full;
1212 hw->fc.current_mode = ixgbe_fc_full;
1213 hw->fc.pause_time = IXGBE_FC_PAUSE;
1214 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1215 hw->fc.low_water[i] = IXGBE_FC_LO;
1216 hw->fc.high_water[i] = IXGBE_FC_HI;
1218 hw->fc.send_xon = 1;
1220 /* Make sure we have a good EEPROM before we read from it */
1221 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1222 if (diag != IXGBE_SUCCESS) {
1223 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1227 #ifdef RTE_NIC_BYPASS
1228 diag = ixgbe_bypass_init_hw(hw);
1230 diag = ixgbe_init_hw(hw);
1231 #endif /* RTE_NIC_BYPASS */
1234 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1235 * is called too soon after the kernel driver unbinding/binding occurs.
1236 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1237 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1238 * also called. See ixgbe_identify_phy_82599(). The reason for the
1239 * failure is not known, and only occuts when virtualisation features
1240 * are disabled in the bios. A delay of 100ms was found to be enough by
1241 * trial-and-error, and is doubled to be safe.
1243 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1245 diag = ixgbe_init_hw(hw);
1248 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1249 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1250 "LOM. Please be aware there may be issues associated "
1251 "with your hardware.");
1252 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1253 "please contact your Intel or hardware representative "
1254 "who provided you with this hardware.");
1255 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1256 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1258 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1262 /* Reset the hw statistics */
1263 ixgbe_dev_stats_reset(eth_dev);
1265 /* disable interrupt */
1266 ixgbe_disable_intr(hw);
1268 /* reset mappings for queue statistics hw counters*/
1269 ixgbe_reset_qstat_mappings(hw);
1271 /* Allocate memory for storing MAC addresses */
1272 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1273 hw->mac.num_rar_entries, 0);
1274 if (eth_dev->data->mac_addrs == NULL) {
1276 "Failed to allocate %u bytes needed to store "
1278 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1281 /* Copy the permanent MAC address */
1282 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1283 ð_dev->data->mac_addrs[0]);
1285 /* Allocate memory for storing hash filter MAC addresses */
1286 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1287 IXGBE_VMDQ_NUM_UC_MAC, 0);
1288 if (eth_dev->data->hash_mac_addrs == NULL) {
1290 "Failed to allocate %d bytes needed to store MAC addresses",
1291 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1295 /* initialize the vfta */
1296 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1298 /* initialize the hw strip bitmap*/
1299 memset(hwstrip, 0, sizeof(*hwstrip));
1301 /* initialize PF if max_vfs not zero */
1302 ixgbe_pf_host_init(eth_dev);
1304 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1305 /* let hardware know driver is loaded */
1306 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1307 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1308 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1309 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1310 IXGBE_WRITE_FLUSH(hw);
1312 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1313 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1314 (int) hw->mac.type, (int) hw->phy.type,
1315 (int) hw->phy.sfp_type);
1317 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1318 (int) hw->mac.type, (int) hw->phy.type);
1320 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1321 eth_dev->data->port_id, pci_dev->id.vendor_id,
1322 pci_dev->id.device_id);
1324 rte_intr_callback_register(intr_handle,
1325 ixgbe_dev_interrupt_handler, eth_dev);
1327 /* enable uio/vfio intr/eventfd mapping */
1328 rte_intr_enable(intr_handle);
1330 /* enable support intr */
1331 ixgbe_enable_intr(eth_dev);
1333 /* initialize filter info */
1334 memset(filter_info, 0,
1335 sizeof(struct ixgbe_filter_info));
1337 /* initialize 5tuple filter list */
1338 TAILQ_INIT(&filter_info->fivetuple_list);
1340 /* initialize flow director filter list & hash */
1341 ixgbe_fdir_filter_init(eth_dev);
1343 /* initialize l2 tunnel filter list & hash */
1344 ixgbe_l2_tn_filter_init(eth_dev);
1349 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1351 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1352 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1353 struct ixgbe_hw *hw;
1355 PMD_INIT_FUNC_TRACE();
1357 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1360 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1362 if (hw->adapter_stopped == 0)
1363 ixgbe_dev_close(eth_dev);
1365 eth_dev->dev_ops = NULL;
1366 eth_dev->rx_pkt_burst = NULL;
1367 eth_dev->tx_pkt_burst = NULL;
1369 /* Unlock any pending hardware semaphore */
1370 ixgbe_swfw_lock_reset(hw);
1372 /* disable uio intr before callback unregister */
1373 rte_intr_disable(intr_handle);
1374 rte_intr_callback_unregister(intr_handle,
1375 ixgbe_dev_interrupt_handler, eth_dev);
1377 /* uninitialize PF if max_vfs not zero */
1378 ixgbe_pf_host_uninit(eth_dev);
1380 rte_free(eth_dev->data->mac_addrs);
1381 eth_dev->data->mac_addrs = NULL;
1383 rte_free(eth_dev->data->hash_mac_addrs);
1384 eth_dev->data->hash_mac_addrs = NULL;
1386 /* remove all the fdir filters & hash */
1387 ixgbe_fdir_filter_uninit(eth_dev);
1389 /* remove all the L2 tunnel filters & hash */
1390 ixgbe_l2_tn_filter_uninit(eth_dev);
1392 /* Remove all ntuple filters of the device */
1393 ixgbe_ntuple_filter_uninit(eth_dev);
1398 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1400 struct ixgbe_filter_info *filter_info =
1401 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1402 struct ixgbe_5tuple_filter *p_5tuple;
1404 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1405 TAILQ_REMOVE(&filter_info->fivetuple_list,
1410 memset(filter_info->fivetuple_mask, 0,
1411 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1416 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1418 struct ixgbe_hw_fdir_info *fdir_info =
1419 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1420 struct ixgbe_fdir_filter *fdir_filter;
1422 if (fdir_info->hash_map)
1423 rte_free(fdir_info->hash_map);
1424 if (fdir_info->hash_handle)
1425 rte_hash_free(fdir_info->hash_handle);
1427 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1428 TAILQ_REMOVE(&fdir_info->fdir_list,
1431 rte_free(fdir_filter);
1437 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1439 struct ixgbe_l2_tn_info *l2_tn_info =
1440 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1441 struct ixgbe_l2_tn_filter *l2_tn_filter;
1443 if (l2_tn_info->hash_map)
1444 rte_free(l2_tn_info->hash_map);
1445 if (l2_tn_info->hash_handle)
1446 rte_hash_free(l2_tn_info->hash_handle);
1448 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1449 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1452 rte_free(l2_tn_filter);
1458 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1460 struct ixgbe_hw_fdir_info *fdir_info =
1461 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1462 char fdir_hash_name[RTE_HASH_NAMESIZE];
1463 struct rte_hash_parameters fdir_hash_params = {
1464 .name = fdir_hash_name,
1465 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1466 .key_len = sizeof(union ixgbe_atr_input),
1467 .hash_func = rte_hash_crc,
1468 .hash_func_init_val = 0,
1469 .socket_id = rte_socket_id(),
1472 TAILQ_INIT(&fdir_info->fdir_list);
1473 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1474 "fdir_%s", eth_dev->data->name);
1475 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1476 if (!fdir_info->hash_handle) {
1477 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1480 fdir_info->hash_map = rte_zmalloc("ixgbe",
1481 sizeof(struct ixgbe_fdir_filter *) *
1482 IXGBE_MAX_FDIR_FILTER_NUM,
1484 if (!fdir_info->hash_map) {
1486 "Failed to allocate memory for fdir hash map!");
1492 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1494 struct ixgbe_l2_tn_info *l2_tn_info =
1495 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1496 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1497 struct rte_hash_parameters l2_tn_hash_params = {
1498 .name = l2_tn_hash_name,
1499 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1500 .key_len = sizeof(struct ixgbe_l2_tn_key),
1501 .hash_func = rte_hash_crc,
1502 .hash_func_init_val = 0,
1503 .socket_id = rte_socket_id(),
1506 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1507 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1508 "l2_tn_%s", eth_dev->data->name);
1509 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1510 if (!l2_tn_info->hash_handle) {
1511 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1514 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1515 sizeof(struct ixgbe_l2_tn_filter *) *
1516 IXGBE_MAX_L2_TN_FILTER_NUM,
1518 if (!l2_tn_info->hash_map) {
1520 "Failed to allocate memory for L2 TN hash map!");
1527 * Negotiate mailbox API version with the PF.
1528 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1529 * Then we try to negotiate starting with the most recent one.
1530 * If all negotiation attempts fail, then we will proceed with
1531 * the default one (ixgbe_mbox_api_10).
1534 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1538 /* start with highest supported, proceed down */
1539 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1546 i != RTE_DIM(sup_ver) &&
1547 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1553 generate_random_mac_addr(struct ether_addr *mac_addr)
1557 /* Set Organizationally Unique Identifier (OUI) prefix. */
1558 mac_addr->addr_bytes[0] = 0x00;
1559 mac_addr->addr_bytes[1] = 0x09;
1560 mac_addr->addr_bytes[2] = 0xC0;
1561 /* Force indication of locally assigned MAC address. */
1562 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1563 /* Generate the last 3 bytes of the MAC address with a random number. */
1564 random = rte_rand();
1565 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1569 * Virtual Function device init
1572 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1576 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1577 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1578 struct ixgbe_hw *hw =
1579 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1580 struct ixgbe_vfta *shadow_vfta =
1581 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1582 struct ixgbe_hwstrip *hwstrip =
1583 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1584 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1586 PMD_INIT_FUNC_TRACE();
1588 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1589 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1590 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1592 /* for secondary processes, we don't initialise any further as primary
1593 * has already done this work. Only check we don't need a different
1596 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1597 struct ixgbe_tx_queue *txq;
1598 /* TX queue function in primary, set by last queue initialized
1599 * Tx queue may not initialized by primary process
1601 if (eth_dev->data->tx_queues) {
1602 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1603 ixgbe_set_tx_function(eth_dev, txq);
1605 /* Use default TX function if we get here */
1606 PMD_INIT_LOG(NOTICE,
1607 "No TX queues configured yet. Using default TX function.");
1610 ixgbe_set_rx_function(eth_dev);
1615 rte_eth_copy_pci_info(eth_dev, pci_dev);
1616 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1618 hw->device_id = pci_dev->id.device_id;
1619 hw->vendor_id = pci_dev->id.vendor_id;
1620 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1622 /* initialize the vfta */
1623 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1625 /* initialize the hw strip bitmap*/
1626 memset(hwstrip, 0, sizeof(*hwstrip));
1628 /* Initialize the shared code (base driver) */
1629 diag = ixgbe_init_shared_code(hw);
1630 if (diag != IXGBE_SUCCESS) {
1631 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1635 /* init_mailbox_params */
1636 hw->mbx.ops.init_params(hw);
1638 /* Reset the hw statistics */
1639 ixgbevf_dev_stats_reset(eth_dev);
1641 /* Disable the interrupts for VF */
1642 ixgbevf_intr_disable(hw);
1644 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1645 diag = hw->mac.ops.reset_hw(hw);
1648 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1649 * the underlying PF driver has not assigned a MAC address to the VF.
1650 * In this case, assign a random MAC address.
1652 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1653 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1657 /* negotiate mailbox API version to use with the PF. */
1658 ixgbevf_negotiate_api(hw);
1660 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1661 ixgbevf_get_queues(hw, &tcs, &tc);
1663 /* Allocate memory for storing MAC addresses */
1664 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1665 hw->mac.num_rar_entries, 0);
1666 if (eth_dev->data->mac_addrs == NULL) {
1668 "Failed to allocate %u bytes needed to store "
1670 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1674 /* Generate a random MAC address, if none was assigned by PF. */
1675 if (is_zero_ether_addr(perm_addr)) {
1676 generate_random_mac_addr(perm_addr);
1677 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1679 rte_free(eth_dev->data->mac_addrs);
1680 eth_dev->data->mac_addrs = NULL;
1683 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1684 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1685 "%02x:%02x:%02x:%02x:%02x:%02x",
1686 perm_addr->addr_bytes[0],
1687 perm_addr->addr_bytes[1],
1688 perm_addr->addr_bytes[2],
1689 perm_addr->addr_bytes[3],
1690 perm_addr->addr_bytes[4],
1691 perm_addr->addr_bytes[5]);
1694 /* Copy the permanent MAC address */
1695 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1697 /* reset the hardware with the new settings */
1698 diag = hw->mac.ops.start_hw(hw);
1704 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1708 rte_intr_callback_register(intr_handle,
1709 ixgbevf_dev_interrupt_handler, eth_dev);
1710 rte_intr_enable(intr_handle);
1711 ixgbevf_intr_enable(hw);
1713 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1714 eth_dev->data->port_id, pci_dev->id.vendor_id,
1715 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1720 /* Virtual Function device uninit */
1723 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1725 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1726 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1727 struct ixgbe_hw *hw;
1729 PMD_INIT_FUNC_TRACE();
1731 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1734 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1736 if (hw->adapter_stopped == 0)
1737 ixgbevf_dev_close(eth_dev);
1739 eth_dev->dev_ops = NULL;
1740 eth_dev->rx_pkt_burst = NULL;
1741 eth_dev->tx_pkt_burst = NULL;
1743 /* Disable the interrupts for VF */
1744 ixgbevf_intr_disable(hw);
1746 rte_free(eth_dev->data->mac_addrs);
1747 eth_dev->data->mac_addrs = NULL;
1749 rte_intr_disable(intr_handle);
1750 rte_intr_callback_unregister(intr_handle,
1751 ixgbevf_dev_interrupt_handler, eth_dev);
1756 static struct eth_driver rte_ixgbe_pmd = {
1758 .id_table = pci_id_ixgbe_map,
1759 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1760 .probe = rte_eth_dev_pci_probe,
1761 .remove = rte_eth_dev_pci_remove,
1763 .eth_dev_init = eth_ixgbe_dev_init,
1764 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1765 .dev_private_size = sizeof(struct ixgbe_adapter),
1769 * virtual function driver struct
1771 static struct eth_driver rte_ixgbevf_pmd = {
1773 .id_table = pci_id_ixgbevf_map,
1774 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1775 .probe = rte_eth_dev_pci_probe,
1776 .remove = rte_eth_dev_pci_remove,
1778 .eth_dev_init = eth_ixgbevf_dev_init,
1779 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1780 .dev_private_size = sizeof(struct ixgbe_adapter),
1784 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1786 struct ixgbe_hw *hw =
1787 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1788 struct ixgbe_vfta *shadow_vfta =
1789 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1794 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1795 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1796 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1801 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1803 /* update local VFTA copy */
1804 shadow_vfta->vfta[vid_idx] = vfta;
1810 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1813 ixgbe_vlan_hw_strip_enable(dev, queue);
1815 ixgbe_vlan_hw_strip_disable(dev, queue);
1819 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1820 enum rte_vlan_type vlan_type,
1823 struct ixgbe_hw *hw =
1824 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1830 qinq &= IXGBE_DMATXCTL_GDV;
1832 switch (vlan_type) {
1833 case ETH_VLAN_TYPE_INNER:
1835 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1836 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1837 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1838 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1839 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1840 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1841 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1844 PMD_DRV_LOG(ERR, "Inner type is not supported"
1848 case ETH_VLAN_TYPE_OUTER:
1850 /* Only the high 16-bits is valid */
1851 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1852 IXGBE_EXVET_VET_EXT_SHIFT);
1854 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1855 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1856 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1857 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1858 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1859 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1860 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1866 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1874 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1876 struct ixgbe_hw *hw =
1877 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1880 PMD_INIT_FUNC_TRACE();
1882 /* Filter Table Disable */
1883 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1884 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1886 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1890 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1892 struct ixgbe_hw *hw =
1893 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1894 struct ixgbe_vfta *shadow_vfta =
1895 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1899 PMD_INIT_FUNC_TRACE();
1901 /* Filter Table Enable */
1902 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1903 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1904 vlnctrl |= IXGBE_VLNCTRL_VFE;
1906 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1908 /* write whatever is in local vfta copy */
1909 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1910 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1914 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1916 struct ixgbe_hwstrip *hwstrip =
1917 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1918 struct ixgbe_rx_queue *rxq;
1920 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1924 IXGBE_SET_HWSTRIP(hwstrip, queue);
1926 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1928 if (queue >= dev->data->nb_rx_queues)
1931 rxq = dev->data->rx_queues[queue];
1934 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1936 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1940 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1942 struct ixgbe_hw *hw =
1943 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1946 PMD_INIT_FUNC_TRACE();
1948 if (hw->mac.type == ixgbe_mac_82598EB) {
1949 /* No queue level support */
1950 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1954 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1955 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1956 ctrl &= ~IXGBE_RXDCTL_VME;
1957 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1959 /* record those setting for HW strip per queue */
1960 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1964 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1966 struct ixgbe_hw *hw =
1967 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1970 PMD_INIT_FUNC_TRACE();
1972 if (hw->mac.type == ixgbe_mac_82598EB) {
1973 /* No queue level supported */
1974 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1978 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1979 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1980 ctrl |= IXGBE_RXDCTL_VME;
1981 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1983 /* record those setting for HW strip per queue */
1984 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1988 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1990 struct ixgbe_hw *hw =
1991 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1994 struct ixgbe_rx_queue *rxq;
1996 PMD_INIT_FUNC_TRACE();
1998 if (hw->mac.type == ixgbe_mac_82598EB) {
1999 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2000 ctrl &= ~IXGBE_VLNCTRL_VME;
2001 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2003 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2004 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2005 rxq = dev->data->rx_queues[i];
2006 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2007 ctrl &= ~IXGBE_RXDCTL_VME;
2008 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2010 /* record those setting for HW strip per queue */
2011 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2017 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2019 struct ixgbe_hw *hw =
2020 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023 struct ixgbe_rx_queue *rxq;
2025 PMD_INIT_FUNC_TRACE();
2027 if (hw->mac.type == ixgbe_mac_82598EB) {
2028 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2029 ctrl |= IXGBE_VLNCTRL_VME;
2030 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2032 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2033 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2034 rxq = dev->data->rx_queues[i];
2035 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2036 ctrl |= IXGBE_RXDCTL_VME;
2037 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2039 /* record those setting for HW strip per queue */
2040 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2046 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2048 struct ixgbe_hw *hw =
2049 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052 PMD_INIT_FUNC_TRACE();
2054 /* DMATXCTRL: Geric Double VLAN Disable */
2055 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2056 ctrl &= ~IXGBE_DMATXCTL_GDV;
2057 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2059 /* CTRL_EXT: Global Double VLAN Disable */
2060 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2061 ctrl &= ~IXGBE_EXTENDED_VLAN;
2062 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2067 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2069 struct ixgbe_hw *hw =
2070 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073 PMD_INIT_FUNC_TRACE();
2075 /* DMATXCTRL: Geric Double VLAN Enable */
2076 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2077 ctrl |= IXGBE_DMATXCTL_GDV;
2078 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2080 /* CTRL_EXT: Global Double VLAN Enable */
2081 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2082 ctrl |= IXGBE_EXTENDED_VLAN;
2083 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2085 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2086 if (hw->mac.type == ixgbe_mac_X550 ||
2087 hw->mac.type == ixgbe_mac_X550EM_x ||
2088 hw->mac.type == ixgbe_mac_X550EM_a) {
2089 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2090 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2091 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2095 * VET EXT field in the EXVET register = 0x8100 by default
2096 * So no need to change. Same to VT field of DMATXCTL register
2101 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2103 if (mask & ETH_VLAN_STRIP_MASK) {
2104 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2105 ixgbe_vlan_hw_strip_enable_all(dev);
2107 ixgbe_vlan_hw_strip_disable_all(dev);
2110 if (mask & ETH_VLAN_FILTER_MASK) {
2111 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2112 ixgbe_vlan_hw_filter_enable(dev);
2114 ixgbe_vlan_hw_filter_disable(dev);
2117 if (mask & ETH_VLAN_EXTEND_MASK) {
2118 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2119 ixgbe_vlan_hw_extend_enable(dev);
2121 ixgbe_vlan_hw_extend_disable(dev);
2126 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2128 struct ixgbe_hw *hw =
2129 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2130 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2131 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2133 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2134 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2138 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2140 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2145 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2148 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2154 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2155 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2161 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2163 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2164 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2165 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2166 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2168 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2169 /* check multi-queue mode */
2170 switch (dev_conf->rxmode.mq_mode) {
2171 case ETH_MQ_RX_VMDQ_DCB:
2172 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2174 case ETH_MQ_RX_VMDQ_DCB_RSS:
2175 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2176 PMD_INIT_LOG(ERR, "SRIOV active,"
2177 " unsupported mq_mode rx %d.",
2178 dev_conf->rxmode.mq_mode);
2181 case ETH_MQ_RX_VMDQ_RSS:
2182 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2183 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2184 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2185 PMD_INIT_LOG(ERR, "SRIOV is active,"
2186 " invalid queue number"
2187 " for VMDQ RSS, allowed"
2188 " value are 1, 2 or 4.");
2192 case ETH_MQ_RX_VMDQ_ONLY:
2193 case ETH_MQ_RX_NONE:
2194 /* if nothing mq mode configure, use default scheme */
2195 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2196 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2197 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2199 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2200 /* SRIOV only works in VMDq enable mode */
2201 PMD_INIT_LOG(ERR, "SRIOV is active,"
2202 " wrong mq_mode rx %d.",
2203 dev_conf->rxmode.mq_mode);
2207 switch (dev_conf->txmode.mq_mode) {
2208 case ETH_MQ_TX_VMDQ_DCB:
2209 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2210 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2212 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2213 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2217 /* check valid queue number */
2218 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2219 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2220 PMD_INIT_LOG(ERR, "SRIOV is active,"
2221 " nb_rx_q=%d nb_tx_q=%d queue number"
2222 " must be less than or equal to %d.",
2224 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2228 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2229 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2233 /* check configuration for vmdb+dcb mode */
2234 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2235 const struct rte_eth_vmdq_dcb_conf *conf;
2237 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2238 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2239 IXGBE_VMDQ_DCB_NB_QUEUES);
2242 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2243 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2244 conf->nb_queue_pools == ETH_32_POOLS)) {
2245 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2246 " nb_queue_pools must be %d or %d.",
2247 ETH_16_POOLS, ETH_32_POOLS);
2251 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2252 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2254 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2255 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2256 IXGBE_VMDQ_DCB_NB_QUEUES);
2259 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2260 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2261 conf->nb_queue_pools == ETH_32_POOLS)) {
2262 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2263 " nb_queue_pools != %d and"
2264 " nb_queue_pools != %d.",
2265 ETH_16_POOLS, ETH_32_POOLS);
2270 /* For DCB mode check our configuration before we go further */
2271 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2272 const struct rte_eth_dcb_rx_conf *conf;
2274 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2275 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2276 IXGBE_DCB_NB_QUEUES);
2279 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2280 if (!(conf->nb_tcs == ETH_4_TCS ||
2281 conf->nb_tcs == ETH_8_TCS)) {
2282 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2283 " and nb_tcs != %d.",
2284 ETH_4_TCS, ETH_8_TCS);
2289 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2290 const struct rte_eth_dcb_tx_conf *conf;
2292 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2293 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2294 IXGBE_DCB_NB_QUEUES);
2297 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2298 if (!(conf->nb_tcs == ETH_4_TCS ||
2299 conf->nb_tcs == ETH_8_TCS)) {
2300 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2301 " and nb_tcs != %d.",
2302 ETH_4_TCS, ETH_8_TCS);
2308 * When DCB/VT is off, maximum number of queues changes,
2309 * except for 82598EB, which remains constant.
2311 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2312 hw->mac.type != ixgbe_mac_82598EB) {
2313 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2315 "Neither VT nor DCB are enabled, "
2317 IXGBE_NONE_MODE_TX_NB_QUEUES);
2326 ixgbe_dev_configure(struct rte_eth_dev *dev)
2328 struct ixgbe_interrupt *intr =
2329 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2330 struct ixgbe_adapter *adapter =
2331 (struct ixgbe_adapter *)dev->data->dev_private;
2334 PMD_INIT_FUNC_TRACE();
2335 /* multipe queue mode checking */
2336 ret = ixgbe_check_mq_mode(dev);
2338 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2343 /* set flag to update link status after init */
2344 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2347 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2348 * allocation or vector Rx preconditions we will reset it.
2350 adapter->rx_bulk_alloc_allowed = true;
2351 adapter->rx_vec_allowed = true;
2357 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2359 struct ixgbe_hw *hw =
2360 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2361 struct ixgbe_interrupt *intr =
2362 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2365 /* only set up it on X550EM_X */
2366 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2367 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2368 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2369 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2370 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2371 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2376 * Configure device link speed and setup link.
2377 * It returns 0 on success.
2380 ixgbe_dev_start(struct rte_eth_dev *dev)
2382 struct ixgbe_hw *hw =
2383 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384 struct ixgbe_vf_info *vfinfo =
2385 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2386 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2387 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2388 uint32_t intr_vector = 0;
2389 int err, link_up = 0, negotiate = 0;
2394 uint32_t *link_speeds;
2396 PMD_INIT_FUNC_TRACE();
2398 /* IXGBE devices don't support:
2399 * - half duplex (checked afterwards for valid speeds)
2400 * - fixed speed: TODO implement
2402 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2403 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2404 dev->data->port_id);
2408 /* disable uio/vfio intr/eventfd mapping */
2409 rte_intr_disable(intr_handle);
2412 hw->adapter_stopped = 0;
2413 ixgbe_stop_adapter(hw);
2415 /* reinitialize adapter
2416 * this calls reset and start
2418 status = ixgbe_pf_reset_hw(hw);
2421 hw->mac.ops.start_hw(hw);
2422 hw->mac.get_link_status = true;
2424 /* configure PF module if SRIOV enabled */
2425 ixgbe_pf_host_configure(dev);
2427 ixgbe_dev_phy_intr_setup(dev);
2429 /* check and configure queue intr-vector mapping */
2430 if ((rte_intr_cap_multiple(intr_handle) ||
2431 !RTE_ETH_DEV_SRIOV(dev).active) &&
2432 dev->data->dev_conf.intr_conf.rxq != 0) {
2433 intr_vector = dev->data->nb_rx_queues;
2434 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2435 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2436 IXGBE_MAX_INTR_QUEUE_NUM);
2439 if (rte_intr_efd_enable(intr_handle, intr_vector))
2443 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2444 intr_handle->intr_vec =
2445 rte_zmalloc("intr_vec",
2446 dev->data->nb_rx_queues * sizeof(int), 0);
2447 if (intr_handle->intr_vec == NULL) {
2448 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2449 " intr_vec\n", dev->data->nb_rx_queues);
2454 /* confiugre msix for sleep until rx interrupt */
2455 ixgbe_configure_msix(dev);
2457 /* initialize transmission unit */
2458 ixgbe_dev_tx_init(dev);
2460 /* This can fail when allocating mbufs for descriptor rings */
2461 err = ixgbe_dev_rx_init(dev);
2463 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2467 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2468 ETH_VLAN_EXTEND_MASK;
2469 ixgbe_vlan_offload_set(dev, mask);
2471 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2472 /* Enable vlan filtering for VMDq */
2473 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2476 /* Configure DCB hw */
2477 ixgbe_configure_dcb(dev);
2479 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2480 err = ixgbe_fdir_configure(dev);
2485 /* Restore vf rate limit */
2486 if (vfinfo != NULL) {
2487 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2488 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2489 if (vfinfo[vf].tx_rate[idx] != 0)
2490 rte_pmd_ixgbe_set_vf_rate_limit(
2491 dev->data->port_id, vf,
2492 vfinfo[vf].tx_rate[idx],
2496 ixgbe_restore_statistics_mapping(dev);
2498 err = ixgbe_dev_rxtx_start(dev);
2500 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2504 /* Skip link setup if loopback mode is enabled for 82599. */
2505 if (hw->mac.type == ixgbe_mac_82599EB &&
2506 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2507 goto skip_link_setup;
2509 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2510 err = hw->mac.ops.setup_sfp(hw);
2515 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2516 /* Turn on the copper */
2517 ixgbe_set_phy_power(hw, true);
2519 /* Turn on the laser */
2520 ixgbe_enable_tx_laser(hw);
2523 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2526 dev->data->dev_link.link_status = link_up;
2528 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2532 link_speeds = &dev->data->dev_conf.link_speeds;
2533 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2534 ETH_LINK_SPEED_10G)) {
2535 PMD_INIT_LOG(ERR, "Invalid link setting");
2540 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2541 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2542 IXGBE_LINK_SPEED_82599_AUTONEG :
2543 IXGBE_LINK_SPEED_82598_AUTONEG;
2545 if (*link_speeds & ETH_LINK_SPEED_10G)
2546 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2547 if (*link_speeds & ETH_LINK_SPEED_1G)
2548 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2549 if (*link_speeds & ETH_LINK_SPEED_100M)
2550 speed |= IXGBE_LINK_SPEED_100_FULL;
2553 err = ixgbe_setup_link(hw, speed, link_up);
2559 if (rte_intr_allow_others(intr_handle)) {
2560 /* check if lsc interrupt is enabled */
2561 if (dev->data->dev_conf.intr_conf.lsc != 0)
2562 ixgbe_dev_lsc_interrupt_setup(dev);
2563 ixgbe_dev_macsec_interrupt_setup(dev);
2565 rte_intr_callback_unregister(intr_handle,
2566 ixgbe_dev_interrupt_handler, dev);
2567 if (dev->data->dev_conf.intr_conf.lsc != 0)
2568 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2569 " no intr multiplex\n");
2572 /* check if rxq interrupt is enabled */
2573 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2574 rte_intr_dp_is_en(intr_handle))
2575 ixgbe_dev_rxq_interrupt_setup(dev);
2577 /* enable uio/vfio intr/eventfd mapping */
2578 rte_intr_enable(intr_handle);
2580 /* resume enabled intr since hw reset */
2581 ixgbe_enable_intr(dev);
2582 ixgbe_filter_restore(dev);
2587 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2588 ixgbe_dev_clear_queues(dev);
2593 * Stop device: disable rx and tx functions to allow for reconfiguring.
2596 ixgbe_dev_stop(struct rte_eth_dev *dev)
2598 struct rte_eth_link link;
2599 struct ixgbe_hw *hw =
2600 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2601 struct ixgbe_vf_info *vfinfo =
2602 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2603 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2604 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2607 PMD_INIT_FUNC_TRACE();
2609 /* disable interrupts */
2610 ixgbe_disable_intr(hw);
2613 ixgbe_pf_reset_hw(hw);
2614 hw->adapter_stopped = 0;
2617 ixgbe_stop_adapter(hw);
2619 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2620 vfinfo[vf].clear_to_send = false;
2622 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2623 /* Turn off the copper */
2624 ixgbe_set_phy_power(hw, false);
2626 /* Turn off the laser */
2627 ixgbe_disable_tx_laser(hw);
2630 ixgbe_dev_clear_queues(dev);
2632 /* Clear stored conf */
2633 dev->data->scattered_rx = 0;
2636 /* Clear recorded link status */
2637 memset(&link, 0, sizeof(link));
2638 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2640 if (!rte_intr_allow_others(intr_handle))
2641 /* resume to the default handler */
2642 rte_intr_callback_register(intr_handle,
2643 ixgbe_dev_interrupt_handler,
2646 /* Clean datapath event and queue/vec mapping */
2647 rte_intr_efd_disable(intr_handle);
2648 if (intr_handle->intr_vec != NULL) {
2649 rte_free(intr_handle->intr_vec);
2650 intr_handle->intr_vec = NULL;
2655 * Set device link up: enable tx.
2658 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2660 struct ixgbe_hw *hw =
2661 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2662 if (hw->mac.type == ixgbe_mac_82599EB) {
2663 #ifdef RTE_NIC_BYPASS
2664 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2665 /* Not suported in bypass mode */
2666 PMD_INIT_LOG(ERR, "Set link up is not supported "
2667 "by device id 0x%x", hw->device_id);
2673 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2674 /* Turn on the copper */
2675 ixgbe_set_phy_power(hw, true);
2677 /* Turn on the laser */
2678 ixgbe_enable_tx_laser(hw);
2685 * Set device link down: disable tx.
2688 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2690 struct ixgbe_hw *hw =
2691 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692 if (hw->mac.type == ixgbe_mac_82599EB) {
2693 #ifdef RTE_NIC_BYPASS
2694 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2695 /* Not suported in bypass mode */
2696 PMD_INIT_LOG(ERR, "Set link down is not supported "
2697 "by device id 0x%x", hw->device_id);
2703 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2704 /* Turn off the copper */
2705 ixgbe_set_phy_power(hw, false);
2707 /* Turn off the laser */
2708 ixgbe_disable_tx_laser(hw);
2715 * Reest and stop device.
2718 ixgbe_dev_close(struct rte_eth_dev *dev)
2720 struct ixgbe_hw *hw =
2721 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2723 PMD_INIT_FUNC_TRACE();
2725 ixgbe_pf_reset_hw(hw);
2727 ixgbe_dev_stop(dev);
2728 hw->adapter_stopped = 1;
2730 ixgbe_dev_free_queues(dev);
2732 ixgbe_disable_pcie_master(hw);
2734 /* reprogram the RAR[0] in case user changed it. */
2735 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2739 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2740 struct ixgbe_hw_stats *hw_stats,
2741 struct ixgbe_macsec_stats *macsec_stats,
2742 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2743 uint64_t *total_qprc, uint64_t *total_qprdc)
2745 uint32_t bprc, lxon, lxoff, total;
2746 uint32_t delta_gprc = 0;
2748 /* Workaround for RX byte count not including CRC bytes when CRC
2749 * strip is enabled. CRC bytes are removed from counters when crc_strip
2752 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2753 IXGBE_HLREG0_RXCRCSTRP);
2755 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2756 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2757 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2758 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2760 for (i = 0; i < 8; i++) {
2761 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2763 /* global total per queue */
2764 hw_stats->mpc[i] += mp;
2765 /* Running comprehensive total for stats display */
2766 *total_missed_rx += hw_stats->mpc[i];
2767 if (hw->mac.type == ixgbe_mac_82598EB) {
2768 hw_stats->rnbc[i] +=
2769 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2770 hw_stats->pxonrxc[i] +=
2771 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2772 hw_stats->pxoffrxc[i] +=
2773 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2775 hw_stats->pxonrxc[i] +=
2776 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2777 hw_stats->pxoffrxc[i] +=
2778 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2779 hw_stats->pxon2offc[i] +=
2780 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2782 hw_stats->pxontxc[i] +=
2783 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2784 hw_stats->pxofftxc[i] +=
2785 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2787 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2788 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2789 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2790 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2792 delta_gprc += delta_qprc;
2794 hw_stats->qprc[i] += delta_qprc;
2795 hw_stats->qptc[i] += delta_qptc;
2797 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2798 hw_stats->qbrc[i] +=
2799 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2801 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2803 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2804 hw_stats->qbtc[i] +=
2805 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2807 hw_stats->qprdc[i] += delta_qprdc;
2808 *total_qprdc += hw_stats->qprdc[i];
2810 *total_qprc += hw_stats->qprc[i];
2811 *total_qbrc += hw_stats->qbrc[i];
2813 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2814 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2815 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2818 * An errata states that gprc actually counts good + missed packets:
2819 * Workaround to set gprc to summated queue packet receives
2821 hw_stats->gprc = *total_qprc;
2823 if (hw->mac.type != ixgbe_mac_82598EB) {
2824 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2825 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2826 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2827 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2828 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2829 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2830 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2831 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2833 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2834 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2835 /* 82598 only has a counter in the high register */
2836 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2837 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2838 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2840 uint64_t old_tpr = hw_stats->tpr;
2842 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2843 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2846 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2848 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2849 hw_stats->gptc += delta_gptc;
2850 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2851 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2854 * Workaround: mprc hardware is incorrectly counting
2855 * broadcasts, so for now we subtract those.
2857 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2858 hw_stats->bprc += bprc;
2859 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2860 if (hw->mac.type == ixgbe_mac_82598EB)
2861 hw_stats->mprc -= bprc;
2863 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2864 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2865 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2866 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2867 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2868 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2870 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2871 hw_stats->lxontxc += lxon;
2872 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2873 hw_stats->lxofftxc += lxoff;
2874 total = lxon + lxoff;
2876 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2877 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2878 hw_stats->gptc -= total;
2879 hw_stats->mptc -= total;
2880 hw_stats->ptc64 -= total;
2881 hw_stats->gotc -= total * ETHER_MIN_LEN;
2883 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2884 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2885 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2886 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2887 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2888 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2889 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2890 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2891 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2892 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2893 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2894 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2895 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2896 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2897 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2898 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2899 /* Only read FCOE on 82599 */
2900 if (hw->mac.type != ixgbe_mac_82598EB) {
2901 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2902 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2903 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2904 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2905 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2908 /* Flow Director Stats registers */
2909 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2910 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2912 /* MACsec Stats registers */
2913 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2914 macsec_stats->out_pkts_encrypted +=
2915 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2916 macsec_stats->out_pkts_protected +=
2917 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2918 macsec_stats->out_octets_encrypted +=
2919 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2920 macsec_stats->out_octets_protected +=
2921 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2922 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2923 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2924 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2925 macsec_stats->in_pkts_unknownsci +=
2926 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2927 macsec_stats->in_octets_decrypted +=
2928 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2929 macsec_stats->in_octets_validated +=
2930 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2931 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2932 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2933 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2934 for (i = 0; i < 2; i++) {
2935 macsec_stats->in_pkts_ok +=
2936 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2937 macsec_stats->in_pkts_invalid +=
2938 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2939 macsec_stats->in_pkts_notvalid +=
2940 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2942 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2943 macsec_stats->in_pkts_notusingsa +=
2944 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2948 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2951 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2953 struct ixgbe_hw *hw =
2954 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955 struct ixgbe_hw_stats *hw_stats =
2956 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2957 struct ixgbe_macsec_stats *macsec_stats =
2958 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2959 dev->data->dev_private);
2960 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2963 total_missed_rx = 0;
2968 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2969 &total_qbrc, &total_qprc, &total_qprdc);
2974 /* Fill out the rte_eth_stats statistics structure */
2975 stats->ipackets = total_qprc;
2976 stats->ibytes = total_qbrc;
2977 stats->opackets = hw_stats->gptc;
2978 stats->obytes = hw_stats->gotc;
2980 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2981 stats->q_ipackets[i] = hw_stats->qprc[i];
2982 stats->q_opackets[i] = hw_stats->qptc[i];
2983 stats->q_ibytes[i] = hw_stats->qbrc[i];
2984 stats->q_obytes[i] = hw_stats->qbtc[i];
2985 stats->q_errors[i] = hw_stats->qprdc[i];
2989 stats->imissed = total_missed_rx;
2990 stats->ierrors = hw_stats->crcerrs +
3006 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3008 struct ixgbe_hw_stats *stats =
3009 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3011 /* HW registers are cleared on read */
3012 ixgbe_dev_stats_get(dev, NULL);
3014 /* Reset software totals */
3015 memset(stats, 0, sizeof(*stats));
3018 /* This function calculates the number of xstats based on the current config */
3020 ixgbe_xstats_calc_num(void) {
3021 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3022 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3023 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3026 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3027 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3029 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3030 unsigned stat, i, count;
3032 if (xstats_names != NULL) {
3035 /* Note: limit >= cnt_stats checked upstream
3036 * in rte_eth_xstats_names()
3039 /* Extended stats from ixgbe_hw_stats */
3040 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3041 snprintf(xstats_names[count].name,
3042 sizeof(xstats_names[count].name),
3044 rte_ixgbe_stats_strings[i].name);
3049 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3050 snprintf(xstats_names[count].name,
3051 sizeof(xstats_names[count].name),
3053 rte_ixgbe_macsec_strings[i].name);
3057 /* RX Priority Stats */
3058 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3059 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3060 snprintf(xstats_names[count].name,
3061 sizeof(xstats_names[count].name),
3062 "rx_priority%u_%s", i,
3063 rte_ixgbe_rxq_strings[stat].name);
3068 /* TX Priority Stats */
3069 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3070 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3071 snprintf(xstats_names[count].name,
3072 sizeof(xstats_names[count].name),
3073 "tx_priority%u_%s", i,
3074 rte_ixgbe_txq_strings[stat].name);
3082 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3083 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3087 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3090 if (xstats_names != NULL)
3091 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3092 snprintf(xstats_names[i].name,
3093 sizeof(xstats_names[i].name),
3094 "%s", rte_ixgbevf_stats_strings[i].name);
3095 return IXGBEVF_NB_XSTATS;
3099 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3102 struct ixgbe_hw *hw =
3103 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3104 struct ixgbe_hw_stats *hw_stats =
3105 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3106 struct ixgbe_macsec_stats *macsec_stats =
3107 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3108 dev->data->dev_private);
3109 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3110 unsigned i, stat, count = 0;
3112 count = ixgbe_xstats_calc_num();
3117 total_missed_rx = 0;
3122 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3123 &total_qbrc, &total_qprc, &total_qprdc);
3125 /* If this is a reset xstats is NULL, and we have cleared the
3126 * registers by reading them.
3131 /* Extended stats from ixgbe_hw_stats */
3133 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3134 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3135 rte_ixgbe_stats_strings[i].offset);
3136 xstats[count].id = count;
3141 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3142 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3143 rte_ixgbe_macsec_strings[i].offset);
3144 xstats[count].id = count;
3148 /* RX Priority Stats */
3149 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3150 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3151 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3152 rte_ixgbe_rxq_strings[stat].offset +
3153 (sizeof(uint64_t) * i));
3154 xstats[count].id = count;
3159 /* TX Priority Stats */
3160 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3161 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3162 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3163 rte_ixgbe_txq_strings[stat].offset +
3164 (sizeof(uint64_t) * i));
3165 xstats[count].id = count;
3173 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3175 struct ixgbe_hw_stats *stats =
3176 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3177 struct ixgbe_macsec_stats *macsec_stats =
3178 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3179 dev->data->dev_private);
3181 unsigned count = ixgbe_xstats_calc_num();
3183 /* HW registers are cleared on read */
3184 ixgbe_dev_xstats_get(dev, NULL, count);
3186 /* Reset software totals */
3187 memset(stats, 0, sizeof(*stats));
3188 memset(macsec_stats, 0, sizeof(*macsec_stats));
3192 ixgbevf_update_stats(struct rte_eth_dev *dev)
3194 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3195 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3196 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3198 /* Good Rx packet, include VF loopback */
3199 UPDATE_VF_STAT(IXGBE_VFGPRC,
3200 hw_stats->last_vfgprc, hw_stats->vfgprc);
3202 /* Good Rx octets, include VF loopback */
3203 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3204 hw_stats->last_vfgorc, hw_stats->vfgorc);
3206 /* Good Tx packet, include VF loopback */
3207 UPDATE_VF_STAT(IXGBE_VFGPTC,
3208 hw_stats->last_vfgptc, hw_stats->vfgptc);
3210 /* Good Tx octets, include VF loopback */
3211 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3212 hw_stats->last_vfgotc, hw_stats->vfgotc);
3214 /* Rx Multicst Packet */
3215 UPDATE_VF_STAT(IXGBE_VFMPRC,
3216 hw_stats->last_vfmprc, hw_stats->vfmprc);
3220 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3223 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3224 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3227 if (n < IXGBEVF_NB_XSTATS)
3228 return IXGBEVF_NB_XSTATS;
3230 ixgbevf_update_stats(dev);
3235 /* Extended stats */
3236 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3237 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3238 rte_ixgbevf_stats_strings[i].offset);
3241 return IXGBEVF_NB_XSTATS;
3245 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3247 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3248 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3250 ixgbevf_update_stats(dev);
3255 stats->ipackets = hw_stats->vfgprc;
3256 stats->ibytes = hw_stats->vfgorc;
3257 stats->opackets = hw_stats->vfgptc;
3258 stats->obytes = hw_stats->vfgotc;
3262 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3264 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3265 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3267 /* Sync HW register to the last stats */
3268 ixgbevf_dev_stats_get(dev, NULL);
3270 /* reset HW current stats*/
3271 hw_stats->vfgprc = 0;
3272 hw_stats->vfgorc = 0;
3273 hw_stats->vfgptc = 0;
3274 hw_stats->vfgotc = 0;
3278 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3280 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281 u16 eeprom_verh, eeprom_verl;
3285 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3286 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3288 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3289 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3291 ret += 1; /* add the size of '\0' */
3292 if (fw_size < (u32)ret)
3299 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3301 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3302 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3303 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3305 dev_info->pci_dev = pci_dev;
3306 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3307 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3308 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3310 * When DCB/VT is off, maximum number of queues changes,
3311 * except for 82598EB, which remains constant.
3313 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3314 hw->mac.type != ixgbe_mac_82598EB)
3315 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3317 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3318 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3319 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3320 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3321 dev_info->max_vfs = pci_dev->max_vfs;
3322 if (hw->mac.type == ixgbe_mac_82598EB)
3323 dev_info->max_vmdq_pools = ETH_16_POOLS;
3325 dev_info->max_vmdq_pools = ETH_64_POOLS;
3326 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3327 dev_info->rx_offload_capa =
3328 DEV_RX_OFFLOAD_VLAN_STRIP |
3329 DEV_RX_OFFLOAD_IPV4_CKSUM |
3330 DEV_RX_OFFLOAD_UDP_CKSUM |
3331 DEV_RX_OFFLOAD_TCP_CKSUM;
3334 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3337 if ((hw->mac.type == ixgbe_mac_82599EB ||
3338 hw->mac.type == ixgbe_mac_X540) &&
3339 !RTE_ETH_DEV_SRIOV(dev).active)
3340 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3342 if (hw->mac.type == ixgbe_mac_82599EB ||
3343 hw->mac.type == ixgbe_mac_X540)
3344 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3346 if (hw->mac.type == ixgbe_mac_X550 ||
3347 hw->mac.type == ixgbe_mac_X550EM_x ||
3348 hw->mac.type == ixgbe_mac_X550EM_a)
3349 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3351 dev_info->tx_offload_capa =
3352 DEV_TX_OFFLOAD_VLAN_INSERT |
3353 DEV_TX_OFFLOAD_IPV4_CKSUM |
3354 DEV_TX_OFFLOAD_UDP_CKSUM |
3355 DEV_TX_OFFLOAD_TCP_CKSUM |
3356 DEV_TX_OFFLOAD_SCTP_CKSUM |
3357 DEV_TX_OFFLOAD_TCP_TSO;
3359 if (hw->mac.type == ixgbe_mac_82599EB ||
3360 hw->mac.type == ixgbe_mac_X540)
3361 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3363 if (hw->mac.type == ixgbe_mac_X550 ||
3364 hw->mac.type == ixgbe_mac_X550EM_x ||
3365 hw->mac.type == ixgbe_mac_X550EM_a)
3366 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3368 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3370 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3371 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3372 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3374 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3378 dev_info->default_txconf = (struct rte_eth_txconf) {
3380 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3381 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3382 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3384 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3385 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3386 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3387 ETH_TXQ_FLAGS_NOOFFLOADS,
3390 dev_info->rx_desc_lim = rx_desc_lim;
3391 dev_info->tx_desc_lim = tx_desc_lim;
3393 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3394 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3395 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3397 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3398 if (hw->mac.type == ixgbe_mac_X540 ||
3399 hw->mac.type == ixgbe_mac_X540_vf ||
3400 hw->mac.type == ixgbe_mac_X550 ||
3401 hw->mac.type == ixgbe_mac_X550_vf) {
3402 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3406 static const uint32_t *
3407 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3409 static const uint32_t ptypes[] = {
3410 /* For non-vec functions,
3411 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3412 * for vec functions,
3413 * refers to _recv_raw_pkts_vec().
3417 RTE_PTYPE_L3_IPV4_EXT,
3419 RTE_PTYPE_L3_IPV6_EXT,
3423 RTE_PTYPE_TUNNEL_IP,
3424 RTE_PTYPE_INNER_L3_IPV6,
3425 RTE_PTYPE_INNER_L3_IPV6_EXT,
3426 RTE_PTYPE_INNER_L4_TCP,
3427 RTE_PTYPE_INNER_L4_UDP,
3431 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3432 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3433 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3434 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3440 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3441 struct rte_eth_dev_info *dev_info)
3443 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3444 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3446 dev_info->pci_dev = pci_dev;
3447 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3448 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3449 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3450 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3451 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3452 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3453 dev_info->max_vfs = pci_dev->max_vfs;
3454 if (hw->mac.type == ixgbe_mac_82598EB)
3455 dev_info->max_vmdq_pools = ETH_16_POOLS;
3457 dev_info->max_vmdq_pools = ETH_64_POOLS;
3458 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3459 DEV_RX_OFFLOAD_IPV4_CKSUM |
3460 DEV_RX_OFFLOAD_UDP_CKSUM |
3461 DEV_RX_OFFLOAD_TCP_CKSUM;
3462 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3463 DEV_TX_OFFLOAD_IPV4_CKSUM |
3464 DEV_TX_OFFLOAD_UDP_CKSUM |
3465 DEV_TX_OFFLOAD_TCP_CKSUM |
3466 DEV_TX_OFFLOAD_SCTP_CKSUM |
3467 DEV_TX_OFFLOAD_TCP_TSO;
3469 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3471 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3472 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3473 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3475 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3479 dev_info->default_txconf = (struct rte_eth_txconf) {
3481 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3482 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3483 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3485 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3486 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3487 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3488 ETH_TXQ_FLAGS_NOOFFLOADS,
3491 dev_info->rx_desc_lim = rx_desc_lim;
3492 dev_info->tx_desc_lim = tx_desc_lim;
3495 /* return 0 means link status changed, -1 means not changed */
3497 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3499 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3500 struct rte_eth_link link, old;
3501 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3505 link.link_status = ETH_LINK_DOWN;
3506 link.link_speed = 0;
3507 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3508 memset(&old, 0, sizeof(old));
3509 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3511 hw->mac.get_link_status = true;
3513 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3514 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3515 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3517 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3520 link.link_speed = ETH_SPEED_NUM_100M;
3521 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3522 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3523 if (link.link_status == old.link_status)
3529 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3530 if (link.link_status == old.link_status)
3534 link.link_status = ETH_LINK_UP;
3535 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3537 switch (link_speed) {
3539 case IXGBE_LINK_SPEED_UNKNOWN:
3540 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3541 link.link_speed = ETH_SPEED_NUM_100M;
3544 case IXGBE_LINK_SPEED_100_FULL:
3545 link.link_speed = ETH_SPEED_NUM_100M;
3548 case IXGBE_LINK_SPEED_1GB_FULL:
3549 link.link_speed = ETH_SPEED_NUM_1G;
3552 case IXGBE_LINK_SPEED_10GB_FULL:
3553 link.link_speed = ETH_SPEED_NUM_10G;
3556 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3558 if (link.link_status == old.link_status)
3565 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3567 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3570 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3571 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3572 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3576 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3578 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3581 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3582 fctrl &= (~IXGBE_FCTRL_UPE);
3583 if (dev->data->all_multicast == 1)
3584 fctrl |= IXGBE_FCTRL_MPE;
3586 fctrl &= (~IXGBE_FCTRL_MPE);
3587 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3591 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3593 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3596 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3597 fctrl |= IXGBE_FCTRL_MPE;
3598 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3602 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3604 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3607 if (dev->data->promiscuous == 1)
3608 return; /* must remain in all_multicast mode */
3610 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3611 fctrl &= (~IXGBE_FCTRL_MPE);
3612 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3616 * It clears the interrupt causes and enables the interrupt.
3617 * It will be called once only during nic initialized.
3620 * Pointer to struct rte_eth_dev.
3623 * - On success, zero.
3624 * - On failure, a negative value.
3627 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3629 struct ixgbe_interrupt *intr =
3630 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3632 ixgbe_dev_link_status_print(dev);
3633 intr->mask |= IXGBE_EICR_LSC;
3639 * It clears the interrupt causes and enables the interrupt.
3640 * It will be called once only during nic initialized.
3643 * Pointer to struct rte_eth_dev.
3646 * - On success, zero.
3647 * - On failure, a negative value.
3650 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3652 struct ixgbe_interrupt *intr =
3653 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3655 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3661 * It clears the interrupt causes and enables the interrupt.
3662 * It will be called once only during nic initialized.
3665 * Pointer to struct rte_eth_dev.
3668 * - On success, zero.
3669 * - On failure, a negative value.
3672 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3674 struct ixgbe_interrupt *intr =
3675 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3677 intr->mask |= IXGBE_EICR_LINKSEC;
3683 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3686 * Pointer to struct rte_eth_dev.
3689 * - On success, zero.
3690 * - On failure, a negative value.
3693 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3696 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3697 struct ixgbe_interrupt *intr =
3698 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3700 /* clear all cause mask */
3701 ixgbe_disable_intr(hw);
3703 /* read-on-clear nic registers here */
3704 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3705 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3709 /* set flag for async link update */
3710 if (eicr & IXGBE_EICR_LSC)
3711 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3713 if (eicr & IXGBE_EICR_MAILBOX)
3714 intr->flags |= IXGBE_FLAG_MAILBOX;
3716 if (eicr & IXGBE_EICR_LINKSEC)
3717 intr->flags |= IXGBE_FLAG_MACSEC;
3719 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3720 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3721 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3722 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3728 * It gets and then prints the link status.
3731 * Pointer to struct rte_eth_dev.
3734 * - On success, zero.
3735 * - On failure, a negative value.
3738 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3740 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3741 struct rte_eth_link link;
3743 memset(&link, 0, sizeof(link));
3744 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3745 if (link.link_status) {
3746 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3747 (int)(dev->data->port_id),
3748 (unsigned)link.link_speed,
3749 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3750 "full-duplex" : "half-duplex");
3752 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3753 (int)(dev->data->port_id));
3755 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3756 pci_dev->addr.domain,
3758 pci_dev->addr.devid,
3759 pci_dev->addr.function);
3763 * It executes link_update after knowing an interrupt occurred.
3766 * Pointer to struct rte_eth_dev.
3769 * - On success, zero.
3770 * - On failure, a negative value.
3773 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3774 struct rte_intr_handle *intr_handle)
3776 struct ixgbe_interrupt *intr =
3777 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3779 struct rte_eth_link link;
3780 int intr_enable_delay = false;
3781 struct ixgbe_hw *hw =
3782 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3784 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3786 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3787 ixgbe_pf_mbx_process(dev);
3788 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3791 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3792 ixgbe_handle_lasi(hw);
3793 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3796 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3797 /* get the link status before link update, for predicting later */
3798 memset(&link, 0, sizeof(link));
3799 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3801 ixgbe_dev_link_update(dev, 0);
3804 if (!link.link_status)
3805 /* handle it 1 sec later, wait it being stable */
3806 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3807 /* likely to down */
3809 /* handle it 4 sec later, wait it being stable */
3810 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3812 ixgbe_dev_link_status_print(dev);
3814 intr_enable_delay = true;
3817 if (intr_enable_delay) {
3818 if (rte_eal_alarm_set(timeout * 1000,
3819 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3820 PMD_DRV_LOG(ERR, "Error setting alarm");
3822 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3823 ixgbe_enable_intr(dev);
3824 rte_intr_enable(intr_handle);
3832 * Interrupt handler which shall be registered for alarm callback for delayed
3833 * handling specific interrupt to wait for the stable nic state. As the
3834 * NIC interrupt state is not stable for ixgbe after link is just down,
3835 * it needs to wait 4 seconds to get the stable status.
3838 * Pointer to interrupt handle.
3840 * The address of parameter (struct rte_eth_dev *) regsitered before.
3846 ixgbe_dev_interrupt_delayed_handler(void *param)
3848 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3849 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3850 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3851 struct ixgbe_interrupt *intr =
3852 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3853 struct ixgbe_hw *hw =
3854 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3857 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3858 if (eicr & IXGBE_EICR_MAILBOX)
3859 ixgbe_pf_mbx_process(dev);
3861 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3862 ixgbe_handle_lasi(hw);
3863 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3866 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3867 ixgbe_dev_link_update(dev, 0);
3868 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3869 ixgbe_dev_link_status_print(dev);
3870 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3873 if (intr->flags & IXGBE_FLAG_MACSEC) {
3874 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3876 intr->flags &= ~IXGBE_FLAG_MACSEC;
3879 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3880 ixgbe_enable_intr(dev);
3881 rte_intr_enable(intr_handle);
3885 * Interrupt handler triggered by NIC for handling
3886 * specific interrupt.
3889 * Pointer to interrupt handle.
3891 * The address of parameter (struct rte_eth_dev *) regsitered before.
3897 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3900 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3902 ixgbe_dev_interrupt_get_status(dev);
3903 ixgbe_dev_interrupt_action(dev, handle);
3907 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3909 struct ixgbe_hw *hw;
3911 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3912 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3916 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3918 struct ixgbe_hw *hw;
3920 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3925 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3927 struct ixgbe_hw *hw;
3933 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3935 fc_conf->pause_time = hw->fc.pause_time;
3936 fc_conf->high_water = hw->fc.high_water[0];
3937 fc_conf->low_water = hw->fc.low_water[0];
3938 fc_conf->send_xon = hw->fc.send_xon;
3939 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3942 * Return rx_pause status according to actual setting of
3945 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3946 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3952 * Return tx_pause status according to actual setting of
3955 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3956 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3961 if (rx_pause && tx_pause)
3962 fc_conf->mode = RTE_FC_FULL;
3964 fc_conf->mode = RTE_FC_RX_PAUSE;
3966 fc_conf->mode = RTE_FC_TX_PAUSE;
3968 fc_conf->mode = RTE_FC_NONE;
3974 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3976 struct ixgbe_hw *hw;
3978 uint32_t rx_buf_size;
3979 uint32_t max_high_water;
3981 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3988 PMD_INIT_FUNC_TRACE();
3990 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3991 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3992 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3995 * At least reserve one Ethernet frame for watermark
3996 * high_water/low_water in kilo bytes for ixgbe
3998 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3999 if ((fc_conf->high_water > max_high_water) ||
4000 (fc_conf->high_water < fc_conf->low_water)) {
4001 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4002 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4006 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4007 hw->fc.pause_time = fc_conf->pause_time;
4008 hw->fc.high_water[0] = fc_conf->high_water;
4009 hw->fc.low_water[0] = fc_conf->low_water;
4010 hw->fc.send_xon = fc_conf->send_xon;
4011 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4013 err = ixgbe_fc_enable(hw);
4015 /* Not negotiated is not an error case */
4016 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4018 /* check if we want to forward MAC frames - driver doesn't have native
4019 * capability to do that, so we'll write the registers ourselves */
4021 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4023 /* set or clear MFLCN.PMCF bit depending on configuration */
4024 if (fc_conf->mac_ctrl_frame_fwd != 0)
4025 mflcn |= IXGBE_MFLCN_PMCF;
4027 mflcn &= ~IXGBE_MFLCN_PMCF;
4029 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4030 IXGBE_WRITE_FLUSH(hw);
4035 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4040 * ixgbe_pfc_enable_generic - Enable flow control
4041 * @hw: pointer to hardware structure
4042 * @tc_num: traffic class number
4043 * Enable flow control according to the current settings.
4046 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4049 uint32_t mflcn_reg, fccfg_reg;
4051 uint32_t fcrtl, fcrth;
4055 /* Validate the water mark configuration */
4056 if (!hw->fc.pause_time) {
4057 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4061 /* Low water mark of zero causes XOFF floods */
4062 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4063 /* High/Low water can not be 0 */
4064 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4065 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4066 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4070 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4071 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4072 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4076 /* Negotiate the fc mode to use */
4077 ixgbe_fc_autoneg(hw);
4079 /* Disable any previous flow control settings */
4080 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4081 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4083 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4084 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4086 switch (hw->fc.current_mode) {
4089 * If the count of enabled RX Priority Flow control >1,
4090 * and the TX pause can not be disabled
4093 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4094 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4095 if (reg & IXGBE_FCRTH_FCEN)
4099 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4101 case ixgbe_fc_rx_pause:
4103 * Rx Flow control is enabled and Tx Flow control is
4104 * disabled by software override. Since there really
4105 * isn't a way to advertise that we are capable of RX
4106 * Pause ONLY, we will advertise that we support both
4107 * symmetric and asymmetric Rx PAUSE. Later, we will
4108 * disable the adapter's ability to send PAUSE frames.
4110 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4112 * If the count of enabled RX Priority Flow control >1,
4113 * and the TX pause can not be disabled
4116 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4117 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4118 if (reg & IXGBE_FCRTH_FCEN)
4122 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4124 case ixgbe_fc_tx_pause:
4126 * Tx Flow control is enabled, and Rx Flow control is
4127 * disabled by software override.
4129 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4132 /* Flow control (both Rx and Tx) is enabled by SW override. */
4133 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4134 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4137 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4138 ret_val = IXGBE_ERR_CONFIG;
4142 /* Set 802.3x based flow control settings. */
4143 mflcn_reg |= IXGBE_MFLCN_DPF;
4144 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4145 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4147 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4148 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4149 hw->fc.high_water[tc_num]) {
4150 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4151 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4152 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4154 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4156 * In order to prevent Tx hangs when the internal Tx
4157 * switch is enabled we must set the high water mark
4158 * to the maximum FCRTH value. This allows the Tx
4159 * switch to function even under heavy Rx workloads.
4161 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4163 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4165 /* Configure pause time (2 TCs per register) */
4166 reg = hw->fc.pause_time * 0x00010001;
4167 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4168 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4170 /* Configure flow control refresh threshold value */
4171 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4178 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4180 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4181 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4183 if (hw->mac.type != ixgbe_mac_82598EB) {
4184 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4190 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4193 uint32_t rx_buf_size;
4194 uint32_t max_high_water;
4196 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4197 struct ixgbe_hw *hw =
4198 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199 struct ixgbe_dcb_config *dcb_config =
4200 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4202 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4209 PMD_INIT_FUNC_TRACE();
4211 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4212 tc_num = map[pfc_conf->priority];
4213 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4214 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4216 * At least reserve one Ethernet frame for watermark
4217 * high_water/low_water in kilo bytes for ixgbe
4219 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4220 if ((pfc_conf->fc.high_water > max_high_water) ||
4221 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4222 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4223 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4227 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4228 hw->fc.pause_time = pfc_conf->fc.pause_time;
4229 hw->fc.send_xon = pfc_conf->fc.send_xon;
4230 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4231 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4233 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4235 /* Not negotiated is not an error case */
4236 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4239 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4244 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4245 struct rte_eth_rss_reta_entry64 *reta_conf,
4248 uint16_t i, sp_reta_size;
4251 uint16_t idx, shift;
4252 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4255 PMD_INIT_FUNC_TRACE();
4257 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4258 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4263 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4264 if (reta_size != sp_reta_size) {
4265 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4266 "(%d) doesn't match the number hardware can supported "
4267 "(%d)\n", reta_size, sp_reta_size);
4271 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4272 idx = i / RTE_RETA_GROUP_SIZE;
4273 shift = i % RTE_RETA_GROUP_SIZE;
4274 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4278 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4279 if (mask == IXGBE_4_BIT_MASK)
4282 r = IXGBE_READ_REG(hw, reta_reg);
4283 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4284 if (mask & (0x1 << j))
4285 reta |= reta_conf[idx].reta[shift + j] <<
4288 reta |= r & (IXGBE_8_BIT_MASK <<
4291 IXGBE_WRITE_REG(hw, reta_reg, reta);
4298 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4299 struct rte_eth_rss_reta_entry64 *reta_conf,
4302 uint16_t i, sp_reta_size;
4305 uint16_t idx, shift;
4306 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4309 PMD_INIT_FUNC_TRACE();
4310 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4311 if (reta_size != sp_reta_size) {
4312 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4313 "(%d) doesn't match the number hardware can supported "
4314 "(%d)\n", reta_size, sp_reta_size);
4318 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4319 idx = i / RTE_RETA_GROUP_SIZE;
4320 shift = i % RTE_RETA_GROUP_SIZE;
4321 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4326 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4327 reta = IXGBE_READ_REG(hw, reta_reg);
4328 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4329 if (mask & (0x1 << j))
4330 reta_conf[idx].reta[shift + j] =
4331 ((reta >> (CHAR_BIT * j)) &
4340 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4341 uint32_t index, uint32_t pool)
4343 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4344 uint32_t enable_addr = 1;
4346 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4350 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4352 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4354 ixgbe_clear_rar(hw, index);
4358 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4360 ixgbe_remove_rar(dev, 0);
4362 ixgbe_add_rar(dev, addr, 0, 0);
4366 is_ixgbe_pmd(const char *driver_name)
4368 if (!strstr(driver_name, "ixgbe"))
4371 if (strstr(driver_name, "ixgbe_vf"))
4378 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4379 struct ether_addr *mac_addr)
4381 struct ixgbe_hw *hw;
4382 struct ixgbe_vf_info *vfinfo;
4384 uint8_t *new_mac = (uint8_t *)(mac_addr);
4385 struct rte_eth_dev *dev;
4386 struct rte_eth_dev_info dev_info;
4388 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4390 dev = &rte_eth_devices[port];
4391 rte_eth_dev_info_get(port, &dev_info);
4393 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4396 if (vf >= dev_info.max_vfs)
4399 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4400 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4401 rar_entry = hw->mac.num_rar_entries - (vf + 1);
4403 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4404 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4406 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4413 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4417 struct ixgbe_hw *hw;
4418 struct rte_eth_dev_info dev_info;
4419 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4421 ixgbe_dev_info_get(dev, &dev_info);
4423 /* check that mtu is within the allowed range */
4424 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4427 /* refuse mtu that requires the support of scattered packets when this
4428 * feature has not been enabled before.
4430 if (!dev->data->scattered_rx &&
4431 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4432 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4435 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4436 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4438 /* switch to jumbo mode if needed */
4439 if (frame_size > ETHER_MAX_LEN) {
4440 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4441 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4443 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4444 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4446 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4448 /* update max frame size */
4449 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4451 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4452 maxfrs &= 0x0000FFFF;
4453 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4454 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4460 * Virtual Function operations
4463 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4465 PMD_INIT_FUNC_TRACE();
4467 /* Clear interrupt mask to stop from interrupts being generated */
4468 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4470 IXGBE_WRITE_FLUSH(hw);
4474 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4476 PMD_INIT_FUNC_TRACE();
4478 /* VF enable interrupt autoclean */
4479 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4480 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4481 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4483 IXGBE_WRITE_FLUSH(hw);
4487 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4489 struct rte_eth_conf *conf = &dev->data->dev_conf;
4490 struct ixgbe_adapter *adapter =
4491 (struct ixgbe_adapter *)dev->data->dev_private;
4493 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4494 dev->data->port_id);
4497 * VF has no ability to enable/disable HW CRC
4498 * Keep the persistent behavior the same as Host PF
4500 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4501 if (!conf->rxmode.hw_strip_crc) {
4502 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4503 conf->rxmode.hw_strip_crc = 1;
4506 if (conf->rxmode.hw_strip_crc) {
4507 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4508 conf->rxmode.hw_strip_crc = 0;
4513 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4514 * allocation or vector Rx preconditions we will reset it.
4516 adapter->rx_bulk_alloc_allowed = true;
4517 adapter->rx_vec_allowed = true;
4523 ixgbevf_dev_start(struct rte_eth_dev *dev)
4525 struct ixgbe_hw *hw =
4526 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527 uint32_t intr_vector = 0;
4528 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4529 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4533 PMD_INIT_FUNC_TRACE();
4535 hw->mac.ops.reset_hw(hw);
4536 hw->mac.get_link_status = true;
4538 /* negotiate mailbox API version to use with the PF. */
4539 ixgbevf_negotiate_api(hw);
4541 ixgbevf_dev_tx_init(dev);
4543 /* This can fail when allocating mbufs for descriptor rings */
4544 err = ixgbevf_dev_rx_init(dev);
4546 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4547 ixgbe_dev_clear_queues(dev);
4552 ixgbevf_set_vfta_all(dev, 1);
4555 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4556 ETH_VLAN_EXTEND_MASK;
4557 ixgbevf_vlan_offload_set(dev, mask);
4559 ixgbevf_dev_rxtx_start(dev);
4561 /* check and configure queue intr-vector mapping */
4562 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4563 intr_vector = dev->data->nb_rx_queues;
4564 if (rte_intr_efd_enable(intr_handle, intr_vector))
4568 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4569 intr_handle->intr_vec =
4570 rte_zmalloc("intr_vec",
4571 dev->data->nb_rx_queues * sizeof(int), 0);
4572 if (intr_handle->intr_vec == NULL) {
4573 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4574 " intr_vec\n", dev->data->nb_rx_queues);
4578 ixgbevf_configure_msix(dev);
4580 rte_intr_enable(intr_handle);
4582 /* Re-enable interrupt for VF */
4583 ixgbevf_intr_enable(hw);
4589 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4591 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4592 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4593 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4595 PMD_INIT_FUNC_TRACE();
4597 ixgbevf_intr_disable(hw);
4599 hw->adapter_stopped = 1;
4600 ixgbe_stop_adapter(hw);
4603 * Clear what we set, but we still keep shadow_vfta to
4604 * restore after device starts
4606 ixgbevf_set_vfta_all(dev, 0);
4608 /* Clear stored conf */
4609 dev->data->scattered_rx = 0;
4611 ixgbe_dev_clear_queues(dev);
4613 /* Clean datapath event and queue/vec mapping */
4614 rte_intr_efd_disable(intr_handle);
4615 if (intr_handle->intr_vec != NULL) {
4616 rte_free(intr_handle->intr_vec);
4617 intr_handle->intr_vec = NULL;
4622 ixgbevf_dev_close(struct rte_eth_dev *dev)
4624 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4626 PMD_INIT_FUNC_TRACE();
4630 ixgbevf_dev_stop(dev);
4632 ixgbe_dev_free_queues(dev);
4635 * Remove the VF MAC address ro ensure
4636 * that the VF traffic goes to the PF
4637 * after stop, close and detach of the VF
4639 ixgbevf_remove_mac_addr(dev, 0);
4642 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4644 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4645 struct ixgbe_vfta *shadow_vfta =
4646 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4647 int i = 0, j = 0, vfta = 0, mask = 1;
4649 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4650 vfta = shadow_vfta->vfta[i];
4653 for (j = 0; j < 32; j++) {
4655 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4665 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4667 struct ixgbe_hw *hw =
4668 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4669 struct ixgbe_vfta *shadow_vfta =
4670 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4671 uint32_t vid_idx = 0;
4672 uint32_t vid_bit = 0;
4675 PMD_INIT_FUNC_TRACE();
4677 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4678 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4680 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4683 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4684 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4686 /* Save what we set and retore it after device reset */
4688 shadow_vfta->vfta[vid_idx] |= vid_bit;
4690 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4696 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4698 struct ixgbe_hw *hw =
4699 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702 PMD_INIT_FUNC_TRACE();
4704 if (queue >= hw->mac.max_rx_queues)
4707 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4709 ctrl |= IXGBE_RXDCTL_VME;
4711 ctrl &= ~IXGBE_RXDCTL_VME;
4712 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4714 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4718 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4720 struct ixgbe_hw *hw =
4721 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4725 /* VF function only support hw strip feature, others are not support */
4726 if (mask & ETH_VLAN_STRIP_MASK) {
4727 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4729 for (i = 0; i < hw->mac.max_rx_queues; i++)
4730 ixgbevf_vlan_strip_queue_set(dev, i, on);
4735 ixgbe_vt_check(struct ixgbe_hw *hw)
4739 /* if Virtualization Technology is enabled */
4740 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4741 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4742 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4750 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4752 uint32_t vector = 0;
4754 switch (hw->mac.mc_filter_type) {
4755 case 0: /* use bits [47:36] of the address */
4756 vector = ((uc_addr->addr_bytes[4] >> 4) |
4757 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4759 case 1: /* use bits [46:35] of the address */
4760 vector = ((uc_addr->addr_bytes[4] >> 3) |
4761 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4763 case 2: /* use bits [45:34] of the address */
4764 vector = ((uc_addr->addr_bytes[4] >> 2) |
4765 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4767 case 3: /* use bits [43:32] of the address */
4768 vector = ((uc_addr->addr_bytes[4]) |
4769 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4771 default: /* Invalid mc_filter_type */
4775 /* vector can only be 12-bits or boundary will be exceeded */
4781 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4789 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4790 const uint32_t ixgbe_uta_bit_shift = 5;
4791 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4792 const uint32_t bit1 = 0x1;
4794 struct ixgbe_hw *hw =
4795 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4796 struct ixgbe_uta_info *uta_info =
4797 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4799 /* The UTA table only exists on 82599 hardware and newer */
4800 if (hw->mac.type < ixgbe_mac_82599EB)
4803 vector = ixgbe_uta_vector(hw, mac_addr);
4804 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4805 uta_shift = vector & ixgbe_uta_bit_mask;
4807 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4811 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4813 uta_info->uta_in_use++;
4814 reg_val |= (bit1 << uta_shift);
4815 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4817 uta_info->uta_in_use--;
4818 reg_val &= ~(bit1 << uta_shift);
4819 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4822 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4824 if (uta_info->uta_in_use > 0)
4825 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4826 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4828 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4834 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4837 struct ixgbe_hw *hw =
4838 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839 struct ixgbe_uta_info *uta_info =
4840 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4842 /* The UTA table only exists on 82599 hardware and newer */
4843 if (hw->mac.type < ixgbe_mac_82599EB)
4847 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4848 uta_info->uta_shadow[i] = ~0;
4849 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4852 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4853 uta_info->uta_shadow[i] = 0;
4854 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4862 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4864 uint32_t new_val = orig_val;
4866 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4867 new_val |= IXGBE_VMOLR_AUPE;
4868 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4869 new_val |= IXGBE_VMOLR_ROMPE;
4870 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4871 new_val |= IXGBE_VMOLR_ROPE;
4872 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4873 new_val |= IXGBE_VMOLR_BAM;
4874 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4875 new_val |= IXGBE_VMOLR_MPE;
4882 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4884 struct ixgbe_hw *hw;
4885 struct ixgbe_mac_info *mac;
4886 struct rte_eth_dev *dev;
4887 struct rte_eth_dev_info dev_info;
4889 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4891 dev = &rte_eth_devices[port];
4892 rte_eth_dev_info_get(port, &dev_info);
4894 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4897 if (vf >= dev_info.max_vfs)
4903 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4906 mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4912 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4914 struct ixgbe_hw *hw;
4915 struct ixgbe_mac_info *mac;
4916 struct rte_eth_dev *dev;
4917 struct rte_eth_dev_info dev_info;
4919 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4921 dev = &rte_eth_devices[port];
4922 rte_eth_dev_info_get(port, &dev_info);
4924 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4927 if (vf >= dev_info.max_vfs)
4933 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4935 mac->ops.set_mac_anti_spoofing(hw, on, vf);
4941 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4943 struct ixgbe_hw *hw;
4945 struct rte_eth_dev *dev;
4946 struct rte_eth_dev_info dev_info;
4948 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4950 dev = &rte_eth_devices[port];
4951 rte_eth_dev_info_get(port, &dev_info);
4953 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4956 if (vf >= dev_info.max_vfs)
4959 if (vlan_id > ETHER_MAX_VLAN_ID)
4962 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4963 ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4966 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4971 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4977 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4979 struct ixgbe_hw *hw;
4981 struct rte_eth_dev *dev;
4982 struct rte_eth_dev_info dev_info;
4984 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4986 dev = &rte_eth_devices[port];
4987 rte_eth_dev_info_get(port, &dev_info);
4989 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4995 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4996 ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4997 /* enable or disable VMDQ loopback */
4999 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5001 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5003 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5009 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5011 struct ixgbe_hw *hw;
5014 int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5015 struct rte_eth_dev *dev;
5016 struct rte_eth_dev_info dev_info;
5018 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5020 dev = &rte_eth_devices[port];
5021 rte_eth_dev_info_get(port, &dev_info);
5023 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5029 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5030 for (i = 0; i <= num_queues; i++) {
5031 reg_value = IXGBE_QDE_WRITE |
5032 (i << IXGBE_QDE_IDX_SHIFT) |
5033 (on & IXGBE_QDE_ENABLE);
5034 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5041 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5043 struct ixgbe_hw *hw;
5045 struct rte_eth_dev *dev;
5046 struct rte_eth_dev_info dev_info;
5048 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5050 dev = &rte_eth_devices[port];
5051 rte_eth_dev_info_get(port, &dev_info);
5053 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5056 /* only support VF's 0 to 63 */
5057 if ((vf >= dev_info.max_vfs) || (vf > 63))
5063 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5064 reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5066 reg_value |= IXGBE_SRRCTL_DROP_EN;
5068 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5070 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5076 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5078 struct rte_eth_dev *dev;
5079 struct rte_eth_dev_info dev_info;
5080 uint16_t queues_per_pool;
5083 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5085 dev = &rte_eth_devices[port];
5086 rte_eth_dev_info_get(port, &dev_info);
5088 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5091 if (vf >= dev_info.max_vfs)
5097 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5099 /* The PF has 128 queue pairs and in SRIOV configuration
5100 * those queues will be assigned to VF's, so RXDCTL
5101 * registers will be dealing with queues which will be
5103 * Let's say we have SRIOV configured with 31 VF's then the
5104 * first 124 queues 0-123 will be allocated to VF's and only
5105 * the last 4 queues 123-127 will be assigned to the PF.
5108 queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5110 for (q = 0; q < queues_per_pool; q++)
5111 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5112 q + vf * queues_per_pool, on);
5117 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5120 struct rte_eth_dev *dev;
5121 struct rte_eth_dev_info dev_info;
5122 struct ixgbe_hw *hw;
5125 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5127 dev = &rte_eth_devices[port];
5128 rte_eth_dev_info_get(port, &dev_info);
5130 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5133 if (vf >= dev_info.max_vfs)
5139 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5142 if (hw->mac.type == ixgbe_mac_82598EB) {
5143 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5144 " on 82599 hardware and newer");
5147 if (ixgbe_vt_check(hw) < 0)
5150 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5157 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5163 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5165 struct rte_eth_dev *dev;
5166 struct rte_eth_dev_info dev_info;
5169 const uint8_t bit1 = 0x1;
5170 struct ixgbe_hw *hw;
5172 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5174 dev = &rte_eth_devices[port];
5175 rte_eth_dev_info_get(port, &dev_info);
5177 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5180 if (vf >= dev_info.max_vfs)
5186 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5188 if (ixgbe_vt_check(hw) < 0)
5191 /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5193 addr = IXGBE_VFRE(1);
5194 val = bit1 << (vf - 32);
5196 addr = IXGBE_VFRE(0);
5200 reg = IXGBE_READ_REG(hw, addr);
5207 IXGBE_WRITE_REG(hw, addr, reg);
5213 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5215 struct rte_eth_dev *dev;
5216 struct rte_eth_dev_info dev_info;
5219 const uint8_t bit1 = 0x1;
5221 struct ixgbe_hw *hw;
5223 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5225 dev = &rte_eth_devices[port];
5226 rte_eth_dev_info_get(port, &dev_info);
5228 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5231 if (vf >= dev_info.max_vfs)
5237 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5238 if (ixgbe_vt_check(hw) < 0)
5241 /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5243 addr = IXGBE_VFTE(1);
5244 val = bit1 << (vf - 32);
5246 addr = IXGBE_VFTE(0);
5250 reg = IXGBE_READ_REG(hw, addr);
5257 IXGBE_WRITE_REG(hw, addr, reg);
5263 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5264 uint64_t vf_mask, uint8_t vlan_on)
5266 struct rte_eth_dev *dev;
5267 struct rte_eth_dev_info dev_info;
5270 struct ixgbe_hw *hw;
5272 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5274 dev = &rte_eth_devices[port];
5275 rte_eth_dev_info_get(port, &dev_info);
5277 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5280 if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5283 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5284 if (ixgbe_vt_check(hw) < 0)
5287 for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5288 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5289 ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5299 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5300 uint16_t tx_rate, uint64_t q_msk)
5302 struct rte_eth_dev *dev;
5303 struct rte_eth_dev_info dev_info;
5304 struct ixgbe_hw *hw;
5305 struct ixgbe_vf_info *vfinfo;
5306 struct rte_eth_link link;
5307 uint8_t nb_q_per_pool;
5308 uint32_t queue_stride;
5309 uint32_t queue_idx, idx = 0, vf_idx;
5311 uint16_t total_rate = 0;
5312 struct rte_pci_device *pci_dev;
5314 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5316 dev = &rte_eth_devices[port];
5317 rte_eth_dev_info_get(port, &dev_info);
5318 rte_eth_link_get_nowait(port, &link);
5320 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5323 if (vf >= dev_info.max_vfs)
5326 if (tx_rate > link.link_speed)
5332 pci_dev = IXGBE_DEV_TO_PCI(dev);
5333 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5334 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5335 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5336 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5337 queue_idx = vf * queue_stride;
5338 queue_end = queue_idx + nb_q_per_pool - 1;
5339 if (queue_end >= hw->mac.max_tx_queues)
5343 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5346 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5348 total_rate += vfinfo[vf_idx].tx_rate[idx];
5354 /* Store tx_rate for this vf. */
5355 for (idx = 0; idx < nb_q_per_pool; idx++) {
5356 if (((uint64_t)0x1 << idx) & q_msk) {
5357 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5358 vfinfo[vf].tx_rate[idx] = tx_rate;
5359 total_rate += tx_rate;
5363 if (total_rate > dev->data->dev_link.link_speed) {
5364 /* Reset stored TX rate of the VF if it causes exceed
5367 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5371 /* Set RTTBCNRC of each queue/pool for vf X */
5372 for (; queue_idx <= queue_end; queue_idx++) {
5374 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5381 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5382 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5383 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5384 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5385 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5386 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5387 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5390 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5391 struct rte_eth_mirror_conf *mirror_conf,
5392 uint8_t rule_id, uint8_t on)
5394 uint32_t mr_ctl, vlvf;
5395 uint32_t mp_lsb = 0;
5396 uint32_t mv_msb = 0;
5397 uint32_t mv_lsb = 0;
5398 uint32_t mp_msb = 0;
5401 uint64_t vlan_mask = 0;
5403 const uint8_t pool_mask_offset = 32;
5404 const uint8_t vlan_mask_offset = 32;
5405 const uint8_t dst_pool_offset = 8;
5406 const uint8_t rule_mr_offset = 4;
5407 const uint8_t mirror_rule_mask = 0x0F;
5409 struct ixgbe_mirror_info *mr_info =
5410 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5411 struct ixgbe_hw *hw =
5412 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5413 uint8_t mirror_type = 0;
5415 if (ixgbe_vt_check(hw) < 0)
5418 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5421 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5422 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5423 mirror_conf->rule_type);
5427 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5428 mirror_type |= IXGBE_MRCTL_VLME;
5429 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5430 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5431 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5432 /* search vlan id related pool vlan filter index */
5433 reg_index = ixgbe_find_vlvf_slot(hw,
5434 mirror_conf->vlan.vlan_id[i],
5438 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5439 if ((vlvf & IXGBE_VLVF_VIEN) &&
5440 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5441 mirror_conf->vlan.vlan_id[i]))
5442 vlan_mask |= (1ULL << reg_index);
5449 mv_lsb = vlan_mask & 0xFFFFFFFF;
5450 mv_msb = vlan_mask >> vlan_mask_offset;
5452 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5453 mirror_conf->vlan.vlan_mask;
5454 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5455 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5456 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5457 mirror_conf->vlan.vlan_id[i];
5462 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5463 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5464 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5469 * if enable pool mirror, write related pool mask register,if disable
5470 * pool mirror, clear PFMRVM register
5472 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5473 mirror_type |= IXGBE_MRCTL_VPME;
5475 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5476 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5477 mr_info->mr_conf[rule_id].pool_mask =
5478 mirror_conf->pool_mask;
5483 mr_info->mr_conf[rule_id].pool_mask = 0;
5486 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5487 mirror_type |= IXGBE_MRCTL_UPME;
5488 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5489 mirror_type |= IXGBE_MRCTL_DPME;
5491 /* read mirror control register and recalculate it */
5492 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5495 mr_ctl |= mirror_type;
5496 mr_ctl &= mirror_rule_mask;
5497 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5499 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5501 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5502 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5504 /* write mirrror control register */
5505 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5507 /* write pool mirrror control register */
5508 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5509 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5510 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5513 /* write VLAN mirrror control register */
5514 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5515 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5516 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5524 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5527 uint32_t lsb_val = 0;
5528 uint32_t msb_val = 0;
5529 const uint8_t rule_mr_offset = 4;
5531 struct ixgbe_hw *hw =
5532 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5533 struct ixgbe_mirror_info *mr_info =
5534 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5536 if (ixgbe_vt_check(hw) < 0)
5539 memset(&mr_info->mr_conf[rule_id], 0,
5540 sizeof(struct rte_eth_mirror_conf));
5542 /* clear PFVMCTL register */
5543 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5545 /* clear pool mask register */
5546 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5547 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5549 /* clear vlan mask register */
5550 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5551 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5557 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5559 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5560 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5562 struct ixgbe_hw *hw =
5563 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5565 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5566 mask |= (1 << IXGBE_MISC_VEC_ID);
5567 RTE_SET_USED(queue_id);
5568 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5570 rte_intr_enable(intr_handle);
5576 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5579 struct ixgbe_hw *hw =
5580 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5582 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5583 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5584 RTE_SET_USED(queue_id);
5585 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5591 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5593 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5594 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5596 struct ixgbe_hw *hw =
5597 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5598 struct ixgbe_interrupt *intr =
5599 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5601 if (queue_id < 16) {
5602 ixgbe_disable_intr(hw);
5603 intr->mask |= (1 << queue_id);
5604 ixgbe_enable_intr(dev);
5605 } else if (queue_id < 32) {
5606 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5607 mask &= (1 << queue_id);
5608 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5609 } else if (queue_id < 64) {
5610 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5611 mask &= (1 << (queue_id - 32));
5612 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5614 rte_intr_enable(intr_handle);
5620 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5623 struct ixgbe_hw *hw =
5624 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5625 struct ixgbe_interrupt *intr =
5626 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5628 if (queue_id < 16) {
5629 ixgbe_disable_intr(hw);
5630 intr->mask &= ~(1 << queue_id);
5631 ixgbe_enable_intr(dev);
5632 } else if (queue_id < 32) {
5633 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5634 mask &= ~(1 << queue_id);
5635 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5636 } else if (queue_id < 64) {
5637 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5638 mask &= ~(1 << (queue_id - 32));
5639 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5646 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5647 uint8_t queue, uint8_t msix_vector)
5651 if (direction == -1) {
5653 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5654 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5657 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5659 /* rx or tx cause */
5660 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5661 idx = ((16 * (queue & 1)) + (8 * direction));
5662 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5663 tmp &= ~(0xFF << idx);
5664 tmp |= (msix_vector << idx);
5665 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5670 * set the IVAR registers, mapping interrupt causes to vectors
5672 * pointer to ixgbe_hw struct
5674 * 0 for Rx, 1 for Tx, -1 for other causes
5676 * queue to map the corresponding interrupt to
5678 * the vector to map to the corresponding queue
5681 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5682 uint8_t queue, uint8_t msix_vector)
5686 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5687 if (hw->mac.type == ixgbe_mac_82598EB) {
5688 if (direction == -1)
5690 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5691 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5692 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5693 tmp |= (msix_vector << (8 * (queue & 0x3)));
5694 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5695 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5696 (hw->mac.type == ixgbe_mac_X540)) {
5697 if (direction == -1) {
5699 idx = ((queue & 1) * 8);
5700 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5701 tmp &= ~(0xFF << idx);
5702 tmp |= (msix_vector << idx);
5703 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5705 /* rx or tx causes */
5706 idx = ((16 * (queue & 1)) + (8 * direction));
5707 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5708 tmp &= ~(0xFF << idx);
5709 tmp |= (msix_vector << idx);
5710 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5716 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5718 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5719 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5720 struct ixgbe_hw *hw =
5721 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5723 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5725 /* Configure VF other cause ivar */
5726 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5728 /* won't configure msix register if no mapping is done
5729 * between intr vector and event fd.
5731 if (!rte_intr_dp_is_en(intr_handle))
5734 /* Configure all RX queues of VF */
5735 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5736 /* Force all queue use vector 0,
5737 * as IXGBE_VF_MAXMSIVECOTR = 1
5739 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5740 intr_handle->intr_vec[q_idx] = vector_idx;
5745 * Sets up the hardware to properly generate MSI-X interrupts
5747 * board private structure
5750 ixgbe_configure_msix(struct rte_eth_dev *dev)
5752 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5753 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5754 struct ixgbe_hw *hw =
5755 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5756 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5757 uint32_t vec = IXGBE_MISC_VEC_ID;
5761 /* won't configure msix register if no mapping is done
5762 * between intr vector and event fd
5764 if (!rte_intr_dp_is_en(intr_handle))
5767 if (rte_intr_allow_others(intr_handle))
5768 vec = base = IXGBE_RX_VEC_START;
5770 /* setup GPIE for MSI-x mode */
5771 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5772 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5773 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5774 /* auto clearing and auto setting corresponding bits in EIMS
5775 * when MSI-X interrupt is triggered
5777 if (hw->mac.type == ixgbe_mac_82598EB) {
5778 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5780 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5781 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5783 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5785 /* Populate the IVAR table and set the ITR values to the
5786 * corresponding register.
5788 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5790 /* by default, 1:1 mapping */
5791 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5792 intr_handle->intr_vec[queue_id] = vec;
5793 if (vec < base + intr_handle->nb_efd - 1)
5797 switch (hw->mac.type) {
5798 case ixgbe_mac_82598EB:
5799 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5802 case ixgbe_mac_82599EB:
5803 case ixgbe_mac_X540:
5804 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5809 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5810 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5812 /* set up to autoclear timer, and the vectors */
5813 mask = IXGBE_EIMS_ENABLE_MASK;
5814 mask &= ~(IXGBE_EIMS_OTHER |
5815 IXGBE_EIMS_MAILBOX |
5818 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5821 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5822 uint16_t queue_idx, uint16_t tx_rate)
5824 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5825 uint32_t rf_dec, rf_int;
5827 uint16_t link_speed = dev->data->dev_link.link_speed;
5829 if (queue_idx >= hw->mac.max_tx_queues)
5833 /* Calculate the rate factor values to set */
5834 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5835 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5836 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5838 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5839 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5840 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5841 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5847 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5848 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5851 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5852 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5853 IXGBE_MAX_JUMBO_FRAME_SIZE))
5854 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5855 IXGBE_MMW_SIZE_JUMBO_FRAME);
5857 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5858 IXGBE_MMW_SIZE_DEFAULT);
5860 /* Set RTTBCNRC of queue X */
5861 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5862 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5863 IXGBE_WRITE_FLUSH(hw);
5869 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5870 __attribute__((unused)) uint32_t index,
5871 __attribute__((unused)) uint32_t pool)
5873 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5877 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5878 * operation. Trap this case to avoid exhausting the [very limited]
5879 * set of PF resources used to store VF MAC addresses.
5881 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5883 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5886 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5890 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5892 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5893 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5894 struct ether_addr *mac_addr;
5899 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5900 * not support the deletion of a given MAC address.
5901 * Instead, it imposes to delete all MAC addresses, then to add again
5902 * all MAC addresses with the exception of the one to be deleted.
5904 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5907 * Add again all MAC addresses, with the exception of the deleted one
5908 * and of the permanent MAC address.
5910 for (i = 0, mac_addr = dev->data->mac_addrs;
5911 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5912 /* Skip the deleted MAC address */
5915 /* Skip NULL MAC addresses */
5916 if (is_zero_ether_addr(mac_addr))
5918 /* Skip the permanent MAC address */
5919 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5921 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5924 "Adding again MAC address "
5925 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5927 mac_addr->addr_bytes[0],
5928 mac_addr->addr_bytes[1],
5929 mac_addr->addr_bytes[2],
5930 mac_addr->addr_bytes[3],
5931 mac_addr->addr_bytes[4],
5932 mac_addr->addr_bytes[5],
5938 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5940 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5942 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5945 #define MAC_TYPE_FILTER_SUP(type) do {\
5946 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5947 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5948 (type) != ixgbe_mac_X550EM_a)\
5953 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5954 struct rte_eth_syn_filter *filter,
5957 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5958 struct ixgbe_filter_info *filter_info =
5959 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5963 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5966 syn_info = filter_info->syn_info;
5969 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5971 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5972 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5974 if (filter->hig_pri)
5975 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5977 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5979 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5980 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5982 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5985 filter_info->syn_info = synqf;
5986 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5987 IXGBE_WRITE_FLUSH(hw);
5992 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5993 struct rte_eth_syn_filter *filter)
5995 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5996 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5998 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5999 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6000 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6007 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6008 enum rte_filter_op filter_op,
6011 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6014 MAC_TYPE_FILTER_SUP(hw->mac.type);
6016 if (filter_op == RTE_ETH_FILTER_NOP)
6020 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6025 switch (filter_op) {
6026 case RTE_ETH_FILTER_ADD:
6027 ret = ixgbe_syn_filter_set(dev,
6028 (struct rte_eth_syn_filter *)arg,
6031 case RTE_ETH_FILTER_DELETE:
6032 ret = ixgbe_syn_filter_set(dev,
6033 (struct rte_eth_syn_filter *)arg,
6036 case RTE_ETH_FILTER_GET:
6037 ret = ixgbe_syn_filter_get(dev,
6038 (struct rte_eth_syn_filter *)arg);
6041 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6050 static inline enum ixgbe_5tuple_protocol
6051 convert_protocol_type(uint8_t protocol_value)
6053 if (protocol_value == IPPROTO_TCP)
6054 return IXGBE_FILTER_PROTOCOL_TCP;
6055 else if (protocol_value == IPPROTO_UDP)
6056 return IXGBE_FILTER_PROTOCOL_UDP;
6057 else if (protocol_value == IPPROTO_SCTP)
6058 return IXGBE_FILTER_PROTOCOL_SCTP;
6060 return IXGBE_FILTER_PROTOCOL_NONE;
6063 /* inject a 5-tuple filter to HW */
6065 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6066 struct ixgbe_5tuple_filter *filter)
6068 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6070 uint32_t ftqf, sdpqf;
6071 uint32_t l34timir = 0;
6072 uint8_t mask = 0xff;
6076 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6077 IXGBE_SDPQF_DSTPORT_SHIFT);
6078 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6080 ftqf = (uint32_t)(filter->filter_info.proto &
6081 IXGBE_FTQF_PROTOCOL_MASK);
6082 ftqf |= (uint32_t)((filter->filter_info.priority &
6083 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6084 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6085 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6086 if (filter->filter_info.dst_ip_mask == 0)
6087 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6088 if (filter->filter_info.src_port_mask == 0)
6089 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6090 if (filter->filter_info.dst_port_mask == 0)
6091 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6092 if (filter->filter_info.proto_mask == 0)
6093 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6094 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6095 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6096 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6098 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6099 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6100 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6101 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6103 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6104 l34timir |= (uint32_t)(filter->queue <<
6105 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6106 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6110 * add a 5tuple filter
6113 * dev: Pointer to struct rte_eth_dev.
6114 * index: the index the filter allocates.
6115 * filter: ponter to the filter that will be added.
6116 * rx_queue: the queue id the filter assigned to.
6119 * - On success, zero.
6120 * - On failure, a negative value.
6123 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6124 struct ixgbe_5tuple_filter *filter)
6126 struct ixgbe_filter_info *filter_info =
6127 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6131 * look for an unused 5tuple filter index,
6132 * and insert the filter to list.
6134 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6135 idx = i / (sizeof(uint32_t) * NBBY);
6136 shift = i % (sizeof(uint32_t) * NBBY);
6137 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6138 filter_info->fivetuple_mask[idx] |= 1 << shift;
6140 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6146 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6147 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6151 ixgbe_inject_5tuple_filter(dev, filter);
6157 * remove a 5tuple filter
6160 * dev: Pointer to struct rte_eth_dev.
6161 * filter: the pointer of the filter will be removed.
6164 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6165 struct ixgbe_5tuple_filter *filter)
6167 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6168 struct ixgbe_filter_info *filter_info =
6169 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6170 uint16_t index = filter->index;
6172 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6173 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6174 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6177 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6178 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6179 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6180 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6181 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6185 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6187 struct ixgbe_hw *hw;
6188 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6190 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6192 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6195 /* refuse mtu that requires the support of scattered packets when this
6196 * feature has not been enabled before.
6198 if (!dev->data->scattered_rx &&
6199 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6200 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6204 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6205 * request of the version 2.0 of the mailbox API.
6206 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6207 * of the mailbox API.
6208 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6209 * prior to 3.11.33 which contains the following change:
6210 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6212 ixgbevf_rlpml_set_vf(hw, max_frame);
6214 /* update max frame size */
6215 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6219 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
6220 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6224 static inline struct ixgbe_5tuple_filter *
6225 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6226 struct ixgbe_5tuple_filter_info *key)
6228 struct ixgbe_5tuple_filter *it;
6230 TAILQ_FOREACH(it, filter_list, entries) {
6231 if (memcmp(key, &it->filter_info,
6232 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6239 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6241 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6242 struct ixgbe_5tuple_filter_info *filter_info)
6244 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6245 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6246 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6249 switch (filter->dst_ip_mask) {
6251 filter_info->dst_ip_mask = 0;
6252 filter_info->dst_ip = filter->dst_ip;
6255 filter_info->dst_ip_mask = 1;
6258 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6262 switch (filter->src_ip_mask) {
6264 filter_info->src_ip_mask = 0;
6265 filter_info->src_ip = filter->src_ip;
6268 filter_info->src_ip_mask = 1;
6271 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6275 switch (filter->dst_port_mask) {
6277 filter_info->dst_port_mask = 0;
6278 filter_info->dst_port = filter->dst_port;
6281 filter_info->dst_port_mask = 1;
6284 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6288 switch (filter->src_port_mask) {
6290 filter_info->src_port_mask = 0;
6291 filter_info->src_port = filter->src_port;
6294 filter_info->src_port_mask = 1;
6297 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6301 switch (filter->proto_mask) {
6303 filter_info->proto_mask = 0;
6304 filter_info->proto =
6305 convert_protocol_type(filter->proto);
6308 filter_info->proto_mask = 1;
6311 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6315 filter_info->priority = (uint8_t)filter->priority;
6320 * add or delete a ntuple filter
6323 * dev: Pointer to struct rte_eth_dev.
6324 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6325 * add: if true, add filter, if false, remove filter
6328 * - On success, zero.
6329 * - On failure, a negative value.
6332 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6333 struct rte_eth_ntuple_filter *ntuple_filter,
6336 struct ixgbe_filter_info *filter_info =
6337 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6338 struct ixgbe_5tuple_filter_info filter_5tuple;
6339 struct ixgbe_5tuple_filter *filter;
6342 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6343 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6347 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6348 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6352 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6354 if (filter != NULL && add) {
6355 PMD_DRV_LOG(ERR, "filter exists.");
6358 if (filter == NULL && !add) {
6359 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6364 filter = rte_zmalloc("ixgbe_5tuple_filter",
6365 sizeof(struct ixgbe_5tuple_filter), 0);
6368 (void)rte_memcpy(&filter->filter_info,
6370 sizeof(struct ixgbe_5tuple_filter_info));
6371 filter->queue = ntuple_filter->queue;
6372 ret = ixgbe_add_5tuple_filter(dev, filter);
6378 ixgbe_remove_5tuple_filter(dev, filter);
6384 * get a ntuple filter
6387 * dev: Pointer to struct rte_eth_dev.
6388 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6391 * - On success, zero.
6392 * - On failure, a negative value.
6395 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6396 struct rte_eth_ntuple_filter *ntuple_filter)
6398 struct ixgbe_filter_info *filter_info =
6399 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6400 struct ixgbe_5tuple_filter_info filter_5tuple;
6401 struct ixgbe_5tuple_filter *filter;
6404 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6405 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6409 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6410 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6414 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6416 if (filter == NULL) {
6417 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6420 ntuple_filter->queue = filter->queue;
6425 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6426 * @dev: pointer to rte_eth_dev structure
6427 * @filter_op:operation will be taken.
6428 * @arg: a pointer to specific structure corresponding to the filter_op
6431 * - On success, zero.
6432 * - On failure, a negative value.
6435 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6436 enum rte_filter_op filter_op,
6439 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6442 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6444 if (filter_op == RTE_ETH_FILTER_NOP)
6448 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6453 switch (filter_op) {
6454 case RTE_ETH_FILTER_ADD:
6455 ret = ixgbe_add_del_ntuple_filter(dev,
6456 (struct rte_eth_ntuple_filter *)arg,
6459 case RTE_ETH_FILTER_DELETE:
6460 ret = ixgbe_add_del_ntuple_filter(dev,
6461 (struct rte_eth_ntuple_filter *)arg,
6464 case RTE_ETH_FILTER_GET:
6465 ret = ixgbe_get_ntuple_filter(dev,
6466 (struct rte_eth_ntuple_filter *)arg);
6469 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6477 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6482 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6483 if (filter_info->ethertype_filters[i] == ethertype &&
6484 (filter_info->ethertype_mask & (1 << i)))
6491 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6496 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6497 if (!(filter_info->ethertype_mask & (1 << i))) {
6498 filter_info->ethertype_mask |= 1 << i;
6499 filter_info->ethertype_filters[i] = ethertype;
6507 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6510 if (idx >= IXGBE_MAX_ETQF_FILTERS)
6512 filter_info->ethertype_mask &= ~(1 << idx);
6513 filter_info->ethertype_filters[idx] = 0;
6518 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6519 struct rte_eth_ethertype_filter *filter,
6522 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6523 struct ixgbe_filter_info *filter_info =
6524 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6529 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6532 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6533 filter->ether_type == ETHER_TYPE_IPv6) {
6534 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6535 " ethertype filter.", filter->ether_type);
6539 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6540 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6543 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6544 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6548 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6549 if (ret >= 0 && add) {
6550 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6551 filter->ether_type);
6554 if (ret < 0 && !add) {
6555 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6556 filter->ether_type);
6561 ret = ixgbe_ethertype_filter_insert(filter_info,
6562 filter->ether_type);
6564 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6567 etqf = IXGBE_ETQF_FILTER_EN;
6568 etqf |= (uint32_t)filter->ether_type;
6569 etqs |= (uint32_t)((filter->queue <<
6570 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6571 IXGBE_ETQS_RX_QUEUE);
6572 etqs |= IXGBE_ETQS_QUEUE_EN;
6574 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6578 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6579 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6580 IXGBE_WRITE_FLUSH(hw);
6586 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6587 struct rte_eth_ethertype_filter *filter)
6589 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6590 struct ixgbe_filter_info *filter_info =
6591 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6592 uint32_t etqf, etqs;
6595 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6597 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6598 filter->ether_type);
6602 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6603 if (etqf & IXGBE_ETQF_FILTER_EN) {
6604 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6605 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6607 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6608 IXGBE_ETQS_RX_QUEUE_SHIFT;
6615 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6616 * @dev: pointer to rte_eth_dev structure
6617 * @filter_op:operation will be taken.
6618 * @arg: a pointer to specific structure corresponding to the filter_op
6621 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6622 enum rte_filter_op filter_op,
6625 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6628 MAC_TYPE_FILTER_SUP(hw->mac.type);
6630 if (filter_op == RTE_ETH_FILTER_NOP)
6634 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6639 switch (filter_op) {
6640 case RTE_ETH_FILTER_ADD:
6641 ret = ixgbe_add_del_ethertype_filter(dev,
6642 (struct rte_eth_ethertype_filter *)arg,
6645 case RTE_ETH_FILTER_DELETE:
6646 ret = ixgbe_add_del_ethertype_filter(dev,
6647 (struct rte_eth_ethertype_filter *)arg,
6650 case RTE_ETH_FILTER_GET:
6651 ret = ixgbe_get_ethertype_filter(dev,
6652 (struct rte_eth_ethertype_filter *)arg);
6655 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6663 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6664 enum rte_filter_type filter_type,
6665 enum rte_filter_op filter_op,
6670 switch (filter_type) {
6671 case RTE_ETH_FILTER_NTUPLE:
6672 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6674 case RTE_ETH_FILTER_ETHERTYPE:
6675 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6677 case RTE_ETH_FILTER_SYN:
6678 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6680 case RTE_ETH_FILTER_FDIR:
6681 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6683 case RTE_ETH_FILTER_L2_TUNNEL:
6684 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6687 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6696 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6697 u8 **mc_addr_ptr, u32 *vmdq)
6702 mc_addr = *mc_addr_ptr;
6703 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6708 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6709 struct ether_addr *mc_addr_set,
6710 uint32_t nb_mc_addr)
6712 struct ixgbe_hw *hw;
6715 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6716 mc_addr_list = (u8 *)mc_addr_set;
6717 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6718 ixgbe_dev_addr_list_itr, TRUE);
6722 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6724 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6725 uint64_t systime_cycles;
6727 switch (hw->mac.type) {
6728 case ixgbe_mac_X550:
6729 case ixgbe_mac_X550EM_x:
6730 case ixgbe_mac_X550EM_a:
6731 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6732 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6733 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6737 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6738 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6742 return systime_cycles;
6746 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6748 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6749 uint64_t rx_tstamp_cycles;
6751 switch (hw->mac.type) {
6752 case ixgbe_mac_X550:
6753 case ixgbe_mac_X550EM_x:
6754 case ixgbe_mac_X550EM_a:
6755 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6756 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6757 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6761 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6762 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6763 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6767 return rx_tstamp_cycles;
6771 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6773 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6774 uint64_t tx_tstamp_cycles;
6776 switch (hw->mac.type) {
6777 case ixgbe_mac_X550:
6778 case ixgbe_mac_X550EM_x:
6779 case ixgbe_mac_X550EM_a:
6780 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6781 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6782 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6786 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6787 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6788 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6792 return tx_tstamp_cycles;
6796 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6798 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6799 struct ixgbe_adapter *adapter =
6800 (struct ixgbe_adapter *)dev->data->dev_private;
6801 struct rte_eth_link link;
6802 uint32_t incval = 0;
6805 /* Get current link speed. */
6806 memset(&link, 0, sizeof(link));
6807 ixgbe_dev_link_update(dev, 1);
6808 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6810 switch (link.link_speed) {
6811 case ETH_SPEED_NUM_100M:
6812 incval = IXGBE_INCVAL_100;
6813 shift = IXGBE_INCVAL_SHIFT_100;
6815 case ETH_SPEED_NUM_1G:
6816 incval = IXGBE_INCVAL_1GB;
6817 shift = IXGBE_INCVAL_SHIFT_1GB;
6819 case ETH_SPEED_NUM_10G:
6821 incval = IXGBE_INCVAL_10GB;
6822 shift = IXGBE_INCVAL_SHIFT_10GB;
6826 switch (hw->mac.type) {
6827 case ixgbe_mac_X550:
6828 case ixgbe_mac_X550EM_x:
6829 case ixgbe_mac_X550EM_a:
6830 /* Independent of link speed. */
6832 /* Cycles read will be interpreted as ns. */
6835 case ixgbe_mac_X540:
6836 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6838 case ixgbe_mac_82599EB:
6839 incval >>= IXGBE_INCVAL_SHIFT_82599;
6840 shift -= IXGBE_INCVAL_SHIFT_82599;
6841 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6842 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6845 /* Not supported. */
6849 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6850 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6851 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6853 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6854 adapter->systime_tc.cc_shift = shift;
6855 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6857 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6858 adapter->rx_tstamp_tc.cc_shift = shift;
6859 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6861 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6862 adapter->tx_tstamp_tc.cc_shift = shift;
6863 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6867 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6869 struct ixgbe_adapter *adapter =
6870 (struct ixgbe_adapter *)dev->data->dev_private;
6872 adapter->systime_tc.nsec += delta;
6873 adapter->rx_tstamp_tc.nsec += delta;
6874 adapter->tx_tstamp_tc.nsec += delta;
6880 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6883 struct ixgbe_adapter *adapter =
6884 (struct ixgbe_adapter *)dev->data->dev_private;
6886 ns = rte_timespec_to_ns(ts);
6887 /* Set the timecounters to a new value. */
6888 adapter->systime_tc.nsec = ns;
6889 adapter->rx_tstamp_tc.nsec = ns;
6890 adapter->tx_tstamp_tc.nsec = ns;
6896 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6898 uint64_t ns, systime_cycles;
6899 struct ixgbe_adapter *adapter =
6900 (struct ixgbe_adapter *)dev->data->dev_private;
6902 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6903 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6904 *ts = rte_ns_to_timespec(ns);
6910 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6912 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6916 /* Stop the timesync system time. */
6917 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6918 /* Reset the timesync system time value. */
6919 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6920 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6922 /* Enable system time for platforms where it isn't on by default. */
6923 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6924 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6925 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6927 ixgbe_start_timecounters(dev);
6929 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6930 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6932 IXGBE_ETQF_FILTER_EN |
6935 /* Enable timestamping of received PTP packets. */
6936 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6937 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6938 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6940 /* Enable timestamping of transmitted PTP packets. */
6941 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6942 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6943 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6945 IXGBE_WRITE_FLUSH(hw);
6951 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6953 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6956 /* Disable timestamping of transmitted PTP packets. */
6957 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6958 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6959 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6961 /* Disable timestamping of received PTP packets. */
6962 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6963 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6964 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6966 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6967 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6969 /* Stop incrementating the System Time registers. */
6970 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6976 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6977 struct timespec *timestamp,
6978 uint32_t flags __rte_unused)
6980 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6981 struct ixgbe_adapter *adapter =
6982 (struct ixgbe_adapter *)dev->data->dev_private;
6983 uint32_t tsync_rxctl;
6984 uint64_t rx_tstamp_cycles;
6987 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6988 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6991 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6992 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6993 *timestamp = rte_ns_to_timespec(ns);
6999 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7000 struct timespec *timestamp)
7002 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7003 struct ixgbe_adapter *adapter =
7004 (struct ixgbe_adapter *)dev->data->dev_private;
7005 uint32_t tsync_txctl;
7006 uint64_t tx_tstamp_cycles;
7009 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7010 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7013 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7014 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7015 *timestamp = rte_ns_to_timespec(ns);
7021 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7023 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7026 const struct reg_info *reg_group;
7027 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7028 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7030 while ((reg_group = reg_set[g_ind++]))
7031 count += ixgbe_regs_group_count(reg_group);
7037 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7041 const struct reg_info *reg_group;
7043 while ((reg_group = ixgbevf_regs[g_ind++]))
7044 count += ixgbe_regs_group_count(reg_group);
7050 ixgbe_get_regs(struct rte_eth_dev *dev,
7051 struct rte_dev_reg_info *regs)
7053 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7054 uint32_t *data = regs->data;
7057 const struct reg_info *reg_group;
7058 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7059 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7062 regs->length = ixgbe_get_reg_length(dev);
7063 regs->width = sizeof(uint32_t);
7067 /* Support only full register dump */
7068 if ((regs->length == 0) ||
7069 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7070 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7072 while ((reg_group = reg_set[g_ind++]))
7073 count += ixgbe_read_regs_group(dev, &data[count],
7082 ixgbevf_get_regs(struct rte_eth_dev *dev,
7083 struct rte_dev_reg_info *regs)
7085 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7086 uint32_t *data = regs->data;
7089 const struct reg_info *reg_group;
7092 regs->length = ixgbevf_get_reg_length(dev);
7093 regs->width = sizeof(uint32_t);
7097 /* Support only full register dump */
7098 if ((regs->length == 0) ||
7099 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7100 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7102 while ((reg_group = ixgbevf_regs[g_ind++]))
7103 count += ixgbe_read_regs_group(dev, &data[count],
7112 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7114 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7116 /* Return unit is byte count */
7117 return hw->eeprom.word_size * 2;
7121 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7122 struct rte_dev_eeprom_info *in_eeprom)
7124 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7125 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7126 uint16_t *data = in_eeprom->data;
7129 first = in_eeprom->offset >> 1;
7130 length = in_eeprom->length >> 1;
7131 if ((first > hw->eeprom.word_size) ||
7132 ((first + length) > hw->eeprom.word_size))
7135 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7137 return eeprom->ops.read_buffer(hw, first, length, data);
7141 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7142 struct rte_dev_eeprom_info *in_eeprom)
7144 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7145 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7146 uint16_t *data = in_eeprom->data;
7149 first = in_eeprom->offset >> 1;
7150 length = in_eeprom->length >> 1;
7151 if ((first > hw->eeprom.word_size) ||
7152 ((first + length) > hw->eeprom.word_size))
7155 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7157 return eeprom->ops.write_buffer(hw, first, length, data);
7161 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7163 case ixgbe_mac_X550:
7164 case ixgbe_mac_X550EM_x:
7165 case ixgbe_mac_X550EM_a:
7166 return ETH_RSS_RETA_SIZE_512;
7167 case ixgbe_mac_X550_vf:
7168 case ixgbe_mac_X550EM_x_vf:
7169 case ixgbe_mac_X550EM_a_vf:
7170 return ETH_RSS_RETA_SIZE_64;
7172 return ETH_RSS_RETA_SIZE_128;
7177 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7179 case ixgbe_mac_X550:
7180 case ixgbe_mac_X550EM_x:
7181 case ixgbe_mac_X550EM_a:
7182 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7183 return IXGBE_RETA(reta_idx >> 2);
7185 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7186 case ixgbe_mac_X550_vf:
7187 case ixgbe_mac_X550EM_x_vf:
7188 case ixgbe_mac_X550EM_a_vf:
7189 return IXGBE_VFRETA(reta_idx >> 2);
7191 return IXGBE_RETA(reta_idx >> 2);
7196 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7198 case ixgbe_mac_X550_vf:
7199 case ixgbe_mac_X550EM_x_vf:
7200 case ixgbe_mac_X550EM_a_vf:
7201 return IXGBE_VFMRQC;
7208 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7210 case ixgbe_mac_X550_vf:
7211 case ixgbe_mac_X550EM_x_vf:
7212 case ixgbe_mac_X550EM_a_vf:
7213 return IXGBE_VFRSSRK(i);
7215 return IXGBE_RSSRK(i);
7220 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7222 case ixgbe_mac_82599_vf:
7223 case ixgbe_mac_X540_vf:
7231 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7232 struct rte_eth_dcb_info *dcb_info)
7234 struct ixgbe_dcb_config *dcb_config =
7235 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7236 struct ixgbe_dcb_tc_config *tc;
7239 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7240 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7242 dcb_info->nb_tcs = 1;
7244 if (dcb_config->vt_mode) { /* vt is enabled*/
7245 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7246 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7247 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7248 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7249 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7250 for (j = 0; j < dcb_info->nb_tcs; j++) {
7251 dcb_info->tc_queue.tc_rxq[i][j].base =
7252 i * dcb_info->nb_tcs + j;
7253 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7254 dcb_info->tc_queue.tc_txq[i][j].base =
7255 i * dcb_info->nb_tcs + j;
7256 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7259 } else { /* vt is disabled*/
7260 struct rte_eth_dcb_rx_conf *rx_conf =
7261 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7262 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7263 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7264 if (dcb_info->nb_tcs == ETH_4_TCS) {
7265 for (i = 0; i < dcb_info->nb_tcs; i++) {
7266 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7267 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7269 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7270 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7271 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7272 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7273 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7274 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7275 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7276 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7277 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7278 for (i = 0; i < dcb_info->nb_tcs; i++) {
7279 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7280 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7282 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7283 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7284 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7285 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7286 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7287 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7288 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7289 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7290 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7291 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7292 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7293 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7294 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7295 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7296 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7297 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7300 for (i = 0; i < dcb_info->nb_tcs; i++) {
7301 tc = &dcb_config->tc_config[i];
7302 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7307 /* Update e-tag ether type */
7309 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7310 uint16_t ether_type)
7312 uint32_t etag_etype;
7314 if (hw->mac.type != ixgbe_mac_X550 &&
7315 hw->mac.type != ixgbe_mac_X550EM_x &&
7316 hw->mac.type != ixgbe_mac_X550EM_a) {
7320 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7321 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7322 etag_etype |= ether_type;
7323 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7324 IXGBE_WRITE_FLUSH(hw);
7329 /* Config l2 tunnel ether type */
7331 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7332 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7335 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7337 if (l2_tunnel == NULL)
7340 switch (l2_tunnel->l2_tunnel_type) {
7341 case RTE_L2_TUNNEL_TYPE_E_TAG:
7342 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7345 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7353 /* Enable e-tag tunnel */
7355 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7357 uint32_t etag_etype;
7359 if (hw->mac.type != ixgbe_mac_X550 &&
7360 hw->mac.type != ixgbe_mac_X550EM_x &&
7361 hw->mac.type != ixgbe_mac_X550EM_a) {
7365 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7366 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7367 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7368 IXGBE_WRITE_FLUSH(hw);
7373 /* Enable l2 tunnel */
7375 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7376 enum rte_eth_tunnel_type l2_tunnel_type)
7379 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7381 switch (l2_tunnel_type) {
7382 case RTE_L2_TUNNEL_TYPE_E_TAG:
7383 ret = ixgbe_e_tag_enable(hw);
7386 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7394 /* Disable e-tag tunnel */
7396 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7398 uint32_t etag_etype;
7400 if (hw->mac.type != ixgbe_mac_X550 &&
7401 hw->mac.type != ixgbe_mac_X550EM_x &&
7402 hw->mac.type != ixgbe_mac_X550EM_a) {
7406 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7407 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7408 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7409 IXGBE_WRITE_FLUSH(hw);
7414 /* Disable l2 tunnel */
7416 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7417 enum rte_eth_tunnel_type l2_tunnel_type)
7420 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7422 switch (l2_tunnel_type) {
7423 case RTE_L2_TUNNEL_TYPE_E_TAG:
7424 ret = ixgbe_e_tag_disable(hw);
7427 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7436 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7437 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7440 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7441 uint32_t i, rar_entries;
7442 uint32_t rar_low, rar_high;
7444 if (hw->mac.type != ixgbe_mac_X550 &&
7445 hw->mac.type != ixgbe_mac_X550EM_x &&
7446 hw->mac.type != ixgbe_mac_X550EM_a) {
7450 rar_entries = ixgbe_get_num_rx_addrs(hw);
7452 for (i = 1; i < rar_entries; i++) {
7453 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7454 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7455 if ((rar_high & IXGBE_RAH_AV) &&
7456 (rar_high & IXGBE_RAH_ADTYPE) &&
7457 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7458 l2_tunnel->tunnel_id)) {
7459 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7460 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7462 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7472 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7473 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7476 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7477 uint32_t i, rar_entries;
7478 uint32_t rar_low, rar_high;
7480 if (hw->mac.type != ixgbe_mac_X550 &&
7481 hw->mac.type != ixgbe_mac_X550EM_x &&
7482 hw->mac.type != ixgbe_mac_X550EM_a) {
7486 /* One entry for one tunnel. Try to remove potential existing entry. */
7487 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7489 rar_entries = ixgbe_get_num_rx_addrs(hw);
7491 for (i = 1; i < rar_entries; i++) {
7492 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7493 if (rar_high & IXGBE_RAH_AV) {
7496 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7497 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7498 rar_low = l2_tunnel->tunnel_id;
7500 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7501 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7507 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7508 " Please remove a rule before adding a new one.");
7512 static inline struct ixgbe_l2_tn_filter *
7513 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7514 struct ixgbe_l2_tn_key *key)
7518 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7522 return l2_tn_info->hash_map[ret];
7526 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7527 struct ixgbe_l2_tn_filter *l2_tn_filter)
7531 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7532 &l2_tn_filter->key);
7536 "Failed to insert L2 tunnel filter"
7537 " to hash table %d!",
7542 l2_tn_info->hash_map[ret] = l2_tn_filter;
7544 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7550 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7551 struct ixgbe_l2_tn_key *key)
7554 struct ixgbe_l2_tn_filter *l2_tn_filter;
7556 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7560 "No such L2 tunnel filter to delete %d!",
7565 l2_tn_filter = l2_tn_info->hash_map[ret];
7566 l2_tn_info->hash_map[ret] = NULL;
7568 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7569 rte_free(l2_tn_filter);
7574 /* Add l2 tunnel filter */
7576 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7577 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7580 struct ixgbe_l2_tn_info *l2_tn_info =
7581 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7582 struct ixgbe_l2_tn_key key;
7583 struct ixgbe_l2_tn_filter *node;
7585 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7586 key.tn_id = l2_tunnel->tunnel_id;
7588 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7591 PMD_DRV_LOG(ERR, "The L2 tunnel filter already exists!");
7595 node = rte_zmalloc("ixgbe_l2_tn",
7596 sizeof(struct ixgbe_l2_tn_filter),
7601 (void)rte_memcpy(&node->key,
7603 sizeof(struct ixgbe_l2_tn_key));
7604 node->pool = l2_tunnel->pool;
7605 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7611 switch (l2_tunnel->l2_tunnel_type) {
7612 case RTE_L2_TUNNEL_TYPE_E_TAG:
7613 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7616 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7622 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7627 /* Delete l2 tunnel filter */
7629 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7630 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7633 struct ixgbe_l2_tn_info *l2_tn_info =
7634 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7635 struct ixgbe_l2_tn_key key;
7637 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7638 key.tn_id = l2_tunnel->tunnel_id;
7639 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7643 switch (l2_tunnel->l2_tunnel_type) {
7644 case RTE_L2_TUNNEL_TYPE_E_TAG:
7645 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7648 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7657 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7658 * @dev: pointer to rte_eth_dev structure
7659 * @filter_op:operation will be taken.
7660 * @arg: a pointer to specific structure corresponding to the filter_op
7663 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7664 enum rte_filter_op filter_op,
7669 if (filter_op == RTE_ETH_FILTER_NOP)
7673 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7678 switch (filter_op) {
7679 case RTE_ETH_FILTER_ADD:
7680 ret = ixgbe_dev_l2_tunnel_filter_add
7682 (struct rte_eth_l2_tunnel_conf *)arg);
7684 case RTE_ETH_FILTER_DELETE:
7685 ret = ixgbe_dev_l2_tunnel_filter_del
7687 (struct rte_eth_l2_tunnel_conf *)arg);
7690 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7698 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7702 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7704 if (hw->mac.type != ixgbe_mac_X550 &&
7705 hw->mac.type != ixgbe_mac_X550EM_x &&
7706 hw->mac.type != ixgbe_mac_X550EM_a) {
7710 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7711 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7713 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7714 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7719 /* Enable l2 tunnel forwarding */
7721 ixgbe_dev_l2_tunnel_forwarding_enable
7722 (struct rte_eth_dev *dev,
7723 enum rte_eth_tunnel_type l2_tunnel_type)
7727 switch (l2_tunnel_type) {
7728 case RTE_L2_TUNNEL_TYPE_E_TAG:
7729 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7732 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7740 /* Disable l2 tunnel forwarding */
7742 ixgbe_dev_l2_tunnel_forwarding_disable
7743 (struct rte_eth_dev *dev,
7744 enum rte_eth_tunnel_type l2_tunnel_type)
7748 switch (l2_tunnel_type) {
7749 case RTE_L2_TUNNEL_TYPE_E_TAG:
7750 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7753 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7762 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7763 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7766 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7768 uint32_t vmtir, vmvir;
7769 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7771 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7773 "VF id %u should be less than %u",
7779 if (hw->mac.type != ixgbe_mac_X550 &&
7780 hw->mac.type != ixgbe_mac_X550EM_x &&
7781 hw->mac.type != ixgbe_mac_X550EM_a) {
7786 vmtir = l2_tunnel->tunnel_id;
7790 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7792 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7793 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7795 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7796 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7801 /* Enable l2 tunnel tag insertion */
7803 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7804 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7808 switch (l2_tunnel->l2_tunnel_type) {
7809 case RTE_L2_TUNNEL_TYPE_E_TAG:
7810 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7813 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7821 /* Disable l2 tunnel tag insertion */
7823 ixgbe_dev_l2_tunnel_insertion_disable
7824 (struct rte_eth_dev *dev,
7825 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7829 switch (l2_tunnel->l2_tunnel_type) {
7830 case RTE_L2_TUNNEL_TYPE_E_TAG:
7831 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7834 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7843 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7848 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7850 if (hw->mac.type != ixgbe_mac_X550 &&
7851 hw->mac.type != ixgbe_mac_X550EM_x &&
7852 hw->mac.type != ixgbe_mac_X550EM_a) {
7856 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7858 qde |= IXGBE_QDE_STRIP_TAG;
7860 qde &= ~IXGBE_QDE_STRIP_TAG;
7861 qde &= ~IXGBE_QDE_READ;
7862 qde |= IXGBE_QDE_WRITE;
7863 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7868 /* Enable l2 tunnel tag stripping */
7870 ixgbe_dev_l2_tunnel_stripping_enable
7871 (struct rte_eth_dev *dev,
7872 enum rte_eth_tunnel_type l2_tunnel_type)
7876 switch (l2_tunnel_type) {
7877 case RTE_L2_TUNNEL_TYPE_E_TAG:
7878 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7881 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7889 /* Disable l2 tunnel tag stripping */
7891 ixgbe_dev_l2_tunnel_stripping_disable
7892 (struct rte_eth_dev *dev,
7893 enum rte_eth_tunnel_type l2_tunnel_type)
7897 switch (l2_tunnel_type) {
7898 case RTE_L2_TUNNEL_TYPE_E_TAG:
7899 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7902 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7910 /* Enable/disable l2 tunnel offload functions */
7912 ixgbe_dev_l2_tunnel_offload_set
7913 (struct rte_eth_dev *dev,
7914 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7920 if (l2_tunnel == NULL)
7924 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7926 ret = ixgbe_dev_l2_tunnel_enable(
7928 l2_tunnel->l2_tunnel_type);
7930 ret = ixgbe_dev_l2_tunnel_disable(
7932 l2_tunnel->l2_tunnel_type);
7935 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7937 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7941 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7946 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7948 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7950 l2_tunnel->l2_tunnel_type);
7952 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7954 l2_tunnel->l2_tunnel_type);
7957 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7959 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7961 l2_tunnel->l2_tunnel_type);
7963 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7965 l2_tunnel->l2_tunnel_type);
7972 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7975 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7976 IXGBE_WRITE_FLUSH(hw);
7981 /* There's only one register for VxLAN UDP port.
7982 * So, we cannot add several ports. Will update it.
7985 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7989 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7993 return ixgbe_update_vxlan_port(hw, port);
7996 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7997 * UDP port, it must have a value.
7998 * So, will reset it to the original value 0.
8001 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8006 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8008 if (cur_port != port) {
8009 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8013 return ixgbe_update_vxlan_port(hw, 0);
8016 /* Add UDP tunneling port */
8018 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8019 struct rte_eth_udp_tunnel *udp_tunnel)
8022 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8024 if (hw->mac.type != ixgbe_mac_X550 &&
8025 hw->mac.type != ixgbe_mac_X550EM_x &&
8026 hw->mac.type != ixgbe_mac_X550EM_a) {
8030 if (udp_tunnel == NULL)
8033 switch (udp_tunnel->prot_type) {
8034 case RTE_TUNNEL_TYPE_VXLAN:
8035 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8038 case RTE_TUNNEL_TYPE_GENEVE:
8039 case RTE_TUNNEL_TYPE_TEREDO:
8040 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8045 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8053 /* Remove UDP tunneling port */
8055 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8056 struct rte_eth_udp_tunnel *udp_tunnel)
8059 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8061 if (hw->mac.type != ixgbe_mac_X550 &&
8062 hw->mac.type != ixgbe_mac_X550EM_x &&
8063 hw->mac.type != ixgbe_mac_X550EM_a) {
8067 if (udp_tunnel == NULL)
8070 switch (udp_tunnel->prot_type) {
8071 case RTE_TUNNEL_TYPE_VXLAN:
8072 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8074 case RTE_TUNNEL_TYPE_GENEVE:
8075 case RTE_TUNNEL_TYPE_TEREDO:
8076 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8080 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8089 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8091 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8093 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8097 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8099 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8101 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8104 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8106 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8109 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8112 /* PF reset VF event */
8113 if (in_msg == IXGBE_PF_CONTROL_MSG)
8114 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8118 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8122 struct ixgbe_interrupt *intr =
8123 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8124 ixgbevf_intr_disable(hw);
8126 /* read-on-clear nic registers here */
8127 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8130 /* only one misc vector supported - mailbox */
8131 eicr &= IXGBE_VTEICR_MASK;
8132 if (eicr == IXGBE_MISC_VEC_ID)
8133 intr->flags |= IXGBE_FLAG_MAILBOX;
8139 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8141 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8142 struct ixgbe_interrupt *intr =
8143 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8145 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8146 ixgbevf_mbx_process(dev);
8147 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8150 ixgbevf_intr_enable(hw);
8156 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8159 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8161 ixgbevf_dev_interrupt_get_status(dev);
8162 ixgbevf_dev_interrupt_action(dev);
8166 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8167 * @hw: pointer to hardware structure
8169 * Stops the transmit data path and waits for the HW to internally empty
8170 * the Tx security block
8172 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8174 #define IXGBE_MAX_SECTX_POLL 40
8179 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8180 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8181 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8182 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8183 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8184 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8186 /* Use interrupt-safe sleep just in case */
8190 /* For informational purposes only */
8191 if (i >= IXGBE_MAX_SECTX_POLL)
8192 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8193 "path fully disabled. Continuing with init.\n");
8195 return IXGBE_SUCCESS;
8199 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8200 * @hw: pointer to hardware structure
8202 * Enables the transmit data path.
8204 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8208 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8209 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8210 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8211 IXGBE_WRITE_FLUSH(hw);
8213 return IXGBE_SUCCESS;
8217 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8219 struct ixgbe_hw *hw;
8220 struct rte_eth_dev *dev;
8223 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8225 dev = &rte_eth_devices[port];
8226 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8228 /* Stop the data paths */
8229 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8233 * As no ixgbe_disable_sec_rx_path equivalent is
8234 * implemented for tx in the base code, and we are
8235 * not allowed to modify the base code in DPDK, so
8236 * just call the hand-written one directly for now.
8237 * The hardware support has been checked by
8238 * ixgbe_disable_sec_rx_path().
8240 ixgbe_disable_sec_tx_path_generic(hw);
8242 /* Enable Ethernet CRC (required by MACsec offload) */
8243 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8244 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8245 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8247 /* Enable the TX and RX crypto engines */
8248 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8249 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8250 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8252 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8253 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8254 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8256 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8257 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8259 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8261 /* Enable SA lookup */
8262 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8263 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8264 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8265 IXGBE_LSECTXCTRL_AUTH;
8266 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8267 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8268 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8269 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8271 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8272 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8273 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8274 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8276 ctrl |= IXGBE_LSECRXCTRL_RP;
8278 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8279 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8281 /* Start the data paths */
8282 ixgbe_enable_sec_rx_path(hw);
8285 * As no ixgbe_enable_sec_rx_path equivalent is
8286 * implemented for tx in the base code, and we are
8287 * not allowed to modify the base code in DPDK, so
8288 * just call the hand-written one directly for now.
8290 ixgbe_enable_sec_tx_path_generic(hw);
8296 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8298 struct ixgbe_hw *hw;
8299 struct rte_eth_dev *dev;
8302 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8304 dev = &rte_eth_devices[port];
8305 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8307 /* Stop the data paths */
8308 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8312 * As no ixgbe_disable_sec_rx_path equivalent is
8313 * implemented for tx in the base code, and we are
8314 * not allowed to modify the base code in DPDK, so
8315 * just call the hand-written one directly for now.
8316 * The hardware support has been checked by
8317 * ixgbe_disable_sec_rx_path().
8319 ixgbe_disable_sec_tx_path_generic(hw);
8321 /* Disable the TX and RX crypto engines */
8322 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8323 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8324 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8326 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8327 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8328 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8330 /* Disable SA lookup */
8331 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8332 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8333 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8334 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8336 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8337 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8338 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8339 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8341 /* Start the data paths */
8342 ixgbe_enable_sec_rx_path(hw);
8345 * As no ixgbe_enable_sec_rx_path equivalent is
8346 * implemented for tx in the base code, and we are
8347 * not allowed to modify the base code in DPDK, so
8348 * just call the hand-written one directly for now.
8350 ixgbe_enable_sec_tx_path_generic(hw);
8356 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8358 struct ixgbe_hw *hw;
8359 struct rte_eth_dev *dev;
8362 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8364 dev = &rte_eth_devices[port];
8365 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8367 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8368 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8370 ctrl = mac[4] | (mac[5] << 8);
8371 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8377 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8379 struct ixgbe_hw *hw;
8380 struct rte_eth_dev *dev;
8383 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8385 dev = &rte_eth_devices[port];
8386 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8388 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8389 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8391 pi = rte_cpu_to_be_16(pi);
8392 ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8393 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8399 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8400 uint32_t pn, uint8_t *key)
8402 struct ixgbe_hw *hw;
8403 struct rte_eth_dev *dev;
8406 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8408 dev = &rte_eth_devices[port];
8409 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8411 if (idx != 0 && idx != 1)
8417 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8419 /* Set the PN and key */
8420 pn = rte_cpu_to_be_32(pn);
8422 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8424 for (i = 0; i < 4; i++) {
8425 ctrl = (key[i * 4 + 0] << 0) |
8426 (key[i * 4 + 1] << 8) |
8427 (key[i * 4 + 2] << 16) |
8428 (key[i * 4 + 3] << 24);
8429 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8432 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8434 for (i = 0; i < 4; i++) {
8435 ctrl = (key[i * 4 + 0] << 0) |
8436 (key[i * 4 + 1] << 8) |
8437 (key[i * 4 + 2] << 16) |
8438 (key[i * 4 + 3] << 24);
8439 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8443 /* Set AN and select the SA */
8444 ctrl = (an << idx * 2) | (idx << 4);
8445 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8451 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8452 uint32_t pn, uint8_t *key)
8454 struct ixgbe_hw *hw;
8455 struct rte_eth_dev *dev;
8458 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8460 dev = &rte_eth_devices[port];
8461 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8463 if (idx != 0 && idx != 1)
8470 pn = rte_cpu_to_be_32(pn);
8471 IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8474 for (i = 0; i < 4; i++) {
8475 ctrl = (key[i * 4 + 0] << 0) |
8476 (key[i * 4 + 1] << 8) |
8477 (key[i * 4 + 2] << 16) |
8478 (key[i * 4 + 3] << 24);
8479 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8482 /* Set the AN and validate the SA */
8483 ctrl = an | (1 << 2);
8484 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8489 /* restore n-tuple filter */
8491 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8493 struct ixgbe_filter_info *filter_info =
8494 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8495 struct ixgbe_5tuple_filter *node;
8497 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8498 ixgbe_inject_5tuple_filter(dev, node);
8503 ixgbe_filter_restore(struct rte_eth_dev *dev)
8505 ixgbe_ntuple_filter_restore(dev);
8510 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8511 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8512 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8513 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8514 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8515 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");