drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 155 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 156 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 157 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 158 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 159 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 160 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 161 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 162 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 163 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 165 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 167                                 int wait_to_complete);
 168 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 169                                 struct rte_eth_stats *stats);
 170 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 171                                 struct rte_eth_xstats *xstats, unsigned n);
 172 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 173                                   struct rte_eth_xstats *xstats, unsigned n);
 174 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 177                                              uint16_t queue_id,
 178                                              uint8_t stat_idx,
 179                                              uint8_t is_rx);
 180 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 181                                struct rte_eth_dev_info *dev_info);
 182 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 183                                  struct rte_eth_dev_info *dev_info);
 184 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 185
 186 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 187                 uint16_t vlan_id, int on);
 188 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 189                                enum rte_vlan_type vlan_type,
 190                                uint16_t tpid_id);
 191 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 192                 uint16_t queue, bool on);
 193 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 194                 int on);
 195 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 220 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 221                 void *param);
 222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 223 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 224                 uint32_t index, uint32_t pool);
 225 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 226 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 227                                            struct ether_addr *mac_addr);
 228 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 229
 230 /* For Virtual Function support */
 231 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 232 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 233 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 234 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 235 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 236 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 237 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 238 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 239 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 240                 struct rte_eth_stats *stats);
 241 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 242 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 243                 uint16_t vlan_id, int on);
 244 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 245                 uint16_t queue, int on);
 246 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 247 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 248 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                             uint16_t queue_id);
 250 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                              uint16_t queue_id);
 252 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 253                                  uint8_t queue, uint8_t msix_vector);
 254 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 255
 256 /* For Eth VMDQ APIs support */
 257 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 258                 ether_addr* mac_addr,uint8_t on);
 259 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 260 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 261                 uint16_t rx_mask, uint8_t on);
 262 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 263 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 264 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 265                 uint64_t pool_mask,uint8_t vlan_on);
 266 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 267                 struct rte_eth_mirror_conf *mirror_conf,
 268                 uint8_t rule_id, uint8_t on);
 269 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 270                 uint8_t rule_id);
 271 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                           uint16_t queue_id);
 273 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                            uint16_t queue_id);
 275 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 276                                uint8_t queue, uint8_t msix_vector);
 277 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 278
 279 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 280                 uint16_t queue_idx, uint16_t tx_rate);
 281 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 282                 uint16_t tx_rate, uint64_t q_msk);
 283
 284 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 285                                  struct ether_addr *mac_addr,
 286                                  uint32_t index, uint32_t pool);
 287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                                              struct ether_addr *mac_addr);
 290 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 291                         struct rte_eth_syn_filter *filter,
 292                         bool add);
 293 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 294                         struct rte_eth_syn_filter *filter);
 295 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 296                         enum rte_filter_op filter_op,
 297                         void *arg);
 298 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 301                         struct ixgbe_5tuple_filter *filter);
 302 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ntuple_filter *filter,
 304                         bool add);
 305 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 306                                 enum rte_filter_op filter_op,
 307                                 void *arg);
 308 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 309                         struct rte_eth_ntuple_filter *filter);
 310 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 311                         struct rte_eth_ethertype_filter *filter,
 312                         bool add);
 313 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 314                                 enum rte_filter_op filter_op,
 315                                 void *arg);
 316 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 317                         struct rte_eth_ethertype_filter *filter);
 318 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 319                      enum rte_filter_type filter_type,
 320                      enum rte_filter_op filter_op,
 321                      void *arg);
 322 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 323
 324 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 325                                       struct ether_addr *mc_addr_set,
 326                                       uint32_t nb_mc_addr);
 327 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                    struct rte_eth_dcb_info *dcb_info);
 329
 330 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 331 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 332                             struct rte_dev_reg_info *regs);
 333 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 334 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 335                                 struct rte_dev_eeprom_info *eeprom);
 336 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 337                                 struct rte_dev_eeprom_info *eeprom);
 338
 339 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 340 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 341                                 struct rte_dev_reg_info *regs);
 342
 343 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 344 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 345 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                             struct timespec *timestamp,
 347                                             uint32_t flags);
 348 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                             struct timespec *timestamp);
 350 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 351 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 352                                    struct timespec *timestamp);
 353 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 354                                    const struct timespec *timestamp);
 355
 356 static int ixgbe_dev_l2_tunnel_eth_type_conf
 357         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 358 static int ixgbe_dev_l2_tunnel_offload_set
 359         (struct rte_eth_dev *dev,
 360          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 361          uint32_t mask,
 362          uint8_t en);
 363 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 364                                              enum rte_filter_op filter_op,
 365                                              void *arg);
 366
 367 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 368                                          struct rte_eth_udp_tunnel *udp_tunnel);
 369 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 370                                          struct rte_eth_udp_tunnel *udp_tunnel);
 371
 372 /*
 373  * Define VF Stats MACRO for Non "cleared on read" register
 374  */
 375 #define UPDATE_VF_STAT(reg, last, cur)                          \
 376 {                                                               \
 377         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 378         cur += (latest - last) & UINT_MAX;                      \
 379         last = latest;                                          \
 380 }
 381
 382 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 383 {                                                                \
 384         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 385         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 386         u64 latest = ((new_msb << 32) | new_lsb);                \
 387         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 388         last = latest;                                           \
 389 }
 390
 391 #define IXGBE_SET_HWSTRIP(h, q) do{\
 392                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] |= 1 << bit;\
 395         } while (0)
 396
 397 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 398                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 400                 (h)->bitmap[idx] &= ~(1 << bit);\
 401         } while (0)
 402
 403 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 404                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 405                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 406                 (r) = (h)->bitmap[idx] >> bit & 1;\
 407         } while (0)
 408
 409 /*
 410  * The set of PCI devices this driver supports
 411  */
 412 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 413
 414 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 415 #include "rte_pci_dev_ids.h"
 416
 417 { .vendor_id = 0, /* sentinel */ },
 418 };
 419
 420
 421 /*
 422  * The set of PCI devices this driver supports (for 82599 VF)
 423  */
 424 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 425
 426 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 427 #include "rte_pci_dev_ids.h"
 428 { .vendor_id = 0, /* sentinel */ },
 429
 430 };
 431
 432 static const struct rte_eth_desc_lim rx_desc_lim = {
 433         .nb_max = IXGBE_MAX_RING_DESC,
 434         .nb_min = IXGBE_MIN_RING_DESC,
 435         .nb_align = IXGBE_RXD_ALIGN,
 436 };
 437
 438 static const struct rte_eth_desc_lim tx_desc_lim = {
 439         .nb_max = IXGBE_MAX_RING_DESC,
 440         .nb_min = IXGBE_MIN_RING_DESC,
 441         .nb_align = IXGBE_TXD_ALIGN,
 442 };
 443
 444 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 445         .dev_configure        = ixgbe_dev_configure,
 446         .dev_start            = ixgbe_dev_start,
 447         .dev_stop             = ixgbe_dev_stop,
 448         .dev_set_link_up    = ixgbe_dev_set_link_up,
 449         .dev_set_link_down  = ixgbe_dev_set_link_down,
 450         .dev_close            = ixgbe_dev_close,
 451         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 452         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 453         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 454         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 455         .link_update          = ixgbe_dev_link_update,
 456         .stats_get            = ixgbe_dev_stats_get,
 457         .xstats_get           = ixgbe_dev_xstats_get,
 458         .stats_reset          = ixgbe_dev_stats_reset,
 459         .xstats_reset         = ixgbe_dev_xstats_reset,
 460         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 461         .dev_infos_get        = ixgbe_dev_info_get,
 462         .mtu_set              = ixgbe_dev_mtu_set,
 463         .vlan_filter_set      = ixgbe_vlan_filter_set,
 464         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 465         .vlan_offload_set     = ixgbe_vlan_offload_set,
 466         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 467         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 468         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 469         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 470         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 471         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 472         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 473         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 474         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 475         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 476         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 477         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 478         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 479         .dev_led_on           = ixgbe_dev_led_on,
 480         .dev_led_off          = ixgbe_dev_led_off,
 481         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 482         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 483         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 484         .mac_addr_add         = ixgbe_add_rar,
 485         .mac_addr_remove      = ixgbe_remove_rar,
 486         .mac_addr_set         = ixgbe_set_default_mac_addr,
 487         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 488         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 489         .mirror_rule_set      = ixgbe_mirror_rule_set,
 490         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 491         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 492         .set_vf_rx            = ixgbe_set_pool_rx,
 493         .set_vf_tx            = ixgbe_set_pool_tx,
 494         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 495         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 496         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 497         .reta_update          = ixgbe_dev_rss_reta_update,
 498         .reta_query           = ixgbe_dev_rss_reta_query,
 499 #ifdef RTE_NIC_BYPASS
 500         .bypass_init          = ixgbe_bypass_init,
 501         .bypass_state_set     = ixgbe_bypass_state_store,
 502         .bypass_state_show    = ixgbe_bypass_state_show,
 503         .bypass_event_set     = ixgbe_bypass_event_store,
 504         .bypass_event_show    = ixgbe_bypass_event_show,
 505         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 506         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 507         .bypass_ver_show      = ixgbe_bypass_ver_show,
 508         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 509 #endif /* RTE_NIC_BYPASS */
 510         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 511         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 512         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 513         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 514         .rxq_info_get         = ixgbe_rxq_info_get,
 515         .txq_info_get         = ixgbe_txq_info_get,
 516         .timesync_enable      = ixgbe_timesync_enable,
 517         .timesync_disable     = ixgbe_timesync_disable,
 518         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 519         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 520         .get_reg_length       = ixgbe_get_reg_length,
 521         .get_reg              = ixgbe_get_regs,
 522         .get_eeprom_length    = ixgbe_get_eeprom_length,
 523         .get_eeprom           = ixgbe_get_eeprom,
 524         .set_eeprom           = ixgbe_set_eeprom,
 525         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 526         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 527         .timesync_read_time   = ixgbe_timesync_read_time,
 528         .timesync_write_time  = ixgbe_timesync_write_time,
 529         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 530         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 531         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 532         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 533 };
 534
 535 /*
 536  * dev_ops for virtual function, bare necessities for basic vf
 537  * operation have been implemented
 538  */
 539 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 540         .dev_configure        = ixgbevf_dev_configure,
 541         .dev_start            = ixgbevf_dev_start,
 542         .dev_stop             = ixgbevf_dev_stop,
 543         .link_update          = ixgbe_dev_link_update,
 544         .stats_get            = ixgbevf_dev_stats_get,
 545         .xstats_get           = ixgbevf_dev_xstats_get,
 546         .stats_reset          = ixgbevf_dev_stats_reset,
 547         .xstats_reset         = ixgbevf_dev_stats_reset,
 548         .dev_close            = ixgbevf_dev_close,
 549         .dev_infos_get        = ixgbevf_dev_info_get,
 550         .mtu_set              = ixgbevf_dev_set_mtu,
 551         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 552         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 553         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 554         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 555         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 556         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 557         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 558         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 559         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 560         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 561         .mac_addr_add         = ixgbevf_add_mac_addr,
 562         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 563         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 564         .rxq_info_get         = ixgbe_rxq_info_get,
 565         .txq_info_get         = ixgbe_txq_info_get,
 566         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 567         .get_reg_length       = ixgbevf_get_reg_length,
 568         .get_reg              = ixgbevf_get_regs,
 569         .reta_update          = ixgbe_dev_rss_reta_update,
 570         .reta_query           = ixgbe_dev_rss_reta_query,
 571         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 572         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 573 };
 574
 575 /* store statistics names and its offset in stats structure */
 576 struct rte_ixgbe_xstats_name_off {
 577         char name[RTE_ETH_XSTATS_NAME_SIZE];
 578         unsigned offset;
 579 };
 580
 581 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 582         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 583         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 584         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 585         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 586         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 587         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 588         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 589         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 590         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 591         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 592         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 593         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 594         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 595         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 596         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 597                 prc1023)},
 598         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 599                 prc1522)},
 600         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 601         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 602         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 603         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 604         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 605         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 606         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 607         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 608         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 609         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 610         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 611         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 612         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 613         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 614         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 615         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 616         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 617                 ptc1023)},
 618         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 619                 ptc1522)},
 620         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 621         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 622         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 623         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 624
 625         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 626                 fdirustat_add)},
 627         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 628                 fdirustat_remove)},
 629         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 630                 fdirfstat_fadd)},
 631         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 632                 fdirfstat_fremove)},
 633         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 634                 fdirmatch)},
 635         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 636                 fdirmiss)},
 637
 638         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 639         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 640         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 641                 fclast)},
 642         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 643         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 644         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 645         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 646         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 647                 fcoe_noddp)},
 648         {"rx_fcoe_no_direct_data_placement_ext_buff",
 649                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 650
 651         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 652                 lxontxc)},
 653         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 654                 lxonrxc)},
 655         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 656                 lxofftxc)},
 657         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 658                 lxoffrxc)},
 659         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 660 };
 661
 662 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 663                            sizeof(rte_ixgbe_stats_strings[0]))
 664
 665 /* Per-queue statistics */
 666 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 667         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 668         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 669         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 670         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 671 };
 672
 673 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 674                            sizeof(rte_ixgbe_rxq_strings[0]))
 675
 676 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 677         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 678         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 679         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 680                 pxon2offc)},
 681 };
 682
 683 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 684                            sizeof(rte_ixgbe_txq_strings[0]))
 685
 686 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 687         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 688 };
 689
 690 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 691                 sizeof(rte_ixgbevf_stats_strings[0]))
 692
 693 /**
 694  * Atomically reads the link status information from global
 695  * structure rte_eth_dev.
 696  *
 697  * @param dev
 698  *   - Pointer to the structure rte_eth_dev to read from.
 699  *   - Pointer to the buffer to be saved with the link status.
 700  *
 701  * @return
 702  *   - On success, zero.
 703  *   - On failure, negative value.
 704  */
 705 static inline int
 706 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 707                                 struct rte_eth_link *link)
 708 {
 709         struct rte_eth_link *dst = link;
 710         struct rte_eth_link *src = &(dev->data->dev_link);
 711
 712         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 713                                         *(uint64_t *)src) == 0)
 714                 return -1;
 715
 716         return 0;
 717 }
 718
 719 /**
 720  * Atomically writes the link status information into global
 721  * structure rte_eth_dev.
 722  *
 723  * @param dev
 724  *   - Pointer to the structure rte_eth_dev to read from.
 725  *   - Pointer to the buffer to be saved with the link status.
 726  *
 727  * @return
 728  *   - On success, zero.
 729  *   - On failure, negative value.
 730  */
 731 static inline int
 732 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 733                                 struct rte_eth_link *link)
 734 {
 735         struct rte_eth_link *dst = &(dev->data->dev_link);
 736         struct rte_eth_link *src = link;
 737
 738         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 739                                         *(uint64_t *)src) == 0)
 740                 return -1;
 741
 742         return 0;
 743 }
 744
 745 /*
 746  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 747  */
 748 static inline int
 749 ixgbe_is_sfp(struct ixgbe_hw *hw)
 750 {
 751         switch (hw->phy.type) {
 752         case ixgbe_phy_sfp_avago:
 753         case ixgbe_phy_sfp_ftl:
 754         case ixgbe_phy_sfp_intel:
 755         case ixgbe_phy_sfp_unknown:
 756         case ixgbe_phy_sfp_passive_tyco:
 757         case ixgbe_phy_sfp_passive_unknown:
 758                 return 1;
 759         default:
 760                 return 0;
 761         }
 762 }
 763
 764 static inline int32_t
 765 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 766 {
 767         uint32_t ctrl_ext;
 768         int32_t status;
 769
 770         status = ixgbe_reset_hw(hw);
 771
 772         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 773         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 774         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 775         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 776         IXGBE_WRITE_FLUSH(hw);
 777
 778         return status;
 779 }
 780
 781 static inline void
 782 ixgbe_enable_intr(struct rte_eth_dev *dev)
 783 {
 784         struct ixgbe_interrupt *intr =
 785                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 786         struct ixgbe_hw *hw =
 787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 788
 789         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 790         IXGBE_WRITE_FLUSH(hw);
 791 }
 792
 793 /*
 794  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 795  */
 796 static void
 797 ixgbe_disable_intr(struct ixgbe_hw *hw)
 798 {
 799         PMD_INIT_FUNC_TRACE();
 800
 801         if (hw->mac.type == ixgbe_mac_82598EB) {
 802                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 803         } else {
 804                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 805                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 806                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 807         }
 808         IXGBE_WRITE_FLUSH(hw);
 809 }
 810
 811 /*
 812  * This function resets queue statistics mapping registers.
 813  * From Niantic datasheet, Initialization of Statistics section:
 814  * "...if software requires the queue counters, the RQSMR and TQSM registers
 815  * must be re-programmed following a device reset.
 816  */
 817 static void
 818 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 819 {
 820         uint32_t i;
 821
 822         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 823                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 824                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 825         }
 826 }
 827
 828
 829 static int
 830 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 831                                   uint16_t queue_id,
 832                                   uint8_t stat_idx,
 833                                   uint8_t is_rx)
 834 {
 835 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 836 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 837 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 838
 839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 840         struct ixgbe_stat_mapping_registers *stat_mappings =
 841                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 842         uint32_t qsmr_mask = 0;
 843         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 844         uint32_t q_map;
 845         uint8_t n, offset;
 846
 847         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 848                 (hw->mac.type != ixgbe_mac_X540) &&
 849                 (hw->mac.type != ixgbe_mac_X550) &&
 850                 (hw->mac.type != ixgbe_mac_X550EM_x))
 851                 return -ENOSYS;
 852
 853         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 854                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 855                      queue_id, stat_idx);
 856
 857         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 858         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 859                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 860                 return -EIO;
 861         }
 862         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 863
 864         /* Now clear any previous stat_idx set */
 865         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 866         if (!is_rx)
 867                 stat_mappings->tqsm[n] &= ~clearing_mask;
 868         else
 869                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 870
 871         q_map = (uint32_t)stat_idx;
 872         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 873         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 874         if (!is_rx)
 875                 stat_mappings->tqsm[n] |= qsmr_mask;
 876         else
 877                 stat_mappings->rqsmr[n] |= qsmr_mask;
 878
 879         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 880                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 881                      queue_id, stat_idx);
 882         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 883                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 884
 885         /* Now write the mapping in the appropriate register */
 886         if (is_rx) {
 887                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 888                              stat_mappings->rqsmr[n], n);
 889                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 890         }
 891         else {
 892                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 893                              stat_mappings->tqsm[n], n);
 894                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 895         }
 896         return 0;
 897 }
 898
 899 static void
 900 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 901 {
 902         struct ixgbe_stat_mapping_registers *stat_mappings =
 903                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 905         int i;
 906
 907         /* write whatever was in stat mapping table to the NIC */
 908         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 909                 /* rx */
 910                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 911
 912                 /* tx */
 913                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 914         }
 915 }
 916
 917 static void
 918 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 919 {
 920         uint8_t i;
 921         struct ixgbe_dcb_tc_config *tc;
 922         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 923
 924         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 925         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 926         for (i = 0; i < dcb_max_tc; i++) {
 927                 tc = &dcb_config->tc_config[i];
 928                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 929                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 930                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 931                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 932                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 933                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 934                 tc->pfc = ixgbe_dcb_pfc_disabled;
 935         }
 936
 937         /* Initialize default user to priority mapping, UPx->TC0 */
 938         tc = &dcb_config->tc_config[0];
 939         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 940         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 941         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 942                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 943                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 944         }
 945         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 946         dcb_config->pfc_mode_enable = false;
 947         dcb_config->vt_mode = true;
 948         dcb_config->round_robin_enable = false;
 949         /* support all DCB capabilities in 82599 */
 950         dcb_config->support.capabilities = 0xFF;
 951
 952         /*we only support 4 Tcs for X540, X550 */
 953         if (hw->mac.type == ixgbe_mac_X540 ||
 954                 hw->mac.type == ixgbe_mac_X550 ||
 955                 hw->mac.type == ixgbe_mac_X550EM_x) {
 956                 dcb_config->num_tcs.pg_tcs = 4;
 957                 dcb_config->num_tcs.pfc_tcs = 4;
 958         }
 959 }
 960
 961 /*
 962  * Ensure that all locks are released before first NVM or PHY access
 963  */
 964 static void
 965 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 966 {
 967         uint16_t mask;
 968
 969         /*
 970          * Phy lock should not fail in this early stage. If this is the case,
 971          * it is due to an improper exit of the application.
 972          * So force the release of the faulty lock. Release of common lock
 973          * is done automatically by swfw_sync function.
 974          */
 975         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 976         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 977                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 978         }
 979         ixgbe_release_swfw_semaphore(hw, mask);
 980
 981         /*
 982          * These ones are more tricky since they are common to all ports; but
 983          * swfw_sync retries last long enough (1s) to be almost sure that if
 984          * lock can not be taken it is due to an improper lock of the
 985          * semaphore.
 986          */
 987         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 988         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 989                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 990         }
 991         ixgbe_release_swfw_semaphore(hw, mask);
 992 }
 993
 994 /*
 995  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 996  * It returns 0 on success.
 997  */
 998 static int
 999 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1000 {
1001         struct rte_pci_device *pci_dev;
1002         struct ixgbe_hw *hw =
1003                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1004         struct ixgbe_vfta * shadow_vfta =
1005                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1006         struct ixgbe_hwstrip *hwstrip =
1007                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1008         struct ixgbe_dcb_config *dcb_config =
1009                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1010         struct ixgbe_filter_info *filter_info =
1011                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1012         uint32_t ctrl_ext;
1013         uint16_t csum;
1014         int diag, i;
1015
1016         PMD_INIT_FUNC_TRACE();
1017
1018         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1019         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1020         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1021
1022         /*
1023          * For secondary processes, we don't initialise any further as primary
1024          * has already done this work. Only check we don't need a different
1025          * RX and TX function.
1026          */
1027         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1028                 struct ixgbe_tx_queue *txq;
1029                 /* TX queue function in primary, set by last queue initialized
1030                  * Tx queue may not initialized by primary process */
1031                 if (eth_dev->data->tx_queues) {
1032                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1033                         ixgbe_set_tx_function(eth_dev, txq);
1034                 } else {
1035                         /* Use default TX function if we get here */
1036                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1037                                              "Using default TX function.");
1038                 }
1039
1040                 ixgbe_set_rx_function(eth_dev);
1041
1042                 return 0;
1043         }
1044         pci_dev = eth_dev->pci_dev;
1045
1046         rte_eth_copy_pci_info(eth_dev, pci_dev);
1047
1048         /* Vendor and Device ID need to be set before init of shared code */
1049         hw->device_id = pci_dev->id.device_id;
1050         hw->vendor_id = pci_dev->id.vendor_id;
1051         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1052         hw->allow_unsupported_sfp = 1;
1053
1054         /* Initialize the shared code (base driver) */
1055 #ifdef RTE_NIC_BYPASS
1056         diag = ixgbe_bypass_init_shared_code(hw);
1057 #else
1058         diag = ixgbe_init_shared_code(hw);
1059 #endif /* RTE_NIC_BYPASS */
1060
1061         if (diag != IXGBE_SUCCESS) {
1062                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1063                 return -EIO;
1064         }
1065
1066         /* pick up the PCI bus settings for reporting later */
1067         ixgbe_get_bus_info(hw);
1068
1069         /* Unlock any pending hardware semaphore */
1070         ixgbe_swfw_lock_reset(hw);
1071
1072         /* Initialize DCB configuration*/
1073         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1074         ixgbe_dcb_init(hw,dcb_config);
1075         /* Get Hardware Flow Control setting */
1076         hw->fc.requested_mode = ixgbe_fc_full;
1077         hw->fc.current_mode = ixgbe_fc_full;
1078         hw->fc.pause_time = IXGBE_FC_PAUSE;
1079         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1080                 hw->fc.low_water[i] = IXGBE_FC_LO;
1081                 hw->fc.high_water[i] = IXGBE_FC_HI;
1082         }
1083         hw->fc.send_xon = 1;
1084
1085         /* Make sure we have a good EEPROM before we read from it */
1086         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1087         if (diag != IXGBE_SUCCESS) {
1088                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1089                 return -EIO;
1090         }
1091
1092 #ifdef RTE_NIC_BYPASS
1093         diag = ixgbe_bypass_init_hw(hw);
1094 #else
1095         diag = ixgbe_init_hw(hw);
1096 #endif /* RTE_NIC_BYPASS */
1097
1098         /*
1099          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1100          * is called too soon after the kernel driver unbinding/binding occurs.
1101          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1102          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1103          * also called. See ixgbe_identify_phy_82599(). The reason for the
1104          * failure is not known, and only occuts when virtualisation features
1105          * are disabled in the bios. A delay of 100ms  was found to be enough by
1106          * trial-and-error, and is doubled to be safe.
1107          */
1108         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1109                 rte_delay_ms(200);
1110                 diag = ixgbe_init_hw(hw);
1111         }
1112
1113         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1114                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1115                     "LOM.  Please be aware there may be issues associated "
1116                     "with your hardware.");
1117                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1118                     "please contact your Intel or hardware representative "
1119                     "who provided you with this hardware.");
1120         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1121                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1122         if (diag) {
1123                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1124                 return -EIO;
1125         }
1126
1127         /* Reset the hw statistics */
1128         ixgbe_dev_stats_reset(eth_dev);
1129
1130         /* disable interrupt */
1131         ixgbe_disable_intr(hw);
1132
1133         /* reset mappings for queue statistics hw counters*/
1134         ixgbe_reset_qstat_mappings(hw);
1135
1136         /* Allocate memory for storing MAC addresses */
1137         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1138                         hw->mac.num_rar_entries, 0);
1139         if (eth_dev->data->mac_addrs == NULL) {
1140                 PMD_INIT_LOG(ERR,
1141                         "Failed to allocate %u bytes needed to store "
1142                         "MAC addresses",
1143                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1144                 return -ENOMEM;
1145         }
1146         /* Copy the permanent MAC address */
1147         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1148                         &eth_dev->data->mac_addrs[0]);
1149
1150         /* Allocate memory for storing hash filter MAC addresses */
1151         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1152                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1153         if (eth_dev->data->hash_mac_addrs == NULL) {
1154                 PMD_INIT_LOG(ERR,
1155                         "Failed to allocate %d bytes needed to store MAC addresses",
1156                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1157                 return -ENOMEM;
1158         }
1159
1160         /* initialize the vfta */
1161         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1162
1163         /* initialize the hw strip bitmap*/
1164         memset(hwstrip, 0, sizeof(*hwstrip));
1165
1166         /* initialize PF if max_vfs not zero */
1167         ixgbe_pf_host_init(eth_dev);
1168
1169         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1170         /* let hardware know driver is loaded */
1171         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1172         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1173         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1174         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1175         IXGBE_WRITE_FLUSH(hw);
1176
1177         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1178                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1179                              (int) hw->mac.type, (int) hw->phy.type,
1180                              (int) hw->phy.sfp_type);
1181         else
1182                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1183                              (int) hw->mac.type, (int) hw->phy.type);
1184
1185         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1186                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1187                         pci_dev->id.device_id);
1188
1189         rte_intr_callback_register(&pci_dev->intr_handle,
1190                                    ixgbe_dev_interrupt_handler,
1191                                    (void *)eth_dev);
1192
1193         /* enable uio/vfio intr/eventfd mapping */
1194         rte_intr_enable(&pci_dev->intr_handle);
1195
1196         /* enable support intr */
1197         ixgbe_enable_intr(eth_dev);
1198
1199         /* initialize 5tuple filter list */
1200         TAILQ_INIT(&filter_info->fivetuple_list);
1201         memset(filter_info->fivetuple_mask, 0,
1202                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1203
1204         return 0;
1205 }
1206
1207 static int
1208 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1209 {
1210         struct rte_pci_device *pci_dev;
1211         struct ixgbe_hw *hw;
1212
1213         PMD_INIT_FUNC_TRACE();
1214
1215         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1216                 return -EPERM;
1217
1218         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1219         pci_dev = eth_dev->pci_dev;
1220
1221         if (hw->adapter_stopped == 0)
1222                 ixgbe_dev_close(eth_dev);
1223
1224         eth_dev->dev_ops = NULL;
1225         eth_dev->rx_pkt_burst = NULL;
1226         eth_dev->tx_pkt_burst = NULL;
1227
1228         /* Unlock any pending hardware semaphore */
1229         ixgbe_swfw_lock_reset(hw);
1230
1231         /* disable uio intr before callback unregister */
1232         rte_intr_disable(&(pci_dev->intr_handle));
1233         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1234                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1235
1236         /* uninitialize PF if max_vfs not zero */
1237         ixgbe_pf_host_uninit(eth_dev);
1238
1239         rte_free(eth_dev->data->mac_addrs);
1240         eth_dev->data->mac_addrs = NULL;
1241
1242         rte_free(eth_dev->data->hash_mac_addrs);
1243         eth_dev->data->hash_mac_addrs = NULL;
1244
1245         return 0;
1246 }
1247
1248 /*
1249  * Negotiate mailbox API version with the PF.
1250  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1251  * Then we try to negotiate starting with the most recent one.
1252  * If all negotiation attempts fail, then we will proceed with
1253  * the default one (ixgbe_mbox_api_10).
1254  */
1255 static void
1256 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1257 {
1258         int32_t i;
1259
1260         /* start with highest supported, proceed down */
1261         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1262                 ixgbe_mbox_api_11,
1263                 ixgbe_mbox_api_10,
1264         };
1265
1266         for (i = 0;
1267                         i != RTE_DIM(sup_ver) &&
1268                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1269                         i++)
1270                 ;
1271 }
1272
1273 static void
1274 generate_random_mac_addr(struct ether_addr *mac_addr)
1275 {
1276         uint64_t random;
1277
1278         /* Set Organizationally Unique Identifier (OUI) prefix. */
1279         mac_addr->addr_bytes[0] = 0x00;
1280         mac_addr->addr_bytes[1] = 0x09;
1281         mac_addr->addr_bytes[2] = 0xC0;
1282         /* Force indication of locally assigned MAC address. */
1283         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1284         /* Generate the last 3 bytes of the MAC address with a random number. */
1285         random = rte_rand();
1286         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1287 }
1288
1289 /*
1290  * Virtual Function device init
1291  */
1292 static int
1293 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1294 {
1295         int diag;
1296         uint32_t tc, tcs;
1297         struct rte_pci_device *pci_dev;
1298         struct ixgbe_hw *hw =
1299                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1300         struct ixgbe_vfta * shadow_vfta =
1301                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1302         struct ixgbe_hwstrip *hwstrip =
1303                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1304         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1305
1306         PMD_INIT_FUNC_TRACE();
1307
1308         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1309         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1310         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1311
1312         /* for secondary processes, we don't initialise any further as primary
1313          * has already done this work. Only check we don't need a different
1314          * RX function */
1315         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1316                 if (eth_dev->data->scattered_rx)
1317                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1318                 return 0;
1319         }
1320
1321         pci_dev = eth_dev->pci_dev;
1322
1323         rte_eth_copy_pci_info(eth_dev, pci_dev);
1324
1325         hw->device_id = pci_dev->id.device_id;
1326         hw->vendor_id = pci_dev->id.vendor_id;
1327         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1328
1329         /* initialize the vfta */
1330         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1331
1332         /* initialize the hw strip bitmap*/
1333         memset(hwstrip, 0, sizeof(*hwstrip));
1334
1335         /* Initialize the shared code (base driver) */
1336         diag = ixgbe_init_shared_code(hw);
1337         if (diag != IXGBE_SUCCESS) {
1338                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1339                 return -EIO;
1340         }
1341
1342         /* init_mailbox_params */
1343         hw->mbx.ops.init_params(hw);
1344
1345         /* Reset the hw statistics */
1346         ixgbevf_dev_stats_reset(eth_dev);
1347
1348         /* Disable the interrupts for VF */
1349         ixgbevf_intr_disable(hw);
1350
1351         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1352         diag = hw->mac.ops.reset_hw(hw);
1353
1354         /*
1355          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1356          * the underlying PF driver has not assigned a MAC address to the VF.
1357          * In this case, assign a random MAC address.
1358          */
1359         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1360                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1361                 return diag;
1362         }
1363
1364         /* negotiate mailbox API version to use with the PF. */
1365         ixgbevf_negotiate_api(hw);
1366
1367         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1368         ixgbevf_get_queues(hw, &tcs, &tc);
1369
1370         /* Allocate memory for storing MAC addresses */
1371         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1372                         hw->mac.num_rar_entries, 0);
1373         if (eth_dev->data->mac_addrs == NULL) {
1374                 PMD_INIT_LOG(ERR,
1375                         "Failed to allocate %u bytes needed to store "
1376                         "MAC addresses",
1377                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1378                 return -ENOMEM;
1379         }
1380
1381         /* Generate a random MAC address, if none was assigned by PF. */
1382         if (is_zero_ether_addr(perm_addr)) {
1383                 generate_random_mac_addr(perm_addr);
1384                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1385                 if (diag) {
1386                         rte_free(eth_dev->data->mac_addrs);
1387                         eth_dev->data->mac_addrs = NULL;
1388                         return diag;
1389                 }
1390                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1391                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1392                              "%02x:%02x:%02x:%02x:%02x:%02x",
1393                              perm_addr->addr_bytes[0],
1394                              perm_addr->addr_bytes[1],
1395                              perm_addr->addr_bytes[2],
1396                              perm_addr->addr_bytes[3],
1397                              perm_addr->addr_bytes[4],
1398                              perm_addr->addr_bytes[5]);
1399         }
1400
1401         /* Copy the permanent MAC address */
1402         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1403
1404         /* reset the hardware with the new settings */
1405         diag = hw->mac.ops.start_hw(hw);
1406         switch (diag) {
1407                 case  0:
1408                         break;
1409
1410                 default:
1411                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1412                         return -EIO;
1413         }
1414
1415         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1416                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1417                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1418
1419         return 0;
1420 }
1421
1422 /* Virtual Function device uninit */
1423
1424 static int
1425 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1426 {
1427         struct ixgbe_hw *hw;
1428         unsigned i;
1429
1430         PMD_INIT_FUNC_TRACE();
1431
1432         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1433                 return -EPERM;
1434
1435         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1436
1437         if (hw->adapter_stopped == 0)
1438                 ixgbevf_dev_close(eth_dev);
1439
1440         eth_dev->dev_ops = NULL;
1441         eth_dev->rx_pkt_burst = NULL;
1442         eth_dev->tx_pkt_burst = NULL;
1443
1444         /* Disable the interrupts for VF */
1445         ixgbevf_intr_disable(hw);
1446
1447         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1448                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1449                 eth_dev->data->rx_queues[i] = NULL;
1450         }
1451         eth_dev->data->nb_rx_queues = 0;
1452
1453         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1454                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1455                 eth_dev->data->tx_queues[i] = NULL;
1456         }
1457         eth_dev->data->nb_tx_queues = 0;
1458
1459         rte_free(eth_dev->data->mac_addrs);
1460         eth_dev->data->mac_addrs = NULL;
1461
1462         return 0;
1463 }
1464
1465 static struct eth_driver rte_ixgbe_pmd = {
1466         .pci_drv = {
1467                 .name = "rte_ixgbe_pmd",
1468                 .id_table = pci_id_ixgbe_map,
1469                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1470                         RTE_PCI_DRV_DETACHABLE,
1471         },
1472         .eth_dev_init = eth_ixgbe_dev_init,
1473         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1474         .dev_private_size = sizeof(struct ixgbe_adapter),
1475 };
1476
1477 /*
1478  * virtual function driver struct
1479  */
1480 static struct eth_driver rte_ixgbevf_pmd = {
1481         .pci_drv = {
1482                 .name = "rte_ixgbevf_pmd",
1483                 .id_table = pci_id_ixgbevf_map,
1484                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1485         },
1486         .eth_dev_init = eth_ixgbevf_dev_init,
1487         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1488         .dev_private_size = sizeof(struct ixgbe_adapter),
1489 };
1490
1491 /*
1492  * Driver initialization routine.
1493  * Invoked once at EAL init time.
1494  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1495  */
1496 static int
1497 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1498 {
1499         PMD_INIT_FUNC_TRACE();
1500
1501         rte_eth_driver_register(&rte_ixgbe_pmd);
1502         return 0;
1503 }
1504
1505 /*
1506  * VF Driver initialization routine.
1507  * Invoked one at EAL init time.
1508  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1509  */
1510 static int
1511 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1512 {
1513         PMD_INIT_FUNC_TRACE();
1514
1515         rte_eth_driver_register(&rte_ixgbevf_pmd);
1516         return 0;
1517 }
1518
1519 static int
1520 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1521 {
1522         struct ixgbe_hw *hw =
1523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524         struct ixgbe_vfta * shadow_vfta =
1525                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1526         uint32_t vfta;
1527         uint32_t vid_idx;
1528         uint32_t vid_bit;
1529
1530         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1531         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1532         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1533         if (on)
1534                 vfta |= vid_bit;
1535         else
1536                 vfta &= ~vid_bit;
1537         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1538
1539         /* update local VFTA copy */
1540         shadow_vfta->vfta[vid_idx] = vfta;
1541
1542         return 0;
1543 }
1544
1545 static void
1546 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1547 {
1548         if (on)
1549                 ixgbe_vlan_hw_strip_enable(dev, queue);
1550         else
1551                 ixgbe_vlan_hw_strip_disable(dev, queue);
1552 }
1553
1554 static int
1555 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1556                     enum rte_vlan_type vlan_type,
1557                     uint16_t tpid)
1558 {
1559         struct ixgbe_hw *hw =
1560                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1561         int ret = 0;
1562
1563         switch (vlan_type) {
1564         case ETH_VLAN_TYPE_INNER:
1565                 /* Only the high 16-bits is valid */
1566                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1567                 break;
1568         default:
1569                 ret = -EINVAL;
1570                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1571                 break;
1572         }
1573
1574         return ret;
1575 }
1576
1577 void
1578 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1579 {
1580         struct ixgbe_hw *hw =
1581                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582         uint32_t vlnctrl;
1583
1584         PMD_INIT_FUNC_TRACE();
1585
1586         /* Filter Table Disable */
1587         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1588         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1589
1590         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1591 }
1592
1593 void
1594 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1595 {
1596         struct ixgbe_hw *hw =
1597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598         struct ixgbe_vfta * shadow_vfta =
1599                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1600         uint32_t vlnctrl;
1601         uint16_t i;
1602
1603         PMD_INIT_FUNC_TRACE();
1604
1605         /* Filter Table Enable */
1606         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1607         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1608         vlnctrl |= IXGBE_VLNCTRL_VFE;
1609
1610         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1611
1612         /* write whatever is in local vfta copy */
1613         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1614                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1615 }
1616
1617 static void
1618 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1619 {
1620         struct ixgbe_hwstrip *hwstrip =
1621                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1622
1623         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1624                 return;
1625
1626         if (on)
1627                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1628         else
1629                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1630 }
1631
1632 static void
1633 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1634 {
1635         struct ixgbe_hw *hw =
1636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         uint32_t ctrl;
1638
1639         PMD_INIT_FUNC_TRACE();
1640
1641         if (hw->mac.type == ixgbe_mac_82598EB) {
1642                 /* No queue level support */
1643                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1644                 return;
1645         }
1646         else {
1647                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1648                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1649                 ctrl &= ~IXGBE_RXDCTL_VME;
1650                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1651         }
1652         /* record those setting for HW strip per queue */
1653         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1654 }
1655
1656 static void
1657 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1658 {
1659         struct ixgbe_hw *hw =
1660                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1661         uint32_t ctrl;
1662
1663         PMD_INIT_FUNC_TRACE();
1664
1665         if (hw->mac.type == ixgbe_mac_82598EB) {
1666                 /* No queue level supported */
1667                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1668                 return;
1669         }
1670         else {
1671                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1672                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1673                 ctrl |= IXGBE_RXDCTL_VME;
1674                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1675         }
1676         /* record those setting for HW strip per queue */
1677         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1678 }
1679
1680 void
1681 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1682 {
1683         struct ixgbe_hw *hw =
1684                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         uint32_t ctrl;
1686         uint16_t i;
1687
1688         PMD_INIT_FUNC_TRACE();
1689
1690         if (hw->mac.type == ixgbe_mac_82598EB) {
1691                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1692                 ctrl &= ~IXGBE_VLNCTRL_VME;
1693                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1694         }
1695         else {
1696                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1697                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1698                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1699                         ctrl &= ~IXGBE_RXDCTL_VME;
1700                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1701
1702                         /* record those setting for HW strip per queue */
1703                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1704                 }
1705         }
1706 }
1707
1708 void
1709 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1710 {
1711         struct ixgbe_hw *hw =
1712                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1713         uint32_t ctrl;
1714         uint16_t i;
1715
1716         PMD_INIT_FUNC_TRACE();
1717
1718         if (hw->mac.type == ixgbe_mac_82598EB) {
1719                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1720                 ctrl |= IXGBE_VLNCTRL_VME;
1721                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1722         }
1723         else {
1724                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1725                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1726                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1727                         ctrl |= IXGBE_RXDCTL_VME;
1728                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1729
1730                         /* record those setting for HW strip per queue */
1731                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1732                 }
1733         }
1734 }
1735
1736 static void
1737 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1738 {
1739         struct ixgbe_hw *hw =
1740                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1741         uint32_t ctrl;
1742
1743         PMD_INIT_FUNC_TRACE();
1744
1745         /* DMATXCTRL: Geric Double VLAN Disable */
1746         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1747         ctrl &= ~IXGBE_DMATXCTL_GDV;
1748         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1749
1750         /* CTRL_EXT: Global Double VLAN Disable */
1751         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1752         ctrl &= ~IXGBE_EXTENDED_VLAN;
1753         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1754
1755 }
1756
1757 static void
1758 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1759 {
1760         struct ixgbe_hw *hw =
1761                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1762         uint32_t ctrl;
1763
1764         PMD_INIT_FUNC_TRACE();
1765
1766         /* DMATXCTRL: Geric Double VLAN Enable */
1767         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1768         ctrl |= IXGBE_DMATXCTL_GDV;
1769         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1770
1771         /* CTRL_EXT: Global Double VLAN Enable */
1772         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1773         ctrl |= IXGBE_EXTENDED_VLAN;
1774         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1775
1776         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1777         if (hw->mac.type == ixgbe_mac_X550 ||
1778             hw->mac.type == ixgbe_mac_X550EM_x) {
1779                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1780                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1781                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1782         }
1783
1784         /*
1785          * VET EXT field in the EXVET register = 0x8100 by default
1786          * So no need to change. Same to VT field of DMATXCTL register
1787          */
1788 }
1789
1790 static void
1791 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1792 {
1793         if (mask & ETH_VLAN_STRIP_MASK) {
1794                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1795                         ixgbe_vlan_hw_strip_enable_all(dev);
1796                 else
1797                         ixgbe_vlan_hw_strip_disable_all(dev);
1798         }
1799
1800         if (mask & ETH_VLAN_FILTER_MASK) {
1801                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1802                         ixgbe_vlan_hw_filter_enable(dev);
1803                 else
1804                         ixgbe_vlan_hw_filter_disable(dev);
1805         }
1806
1807         if (mask & ETH_VLAN_EXTEND_MASK) {
1808                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1809                         ixgbe_vlan_hw_extend_enable(dev);
1810                 else
1811                         ixgbe_vlan_hw_extend_disable(dev);
1812         }
1813 }
1814
1815 static void
1816 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1817 {
1818         struct ixgbe_hw *hw =
1819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1821         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1822         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1823         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1824 }
1825
1826 static int
1827 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1828 {
1829         switch (nb_rx_q) {
1830         case 1:
1831         case 2:
1832                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1833                 break;
1834         case 4:
1835                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1836                 break;
1837         default:
1838                 return -EINVAL;
1839         }
1840
1841         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1842         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1843
1844         return 0;
1845 }
1846
1847 static int
1848 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1849 {
1850         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1851         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1852         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1853
1854         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1855                 /* check multi-queue mode */
1856                 switch (dev_conf->rxmode.mq_mode) {
1857                 case ETH_MQ_RX_VMDQ_DCB:
1858                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1859                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1860                         PMD_INIT_LOG(ERR, "SRIOV active,"
1861                                         " unsupported mq_mode rx %d.",
1862                                         dev_conf->rxmode.mq_mode);
1863                         return -EINVAL;
1864                 case ETH_MQ_RX_RSS:
1865                 case ETH_MQ_RX_VMDQ_RSS:
1866                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1867                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1868                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1869                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1870                                                 " invalid queue number"
1871                                                 " for VMDQ RSS, allowed"
1872                                                 " value are 1, 2 or 4.");
1873                                         return -EINVAL;
1874                                 }
1875                         break;
1876                 case ETH_MQ_RX_VMDQ_ONLY:
1877                 case ETH_MQ_RX_NONE:
1878                         /* if nothing mq mode configure, use default scheme */
1879                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1880                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1881                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1882                         break;
1883                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1884                         /* SRIOV only works in VMDq enable mode */
1885                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1886                                         " wrong mq_mode rx %d.",
1887                                         dev_conf->rxmode.mq_mode);
1888                         return -EINVAL;
1889                 }
1890
1891                 switch (dev_conf->txmode.mq_mode) {
1892                 case ETH_MQ_TX_VMDQ_DCB:
1893                         /* DCB VMDQ in SRIOV mode, not implement yet */
1894                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1895                                         " unsupported VMDQ mq_mode tx %d.",
1896                                         dev_conf->txmode.mq_mode);
1897                         return -EINVAL;
1898                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1899                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1900                         break;
1901                 }
1902
1903                 /* check valid queue number */
1904                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1905                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1906                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1907                                         " queue number must less equal to %d.",
1908                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1909                         return -EINVAL;
1910                 }
1911         } else {
1912                 /* check configuration for vmdb+dcb mode */
1913                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1914                         const struct rte_eth_vmdq_dcb_conf *conf;
1915
1916                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1917                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1918                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1919                                 return -EINVAL;
1920                         }
1921                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1922                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1923                                conf->nb_queue_pools == ETH_32_POOLS)) {
1924                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1925                                                 " nb_queue_pools must be %d or %d.",
1926                                                 ETH_16_POOLS, ETH_32_POOLS);
1927                                 return -EINVAL;
1928                         }
1929                 }
1930                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1931                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1932
1933                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1934                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1935                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1936                                 return -EINVAL;
1937                         }
1938                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1939                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1940                                conf->nb_queue_pools == ETH_32_POOLS)) {
1941                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1942                                                 " nb_queue_pools != %d and"
1943                                                 " nb_queue_pools != %d.",
1944                                                 ETH_16_POOLS, ETH_32_POOLS);
1945                                 return -EINVAL;
1946                         }
1947                 }
1948
1949                 /* For DCB mode check our configuration before we go further */
1950                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1951                         const struct rte_eth_dcb_rx_conf *conf;
1952
1953                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1954                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1955                                                  IXGBE_DCB_NB_QUEUES);
1956                                 return -EINVAL;
1957                         }
1958                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1959                         if (!(conf->nb_tcs == ETH_4_TCS ||
1960                                conf->nb_tcs == ETH_8_TCS)) {
1961                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1962                                                 " and nb_tcs != %d.",
1963                                                 ETH_4_TCS, ETH_8_TCS);
1964                                 return -EINVAL;
1965                         }
1966                 }
1967
1968                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1969                         const struct rte_eth_dcb_tx_conf *conf;
1970
1971                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1972                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1973                                                  IXGBE_DCB_NB_QUEUES);
1974                                 return -EINVAL;
1975                         }
1976                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1977                         if (!(conf->nb_tcs == ETH_4_TCS ||
1978                                conf->nb_tcs == ETH_8_TCS)) {
1979                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1980                                                 " and nb_tcs != %d.",
1981                                                 ETH_4_TCS, ETH_8_TCS);
1982                                 return -EINVAL;
1983                         }
1984                 }
1985         }
1986         return 0;
1987 }
1988
1989 static int
1990 ixgbe_dev_configure(struct rte_eth_dev *dev)
1991 {
1992         struct ixgbe_interrupt *intr =
1993                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1994         struct ixgbe_adapter *adapter =
1995                 (struct ixgbe_adapter *)dev->data->dev_private;
1996         int ret;
1997
1998         PMD_INIT_FUNC_TRACE();
1999         /* multipe queue mode checking */
2000         ret  = ixgbe_check_mq_mode(dev);
2001         if (ret != 0) {
2002                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2003                             ret);
2004                 return ret;
2005         }
2006
2007         /* set flag to update link status after init */
2008         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2009
2010         /*
2011          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2012          * allocation or vector Rx preconditions we will reset it.
2013          */
2014         adapter->rx_bulk_alloc_allowed = true;
2015         adapter->rx_vec_allowed = true;
2016
2017         return 0;
2018 }
2019
2020 /*
2021  * Configure device link speed and setup link.
2022  * It returns 0 on success.
2023  */
2024 static int
2025 ixgbe_dev_start(struct rte_eth_dev *dev)
2026 {
2027         struct ixgbe_hw *hw =
2028                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         struct ixgbe_vf_info *vfinfo =
2030                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2031         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2032         uint32_t intr_vector = 0;
2033         int err, link_up = 0, negotiate = 0;
2034         uint32_t speed = 0;
2035         int mask = 0;
2036         int status;
2037         uint16_t vf, idx;
2038
2039         PMD_INIT_FUNC_TRACE();
2040
2041         /* IXGBE devices don't support half duplex */
2042         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2043                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2044                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2045                              dev->data->dev_conf.link_duplex,
2046                              dev->data->port_id);
2047                 return -EINVAL;
2048         }
2049
2050         /* disable uio/vfio intr/eventfd mapping */
2051         rte_intr_disable(intr_handle);
2052
2053         /* stop adapter */
2054         hw->adapter_stopped = 0;
2055         ixgbe_stop_adapter(hw);
2056
2057         /* reinitialize adapter
2058          * this calls reset and start */
2059         status = ixgbe_pf_reset_hw(hw);
2060         if (status != 0)
2061                 return -1;
2062         hw->mac.ops.start_hw(hw);
2063         hw->mac.get_link_status = true;
2064
2065         /* configure PF module if SRIOV enabled */
2066         ixgbe_pf_host_configure(dev);
2067
2068         /* check and configure queue intr-vector mapping */
2069         if ((rte_intr_cap_multiple(intr_handle) ||
2070              !RTE_ETH_DEV_SRIOV(dev).active) &&
2071             dev->data->dev_conf.intr_conf.rxq != 0) {
2072                 intr_vector = dev->data->nb_rx_queues;
2073                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2074                         return -1;
2075         }
2076
2077         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2078                 intr_handle->intr_vec =
2079                         rte_zmalloc("intr_vec",
2080                                     dev->data->nb_rx_queues * sizeof(int), 0);
2081                 if (intr_handle->intr_vec == NULL) {
2082                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2083                                      " intr_vec\n", dev->data->nb_rx_queues);
2084                         return -ENOMEM;
2085                 }
2086         }
2087
2088         /* confiugre msix for sleep until rx interrupt */
2089         ixgbe_configure_msix(dev);
2090
2091         /* initialize transmission unit */
2092         ixgbe_dev_tx_init(dev);
2093
2094         /* This can fail when allocating mbufs for descriptor rings */
2095         err = ixgbe_dev_rx_init(dev);
2096         if (err) {
2097                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2098                 goto error;
2099         }
2100
2101         err = ixgbe_dev_rxtx_start(dev);
2102         if (err < 0) {
2103                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2104                 goto error;
2105         }
2106
2107         /* Skip link setup if loopback mode is enabled for 82599. */
2108         if (hw->mac.type == ixgbe_mac_82599EB &&
2109                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2110                 goto skip_link_setup;
2111
2112         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2113                 err = hw->mac.ops.setup_sfp(hw);
2114                 if (err)
2115                         goto error;
2116         }
2117
2118         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2119                 /* Turn on the copper */
2120                 ixgbe_set_phy_power(hw, true);
2121         } else {
2122                 /* Turn on the laser */
2123                 ixgbe_enable_tx_laser(hw);
2124         }
2125
2126         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2127         if (err)
2128                 goto error;
2129         dev->data->dev_link.link_status = link_up;
2130
2131         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2132         if (err)
2133                 goto error;
2134
2135         switch(dev->data->dev_conf.link_speed) {
2136         case ETH_LINK_SPEED_AUTONEG:
2137                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2138                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2139                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2140                 break;
2141         case ETH_LINK_SPEED_100:
2142                 /*
2143                  * Invalid for 82598 but error will be detected by
2144                  * ixgbe_setup_link()
2145                  */
2146                 speed = IXGBE_LINK_SPEED_100_FULL;
2147                 break;
2148         case ETH_LINK_SPEED_1000:
2149                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2150                 break;
2151         case ETH_LINK_SPEED_10000:
2152                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2153                 break;
2154         default:
2155                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2156                              dev->data->dev_conf.link_speed,
2157                              dev->data->port_id);
2158                 goto error;
2159         }
2160
2161         err = ixgbe_setup_link(hw, speed, link_up);
2162         if (err)
2163                 goto error;
2164
2165 skip_link_setup:
2166
2167         if (rte_intr_allow_others(intr_handle)) {
2168                 /* check if lsc interrupt is enabled */
2169                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2170                         ixgbe_dev_lsc_interrupt_setup(dev);
2171         } else {
2172                 rte_intr_callback_unregister(intr_handle,
2173                                              ixgbe_dev_interrupt_handler,
2174                                              (void *)dev);
2175                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2176                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2177                                      " no intr multiplex\n");
2178         }
2179
2180         /* check if rxq interrupt is enabled */
2181         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2182             rte_intr_dp_is_en(intr_handle))
2183                 ixgbe_dev_rxq_interrupt_setup(dev);
2184
2185         /* enable uio/vfio intr/eventfd mapping */
2186         rte_intr_enable(intr_handle);
2187
2188         /* resume enabled intr since hw reset */
2189         ixgbe_enable_intr(dev);
2190
2191         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2192                 ETH_VLAN_EXTEND_MASK;
2193         ixgbe_vlan_offload_set(dev, mask);
2194
2195         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2196                 /* Enable vlan filtering for VMDq */
2197                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2198         }
2199
2200         /* Configure DCB hw */
2201         ixgbe_configure_dcb(dev);
2202
2203         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2204                 err = ixgbe_fdir_configure(dev);
2205                 if (err)
2206                         goto error;
2207         }
2208
2209         /* Restore vf rate limit */
2210         if (vfinfo != NULL) {
2211                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2212                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2213                                 if (vfinfo[vf].tx_rate[idx] != 0)
2214                                         ixgbe_set_vf_rate_limit(dev, vf,
2215                                                 vfinfo[vf].tx_rate[idx],
2216                                                 1 << idx);
2217         }
2218
2219         ixgbe_restore_statistics_mapping(dev);
2220
2221         return 0;
2222
2223 error:
2224         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2225         ixgbe_dev_clear_queues(dev);
2226         return -EIO;
2227 }
2228
2229 /*
2230  * Stop device: disable rx and tx functions to allow for reconfiguring.
2231  */
2232 static void
2233 ixgbe_dev_stop(struct rte_eth_dev *dev)
2234 {
2235         struct rte_eth_link link;
2236         struct ixgbe_hw *hw =
2237                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238         struct ixgbe_vf_info *vfinfo =
2239                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2240         struct ixgbe_filter_info *filter_info =
2241                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2242         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2243         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2244         int vf;
2245
2246         PMD_INIT_FUNC_TRACE();
2247
2248         /* disable interrupts */
2249         ixgbe_disable_intr(hw);
2250
2251         /* reset the NIC */
2252         ixgbe_pf_reset_hw(hw);
2253         hw->adapter_stopped = 0;
2254
2255         /* stop adapter */
2256         ixgbe_stop_adapter(hw);
2257
2258         for (vf = 0; vfinfo != NULL &&
2259                      vf < dev->pci_dev->max_vfs; vf++)
2260                 vfinfo[vf].clear_to_send = false;
2261
2262         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2263                 /* Turn off the copper */
2264                 ixgbe_set_phy_power(hw, false);
2265         } else {
2266                 /* Turn off the laser */
2267                 ixgbe_disable_tx_laser(hw);
2268         }
2269
2270         ixgbe_dev_clear_queues(dev);
2271
2272         /* Clear stored conf */
2273         dev->data->scattered_rx = 0;
2274         dev->data->lro = 0;
2275
2276         /* Clear recorded link status */
2277         memset(&link, 0, sizeof(link));
2278         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2279
2280         /* Remove all ntuple filters of the device */
2281         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2282              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2283                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2284                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2285                              p_5tuple, entries);
2286                 rte_free(p_5tuple);
2287         }
2288         memset(filter_info->fivetuple_mask, 0,
2289                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2290
2291         if (!rte_intr_allow_others(intr_handle))
2292                 /* resume to the default handler */
2293                 rte_intr_callback_register(intr_handle,
2294                                            ixgbe_dev_interrupt_handler,
2295                                            (void *)dev);
2296
2297         /* Clean datapath event and queue/vec mapping */
2298         rte_intr_efd_disable(intr_handle);
2299         if (intr_handle->intr_vec != NULL) {
2300                 rte_free(intr_handle->intr_vec);
2301                 intr_handle->intr_vec = NULL;
2302         }
2303 }
2304
2305 /*
2306  * Set device link up: enable tx.
2307  */
2308 static int
2309 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2310 {
2311         struct ixgbe_hw *hw =
2312                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2313         if (hw->mac.type == ixgbe_mac_82599EB) {
2314 #ifdef RTE_NIC_BYPASS
2315                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2316                         /* Not suported in bypass mode */
2317                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2318                                      "by device id 0x%x", hw->device_id);
2319                         return -ENOTSUP;
2320                 }
2321 #endif
2322         }
2323
2324         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2325                 /* Turn on the copper */
2326                 ixgbe_set_phy_power(hw, true);
2327         } else {
2328                 /* Turn on the laser */
2329                 ixgbe_enable_tx_laser(hw);
2330         }
2331
2332         return 0;
2333 }
2334
2335 /*
2336  * Set device link down: disable tx.
2337  */
2338 static int
2339 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2340 {
2341         struct ixgbe_hw *hw =
2342                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343         if (hw->mac.type == ixgbe_mac_82599EB) {
2344 #ifdef RTE_NIC_BYPASS
2345                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2346                         /* Not suported in bypass mode */
2347                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2348                                      "by device id 0x%x", hw->device_id);
2349                         return -ENOTSUP;
2350                 }
2351 #endif
2352         }
2353
2354         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2355                 /* Turn off the copper */
2356                 ixgbe_set_phy_power(hw, false);
2357         } else {
2358                 /* Turn off the laser */
2359                 ixgbe_disable_tx_laser(hw);
2360         }
2361
2362         return 0;
2363 }
2364
2365 /*
2366  * Reest and stop device.
2367  */
2368 static void
2369 ixgbe_dev_close(struct rte_eth_dev *dev)
2370 {
2371         struct ixgbe_hw *hw =
2372                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373
2374         PMD_INIT_FUNC_TRACE();
2375
2376         ixgbe_pf_reset_hw(hw);
2377
2378         ixgbe_dev_stop(dev);
2379         hw->adapter_stopped = 1;
2380
2381         ixgbe_dev_free_queues(dev);
2382
2383         ixgbe_disable_pcie_master(hw);
2384
2385         /* reprogram the RAR[0] in case user changed it. */
2386         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2387 }
2388
2389 static void
2390 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2391                            struct ixgbe_hw_stats *hw_stats,
2392                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2393                            uint64_t *total_qprc, uint64_t *total_qprdc)
2394 {
2395         uint32_t bprc, lxon, lxoff, total;
2396         uint32_t delta_gprc = 0;
2397         unsigned i;
2398         /* Workaround for RX byte count not including CRC bytes when CRC
2399 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2400          * is disabled.
2401 +        */
2402         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2403                         IXGBE_HLREG0_RXCRCSTRP);
2404
2405         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2406         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2407         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2408         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2409
2410         for (i = 0; i < 8; i++) {
2411                 uint32_t mp;
2412                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2413                 /* global total per queue */
2414                 hw_stats->mpc[i] += mp;
2415                 /* Running comprehensive total for stats display */
2416                 *total_missed_rx += hw_stats->mpc[i];
2417                 if (hw->mac.type == ixgbe_mac_82598EB) {
2418                         hw_stats->rnbc[i] +=
2419                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2420                         hw_stats->pxonrxc[i] +=
2421                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2422                         hw_stats->pxoffrxc[i] +=
2423                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2424                 } else {
2425                         hw_stats->pxonrxc[i] +=
2426                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2427                         hw_stats->pxoffrxc[i] +=
2428                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2429                         hw_stats->pxon2offc[i] +=
2430                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2431                 }
2432                 hw_stats->pxontxc[i] +=
2433                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2434                 hw_stats->pxofftxc[i] +=
2435                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2436         }
2437         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2438                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2439                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2440                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2441
2442                 delta_gprc += delta_qprc;
2443
2444                 hw_stats->qprc[i] += delta_qprc;
2445                 hw_stats->qptc[i] += delta_qptc;
2446
2447                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2448                 hw_stats->qbrc[i] +=
2449                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2450                 if (crc_strip == 0)
2451                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2452
2453                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2454                 hw_stats->qbtc[i] +=
2455                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2456
2457                 hw_stats->qprdc[i] += delta_qprdc;
2458                 *total_qprdc += hw_stats->qprdc[i];
2459
2460                 *total_qprc += hw_stats->qprc[i];
2461                 *total_qbrc += hw_stats->qbrc[i];
2462         }
2463         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2464         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2465         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2466
2467         /*
2468          * An errata states that gprc actually counts good + missed packets:
2469          * Workaround to set gprc to summated queue packet receives
2470          */
2471         hw_stats->gprc = *total_qprc;
2472
2473         if (hw->mac.type != ixgbe_mac_82598EB) {
2474                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2475                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2476                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2477                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2478                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2479                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2480                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2481                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2482         } else {
2483                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2484                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2485                 /* 82598 only has a counter in the high register */
2486                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2487                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2488                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2489         }
2490         uint64_t old_tpr = hw_stats->tpr;
2491
2492         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2493         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2494
2495         if (crc_strip == 0)
2496                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2497
2498         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2499         hw_stats->gptc += delta_gptc;
2500         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2501         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2502
2503         /*
2504          * Workaround: mprc hardware is incorrectly counting
2505          * broadcasts, so for now we subtract those.
2506          */
2507         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2508         hw_stats->bprc += bprc;
2509         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2510         if (hw->mac.type == ixgbe_mac_82598EB)
2511                 hw_stats->mprc -= bprc;
2512
2513         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2514         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2515         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2516         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2517         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2518         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2519
2520         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2521         hw_stats->lxontxc += lxon;
2522         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2523         hw_stats->lxofftxc += lxoff;
2524         total = lxon + lxoff;
2525
2526         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2527         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2528         hw_stats->gptc -= total;
2529         hw_stats->mptc -= total;
2530         hw_stats->ptc64 -= total;
2531         hw_stats->gotc -= total * ETHER_MIN_LEN;
2532
2533         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2534         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2535         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2536         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2537         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2538         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2539         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2540         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2541         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2542         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2543         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2544         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2545         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2546         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2547         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2548         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2549         /* Only read FCOE on 82599 */
2550         if (hw->mac.type != ixgbe_mac_82598EB) {
2551                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2552                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2553                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2554                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2555                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2556         }
2557
2558         /* Flow Director Stats registers */
2559         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2560         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2561 }
2562
2563 /*
2564  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2565  */
2566 static void
2567 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2568 {
2569         struct ixgbe_hw *hw =
2570                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2571         struct ixgbe_hw_stats *hw_stats =
2572                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2573         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2574         unsigned i;
2575
2576         total_missed_rx = 0;
2577         total_qbrc = 0;
2578         total_qprc = 0;
2579         total_qprdc = 0;
2580
2581         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2582                         &total_qprc, &total_qprdc);
2583
2584         if (stats == NULL)
2585                 return;
2586
2587         /* Fill out the rte_eth_stats statistics structure */
2588         stats->ipackets = total_qprc;
2589         stats->ibytes = total_qbrc;
2590         stats->opackets = hw_stats->gptc;
2591         stats->obytes = hw_stats->gotc;
2592
2593         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2594                 stats->q_ipackets[i] = hw_stats->qprc[i];
2595                 stats->q_opackets[i] = hw_stats->qptc[i];
2596                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2597                 stats->q_obytes[i] = hw_stats->qbtc[i];
2598                 stats->q_errors[i] = hw_stats->qprdc[i];
2599         }
2600
2601         /* Rx Errors */
2602         stats->imissed  = total_missed_rx;
2603         stats->ierrors  = hw_stats->crcerrs +
2604                           hw_stats->mspdc +
2605                           hw_stats->rlec +
2606                           hw_stats->ruc +
2607                           hw_stats->roc +
2608                           total_missed_rx +
2609                           hw_stats->illerrc +
2610                           hw_stats->errbc +
2611                           hw_stats->rfc +
2612                           hw_stats->fccrc +
2613                           hw_stats->fclast;
2614
2615         /* Tx Errors */
2616         stats->oerrors  = 0;
2617 }
2618
2619 static void
2620 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2621 {
2622         struct ixgbe_hw_stats *stats =
2623                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2624
2625         /* HW registers are cleared on read */
2626         ixgbe_dev_stats_get(dev, NULL);
2627
2628         /* Reset software totals */
2629         memset(stats, 0, sizeof(*stats));
2630 }
2631
2632 /* This function calculates the number of xstats based on the current config */
2633 static unsigned
2634 ixgbe_xstats_calc_num(void) {
2635         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2636                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2637 }
2638
2639 static int
2640 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2641                                          unsigned n)
2642 {
2643         struct ixgbe_hw *hw =
2644                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2645         struct ixgbe_hw_stats *hw_stats =
2646                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2647         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2648         unsigned i, stat, count = 0;
2649
2650         count = ixgbe_xstats_calc_num();
2651
2652         if (n < count)
2653                 return count;
2654
2655         total_missed_rx = 0;
2656         total_qbrc = 0;
2657         total_qprc = 0;
2658         total_qprdc = 0;
2659
2660         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2661                                    &total_qprc, &total_qprdc);
2662
2663         /* If this is a reset xstats is NULL, and we have cleared the
2664          * registers by reading them.
2665          */
2666         if (!xstats)
2667                 return 0;
2668
2669         /* Extended stats from ixgbe_hw_stats */
2670         count = 0;
2671         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2672                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2673                          rte_ixgbe_stats_strings[i].name);
2674                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2675                                 rte_ixgbe_stats_strings[i].offset);
2676                 count++;
2677         }
2678
2679         /* RX Priority Stats */
2680         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2681                 for (i = 0; i < 8; i++) {
2682                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2683                                  "rx_priority%u_%s", i,
2684                                  rte_ixgbe_rxq_strings[stat].name);
2685                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2686                                         rte_ixgbe_rxq_strings[stat].offset +
2687                                         (sizeof(uint64_t) * i));
2688                         count++;
2689                 }
2690         }
2691
2692         /* TX Priority Stats */
2693         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2694                 for (i = 0; i < 8; i++) {
2695                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2696                                  "tx_priority%u_%s", i,
2697                                  rte_ixgbe_txq_strings[stat].name);
2698                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2699                                         rte_ixgbe_txq_strings[stat].offset +
2700                                         (sizeof(uint64_t) * i));
2701                         count++;
2702                 }
2703         }
2704
2705         return count;
2706 }
2707
2708 static void
2709 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2710 {
2711         struct ixgbe_hw_stats *stats =
2712                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2713
2714         unsigned count = ixgbe_xstats_calc_num();
2715
2716         /* HW registers are cleared on read */
2717         ixgbe_dev_xstats_get(dev, NULL, count);
2718
2719         /* Reset software totals */
2720         memset(stats, 0, sizeof(*stats));
2721 }
2722
2723 static void
2724 ixgbevf_update_stats(struct rte_eth_dev *dev)
2725 {
2726         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2727         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2728                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2729
2730         /* Good Rx packet, include VF loopback */
2731         UPDATE_VF_STAT(IXGBE_VFGPRC,
2732             hw_stats->last_vfgprc, hw_stats->vfgprc);
2733
2734         /* Good Rx octets, include VF loopback */
2735         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2736             hw_stats->last_vfgorc, hw_stats->vfgorc);
2737
2738         /* Good Tx packet, include VF loopback */
2739         UPDATE_VF_STAT(IXGBE_VFGPTC,
2740             hw_stats->last_vfgptc, hw_stats->vfgptc);
2741
2742         /* Good Tx octets, include VF loopback */
2743         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2744             hw_stats->last_vfgotc, hw_stats->vfgotc);
2745
2746         /* Rx Multicst Packet */
2747         UPDATE_VF_STAT(IXGBE_VFMPRC,
2748             hw_stats->last_vfmprc, hw_stats->vfmprc);
2749 }
2750
2751 static int
2752 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2753                        unsigned n)
2754 {
2755         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2756                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2757         unsigned i;
2758
2759         if (n < IXGBEVF_NB_XSTATS)
2760                 return IXGBEVF_NB_XSTATS;
2761
2762         ixgbevf_update_stats(dev);
2763
2764         if (!xstats)
2765                 return 0;
2766
2767         /* Extended stats */
2768         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2769                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2770                          "%s", rte_ixgbevf_stats_strings[i].name);
2771                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2772                         rte_ixgbevf_stats_strings[i].offset);
2773         }
2774
2775         return IXGBEVF_NB_XSTATS;
2776 }
2777
2778 static void
2779 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2780 {
2781         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2782                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2783
2784         ixgbevf_update_stats(dev);
2785
2786         if (stats == NULL)
2787                 return;
2788
2789         stats->ipackets = hw_stats->vfgprc;
2790         stats->ibytes = hw_stats->vfgorc;
2791         stats->opackets = hw_stats->vfgptc;
2792         stats->obytes = hw_stats->vfgotc;
2793         stats->imcasts = hw_stats->vfmprc;
2794         /* stats->imcasts should be removed as imcasts is deprecated */
2795 }
2796
2797 static void
2798 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2799 {
2800         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2801                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2802
2803         /* Sync HW register to the last stats */
2804         ixgbevf_dev_stats_get(dev, NULL);
2805
2806         /* reset HW current stats*/
2807         hw_stats->vfgprc = 0;
2808         hw_stats->vfgorc = 0;
2809         hw_stats->vfgptc = 0;
2810         hw_stats->vfgotc = 0;
2811         hw_stats->vfmprc = 0;
2812
2813 }
2814
2815 static void
2816 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2817 {
2818         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819
2820         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2821         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2822         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2823         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2824         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2825         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2826         dev_info->max_vfs = dev->pci_dev->max_vfs;
2827         if (hw->mac.type == ixgbe_mac_82598EB)
2828                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2829         else
2830                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2831         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2832         dev_info->rx_offload_capa =
2833                 DEV_RX_OFFLOAD_VLAN_STRIP |
2834                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2835                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2836                 DEV_RX_OFFLOAD_TCP_CKSUM;
2837
2838         /*
2839          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2840          * mode.
2841          */
2842         if ((hw->mac.type == ixgbe_mac_82599EB ||
2843              hw->mac.type == ixgbe_mac_X540) &&
2844             !RTE_ETH_DEV_SRIOV(dev).active)
2845                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2846
2847         if (hw->mac.type == ixgbe_mac_X550 ||
2848             hw->mac.type == ixgbe_mac_X550EM_x)
2849                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2850
2851         dev_info->tx_offload_capa =
2852                 DEV_TX_OFFLOAD_VLAN_INSERT |
2853                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2854                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2855                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2856                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2857                 DEV_TX_OFFLOAD_TCP_TSO;
2858
2859         if (hw->mac.type == ixgbe_mac_X550 ||
2860             hw->mac.type == ixgbe_mac_X550EM_x)
2861                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2862
2863         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2864                 .rx_thresh = {
2865                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2866                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2867                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2868                 },
2869                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2870                 .rx_drop_en = 0,
2871         };
2872
2873         dev_info->default_txconf = (struct rte_eth_txconf) {
2874                 .tx_thresh = {
2875                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2876                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2877                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2878                 },
2879                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2880                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2881                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2882                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2883         };
2884
2885         dev_info->rx_desc_lim = rx_desc_lim;
2886         dev_info->tx_desc_lim = tx_desc_lim;
2887
2888         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2889         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2890         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2891 }
2892
2893 static void
2894 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2895                      struct rte_eth_dev_info *dev_info)
2896 {
2897         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2898
2899         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2900         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2901         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2902         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2903         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2904         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2905         dev_info->max_vfs = dev->pci_dev->max_vfs;
2906         if (hw->mac.type == ixgbe_mac_82598EB)
2907                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2908         else
2909                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2910         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2911                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2912                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2913                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2914         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2915                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2916                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2917                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2918                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2919                                 DEV_TX_OFFLOAD_TCP_TSO;
2920
2921         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2922                 .rx_thresh = {
2923                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2924                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2925                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2926                 },
2927                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2928                 .rx_drop_en = 0,
2929         };
2930
2931         dev_info->default_txconf = (struct rte_eth_txconf) {
2932                 .tx_thresh = {
2933                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2934                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2935                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2936                 },
2937                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2938                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2939                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2940                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2941         };
2942
2943         dev_info->rx_desc_lim = rx_desc_lim;
2944         dev_info->tx_desc_lim = tx_desc_lim;
2945 }
2946
2947 /* return 0 means link status changed, -1 means not changed */
2948 static int
2949 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2950 {
2951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952         struct rte_eth_link link, old;
2953         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2954         int link_up;
2955         int diag;
2956
2957         link.link_status = 0;
2958         link.link_speed = 0;
2959         link.link_duplex = 0;
2960         memset(&old, 0, sizeof(old));
2961         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2962
2963         hw->mac.get_link_status = true;
2964
2965         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2966         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2967                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2968         else
2969                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2970
2971         if (diag != 0) {
2972                 link.link_speed = ETH_LINK_SPEED_100;
2973                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2974                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2975                 if (link.link_status == old.link_status)
2976                         return -1;
2977                 return 0;
2978         }
2979
2980         if (link_up == 0) {
2981                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2982                 if (link.link_status == old.link_status)
2983                         return -1;
2984                 return 0;
2985         }
2986         link.link_status = 1;
2987         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2988
2989         switch (link_speed) {
2990         default:
2991         case IXGBE_LINK_SPEED_UNKNOWN:
2992                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2993                 link.link_speed = ETH_LINK_SPEED_100;
2994                 break;
2995
2996         case IXGBE_LINK_SPEED_100_FULL:
2997                 link.link_speed = ETH_LINK_SPEED_100;
2998                 break;
2999
3000         case IXGBE_LINK_SPEED_1GB_FULL:
3001                 link.link_speed = ETH_LINK_SPEED_1000;
3002                 break;
3003
3004         case IXGBE_LINK_SPEED_10GB_FULL:
3005                 link.link_speed = ETH_LINK_SPEED_10000;
3006                 break;
3007         }
3008         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3009
3010         if (link.link_status == old.link_status)
3011                 return -1;
3012
3013         return 0;
3014 }
3015
3016 static void
3017 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3018 {
3019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3020         uint32_t fctrl;
3021
3022         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3023         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3024         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3025 }
3026
3027 static void
3028 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3029 {
3030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3031         uint32_t fctrl;
3032
3033         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3034         fctrl &= (~IXGBE_FCTRL_UPE);
3035         if (dev->data->all_multicast == 1)
3036                 fctrl |= IXGBE_FCTRL_MPE;
3037         else
3038                 fctrl &= (~IXGBE_FCTRL_MPE);
3039         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3040 }
3041
3042 static void
3043 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3044 {
3045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3046         uint32_t fctrl;
3047
3048         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3049         fctrl |= IXGBE_FCTRL_MPE;
3050         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3051 }
3052
3053 static void
3054 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3055 {
3056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3057         uint32_t fctrl;
3058
3059         if (dev->data->promiscuous == 1)
3060                 return; /* must remain in all_multicast mode */
3061
3062         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3063         fctrl &= (~IXGBE_FCTRL_MPE);
3064         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3065 }
3066
3067 /**
3068  * It clears the interrupt causes and enables the interrupt.
3069  * It will be called once only during nic initialized.
3070  *
3071  * @param dev
3072  *  Pointer to struct rte_eth_dev.
3073  *
3074  * @return
3075  *  - On success, zero.
3076  *  - On failure, a negative value.
3077  */
3078 static int
3079 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3080 {
3081         struct ixgbe_interrupt *intr =
3082                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3083
3084         ixgbe_dev_link_status_print(dev);
3085         intr->mask |= IXGBE_EICR_LSC;
3086
3087         return 0;
3088 }
3089
3090 /**
3091  * It clears the interrupt causes and enables the interrupt.
3092  * It will be called once only during nic initialized.
3093  *
3094  * @param dev
3095  *  Pointer to struct rte_eth_dev.
3096  *
3097  * @return
3098  *  - On success, zero.
3099  *  - On failure, a negative value.
3100  */
3101 static int
3102 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3103 {
3104         struct ixgbe_interrupt *intr =
3105                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3106
3107         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3108
3109         return 0;
3110 }
3111
3112 /*
3113  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3114  *
3115  * @param dev
3116  *  Pointer to struct rte_eth_dev.
3117  *
3118  * @return
3119  *  - On success, zero.
3120  *  - On failure, a negative value.
3121  */
3122 static int
3123 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3124 {
3125         uint32_t eicr;
3126         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3127         struct ixgbe_interrupt *intr =
3128                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3129
3130         /* clear all cause mask */
3131         ixgbe_disable_intr(hw);
3132
3133         /* read-on-clear nic registers here */
3134         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3135         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3136
3137         intr->flags = 0;
3138
3139         /* set flag for async link update */
3140         if (eicr & IXGBE_EICR_LSC)
3141                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3142
3143         if (eicr & IXGBE_EICR_MAILBOX)
3144                 intr->flags |= IXGBE_FLAG_MAILBOX;
3145
3146         return 0;
3147 }
3148
3149 /**
3150  * It gets and then prints the link status.
3151  *
3152  * @param dev
3153  *  Pointer to struct rte_eth_dev.
3154  *
3155  * @return
3156  *  - On success, zero.
3157  *  - On failure, a negative value.
3158  */
3159 static void
3160 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3161 {
3162         struct rte_eth_link link;
3163
3164         memset(&link, 0, sizeof(link));
3165         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3166         if (link.link_status) {
3167                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3168                                         (int)(dev->data->port_id),
3169                                         (unsigned)link.link_speed,
3170                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3171                                         "full-duplex" : "half-duplex");
3172         } else {
3173                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3174                                 (int)(dev->data->port_id));
3175         }
3176         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3177                                 dev->pci_dev->addr.domain,
3178                                 dev->pci_dev->addr.bus,
3179                                 dev->pci_dev->addr.devid,
3180                                 dev->pci_dev->addr.function);
3181 }
3182
3183 /*
3184  * It executes link_update after knowing an interrupt occurred.
3185  *
3186  * @param dev
3187  *  Pointer to struct rte_eth_dev.
3188  *
3189  * @return
3190  *  - On success, zero.
3191  *  - On failure, a negative value.
3192  */
3193 static int
3194 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3195 {
3196         struct ixgbe_interrupt *intr =
3197                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3198         int64_t timeout;
3199         struct rte_eth_link link;
3200         int intr_enable_delay = false;
3201
3202         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3203
3204         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3205                 ixgbe_pf_mbx_process(dev);
3206                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3207         }
3208
3209         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3210                 /* get the link status before link update, for predicting later */
3211                 memset(&link, 0, sizeof(link));
3212                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3213
3214                 ixgbe_dev_link_update(dev, 0);
3215
3216                 /* likely to up */
3217                 if (!link.link_status)
3218                         /* handle it 1 sec later, wait it being stable */
3219                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3220                 /* likely to down */
3221                 else
3222                         /* handle it 4 sec later, wait it being stable */
3223                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3224
3225                 ixgbe_dev_link_status_print(dev);
3226
3227                 intr_enable_delay = true;
3228         }
3229
3230         if (intr_enable_delay) {
3231                 if (rte_eal_alarm_set(timeout * 1000,
3232                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3233                         PMD_DRV_LOG(ERR, "Error setting alarm");
3234         } else {
3235                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3236                 ixgbe_enable_intr(dev);
3237                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3238         }
3239
3240
3241         return 0;
3242 }
3243
3244 /**
3245  * Interrupt handler which shall be registered for alarm callback for delayed
3246  * handling specific interrupt to wait for the stable nic state. As the
3247  * NIC interrupt state is not stable for ixgbe after link is just down,
3248  * it needs to wait 4 seconds to get the stable status.
3249  *
3250  * @param handle
3251  *  Pointer to interrupt handle.
3252  * @param param
3253  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3254  *
3255  * @return
3256  *  void
3257  */
3258 static void
3259 ixgbe_dev_interrupt_delayed_handler(void *param)
3260 {
3261         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3262         struct ixgbe_interrupt *intr =
3263                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3264         struct ixgbe_hw *hw =
3265                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3266         uint32_t eicr;
3267
3268         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3269         if (eicr & IXGBE_EICR_MAILBOX)
3270                 ixgbe_pf_mbx_process(dev);
3271
3272         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3273                 ixgbe_dev_link_update(dev, 0);
3274                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3275                 ixgbe_dev_link_status_print(dev);
3276                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3277         }
3278
3279         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3280         ixgbe_enable_intr(dev);
3281         rte_intr_enable(&(dev->pci_dev->intr_handle));
3282 }
3283
3284 /**
3285  * Interrupt handler triggered by NIC  for handling
3286  * specific interrupt.
3287  *
3288  * @param handle
3289  *  Pointer to interrupt handle.
3290  * @param param
3291  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3292  *
3293  * @return
3294  *  void
3295  */
3296 static void
3297 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3298                             void *param)
3299 {
3300         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3301
3302         ixgbe_dev_interrupt_get_status(dev);
3303         ixgbe_dev_interrupt_action(dev);
3304 }
3305
3306 static int
3307 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3308 {
3309         struct ixgbe_hw *hw;
3310
3311         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3313 }
3314
3315 static int
3316 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3317 {
3318         struct ixgbe_hw *hw;
3319
3320         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3321         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3322 }
3323
3324 static int
3325 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3326 {
3327         struct ixgbe_hw *hw;
3328         uint32_t mflcn_reg;
3329         uint32_t fccfg_reg;
3330         int rx_pause;
3331         int tx_pause;
3332
3333         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3334
3335         fc_conf->pause_time = hw->fc.pause_time;
3336         fc_conf->high_water = hw->fc.high_water[0];
3337         fc_conf->low_water = hw->fc.low_water[0];
3338         fc_conf->send_xon = hw->fc.send_xon;
3339         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3340
3341         /*
3342          * Return rx_pause status according to actual setting of
3343          * MFLCN register.
3344          */
3345         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3346         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3347                 rx_pause = 1;
3348         else
3349                 rx_pause = 0;
3350
3351         /*
3352          * Return tx_pause status according to actual setting of
3353          * FCCFG register.
3354          */
3355         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3356         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3357                 tx_pause = 1;
3358         else
3359                 tx_pause = 0;
3360
3361         if (rx_pause && tx_pause)
3362                 fc_conf->mode = RTE_FC_FULL;
3363         else if (rx_pause)
3364                 fc_conf->mode = RTE_FC_RX_PAUSE;
3365         else if (tx_pause)
3366                 fc_conf->mode = RTE_FC_TX_PAUSE;
3367         else
3368                 fc_conf->mode = RTE_FC_NONE;
3369
3370         return 0;
3371 }
3372
3373 static int
3374 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3375 {
3376         struct ixgbe_hw *hw;
3377         int err;
3378         uint32_t rx_buf_size;
3379         uint32_t max_high_water;
3380         uint32_t mflcn;
3381         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3382                 ixgbe_fc_none,
3383                 ixgbe_fc_rx_pause,
3384                 ixgbe_fc_tx_pause,
3385                 ixgbe_fc_full
3386         };
3387
3388         PMD_INIT_FUNC_TRACE();
3389
3390         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3391         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3392         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3393
3394         /*
3395          * At least reserve one Ethernet frame for watermark
3396          * high_water/low_water in kilo bytes for ixgbe
3397          */
3398         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3399         if ((fc_conf->high_water > max_high_water) ||
3400                 (fc_conf->high_water < fc_conf->low_water)) {
3401                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3402                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3403                 return -EINVAL;
3404         }
3405
3406         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3407         hw->fc.pause_time     = fc_conf->pause_time;
3408         hw->fc.high_water[0]  = fc_conf->high_water;
3409         hw->fc.low_water[0]   = fc_conf->low_water;
3410         hw->fc.send_xon       = fc_conf->send_xon;
3411         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3412
3413         err = ixgbe_fc_enable(hw);
3414
3415         /* Not negotiated is not an error case */
3416         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3417
3418                 /* check if we want to forward MAC frames - driver doesn't have native
3419                  * capability to do that, so we'll write the registers ourselves */
3420
3421                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3422
3423                 /* set or clear MFLCN.PMCF bit depending on configuration */
3424                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3425                         mflcn |= IXGBE_MFLCN_PMCF;
3426                 else
3427                         mflcn &= ~IXGBE_MFLCN_PMCF;
3428
3429                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3430                 IXGBE_WRITE_FLUSH(hw);
3431
3432                 return 0;
3433         }
3434
3435         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3436         return -EIO;
3437 }
3438
3439 /**
3440  *  ixgbe_pfc_enable_generic - Enable flow control
3441  *  @hw: pointer to hardware structure
3442  *  @tc_num: traffic class number
3443  *  Enable flow control according to the current settings.
3444  */
3445 static int
3446 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3447 {
3448         int ret_val = 0;
3449         uint32_t mflcn_reg, fccfg_reg;
3450         uint32_t reg;
3451         uint32_t fcrtl, fcrth;
3452         uint8_t i;
3453         uint8_t nb_rx_en;
3454
3455         /* Validate the water mark configuration */
3456         if (!hw->fc.pause_time) {
3457                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3458                 goto out;
3459         }
3460
3461         /* Low water mark of zero causes XOFF floods */
3462         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3463                  /* High/Low water can not be 0 */
3464                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3465                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3466                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3467                         goto out;
3468                 }
3469
3470                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3471                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3472                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3473                         goto out;
3474                 }
3475         }
3476         /* Negotiate the fc mode to use */
3477         ixgbe_fc_autoneg(hw);
3478
3479         /* Disable any previous flow control settings */
3480         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3481         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3482
3483         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3484         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3485
3486         switch (hw->fc.current_mode) {
3487         case ixgbe_fc_none:
3488                 /*
3489                  * If the count of enabled RX Priority Flow control >1,
3490                  * and the TX pause can not be disabled
3491                  */
3492                 nb_rx_en = 0;
3493                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3494                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3495                         if (reg & IXGBE_FCRTH_FCEN)
3496                                 nb_rx_en++;
3497                 }
3498                 if (nb_rx_en > 1)
3499                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3500                 break;
3501         case ixgbe_fc_rx_pause:
3502                 /*
3503                  * Rx Flow control is enabled and Tx Flow control is
3504                  * disabled by software override. Since there really
3505                  * isn't a way to advertise that we are capable of RX
3506                  * Pause ONLY, we will advertise that we support both
3507                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3508                  * disable the adapter's ability to send PAUSE frames.
3509                  */
3510                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3511                 /*
3512                  * If the count of enabled RX Priority Flow control >1,
3513                  * and the TX pause can not be disabled
3514                  */
3515                 nb_rx_en = 0;
3516                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3517                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3518                         if (reg & IXGBE_FCRTH_FCEN)
3519                                 nb_rx_en++;
3520                 }
3521                 if (nb_rx_en > 1)
3522                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3523                 break;
3524         case ixgbe_fc_tx_pause:
3525                 /*
3526                  * Tx Flow control is enabled, and Rx Flow control is
3527                  * disabled by software override.
3528                  */
3529                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3530                 break;
3531         case ixgbe_fc_full:
3532                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3533                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3534                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3535                 break;
3536         default:
3537                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3538                 ret_val = IXGBE_ERR_CONFIG;
3539                 goto out;
3540                 break;
3541         }
3542
3543         /* Set 802.3x based flow control settings. */
3544         mflcn_reg |= IXGBE_MFLCN_DPF;
3545         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3546         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3547
3548         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3549         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3550                 hw->fc.high_water[tc_num]) {
3551                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3552                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3553                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3554         } else {
3555                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3556                 /*
3557                  * In order to prevent Tx hangs when the internal Tx
3558                  * switch is enabled we must set the high water mark
3559                  * to the maximum FCRTH value.  This allows the Tx
3560                  * switch to function even under heavy Rx workloads.
3561                  */
3562                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3563         }
3564         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3565
3566         /* Configure pause time (2 TCs per register) */
3567         reg = hw->fc.pause_time * 0x00010001;
3568         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3569                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3570
3571         /* Configure flow control refresh threshold value */
3572         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3573
3574 out:
3575         return ret_val;
3576 }
3577
3578 static int
3579 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3580 {
3581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3582         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3583
3584         if (hw->mac.type != ixgbe_mac_82598EB) {
3585                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3586         }
3587         return ret_val;
3588 }
3589
3590 static int
3591 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3592 {
3593         int err;
3594         uint32_t rx_buf_size;
3595         uint32_t max_high_water;
3596         uint8_t tc_num;
3597         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3598         struct ixgbe_hw *hw =
3599                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3600         struct ixgbe_dcb_config *dcb_config =
3601                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3602
3603         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3604                 ixgbe_fc_none,
3605                 ixgbe_fc_rx_pause,
3606                 ixgbe_fc_tx_pause,
3607                 ixgbe_fc_full
3608         };
3609
3610         PMD_INIT_FUNC_TRACE();
3611
3612         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3613         tc_num = map[pfc_conf->priority];
3614         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3615         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3616         /*
3617          * At least reserve one Ethernet frame for watermark
3618          * high_water/low_water in kilo bytes for ixgbe
3619          */
3620         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3621         if ((pfc_conf->fc.high_water > max_high_water) ||
3622             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3623                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3624                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3625                 return -EINVAL;
3626         }
3627
3628         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3629         hw->fc.pause_time = pfc_conf->fc.pause_time;
3630         hw->fc.send_xon = pfc_conf->fc.send_xon;
3631         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3632         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3633
3634         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3635
3636         /* Not negotiated is not an error case */
3637         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3638                 return 0;
3639
3640         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3641         return -EIO;
3642 }
3643
3644 static int
3645 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3646                           struct rte_eth_rss_reta_entry64 *reta_conf,
3647                           uint16_t reta_size)
3648 {
3649         uint8_t i, j, mask;
3650         uint32_t reta, r;
3651         uint16_t idx, shift;
3652         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3653         uint16_t sp_reta_size;
3654         uint32_t reta_reg;
3655
3656         PMD_INIT_FUNC_TRACE();
3657
3658         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3659                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3660                         "NIC.");
3661                 return -ENOTSUP;
3662         }
3663
3664         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3665         if (reta_size != sp_reta_size) {
3666                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3667                         "(%d) doesn't match the number hardware can supported "
3668                         "(%d)\n", reta_size, sp_reta_size);
3669                 return -EINVAL;
3670         }
3671
3672         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3673                 idx = i / RTE_RETA_GROUP_SIZE;
3674                 shift = i % RTE_RETA_GROUP_SIZE;
3675                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3676                                                 IXGBE_4_BIT_MASK);
3677                 if (!mask)
3678                         continue;
3679                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3680                 if (mask == IXGBE_4_BIT_MASK)
3681                         r = 0;
3682                 else
3683                         r = IXGBE_READ_REG(hw, reta_reg);
3684                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3685                         if (mask & (0x1 << j))
3686                                 reta |= reta_conf[idx].reta[shift + j] <<
3687                                                         (CHAR_BIT * j);
3688                         else
3689                                 reta |= r & (IXGBE_8_BIT_MASK <<
3690                                                 (CHAR_BIT * j));
3691                 }
3692                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3693         }
3694
3695         return 0;
3696 }
3697
3698 static int
3699 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3700                          struct rte_eth_rss_reta_entry64 *reta_conf,
3701                          uint16_t reta_size)
3702 {
3703         uint8_t i, j, mask;
3704         uint32_t reta;
3705         uint16_t idx, shift;
3706         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3707         uint16_t sp_reta_size;
3708         uint32_t reta_reg;
3709
3710         PMD_INIT_FUNC_TRACE();
3711         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3712         if (reta_size != sp_reta_size) {
3713                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3714                         "(%d) doesn't match the number hardware can supported "
3715                         "(%d)\n", reta_size, sp_reta_size);
3716                 return -EINVAL;
3717         }
3718
3719         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3720                 idx = i / RTE_RETA_GROUP_SIZE;
3721                 shift = i % RTE_RETA_GROUP_SIZE;
3722                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3723                                                 IXGBE_4_BIT_MASK);
3724                 if (!mask)
3725                         continue;
3726
3727                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3728                 reta = IXGBE_READ_REG(hw, reta_reg);
3729                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3730                         if (mask & (0x1 << j))
3731                                 reta_conf[idx].reta[shift + j] =
3732                                         ((reta >> (CHAR_BIT * j)) &
3733                                                 IXGBE_8_BIT_MASK);
3734                 }
3735         }
3736
3737         return 0;
3738 }
3739
3740 static void
3741 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3742                                 uint32_t index, uint32_t pool)
3743 {
3744         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3745         uint32_t enable_addr = 1;
3746
3747         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3748 }
3749
3750 static void
3751 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3752 {
3753         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3754
3755         ixgbe_clear_rar(hw, index);
3756 }
3757
3758 static void
3759 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3760 {
3761         ixgbe_remove_rar(dev, 0);
3762
3763         ixgbe_add_rar(dev, addr, 0, 0);
3764 }
3765
3766 static int
3767 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3768 {
3769         uint32_t hlreg0;
3770         uint32_t maxfrs;
3771         struct ixgbe_hw *hw;
3772         struct rte_eth_dev_info dev_info;
3773         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3774
3775         ixgbe_dev_info_get(dev, &dev_info);
3776
3777         /* check that mtu is within the allowed range */
3778         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3779                 return -EINVAL;
3780
3781         /* refuse mtu that requires the support of scattered packets when this
3782          * feature has not been enabled before. */
3783         if (!dev->data->scattered_rx &&
3784             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3785              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3786                 return -EINVAL;
3787
3788         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3789         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3790
3791         /* switch to jumbo mode if needed */
3792         if (frame_size > ETHER_MAX_LEN) {
3793                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3794                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3795         } else {
3796                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3797                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3798         }
3799         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3800
3801         /* update max frame size */
3802         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3803
3804         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3805         maxfrs &= 0x0000FFFF;
3806         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3807         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3808
3809         return 0;
3810 }
3811
3812 /*
3813  * Virtual Function operations
3814  */
3815 static void
3816 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3817 {
3818         PMD_INIT_FUNC_TRACE();
3819
3820         /* Clear interrupt mask to stop from interrupts being generated */
3821         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3822
3823         IXGBE_WRITE_FLUSH(hw);
3824 }
3825
3826 static void
3827 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3828 {
3829         PMD_INIT_FUNC_TRACE();
3830
3831         /* VF enable interrupt autoclean */
3832         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3833         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3834         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3835
3836         IXGBE_WRITE_FLUSH(hw);
3837 }
3838
3839 static int
3840 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3841 {
3842         struct rte_eth_conf* conf = &dev->data->dev_conf;
3843         struct ixgbe_adapter *adapter =
3844                         (struct ixgbe_adapter *)dev->data->dev_private;
3845
3846         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3847                      dev->data->port_id);
3848
3849         /*
3850          * VF has no ability to enable/disable HW CRC
3851          * Keep the persistent behavior the same as Host PF
3852          */
3853 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3854         if (!conf->rxmode.hw_strip_crc) {
3855                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3856                 conf->rxmode.hw_strip_crc = 1;
3857         }
3858 #else
3859         if (conf->rxmode.hw_strip_crc) {
3860                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3861                 conf->rxmode.hw_strip_crc = 0;
3862         }
3863 #endif
3864
3865         /*
3866          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3867          * allocation or vector Rx preconditions we will reset it.
3868          */
3869         adapter->rx_bulk_alloc_allowed = true;
3870         adapter->rx_vec_allowed = true;
3871
3872         return 0;
3873 }
3874
3875 static int
3876 ixgbevf_dev_start(struct rte_eth_dev *dev)
3877 {
3878         struct ixgbe_hw *hw =
3879                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3880         uint32_t intr_vector = 0;
3881         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3882
3883         int err, mask = 0;
3884
3885         PMD_INIT_FUNC_TRACE();
3886
3887         hw->mac.ops.reset_hw(hw);
3888         hw->mac.get_link_status = true;
3889
3890         /* negotiate mailbox API version to use with the PF. */
3891         ixgbevf_negotiate_api(hw);
3892
3893         ixgbevf_dev_tx_init(dev);
3894
3895         /* This can fail when allocating mbufs for descriptor rings */
3896         err = ixgbevf_dev_rx_init(dev);
3897         if (err) {
3898                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3899                 ixgbe_dev_clear_queues(dev);
3900                 return err;
3901         }
3902
3903         /* Set vfta */
3904         ixgbevf_set_vfta_all(dev,1);
3905
3906         /* Set HW strip */
3907         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3908                 ETH_VLAN_EXTEND_MASK;
3909         ixgbevf_vlan_offload_set(dev, mask);
3910
3911         ixgbevf_dev_rxtx_start(dev);
3912
3913         /* check and configure queue intr-vector mapping */
3914         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3915                 intr_vector = dev->data->nb_rx_queues;
3916                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3917                         return -1;
3918         }
3919
3920         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3921                 intr_handle->intr_vec =
3922                         rte_zmalloc("intr_vec",
3923                                     dev->data->nb_rx_queues * sizeof(int), 0);
3924                 if (intr_handle->intr_vec == NULL) {
3925                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3926                                      " intr_vec\n", dev->data->nb_rx_queues);
3927                         return -ENOMEM;
3928                 }
3929         }
3930         ixgbevf_configure_msix(dev);
3931
3932         rte_intr_enable(intr_handle);
3933
3934         /* Re-enable interrupt for VF */
3935         ixgbevf_intr_enable(hw);
3936
3937         return 0;
3938 }
3939
3940 static void
3941 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3942 {
3943         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3945
3946         PMD_INIT_FUNC_TRACE();
3947
3948         hw->adapter_stopped = 1;
3949         ixgbe_stop_adapter(hw);
3950
3951         /*
3952           * Clear what we set, but we still keep shadow_vfta to
3953           * restore after device starts
3954           */
3955         ixgbevf_set_vfta_all(dev,0);
3956
3957         /* Clear stored conf */
3958         dev->data->scattered_rx = 0;
3959
3960         ixgbe_dev_clear_queues(dev);
3961
3962         /* Clean datapath event and queue/vec mapping */
3963         rte_intr_efd_disable(intr_handle);
3964         if (intr_handle->intr_vec != NULL) {
3965                 rte_free(intr_handle->intr_vec);
3966                 intr_handle->intr_vec = NULL;
3967         }
3968 }
3969
3970 static void
3971 ixgbevf_dev_close(struct rte_eth_dev *dev)
3972 {
3973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3974
3975         PMD_INIT_FUNC_TRACE();
3976
3977         ixgbe_reset_hw(hw);
3978
3979         ixgbevf_dev_stop(dev);
3980
3981         ixgbe_dev_free_queues(dev);
3982
3983         /* reprogram the RAR[0] in case user changed it. */
3984         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3985 }
3986
3987 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3988 {
3989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3990         struct ixgbe_vfta * shadow_vfta =
3991                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3992         int i = 0, j = 0, vfta = 0, mask = 1;
3993
3994         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3995                 vfta = shadow_vfta->vfta[i];
3996                 if (vfta) {
3997                         mask = 1;
3998                         for (j = 0; j < 32; j++){
3999                                 if (vfta & mask)
4000                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4001                                 mask<<=1;
4002                         }
4003                 }
4004         }
4005
4006 }
4007
4008 static int
4009 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4010 {
4011         struct ixgbe_hw *hw =
4012                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4013         struct ixgbe_vfta * shadow_vfta =
4014                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4015         uint32_t vid_idx = 0;
4016         uint32_t vid_bit = 0;
4017         int ret = 0;
4018
4019         PMD_INIT_FUNC_TRACE();
4020
4021         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4022         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4023         if (ret) {
4024                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4025                 return ret;
4026         }
4027         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4028         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4029
4030         /* Save what we set and retore it after device reset */
4031         if (on)
4032                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4033         else
4034                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4035
4036         return 0;
4037 }
4038
4039 static void
4040 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4041 {
4042         struct ixgbe_hw *hw =
4043                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4044         uint32_t ctrl;
4045
4046         PMD_INIT_FUNC_TRACE();
4047
4048         if (queue >= hw->mac.max_rx_queues)
4049                 return;
4050
4051         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4052         if (on)
4053                 ctrl |= IXGBE_RXDCTL_VME;
4054         else
4055                 ctrl &= ~IXGBE_RXDCTL_VME;
4056         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4057
4058         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4059 }
4060
4061 static void
4062 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4063 {
4064         struct ixgbe_hw *hw =
4065                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4066         uint16_t i;
4067         int on = 0;
4068
4069         /* VF function only support hw strip feature, others are not support */
4070         if (mask & ETH_VLAN_STRIP_MASK) {
4071                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4072
4073                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4074                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4075         }
4076 }
4077
4078 static int
4079 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4080 {
4081         uint32_t reg_val;
4082
4083         /* we only need to do this if VMDq is enabled */
4084         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4085         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4086                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4087                 return -1;
4088         }
4089
4090         return 0;
4091 }
4092
4093 static uint32_t
4094 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4095 {
4096         uint32_t vector = 0;
4097         switch (hw->mac.mc_filter_type) {
4098         case 0:   /* use bits [47:36] of the address */
4099                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4100                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4101                 break;
4102         case 1:   /* use bits [46:35] of the address */
4103                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4104                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4105                 break;
4106         case 2:   /* use bits [45:34] of the address */
4107                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4108                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4109                 break;
4110         case 3:   /* use bits [43:32] of the address */
4111                 vector = ((uc_addr->addr_bytes[4]) |
4112                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4113                 break;
4114         default:  /* Invalid mc_filter_type */
4115                 break;
4116         }
4117
4118         /* vector can only be 12-bits or boundary will be exceeded */
4119         vector &= 0xFFF;
4120         return vector;
4121 }
4122
4123 static int
4124 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4125                                uint8_t on)
4126 {
4127         uint32_t vector;
4128         uint32_t uta_idx;
4129         uint32_t reg_val;
4130         uint32_t uta_shift;
4131         uint32_t rc;
4132         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4133         const uint32_t ixgbe_uta_bit_shift = 5;
4134         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4135         const uint32_t bit1 = 0x1;
4136
4137         struct ixgbe_hw *hw =
4138                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4139         struct ixgbe_uta_info *uta_info =
4140                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4141
4142         /* The UTA table only exists on 82599 hardware and newer */
4143         if (hw->mac.type < ixgbe_mac_82599EB)
4144                 return -ENOTSUP;
4145
4146         vector = ixgbe_uta_vector(hw,mac_addr);
4147         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4148         uta_shift = vector & ixgbe_uta_bit_mask;
4149
4150         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4151         if (rc == on)
4152                 return 0;
4153
4154         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4155         if (on) {
4156                 uta_info->uta_in_use++;
4157                 reg_val |= (bit1 << uta_shift);
4158                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4159         } else {
4160                 uta_info->uta_in_use--;
4161                 reg_val &= ~(bit1 << uta_shift);
4162                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4163         }
4164
4165         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4166
4167         if (uta_info->uta_in_use > 0)
4168                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4169                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4170         else
4171                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4172
4173         return 0;
4174 }
4175
4176 static int
4177 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4178 {
4179         int i;
4180         struct ixgbe_hw *hw =
4181                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182         struct ixgbe_uta_info *uta_info =
4183                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4184
4185         /* The UTA table only exists on 82599 hardware and newer */
4186         if (hw->mac.type < ixgbe_mac_82599EB)
4187                 return -ENOTSUP;
4188
4189         if (on) {
4190                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4191                         uta_info->uta_shadow[i] = ~0;
4192                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4193                 }
4194         } else {
4195                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4196                         uta_info->uta_shadow[i] = 0;
4197                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4198                 }
4199         }
4200         return 0;
4201
4202 }
4203
4204 uint32_t
4205 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4206 {
4207         uint32_t new_val = orig_val;
4208
4209         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4210                 new_val |= IXGBE_VMOLR_AUPE;
4211         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4212                 new_val |= IXGBE_VMOLR_ROMPE;
4213         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4214                 new_val |= IXGBE_VMOLR_ROPE;
4215         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4216                 new_val |= IXGBE_VMOLR_BAM;
4217         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4218                 new_val |= IXGBE_VMOLR_MPE;
4219
4220         return new_val;
4221 }
4222
4223 static int
4224 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4225                                uint16_t rx_mask, uint8_t on)
4226 {
4227         int val = 0;
4228
4229         struct ixgbe_hw *hw =
4230                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4231         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4232
4233         if (hw->mac.type == ixgbe_mac_82598EB) {
4234                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4235                              " on 82599 hardware and newer");
4236                 return -ENOTSUP;
4237         }
4238         if (ixgbe_vmdq_mode_check(hw) < 0)
4239                 return -ENOTSUP;
4240
4241         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4242
4243         if (on)
4244                 vmolr |= val;
4245         else
4246                 vmolr &= ~val;
4247
4248         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4249
4250         return 0;
4251 }
4252
4253 static int
4254 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4255 {
4256         uint32_t reg,addr;
4257         uint32_t val;
4258         const uint8_t bit1 = 0x1;
4259
4260         struct ixgbe_hw *hw =
4261                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4262
4263         if (ixgbe_vmdq_mode_check(hw) < 0)
4264                 return -ENOTSUP;
4265
4266         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4267         reg = IXGBE_READ_REG(hw, addr);
4268         val = bit1 << pool;
4269
4270         if (on)
4271                 reg |= val;
4272         else
4273                 reg &= ~val;
4274
4275         IXGBE_WRITE_REG(hw, addr,reg);
4276
4277         return 0;
4278 }
4279
4280 static int
4281 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4282 {
4283         uint32_t reg,addr;
4284         uint32_t val;
4285         const uint8_t bit1 = 0x1;
4286
4287         struct ixgbe_hw *hw =
4288                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4289
4290         if (ixgbe_vmdq_mode_check(hw) < 0)
4291                 return -ENOTSUP;
4292
4293         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4294         reg = IXGBE_READ_REG(hw, addr);
4295         val = bit1 << pool;
4296
4297         if (on)
4298                 reg |= val;
4299         else
4300                 reg &= ~val;
4301
4302         IXGBE_WRITE_REG(hw, addr,reg);
4303
4304         return 0;
4305 }
4306
4307 static int
4308 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4309                         uint64_t pool_mask, uint8_t vlan_on)
4310 {
4311         int ret = 0;
4312         uint16_t pool_idx;
4313         struct ixgbe_hw *hw =
4314                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4315
4316         if (ixgbe_vmdq_mode_check(hw) < 0)
4317                 return -ENOTSUP;
4318         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4319                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4320                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4321                         if (ret < 0)
4322                                 return ret;
4323         }
4324
4325         return ret;
4326 }
4327
4328 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4329 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4330 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4331 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4332 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4333         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4334         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4335
4336 static int
4337 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4338                         struct rte_eth_mirror_conf *mirror_conf,
4339                         uint8_t rule_id, uint8_t on)
4340 {
4341         uint32_t mr_ctl,vlvf;
4342         uint32_t mp_lsb = 0;
4343         uint32_t mv_msb = 0;
4344         uint32_t mv_lsb = 0;
4345         uint32_t mp_msb = 0;
4346         uint8_t i = 0;
4347         int reg_index = 0;
4348         uint64_t vlan_mask = 0;
4349
4350         const uint8_t pool_mask_offset = 32;
4351         const uint8_t vlan_mask_offset = 32;
4352         const uint8_t dst_pool_offset = 8;
4353         const uint8_t rule_mr_offset  = 4;
4354         const uint8_t mirror_rule_mask= 0x0F;
4355
4356         struct ixgbe_mirror_info *mr_info =
4357                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4358         struct ixgbe_hw *hw =
4359                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4360         uint8_t mirror_type = 0;
4361
4362         if (ixgbe_vmdq_mode_check(hw) < 0)
4363                 return -ENOTSUP;
4364
4365         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4366                 return -EINVAL;
4367
4368         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4369                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4370                         mirror_conf->rule_type);
4371                 return -EINVAL;
4372         }
4373
4374         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4375                 mirror_type |= IXGBE_MRCTL_VLME;
4376                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4377                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4378                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4379                                 /* search vlan id related pool vlan filter index */
4380                                 reg_index = ixgbe_find_vlvf_slot(hw,
4381                                                 mirror_conf->vlan.vlan_id[i]);
4382                                 if (reg_index < 0)
4383                                         return -EINVAL;
4384                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4385                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4386                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4387                                       mirror_conf->vlan.vlan_id[i]))
4388                                         vlan_mask |= (1ULL << reg_index);
4389                                 else
4390                                         return -EINVAL;
4391                         }
4392                 }
4393
4394                 if (on) {
4395                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4396                         mv_msb = vlan_mask >> vlan_mask_offset;
4397
4398                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4399                                                 mirror_conf->vlan.vlan_mask;
4400                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4401                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4402                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4403                                                 mirror_conf->vlan.vlan_id[i];
4404                         }
4405                 } else {
4406                         mv_lsb = 0;
4407                         mv_msb = 0;
4408                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4409                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4410                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4411                 }
4412         }
4413
4414         /*
4415          * if enable pool mirror, write related pool mask register,if disable
4416          * pool mirror, clear PFMRVM register
4417          */
4418         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4419                 mirror_type |= IXGBE_MRCTL_VPME;
4420                 if (on) {
4421                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4422                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4423                         mr_info->mr_conf[rule_id].pool_mask =
4424                                         mirror_conf->pool_mask;
4425
4426                 } else {
4427                         mp_lsb = 0;
4428                         mp_msb = 0;
4429                         mr_info->mr_conf[rule_id].pool_mask = 0;
4430                 }
4431         }
4432         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4433                 mirror_type |= IXGBE_MRCTL_UPME;
4434         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4435                 mirror_type |= IXGBE_MRCTL_DPME;
4436
4437         /* read  mirror control register and recalculate it */
4438         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4439
4440         if (on) {
4441                 mr_ctl |= mirror_type;
4442                 mr_ctl &= mirror_rule_mask;
4443                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4444         } else
4445                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4446
4447         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4448         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4449
4450         /* write mirrror control  register */
4451         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4452
4453         /* write pool mirrror control  register */
4454         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4455                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4456                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4457                                 mp_msb);
4458         }
4459         /* write VLAN mirrror control  register */
4460         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4461                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4462                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4463                                 mv_msb);
4464         }
4465
4466         return 0;
4467 }
4468
4469 static int
4470 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4471 {
4472         int mr_ctl = 0;
4473         uint32_t lsb_val = 0;
4474         uint32_t msb_val = 0;
4475         const uint8_t rule_mr_offset = 4;
4476
4477         struct ixgbe_hw *hw =
4478                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4479         struct ixgbe_mirror_info *mr_info =
4480                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4481
4482         if (ixgbe_vmdq_mode_check(hw) < 0)
4483                 return -ENOTSUP;
4484
4485         memset(&mr_info->mr_conf[rule_id], 0,
4486                 sizeof(struct rte_eth_mirror_conf));
4487
4488         /* clear PFVMCTL register */
4489         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4490
4491         /* clear pool mask register */
4492         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4493         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4494
4495         /* clear vlan mask register */
4496         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4497         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4498
4499         return 0;
4500 }
4501
4502 static int
4503 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4504 {
4505         uint32_t mask;
4506         struct ixgbe_hw *hw =
4507                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4508
4509         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4510         mask |= (1 << IXGBE_MISC_VEC_ID);
4511         RTE_SET_USED(queue_id);
4512         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4513
4514         rte_intr_enable(&dev->pci_dev->intr_handle);
4515
4516         return 0;
4517 }
4518
4519 static int
4520 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4521 {
4522         uint32_t mask;
4523         struct ixgbe_hw *hw =
4524                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4525
4526         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4527         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4528         RTE_SET_USED(queue_id);
4529         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4530
4531         return 0;
4532 }
4533
4534 static int
4535 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4536 {
4537         uint32_t mask;
4538         struct ixgbe_hw *hw =
4539                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4540         struct ixgbe_interrupt *intr =
4541                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4542
4543         if (queue_id < 16) {
4544                 ixgbe_disable_intr(hw);
4545                 intr->mask |= (1 << queue_id);
4546                 ixgbe_enable_intr(dev);
4547         } else if (queue_id < 32) {
4548                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4549                 mask &= (1 << queue_id);
4550                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4551         } else if (queue_id < 64) {
4552                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4553                 mask &= (1 << (queue_id - 32));
4554                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4555         }
4556         rte_intr_enable(&dev->pci_dev->intr_handle);
4557
4558         return 0;
4559 }
4560
4561 static int
4562 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4563 {
4564         uint32_t mask;
4565         struct ixgbe_hw *hw =
4566                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4567         struct ixgbe_interrupt *intr =
4568                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4569
4570         if (queue_id < 16) {
4571                 ixgbe_disable_intr(hw);
4572                 intr->mask &= ~(1 << queue_id);
4573                 ixgbe_enable_intr(dev);
4574         } else if (queue_id < 32) {
4575                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4576                 mask &= ~(1 << queue_id);
4577                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4578         } else if (queue_id < 64) {
4579                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4580                 mask &= ~(1 << (queue_id - 32));
4581                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4582         }
4583
4584         return 0;
4585 }
4586
4587 static void
4588 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4589                      uint8_t queue, uint8_t msix_vector)
4590 {
4591         uint32_t tmp, idx;
4592
4593         if (direction == -1) {
4594                 /* other causes */
4595                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4596                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4597                 tmp &= ~0xFF;
4598                 tmp |= msix_vector;
4599                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4600         } else {
4601                 /* rx or tx cause */
4602                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4603                 idx = ((16 * (queue & 1)) + (8 * direction));
4604                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4605                 tmp &= ~(0xFF << idx);
4606                 tmp |= (msix_vector << idx);
4607                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4608         }
4609 }
4610
4611 /**
4612  * set the IVAR registers, mapping interrupt causes to vectors
4613  * @param hw
4614  *  pointer to ixgbe_hw struct
4615  * @direction
4616  *  0 for Rx, 1 for Tx, -1 for other causes
4617  * @queue
4618  *  queue to map the corresponding interrupt to
4619  * @msix_vector
4620  *  the vector to map to the corresponding queue
4621  */
4622 static void
4623 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4624                    uint8_t queue, uint8_t msix_vector)
4625 {
4626         uint32_t tmp, idx;
4627
4628         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4629         if (hw->mac.type == ixgbe_mac_82598EB) {
4630                 if (direction == -1)
4631                         direction = 0;
4632                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4633                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4634                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4635                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4636                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4637         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4638                         (hw->mac.type == ixgbe_mac_X540)) {
4639                 if (direction == -1) {
4640                         /* other causes */
4641                         idx = ((queue & 1) * 8);
4642                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4643                         tmp &= ~(0xFF << idx);
4644                         tmp |= (msix_vector << idx);
4645                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4646                 } else {
4647                         /* rx or tx causes */
4648                         idx = ((16 * (queue & 1)) + (8 * direction));
4649                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4650                         tmp &= ~(0xFF << idx);
4651                         tmp |= (msix_vector << idx);
4652                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4653                 }
4654         }
4655 }
4656
4657 static void
4658 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4659 {
4660         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4661         struct ixgbe_hw *hw =
4662                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663         uint32_t q_idx;
4664         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4665
4666         /* won't configure msix register if no mapping is done
4667          * between intr vector and event fd.
4668          */
4669         if (!rte_intr_dp_is_en(intr_handle))
4670                 return;
4671
4672         /* Configure all RX queues of VF */
4673         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4674                 /* Force all queue use vector 0,
4675                  * as IXGBE_VF_MAXMSIVECOTR = 1
4676                  */
4677                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4678                 intr_handle->intr_vec[q_idx] = vector_idx;
4679         }
4680
4681         /* Configure VF other cause ivar */
4682         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4683 }
4684
4685 /**
4686  * Sets up the hardware to properly generate MSI-X interrupts
4687  * @hw
4688  *  board private structure
4689  */
4690 static void
4691 ixgbe_configure_msix(struct rte_eth_dev *dev)
4692 {
4693         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4694         struct ixgbe_hw *hw =
4695                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4696         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4697         uint32_t vec = IXGBE_MISC_VEC_ID;
4698         uint32_t mask;
4699         uint32_t gpie;
4700
4701         /* won't configure msix register if no mapping is done
4702          * between intr vector and event fd
4703          */
4704         if (!rte_intr_dp_is_en(intr_handle))
4705                 return;
4706
4707         if (rte_intr_allow_others(intr_handle))
4708                 vec = base = IXGBE_RX_VEC_START;
4709
4710         /* setup GPIE for MSI-x mode */
4711         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4712         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4713                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4714         /* auto clearing and auto setting corresponding bits in EIMS
4715          * when MSI-X interrupt is triggered
4716          */
4717         if (hw->mac.type == ixgbe_mac_82598EB) {
4718                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4719         } else {
4720                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4721                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4722         }
4723         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4724
4725         /* Populate the IVAR table and set the ITR values to the
4726          * corresponding register.
4727          */
4728         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4729              queue_id++) {
4730                 /* by default, 1:1 mapping */
4731                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4732                 intr_handle->intr_vec[queue_id] = vec;
4733                 if (vec < base + intr_handle->nb_efd - 1)
4734                         vec++;
4735         }
4736
4737         switch (hw->mac.type) {
4738         case ixgbe_mac_82598EB:
4739                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4740                                    IXGBE_MISC_VEC_ID);
4741                 break;
4742         case ixgbe_mac_82599EB:
4743         case ixgbe_mac_X540:
4744                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4745                 break;
4746         default:
4747                 break;
4748         }
4749         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4750                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4751
4752         /* set up to autoclear timer, and the vectors */
4753         mask = IXGBE_EIMS_ENABLE_MASK;
4754         mask &= ~(IXGBE_EIMS_OTHER |
4755                   IXGBE_EIMS_MAILBOX |
4756                   IXGBE_EIMS_LSC);
4757
4758         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4759 }
4760
4761 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4762         uint16_t queue_idx, uint16_t tx_rate)
4763 {
4764         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4765         uint32_t rf_dec, rf_int;
4766         uint32_t bcnrc_val;
4767         uint16_t link_speed = dev->data->dev_link.link_speed;
4768
4769         if (queue_idx >= hw->mac.max_tx_queues)
4770                 return -EINVAL;
4771
4772         if (tx_rate != 0) {
4773                 /* Calculate the rate factor values to set */
4774                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4775                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4776                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4777
4778                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4779                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4780                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4781                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4782         } else {
4783                 bcnrc_val = 0;
4784         }
4785
4786         /*
4787          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4788          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4789          * set as 0x4.
4790          */
4791         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4792                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4793                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4794                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4795                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4796         else
4797                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4798                         IXGBE_MMW_SIZE_DEFAULT);
4799
4800         /* Set RTTBCNRC of queue X */
4801         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4802         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4803         IXGBE_WRITE_FLUSH(hw);
4804
4805         return 0;
4806 }
4807
4808 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4809         uint16_t tx_rate, uint64_t q_msk)
4810 {
4811         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4812         struct ixgbe_vf_info *vfinfo =
4813                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4814         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4815         uint32_t queue_stride =
4816                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4817         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4818         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4819         uint16_t total_rate = 0;
4820
4821         if (queue_end >= hw->mac.max_tx_queues)
4822                 return -EINVAL;
4823
4824         if (vfinfo != NULL) {
4825                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4826                         if (vf_idx == vf)
4827                                 continue;
4828                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4829                                 idx++)
4830                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4831                 }
4832         } else
4833                 return -EINVAL;
4834
4835         /* Store tx_rate for this vf. */
4836         for (idx = 0; idx < nb_q_per_pool; idx++) {
4837                 if (((uint64_t)0x1 << idx) & q_msk) {
4838                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4839                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4840                         total_rate += tx_rate;
4841                 }
4842         }
4843
4844         if (total_rate > dev->data->dev_link.link_speed) {
4845                 /*
4846                  * Reset stored TX rate of the VF if it causes exceed
4847                  * link speed.
4848                  */
4849                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4850                 return -EINVAL;
4851         }
4852
4853         /* Set RTTBCNRC of each queue/pool for vf X  */
4854         for (; queue_idx <= queue_end; queue_idx++) {
4855                 if (0x1 & q_msk)
4856                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4857                 q_msk = q_msk >> 1;
4858         }
4859
4860         return 0;
4861 }
4862
4863 static void
4864 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4865                      __attribute__((unused)) uint32_t index,
4866                      __attribute__((unused)) uint32_t pool)
4867 {
4868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4869         int diag;
4870
4871         /*
4872          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4873          * operation. Trap this case to avoid exhausting the [very limited]
4874          * set of PF resources used to store VF MAC addresses.
4875          */
4876         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4877                 return;
4878         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4879         if (diag == 0)
4880                 return;
4881         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4882 }
4883
4884 static void
4885 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4886 {
4887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4888         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4889         struct ether_addr *mac_addr;
4890         uint32_t i;
4891         int diag;
4892
4893         /*
4894          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4895          * not support the deletion of a given MAC address.
4896          * Instead, it imposes to delete all MAC addresses, then to add again
4897          * all MAC addresses with the exception of the one to be deleted.
4898          */
4899         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4900
4901         /*
4902          * Add again all MAC addresses, with the exception of the deleted one
4903          * and of the permanent MAC address.
4904          */
4905         for (i = 0, mac_addr = dev->data->mac_addrs;
4906              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4907                 /* Skip the deleted MAC address */
4908                 if (i == index)
4909                         continue;
4910                 /* Skip NULL MAC addresses */
4911                 if (is_zero_ether_addr(mac_addr))
4912                         continue;
4913                 /* Skip the permanent MAC address */
4914                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4915                         continue;
4916                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4917                 if (diag != 0)
4918                         PMD_DRV_LOG(ERR,
4919                                     "Adding again MAC address "
4920                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4921                                     "diag=%d",
4922                                     mac_addr->addr_bytes[0],
4923                                     mac_addr->addr_bytes[1],
4924                                     mac_addr->addr_bytes[2],
4925                                     mac_addr->addr_bytes[3],
4926                                     mac_addr->addr_bytes[4],
4927                                     mac_addr->addr_bytes[5],
4928                                     diag);
4929         }
4930 }
4931
4932 static void
4933 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4934 {
4935         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4936
4937         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4938 }
4939
4940 #define MAC_TYPE_FILTER_SUP(type)    do {\
4941         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4942                 (type) != ixgbe_mac_X550)\
4943                 return -ENOTSUP;\
4944 } while (0)
4945
4946 static int
4947 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4948                         struct rte_eth_syn_filter *filter,
4949                         bool add)
4950 {
4951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4952         uint32_t synqf;
4953
4954         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4955                 return -EINVAL;
4956
4957         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4958
4959         if (add) {
4960                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4961                         return -EINVAL;
4962                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4963                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4964
4965                 if (filter->hig_pri)
4966                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4967                 else
4968                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4969         } else {
4970                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4971                         return -ENOENT;
4972                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4973         }
4974         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4975         IXGBE_WRITE_FLUSH(hw);
4976         return 0;
4977 }
4978
4979 static int
4980 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4981                         struct rte_eth_syn_filter *filter)
4982 {
4983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4984         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4985
4986         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4987                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4988                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4989                 return 0;
4990         }
4991         return -ENOENT;
4992 }
4993
4994 static int
4995 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4996                         enum rte_filter_op filter_op,
4997                         void *arg)
4998 {
4999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5000         int ret;
5001
5002         MAC_TYPE_FILTER_SUP(hw->mac.type);
5003
5004         if (filter_op == RTE_ETH_FILTER_NOP)
5005                 return 0;
5006
5007         if (arg == NULL) {
5008                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5009                             filter_op);
5010                 return -EINVAL;
5011         }
5012
5013         switch (filter_op) {
5014         case RTE_ETH_FILTER_ADD:
5015                 ret = ixgbe_syn_filter_set(dev,
5016                                 (struct rte_eth_syn_filter *)arg,
5017                                 TRUE);
5018                 break;
5019         case RTE_ETH_FILTER_DELETE:
5020                 ret = ixgbe_syn_filter_set(dev,
5021                                 (struct rte_eth_syn_filter *)arg,
5022                                 FALSE);
5023                 break;
5024         case RTE_ETH_FILTER_GET:
5025                 ret = ixgbe_syn_filter_get(dev,
5026                                 (struct rte_eth_syn_filter *)arg);
5027                 break;
5028         default:
5029                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5030                 ret = -EINVAL;
5031                 break;
5032         }
5033
5034         return ret;
5035 }
5036
5037
5038 static inline enum ixgbe_5tuple_protocol
5039 convert_protocol_type(uint8_t protocol_value)
5040 {
5041         if (protocol_value == IPPROTO_TCP)
5042                 return IXGBE_FILTER_PROTOCOL_TCP;
5043         else if (protocol_value == IPPROTO_UDP)
5044                 return IXGBE_FILTER_PROTOCOL_UDP;
5045         else if (protocol_value == IPPROTO_SCTP)
5046                 return IXGBE_FILTER_PROTOCOL_SCTP;
5047         else
5048                 return IXGBE_FILTER_PROTOCOL_NONE;
5049 }
5050
5051 /*
5052  * add a 5tuple filter
5053  *
5054  * @param
5055  * dev: Pointer to struct rte_eth_dev.
5056  * index: the index the filter allocates.
5057  * filter: ponter to the filter that will be added.
5058  * rx_queue: the queue id the filter assigned to.
5059  *
5060  * @return
5061  *    - On success, zero.
5062  *    - On failure, a negative value.
5063  */
5064 static int
5065 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5066                         struct ixgbe_5tuple_filter *filter)
5067 {
5068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069         struct ixgbe_filter_info *filter_info =
5070                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5071         int i, idx, shift;
5072         uint32_t ftqf, sdpqf;
5073         uint32_t l34timir = 0;
5074         uint8_t mask = 0xff;
5075
5076         /*
5077          * look for an unused 5tuple filter index,
5078          * and insert the filter to list.
5079          */
5080         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5081                 idx = i / (sizeof(uint32_t) * NBBY);
5082                 shift = i % (sizeof(uint32_t) * NBBY);
5083                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5084                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5085                         filter->index = i;
5086                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5087                                           filter,
5088                                           entries);
5089                         break;
5090                 }
5091         }
5092         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5093                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5094                 return -ENOSYS;
5095         }
5096
5097         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5098                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5099         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5100
5101         ftqf = (uint32_t)(filter->filter_info.proto &
5102                 IXGBE_FTQF_PROTOCOL_MASK);
5103         ftqf |= (uint32_t)((filter->filter_info.priority &
5104                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5105         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5106                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5107         if (filter->filter_info.dst_ip_mask == 0)
5108                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5109         if (filter->filter_info.src_port_mask == 0)
5110                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5111         if (filter->filter_info.dst_port_mask == 0)
5112                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5113         if (filter->filter_info.proto_mask == 0)
5114                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5115         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5116         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5117         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5118
5119         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5120         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5121         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5122         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5123
5124         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5125         l34timir |= (uint32_t)(filter->queue <<
5126                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5127         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5128         return 0;
5129 }
5130
5131 /*
5132  * remove a 5tuple filter
5133  *
5134  * @param
5135  * dev: Pointer to struct rte_eth_dev.
5136  * filter: the pointer of the filter will be removed.
5137  */
5138 static void
5139 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5140                         struct ixgbe_5tuple_filter *filter)
5141 {
5142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5143         struct ixgbe_filter_info *filter_info =
5144                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5145         uint16_t index = filter->index;
5146
5147         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5148                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5149         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5150         rte_free(filter);
5151
5152         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5153         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5154         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5155         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5156         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5157 }
5158
5159 static int
5160 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5161 {
5162         struct ixgbe_hw *hw;
5163         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5164
5165         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5166
5167         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5168                 return -EINVAL;
5169
5170         /* refuse mtu that requires the support of scattered packets when this
5171          * feature has not been enabled before. */
5172         if (!dev->data->scattered_rx &&
5173             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5174              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5175                 return -EINVAL;
5176
5177         /*
5178          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5179          * request of the version 2.0 of the mailbox API.
5180          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5181          * of the mailbox API.
5182          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5183          * prior to 3.11.33 which contains the following change:
5184          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5185          */
5186         ixgbevf_rlpml_set_vf(hw, max_frame);
5187
5188         /* update max frame size */
5189         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5190         return 0;
5191 }
5192
5193 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5194         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5195                 return -ENOTSUP;\
5196 } while (0)
5197
5198 static inline struct ixgbe_5tuple_filter *
5199 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5200                         struct ixgbe_5tuple_filter_info *key)
5201 {
5202         struct ixgbe_5tuple_filter *it;
5203
5204         TAILQ_FOREACH(it, filter_list, entries) {
5205                 if (memcmp(key, &it->filter_info,
5206                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5207                         return it;
5208                 }
5209         }
5210         return NULL;
5211 }
5212
5213 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5214 static inline int
5215 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5216                         struct ixgbe_5tuple_filter_info *filter_info)
5217 {
5218         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5219                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5220                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5221                 return -EINVAL;
5222
5223         switch (filter->dst_ip_mask) {
5224         case UINT32_MAX:
5225                 filter_info->dst_ip_mask = 0;
5226                 filter_info->dst_ip = filter->dst_ip;
5227                 break;
5228         case 0:
5229                 filter_info->dst_ip_mask = 1;
5230                 break;
5231         default:
5232                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5233                 return -EINVAL;
5234         }
5235
5236         switch (filter->src_ip_mask) {
5237         case UINT32_MAX:
5238                 filter_info->src_ip_mask = 0;
5239                 filter_info->src_ip = filter->src_ip;
5240                 break;
5241         case 0:
5242                 filter_info->src_ip_mask = 1;
5243                 break;
5244         default:
5245                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5246                 return -EINVAL;
5247         }
5248
5249         switch (filter->dst_port_mask) {
5250         case UINT16_MAX:
5251                 filter_info->dst_port_mask = 0;
5252                 filter_info->dst_port = filter->dst_port;
5253                 break;
5254         case 0:
5255                 filter_info->dst_port_mask = 1;
5256                 break;
5257         default:
5258                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5259                 return -EINVAL;
5260         }
5261
5262         switch (filter->src_port_mask) {
5263         case UINT16_MAX:
5264                 filter_info->src_port_mask = 0;
5265                 filter_info->src_port = filter->src_port;
5266                 break;
5267         case 0:
5268                 filter_info->src_port_mask = 1;
5269                 break;
5270         default:
5271                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5272                 return -EINVAL;
5273         }
5274
5275         switch (filter->proto_mask) {
5276         case UINT8_MAX:
5277                 filter_info->proto_mask = 0;
5278                 filter_info->proto =
5279                         convert_protocol_type(filter->proto);
5280                 break;
5281         case 0:
5282                 filter_info->proto_mask = 1;
5283                 break;
5284         default:
5285                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5286                 return -EINVAL;
5287         }
5288
5289         filter_info->priority = (uint8_t)filter->priority;
5290         return 0;
5291 }
5292
5293 /*
5294  * add or delete a ntuple filter
5295  *
5296  * @param
5297  * dev: Pointer to struct rte_eth_dev.
5298  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5299  * add: if true, add filter, if false, remove filter
5300  *
5301  * @return
5302  *    - On success, zero.
5303  *    - On failure, a negative value.
5304  */
5305 static int
5306 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5307                         struct rte_eth_ntuple_filter *ntuple_filter,
5308                         bool add)
5309 {
5310         struct ixgbe_filter_info *filter_info =
5311                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5312         struct ixgbe_5tuple_filter_info filter_5tuple;
5313         struct ixgbe_5tuple_filter *filter;
5314         int ret;
5315
5316         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5317                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5318                 return -EINVAL;
5319         }
5320
5321         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5322         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5323         if (ret < 0)
5324                 return ret;
5325
5326         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5327                                          &filter_5tuple);
5328         if (filter != NULL && add) {
5329                 PMD_DRV_LOG(ERR, "filter exists.");
5330                 return -EEXIST;
5331         }
5332         if (filter == NULL && !add) {
5333                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5334                 return -ENOENT;
5335         }
5336
5337         if (add) {
5338                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5339                                 sizeof(struct ixgbe_5tuple_filter), 0);
5340                 if (filter == NULL)
5341                         return -ENOMEM;
5342                 (void)rte_memcpy(&filter->filter_info,
5343                                  &filter_5tuple,
5344                                  sizeof(struct ixgbe_5tuple_filter_info));
5345                 filter->queue = ntuple_filter->queue;
5346                 ret = ixgbe_add_5tuple_filter(dev, filter);
5347                 if (ret < 0) {
5348                         rte_free(filter);
5349                         return ret;
5350                 }
5351         } else
5352                 ixgbe_remove_5tuple_filter(dev, filter);
5353
5354         return 0;
5355 }
5356
5357 /*
5358  * get a ntuple filter
5359  *
5360  * @param
5361  * dev: Pointer to struct rte_eth_dev.
5362  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5363  *
5364  * @return
5365  *    - On success, zero.
5366  *    - On failure, a negative value.
5367  */
5368 static int
5369 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5370                         struct rte_eth_ntuple_filter *ntuple_filter)
5371 {
5372         struct ixgbe_filter_info *filter_info =
5373                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5374         struct ixgbe_5tuple_filter_info filter_5tuple;
5375         struct ixgbe_5tuple_filter *filter;
5376         int ret;
5377
5378         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5379                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5380                 return -EINVAL;
5381         }
5382
5383         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5384         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5385         if (ret < 0)
5386                 return ret;
5387
5388         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5389                                          &filter_5tuple);
5390         if (filter == NULL) {
5391                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5392                 return -ENOENT;
5393         }
5394         ntuple_filter->queue = filter->queue;
5395         return 0;
5396 }
5397
5398 /*
5399  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5400  * @dev: pointer to rte_eth_dev structure
5401  * @filter_op:operation will be taken.
5402  * @arg: a pointer to specific structure corresponding to the filter_op
5403  *
5404  * @return
5405  *    - On success, zero.
5406  *    - On failure, a negative value.
5407  */
5408 static int
5409 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5410                                 enum rte_filter_op filter_op,
5411                                 void *arg)
5412 {
5413         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5414         int ret;
5415
5416         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5417
5418         if (filter_op == RTE_ETH_FILTER_NOP)
5419                 return 0;
5420
5421         if (arg == NULL) {
5422                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5423                             filter_op);
5424                 return -EINVAL;
5425         }
5426
5427         switch (filter_op) {
5428         case RTE_ETH_FILTER_ADD:
5429                 ret = ixgbe_add_del_ntuple_filter(dev,
5430                         (struct rte_eth_ntuple_filter *)arg,
5431                         TRUE);
5432                 break;
5433         case RTE_ETH_FILTER_DELETE:
5434                 ret = ixgbe_add_del_ntuple_filter(dev,
5435                         (struct rte_eth_ntuple_filter *)arg,
5436                         FALSE);
5437                 break;
5438         case RTE_ETH_FILTER_GET:
5439                 ret = ixgbe_get_ntuple_filter(dev,
5440                         (struct rte_eth_ntuple_filter *)arg);
5441                 break;
5442         default:
5443                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5444                 ret = -EINVAL;
5445                 break;
5446         }
5447         return ret;
5448 }
5449
5450 static inline int
5451 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5452                         uint16_t ethertype)
5453 {
5454         int i;
5455
5456         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5457                 if (filter_info->ethertype_filters[i] == ethertype &&
5458                     (filter_info->ethertype_mask & (1 << i)))
5459                         return i;
5460         }
5461         return -1;
5462 }
5463
5464 static inline int
5465 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5466                         uint16_t ethertype)
5467 {
5468         int i;
5469
5470         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5471                 if (!(filter_info->ethertype_mask & (1 << i))) {
5472                         filter_info->ethertype_mask |= 1 << i;
5473                         filter_info->ethertype_filters[i] = ethertype;
5474                         return i;
5475                 }
5476         }
5477         return -1;
5478 }
5479
5480 static inline int
5481 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5482                         uint8_t idx)
5483 {
5484         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5485                 return -1;
5486         filter_info->ethertype_mask &= ~(1 << idx);
5487         filter_info->ethertype_filters[idx] = 0;
5488         return idx;
5489 }
5490
5491 static int
5492 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5493                         struct rte_eth_ethertype_filter *filter,
5494                         bool add)
5495 {
5496         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5497         struct ixgbe_filter_info *filter_info =
5498                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5499         uint32_t etqf = 0;
5500         uint32_t etqs = 0;
5501         int ret;
5502
5503         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5504                 return -EINVAL;
5505
5506         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5507                 filter->ether_type == ETHER_TYPE_IPv6) {
5508                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5509                         " ethertype filter.", filter->ether_type);
5510                 return -EINVAL;
5511         }
5512
5513         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5514                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5515                 return -EINVAL;
5516         }
5517         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5518                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5519                 return -EINVAL;
5520         }
5521
5522         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5523         if (ret >= 0 && add) {
5524                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5525                             filter->ether_type);
5526                 return -EEXIST;
5527         }
5528         if (ret < 0 && !add) {
5529                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5530                             filter->ether_type);
5531                 return -ENOENT;
5532         }
5533
5534         if (add) {
5535                 ret = ixgbe_ethertype_filter_insert(filter_info,
5536                         filter->ether_type);
5537                 if (ret < 0) {
5538                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5539                         return -ENOSYS;
5540                 }
5541                 etqf = IXGBE_ETQF_FILTER_EN;
5542                 etqf |= (uint32_t)filter->ether_type;
5543                 etqs |= (uint32_t)((filter->queue <<
5544                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5545                                     IXGBE_ETQS_RX_QUEUE);
5546                 etqs |= IXGBE_ETQS_QUEUE_EN;
5547         } else {
5548                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5549                 if (ret < 0)
5550                         return -ENOSYS;
5551         }
5552         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5553         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5554         IXGBE_WRITE_FLUSH(hw);
5555
5556         return 0;
5557 }
5558
5559 static int
5560 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5561                         struct rte_eth_ethertype_filter *filter)
5562 {
5563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5564         struct ixgbe_filter_info *filter_info =
5565                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5566         uint32_t etqf, etqs;
5567         int ret;
5568
5569         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5570         if (ret < 0) {
5571                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5572                             filter->ether_type);
5573                 return -ENOENT;
5574         }
5575
5576         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5577         if (etqf & IXGBE_ETQF_FILTER_EN) {
5578                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5579                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5580                 filter->flags = 0;
5581                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5582                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5583                 return 0;
5584         }
5585         return -ENOENT;
5586 }
5587
5588 /*
5589  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5590  * @dev: pointer to rte_eth_dev structure
5591  * @filter_op:operation will be taken.
5592  * @arg: a pointer to specific structure corresponding to the filter_op
5593  */
5594 static int
5595 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5596                                 enum rte_filter_op filter_op,
5597                                 void *arg)
5598 {
5599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5600         int ret;
5601
5602         MAC_TYPE_FILTER_SUP(hw->mac.type);
5603
5604         if (filter_op == RTE_ETH_FILTER_NOP)
5605                 return 0;
5606
5607         if (arg == NULL) {
5608                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5609                             filter_op);
5610                 return -EINVAL;
5611         }
5612
5613         switch (filter_op) {
5614         case RTE_ETH_FILTER_ADD:
5615                 ret = ixgbe_add_del_ethertype_filter(dev,
5616                         (struct rte_eth_ethertype_filter *)arg,
5617                         TRUE);
5618                 break;
5619         case RTE_ETH_FILTER_DELETE:
5620                 ret = ixgbe_add_del_ethertype_filter(dev,
5621                         (struct rte_eth_ethertype_filter *)arg,
5622                         FALSE);
5623                 break;
5624         case RTE_ETH_FILTER_GET:
5625                 ret = ixgbe_get_ethertype_filter(dev,
5626                         (struct rte_eth_ethertype_filter *)arg);
5627                 break;
5628         default:
5629                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5630                 ret = -EINVAL;
5631                 break;
5632         }
5633         return ret;
5634 }
5635
5636 static int
5637 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5638                      enum rte_filter_type filter_type,
5639                      enum rte_filter_op filter_op,
5640                      void *arg)
5641 {
5642         int ret = -EINVAL;
5643
5644         switch (filter_type) {
5645         case RTE_ETH_FILTER_NTUPLE:
5646                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5647                 break;
5648         case RTE_ETH_FILTER_ETHERTYPE:
5649                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5650                 break;
5651         case RTE_ETH_FILTER_SYN:
5652                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5653                 break;
5654         case RTE_ETH_FILTER_FDIR:
5655                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5656                 break;
5657         case RTE_ETH_FILTER_L2_TUNNEL:
5658                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5659                 break;
5660         default:
5661                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5662                                                         filter_type);
5663                 break;
5664         }
5665
5666         return ret;
5667 }
5668
5669 static u8 *
5670 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5671                         u8 **mc_addr_ptr, u32 *vmdq)
5672 {
5673         u8 *mc_addr;
5674
5675         *vmdq = 0;
5676         mc_addr = *mc_addr_ptr;
5677         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5678         return mc_addr;
5679 }
5680
5681 static int
5682 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5683                           struct ether_addr *mc_addr_set,
5684                           uint32_t nb_mc_addr)
5685 {
5686         struct ixgbe_hw *hw;
5687         u8 *mc_addr_list;
5688
5689         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5690         mc_addr_list = (u8 *)mc_addr_set;
5691         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5692                                          ixgbe_dev_addr_list_itr, TRUE);
5693 }
5694
5695 static uint64_t
5696 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5697 {
5698         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5699         uint64_t systime_cycles;
5700
5701         switch (hw->mac.type) {
5702         case ixgbe_mac_X550:
5703                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5704                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5705                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5706                                 * NSEC_PER_SEC;
5707                 break;
5708         default:
5709                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5710                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5711                                 << 32;
5712         }
5713
5714         return systime_cycles;
5715 }
5716
5717 static uint64_t
5718 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5719 {
5720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5721         uint64_t rx_tstamp_cycles;
5722
5723         switch (hw->mac.type) {
5724         case ixgbe_mac_X550:
5725                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5726                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5727                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5728                                 * NSEC_PER_SEC;
5729                 break;
5730         default:
5731                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5732                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5733                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5734                                 << 32;
5735         }
5736
5737         return rx_tstamp_cycles;
5738 }
5739
5740 static uint64_t
5741 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5742 {
5743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5744         uint64_t tx_tstamp_cycles;
5745
5746         switch (hw->mac.type) {
5747         case ixgbe_mac_X550:
5748                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5749                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5750                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5751                                 * NSEC_PER_SEC;
5752                 break;
5753         default:
5754                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5755                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5756                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5757                                 << 32;
5758         }
5759
5760         return tx_tstamp_cycles;
5761 }
5762
5763 static void
5764 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5765 {
5766         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5767         struct ixgbe_adapter *adapter =
5768                 (struct ixgbe_adapter *)dev->data->dev_private;
5769         struct rte_eth_link link;
5770         uint32_t incval = 0;
5771         uint32_t shift = 0;
5772
5773         /* Get current link speed. */
5774         memset(&link, 0, sizeof(link));
5775         ixgbe_dev_link_update(dev, 1);
5776         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5777
5778         switch (link.link_speed) {
5779         case ETH_LINK_SPEED_100:
5780                 incval = IXGBE_INCVAL_100;
5781                 shift = IXGBE_INCVAL_SHIFT_100;
5782                 break;
5783         case ETH_LINK_SPEED_1000:
5784                 incval = IXGBE_INCVAL_1GB;
5785                 shift = IXGBE_INCVAL_SHIFT_1GB;
5786                 break;
5787         case ETH_LINK_SPEED_10000:
5788         default:
5789                 incval = IXGBE_INCVAL_10GB;
5790                 shift = IXGBE_INCVAL_SHIFT_10GB;
5791                 break;
5792         }
5793
5794         switch (hw->mac.type) {
5795         case ixgbe_mac_X550:
5796                 /* Independent of link speed. */
5797                 incval = 1;
5798                 /* Cycles read will be interpreted as ns. */
5799                 shift = 0;
5800                 /* Fall-through */
5801         case ixgbe_mac_X540:
5802                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5803                 break;
5804         case ixgbe_mac_82599EB:
5805                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5806                 shift -= IXGBE_INCVAL_SHIFT_82599;
5807                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5808                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5809                 break;
5810         default:
5811                 /* Not supported. */
5812                 return;
5813         }
5814
5815         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5816         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5817         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5818
5819         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5820         adapter->systime_tc.cc_shift = shift;
5821         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5822
5823         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5824         adapter->rx_tstamp_tc.cc_shift = shift;
5825         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5826
5827         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5828         adapter->tx_tstamp_tc.cc_shift = shift;
5829         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5830 }
5831
5832 static int
5833 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5834 {
5835         struct ixgbe_adapter *adapter =
5836                         (struct ixgbe_adapter *)dev->data->dev_private;
5837
5838         adapter->systime_tc.nsec += delta;
5839         adapter->rx_tstamp_tc.nsec += delta;
5840         adapter->tx_tstamp_tc.nsec += delta;
5841
5842         return 0;
5843 }
5844
5845 static int
5846 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5847 {
5848         uint64_t ns;
5849         struct ixgbe_adapter *adapter =
5850                         (struct ixgbe_adapter *)dev->data->dev_private;
5851
5852         ns = rte_timespec_to_ns(ts);
5853         /* Set the timecounters to a new value. */
5854         adapter->systime_tc.nsec = ns;
5855         adapter->rx_tstamp_tc.nsec = ns;
5856         adapter->tx_tstamp_tc.nsec = ns;
5857
5858         return 0;
5859 }
5860
5861 static int
5862 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5863 {
5864         uint64_t ns, systime_cycles;
5865         struct ixgbe_adapter *adapter =
5866                         (struct ixgbe_adapter *)dev->data->dev_private;
5867
5868         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5869         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5870         *ts = rte_ns_to_timespec(ns);
5871
5872         return 0;
5873 }
5874
5875 static int
5876 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5877 {
5878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5879         uint32_t tsync_ctl;
5880         uint32_t tsauxc;
5881
5882         /* Stop the timesync system time. */
5883         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5884         /* Reset the timesync system time value. */
5885         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5886         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5887
5888         /* Enable system time for platforms where it isn't on by default. */
5889         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5890         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5891         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5892
5893         ixgbe_start_timecounters(dev);
5894
5895         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5896         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5897                         (ETHER_TYPE_1588 |
5898                          IXGBE_ETQF_FILTER_EN |
5899                          IXGBE_ETQF_1588));
5900
5901         /* Enable timestamping of received PTP packets. */
5902         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5903         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5904         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5905
5906         /* Enable timestamping of transmitted PTP packets. */
5907         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5908         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5909         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5910
5911         IXGBE_WRITE_FLUSH(hw);
5912
5913         return 0;
5914 }
5915
5916 static int
5917 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5918 {
5919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5920         uint32_t tsync_ctl;
5921
5922         /* Disable timestamping of transmitted PTP packets. */
5923         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5924         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5925         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5926
5927         /* Disable timestamping of received PTP packets. */
5928         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5929         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5930         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5931
5932         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5933         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5934
5935         /* Stop incrementating the System Time registers. */
5936         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5937
5938         return 0;
5939 }
5940
5941 static int
5942 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5943                                  struct timespec *timestamp,
5944                                  uint32_t flags __rte_unused)
5945 {
5946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5947         struct ixgbe_adapter *adapter =
5948                 (struct ixgbe_adapter *)dev->data->dev_private;
5949         uint32_t tsync_rxctl;
5950         uint64_t rx_tstamp_cycles;
5951         uint64_t ns;
5952
5953         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5954         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5955                 return -EINVAL;
5956
5957         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
5958         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5959         *timestamp = rte_ns_to_timespec(ns);
5960
5961         return  0;
5962 }
5963
5964 static int
5965 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5966                                  struct timespec *timestamp)
5967 {
5968         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5969         struct ixgbe_adapter *adapter =
5970                 (struct ixgbe_adapter *)dev->data->dev_private;
5971         uint32_t tsync_txctl;
5972         uint64_t tx_tstamp_cycles;
5973         uint64_t ns;
5974
5975         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5976         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5977                 return -EINVAL;
5978
5979         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
5980         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5981         *timestamp = rte_ns_to_timespec(ns);
5982
5983         return 0;
5984 }
5985
5986 static int
5987 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5988 {
5989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5990         int count = 0;
5991         int g_ind = 0;
5992         const struct reg_info *reg_group;
5993         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5994                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5995
5996         while ((reg_group = reg_set[g_ind++]))
5997                 count += ixgbe_regs_group_count(reg_group);
5998
5999         return count;
6000 }
6001
6002 static int
6003 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6004 {
6005         int count = 0;
6006         int g_ind = 0;
6007         const struct reg_info *reg_group;
6008
6009         while ((reg_group = ixgbevf_regs[g_ind++]))
6010                 count += ixgbe_regs_group_count(reg_group);
6011
6012         return count;
6013 }
6014
6015 static int
6016 ixgbe_get_regs(struct rte_eth_dev *dev,
6017               struct rte_dev_reg_info *regs)
6018 {
6019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6020         uint32_t *data = regs->data;
6021         int g_ind = 0;
6022         int count = 0;
6023         const struct reg_info *reg_group;
6024         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6025                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6026
6027         /* Support only full register dump */
6028         if ((regs->length == 0) ||
6029             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6030                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6031                         hw->device_id;
6032                 while ((reg_group = reg_set[g_ind++]))
6033                         count += ixgbe_read_regs_group(dev, &data[count],
6034                                 reg_group);
6035                 return 0;
6036         }
6037
6038         return -ENOTSUP;
6039 }
6040
6041 static int
6042 ixgbevf_get_regs(struct rte_eth_dev *dev,
6043                 struct rte_dev_reg_info *regs)
6044 {
6045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6046         uint32_t *data = regs->data;
6047         int g_ind = 0;
6048         int count = 0;
6049         const struct reg_info *reg_group;
6050
6051         /* Support only full register dump */
6052         if ((regs->length == 0) ||
6053             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6054                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6055                         hw->device_id;
6056                 while ((reg_group = ixgbevf_regs[g_ind++]))
6057                         count += ixgbe_read_regs_group(dev, &data[count],
6058                                                       reg_group);
6059                 return 0;
6060         }
6061
6062         return -ENOTSUP;
6063 }
6064
6065 static int
6066 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6067 {
6068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6069
6070         /* Return unit is byte count */
6071         return hw->eeprom.word_size * 2;
6072 }
6073
6074 static int
6075 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6076                 struct rte_dev_eeprom_info *in_eeprom)
6077 {
6078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6079         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6080         uint16_t *data = in_eeprom->data;
6081         int first, length;
6082
6083         first = in_eeprom->offset >> 1;
6084         length = in_eeprom->length >> 1;
6085         if ((first > hw->eeprom.word_size) ||
6086             ((first + length) > hw->eeprom.word_size))
6087                 return -EINVAL;
6088
6089         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6090
6091         return eeprom->ops.read_buffer(hw, first, length, data);
6092 }
6093
6094 static int
6095 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6096                 struct rte_dev_eeprom_info *in_eeprom)
6097 {
6098         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6099         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6100         uint16_t *data = in_eeprom->data;
6101         int first, length;
6102
6103         first = in_eeprom->offset >> 1;
6104         length = in_eeprom->length >> 1;
6105         if ((first > hw->eeprom.word_size) ||
6106             ((first + length) > hw->eeprom.word_size))
6107                 return -EINVAL;
6108
6109         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6110
6111         return eeprom->ops.write_buffer(hw,  first, length, data);
6112 }
6113
6114 uint16_t
6115 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6116         switch (mac_type) {
6117         case ixgbe_mac_X550:
6118         case ixgbe_mac_X550EM_x:
6119                 return ETH_RSS_RETA_SIZE_512;
6120         case ixgbe_mac_X550_vf:
6121         case ixgbe_mac_X550EM_x_vf:
6122                 return ETH_RSS_RETA_SIZE_64;
6123         default:
6124                 return ETH_RSS_RETA_SIZE_128;
6125         }
6126 }
6127
6128 uint32_t
6129 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6130         switch (mac_type) {
6131         case ixgbe_mac_X550:
6132         case ixgbe_mac_X550EM_x:
6133                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6134                         return IXGBE_RETA(reta_idx >> 2);
6135                 else
6136                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6137         case ixgbe_mac_X550_vf:
6138         case ixgbe_mac_X550EM_x_vf:
6139                 return IXGBE_VFRETA(reta_idx >> 2);
6140         default:
6141                 return IXGBE_RETA(reta_idx >> 2);
6142         }
6143 }
6144
6145 uint32_t
6146 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6147         switch (mac_type) {
6148         case ixgbe_mac_X550_vf:
6149         case ixgbe_mac_X550EM_x_vf:
6150                 return IXGBE_VFMRQC;
6151         default:
6152                 return IXGBE_MRQC;
6153         }
6154 }
6155
6156 uint32_t
6157 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6158         switch (mac_type) {
6159         case ixgbe_mac_X550_vf:
6160         case ixgbe_mac_X550EM_x_vf:
6161                 return IXGBE_VFRSSRK(i);
6162         default:
6163                 return IXGBE_RSSRK(i);
6164         }
6165 }
6166
6167 bool
6168 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6169         switch (mac_type) {
6170         case ixgbe_mac_82599_vf:
6171         case ixgbe_mac_X540_vf:
6172                 return 0;
6173         default:
6174                 return 1;
6175         }
6176 }
6177
6178 static int
6179 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6180                         struct rte_eth_dcb_info *dcb_info)
6181 {
6182         struct ixgbe_dcb_config *dcb_config =
6183                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6184         struct ixgbe_dcb_tc_config *tc;
6185         uint8_t i, j;
6186
6187         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6188                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6189         else
6190                 dcb_info->nb_tcs = 1;
6191
6192         if (dcb_config->vt_mode) { /* vt is enabled*/
6193                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6194                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6195                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6196                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6197                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6198                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6199                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6200                                                 i * dcb_info->nb_tcs + j;
6201                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6202                                 dcb_info->tc_queue.tc_txq[i][j].base =
6203                                                 i * dcb_info->nb_tcs + j;
6204                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6205                         }
6206                 }
6207         } else { /* vt is disabled*/
6208                 struct rte_eth_dcb_rx_conf *rx_conf =
6209                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6210                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6211                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6212                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6213                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6214                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6215                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6216                         }
6217                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6218                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6219                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6220                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6221                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6222                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6223                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6224                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6225                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6226                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6227                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6228                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6229                         }
6230                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6231                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6232                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6233                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6234                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6235                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6236                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6237                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6238                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6239                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6240                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6241                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6242                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6243                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6244                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6245                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6246                 }
6247         }
6248         for (i = 0; i < dcb_info->nb_tcs; i++) {
6249                 tc = &dcb_config->tc_config[i];
6250                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6251         }
6252         return 0;
6253 }
6254
6255 /* Update e-tag ether type */
6256 static int
6257 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6258                             uint16_t ether_type)
6259 {
6260         uint32_t etag_etype;
6261
6262         if (hw->mac.type != ixgbe_mac_X550 &&
6263             hw->mac.type != ixgbe_mac_X550EM_x) {
6264                 return -ENOTSUP;
6265         }
6266
6267         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6268         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6269         etag_etype |= ether_type;
6270         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6271         IXGBE_WRITE_FLUSH(hw);
6272
6273         return 0;
6274 }
6275
6276 /* Config l2 tunnel ether type */
6277 static int
6278 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6279                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6280 {
6281         int ret = 0;
6282         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6283
6284         if (l2_tunnel == NULL)
6285                 return -EINVAL;
6286
6287         switch (l2_tunnel->l2_tunnel_type) {
6288         case RTE_L2_TUNNEL_TYPE_E_TAG:
6289                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6290                 break;
6291         default:
6292                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6293                 ret = -EINVAL;
6294                 break;
6295         }
6296
6297         return ret;
6298 }
6299
6300 /* Enable e-tag tunnel */
6301 static int
6302 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6303 {
6304         uint32_t etag_etype;
6305
6306         if (hw->mac.type != ixgbe_mac_X550 &&
6307             hw->mac.type != ixgbe_mac_X550EM_x) {
6308                 return -ENOTSUP;
6309         }
6310
6311         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6312         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6313         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6314         IXGBE_WRITE_FLUSH(hw);
6315
6316         return 0;
6317 }
6318
6319 /* Enable l2 tunnel */
6320 static int
6321 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6322                            enum rte_eth_tunnel_type l2_tunnel_type)
6323 {
6324         int ret = 0;
6325         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6326
6327         switch (l2_tunnel_type) {
6328         case RTE_L2_TUNNEL_TYPE_E_TAG:
6329                 ret = ixgbe_e_tag_enable(hw);
6330                 break;
6331         default:
6332                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6333                 ret = -EINVAL;
6334                 break;
6335         }
6336
6337         return ret;
6338 }
6339
6340 /* Disable e-tag tunnel */
6341 static int
6342 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6343 {
6344         uint32_t etag_etype;
6345
6346         if (hw->mac.type != ixgbe_mac_X550 &&
6347             hw->mac.type != ixgbe_mac_X550EM_x) {
6348                 return -ENOTSUP;
6349         }
6350
6351         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6352         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6353         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6354         IXGBE_WRITE_FLUSH(hw);
6355
6356         return 0;
6357 }
6358
6359 /* Disable l2 tunnel */
6360 static int
6361 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6362                             enum rte_eth_tunnel_type l2_tunnel_type)
6363 {
6364         int ret = 0;
6365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6366
6367         switch (l2_tunnel_type) {
6368         case RTE_L2_TUNNEL_TYPE_E_TAG:
6369                 ret = ixgbe_e_tag_disable(hw);
6370                 break;
6371         default:
6372                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6373                 ret = -EINVAL;
6374                 break;
6375         }
6376
6377         return ret;
6378 }
6379
6380 static int
6381 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6382                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6383 {
6384         int ret = 0;
6385         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6386         uint32_t i, rar_entries;
6387         uint32_t rar_low, rar_high;
6388
6389         if (hw->mac.type != ixgbe_mac_X550 &&
6390             hw->mac.type != ixgbe_mac_X550EM_x) {
6391                 return -ENOTSUP;
6392         }
6393
6394         rar_entries = ixgbe_get_num_rx_addrs(hw);
6395
6396         for (i = 1; i < rar_entries; i++) {
6397                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6398                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6399                 if ((rar_high & IXGBE_RAH_AV) &&
6400                     (rar_high & IXGBE_RAH_ADTYPE) &&
6401                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6402                      l2_tunnel->tunnel_id)) {
6403                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6404                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6405
6406                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6407
6408                         return ret;
6409                 }
6410         }
6411
6412         return ret;
6413 }
6414
6415 static int
6416 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6417                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6418 {
6419         int ret = 0;
6420         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6421         uint32_t i, rar_entries;
6422         uint32_t rar_low, rar_high;
6423
6424         if (hw->mac.type != ixgbe_mac_X550 &&
6425             hw->mac.type != ixgbe_mac_X550EM_x) {
6426                 return -ENOTSUP;
6427         }
6428
6429         /* One entry for one tunnel. Try to remove potential existing entry. */
6430         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6431
6432         rar_entries = ixgbe_get_num_rx_addrs(hw);
6433
6434         for (i = 1; i < rar_entries; i++) {
6435                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6436                 if (rar_high & IXGBE_RAH_AV) {
6437                         continue;
6438                 } else {
6439                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6440                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6441                         rar_low = l2_tunnel->tunnel_id;
6442
6443                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6444                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6445
6446                         return ret;
6447                 }
6448         }
6449
6450         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6451                      " Please remove a rule before adding a new one.");
6452         return -EINVAL;
6453 }
6454
6455 /* Add l2 tunnel filter */
6456 static int
6457 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6458                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6459 {
6460         int ret = 0;
6461
6462         switch (l2_tunnel->l2_tunnel_type) {
6463         case RTE_L2_TUNNEL_TYPE_E_TAG:
6464                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6465                 break;
6466         default:
6467                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6468                 ret = -EINVAL;
6469                 break;
6470         }
6471
6472         return ret;
6473 }
6474
6475 /* Delete l2 tunnel filter */
6476 static int
6477 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6478                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6479 {
6480         int ret = 0;
6481
6482         switch (l2_tunnel->l2_tunnel_type) {
6483         case RTE_L2_TUNNEL_TYPE_E_TAG:
6484                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6485                 break;
6486         default:
6487                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6488                 ret = -EINVAL;
6489                 break;
6490         }
6491
6492         return ret;
6493 }
6494
6495 /**
6496  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6497  * @dev: pointer to rte_eth_dev structure
6498  * @filter_op:operation will be taken.
6499  * @arg: a pointer to specific structure corresponding to the filter_op
6500  */
6501 static int
6502 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6503                                   enum rte_filter_op filter_op,
6504                                   void *arg)
6505 {
6506         int ret = 0;
6507
6508         if (filter_op == RTE_ETH_FILTER_NOP)
6509                 return 0;
6510
6511         if (arg == NULL) {
6512                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6513                             filter_op);
6514                 return -EINVAL;
6515         }
6516
6517         switch (filter_op) {
6518         case RTE_ETH_FILTER_ADD:
6519                 ret = ixgbe_dev_l2_tunnel_filter_add
6520                         (dev,
6521                          (struct rte_eth_l2_tunnel_conf *)arg);
6522                 break;
6523         case RTE_ETH_FILTER_DELETE:
6524                 ret = ixgbe_dev_l2_tunnel_filter_del
6525                         (dev,
6526                          (struct rte_eth_l2_tunnel_conf *)arg);
6527                 break;
6528         default:
6529                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6530                 ret = -EINVAL;
6531                 break;
6532         }
6533         return ret;
6534 }
6535
6536 static int
6537 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6538 {
6539         int ret = 0;
6540         uint32_t ctrl;
6541         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6542
6543         if (hw->mac.type != ixgbe_mac_X550 &&
6544             hw->mac.type != ixgbe_mac_X550EM_x) {
6545                 return -ENOTSUP;
6546         }
6547
6548         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6549         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6550         if (en)
6551                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6552         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6553
6554         return ret;
6555 }
6556
6557 /* Enable l2 tunnel forwarding */
6558 static int
6559 ixgbe_dev_l2_tunnel_forwarding_enable
6560         (struct rte_eth_dev *dev,
6561          enum rte_eth_tunnel_type l2_tunnel_type)
6562 {
6563         int ret = 0;
6564
6565         switch (l2_tunnel_type) {
6566         case RTE_L2_TUNNEL_TYPE_E_TAG:
6567                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6568                 break;
6569         default:
6570                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6571                 ret = -EINVAL;
6572                 break;
6573         }
6574
6575         return ret;
6576 }
6577
6578 /* Disable l2 tunnel forwarding */
6579 static int
6580 ixgbe_dev_l2_tunnel_forwarding_disable
6581         (struct rte_eth_dev *dev,
6582          enum rte_eth_tunnel_type l2_tunnel_type)
6583 {
6584         int ret = 0;
6585
6586         switch (l2_tunnel_type) {
6587         case RTE_L2_TUNNEL_TYPE_E_TAG:
6588                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6589                 break;
6590         default:
6591                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6592                 ret = -EINVAL;
6593                 break;
6594         }
6595
6596         return ret;
6597 }
6598
6599 static int
6600 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6601                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6602                              bool en)
6603 {
6604         int ret = 0;
6605         uint32_t vmtir, vmvir;
6606         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6607
6608         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6609                 PMD_DRV_LOG(ERR,
6610                             "VF id %u should be less than %u",
6611                             l2_tunnel->vf_id,
6612                             dev->pci_dev->max_vfs);
6613                 return -EINVAL;
6614         }
6615
6616         if (hw->mac.type != ixgbe_mac_X550 &&
6617             hw->mac.type != ixgbe_mac_X550EM_x) {
6618                 return -ENOTSUP;
6619         }
6620
6621         if (en)
6622                 vmtir = l2_tunnel->tunnel_id;
6623         else
6624                 vmtir = 0;
6625
6626         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6627
6628         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6629         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6630         if (en)
6631                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6632         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6633
6634         return ret;
6635 }
6636
6637 /* Enable l2 tunnel tag insertion */
6638 static int
6639 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6640                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6641 {
6642         int ret = 0;
6643
6644         switch (l2_tunnel->l2_tunnel_type) {
6645         case RTE_L2_TUNNEL_TYPE_E_TAG:
6646                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6647                 break;
6648         default:
6649                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6650                 ret = -EINVAL;
6651                 break;
6652         }
6653
6654         return ret;
6655 }
6656
6657 /* Disable l2 tunnel tag insertion */
6658 static int
6659 ixgbe_dev_l2_tunnel_insertion_disable
6660         (struct rte_eth_dev *dev,
6661          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6662 {
6663         int ret = 0;
6664
6665         switch (l2_tunnel->l2_tunnel_type) {
6666         case RTE_L2_TUNNEL_TYPE_E_TAG:
6667                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6668                 break;
6669         default:
6670                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6671                 ret = -EINVAL;
6672                 break;
6673         }
6674
6675         return ret;
6676 }
6677
6678 static int
6679 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6680                              bool en)
6681 {
6682         int ret = 0;
6683         uint32_t qde;
6684         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6685
6686         if (hw->mac.type != ixgbe_mac_X550 &&
6687             hw->mac.type != ixgbe_mac_X550EM_x) {
6688                 return -ENOTSUP;
6689         }
6690
6691         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6692         if (en)
6693                 qde |= IXGBE_QDE_STRIP_TAG;
6694         else
6695                 qde &= ~IXGBE_QDE_STRIP_TAG;
6696         qde &= ~IXGBE_QDE_READ;
6697         qde |= IXGBE_QDE_WRITE;
6698         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6699
6700         return ret;
6701 }
6702
6703 /* Enable l2 tunnel tag stripping */
6704 static int
6705 ixgbe_dev_l2_tunnel_stripping_enable
6706         (struct rte_eth_dev *dev,
6707          enum rte_eth_tunnel_type l2_tunnel_type)
6708 {
6709         int ret = 0;
6710
6711         switch (l2_tunnel_type) {
6712         case RTE_L2_TUNNEL_TYPE_E_TAG:
6713                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6714                 break;
6715         default:
6716                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6717                 ret = -EINVAL;
6718                 break;
6719         }
6720
6721         return ret;
6722 }
6723
6724 /* Disable l2 tunnel tag stripping */
6725 static int
6726 ixgbe_dev_l2_tunnel_stripping_disable
6727         (struct rte_eth_dev *dev,
6728          enum rte_eth_tunnel_type l2_tunnel_type)
6729 {
6730         int ret = 0;
6731
6732         switch (l2_tunnel_type) {
6733         case RTE_L2_TUNNEL_TYPE_E_TAG:
6734                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6735                 break;
6736         default:
6737                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6738                 ret = -EINVAL;
6739                 break;
6740         }
6741
6742         return ret;
6743 }
6744
6745 /* Enable/disable l2 tunnel offload functions */
6746 static int
6747 ixgbe_dev_l2_tunnel_offload_set
6748         (struct rte_eth_dev *dev,
6749          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6750          uint32_t mask,
6751          uint8_t en)
6752 {
6753         int ret = 0;
6754
6755         if (l2_tunnel == NULL)
6756                 return -EINVAL;
6757
6758         ret = -EINVAL;
6759         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6760                 if (en)
6761                         ret = ixgbe_dev_l2_tunnel_enable(
6762                                 dev,
6763                                 l2_tunnel->l2_tunnel_type);
6764                 else
6765                         ret = ixgbe_dev_l2_tunnel_disable(
6766                                 dev,
6767                                 l2_tunnel->l2_tunnel_type);
6768         }
6769
6770         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6771                 if (en)
6772                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6773                                 dev,
6774                                 l2_tunnel);
6775                 else
6776                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6777                                 dev,
6778                                 l2_tunnel);
6779         }
6780
6781         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6782                 if (en)
6783                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6784                                 dev,
6785                                 l2_tunnel->l2_tunnel_type);
6786                 else
6787                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6788                                 dev,
6789                                 l2_tunnel->l2_tunnel_type);
6790         }
6791
6792         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6793                 if (en)
6794                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6795                                 dev,
6796                                 l2_tunnel->l2_tunnel_type);
6797                 else
6798                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6799                                 dev,
6800                                 l2_tunnel->l2_tunnel_type);
6801         }
6802
6803         return ret;
6804 }
6805
6806 static int
6807 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6808                         uint16_t port)
6809 {
6810         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6811         IXGBE_WRITE_FLUSH(hw);
6812
6813         return 0;
6814 }
6815
6816 /* There's only one register for VxLAN UDP port.
6817  * So, we cannot add several ports. Will update it.
6818  */
6819 static int
6820 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6821                      uint16_t port)
6822 {
6823         if (port == 0) {
6824                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6825                 return -EINVAL;
6826         }
6827
6828         return ixgbe_update_vxlan_port(hw, port);
6829 }
6830
6831 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6832  * UDP port, it must have a value.
6833  * So, will reset it to the original value 0.
6834  */
6835 static int
6836 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6837                      uint16_t port)
6838 {
6839         uint16_t cur_port;
6840
6841         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6842
6843         if (cur_port != port) {
6844                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6845                 return -EINVAL;
6846         }
6847
6848         return ixgbe_update_vxlan_port(hw, 0);
6849 }
6850
6851 /* Add UDP tunneling port */
6852 static int
6853 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6854                               struct rte_eth_udp_tunnel *udp_tunnel)
6855 {
6856         int ret = 0;
6857         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6858
6859         if (hw->mac.type != ixgbe_mac_X550 &&
6860             hw->mac.type != ixgbe_mac_X550EM_x) {
6861                 return -ENOTSUP;
6862         }
6863
6864         if (udp_tunnel == NULL)
6865                 return -EINVAL;
6866
6867         switch (udp_tunnel->prot_type) {
6868         case RTE_TUNNEL_TYPE_VXLAN:
6869                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6870                 break;
6871
6872         case RTE_TUNNEL_TYPE_GENEVE:
6873         case RTE_TUNNEL_TYPE_TEREDO:
6874                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6875                 ret = -EINVAL;
6876                 break;
6877
6878         default:
6879                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6880                 ret = -EINVAL;
6881                 break;
6882         }
6883
6884         return ret;
6885 }
6886
6887 /* Remove UDP tunneling port */
6888 static int
6889 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6890                               struct rte_eth_udp_tunnel *udp_tunnel)
6891 {
6892         int ret = 0;
6893         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6894
6895         if (hw->mac.type != ixgbe_mac_X550 &&
6896             hw->mac.type != ixgbe_mac_X550EM_x) {
6897                 return -ENOTSUP;
6898         }
6899
6900         if (udp_tunnel == NULL)
6901                 return -EINVAL;
6902
6903         switch (udp_tunnel->prot_type) {
6904         case RTE_TUNNEL_TYPE_VXLAN:
6905                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
6906                 break;
6907         case RTE_TUNNEL_TYPE_GENEVE:
6908         case RTE_TUNNEL_TYPE_TEREDO:
6909                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6910                 ret = -EINVAL;
6911                 break;
6912         default:
6913                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6914                 ret = -EINVAL;
6915                 break;
6916         }
6917
6918         return ret;
6919 }
6920
6921 static struct rte_driver rte_ixgbe_driver = {
6922         .type = PMD_PDEV,
6923         .init = rte_ixgbe_pmd_init,
6924 };
6925
6926 static struct rte_driver rte_ixgbevf_driver = {
6927         .type = PMD_PDEV,
6928         .init = rte_ixgbevf_pmd_init,
6929 };
6930
6931 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6932 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);