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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
73 * High threshold controlling when to start sending XOFF frames. Must be at
74 * least 8 bytes less than receive packet buffer size. This value is in units
77 #define IXGBE_FC_HI 0x80
80 * Low threshold controlling when to start sending XON frames. This value is
81 * in units of 1024 bytes.
83 #define IXGBE_FC_LO 0x40
85 /* Timer value included in XOFF frames. */
86 #define IXGBE_FC_PAUSE 0x680
88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
89 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
90 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
92 #define IXGBE_MMW_SIZE_DEFAULT 0x4
93 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
96 * Default values for RX/TX configuration
98 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
99 #define IXGBE_DEFAULT_RX_PTHRESH 8
100 #define IXGBE_DEFAULT_RX_HTHRESH 8
101 #define IXGBE_DEFAULT_RX_WTHRESH 0
103 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
104 #define IXGBE_DEFAULT_TX_PTHRESH 32
105 #define IXGBE_DEFAULT_TX_HTHRESH 0
106 #define IXGBE_DEFAULT_TX_WTHRESH 0
107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
109 /* Bit shift and mask */
110 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
111 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
112 #define IXGBE_8_BIT_WIDTH CHAR_BIT
113 #define IXGBE_8_BIT_MASK UINT8_MAX
115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
119 #define IXGBE_HKEY_MAX_INDEX 10
121 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
122 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
123 static int ixgbe_dev_start(struct rte_eth_dev *dev);
124 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
125 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
126 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
127 static void ixgbe_dev_close(struct rte_eth_dev *dev);
128 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
129 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
130 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
131 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
132 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
133 int wait_to_complete);
134 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
135 struct rte_eth_stats *stats);
136 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
137 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
141 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
142 struct rte_eth_dev_info *dev_info);
143 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
144 struct rte_eth_dev_info *dev_info);
145 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
147 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
148 uint16_t vlan_id, int on);
149 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
150 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
151 uint16_t queue, bool on);
152 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
154 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
155 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
156 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
157 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
158 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
160 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
161 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
162 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
163 struct rte_eth_fc_conf *fc_conf);
164 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
165 struct rte_eth_fc_conf *fc_conf);
166 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
167 struct rte_eth_pfc_conf *pfc_conf);
168 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
169 struct rte_eth_rss_reta_entry64 *reta_conf,
171 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
172 struct rte_eth_rss_reta_entry64 *reta_conf,
174 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
175 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
176 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
177 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
178 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
180 static void ixgbe_dev_interrupt_delayed_handler(void *param);
181 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
182 uint32_t index, uint32_t pool);
183 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
184 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
186 /* For Virtual Function support */
187 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
188 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
189 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
190 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
191 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
192 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
193 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
194 struct rte_eth_stats *stats);
195 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
196 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
197 uint16_t vlan_id, int on);
198 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
199 uint16_t queue, int on);
200 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
201 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
203 /* For Eth VMDQ APIs support */
204 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
205 ether_addr* mac_addr,uint8_t on);
206 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
207 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
208 uint16_t rx_mask, uint8_t on);
209 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
210 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
211 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
212 uint64_t pool_mask,uint8_t vlan_on);
213 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
214 struct rte_eth_mirror_conf *mirror_conf,
215 uint8_t rule_id, uint8_t on);
216 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
219 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
220 uint16_t queue_idx, uint16_t tx_rate);
221 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
222 uint16_t tx_rate, uint64_t q_msk);
224 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
225 struct ether_addr *mac_addr,
226 uint32_t index, uint32_t pool);
227 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
228 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
229 struct rte_eth_syn_filter *filter,
231 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
232 struct rte_eth_syn_filter *filter);
233 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
234 enum rte_filter_op filter_op,
236 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
237 struct ixgbe_5tuple_filter *filter);
238 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
239 struct ixgbe_5tuple_filter *filter);
240 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
241 struct rte_eth_ntuple_filter *filter,
243 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
244 enum rte_filter_op filter_op,
246 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
247 struct rte_eth_ntuple_filter *filter);
248 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
249 struct rte_eth_ethertype_filter *filter,
251 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
252 enum rte_filter_op filter_op,
254 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
255 struct rte_eth_ethertype_filter *filter);
256 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
257 enum rte_filter_type filter_type,
258 enum rte_filter_op filter_op,
260 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
262 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
263 struct ether_addr *mc_addr_set,
264 uint32_t nb_mc_addr);
267 * Define VF Stats MACRO for Non "cleared on read" register
269 #define UPDATE_VF_STAT(reg, last, cur) \
271 u32 latest = IXGBE_READ_REG(hw, reg); \
272 cur += latest - last; \
276 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
278 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
279 u64 new_msb = IXGBE_READ_REG(hw, msb); \
280 u64 latest = ((new_msb << 32) | new_lsb); \
281 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
285 #define IXGBE_SET_HWSTRIP(h, q) do{\
286 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
287 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
288 (h)->bitmap[idx] |= 1 << bit;\
291 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
292 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
293 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
294 (h)->bitmap[idx] &= ~(1 << bit);\
297 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
298 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
299 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
300 (r) = (h)->bitmap[idx] >> bit & 1;\
304 * The set of PCI devices this driver supports
306 static const struct rte_pci_id pci_id_ixgbe_map[] = {
308 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
309 #include "rte_pci_dev_ids.h"
311 { .vendor_id = 0, /* sentinel */ },
316 * The set of PCI devices this driver supports (for 82599 VF)
318 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
320 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
321 #include "rte_pci_dev_ids.h"
322 { .vendor_id = 0, /* sentinel */ },
326 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
327 .dev_configure = ixgbe_dev_configure,
328 .dev_start = ixgbe_dev_start,
329 .dev_stop = ixgbe_dev_stop,
330 .dev_set_link_up = ixgbe_dev_set_link_up,
331 .dev_set_link_down = ixgbe_dev_set_link_down,
332 .dev_close = ixgbe_dev_close,
333 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
334 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
335 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
336 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
337 .link_update = ixgbe_dev_link_update,
338 .stats_get = ixgbe_dev_stats_get,
339 .stats_reset = ixgbe_dev_stats_reset,
340 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
341 .dev_infos_get = ixgbe_dev_info_get,
342 .mtu_set = ixgbe_dev_mtu_set,
343 .vlan_filter_set = ixgbe_vlan_filter_set,
344 .vlan_tpid_set = ixgbe_vlan_tpid_set,
345 .vlan_offload_set = ixgbe_vlan_offload_set,
346 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
347 .rx_queue_start = ixgbe_dev_rx_queue_start,
348 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
349 .tx_queue_start = ixgbe_dev_tx_queue_start,
350 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
351 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
352 .rx_queue_release = ixgbe_dev_rx_queue_release,
353 .rx_queue_count = ixgbe_dev_rx_queue_count,
354 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
355 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
356 .tx_queue_release = ixgbe_dev_tx_queue_release,
357 .dev_led_on = ixgbe_dev_led_on,
358 .dev_led_off = ixgbe_dev_led_off,
359 .flow_ctrl_get = ixgbe_flow_ctrl_get,
360 .flow_ctrl_set = ixgbe_flow_ctrl_set,
361 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
362 .mac_addr_add = ixgbe_add_rar,
363 .mac_addr_remove = ixgbe_remove_rar,
364 .uc_hash_table_set = ixgbe_uc_hash_table_set,
365 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
366 .mirror_rule_set = ixgbe_mirror_rule_set,
367 .mirror_rule_reset = ixgbe_mirror_rule_reset,
368 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
369 .set_vf_rx = ixgbe_set_pool_rx,
370 .set_vf_tx = ixgbe_set_pool_tx,
371 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
372 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
373 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
374 .reta_update = ixgbe_dev_rss_reta_update,
375 .reta_query = ixgbe_dev_rss_reta_query,
376 #ifdef RTE_NIC_BYPASS
377 .bypass_init = ixgbe_bypass_init,
378 .bypass_state_set = ixgbe_bypass_state_store,
379 .bypass_state_show = ixgbe_bypass_state_show,
380 .bypass_event_set = ixgbe_bypass_event_store,
381 .bypass_event_show = ixgbe_bypass_event_show,
382 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
383 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
384 .bypass_ver_show = ixgbe_bypass_ver_show,
385 .bypass_wd_reset = ixgbe_bypass_wd_reset,
386 #endif /* RTE_NIC_BYPASS */
387 .rss_hash_update = ixgbe_dev_rss_hash_update,
388 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
389 .filter_ctrl = ixgbe_dev_filter_ctrl,
390 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
394 * dev_ops for virtual function, bare necessities for basic vf
395 * operation have been implemented
397 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
398 .dev_configure = ixgbevf_dev_configure,
399 .dev_start = ixgbevf_dev_start,
400 .dev_stop = ixgbevf_dev_stop,
401 .link_update = ixgbe_dev_link_update,
402 .stats_get = ixgbevf_dev_stats_get,
403 .stats_reset = ixgbevf_dev_stats_reset,
404 .dev_close = ixgbevf_dev_close,
405 .dev_infos_get = ixgbevf_dev_info_get,
406 .mtu_set = ixgbevf_dev_set_mtu,
407 .vlan_filter_set = ixgbevf_vlan_filter_set,
408 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
409 .vlan_offload_set = ixgbevf_vlan_offload_set,
410 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
411 .rx_queue_release = ixgbe_dev_rx_queue_release,
412 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
413 .tx_queue_release = ixgbe_dev_tx_queue_release,
414 .mac_addr_add = ixgbevf_add_mac_addr,
415 .mac_addr_remove = ixgbevf_remove_mac_addr,
416 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
420 * Atomically reads the link status information from global
421 * structure rte_eth_dev.
424 * - Pointer to the structure rte_eth_dev to read from.
425 * - Pointer to the buffer to be saved with the link status.
428 * - On success, zero.
429 * - On failure, negative value.
432 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
433 struct rte_eth_link *link)
435 struct rte_eth_link *dst = link;
436 struct rte_eth_link *src = &(dev->data->dev_link);
438 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
439 *(uint64_t *)src) == 0)
446 * Atomically writes the link status information into global
447 * structure rte_eth_dev.
450 * - Pointer to the structure rte_eth_dev to read from.
451 * - Pointer to the buffer to be saved with the link status.
454 * - On success, zero.
455 * - On failure, negative value.
458 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
459 struct rte_eth_link *link)
461 struct rte_eth_link *dst = &(dev->data->dev_link);
462 struct rte_eth_link *src = link;
464 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
465 *(uint64_t *)src) == 0)
472 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
475 ixgbe_is_sfp(struct ixgbe_hw *hw)
477 switch (hw->phy.type) {
478 case ixgbe_phy_sfp_avago:
479 case ixgbe_phy_sfp_ftl:
480 case ixgbe_phy_sfp_intel:
481 case ixgbe_phy_sfp_unknown:
482 case ixgbe_phy_sfp_passive_tyco:
483 case ixgbe_phy_sfp_passive_unknown:
490 static inline int32_t
491 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
496 status = ixgbe_reset_hw(hw);
498 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
499 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
500 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
501 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
502 IXGBE_WRITE_FLUSH(hw);
508 ixgbe_enable_intr(struct rte_eth_dev *dev)
510 struct ixgbe_interrupt *intr =
511 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
512 struct ixgbe_hw *hw =
513 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
515 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
516 IXGBE_WRITE_FLUSH(hw);
520 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
523 ixgbe_disable_intr(struct ixgbe_hw *hw)
525 PMD_INIT_FUNC_TRACE();
527 if (hw->mac.type == ixgbe_mac_82598EB) {
528 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
530 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
531 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
532 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
534 IXGBE_WRITE_FLUSH(hw);
538 * This function resets queue statistics mapping registers.
539 * From Niantic datasheet, Initialization of Statistics section:
540 * "...if software requires the queue counters, the RQSMR and TQSM registers
541 * must be re-programmed following a device reset.
544 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
548 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
549 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
550 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
556 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
561 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
562 #define NB_QMAP_FIELDS_PER_QSM_REG 4
563 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
565 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
566 struct ixgbe_stat_mapping_registers *stat_mappings =
567 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
568 uint32_t qsmr_mask = 0;
569 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
573 if ((hw->mac.type != ixgbe_mac_82599EB) &&
574 (hw->mac.type != ixgbe_mac_X540) &&
575 (hw->mac.type != ixgbe_mac_X550) &&
576 (hw->mac.type != ixgbe_mac_X550EM_x))
579 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
580 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
583 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
584 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
585 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
588 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
590 /* Now clear any previous stat_idx set */
591 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
593 stat_mappings->tqsm[n] &= ~clearing_mask;
595 stat_mappings->rqsmr[n] &= ~clearing_mask;
597 q_map = (uint32_t)stat_idx;
598 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
599 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
601 stat_mappings->tqsm[n] |= qsmr_mask;
603 stat_mappings->rqsmr[n] |= qsmr_mask;
605 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
606 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
608 PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
609 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
611 /* Now write the mapping in the appropriate register */
613 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
614 stat_mappings->rqsmr[n], n);
615 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
618 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
619 stat_mappings->tqsm[n], n);
620 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
626 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
628 struct ixgbe_stat_mapping_registers *stat_mappings =
629 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
630 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
633 /* write whatever was in stat mapping table to the NIC */
634 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
636 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
639 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
644 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
647 struct ixgbe_dcb_tc_config *tc;
648 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
650 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
651 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
652 for (i = 0; i < dcb_max_tc; i++) {
653 tc = &dcb_config->tc_config[i];
654 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
655 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
656 (uint8_t)(100/dcb_max_tc + (i & 1));
657 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
658 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
659 (uint8_t)(100/dcb_max_tc + (i & 1));
660 tc->pfc = ixgbe_dcb_pfc_disabled;
663 /* Initialize default user to priority mapping, UPx->TC0 */
664 tc = &dcb_config->tc_config[0];
665 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
666 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
667 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
668 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
669 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
671 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
672 dcb_config->pfc_mode_enable = false;
673 dcb_config->vt_mode = true;
674 dcb_config->round_robin_enable = false;
675 /* support all DCB capabilities in 82599 */
676 dcb_config->support.capabilities = 0xFF;
678 /*we only support 4 Tcs for X540, X550 */
679 if (hw->mac.type == ixgbe_mac_X540 ||
680 hw->mac.type == ixgbe_mac_X550 ||
681 hw->mac.type == ixgbe_mac_X550EM_x) {
682 dcb_config->num_tcs.pg_tcs = 4;
683 dcb_config->num_tcs.pfc_tcs = 4;
688 * Ensure that all locks are released before first NVM or PHY access
691 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
696 * Phy lock should not fail in this early stage. If this is the case,
697 * it is due to an improper exit of the application.
698 * So force the release of the faulty lock. Release of common lock
699 * is done automatically by swfw_sync function.
701 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
702 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
703 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
705 ixgbe_release_swfw_semaphore(hw, mask);
708 * These ones are more tricky since they are common to all ports; but
709 * swfw_sync retries last long enough (1s) to be almost sure that if
710 * lock can not be taken it is due to an improper lock of the
713 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
714 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
715 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
717 ixgbe_release_swfw_semaphore(hw, mask);
721 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
722 * It returns 0 on success.
725 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
727 struct rte_pci_device *pci_dev;
728 struct ixgbe_hw *hw =
729 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
730 struct ixgbe_vfta * shadow_vfta =
731 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
732 struct ixgbe_hwstrip *hwstrip =
733 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
734 struct ixgbe_dcb_config *dcb_config =
735 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
736 struct ixgbe_filter_info *filter_info =
737 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
742 PMD_INIT_FUNC_TRACE();
744 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
745 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
746 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
749 * For secondary processes, we don't initialise any further as primary
750 * has already done this work. Only check we don't need a different
751 * RX and TX function.
753 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
754 struct ixgbe_tx_queue *txq;
755 /* TX queue function in primary, set by last queue initialized
756 * Tx queue may not initialized by primary process */
757 if (eth_dev->data->tx_queues) {
758 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
759 ixgbe_set_tx_function(eth_dev, txq);
761 /* Use default TX function if we get here */
762 PMD_INIT_LOG(INFO, "No TX queues configured yet. "
763 "Using default TX function.");
766 ixgbe_set_rx_function(eth_dev);
770 pci_dev = eth_dev->pci_dev;
772 /* Vendor and Device ID need to be set before init of shared code */
773 hw->device_id = pci_dev->id.device_id;
774 hw->vendor_id = pci_dev->id.vendor_id;
775 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
776 hw->allow_unsupported_sfp = 1;
778 /* Initialize the shared code (base driver) */
779 #ifdef RTE_NIC_BYPASS
780 diag = ixgbe_bypass_init_shared_code(hw);
782 diag = ixgbe_init_shared_code(hw);
783 #endif /* RTE_NIC_BYPASS */
785 if (diag != IXGBE_SUCCESS) {
786 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
790 /* pick up the PCI bus settings for reporting later */
791 ixgbe_get_bus_info(hw);
793 /* Unlock any pending hardware semaphore */
794 ixgbe_swfw_lock_reset(hw);
796 /* Initialize DCB configuration*/
797 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
798 ixgbe_dcb_init(hw,dcb_config);
799 /* Get Hardware Flow Control setting */
800 hw->fc.requested_mode = ixgbe_fc_full;
801 hw->fc.current_mode = ixgbe_fc_full;
802 hw->fc.pause_time = IXGBE_FC_PAUSE;
803 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
804 hw->fc.low_water[i] = IXGBE_FC_LO;
805 hw->fc.high_water[i] = IXGBE_FC_HI;
809 /* Make sure we have a good EEPROM before we read from it */
810 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
811 if (diag != IXGBE_SUCCESS) {
812 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
816 #ifdef RTE_NIC_BYPASS
817 diag = ixgbe_bypass_init_hw(hw);
819 diag = ixgbe_init_hw(hw);
820 #endif /* RTE_NIC_BYPASS */
823 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
824 * is called too soon after the kernel driver unbinding/binding occurs.
825 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
826 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
827 * also called. See ixgbe_identify_phy_82599(). The reason for the
828 * failure is not known, and only occuts when virtualisation features
829 * are disabled in the bios. A delay of 100ms was found to be enough by
830 * trial-and-error, and is doubled to be safe.
832 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
834 diag = ixgbe_init_hw(hw);
837 if (diag == IXGBE_ERR_EEPROM_VERSION) {
838 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
839 "LOM. Please be aware there may be issues associated "
840 "with your hardware.");
841 PMD_INIT_LOG(ERR, "If you are experiencing problems "
842 "please contact your Intel or hardware representative "
843 "who provided you with this hardware.");
844 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
845 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
847 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
851 /* disable interrupt */
852 ixgbe_disable_intr(hw);
854 /* reset mappings for queue statistics hw counters*/
855 ixgbe_reset_qstat_mappings(hw);
857 /* Allocate memory for storing MAC addresses */
858 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
859 hw->mac.num_rar_entries, 0);
860 if (eth_dev->data->mac_addrs == NULL) {
862 "Failed to allocate %u bytes needed to store "
864 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
867 /* Copy the permanent MAC address */
868 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
869 ð_dev->data->mac_addrs[0]);
871 /* Allocate memory for storing hash filter MAC addresses */
872 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
873 IXGBE_VMDQ_NUM_UC_MAC, 0);
874 if (eth_dev->data->hash_mac_addrs == NULL) {
876 "Failed to allocate %d bytes needed to store MAC addresses",
877 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
881 /* initialize the vfta */
882 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
884 /* initialize the hw strip bitmap*/
885 memset(hwstrip, 0, sizeof(*hwstrip));
887 /* initialize PF if max_vfs not zero */
888 ixgbe_pf_host_init(eth_dev);
890 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
891 /* let hardware know driver is loaded */
892 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
893 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
894 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
895 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
896 IXGBE_WRITE_FLUSH(hw);
898 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
899 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
900 (int) hw->mac.type, (int) hw->phy.type,
901 (int) hw->phy.sfp_type);
903 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
904 (int) hw->mac.type, (int) hw->phy.type);
906 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
907 eth_dev->data->port_id, pci_dev->id.vendor_id,
908 pci_dev->id.device_id);
910 rte_intr_callback_register(&(pci_dev->intr_handle),
911 ixgbe_dev_interrupt_handler, (void *)eth_dev);
913 /* enable uio intr after callback register */
914 rte_intr_enable(&(pci_dev->intr_handle));
916 /* enable support intr */
917 ixgbe_enable_intr(eth_dev);
919 /* initialize 5tuple filter list */
920 TAILQ_INIT(&filter_info->fivetuple_list);
921 memset(filter_info->fivetuple_mask, 0,
922 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
929 * Negotiate mailbox API version with the PF.
930 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
931 * Then we try to negotiate starting with the most recent one.
932 * If all negotiation attempts fail, then we will proceed with
933 * the default one (ixgbe_mbox_api_10).
936 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
940 /* start with highest supported, proceed down */
941 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
947 i != RTE_DIM(sup_ver) &&
948 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
954 generate_random_mac_addr(struct ether_addr *mac_addr)
958 /* Set Organizationally Unique Identifier (OUI) prefix. */
959 mac_addr->addr_bytes[0] = 0x00;
960 mac_addr->addr_bytes[1] = 0x09;
961 mac_addr->addr_bytes[2] = 0xC0;
962 /* Force indication of locally assigned MAC address. */
963 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
964 /* Generate the last 3 bytes of the MAC address with a random number. */
966 memcpy(&mac_addr->addr_bytes[3], &random, 3);
970 * Virtual Function device init
973 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
977 struct rte_pci_device *pci_dev;
978 struct ixgbe_hw *hw =
979 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
980 struct ixgbe_vfta * shadow_vfta =
981 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
982 struct ixgbe_hwstrip *hwstrip =
983 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
984 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
986 PMD_INIT_FUNC_TRACE();
988 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
989 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
990 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
992 /* for secondary processes, we don't initialise any further as primary
993 * has already done this work. Only check we don't need a different
995 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
996 if (eth_dev->data->scattered_rx)
997 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1001 pci_dev = eth_dev->pci_dev;
1003 hw->device_id = pci_dev->id.device_id;
1004 hw->vendor_id = pci_dev->id.vendor_id;
1005 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1007 /* initialize the vfta */
1008 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1010 /* initialize the hw strip bitmap*/
1011 memset(hwstrip, 0, sizeof(*hwstrip));
1013 /* Initialize the shared code (base driver) */
1014 diag = ixgbe_init_shared_code(hw);
1015 if (diag != IXGBE_SUCCESS) {
1016 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1020 /* init_mailbox_params */
1021 hw->mbx.ops.init_params(hw);
1023 /* Disable the interrupts for VF */
1024 ixgbevf_intr_disable(hw);
1026 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1027 diag = hw->mac.ops.reset_hw(hw);
1030 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1031 * the underlying PF driver has not assigned a MAC address to the VF.
1032 * In this case, assign a random MAC address.
1034 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1035 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1039 /* negotiate mailbox API version to use with the PF. */
1040 ixgbevf_negotiate_api(hw);
1042 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1043 ixgbevf_get_queues(hw, &tcs, &tc);
1045 /* Allocate memory for storing MAC addresses */
1046 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1047 hw->mac.num_rar_entries, 0);
1048 if (eth_dev->data->mac_addrs == NULL) {
1050 "Failed to allocate %u bytes needed to store "
1052 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1056 /* Generate a random MAC address, if none was assigned by PF. */
1057 if (is_zero_ether_addr(perm_addr)) {
1058 generate_random_mac_addr(perm_addr);
1059 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1061 rte_free(eth_dev->data->mac_addrs);
1062 eth_dev->data->mac_addrs = NULL;
1065 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1066 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1067 "%02x:%02x:%02x:%02x:%02x:%02x",
1068 perm_addr->addr_bytes[0],
1069 perm_addr->addr_bytes[1],
1070 perm_addr->addr_bytes[2],
1071 perm_addr->addr_bytes[3],
1072 perm_addr->addr_bytes[4],
1073 perm_addr->addr_bytes[5]);
1076 /* Copy the permanent MAC address */
1077 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1079 /* reset the hardware with the new settings */
1080 diag = hw->mac.ops.start_hw(hw);
1086 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1090 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1091 eth_dev->data->port_id, pci_dev->id.vendor_id,
1092 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1097 static struct eth_driver rte_ixgbe_pmd = {
1099 .name = "rte_ixgbe_pmd",
1100 .id_table = pci_id_ixgbe_map,
1101 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1103 .eth_dev_init = eth_ixgbe_dev_init,
1104 .dev_private_size = sizeof(struct ixgbe_adapter),
1108 * virtual function driver struct
1110 static struct eth_driver rte_ixgbevf_pmd = {
1112 .name = "rte_ixgbevf_pmd",
1113 .id_table = pci_id_ixgbevf_map,
1114 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1116 .eth_dev_init = eth_ixgbevf_dev_init,
1117 .dev_private_size = sizeof(struct ixgbe_adapter),
1121 * Driver initialization routine.
1122 * Invoked once at EAL init time.
1123 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1126 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1128 PMD_INIT_FUNC_TRACE();
1130 rte_eth_driver_register(&rte_ixgbe_pmd);
1135 * VF Driver initialization routine.
1136 * Invoked one at EAL init time.
1137 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1140 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1142 PMD_INIT_FUNC_TRACE();
1144 rte_eth_driver_register(&rte_ixgbevf_pmd);
1149 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1151 struct ixgbe_hw *hw =
1152 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1153 struct ixgbe_vfta * shadow_vfta =
1154 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1159 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1160 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1161 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1166 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1168 /* update local VFTA copy */
1169 shadow_vfta->vfta[vid_idx] = vfta;
1175 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1178 ixgbe_vlan_hw_strip_enable(dev, queue);
1180 ixgbe_vlan_hw_strip_disable(dev, queue);
1184 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1186 struct ixgbe_hw *hw =
1187 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1189 /* Only the high 16-bits is valid */
1190 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1194 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1196 struct ixgbe_hw *hw =
1197 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1200 PMD_INIT_FUNC_TRACE();
1202 /* Filter Table Disable */
1203 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1204 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1206 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1210 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1212 struct ixgbe_hw *hw =
1213 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1214 struct ixgbe_vfta * shadow_vfta =
1215 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1219 PMD_INIT_FUNC_TRACE();
1221 /* Filter Table Enable */
1222 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1223 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1224 vlnctrl |= IXGBE_VLNCTRL_VFE;
1226 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1228 /* write whatever is in local vfta copy */
1229 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1230 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1234 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1236 struct ixgbe_hwstrip *hwstrip =
1237 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1239 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1243 IXGBE_SET_HWSTRIP(hwstrip, queue);
1245 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1249 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1251 struct ixgbe_hw *hw =
1252 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1255 PMD_INIT_FUNC_TRACE();
1257 if (hw->mac.type == ixgbe_mac_82598EB) {
1258 /* No queue level support */
1259 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1263 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1264 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1265 ctrl &= ~IXGBE_RXDCTL_VME;
1266 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1268 /* record those setting for HW strip per queue */
1269 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1273 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1275 struct ixgbe_hw *hw =
1276 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1279 PMD_INIT_FUNC_TRACE();
1281 if (hw->mac.type == ixgbe_mac_82598EB) {
1282 /* No queue level supported */
1283 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1287 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1288 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1289 ctrl |= IXGBE_RXDCTL_VME;
1290 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1292 /* record those setting for HW strip per queue */
1293 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1297 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1299 struct ixgbe_hw *hw =
1300 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1304 PMD_INIT_FUNC_TRACE();
1306 if (hw->mac.type == ixgbe_mac_82598EB) {
1307 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1308 ctrl &= ~IXGBE_VLNCTRL_VME;
1309 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1312 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1313 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1314 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1315 ctrl &= ~IXGBE_RXDCTL_VME;
1316 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1318 /* record those setting for HW strip per queue */
1319 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1325 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1327 struct ixgbe_hw *hw =
1328 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1332 PMD_INIT_FUNC_TRACE();
1334 if (hw->mac.type == ixgbe_mac_82598EB) {
1335 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1336 ctrl |= IXGBE_VLNCTRL_VME;
1337 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1340 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1341 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1342 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1343 ctrl |= IXGBE_RXDCTL_VME;
1344 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1346 /* record those setting for HW strip per queue */
1347 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1353 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1355 struct ixgbe_hw *hw =
1356 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359 PMD_INIT_FUNC_TRACE();
1361 /* DMATXCTRL: Geric Double VLAN Disable */
1362 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1363 ctrl &= ~IXGBE_DMATXCTL_GDV;
1364 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1366 /* CTRL_EXT: Global Double VLAN Disable */
1367 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1368 ctrl &= ~IXGBE_EXTENDED_VLAN;
1369 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1374 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1376 struct ixgbe_hw *hw =
1377 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380 PMD_INIT_FUNC_TRACE();
1382 /* DMATXCTRL: Geric Double VLAN Enable */
1383 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1384 ctrl |= IXGBE_DMATXCTL_GDV;
1385 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1387 /* CTRL_EXT: Global Double VLAN Enable */
1388 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1389 ctrl |= IXGBE_EXTENDED_VLAN;
1390 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1393 * VET EXT field in the EXVET register = 0x8100 by default
1394 * So no need to change. Same to VT field of DMATXCTL register
1399 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1401 if(mask & ETH_VLAN_STRIP_MASK){
1402 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1403 ixgbe_vlan_hw_strip_enable_all(dev);
1405 ixgbe_vlan_hw_strip_disable_all(dev);
1408 if(mask & ETH_VLAN_FILTER_MASK){
1409 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1410 ixgbe_vlan_hw_filter_enable(dev);
1412 ixgbe_vlan_hw_filter_disable(dev);
1415 if(mask & ETH_VLAN_EXTEND_MASK){
1416 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1417 ixgbe_vlan_hw_extend_enable(dev);
1419 ixgbe_vlan_hw_extend_disable(dev);
1424 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1426 struct ixgbe_hw *hw =
1427 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1429 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1430 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1431 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1435 ixgbe_dev_configure(struct rte_eth_dev *dev)
1437 struct ixgbe_interrupt *intr =
1438 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1439 struct ixgbe_adapter *adapter =
1440 (struct ixgbe_adapter *)dev->data->dev_private;
1442 PMD_INIT_FUNC_TRACE();
1444 /* set flag to update link status after init */
1445 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1448 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1449 * allocation or vector Rx preconditions we will reset it.
1451 adapter->rx_bulk_alloc_allowed = true;
1452 adapter->rx_vec_allowed = true;
1458 * Configure device link speed and setup link.
1459 * It returns 0 on success.
1462 ixgbe_dev_start(struct rte_eth_dev *dev)
1464 struct ixgbe_hw *hw =
1465 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1466 struct ixgbe_vf_info *vfinfo =
1467 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1468 int err, link_up = 0, negotiate = 0;
1474 PMD_INIT_FUNC_TRACE();
1476 /* IXGBE devices don't support half duplex */
1477 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1478 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1479 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1480 dev->data->dev_conf.link_duplex,
1481 dev->data->port_id);
1486 hw->adapter_stopped = FALSE;
1487 ixgbe_stop_adapter(hw);
1489 /* reinitialize adapter
1490 * this calls reset and start */
1491 status = ixgbe_pf_reset_hw(hw);
1494 hw->mac.ops.start_hw(hw);
1495 hw->mac.get_link_status = true;
1497 /* configure PF module if SRIOV enabled */
1498 ixgbe_pf_host_configure(dev);
1500 /* initialize transmission unit */
1501 ixgbe_dev_tx_init(dev);
1503 /* This can fail when allocating mbufs for descriptor rings */
1504 err = ixgbe_dev_rx_init(dev);
1506 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1510 err = ixgbe_dev_rxtx_start(dev);
1512 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1516 /* Skip link setup if loopback mode is enabled for 82599. */
1517 if (hw->mac.type == ixgbe_mac_82599EB &&
1518 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1519 goto skip_link_setup;
1521 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1522 err = hw->mac.ops.setup_sfp(hw);
1527 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1528 /* Turn on the copper */
1529 ixgbe_set_phy_power(hw, true);
1531 /* Turn on the laser */
1532 ixgbe_enable_tx_laser(hw);
1535 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1538 dev->data->dev_link.link_status = link_up;
1540 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1544 switch(dev->data->dev_conf.link_speed) {
1545 case ETH_LINK_SPEED_AUTONEG:
1546 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1547 IXGBE_LINK_SPEED_82599_AUTONEG :
1548 IXGBE_LINK_SPEED_82598_AUTONEG;
1550 case ETH_LINK_SPEED_100:
1552 * Invalid for 82598 but error will be detected by
1553 * ixgbe_setup_link()
1555 speed = IXGBE_LINK_SPEED_100_FULL;
1557 case ETH_LINK_SPEED_1000:
1558 speed = IXGBE_LINK_SPEED_1GB_FULL;
1560 case ETH_LINK_SPEED_10000:
1561 speed = IXGBE_LINK_SPEED_10GB_FULL;
1564 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1565 dev->data->dev_conf.link_speed,
1566 dev->data->port_id);
1570 err = ixgbe_setup_link(hw, speed, link_up);
1576 /* check if lsc interrupt is enabled */
1577 if (dev->data->dev_conf.intr_conf.lsc != 0)
1578 ixgbe_dev_lsc_interrupt_setup(dev);
1580 /* resume enabled intr since hw reset */
1581 ixgbe_enable_intr(dev);
1583 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1584 ETH_VLAN_EXTEND_MASK;
1585 ixgbe_vlan_offload_set(dev, mask);
1587 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1588 /* Enable vlan filtering for VMDq */
1589 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1592 /* Configure DCB hw */
1593 ixgbe_configure_dcb(dev);
1595 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1596 err = ixgbe_fdir_configure(dev);
1601 /* Restore vf rate limit */
1602 if (vfinfo != NULL) {
1603 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1604 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1605 if (vfinfo[vf].tx_rate[idx] != 0)
1606 ixgbe_set_vf_rate_limit(dev, vf,
1607 vfinfo[vf].tx_rate[idx],
1611 ixgbe_restore_statistics_mapping(dev);
1616 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1617 ixgbe_dev_clear_queues(dev);
1622 * Stop device: disable rx and tx functions to allow for reconfiguring.
1625 ixgbe_dev_stop(struct rte_eth_dev *dev)
1627 struct rte_eth_link link;
1628 struct ixgbe_hw *hw =
1629 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1630 struct ixgbe_vf_info *vfinfo =
1631 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1632 struct ixgbe_filter_info *filter_info =
1633 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1634 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1637 PMD_INIT_FUNC_TRACE();
1639 /* disable interrupts */
1640 ixgbe_disable_intr(hw);
1643 ixgbe_pf_reset_hw(hw);
1644 hw->adapter_stopped = FALSE;
1647 ixgbe_stop_adapter(hw);
1649 for (vf = 0; vfinfo != NULL &&
1650 vf < dev->pci_dev->max_vfs; vf++)
1651 vfinfo[vf].clear_to_send = false;
1653 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1654 /* Turn off the copper */
1655 ixgbe_set_phy_power(hw, false);
1657 /* Turn off the laser */
1658 ixgbe_disable_tx_laser(hw);
1661 ixgbe_dev_clear_queues(dev);
1663 /* Clear stored conf */
1664 dev->data->scattered_rx = 0;
1667 /* Clear recorded link status */
1668 memset(&link, 0, sizeof(link));
1669 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1671 /* Remove all ntuple filters of the device */
1672 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1673 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1674 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1675 TAILQ_REMOVE(&filter_info->fivetuple_list,
1679 memset(filter_info->fivetuple_mask, 0,
1680 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1685 * Set device link up: enable tx.
1688 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1690 struct ixgbe_hw *hw =
1691 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1692 if (hw->mac.type == ixgbe_mac_82599EB) {
1693 #ifdef RTE_NIC_BYPASS
1694 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1695 /* Not suported in bypass mode */
1696 PMD_INIT_LOG(ERR, "Set link up is not supported "
1697 "by device id 0x%x", hw->device_id);
1703 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1704 /* Turn on the copper */
1705 ixgbe_set_phy_power(hw, true);
1707 /* Turn on the laser */
1708 ixgbe_enable_tx_laser(hw);
1715 * Set device link down: disable tx.
1718 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1720 struct ixgbe_hw *hw =
1721 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1722 if (hw->mac.type == ixgbe_mac_82599EB) {
1723 #ifdef RTE_NIC_BYPASS
1724 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1725 /* Not suported in bypass mode */
1726 PMD_INIT_LOG(ERR, "Set link down is not supported "
1727 "by device id 0x%x", hw->device_id);
1733 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1734 /* Turn off the copper */
1735 ixgbe_set_phy_power(hw, false);
1737 /* Turn off the laser */
1738 ixgbe_disable_tx_laser(hw);
1745 * Reest and stop device.
1748 ixgbe_dev_close(struct rte_eth_dev *dev)
1750 struct ixgbe_hw *hw =
1751 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1753 PMD_INIT_FUNC_TRACE();
1755 ixgbe_pf_reset_hw(hw);
1757 ixgbe_dev_stop(dev);
1758 hw->adapter_stopped = 1;
1760 ixgbe_disable_pcie_master(hw);
1762 /* reprogram the RAR[0] in case user changed it. */
1763 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1767 * This function is based on ixgbe_update_stats_counters() in base/ixgbe.c
1770 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1772 struct ixgbe_hw *hw =
1773 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1774 struct ixgbe_hw_stats *hw_stats =
1775 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1776 uint32_t bprc, lxon, lxoff, total;
1777 uint64_t total_missed_rx, total_qbrc, total_qprc;
1780 total_missed_rx = 0;
1784 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1785 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1786 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1787 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1789 for (i = 0; i < 8; i++) {
1791 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1792 /* global total per queue */
1793 hw_stats->mpc[i] += mp;
1794 /* Running comprehensive total for stats display */
1795 total_missed_rx += hw_stats->mpc[i];
1796 if (hw->mac.type == ixgbe_mac_82598EB)
1797 hw_stats->rnbc[i] +=
1798 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1799 hw_stats->pxontxc[i] +=
1800 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1801 hw_stats->pxonrxc[i] +=
1802 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1803 hw_stats->pxofftxc[i] +=
1804 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1805 hw_stats->pxoffrxc[i] +=
1806 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1807 hw_stats->pxon2offc[i] +=
1808 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1810 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1811 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1812 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1813 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1814 hw_stats->qbrc[i] +=
1815 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1816 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1817 hw_stats->qbtc[i] +=
1818 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1819 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1821 total_qprc += hw_stats->qprc[i];
1822 total_qbrc += hw_stats->qbrc[i];
1824 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1825 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1826 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1828 /* Note that gprc counts missed packets */
1829 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1831 if (hw->mac.type != ixgbe_mac_82598EB) {
1832 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1833 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1834 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1835 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1836 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1837 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1838 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1839 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1841 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1842 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1843 /* 82598 only has a counter in the high register */
1844 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1845 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1846 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1850 * Workaround: mprc hardware is incorrectly counting
1851 * broadcasts, so for now we subtract those.
1853 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1854 hw_stats->bprc += bprc;
1855 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1856 if (hw->mac.type == ixgbe_mac_82598EB)
1857 hw_stats->mprc -= bprc;
1859 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1860 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1861 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1862 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1863 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1864 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1866 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1867 hw_stats->lxontxc += lxon;
1868 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1869 hw_stats->lxofftxc += lxoff;
1870 total = lxon + lxoff;
1872 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1873 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1874 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1875 hw_stats->gptc -= total;
1876 hw_stats->mptc -= total;
1877 hw_stats->ptc64 -= total;
1878 hw_stats->gotc -= total * ETHER_MIN_LEN;
1880 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1881 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1882 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1883 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1884 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1885 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1886 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1887 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1888 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1889 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1890 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1891 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1892 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1893 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1894 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1895 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1896 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1897 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1898 /* Only read FCOE on 82599 */
1899 if (hw->mac.type != ixgbe_mac_82598EB) {
1900 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1901 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1902 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1903 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1904 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1910 /* Fill out the rte_eth_stats statistics structure */
1911 stats->ipackets = total_qprc;
1912 stats->ibytes = total_qbrc;
1913 stats->opackets = hw_stats->gptc;
1914 stats->obytes = hw_stats->gotc;
1915 stats->imcasts = hw_stats->mprc;
1917 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1918 stats->q_ipackets[i] = hw_stats->qprc[i];
1919 stats->q_opackets[i] = hw_stats->qptc[i];
1920 stats->q_ibytes[i] = hw_stats->qbrc[i];
1921 stats->q_obytes[i] = hw_stats->qbtc[i];
1922 stats->q_errors[i] = hw_stats->qprdc[i];
1926 stats->ibadcrc = hw_stats->crcerrs;
1927 stats->ibadlen = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1928 stats->imissed = total_missed_rx;
1929 stats->ierrors = stats->ibadcrc +
1932 hw_stats->illerrc + hw_stats->errbc;
1937 /* XON/XOFF pause frames */
1938 stats->tx_pause_xon = hw_stats->lxontxc;
1939 stats->rx_pause_xon = hw_stats->lxonrxc;
1940 stats->tx_pause_xoff = hw_stats->lxofftxc;
1941 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1943 /* Flow Director Stats registers */
1944 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1945 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1946 stats->fdirmatch = hw_stats->fdirmatch;
1947 stats->fdirmiss = hw_stats->fdirmiss;
1951 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1953 struct ixgbe_hw_stats *stats =
1954 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1956 /* HW registers are cleared on read */
1957 ixgbe_dev_stats_get(dev, NULL);
1959 /* Reset software totals */
1960 memset(stats, 0, sizeof(*stats));
1964 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1966 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1967 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1968 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1970 /* Good Rx packet, include VF loopback */
1971 UPDATE_VF_STAT(IXGBE_VFGPRC,
1972 hw_stats->last_vfgprc, hw_stats->vfgprc);
1974 /* Good Rx octets, include VF loopback */
1975 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1976 hw_stats->last_vfgorc, hw_stats->vfgorc);
1978 /* Good Tx packet, include VF loopback */
1979 UPDATE_VF_STAT(IXGBE_VFGPTC,
1980 hw_stats->last_vfgptc, hw_stats->vfgptc);
1982 /* Good Tx octets, include VF loopback */
1983 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1984 hw_stats->last_vfgotc, hw_stats->vfgotc);
1986 /* Rx Multicst Packet */
1987 UPDATE_VF_STAT(IXGBE_VFMPRC,
1988 hw_stats->last_vfmprc, hw_stats->vfmprc);
1993 stats->ipackets = hw_stats->vfgprc;
1994 stats->ibytes = hw_stats->vfgorc;
1995 stats->opackets = hw_stats->vfgptc;
1996 stats->obytes = hw_stats->vfgotc;
1997 stats->imcasts = hw_stats->vfmprc;
2001 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2003 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2004 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2006 /* Sync HW register to the last stats */
2007 ixgbevf_dev_stats_get(dev, NULL);
2009 /* reset HW current stats*/
2010 hw_stats->vfgprc = 0;
2011 hw_stats->vfgorc = 0;
2012 hw_stats->vfgptc = 0;
2013 hw_stats->vfgotc = 0;
2014 hw_stats->vfmprc = 0;
2019 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2021 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2024 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2025 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2026 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2027 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2028 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2029 dev_info->max_vfs = dev->pci_dev->max_vfs;
2030 if (hw->mac.type == ixgbe_mac_82598EB)
2031 dev_info->max_vmdq_pools = ETH_16_POOLS;
2033 dev_info->max_vmdq_pools = ETH_64_POOLS;
2034 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2035 dev_info->rx_offload_capa =
2036 DEV_RX_OFFLOAD_VLAN_STRIP |
2037 DEV_RX_OFFLOAD_IPV4_CKSUM |
2038 DEV_RX_OFFLOAD_UDP_CKSUM |
2039 DEV_RX_OFFLOAD_TCP_CKSUM;
2042 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2045 if ((hw->mac.type == ixgbe_mac_82599EB ||
2046 hw->mac.type == ixgbe_mac_X540) &&
2047 !RTE_ETH_DEV_SRIOV(dev).active)
2048 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2050 dev_info->tx_offload_capa =
2051 DEV_TX_OFFLOAD_VLAN_INSERT |
2052 DEV_TX_OFFLOAD_IPV4_CKSUM |
2053 DEV_TX_OFFLOAD_UDP_CKSUM |
2054 DEV_TX_OFFLOAD_TCP_CKSUM |
2055 DEV_TX_OFFLOAD_SCTP_CKSUM |
2056 DEV_TX_OFFLOAD_TCP_TSO;
2058 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2060 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2061 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2062 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2064 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2068 dev_info->default_txconf = (struct rte_eth_txconf) {
2070 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2071 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2072 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2074 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2075 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2076 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2077 ETH_TXQ_FLAGS_NOOFFLOADS,
2079 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2080 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2081 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2085 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2086 struct rte_eth_dev_info *dev_info)
2088 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2090 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2091 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2092 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2093 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2094 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2095 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2096 dev_info->max_vfs = dev->pci_dev->max_vfs;
2097 if (hw->mac.type == ixgbe_mac_82598EB)
2098 dev_info->max_vmdq_pools = ETH_16_POOLS;
2100 dev_info->max_vmdq_pools = ETH_64_POOLS;
2101 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2102 DEV_RX_OFFLOAD_IPV4_CKSUM |
2103 DEV_RX_OFFLOAD_UDP_CKSUM |
2104 DEV_RX_OFFLOAD_TCP_CKSUM;
2105 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2106 DEV_TX_OFFLOAD_IPV4_CKSUM |
2107 DEV_TX_OFFLOAD_UDP_CKSUM |
2108 DEV_TX_OFFLOAD_TCP_CKSUM |
2109 DEV_TX_OFFLOAD_SCTP_CKSUM;
2111 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2113 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2114 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2115 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2117 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2121 dev_info->default_txconf = (struct rte_eth_txconf) {
2123 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2124 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2125 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2127 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2128 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2129 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2130 ETH_TXQ_FLAGS_NOOFFLOADS,
2134 /* return 0 means link status changed, -1 means not changed */
2136 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2138 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2139 struct rte_eth_link link, old;
2140 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2144 link.link_status = 0;
2145 link.link_speed = 0;
2146 link.link_duplex = 0;
2147 memset(&old, 0, sizeof(old));
2148 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2150 hw->mac.get_link_status = true;
2152 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2153 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2154 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2156 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2159 link.link_speed = ETH_LINK_SPEED_100;
2160 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2161 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2162 if (link.link_status == old.link_status)
2168 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2169 if (link.link_status == old.link_status)
2173 link.link_status = 1;
2174 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2176 switch (link_speed) {
2178 case IXGBE_LINK_SPEED_UNKNOWN:
2179 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2180 link.link_speed = ETH_LINK_SPEED_100;
2183 case IXGBE_LINK_SPEED_100_FULL:
2184 link.link_speed = ETH_LINK_SPEED_100;
2187 case IXGBE_LINK_SPEED_1GB_FULL:
2188 link.link_speed = ETH_LINK_SPEED_1000;
2191 case IXGBE_LINK_SPEED_10GB_FULL:
2192 link.link_speed = ETH_LINK_SPEED_10000;
2195 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2197 if (link.link_status == old.link_status)
2204 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2206 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2209 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2210 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2211 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2215 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2217 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2221 fctrl &= (~IXGBE_FCTRL_UPE);
2222 if (dev->data->all_multicast == 1)
2223 fctrl |= IXGBE_FCTRL_MPE;
2225 fctrl &= (~IXGBE_FCTRL_MPE);
2226 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2230 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2232 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2235 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2236 fctrl |= IXGBE_FCTRL_MPE;
2237 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2241 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2243 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246 if (dev->data->promiscuous == 1)
2247 return; /* must remain in all_multicast mode */
2249 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2250 fctrl &= (~IXGBE_FCTRL_MPE);
2251 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2255 * It clears the interrupt causes and enables the interrupt.
2256 * It will be called once only during nic initialized.
2259 * Pointer to struct rte_eth_dev.
2262 * - On success, zero.
2263 * - On failure, a negative value.
2266 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2268 struct ixgbe_interrupt *intr =
2269 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2271 ixgbe_dev_link_status_print(dev);
2272 intr->mask |= IXGBE_EICR_LSC;
2278 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2281 * Pointer to struct rte_eth_dev.
2284 * - On success, zero.
2285 * - On failure, a negative value.
2288 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2291 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2292 struct ixgbe_interrupt *intr =
2293 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2295 /* clear all cause mask */
2296 ixgbe_disable_intr(hw);
2298 /* read-on-clear nic registers here */
2299 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2300 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2303 if (eicr & IXGBE_EICR_LSC) {
2304 /* set flag for async link update */
2305 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2308 if (eicr & IXGBE_EICR_MAILBOX)
2309 intr->flags |= IXGBE_FLAG_MAILBOX;
2315 * It gets and then prints the link status.
2318 * Pointer to struct rte_eth_dev.
2321 * - On success, zero.
2322 * - On failure, a negative value.
2325 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2327 struct rte_eth_link link;
2329 memset(&link, 0, sizeof(link));
2330 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2331 if (link.link_status) {
2332 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2333 (int)(dev->data->port_id),
2334 (unsigned)link.link_speed,
2335 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2336 "full-duplex" : "half-duplex");
2338 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2339 (int)(dev->data->port_id));
2341 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2342 dev->pci_dev->addr.domain,
2343 dev->pci_dev->addr.bus,
2344 dev->pci_dev->addr.devid,
2345 dev->pci_dev->addr.function);
2349 * It executes link_update after knowing an interrupt occurred.
2352 * Pointer to struct rte_eth_dev.
2355 * - On success, zero.
2356 * - On failure, a negative value.
2359 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2361 struct ixgbe_interrupt *intr =
2362 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2364 struct rte_eth_link link;
2365 int intr_enable_delay = false;
2367 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2369 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2370 ixgbe_pf_mbx_process(dev);
2371 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2374 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2375 /* get the link status before link update, for predicting later */
2376 memset(&link, 0, sizeof(link));
2377 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2379 ixgbe_dev_link_update(dev, 0);
2382 if (!link.link_status)
2383 /* handle it 1 sec later, wait it being stable */
2384 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2385 /* likely to down */
2387 /* handle it 4 sec later, wait it being stable */
2388 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2390 ixgbe_dev_link_status_print(dev);
2392 intr_enable_delay = true;
2395 if (intr_enable_delay) {
2396 if (rte_eal_alarm_set(timeout * 1000,
2397 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2398 PMD_DRV_LOG(ERR, "Error setting alarm");
2400 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2401 ixgbe_enable_intr(dev);
2402 rte_intr_enable(&(dev->pci_dev->intr_handle));
2410 * Interrupt handler which shall be registered for alarm callback for delayed
2411 * handling specific interrupt to wait for the stable nic state. As the
2412 * NIC interrupt state is not stable for ixgbe after link is just down,
2413 * it needs to wait 4 seconds to get the stable status.
2416 * Pointer to interrupt handle.
2418 * The address of parameter (struct rte_eth_dev *) regsitered before.
2424 ixgbe_dev_interrupt_delayed_handler(void *param)
2426 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2427 struct ixgbe_interrupt *intr =
2428 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2429 struct ixgbe_hw *hw =
2430 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2433 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2434 if (eicr & IXGBE_EICR_MAILBOX)
2435 ixgbe_pf_mbx_process(dev);
2437 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2438 ixgbe_dev_link_update(dev, 0);
2439 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2440 ixgbe_dev_link_status_print(dev);
2441 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2444 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2445 ixgbe_enable_intr(dev);
2446 rte_intr_enable(&(dev->pci_dev->intr_handle));
2450 * Interrupt handler triggered by NIC for handling
2451 * specific interrupt.
2454 * Pointer to interrupt handle.
2456 * The address of parameter (struct rte_eth_dev *) regsitered before.
2462 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2465 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2466 ixgbe_dev_interrupt_get_status(dev);
2467 ixgbe_dev_interrupt_action(dev);
2471 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2473 struct ixgbe_hw *hw;
2475 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2480 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2482 struct ixgbe_hw *hw;
2484 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2485 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2489 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2491 struct ixgbe_hw *hw;
2497 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2499 fc_conf->pause_time = hw->fc.pause_time;
2500 fc_conf->high_water = hw->fc.high_water[0];
2501 fc_conf->low_water = hw->fc.low_water[0];
2502 fc_conf->send_xon = hw->fc.send_xon;
2503 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2506 * Return rx_pause status according to actual setting of
2509 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2510 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2516 * Return tx_pause status according to actual setting of
2519 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2520 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2525 if (rx_pause && tx_pause)
2526 fc_conf->mode = RTE_FC_FULL;
2528 fc_conf->mode = RTE_FC_RX_PAUSE;
2530 fc_conf->mode = RTE_FC_TX_PAUSE;
2532 fc_conf->mode = RTE_FC_NONE;
2538 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2540 struct ixgbe_hw *hw;
2542 uint32_t rx_buf_size;
2543 uint32_t max_high_water;
2545 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2552 PMD_INIT_FUNC_TRACE();
2554 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555 if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2557 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2558 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2561 * At least reserve one Ethernet frame for watermark
2562 * high_water/low_water in kilo bytes for ixgbe
2564 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2565 if ((fc_conf->high_water > max_high_water) ||
2566 (fc_conf->high_water < fc_conf->low_water)) {
2567 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2568 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2572 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2573 hw->fc.pause_time = fc_conf->pause_time;
2574 hw->fc.high_water[0] = fc_conf->high_water;
2575 hw->fc.low_water[0] = fc_conf->low_water;
2576 hw->fc.send_xon = fc_conf->send_xon;
2578 err = ixgbe_fc_enable(hw);
2580 /* Not negotiated is not an error case */
2581 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2583 /* check if we want to forward MAC frames - driver doesn't have native
2584 * capability to do that, so we'll write the registers ourselves */
2586 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2588 /* set or clear MFLCN.PMCF bit depending on configuration */
2589 if (fc_conf->mac_ctrl_frame_fwd != 0)
2590 mflcn |= IXGBE_MFLCN_PMCF;
2592 mflcn &= ~IXGBE_MFLCN_PMCF;
2594 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2595 IXGBE_WRITE_FLUSH(hw);
2600 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2605 * ixgbe_pfc_enable_generic - Enable flow control
2606 * @hw: pointer to hardware structure
2607 * @tc_num: traffic class number
2608 * Enable flow control according to the current settings.
2611 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2614 uint32_t mflcn_reg, fccfg_reg;
2616 uint32_t fcrtl, fcrth;
2620 /* Validate the water mark configuration */
2621 if (!hw->fc.pause_time) {
2622 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2626 /* Low water mark of zero causes XOFF floods */
2627 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2628 /* High/Low water can not be 0 */
2629 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2630 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2631 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2635 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2636 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2637 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2641 /* Negotiate the fc mode to use */
2642 ixgbe_fc_autoneg(hw);
2644 /* Disable any previous flow control settings */
2645 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2646 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2648 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2649 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2651 switch (hw->fc.current_mode) {
2654 * If the count of enabled RX Priority Flow control >1,
2655 * and the TX pause can not be disabled
2658 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2659 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2660 if (reg & IXGBE_FCRTH_FCEN)
2664 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2666 case ixgbe_fc_rx_pause:
2668 * Rx Flow control is enabled and Tx Flow control is
2669 * disabled by software override. Since there really
2670 * isn't a way to advertise that we are capable of RX
2671 * Pause ONLY, we will advertise that we support both
2672 * symmetric and asymmetric Rx PAUSE. Later, we will
2673 * disable the adapter's ability to send PAUSE frames.
2675 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2677 * If the count of enabled RX Priority Flow control >1,
2678 * and the TX pause can not be disabled
2681 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2682 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2683 if (reg & IXGBE_FCRTH_FCEN)
2687 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2689 case ixgbe_fc_tx_pause:
2691 * Tx Flow control is enabled, and Rx Flow control is
2692 * disabled by software override.
2694 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2697 /* Flow control (both Rx and Tx) is enabled by SW override. */
2698 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2699 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2702 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2703 ret_val = IXGBE_ERR_CONFIG;
2708 /* Set 802.3x based flow control settings. */
2709 mflcn_reg |= IXGBE_MFLCN_DPF;
2710 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2711 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2713 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2714 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2715 hw->fc.high_water[tc_num]) {
2716 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2717 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2718 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2720 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2722 * In order to prevent Tx hangs when the internal Tx
2723 * switch is enabled we must set the high water mark
2724 * to the maximum FCRTH value. This allows the Tx
2725 * switch to function even under heavy Rx workloads.
2727 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2729 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2731 /* Configure pause time (2 TCs per register) */
2732 reg = hw->fc.pause_time * 0x00010001;
2733 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2734 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2736 /* Configure flow control refresh threshold value */
2737 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2744 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2746 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2747 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2749 if(hw->mac.type != ixgbe_mac_82598EB) {
2750 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2756 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2759 uint32_t rx_buf_size;
2760 uint32_t max_high_water;
2762 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2763 struct ixgbe_hw *hw =
2764 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765 struct ixgbe_dcb_config *dcb_config =
2766 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2768 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2775 PMD_INIT_FUNC_TRACE();
2777 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2778 tc_num = map[pfc_conf->priority];
2779 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2780 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2782 * At least reserve one Ethernet frame for watermark
2783 * high_water/low_water in kilo bytes for ixgbe
2785 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2786 if ((pfc_conf->fc.high_water > max_high_water) ||
2787 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2788 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2789 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2793 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2794 hw->fc.pause_time = pfc_conf->fc.pause_time;
2795 hw->fc.send_xon = pfc_conf->fc.send_xon;
2796 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2797 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2799 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2801 /* Not negotiated is not an error case */
2802 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2805 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2810 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2811 struct rte_eth_rss_reta_entry64 *reta_conf,
2816 uint16_t idx, shift;
2817 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819 PMD_INIT_FUNC_TRACE();
2820 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2821 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2822 "(%d) doesn't match the number hardware can supported "
2823 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2827 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2828 idx = i / RTE_RETA_GROUP_SIZE;
2829 shift = i % RTE_RETA_GROUP_SIZE;
2830 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2834 if (mask == IXGBE_4_BIT_MASK)
2837 r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2838 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2839 if (mask & (0x1 << j))
2840 reta |= reta_conf[idx].reta[shift + j] <<
2843 reta |= r & (IXGBE_8_BIT_MASK <<
2846 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2853 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2854 struct rte_eth_rss_reta_entry64 *reta_conf,
2859 uint16_t idx, shift;
2860 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862 PMD_INIT_FUNC_TRACE();
2863 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2864 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2865 "(%d) doesn't match the number hardware can supported "
2866 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2870 for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2871 idx = i / RTE_RETA_GROUP_SIZE;
2872 shift = i % RTE_RETA_GROUP_SIZE;
2873 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2878 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2879 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2880 if (mask & (0x1 << j))
2881 reta_conf[idx].reta[shift + j] =
2882 ((reta >> (CHAR_BIT * j)) &
2891 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2892 uint32_t index, uint32_t pool)
2894 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2895 uint32_t enable_addr = 1;
2897 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2901 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2903 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2905 ixgbe_clear_rar(hw, index);
2909 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2913 struct ixgbe_hw *hw;
2914 struct rte_eth_dev_info dev_info;
2915 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2917 ixgbe_dev_info_get(dev, &dev_info);
2919 /* check that mtu is within the allowed range */
2920 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2923 /* refuse mtu that requires the support of scattered packets when this
2924 * feature has not been enabled before. */
2925 if (!dev->data->scattered_rx &&
2926 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2927 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2930 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2931 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2933 /* switch to jumbo mode if needed */
2934 if (frame_size > ETHER_MAX_LEN) {
2935 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2936 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2938 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2939 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2941 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2943 /* update max frame size */
2944 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2946 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2947 maxfrs &= 0x0000FFFF;
2948 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2949 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2955 * Virtual Function operations
2958 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2960 PMD_INIT_FUNC_TRACE();
2962 /* Clear interrupt mask to stop from interrupts being generated */
2963 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2965 IXGBE_WRITE_FLUSH(hw);
2969 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2971 struct rte_eth_conf* conf = &dev->data->dev_conf;
2972 struct ixgbe_adapter *adapter =
2973 (struct ixgbe_adapter *)dev->data->dev_private;
2975 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2976 dev->data->port_id);
2979 * VF has no ability to enable/disable HW CRC
2980 * Keep the persistent behavior the same as Host PF
2982 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2983 if (!conf->rxmode.hw_strip_crc) {
2984 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2985 conf->rxmode.hw_strip_crc = 1;
2988 if (conf->rxmode.hw_strip_crc) {
2989 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2990 conf->rxmode.hw_strip_crc = 0;
2995 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2996 * allocation or vector Rx preconditions we will reset it.
2998 adapter->rx_bulk_alloc_allowed = true;
2999 adapter->rx_vec_allowed = true;
3005 ixgbevf_dev_start(struct rte_eth_dev *dev)
3007 struct ixgbe_hw *hw =
3008 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3011 PMD_INIT_FUNC_TRACE();
3013 hw->mac.ops.reset_hw(hw);
3014 hw->mac.get_link_status = true;
3016 /* negotiate mailbox API version to use with the PF. */
3017 ixgbevf_negotiate_api(hw);
3019 ixgbevf_dev_tx_init(dev);
3021 /* This can fail when allocating mbufs for descriptor rings */
3022 err = ixgbevf_dev_rx_init(dev);
3024 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3025 ixgbe_dev_clear_queues(dev);
3030 ixgbevf_set_vfta_all(dev,1);
3033 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3034 ETH_VLAN_EXTEND_MASK;
3035 ixgbevf_vlan_offload_set(dev, mask);
3037 ixgbevf_dev_rxtx_start(dev);
3043 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3045 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3047 PMD_INIT_FUNC_TRACE();
3049 hw->adapter_stopped = TRUE;
3050 ixgbe_stop_adapter(hw);
3053 * Clear what we set, but we still keep shadow_vfta to
3054 * restore after device starts
3056 ixgbevf_set_vfta_all(dev,0);
3058 /* Clear stored conf */
3059 dev->data->scattered_rx = 0;
3061 ixgbe_dev_clear_queues(dev);
3065 ixgbevf_dev_close(struct rte_eth_dev *dev)
3067 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069 PMD_INIT_FUNC_TRACE();
3073 ixgbevf_dev_stop(dev);
3075 /* reprogram the RAR[0] in case user changed it. */
3076 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3079 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3081 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3082 struct ixgbe_vfta * shadow_vfta =
3083 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3084 int i = 0, j = 0, vfta = 0, mask = 1;
3086 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3087 vfta = shadow_vfta->vfta[i];
3090 for (j = 0; j < 32; j++){
3092 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3101 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3103 struct ixgbe_hw *hw =
3104 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3105 struct ixgbe_vfta * shadow_vfta =
3106 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3107 uint32_t vid_idx = 0;
3108 uint32_t vid_bit = 0;
3111 PMD_INIT_FUNC_TRACE();
3113 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3114 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3116 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3119 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3120 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3122 /* Save what we set and retore it after device reset */
3124 shadow_vfta->vfta[vid_idx] |= vid_bit;
3126 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3132 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3134 struct ixgbe_hw *hw =
3135 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138 PMD_INIT_FUNC_TRACE();
3140 if(queue >= hw->mac.max_rx_queues)
3143 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3145 ctrl |= IXGBE_RXDCTL_VME;
3147 ctrl &= ~IXGBE_RXDCTL_VME;
3148 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3150 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3154 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3156 struct ixgbe_hw *hw =
3157 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3161 /* VF function only support hw strip feature, others are not support */
3162 if(mask & ETH_VLAN_STRIP_MASK){
3163 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3165 for(i=0; i < hw->mac.max_rx_queues; i++)
3166 ixgbevf_vlan_strip_queue_set(dev,i,on);
3171 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3175 /* we only need to do this if VMDq is enabled */
3176 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3177 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3178 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3186 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3188 uint32_t vector = 0;
3189 switch (hw->mac.mc_filter_type) {
3190 case 0: /* use bits [47:36] of the address */
3191 vector = ((uc_addr->addr_bytes[4] >> 4) |
3192 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3194 case 1: /* use bits [46:35] of the address */
3195 vector = ((uc_addr->addr_bytes[4] >> 3) |
3196 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3198 case 2: /* use bits [45:34] of the address */
3199 vector = ((uc_addr->addr_bytes[4] >> 2) |
3200 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3202 case 3: /* use bits [43:32] of the address */
3203 vector = ((uc_addr->addr_bytes[4]) |
3204 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3206 default: /* Invalid mc_filter_type */
3210 /* vector can only be 12-bits or boundary will be exceeded */
3216 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3224 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3225 const uint32_t ixgbe_uta_bit_shift = 5;
3226 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3227 const uint32_t bit1 = 0x1;
3229 struct ixgbe_hw *hw =
3230 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3231 struct ixgbe_uta_info *uta_info =
3232 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3234 /* The UTA table only exists on 82599 hardware and newer */
3235 if (hw->mac.type < ixgbe_mac_82599EB)
3238 vector = ixgbe_uta_vector(hw,mac_addr);
3239 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3240 uta_shift = vector & ixgbe_uta_bit_mask;
3242 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3246 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3248 uta_info->uta_in_use++;
3249 reg_val |= (bit1 << uta_shift);
3250 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3252 uta_info->uta_in_use--;
3253 reg_val &= ~(bit1 << uta_shift);
3254 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3257 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3259 if (uta_info->uta_in_use > 0)
3260 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3261 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3263 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3269 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3272 struct ixgbe_hw *hw =
3273 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3274 struct ixgbe_uta_info *uta_info =
3275 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3277 /* The UTA table only exists on 82599 hardware and newer */
3278 if (hw->mac.type < ixgbe_mac_82599EB)
3282 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3283 uta_info->uta_shadow[i] = ~0;
3284 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3287 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3288 uta_info->uta_shadow[i] = 0;
3289 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3297 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3299 uint32_t new_val = orig_val;
3301 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3302 new_val |= IXGBE_VMOLR_AUPE;
3303 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3304 new_val |= IXGBE_VMOLR_ROMPE;
3305 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3306 new_val |= IXGBE_VMOLR_ROPE;
3307 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3308 new_val |= IXGBE_VMOLR_BAM;
3309 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3310 new_val |= IXGBE_VMOLR_MPE;
3316 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3317 uint16_t rx_mask, uint8_t on)
3321 struct ixgbe_hw *hw =
3322 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3323 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3325 if (hw->mac.type == ixgbe_mac_82598EB) {
3326 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3327 " on 82599 hardware and newer");
3330 if (ixgbe_vmdq_mode_check(hw) < 0)
3333 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3340 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3346 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3350 const uint8_t bit1 = 0x1;
3352 struct ixgbe_hw *hw =
3353 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3355 if (ixgbe_vmdq_mode_check(hw) < 0)
3358 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3359 reg = IXGBE_READ_REG(hw, addr);
3367 IXGBE_WRITE_REG(hw, addr,reg);
3373 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3377 const uint8_t bit1 = 0x1;
3379 struct ixgbe_hw *hw =
3380 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3382 if (ixgbe_vmdq_mode_check(hw) < 0)
3385 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3386 reg = IXGBE_READ_REG(hw, addr);
3394 IXGBE_WRITE_REG(hw, addr,reg);
3400 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3401 uint64_t pool_mask, uint8_t vlan_on)
3405 struct ixgbe_hw *hw =
3406 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3408 if (ixgbe_vmdq_mode_check(hw) < 0)
3410 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3411 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3412 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3420 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
3421 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
3422 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
3423 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
3424 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
3425 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
3426 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
3429 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3430 struct rte_eth_mirror_conf *mirror_conf,
3431 uint8_t rule_id, uint8_t on)
3433 uint32_t mr_ctl,vlvf;
3434 uint32_t mp_lsb = 0;
3435 uint32_t mv_msb = 0;
3436 uint32_t mv_lsb = 0;
3437 uint32_t mp_msb = 0;
3440 uint64_t vlan_mask = 0;
3442 const uint8_t pool_mask_offset = 32;
3443 const uint8_t vlan_mask_offset = 32;
3444 const uint8_t dst_pool_offset = 8;
3445 const uint8_t rule_mr_offset = 4;
3446 const uint8_t mirror_rule_mask= 0x0F;
3448 struct ixgbe_mirror_info *mr_info =
3449 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3450 struct ixgbe_hw *hw =
3451 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3452 uint8_t mirror_type = 0;
3454 if (ixgbe_vmdq_mode_check(hw) < 0)
3457 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3460 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
3461 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
3462 mirror_conf->rule_type);
3466 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
3467 mirror_type |= IXGBE_MRCTL_VLME;
3468 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3469 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3470 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3471 /* search vlan id related pool vlan filter index */
3472 reg_index = ixgbe_find_vlvf_slot(hw,
3473 mirror_conf->vlan.vlan_id[i]);
3476 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3477 if ((vlvf & IXGBE_VLVF_VIEN) &&
3478 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
3479 mirror_conf->vlan.vlan_id[i]))
3480 vlan_mask |= (1ULL << reg_index);
3487 mv_lsb = vlan_mask & 0xFFFFFFFF;
3488 mv_msb = vlan_mask >> vlan_mask_offset;
3490 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3491 mirror_conf->vlan.vlan_mask;
3492 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3493 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3494 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3495 mirror_conf->vlan.vlan_id[i];
3500 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3501 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3502 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3507 * if enable pool mirror, write related pool mask register,if disable
3508 * pool mirror, clear PFMRVM register
3510 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
3511 mirror_type |= IXGBE_MRCTL_VPME;
3513 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3514 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3515 mr_info->mr_conf[rule_id].pool_mask =
3516 mirror_conf->pool_mask;
3521 mr_info->mr_conf[rule_id].pool_mask = 0;
3524 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
3525 mirror_type |= IXGBE_MRCTL_UPME;
3526 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
3527 mirror_type |= IXGBE_MRCTL_DPME;
3529 /* read mirror control register and recalculate it */
3530 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
3533 mr_ctl |= mirror_type;
3534 mr_ctl &= mirror_rule_mask;
3535 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3537 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
3539 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
3540 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3542 /* write mirrror control register */
3543 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3545 /* write pool mirrror control register */
3546 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
3547 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3548 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3551 /* write VLAN mirrror control register */
3552 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
3553 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3554 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3562 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3565 uint32_t lsb_val = 0;
3566 uint32_t msb_val = 0;
3567 const uint8_t rule_mr_offset = 4;
3569 struct ixgbe_hw *hw =
3570 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3571 struct ixgbe_mirror_info *mr_info =
3572 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3574 if (ixgbe_vmdq_mode_check(hw) < 0)
3577 memset(&mr_info->mr_conf[rule_id], 0,
3578 sizeof(struct rte_eth_mirror_conf));
3580 /* clear PFVMCTL register */
3581 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3583 /* clear pool mask register */
3584 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3585 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3587 /* clear vlan mask register */
3588 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3589 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3594 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3595 uint16_t queue_idx, uint16_t tx_rate)
3597 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3598 uint32_t rf_dec, rf_int;
3600 uint16_t link_speed = dev->data->dev_link.link_speed;
3602 if (queue_idx >= hw->mac.max_tx_queues)
3606 /* Calculate the rate factor values to set */
3607 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3608 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3609 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3611 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3612 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3613 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3614 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3620 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3621 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3624 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3625 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3626 IXGBE_MAX_JUMBO_FRAME_SIZE))
3627 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3628 IXGBE_MMW_SIZE_JUMBO_FRAME);
3630 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3631 IXGBE_MMW_SIZE_DEFAULT);
3633 /* Set RTTBCNRC of queue X */
3634 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3635 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3636 IXGBE_WRITE_FLUSH(hw);
3641 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3642 uint16_t tx_rate, uint64_t q_msk)
3644 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3645 struct ixgbe_vf_info *vfinfo =
3646 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3647 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3648 uint32_t queue_stride =
3649 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3650 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3651 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3652 uint16_t total_rate = 0;
3654 if (queue_end >= hw->mac.max_tx_queues)
3657 if (vfinfo != NULL) {
3658 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3661 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3663 total_rate += vfinfo[vf_idx].tx_rate[idx];
3668 /* Store tx_rate for this vf. */
3669 for (idx = 0; idx < nb_q_per_pool; idx++) {
3670 if (((uint64_t)0x1 << idx) & q_msk) {
3671 if (vfinfo[vf].tx_rate[idx] != tx_rate)
3672 vfinfo[vf].tx_rate[idx] = tx_rate;
3673 total_rate += tx_rate;
3677 if (total_rate > dev->data->dev_link.link_speed) {
3679 * Reset stored TX rate of the VF if it causes exceed
3682 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3686 /* Set RTTBCNRC of each queue/pool for vf X */
3687 for (; queue_idx <= queue_end; queue_idx++) {
3689 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3697 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3698 __attribute__((unused)) uint32_t index,
3699 __attribute__((unused)) uint32_t pool)
3701 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3705 * On a 82599 VF, adding again the same MAC addr is not an idempotent
3706 * operation. Trap this case to avoid exhausting the [very limited]
3707 * set of PF resources used to store VF MAC addresses.
3709 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3711 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3714 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3718 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3720 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3721 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3722 struct ether_addr *mac_addr;
3727 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3728 * not support the deletion of a given MAC address.
3729 * Instead, it imposes to delete all MAC addresses, then to add again
3730 * all MAC addresses with the exception of the one to be deleted.
3732 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3735 * Add again all MAC addresses, with the exception of the deleted one
3736 * and of the permanent MAC address.
3738 for (i = 0, mac_addr = dev->data->mac_addrs;
3739 i < hw->mac.num_rar_entries; i++, mac_addr++) {
3740 /* Skip the deleted MAC address */
3743 /* Skip NULL MAC addresses */
3744 if (is_zero_ether_addr(mac_addr))
3746 /* Skip the permanent MAC address */
3747 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3749 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3752 "Adding again MAC address "
3753 "%02x:%02x:%02x:%02x:%02x:%02x failed "
3755 mac_addr->addr_bytes[0],
3756 mac_addr->addr_bytes[1],
3757 mac_addr->addr_bytes[2],
3758 mac_addr->addr_bytes[3],
3759 mac_addr->addr_bytes[4],
3760 mac_addr->addr_bytes[5],
3765 #define MAC_TYPE_FILTER_SUP(type) do {\
3766 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3767 (type) != ixgbe_mac_X550)\
3772 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3773 struct rte_eth_syn_filter *filter,
3776 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3779 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3782 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3785 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3787 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3788 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3790 if (filter->hig_pri)
3791 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3793 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3795 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3797 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3799 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3800 IXGBE_WRITE_FLUSH(hw);
3805 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3806 struct rte_eth_syn_filter *filter)
3808 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3809 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3811 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3812 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3813 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3820 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3821 enum rte_filter_op filter_op,
3824 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3827 MAC_TYPE_FILTER_SUP(hw->mac.type);
3829 if (filter_op == RTE_ETH_FILTER_NOP)
3833 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3838 switch (filter_op) {
3839 case RTE_ETH_FILTER_ADD:
3840 ret = ixgbe_syn_filter_set(dev,
3841 (struct rte_eth_syn_filter *)arg,
3844 case RTE_ETH_FILTER_DELETE:
3845 ret = ixgbe_syn_filter_set(dev,
3846 (struct rte_eth_syn_filter *)arg,
3849 case RTE_ETH_FILTER_GET:
3850 ret = ixgbe_syn_filter_get(dev,
3851 (struct rte_eth_syn_filter *)arg);
3854 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3863 static inline enum ixgbe_5tuple_protocol
3864 convert_protocol_type(uint8_t protocol_value)
3866 if (protocol_value == IPPROTO_TCP)
3867 return IXGBE_FILTER_PROTOCOL_TCP;
3868 else if (protocol_value == IPPROTO_UDP)
3869 return IXGBE_FILTER_PROTOCOL_UDP;
3870 else if (protocol_value == IPPROTO_SCTP)
3871 return IXGBE_FILTER_PROTOCOL_SCTP;
3873 return IXGBE_FILTER_PROTOCOL_NONE;
3877 * add a 5tuple filter
3880 * dev: Pointer to struct rte_eth_dev.
3881 * index: the index the filter allocates.
3882 * filter: ponter to the filter that will be added.
3883 * rx_queue: the queue id the filter assigned to.
3886 * - On success, zero.
3887 * - On failure, a negative value.
3890 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3891 struct ixgbe_5tuple_filter *filter)
3893 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3894 struct ixgbe_filter_info *filter_info =
3895 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3897 uint32_t ftqf, sdpqf;
3898 uint32_t l34timir = 0;
3899 uint8_t mask = 0xff;
3902 * look for an unused 5tuple filter index,
3903 * and insert the filter to list.
3905 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3906 idx = i / (sizeof(uint32_t) * NBBY);
3907 shift = i % (sizeof(uint32_t) * NBBY);
3908 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3909 filter_info->fivetuple_mask[idx] |= 1 << shift;
3911 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3917 if (i >= IXGBE_MAX_FTQF_FILTERS) {
3918 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3922 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3923 IXGBE_SDPQF_DSTPORT_SHIFT);
3924 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3926 ftqf = (uint32_t)(filter->filter_info.proto &
3927 IXGBE_FTQF_PROTOCOL_MASK);
3928 ftqf |= (uint32_t)((filter->filter_info.priority &
3929 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3930 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3931 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3932 if (filter->filter_info.dst_ip_mask == 0)
3933 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3934 if (filter->filter_info.src_port_mask == 0)
3935 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3936 if (filter->filter_info.dst_port_mask == 0)
3937 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3938 if (filter->filter_info.proto_mask == 0)
3939 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3940 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3941 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3942 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3944 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
3945 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
3946 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
3947 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
3949 l34timir |= IXGBE_L34T_IMIR_RESERVE;
3950 l34timir |= (uint32_t)(filter->queue <<
3951 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3952 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3957 * remove a 5tuple filter
3960 * dev: Pointer to struct rte_eth_dev.
3961 * filter: the pointer of the filter will be removed.
3964 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3965 struct ixgbe_5tuple_filter *filter)
3967 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3968 struct ixgbe_filter_info *filter_info =
3969 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3970 uint16_t index = filter->index;
3972 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3973 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3974 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3977 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3978 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3979 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3980 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3981 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3985 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3987 struct ixgbe_hw *hw;
3988 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3990 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3992 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3995 /* refuse mtu that requires the support of scattered packets when this
3996 * feature has not been enabled before. */
3997 if (!dev->data->scattered_rx &&
3998 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3999 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4003 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4004 * request of the version 2.0 of the mailbox API.
4005 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4006 * of the mailbox API.
4007 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4008 * prior to 3.11.33 which contains the following change:
4009 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4011 ixgbevf_rlpml_set_vf(hw, max_frame);
4013 /* update max frame size */
4014 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4018 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
4019 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4023 static inline struct ixgbe_5tuple_filter *
4024 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4025 struct ixgbe_5tuple_filter_info *key)
4027 struct ixgbe_5tuple_filter *it;
4029 TAILQ_FOREACH(it, filter_list, entries) {
4030 if (memcmp(key, &it->filter_info,
4031 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4038 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4040 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4041 struct ixgbe_5tuple_filter_info *filter_info)
4043 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4044 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4045 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4048 switch (filter->dst_ip_mask) {
4050 filter_info->dst_ip_mask = 0;
4051 filter_info->dst_ip = filter->dst_ip;
4054 filter_info->dst_ip_mask = 1;
4057 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4061 switch (filter->src_ip_mask) {
4063 filter_info->src_ip_mask = 0;
4064 filter_info->src_ip = filter->src_ip;
4067 filter_info->src_ip_mask = 1;
4070 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4074 switch (filter->dst_port_mask) {
4076 filter_info->dst_port_mask = 0;
4077 filter_info->dst_port = filter->dst_port;
4080 filter_info->dst_port_mask = 1;
4083 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4087 switch (filter->src_port_mask) {
4089 filter_info->src_port_mask = 0;
4090 filter_info->src_port = filter->src_port;
4093 filter_info->src_port_mask = 1;
4096 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4100 switch (filter->proto_mask) {
4102 filter_info->proto_mask = 0;
4103 filter_info->proto =
4104 convert_protocol_type(filter->proto);
4107 filter_info->proto_mask = 1;
4110 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4114 filter_info->priority = (uint8_t)filter->priority;
4119 * add or delete a ntuple filter
4122 * dev: Pointer to struct rte_eth_dev.
4123 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4124 * add: if true, add filter, if false, remove filter
4127 * - On success, zero.
4128 * - On failure, a negative value.
4131 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4132 struct rte_eth_ntuple_filter *ntuple_filter,
4135 struct ixgbe_filter_info *filter_info =
4136 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4137 struct ixgbe_5tuple_filter_info filter_5tuple;
4138 struct ixgbe_5tuple_filter *filter;
4141 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4142 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4146 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4147 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4151 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4153 if (filter != NULL && add) {
4154 PMD_DRV_LOG(ERR, "filter exists.");
4157 if (filter == NULL && !add) {
4158 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4163 filter = rte_zmalloc("ixgbe_5tuple_filter",
4164 sizeof(struct ixgbe_5tuple_filter), 0);
4167 (void)rte_memcpy(&filter->filter_info,
4169 sizeof(struct ixgbe_5tuple_filter_info));
4170 filter->queue = ntuple_filter->queue;
4171 ret = ixgbe_add_5tuple_filter(dev, filter);
4177 ixgbe_remove_5tuple_filter(dev, filter);
4183 * get a ntuple filter
4186 * dev: Pointer to struct rte_eth_dev.
4187 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4190 * - On success, zero.
4191 * - On failure, a negative value.
4194 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4195 struct rte_eth_ntuple_filter *ntuple_filter)
4197 struct ixgbe_filter_info *filter_info =
4198 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4199 struct ixgbe_5tuple_filter_info filter_5tuple;
4200 struct ixgbe_5tuple_filter *filter;
4203 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4204 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4208 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4209 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4213 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4215 if (filter == NULL) {
4216 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4219 ntuple_filter->queue = filter->queue;
4224 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4225 * @dev: pointer to rte_eth_dev structure
4226 * @filter_op:operation will be taken.
4227 * @arg: a pointer to specific structure corresponding to the filter_op
4230 * - On success, zero.
4231 * - On failure, a negative value.
4234 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4235 enum rte_filter_op filter_op,
4238 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4241 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4243 if (filter_op == RTE_ETH_FILTER_NOP)
4247 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4252 switch (filter_op) {
4253 case RTE_ETH_FILTER_ADD:
4254 ret = ixgbe_add_del_ntuple_filter(dev,
4255 (struct rte_eth_ntuple_filter *)arg,
4258 case RTE_ETH_FILTER_DELETE:
4259 ret = ixgbe_add_del_ntuple_filter(dev,
4260 (struct rte_eth_ntuple_filter *)arg,
4263 case RTE_ETH_FILTER_GET:
4264 ret = ixgbe_get_ntuple_filter(dev,
4265 (struct rte_eth_ntuple_filter *)arg);
4268 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4276 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4281 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4282 if (filter_info->ethertype_filters[i] == ethertype &&
4283 (filter_info->ethertype_mask & (1 << i)))
4290 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4295 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4296 if (!(filter_info->ethertype_mask & (1 << i))) {
4297 filter_info->ethertype_mask |= 1 << i;
4298 filter_info->ethertype_filters[i] = ethertype;
4306 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4309 if (idx >= IXGBE_MAX_ETQF_FILTERS)
4311 filter_info->ethertype_mask &= ~(1 << idx);
4312 filter_info->ethertype_filters[idx] = 0;
4317 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4318 struct rte_eth_ethertype_filter *filter,
4321 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4322 struct ixgbe_filter_info *filter_info =
4323 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4328 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4331 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4332 filter->ether_type == ETHER_TYPE_IPv6) {
4333 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4334 " ethertype filter.", filter->ether_type);
4338 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4339 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4342 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4343 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4347 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4348 if (ret >= 0 && add) {
4349 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4350 filter->ether_type);
4353 if (ret < 0 && !add) {
4354 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4355 filter->ether_type);
4360 ret = ixgbe_ethertype_filter_insert(filter_info,
4361 filter->ether_type);
4363 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4366 etqf = IXGBE_ETQF_FILTER_EN;
4367 etqf |= (uint32_t)filter->ether_type;
4368 etqs |= (uint32_t)((filter->queue <<
4369 IXGBE_ETQS_RX_QUEUE_SHIFT) &
4370 IXGBE_ETQS_RX_QUEUE);
4371 etqs |= IXGBE_ETQS_QUEUE_EN;
4373 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4377 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4378 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4379 IXGBE_WRITE_FLUSH(hw);
4385 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4386 struct rte_eth_ethertype_filter *filter)
4388 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4389 struct ixgbe_filter_info *filter_info =
4390 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4391 uint32_t etqf, etqs;
4394 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4396 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4397 filter->ether_type);
4401 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4402 if (etqf & IXGBE_ETQF_FILTER_EN) {
4403 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4404 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4406 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4407 IXGBE_ETQS_RX_QUEUE_SHIFT;
4414 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4415 * @dev: pointer to rte_eth_dev structure
4416 * @filter_op:operation will be taken.
4417 * @arg: a pointer to specific structure corresponding to the filter_op
4420 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4421 enum rte_filter_op filter_op,
4424 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4427 MAC_TYPE_FILTER_SUP(hw->mac.type);
4429 if (filter_op == RTE_ETH_FILTER_NOP)
4433 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4438 switch (filter_op) {
4439 case RTE_ETH_FILTER_ADD:
4440 ret = ixgbe_add_del_ethertype_filter(dev,
4441 (struct rte_eth_ethertype_filter *)arg,
4444 case RTE_ETH_FILTER_DELETE:
4445 ret = ixgbe_add_del_ethertype_filter(dev,
4446 (struct rte_eth_ethertype_filter *)arg,
4449 case RTE_ETH_FILTER_GET:
4450 ret = ixgbe_get_ethertype_filter(dev,
4451 (struct rte_eth_ethertype_filter *)arg);
4454 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4462 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4463 enum rte_filter_type filter_type,
4464 enum rte_filter_op filter_op,
4469 switch (filter_type) {
4470 case RTE_ETH_FILTER_NTUPLE:
4471 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4473 case RTE_ETH_FILTER_ETHERTYPE:
4474 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4476 case RTE_ETH_FILTER_SYN:
4477 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4479 case RTE_ETH_FILTER_FDIR:
4480 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4483 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4492 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
4493 u8 **mc_addr_ptr, u32 *vmdq)
4498 mc_addr = *mc_addr_ptr;
4499 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
4504 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4505 struct ether_addr *mc_addr_set,
4506 uint32_t nb_mc_addr)
4508 struct ixgbe_hw *hw;
4511 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4512 mc_addr_list = (u8 *)mc_addr_set;
4513 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4514 ixgbe_dev_addr_list_itr, TRUE);
4517 static struct rte_driver rte_ixgbe_driver = {
4519 .init = rte_ixgbe_pmd_init,
4522 static struct rte_driver rte_ixgbevf_driver = {
4524 .init = rte_ixgbevf_pmd_init,
4527 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4528 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);