4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
65 #include "ixgbe_logs.h"
66 #include "base/ixgbe_api.h"
67 #include "base/ixgbe_vf.h"
68 #include "base/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
72 #include "base/ixgbe_type.h"
73 #include "base/ixgbe_phy.h"
74 #include "ixgbe_regs.h"
76 #include "rte_pmd_ixgbe.h"
79 * High threshold controlling when to start sending XOFF frames. Must be at
80 * least 8 bytes less than receive packet buffer size. This value is in units
83 #define IXGBE_FC_HI 0x80
86 * Low threshold controlling when to start sending XON frames. This value is
87 * in units of 1024 bytes.
89 #define IXGBE_FC_LO 0x40
91 /* Default minimum inter-interrupt interval for EITR configuration */
92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
94 /* Timer value included in XOFF frames. */
95 #define IXGBE_FC_PAUSE 0x680
97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
98 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
99 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
101 #define IXGBE_MMW_SIZE_DEFAULT 0x4
102 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
103 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
106 * Default values for RX/TX configuration
108 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
109 #define IXGBE_DEFAULT_RX_PTHRESH 8
110 #define IXGBE_DEFAULT_RX_HTHRESH 8
111 #define IXGBE_DEFAULT_RX_WTHRESH 0
113 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
114 #define IXGBE_DEFAULT_TX_PTHRESH 32
115 #define IXGBE_DEFAULT_TX_HTHRESH 0
116 #define IXGBE_DEFAULT_TX_WTHRESH 0
117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
119 /* Bit shift and mask */
120 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
121 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
122 #define IXGBE_8_BIT_WIDTH CHAR_BIT
123 #define IXGBE_8_BIT_MASK UINT8_MAX
125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
129 #define IXGBE_HKEY_MAX_INDEX 10
131 /* Additional timesync values. */
132 #define NSEC_PER_SEC 1000000000L
133 #define IXGBE_INCVAL_10GB 0x66666666
134 #define IXGBE_INCVAL_1GB 0x40000000
135 #define IXGBE_INCVAL_100 0x50000000
136 #define IXGBE_INCVAL_SHIFT_10GB 28
137 #define IXGBE_INCVAL_SHIFT_1GB 24
138 #define IXGBE_INCVAL_SHIFT_100 21
139 #define IXGBE_INCVAL_SHIFT_82599 7
140 #define IXGBE_INCPER_SHIFT_82599 24
142 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
144 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
146 #define DEFAULT_ETAG_ETYPE 0x893f
147 #define IXGBE_ETAG_ETYPE 0x00005084
148 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
149 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
150 #define IXGBE_RAH_ADTYPE 0x40000000
151 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
152 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
155 #define IXGBE_QDE_STRIP_TAG 0x00000004
156 #define IXGBE_VTEICR_MASK 0x07
158 enum ixgbevf_xcast_modes {
159 IXGBEVF_XCAST_MODE_NONE = 0,
160 IXGBEVF_XCAST_MODE_MULTI,
161 IXGBEVF_XCAST_MODE_ALLMULTI,
164 #define IXGBE_EXVET_VET_EXT_SHIFT 16
165 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
167 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
168 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
169 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
170 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
171 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
172 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
173 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
174 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
175 static int ixgbe_dev_start(struct rte_eth_dev *dev);
176 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
177 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
178 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
179 static void ixgbe_dev_close(struct rte_eth_dev *dev);
180 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
181 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
182 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
183 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
184 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
185 int wait_to_complete);
186 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
187 struct rte_eth_stats *stats);
188 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
189 struct rte_eth_xstat *xstats, unsigned n);
190 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
191 struct rte_eth_xstat *xstats, unsigned n);
192 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
193 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
194 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
195 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
196 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
197 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
198 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
202 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
204 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
205 struct rte_eth_dev_info *dev_info);
206 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
207 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
208 struct rte_eth_dev_info *dev_info);
209 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
211 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
212 uint16_t vlan_id, int on);
213 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
214 enum rte_vlan_type vlan_type,
216 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
217 uint16_t queue, bool on);
218 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
220 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
221 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
222 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
223 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
224 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
226 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
227 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
228 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
229 struct rte_eth_fc_conf *fc_conf);
230 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
231 struct rte_eth_fc_conf *fc_conf);
232 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
233 struct rte_eth_pfc_conf *pfc_conf);
234 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
235 struct rte_eth_rss_reta_entry64 *reta_conf,
237 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
238 struct rte_eth_rss_reta_entry64 *reta_conf,
240 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
241 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
242 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
243 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
244 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
245 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
246 struct rte_intr_handle *handle);
247 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
250 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
251 uint32_t index, uint32_t pool);
252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
254 struct ether_addr *mac_addr);
255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
256 static int is_ixgbe_pmd(const char *driver_name);
258 /* For Virtual Function support */
259 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
260 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
261 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
262 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
263 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
264 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
265 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
266 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
267 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
268 struct rte_eth_stats *stats);
269 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
270 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
271 uint16_t vlan_id, int on);
272 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
273 uint16_t queue, int on);
274 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
275 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
276 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
278 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
280 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
281 uint8_t queue, uint8_t msix_vector);
282 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
283 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
284 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
286 /* For Eth VMDQ APIs support */
287 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
288 ether_addr * mac_addr, uint8_t on);
289 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
291 struct rte_eth_mirror_conf *mirror_conf,
292 uint8_t rule_id, uint8_t on);
293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
300 uint8_t queue, uint8_t msix_vector);
301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
304 uint16_t queue_idx, uint16_t tx_rate);
306 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
307 struct ether_addr *mac_addr,
308 uint32_t index, uint32_t pool);
309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
311 struct ether_addr *mac_addr);
312 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
313 struct rte_eth_syn_filter *filter);
314 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
315 enum rte_filter_op filter_op,
317 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
318 struct ixgbe_5tuple_filter *filter);
319 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
320 struct ixgbe_5tuple_filter *filter);
321 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
322 enum rte_filter_op filter_op,
324 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
325 struct rte_eth_ntuple_filter *filter);
326 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
327 enum rte_filter_op filter_op,
329 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
330 struct rte_eth_ethertype_filter *filter);
331 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
332 enum rte_filter_type filter_type,
333 enum rte_filter_op filter_op,
335 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
337 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
338 struct ether_addr *mc_addr_set,
339 uint32_t nb_mc_addr);
340 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
341 struct rte_eth_dcb_info *dcb_info);
343 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
344 static int ixgbe_get_regs(struct rte_eth_dev *dev,
345 struct rte_dev_reg_info *regs);
346 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
347 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
348 struct rte_dev_eeprom_info *eeprom);
349 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
350 struct rte_dev_eeprom_info *eeprom);
352 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
353 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
354 struct rte_dev_reg_info *regs);
356 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
357 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
358 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
359 struct timespec *timestamp,
361 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
362 struct timespec *timestamp);
363 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
364 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
365 struct timespec *timestamp);
366 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
367 const struct timespec *timestamp);
368 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
371 static int ixgbe_dev_l2_tunnel_eth_type_conf
372 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
373 static int ixgbe_dev_l2_tunnel_offload_set
374 (struct rte_eth_dev *dev,
375 struct rte_eth_l2_tunnel_conf *l2_tunnel,
378 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
379 enum rte_filter_op filter_op,
382 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
383 struct rte_eth_udp_tunnel *udp_tunnel);
384 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
385 struct rte_eth_udp_tunnel *udp_tunnel);
386 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
387 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
390 * Define VF Stats MACRO for Non "cleared on read" register
392 #define UPDATE_VF_STAT(reg, last, cur) \
394 uint32_t latest = IXGBE_READ_REG(hw, reg); \
395 cur += (latest - last) & UINT_MAX; \
399 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
401 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
402 u64 new_msb = IXGBE_READ_REG(hw, msb); \
403 u64 latest = ((new_msb << 32) | new_lsb); \
404 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
408 #define IXGBE_SET_HWSTRIP(h, q) do {\
409 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
410 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
411 (h)->bitmap[idx] |= 1 << bit;\
414 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
415 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
416 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
417 (h)->bitmap[idx] &= ~(1 << bit);\
420 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
421 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
422 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
423 (r) = (h)->bitmap[idx] >> bit & 1;\
427 * The set of PCI devices this driver supports
429 static const struct rte_pci_id pci_id_ixgbe_map[] = {
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
483 #ifdef RTE_NIC_BYPASS
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
486 { .vendor_id = 0, /* sentinel */ },
490 * The set of PCI devices this driver supports (for 82599 VF)
492 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
503 { .vendor_id = 0, /* sentinel */ },
506 static const struct rte_eth_desc_lim rx_desc_lim = {
507 .nb_max = IXGBE_MAX_RING_DESC,
508 .nb_min = IXGBE_MIN_RING_DESC,
509 .nb_align = IXGBE_RXD_ALIGN,
512 static const struct rte_eth_desc_lim tx_desc_lim = {
513 .nb_max = IXGBE_MAX_RING_DESC,
514 .nb_min = IXGBE_MIN_RING_DESC,
515 .nb_align = IXGBE_TXD_ALIGN,
516 .nb_seg_max = IXGBE_TX_MAX_SEG,
517 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
520 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
521 .dev_configure = ixgbe_dev_configure,
522 .dev_start = ixgbe_dev_start,
523 .dev_stop = ixgbe_dev_stop,
524 .dev_set_link_up = ixgbe_dev_set_link_up,
525 .dev_set_link_down = ixgbe_dev_set_link_down,
526 .dev_close = ixgbe_dev_close,
527 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
528 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
529 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
530 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
531 .link_update = ixgbe_dev_link_update,
532 .stats_get = ixgbe_dev_stats_get,
533 .xstats_get = ixgbe_dev_xstats_get,
534 .stats_reset = ixgbe_dev_stats_reset,
535 .xstats_reset = ixgbe_dev_xstats_reset,
536 .xstats_get_names = ixgbe_dev_xstats_get_names,
537 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
538 .fw_version_get = ixgbe_fw_version_get,
539 .dev_infos_get = ixgbe_dev_info_get,
540 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
541 .mtu_set = ixgbe_dev_mtu_set,
542 .vlan_filter_set = ixgbe_vlan_filter_set,
543 .vlan_tpid_set = ixgbe_vlan_tpid_set,
544 .vlan_offload_set = ixgbe_vlan_offload_set,
545 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
546 .rx_queue_start = ixgbe_dev_rx_queue_start,
547 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
548 .tx_queue_start = ixgbe_dev_tx_queue_start,
549 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
550 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
551 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
552 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
553 .rx_queue_release = ixgbe_dev_rx_queue_release,
554 .rx_queue_count = ixgbe_dev_rx_queue_count,
555 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
556 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
557 .tx_queue_release = ixgbe_dev_tx_queue_release,
558 .dev_led_on = ixgbe_dev_led_on,
559 .dev_led_off = ixgbe_dev_led_off,
560 .flow_ctrl_get = ixgbe_flow_ctrl_get,
561 .flow_ctrl_set = ixgbe_flow_ctrl_set,
562 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
563 .mac_addr_add = ixgbe_add_rar,
564 .mac_addr_remove = ixgbe_remove_rar,
565 .mac_addr_set = ixgbe_set_default_mac_addr,
566 .uc_hash_table_set = ixgbe_uc_hash_table_set,
567 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
568 .mirror_rule_set = ixgbe_mirror_rule_set,
569 .mirror_rule_reset = ixgbe_mirror_rule_reset,
570 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
571 .reta_update = ixgbe_dev_rss_reta_update,
572 .reta_query = ixgbe_dev_rss_reta_query,
573 #ifdef RTE_NIC_BYPASS
574 .bypass_init = ixgbe_bypass_init,
575 .bypass_state_set = ixgbe_bypass_state_store,
576 .bypass_state_show = ixgbe_bypass_state_show,
577 .bypass_event_set = ixgbe_bypass_event_store,
578 .bypass_event_show = ixgbe_bypass_event_show,
579 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
580 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
581 .bypass_ver_show = ixgbe_bypass_ver_show,
582 .bypass_wd_reset = ixgbe_bypass_wd_reset,
583 #endif /* RTE_NIC_BYPASS */
584 .rss_hash_update = ixgbe_dev_rss_hash_update,
585 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
586 .filter_ctrl = ixgbe_dev_filter_ctrl,
587 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
588 .rxq_info_get = ixgbe_rxq_info_get,
589 .txq_info_get = ixgbe_txq_info_get,
590 .timesync_enable = ixgbe_timesync_enable,
591 .timesync_disable = ixgbe_timesync_disable,
592 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
593 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
594 .get_reg = ixgbe_get_regs,
595 .get_eeprom_length = ixgbe_get_eeprom_length,
596 .get_eeprom = ixgbe_get_eeprom,
597 .set_eeprom = ixgbe_set_eeprom,
598 .get_dcb_info = ixgbe_dev_get_dcb_info,
599 .timesync_adjust_time = ixgbe_timesync_adjust_time,
600 .timesync_read_time = ixgbe_timesync_read_time,
601 .timesync_write_time = ixgbe_timesync_write_time,
602 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
603 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
604 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
605 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
609 * dev_ops for virtual function, bare necessities for basic vf
610 * operation have been implemented
612 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
613 .dev_configure = ixgbevf_dev_configure,
614 .dev_start = ixgbevf_dev_start,
615 .dev_stop = ixgbevf_dev_stop,
616 .link_update = ixgbe_dev_link_update,
617 .stats_get = ixgbevf_dev_stats_get,
618 .xstats_get = ixgbevf_dev_xstats_get,
619 .stats_reset = ixgbevf_dev_stats_reset,
620 .xstats_reset = ixgbevf_dev_stats_reset,
621 .xstats_get_names = ixgbevf_dev_xstats_get_names,
622 .dev_close = ixgbevf_dev_close,
623 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
624 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
625 .dev_infos_get = ixgbevf_dev_info_get,
626 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
627 .mtu_set = ixgbevf_dev_set_mtu,
628 .vlan_filter_set = ixgbevf_vlan_filter_set,
629 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
630 .vlan_offload_set = ixgbevf_vlan_offload_set,
631 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
632 .rx_queue_release = ixgbe_dev_rx_queue_release,
633 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
634 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
635 .tx_queue_release = ixgbe_dev_tx_queue_release,
636 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
637 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
638 .mac_addr_add = ixgbevf_add_mac_addr,
639 .mac_addr_remove = ixgbevf_remove_mac_addr,
640 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
641 .rxq_info_get = ixgbe_rxq_info_get,
642 .txq_info_get = ixgbe_txq_info_get,
643 .mac_addr_set = ixgbevf_set_default_mac_addr,
644 .get_reg = ixgbevf_get_regs,
645 .reta_update = ixgbe_dev_rss_reta_update,
646 .reta_query = ixgbe_dev_rss_reta_query,
647 .rss_hash_update = ixgbe_dev_rss_hash_update,
648 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
651 /* store statistics names and its offset in stats structure */
652 struct rte_ixgbe_xstats_name_off {
653 char name[RTE_ETH_XSTATS_NAME_SIZE];
657 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
658 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
659 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
660 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
661 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
662 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
663 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
664 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
665 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
666 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
667 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
668 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
669 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
670 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
671 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
672 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
674 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
676 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
677 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
678 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
679 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
680 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
681 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
682 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
683 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
684 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
685 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
686 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
687 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
688 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
689 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
690 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
691 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
692 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
694 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
696 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
697 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
698 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
699 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
701 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
703 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
705 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
707 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
709 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
711 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
714 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
715 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
716 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
718 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
719 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
720 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
721 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
722 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
724 {"rx_fcoe_no_direct_data_placement_ext_buff",
725 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
727 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
729 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
731 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
733 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
735 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
738 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
739 sizeof(rte_ixgbe_stats_strings[0]))
741 /* MACsec statistics */
742 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
743 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
745 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
746 out_pkts_encrypted)},
747 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
748 out_pkts_protected)},
749 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
750 out_octets_encrypted)},
751 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
752 out_octets_protected)},
753 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
755 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
757 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
759 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
760 in_pkts_unknownsci)},
761 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
762 in_octets_decrypted)},
763 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
764 in_octets_validated)},
765 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
769 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
771 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
773 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
775 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
777 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
779 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
780 in_pkts_notusingsa)},
783 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
784 sizeof(rte_ixgbe_macsec_strings[0]))
786 /* Per-queue statistics */
787 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
788 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
789 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
790 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
791 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
794 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
795 sizeof(rte_ixgbe_rxq_strings[0]))
796 #define IXGBE_NB_RXQ_PRIO_VALUES 8
798 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
799 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
800 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
801 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
805 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
806 sizeof(rte_ixgbe_txq_strings[0]))
807 #define IXGBE_NB_TXQ_PRIO_VALUES 8
809 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
810 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
813 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
814 sizeof(rte_ixgbevf_stats_strings[0]))
817 * Atomically reads the link status information from global
818 * structure rte_eth_dev.
821 * - Pointer to the structure rte_eth_dev to read from.
822 * - Pointer to the buffer to be saved with the link status.
825 * - On success, zero.
826 * - On failure, negative value.
829 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
830 struct rte_eth_link *link)
832 struct rte_eth_link *dst = link;
833 struct rte_eth_link *src = &(dev->data->dev_link);
835 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
836 *(uint64_t *)src) == 0)
843 * Atomically writes the link status information into global
844 * structure rte_eth_dev.
847 * - Pointer to the structure rte_eth_dev to read from.
848 * - Pointer to the buffer to be saved with the link status.
851 * - On success, zero.
852 * - On failure, negative value.
855 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
856 struct rte_eth_link *link)
858 struct rte_eth_link *dst = &(dev->data->dev_link);
859 struct rte_eth_link *src = link;
861 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
862 *(uint64_t *)src) == 0)
869 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
872 ixgbe_is_sfp(struct ixgbe_hw *hw)
874 switch (hw->phy.type) {
875 case ixgbe_phy_sfp_avago:
876 case ixgbe_phy_sfp_ftl:
877 case ixgbe_phy_sfp_intel:
878 case ixgbe_phy_sfp_unknown:
879 case ixgbe_phy_sfp_passive_tyco:
880 case ixgbe_phy_sfp_passive_unknown:
887 static inline int32_t
888 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
893 status = ixgbe_reset_hw(hw);
895 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
896 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
897 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
898 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
899 IXGBE_WRITE_FLUSH(hw);
905 ixgbe_enable_intr(struct rte_eth_dev *dev)
907 struct ixgbe_interrupt *intr =
908 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
909 struct ixgbe_hw *hw =
910 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
912 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
913 IXGBE_WRITE_FLUSH(hw);
917 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
920 ixgbe_disable_intr(struct ixgbe_hw *hw)
922 PMD_INIT_FUNC_TRACE();
924 if (hw->mac.type == ixgbe_mac_82598EB) {
925 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
927 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
928 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
929 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
931 IXGBE_WRITE_FLUSH(hw);
935 * This function resets queue statistics mapping registers.
936 * From Niantic datasheet, Initialization of Statistics section:
937 * "...if software requires the queue counters, the RQSMR and TQSM registers
938 * must be re-programmed following a device reset.
941 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
945 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
946 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
947 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
953 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
958 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
959 #define NB_QMAP_FIELDS_PER_QSM_REG 4
960 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
962 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
963 struct ixgbe_stat_mapping_registers *stat_mappings =
964 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
965 uint32_t qsmr_mask = 0;
966 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
970 if ((hw->mac.type != ixgbe_mac_82599EB) &&
971 (hw->mac.type != ixgbe_mac_X540) &&
972 (hw->mac.type != ixgbe_mac_X550) &&
973 (hw->mac.type != ixgbe_mac_X550EM_x) &&
974 (hw->mac.type != ixgbe_mac_X550EM_a))
977 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
978 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
981 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
982 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
983 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
986 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
988 /* Now clear any previous stat_idx set */
989 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
991 stat_mappings->tqsm[n] &= ~clearing_mask;
993 stat_mappings->rqsmr[n] &= ~clearing_mask;
995 q_map = (uint32_t)stat_idx;
996 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
997 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
999 stat_mappings->tqsm[n] |= qsmr_mask;
1001 stat_mappings->rqsmr[n] |= qsmr_mask;
1003 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1004 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1005 queue_id, stat_idx);
1006 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1007 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1009 /* Now write the mapping in the appropriate register */
1011 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1012 stat_mappings->rqsmr[n], n);
1013 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1015 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1016 stat_mappings->tqsm[n], n);
1017 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1023 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1025 struct ixgbe_stat_mapping_registers *stat_mappings =
1026 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1027 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030 /* write whatever was in stat mapping table to the NIC */
1031 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1033 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1036 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1041 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1044 struct ixgbe_dcb_tc_config *tc;
1045 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1047 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1048 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1049 for (i = 0; i < dcb_max_tc; i++) {
1050 tc = &dcb_config->tc_config[i];
1051 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1052 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1053 (uint8_t)(100/dcb_max_tc + (i & 1));
1054 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1055 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1056 (uint8_t)(100/dcb_max_tc + (i & 1));
1057 tc->pfc = ixgbe_dcb_pfc_disabled;
1060 /* Initialize default user to priority mapping, UPx->TC0 */
1061 tc = &dcb_config->tc_config[0];
1062 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1063 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1064 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1065 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1066 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1068 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1069 dcb_config->pfc_mode_enable = false;
1070 dcb_config->vt_mode = true;
1071 dcb_config->round_robin_enable = false;
1072 /* support all DCB capabilities in 82599 */
1073 dcb_config->support.capabilities = 0xFF;
1075 /*we only support 4 Tcs for X540, X550 */
1076 if (hw->mac.type == ixgbe_mac_X540 ||
1077 hw->mac.type == ixgbe_mac_X550 ||
1078 hw->mac.type == ixgbe_mac_X550EM_x ||
1079 hw->mac.type == ixgbe_mac_X550EM_a) {
1080 dcb_config->num_tcs.pg_tcs = 4;
1081 dcb_config->num_tcs.pfc_tcs = 4;
1086 * Ensure that all locks are released before first NVM or PHY access
1089 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1094 * Phy lock should not fail in this early stage. If this is the case,
1095 * it is due to an improper exit of the application.
1096 * So force the release of the faulty lock. Release of common lock
1097 * is done automatically by swfw_sync function.
1099 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1100 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1101 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1103 ixgbe_release_swfw_semaphore(hw, mask);
1106 * These ones are more tricky since they are common to all ports; but
1107 * swfw_sync retries last long enough (1s) to be almost sure that if
1108 * lock can not be taken it is due to an improper lock of the
1111 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1112 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1113 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1115 ixgbe_release_swfw_semaphore(hw, mask);
1119 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1120 * It returns 0 on success.
1123 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1125 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1126 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1127 struct ixgbe_hw *hw =
1128 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1129 struct ixgbe_vfta *shadow_vfta =
1130 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1131 struct ixgbe_hwstrip *hwstrip =
1132 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1133 struct ixgbe_dcb_config *dcb_config =
1134 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1135 struct ixgbe_filter_info *filter_info =
1136 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1141 PMD_INIT_FUNC_TRACE();
1143 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1144 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1145 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1146 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1149 * For secondary processes, we don't initialise any further as primary
1150 * has already done this work. Only check we don't need a different
1151 * RX and TX function.
1153 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1154 struct ixgbe_tx_queue *txq;
1155 /* TX queue function in primary, set by last queue initialized
1156 * Tx queue may not initialized by primary process
1158 if (eth_dev->data->tx_queues) {
1159 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1160 ixgbe_set_tx_function(eth_dev, txq);
1162 /* Use default TX function if we get here */
1163 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1164 "Using default TX function.");
1167 ixgbe_set_rx_function(eth_dev);
1172 rte_eth_copy_pci_info(eth_dev, pci_dev);
1173 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1175 /* Vendor and Device ID need to be set before init of shared code */
1176 hw->device_id = pci_dev->id.device_id;
1177 hw->vendor_id = pci_dev->id.vendor_id;
1178 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1179 hw->allow_unsupported_sfp = 1;
1181 /* Initialize the shared code (base driver) */
1182 #ifdef RTE_NIC_BYPASS
1183 diag = ixgbe_bypass_init_shared_code(hw);
1185 diag = ixgbe_init_shared_code(hw);
1186 #endif /* RTE_NIC_BYPASS */
1188 if (diag != IXGBE_SUCCESS) {
1189 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1193 /* pick up the PCI bus settings for reporting later */
1194 ixgbe_get_bus_info(hw);
1196 /* Unlock any pending hardware semaphore */
1197 ixgbe_swfw_lock_reset(hw);
1199 /* Initialize DCB configuration*/
1200 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1201 ixgbe_dcb_init(hw, dcb_config);
1202 /* Get Hardware Flow Control setting */
1203 hw->fc.requested_mode = ixgbe_fc_full;
1204 hw->fc.current_mode = ixgbe_fc_full;
1205 hw->fc.pause_time = IXGBE_FC_PAUSE;
1206 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1207 hw->fc.low_water[i] = IXGBE_FC_LO;
1208 hw->fc.high_water[i] = IXGBE_FC_HI;
1210 hw->fc.send_xon = 1;
1212 /* Make sure we have a good EEPROM before we read from it */
1213 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1214 if (diag != IXGBE_SUCCESS) {
1215 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1219 #ifdef RTE_NIC_BYPASS
1220 diag = ixgbe_bypass_init_hw(hw);
1222 diag = ixgbe_init_hw(hw);
1223 #endif /* RTE_NIC_BYPASS */
1226 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1227 * is called too soon after the kernel driver unbinding/binding occurs.
1228 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1229 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1230 * also called. See ixgbe_identify_phy_82599(). The reason for the
1231 * failure is not known, and only occuts when virtualisation features
1232 * are disabled in the bios. A delay of 100ms was found to be enough by
1233 * trial-and-error, and is doubled to be safe.
1235 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1237 diag = ixgbe_init_hw(hw);
1240 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1241 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1242 "LOM. Please be aware there may be issues associated "
1243 "with your hardware.");
1244 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1245 "please contact your Intel or hardware representative "
1246 "who provided you with this hardware.");
1247 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1248 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1250 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1254 /* Reset the hw statistics */
1255 ixgbe_dev_stats_reset(eth_dev);
1257 /* disable interrupt */
1258 ixgbe_disable_intr(hw);
1260 /* reset mappings for queue statistics hw counters*/
1261 ixgbe_reset_qstat_mappings(hw);
1263 /* Allocate memory for storing MAC addresses */
1264 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1265 hw->mac.num_rar_entries, 0);
1266 if (eth_dev->data->mac_addrs == NULL) {
1268 "Failed to allocate %u bytes needed to store "
1270 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1273 /* Copy the permanent MAC address */
1274 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1275 ð_dev->data->mac_addrs[0]);
1277 /* Allocate memory for storing hash filter MAC addresses */
1278 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1279 IXGBE_VMDQ_NUM_UC_MAC, 0);
1280 if (eth_dev->data->hash_mac_addrs == NULL) {
1282 "Failed to allocate %d bytes needed to store MAC addresses",
1283 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1287 /* initialize the vfta */
1288 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1290 /* initialize the hw strip bitmap*/
1291 memset(hwstrip, 0, sizeof(*hwstrip));
1293 /* initialize PF if max_vfs not zero */
1294 ixgbe_pf_host_init(eth_dev);
1296 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1297 /* let hardware know driver is loaded */
1298 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1299 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1300 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1301 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1302 IXGBE_WRITE_FLUSH(hw);
1304 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1305 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1306 (int) hw->mac.type, (int) hw->phy.type,
1307 (int) hw->phy.sfp_type);
1309 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1310 (int) hw->mac.type, (int) hw->phy.type);
1312 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1313 eth_dev->data->port_id, pci_dev->id.vendor_id,
1314 pci_dev->id.device_id);
1316 rte_intr_callback_register(intr_handle,
1317 ixgbe_dev_interrupt_handler, eth_dev);
1319 /* enable uio/vfio intr/eventfd mapping */
1320 rte_intr_enable(intr_handle);
1322 /* enable support intr */
1323 ixgbe_enable_intr(eth_dev);
1325 /* initialize filter info */
1326 memset(filter_info, 0,
1327 sizeof(struct ixgbe_filter_info));
1329 /* initialize 5tuple filter list */
1330 TAILQ_INIT(&filter_info->fivetuple_list);
1332 /* initialize flow director filter list & hash */
1333 ixgbe_fdir_filter_init(eth_dev);
1335 /* initialize l2 tunnel filter list & hash */
1336 ixgbe_l2_tn_filter_init(eth_dev);
1338 TAILQ_INIT(&filter_ntuple_list);
1339 TAILQ_INIT(&filter_ethertype_list);
1340 TAILQ_INIT(&filter_syn_list);
1341 TAILQ_INIT(&filter_fdir_list);
1342 TAILQ_INIT(&filter_l2_tunnel_list);
1343 TAILQ_INIT(&ixgbe_flow_list);
1349 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1351 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1352 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1353 struct ixgbe_hw *hw;
1355 PMD_INIT_FUNC_TRACE();
1357 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1360 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1362 if (hw->adapter_stopped == 0)
1363 ixgbe_dev_close(eth_dev);
1365 eth_dev->dev_ops = NULL;
1366 eth_dev->rx_pkt_burst = NULL;
1367 eth_dev->tx_pkt_burst = NULL;
1369 /* Unlock any pending hardware semaphore */
1370 ixgbe_swfw_lock_reset(hw);
1372 /* disable uio intr before callback unregister */
1373 rte_intr_disable(intr_handle);
1374 rte_intr_callback_unregister(intr_handle,
1375 ixgbe_dev_interrupt_handler, eth_dev);
1377 /* uninitialize PF if max_vfs not zero */
1378 ixgbe_pf_host_uninit(eth_dev);
1380 rte_free(eth_dev->data->mac_addrs);
1381 eth_dev->data->mac_addrs = NULL;
1383 rte_free(eth_dev->data->hash_mac_addrs);
1384 eth_dev->data->hash_mac_addrs = NULL;
1386 /* remove all the fdir filters & hash */
1387 ixgbe_fdir_filter_uninit(eth_dev);
1389 /* remove all the L2 tunnel filters & hash */
1390 ixgbe_l2_tn_filter_uninit(eth_dev);
1392 /* Remove all ntuple filters of the device */
1393 ixgbe_ntuple_filter_uninit(eth_dev);
1395 /* clear all the filters list */
1396 ixgbe_filterlist_flush();
1401 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1403 struct ixgbe_filter_info *filter_info =
1404 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1405 struct ixgbe_5tuple_filter *p_5tuple;
1407 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1408 TAILQ_REMOVE(&filter_info->fivetuple_list,
1413 memset(filter_info->fivetuple_mask, 0,
1414 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1419 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1421 struct ixgbe_hw_fdir_info *fdir_info =
1422 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1423 struct ixgbe_fdir_filter *fdir_filter;
1425 if (fdir_info->hash_map)
1426 rte_free(fdir_info->hash_map);
1427 if (fdir_info->hash_handle)
1428 rte_hash_free(fdir_info->hash_handle);
1430 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1431 TAILQ_REMOVE(&fdir_info->fdir_list,
1434 rte_free(fdir_filter);
1440 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1442 struct ixgbe_l2_tn_info *l2_tn_info =
1443 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1444 struct ixgbe_l2_tn_filter *l2_tn_filter;
1446 if (l2_tn_info->hash_map)
1447 rte_free(l2_tn_info->hash_map);
1448 if (l2_tn_info->hash_handle)
1449 rte_hash_free(l2_tn_info->hash_handle);
1451 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1452 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1455 rte_free(l2_tn_filter);
1461 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1463 struct ixgbe_hw_fdir_info *fdir_info =
1464 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1465 char fdir_hash_name[RTE_HASH_NAMESIZE];
1466 struct rte_hash_parameters fdir_hash_params = {
1467 .name = fdir_hash_name,
1468 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1469 .key_len = sizeof(union ixgbe_atr_input),
1470 .hash_func = rte_hash_crc,
1471 .hash_func_init_val = 0,
1472 .socket_id = rte_socket_id(),
1475 TAILQ_INIT(&fdir_info->fdir_list);
1476 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1477 "fdir_%s", eth_dev->data->name);
1478 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1479 if (!fdir_info->hash_handle) {
1480 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1483 fdir_info->hash_map = rte_zmalloc("ixgbe",
1484 sizeof(struct ixgbe_fdir_filter *) *
1485 IXGBE_MAX_FDIR_FILTER_NUM,
1487 if (!fdir_info->hash_map) {
1489 "Failed to allocate memory for fdir hash map!");
1492 fdir_info->mask_added = FALSE;
1497 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1499 struct ixgbe_l2_tn_info *l2_tn_info =
1500 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1501 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1502 struct rte_hash_parameters l2_tn_hash_params = {
1503 .name = l2_tn_hash_name,
1504 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1505 .key_len = sizeof(struct ixgbe_l2_tn_key),
1506 .hash_func = rte_hash_crc,
1507 .hash_func_init_val = 0,
1508 .socket_id = rte_socket_id(),
1511 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1512 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1513 "l2_tn_%s", eth_dev->data->name);
1514 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1515 if (!l2_tn_info->hash_handle) {
1516 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1519 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1520 sizeof(struct ixgbe_l2_tn_filter *) *
1521 IXGBE_MAX_L2_TN_FILTER_NUM,
1523 if (!l2_tn_info->hash_map) {
1525 "Failed to allocate memory for L2 TN hash map!");
1528 l2_tn_info->e_tag_en = FALSE;
1529 l2_tn_info->e_tag_fwd_en = FALSE;
1530 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1535 * Negotiate mailbox API version with the PF.
1536 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1537 * Then we try to negotiate starting with the most recent one.
1538 * If all negotiation attempts fail, then we will proceed with
1539 * the default one (ixgbe_mbox_api_10).
1542 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1546 /* start with highest supported, proceed down */
1547 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1554 i != RTE_DIM(sup_ver) &&
1555 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1561 generate_random_mac_addr(struct ether_addr *mac_addr)
1565 /* Set Organizationally Unique Identifier (OUI) prefix. */
1566 mac_addr->addr_bytes[0] = 0x00;
1567 mac_addr->addr_bytes[1] = 0x09;
1568 mac_addr->addr_bytes[2] = 0xC0;
1569 /* Force indication of locally assigned MAC address. */
1570 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1571 /* Generate the last 3 bytes of the MAC address with a random number. */
1572 random = rte_rand();
1573 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1577 * Virtual Function device init
1580 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1584 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1585 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1586 struct ixgbe_hw *hw =
1587 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1588 struct ixgbe_vfta *shadow_vfta =
1589 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1590 struct ixgbe_hwstrip *hwstrip =
1591 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1592 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1594 PMD_INIT_FUNC_TRACE();
1596 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1597 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1598 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1600 /* for secondary processes, we don't initialise any further as primary
1601 * has already done this work. Only check we don't need a different
1604 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1605 struct ixgbe_tx_queue *txq;
1606 /* TX queue function in primary, set by last queue initialized
1607 * Tx queue may not initialized by primary process
1609 if (eth_dev->data->tx_queues) {
1610 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1611 ixgbe_set_tx_function(eth_dev, txq);
1613 /* Use default TX function if we get here */
1614 PMD_INIT_LOG(NOTICE,
1615 "No TX queues configured yet. Using default TX function.");
1618 ixgbe_set_rx_function(eth_dev);
1623 rte_eth_copy_pci_info(eth_dev, pci_dev);
1624 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1626 hw->device_id = pci_dev->id.device_id;
1627 hw->vendor_id = pci_dev->id.vendor_id;
1628 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1630 /* initialize the vfta */
1631 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1633 /* initialize the hw strip bitmap*/
1634 memset(hwstrip, 0, sizeof(*hwstrip));
1636 /* Initialize the shared code (base driver) */
1637 diag = ixgbe_init_shared_code(hw);
1638 if (diag != IXGBE_SUCCESS) {
1639 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1643 /* init_mailbox_params */
1644 hw->mbx.ops.init_params(hw);
1646 /* Reset the hw statistics */
1647 ixgbevf_dev_stats_reset(eth_dev);
1649 /* Disable the interrupts for VF */
1650 ixgbevf_intr_disable(hw);
1652 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1653 diag = hw->mac.ops.reset_hw(hw);
1656 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1657 * the underlying PF driver has not assigned a MAC address to the VF.
1658 * In this case, assign a random MAC address.
1660 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1661 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1665 /* negotiate mailbox API version to use with the PF. */
1666 ixgbevf_negotiate_api(hw);
1668 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1669 ixgbevf_get_queues(hw, &tcs, &tc);
1671 /* Allocate memory for storing MAC addresses */
1672 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1673 hw->mac.num_rar_entries, 0);
1674 if (eth_dev->data->mac_addrs == NULL) {
1676 "Failed to allocate %u bytes needed to store "
1678 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1682 /* Generate a random MAC address, if none was assigned by PF. */
1683 if (is_zero_ether_addr(perm_addr)) {
1684 generate_random_mac_addr(perm_addr);
1685 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1687 rte_free(eth_dev->data->mac_addrs);
1688 eth_dev->data->mac_addrs = NULL;
1691 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1692 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1693 "%02x:%02x:%02x:%02x:%02x:%02x",
1694 perm_addr->addr_bytes[0],
1695 perm_addr->addr_bytes[1],
1696 perm_addr->addr_bytes[2],
1697 perm_addr->addr_bytes[3],
1698 perm_addr->addr_bytes[4],
1699 perm_addr->addr_bytes[5]);
1702 /* Copy the permanent MAC address */
1703 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1705 /* reset the hardware with the new settings */
1706 diag = hw->mac.ops.start_hw(hw);
1712 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1716 rte_intr_callback_register(intr_handle,
1717 ixgbevf_dev_interrupt_handler, eth_dev);
1718 rte_intr_enable(intr_handle);
1719 ixgbevf_intr_enable(hw);
1721 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1722 eth_dev->data->port_id, pci_dev->id.vendor_id,
1723 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1728 /* Virtual Function device uninit */
1731 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1733 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1734 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1735 struct ixgbe_hw *hw;
1737 PMD_INIT_FUNC_TRACE();
1739 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1742 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1744 if (hw->adapter_stopped == 0)
1745 ixgbevf_dev_close(eth_dev);
1747 eth_dev->dev_ops = NULL;
1748 eth_dev->rx_pkt_burst = NULL;
1749 eth_dev->tx_pkt_burst = NULL;
1751 /* Disable the interrupts for VF */
1752 ixgbevf_intr_disable(hw);
1754 rte_free(eth_dev->data->mac_addrs);
1755 eth_dev->data->mac_addrs = NULL;
1757 rte_intr_disable(intr_handle);
1758 rte_intr_callback_unregister(intr_handle,
1759 ixgbevf_dev_interrupt_handler, eth_dev);
1764 static struct eth_driver rte_ixgbe_pmd = {
1766 .id_table = pci_id_ixgbe_map,
1767 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1768 .probe = rte_eth_dev_pci_probe,
1769 .remove = rte_eth_dev_pci_remove,
1771 .eth_dev_init = eth_ixgbe_dev_init,
1772 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1773 .dev_private_size = sizeof(struct ixgbe_adapter),
1777 * virtual function driver struct
1779 static struct eth_driver rte_ixgbevf_pmd = {
1781 .id_table = pci_id_ixgbevf_map,
1782 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1783 .probe = rte_eth_dev_pci_probe,
1784 .remove = rte_eth_dev_pci_remove,
1786 .eth_dev_init = eth_ixgbevf_dev_init,
1787 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1788 .dev_private_size = sizeof(struct ixgbe_adapter),
1792 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1794 struct ixgbe_hw *hw =
1795 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796 struct ixgbe_vfta *shadow_vfta =
1797 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1802 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1803 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1804 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1809 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1811 /* update local VFTA copy */
1812 shadow_vfta->vfta[vid_idx] = vfta;
1818 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1821 ixgbe_vlan_hw_strip_enable(dev, queue);
1823 ixgbe_vlan_hw_strip_disable(dev, queue);
1827 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1828 enum rte_vlan_type vlan_type,
1831 struct ixgbe_hw *hw =
1832 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1838 qinq &= IXGBE_DMATXCTL_GDV;
1840 switch (vlan_type) {
1841 case ETH_VLAN_TYPE_INNER:
1843 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1844 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1845 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1846 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1847 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1848 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1849 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1852 PMD_DRV_LOG(ERR, "Inner type is not supported"
1856 case ETH_VLAN_TYPE_OUTER:
1858 /* Only the high 16-bits is valid */
1859 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1860 IXGBE_EXVET_VET_EXT_SHIFT);
1862 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1863 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1864 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1865 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1866 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1867 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1868 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1874 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1882 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1884 struct ixgbe_hw *hw =
1885 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1888 PMD_INIT_FUNC_TRACE();
1890 /* Filter Table Disable */
1891 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1892 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1894 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1898 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1900 struct ixgbe_hw *hw =
1901 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1902 struct ixgbe_vfta *shadow_vfta =
1903 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1907 PMD_INIT_FUNC_TRACE();
1909 /* Filter Table Enable */
1910 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1911 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1912 vlnctrl |= IXGBE_VLNCTRL_VFE;
1914 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1916 /* write whatever is in local vfta copy */
1917 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1918 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1922 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1924 struct ixgbe_hwstrip *hwstrip =
1925 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1926 struct ixgbe_rx_queue *rxq;
1928 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1932 IXGBE_SET_HWSTRIP(hwstrip, queue);
1934 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1936 if (queue >= dev->data->nb_rx_queues)
1939 rxq = dev->data->rx_queues[queue];
1942 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1944 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1948 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1950 struct ixgbe_hw *hw =
1951 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1954 PMD_INIT_FUNC_TRACE();
1956 if (hw->mac.type == ixgbe_mac_82598EB) {
1957 /* No queue level support */
1958 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1962 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1963 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1964 ctrl &= ~IXGBE_RXDCTL_VME;
1965 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1967 /* record those setting for HW strip per queue */
1968 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1972 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1974 struct ixgbe_hw *hw =
1975 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978 PMD_INIT_FUNC_TRACE();
1980 if (hw->mac.type == ixgbe_mac_82598EB) {
1981 /* No queue level supported */
1982 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1986 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1987 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1988 ctrl |= IXGBE_RXDCTL_VME;
1989 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1991 /* record those setting for HW strip per queue */
1992 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1996 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1998 struct ixgbe_hw *hw =
1999 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2002 struct ixgbe_rx_queue *rxq;
2004 PMD_INIT_FUNC_TRACE();
2006 if (hw->mac.type == ixgbe_mac_82598EB) {
2007 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2008 ctrl &= ~IXGBE_VLNCTRL_VME;
2009 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2011 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2012 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2013 rxq = dev->data->rx_queues[i];
2014 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2015 ctrl &= ~IXGBE_RXDCTL_VME;
2016 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2018 /* record those setting for HW strip per queue */
2019 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2025 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2027 struct ixgbe_hw *hw =
2028 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031 struct ixgbe_rx_queue *rxq;
2033 PMD_INIT_FUNC_TRACE();
2035 if (hw->mac.type == ixgbe_mac_82598EB) {
2036 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2037 ctrl |= IXGBE_VLNCTRL_VME;
2038 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2040 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2041 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2042 rxq = dev->data->rx_queues[i];
2043 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2044 ctrl |= IXGBE_RXDCTL_VME;
2045 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2047 /* record those setting for HW strip per queue */
2048 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2054 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2056 struct ixgbe_hw *hw =
2057 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060 PMD_INIT_FUNC_TRACE();
2062 /* DMATXCTRL: Geric Double VLAN Disable */
2063 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2064 ctrl &= ~IXGBE_DMATXCTL_GDV;
2065 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2067 /* CTRL_EXT: Global Double VLAN Disable */
2068 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2069 ctrl &= ~IXGBE_EXTENDED_VLAN;
2070 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2075 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2077 struct ixgbe_hw *hw =
2078 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2081 PMD_INIT_FUNC_TRACE();
2083 /* DMATXCTRL: Geric Double VLAN Enable */
2084 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2085 ctrl |= IXGBE_DMATXCTL_GDV;
2086 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2088 /* CTRL_EXT: Global Double VLAN Enable */
2089 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2090 ctrl |= IXGBE_EXTENDED_VLAN;
2091 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2093 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2094 if (hw->mac.type == ixgbe_mac_X550 ||
2095 hw->mac.type == ixgbe_mac_X550EM_x ||
2096 hw->mac.type == ixgbe_mac_X550EM_a) {
2097 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2098 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2099 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2103 * VET EXT field in the EXVET register = 0x8100 by default
2104 * So no need to change. Same to VT field of DMATXCTL register
2109 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2111 if (mask & ETH_VLAN_STRIP_MASK) {
2112 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2113 ixgbe_vlan_hw_strip_enable_all(dev);
2115 ixgbe_vlan_hw_strip_disable_all(dev);
2118 if (mask & ETH_VLAN_FILTER_MASK) {
2119 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2120 ixgbe_vlan_hw_filter_enable(dev);
2122 ixgbe_vlan_hw_filter_disable(dev);
2125 if (mask & ETH_VLAN_EXTEND_MASK) {
2126 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2127 ixgbe_vlan_hw_extend_enable(dev);
2129 ixgbe_vlan_hw_extend_disable(dev);
2134 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2136 struct ixgbe_hw *hw =
2137 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2138 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2139 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2141 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2142 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2146 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2148 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2153 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2156 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2162 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2163 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2169 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2171 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2172 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2174 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2176 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2177 /* check multi-queue mode */
2178 switch (dev_conf->rxmode.mq_mode) {
2179 case ETH_MQ_RX_VMDQ_DCB:
2180 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2182 case ETH_MQ_RX_VMDQ_DCB_RSS:
2183 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2184 PMD_INIT_LOG(ERR, "SRIOV active,"
2185 " unsupported mq_mode rx %d.",
2186 dev_conf->rxmode.mq_mode);
2189 case ETH_MQ_RX_VMDQ_RSS:
2190 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2191 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2192 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2193 PMD_INIT_LOG(ERR, "SRIOV is active,"
2194 " invalid queue number"
2195 " for VMDQ RSS, allowed"
2196 " value are 1, 2 or 4.");
2200 case ETH_MQ_RX_VMDQ_ONLY:
2201 case ETH_MQ_RX_NONE:
2202 /* if nothing mq mode configure, use default scheme */
2203 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2204 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2205 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2207 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2208 /* SRIOV only works in VMDq enable mode */
2209 PMD_INIT_LOG(ERR, "SRIOV is active,"
2210 " wrong mq_mode rx %d.",
2211 dev_conf->rxmode.mq_mode);
2215 switch (dev_conf->txmode.mq_mode) {
2216 case ETH_MQ_TX_VMDQ_DCB:
2217 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2218 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2220 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2221 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2225 /* check valid queue number */
2226 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2227 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2228 PMD_INIT_LOG(ERR, "SRIOV is active,"
2229 " nb_rx_q=%d nb_tx_q=%d queue number"
2230 " must be less than or equal to %d.",
2232 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2236 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2237 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2241 /* check configuration for vmdb+dcb mode */
2242 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2243 const struct rte_eth_vmdq_dcb_conf *conf;
2245 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2246 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2247 IXGBE_VMDQ_DCB_NB_QUEUES);
2250 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2251 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2252 conf->nb_queue_pools == ETH_32_POOLS)) {
2253 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2254 " nb_queue_pools must be %d or %d.",
2255 ETH_16_POOLS, ETH_32_POOLS);
2259 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2260 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2262 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2263 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2264 IXGBE_VMDQ_DCB_NB_QUEUES);
2267 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2268 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2269 conf->nb_queue_pools == ETH_32_POOLS)) {
2270 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2271 " nb_queue_pools != %d and"
2272 " nb_queue_pools != %d.",
2273 ETH_16_POOLS, ETH_32_POOLS);
2278 /* For DCB mode check our configuration before we go further */
2279 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2280 const struct rte_eth_dcb_rx_conf *conf;
2282 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2283 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2284 IXGBE_DCB_NB_QUEUES);
2287 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2288 if (!(conf->nb_tcs == ETH_4_TCS ||
2289 conf->nb_tcs == ETH_8_TCS)) {
2290 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2291 " and nb_tcs != %d.",
2292 ETH_4_TCS, ETH_8_TCS);
2297 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2298 const struct rte_eth_dcb_tx_conf *conf;
2300 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2301 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2302 IXGBE_DCB_NB_QUEUES);
2305 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2306 if (!(conf->nb_tcs == ETH_4_TCS ||
2307 conf->nb_tcs == ETH_8_TCS)) {
2308 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2309 " and nb_tcs != %d.",
2310 ETH_4_TCS, ETH_8_TCS);
2316 * When DCB/VT is off, maximum number of queues changes,
2317 * except for 82598EB, which remains constant.
2319 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2320 hw->mac.type != ixgbe_mac_82598EB) {
2321 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2323 "Neither VT nor DCB are enabled, "
2325 IXGBE_NONE_MODE_TX_NB_QUEUES);
2334 ixgbe_dev_configure(struct rte_eth_dev *dev)
2336 struct ixgbe_interrupt *intr =
2337 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2338 struct ixgbe_adapter *adapter =
2339 (struct ixgbe_adapter *)dev->data->dev_private;
2342 PMD_INIT_FUNC_TRACE();
2343 /* multipe queue mode checking */
2344 ret = ixgbe_check_mq_mode(dev);
2346 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2351 /* set flag to update link status after init */
2352 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2355 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2356 * allocation or vector Rx preconditions we will reset it.
2358 adapter->rx_bulk_alloc_allowed = true;
2359 adapter->rx_vec_allowed = true;
2365 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2367 struct ixgbe_hw *hw =
2368 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2369 struct ixgbe_interrupt *intr =
2370 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2373 /* only set up it on X550EM_X */
2374 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2375 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2376 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2377 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2378 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2379 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2384 * Configure device link speed and setup link.
2385 * It returns 0 on success.
2388 ixgbe_dev_start(struct rte_eth_dev *dev)
2390 struct ixgbe_hw *hw =
2391 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392 struct ixgbe_vf_info *vfinfo =
2393 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2394 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2395 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2396 uint32_t intr_vector = 0;
2397 int err, link_up = 0, negotiate = 0;
2402 uint32_t *link_speeds;
2404 PMD_INIT_FUNC_TRACE();
2406 /* IXGBE devices don't support:
2407 * - half duplex (checked afterwards for valid speeds)
2408 * - fixed speed: TODO implement
2410 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2411 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2412 dev->data->port_id);
2416 /* disable uio/vfio intr/eventfd mapping */
2417 rte_intr_disable(intr_handle);
2420 hw->adapter_stopped = 0;
2421 ixgbe_stop_adapter(hw);
2423 /* reinitialize adapter
2424 * this calls reset and start
2426 status = ixgbe_pf_reset_hw(hw);
2429 hw->mac.ops.start_hw(hw);
2430 hw->mac.get_link_status = true;
2432 /* configure PF module if SRIOV enabled */
2433 ixgbe_pf_host_configure(dev);
2435 ixgbe_dev_phy_intr_setup(dev);
2437 /* check and configure queue intr-vector mapping */
2438 if ((rte_intr_cap_multiple(intr_handle) ||
2439 !RTE_ETH_DEV_SRIOV(dev).active) &&
2440 dev->data->dev_conf.intr_conf.rxq != 0) {
2441 intr_vector = dev->data->nb_rx_queues;
2442 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2443 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2444 IXGBE_MAX_INTR_QUEUE_NUM);
2447 if (rte_intr_efd_enable(intr_handle, intr_vector))
2451 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2452 intr_handle->intr_vec =
2453 rte_zmalloc("intr_vec",
2454 dev->data->nb_rx_queues * sizeof(int), 0);
2455 if (intr_handle->intr_vec == NULL) {
2456 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2457 " intr_vec\n", dev->data->nb_rx_queues);
2462 /* confiugre msix for sleep until rx interrupt */
2463 ixgbe_configure_msix(dev);
2465 /* initialize transmission unit */
2466 ixgbe_dev_tx_init(dev);
2468 /* This can fail when allocating mbufs for descriptor rings */
2469 err = ixgbe_dev_rx_init(dev);
2471 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2475 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2476 ETH_VLAN_EXTEND_MASK;
2477 ixgbe_vlan_offload_set(dev, mask);
2479 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2480 /* Enable vlan filtering for VMDq */
2481 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2484 /* Configure DCB hw */
2485 ixgbe_configure_dcb(dev);
2487 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2488 err = ixgbe_fdir_configure(dev);
2493 /* Restore vf rate limit */
2494 if (vfinfo != NULL) {
2495 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2496 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2497 if (vfinfo[vf].tx_rate[idx] != 0)
2498 rte_pmd_ixgbe_set_vf_rate_limit(
2499 dev->data->port_id, vf,
2500 vfinfo[vf].tx_rate[idx],
2504 ixgbe_restore_statistics_mapping(dev);
2506 err = ixgbe_dev_rxtx_start(dev);
2508 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2512 /* Skip link setup if loopback mode is enabled for 82599. */
2513 if (hw->mac.type == ixgbe_mac_82599EB &&
2514 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2515 goto skip_link_setup;
2517 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2518 err = hw->mac.ops.setup_sfp(hw);
2523 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2524 /* Turn on the copper */
2525 ixgbe_set_phy_power(hw, true);
2527 /* Turn on the laser */
2528 ixgbe_enable_tx_laser(hw);
2531 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2534 dev->data->dev_link.link_status = link_up;
2536 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2540 link_speeds = &dev->data->dev_conf.link_speeds;
2541 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2542 ETH_LINK_SPEED_10G)) {
2543 PMD_INIT_LOG(ERR, "Invalid link setting");
2548 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2549 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2550 IXGBE_LINK_SPEED_82599_AUTONEG :
2551 IXGBE_LINK_SPEED_82598_AUTONEG;
2553 if (*link_speeds & ETH_LINK_SPEED_10G)
2554 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2555 if (*link_speeds & ETH_LINK_SPEED_1G)
2556 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2557 if (*link_speeds & ETH_LINK_SPEED_100M)
2558 speed |= IXGBE_LINK_SPEED_100_FULL;
2561 err = ixgbe_setup_link(hw, speed, link_up);
2567 if (rte_intr_allow_others(intr_handle)) {
2568 /* check if lsc interrupt is enabled */
2569 if (dev->data->dev_conf.intr_conf.lsc != 0)
2570 ixgbe_dev_lsc_interrupt_setup(dev);
2571 ixgbe_dev_macsec_interrupt_setup(dev);
2573 rte_intr_callback_unregister(intr_handle,
2574 ixgbe_dev_interrupt_handler, dev);
2575 if (dev->data->dev_conf.intr_conf.lsc != 0)
2576 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2577 " no intr multiplex\n");
2580 /* check if rxq interrupt is enabled */
2581 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2582 rte_intr_dp_is_en(intr_handle))
2583 ixgbe_dev_rxq_interrupt_setup(dev);
2585 /* enable uio/vfio intr/eventfd mapping */
2586 rte_intr_enable(intr_handle);
2588 /* resume enabled intr since hw reset */
2589 ixgbe_enable_intr(dev);
2590 ixgbe_l2_tunnel_conf(dev);
2591 ixgbe_filter_restore(dev);
2596 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2597 ixgbe_dev_clear_queues(dev);
2602 * Stop device: disable rx and tx functions to allow for reconfiguring.
2605 ixgbe_dev_stop(struct rte_eth_dev *dev)
2607 struct rte_eth_link link;
2608 struct ixgbe_hw *hw =
2609 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2610 struct ixgbe_vf_info *vfinfo =
2611 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2612 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2613 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2616 PMD_INIT_FUNC_TRACE();
2618 /* disable interrupts */
2619 ixgbe_disable_intr(hw);
2622 ixgbe_pf_reset_hw(hw);
2623 hw->adapter_stopped = 0;
2626 ixgbe_stop_adapter(hw);
2628 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2629 vfinfo[vf].clear_to_send = false;
2631 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2632 /* Turn off the copper */
2633 ixgbe_set_phy_power(hw, false);
2635 /* Turn off the laser */
2636 ixgbe_disable_tx_laser(hw);
2639 ixgbe_dev_clear_queues(dev);
2641 /* Clear stored conf */
2642 dev->data->scattered_rx = 0;
2645 /* Clear recorded link status */
2646 memset(&link, 0, sizeof(link));
2647 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2649 if (!rte_intr_allow_others(intr_handle))
2650 /* resume to the default handler */
2651 rte_intr_callback_register(intr_handle,
2652 ixgbe_dev_interrupt_handler,
2655 /* Clean datapath event and queue/vec mapping */
2656 rte_intr_efd_disable(intr_handle);
2657 if (intr_handle->intr_vec != NULL) {
2658 rte_free(intr_handle->intr_vec);
2659 intr_handle->intr_vec = NULL;
2664 * Set device link up: enable tx.
2667 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2669 struct ixgbe_hw *hw =
2670 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2671 if (hw->mac.type == ixgbe_mac_82599EB) {
2672 #ifdef RTE_NIC_BYPASS
2673 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2674 /* Not suported in bypass mode */
2675 PMD_INIT_LOG(ERR, "Set link up is not supported "
2676 "by device id 0x%x", hw->device_id);
2682 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2683 /* Turn on the copper */
2684 ixgbe_set_phy_power(hw, true);
2686 /* Turn on the laser */
2687 ixgbe_enable_tx_laser(hw);
2694 * Set device link down: disable tx.
2697 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2699 struct ixgbe_hw *hw =
2700 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2701 if (hw->mac.type == ixgbe_mac_82599EB) {
2702 #ifdef RTE_NIC_BYPASS
2703 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2704 /* Not suported in bypass mode */
2705 PMD_INIT_LOG(ERR, "Set link down is not supported "
2706 "by device id 0x%x", hw->device_id);
2712 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2713 /* Turn off the copper */
2714 ixgbe_set_phy_power(hw, false);
2716 /* Turn off the laser */
2717 ixgbe_disable_tx_laser(hw);
2724 * Reest and stop device.
2727 ixgbe_dev_close(struct rte_eth_dev *dev)
2729 struct ixgbe_hw *hw =
2730 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2732 PMD_INIT_FUNC_TRACE();
2734 ixgbe_pf_reset_hw(hw);
2736 ixgbe_dev_stop(dev);
2737 hw->adapter_stopped = 1;
2739 ixgbe_dev_free_queues(dev);
2741 ixgbe_disable_pcie_master(hw);
2743 /* reprogram the RAR[0] in case user changed it. */
2744 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2748 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2749 struct ixgbe_hw_stats *hw_stats,
2750 struct ixgbe_macsec_stats *macsec_stats,
2751 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2752 uint64_t *total_qprc, uint64_t *total_qprdc)
2754 uint32_t bprc, lxon, lxoff, total;
2755 uint32_t delta_gprc = 0;
2757 /* Workaround for RX byte count not including CRC bytes when CRC
2758 * strip is enabled. CRC bytes are removed from counters when crc_strip
2761 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2762 IXGBE_HLREG0_RXCRCSTRP);
2764 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2765 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2766 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2767 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2769 for (i = 0; i < 8; i++) {
2770 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2772 /* global total per queue */
2773 hw_stats->mpc[i] += mp;
2774 /* Running comprehensive total for stats display */
2775 *total_missed_rx += hw_stats->mpc[i];
2776 if (hw->mac.type == ixgbe_mac_82598EB) {
2777 hw_stats->rnbc[i] +=
2778 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2779 hw_stats->pxonrxc[i] +=
2780 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2781 hw_stats->pxoffrxc[i] +=
2782 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2784 hw_stats->pxonrxc[i] +=
2785 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2786 hw_stats->pxoffrxc[i] +=
2787 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2788 hw_stats->pxon2offc[i] +=
2789 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2791 hw_stats->pxontxc[i] +=
2792 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2793 hw_stats->pxofftxc[i] +=
2794 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2796 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2797 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2798 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2799 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2801 delta_gprc += delta_qprc;
2803 hw_stats->qprc[i] += delta_qprc;
2804 hw_stats->qptc[i] += delta_qptc;
2806 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2807 hw_stats->qbrc[i] +=
2808 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2810 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2812 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2813 hw_stats->qbtc[i] +=
2814 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2816 hw_stats->qprdc[i] += delta_qprdc;
2817 *total_qprdc += hw_stats->qprdc[i];
2819 *total_qprc += hw_stats->qprc[i];
2820 *total_qbrc += hw_stats->qbrc[i];
2822 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2823 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2824 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2827 * An errata states that gprc actually counts good + missed packets:
2828 * Workaround to set gprc to summated queue packet receives
2830 hw_stats->gprc = *total_qprc;
2832 if (hw->mac.type != ixgbe_mac_82598EB) {
2833 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2834 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2835 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2836 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2837 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2838 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2839 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2840 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2842 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2843 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2844 /* 82598 only has a counter in the high register */
2845 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2846 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2847 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2849 uint64_t old_tpr = hw_stats->tpr;
2851 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2852 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2855 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2857 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2858 hw_stats->gptc += delta_gptc;
2859 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2860 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2863 * Workaround: mprc hardware is incorrectly counting
2864 * broadcasts, so for now we subtract those.
2866 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2867 hw_stats->bprc += bprc;
2868 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2869 if (hw->mac.type == ixgbe_mac_82598EB)
2870 hw_stats->mprc -= bprc;
2872 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2873 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2874 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2875 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2876 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2877 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2879 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2880 hw_stats->lxontxc += lxon;
2881 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2882 hw_stats->lxofftxc += lxoff;
2883 total = lxon + lxoff;
2885 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2886 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2887 hw_stats->gptc -= total;
2888 hw_stats->mptc -= total;
2889 hw_stats->ptc64 -= total;
2890 hw_stats->gotc -= total * ETHER_MIN_LEN;
2892 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2893 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2894 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2895 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2896 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2897 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2898 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2899 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2900 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2901 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2902 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2903 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2904 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2905 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2906 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2907 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2908 /* Only read FCOE on 82599 */
2909 if (hw->mac.type != ixgbe_mac_82598EB) {
2910 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2911 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2912 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2913 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2914 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2917 /* Flow Director Stats registers */
2918 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2919 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2921 /* MACsec Stats registers */
2922 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2923 macsec_stats->out_pkts_encrypted +=
2924 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2925 macsec_stats->out_pkts_protected +=
2926 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2927 macsec_stats->out_octets_encrypted +=
2928 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2929 macsec_stats->out_octets_protected +=
2930 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2931 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2932 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2933 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2934 macsec_stats->in_pkts_unknownsci +=
2935 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2936 macsec_stats->in_octets_decrypted +=
2937 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2938 macsec_stats->in_octets_validated +=
2939 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2940 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2941 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2942 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2943 for (i = 0; i < 2; i++) {
2944 macsec_stats->in_pkts_ok +=
2945 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2946 macsec_stats->in_pkts_invalid +=
2947 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2948 macsec_stats->in_pkts_notvalid +=
2949 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2951 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2952 macsec_stats->in_pkts_notusingsa +=
2953 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2957 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2960 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2962 struct ixgbe_hw *hw =
2963 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964 struct ixgbe_hw_stats *hw_stats =
2965 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2966 struct ixgbe_macsec_stats *macsec_stats =
2967 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2968 dev->data->dev_private);
2969 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2972 total_missed_rx = 0;
2977 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2978 &total_qbrc, &total_qprc, &total_qprdc);
2983 /* Fill out the rte_eth_stats statistics structure */
2984 stats->ipackets = total_qprc;
2985 stats->ibytes = total_qbrc;
2986 stats->opackets = hw_stats->gptc;
2987 stats->obytes = hw_stats->gotc;
2989 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2990 stats->q_ipackets[i] = hw_stats->qprc[i];
2991 stats->q_opackets[i] = hw_stats->qptc[i];
2992 stats->q_ibytes[i] = hw_stats->qbrc[i];
2993 stats->q_obytes[i] = hw_stats->qbtc[i];
2994 stats->q_errors[i] = hw_stats->qprdc[i];
2998 stats->imissed = total_missed_rx;
2999 stats->ierrors = hw_stats->crcerrs +
3015 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3017 struct ixgbe_hw_stats *stats =
3018 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3020 /* HW registers are cleared on read */
3021 ixgbe_dev_stats_get(dev, NULL);
3023 /* Reset software totals */
3024 memset(stats, 0, sizeof(*stats));
3027 /* This function calculates the number of xstats based on the current config */
3029 ixgbe_xstats_calc_num(void) {
3030 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3031 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3032 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3035 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3036 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3038 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3039 unsigned stat, i, count;
3041 if (xstats_names != NULL) {
3044 /* Note: limit >= cnt_stats checked upstream
3045 * in rte_eth_xstats_names()
3048 /* Extended stats from ixgbe_hw_stats */
3049 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3050 snprintf(xstats_names[count].name,
3051 sizeof(xstats_names[count].name),
3053 rte_ixgbe_stats_strings[i].name);
3058 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3059 snprintf(xstats_names[count].name,
3060 sizeof(xstats_names[count].name),
3062 rte_ixgbe_macsec_strings[i].name);
3066 /* RX Priority Stats */
3067 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3068 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3069 snprintf(xstats_names[count].name,
3070 sizeof(xstats_names[count].name),
3071 "rx_priority%u_%s", i,
3072 rte_ixgbe_rxq_strings[stat].name);
3077 /* TX Priority Stats */
3078 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3079 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3080 snprintf(xstats_names[count].name,
3081 sizeof(xstats_names[count].name),
3082 "tx_priority%u_%s", i,
3083 rte_ixgbe_txq_strings[stat].name);
3091 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3092 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3096 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3099 if (xstats_names != NULL)
3100 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3101 snprintf(xstats_names[i].name,
3102 sizeof(xstats_names[i].name),
3103 "%s", rte_ixgbevf_stats_strings[i].name);
3104 return IXGBEVF_NB_XSTATS;
3108 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3111 struct ixgbe_hw *hw =
3112 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3113 struct ixgbe_hw_stats *hw_stats =
3114 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3115 struct ixgbe_macsec_stats *macsec_stats =
3116 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3117 dev->data->dev_private);
3118 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3119 unsigned i, stat, count = 0;
3121 count = ixgbe_xstats_calc_num();
3126 total_missed_rx = 0;
3131 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3132 &total_qbrc, &total_qprc, &total_qprdc);
3134 /* If this is a reset xstats is NULL, and we have cleared the
3135 * registers by reading them.
3140 /* Extended stats from ixgbe_hw_stats */
3142 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3143 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3144 rte_ixgbe_stats_strings[i].offset);
3145 xstats[count].id = count;
3150 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3151 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3152 rte_ixgbe_macsec_strings[i].offset);
3153 xstats[count].id = count;
3157 /* RX Priority Stats */
3158 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3159 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3160 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3161 rte_ixgbe_rxq_strings[stat].offset +
3162 (sizeof(uint64_t) * i));
3163 xstats[count].id = count;
3168 /* TX Priority Stats */
3169 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3170 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3171 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3172 rte_ixgbe_txq_strings[stat].offset +
3173 (sizeof(uint64_t) * i));
3174 xstats[count].id = count;
3182 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3184 struct ixgbe_hw_stats *stats =
3185 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3186 struct ixgbe_macsec_stats *macsec_stats =
3187 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3188 dev->data->dev_private);
3190 unsigned count = ixgbe_xstats_calc_num();
3192 /* HW registers are cleared on read */
3193 ixgbe_dev_xstats_get(dev, NULL, count);
3195 /* Reset software totals */
3196 memset(stats, 0, sizeof(*stats));
3197 memset(macsec_stats, 0, sizeof(*macsec_stats));
3201 ixgbevf_update_stats(struct rte_eth_dev *dev)
3203 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3204 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3205 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3207 /* Good Rx packet, include VF loopback */
3208 UPDATE_VF_STAT(IXGBE_VFGPRC,
3209 hw_stats->last_vfgprc, hw_stats->vfgprc);
3211 /* Good Rx octets, include VF loopback */
3212 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3213 hw_stats->last_vfgorc, hw_stats->vfgorc);
3215 /* Good Tx packet, include VF loopback */
3216 UPDATE_VF_STAT(IXGBE_VFGPTC,
3217 hw_stats->last_vfgptc, hw_stats->vfgptc);
3219 /* Good Tx octets, include VF loopback */
3220 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3221 hw_stats->last_vfgotc, hw_stats->vfgotc);
3223 /* Rx Multicst Packet */
3224 UPDATE_VF_STAT(IXGBE_VFMPRC,
3225 hw_stats->last_vfmprc, hw_stats->vfmprc);
3229 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3232 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3233 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3236 if (n < IXGBEVF_NB_XSTATS)
3237 return IXGBEVF_NB_XSTATS;
3239 ixgbevf_update_stats(dev);
3244 /* Extended stats */
3245 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3246 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3247 rte_ixgbevf_stats_strings[i].offset);
3250 return IXGBEVF_NB_XSTATS;
3254 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3256 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3257 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3259 ixgbevf_update_stats(dev);
3264 stats->ipackets = hw_stats->vfgprc;
3265 stats->ibytes = hw_stats->vfgorc;
3266 stats->opackets = hw_stats->vfgptc;
3267 stats->obytes = hw_stats->vfgotc;
3271 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3273 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3274 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3276 /* Sync HW register to the last stats */
3277 ixgbevf_dev_stats_get(dev, NULL);
3279 /* reset HW current stats*/
3280 hw_stats->vfgprc = 0;
3281 hw_stats->vfgorc = 0;
3282 hw_stats->vfgptc = 0;
3283 hw_stats->vfgotc = 0;
3287 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3289 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3290 u16 eeprom_verh, eeprom_verl;
3294 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3295 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3297 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3298 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3300 ret += 1; /* add the size of '\0' */
3301 if (fw_size < (u32)ret)
3308 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3310 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3311 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3314 dev_info->pci_dev = pci_dev;
3315 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3316 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3317 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3319 * When DCB/VT is off, maximum number of queues changes,
3320 * except for 82598EB, which remains constant.
3322 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3323 hw->mac.type != ixgbe_mac_82598EB)
3324 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3326 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3327 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3328 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3329 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3330 dev_info->max_vfs = pci_dev->max_vfs;
3331 if (hw->mac.type == ixgbe_mac_82598EB)
3332 dev_info->max_vmdq_pools = ETH_16_POOLS;
3334 dev_info->max_vmdq_pools = ETH_64_POOLS;
3335 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3336 dev_info->rx_offload_capa =
3337 DEV_RX_OFFLOAD_VLAN_STRIP |
3338 DEV_RX_OFFLOAD_IPV4_CKSUM |
3339 DEV_RX_OFFLOAD_UDP_CKSUM |
3340 DEV_RX_OFFLOAD_TCP_CKSUM;
3343 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3346 if ((hw->mac.type == ixgbe_mac_82599EB ||
3347 hw->mac.type == ixgbe_mac_X540) &&
3348 !RTE_ETH_DEV_SRIOV(dev).active)
3349 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3351 if (hw->mac.type == ixgbe_mac_82599EB ||
3352 hw->mac.type == ixgbe_mac_X540)
3353 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3355 if (hw->mac.type == ixgbe_mac_X550 ||
3356 hw->mac.type == ixgbe_mac_X550EM_x ||
3357 hw->mac.type == ixgbe_mac_X550EM_a)
3358 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3360 dev_info->tx_offload_capa =
3361 DEV_TX_OFFLOAD_VLAN_INSERT |
3362 DEV_TX_OFFLOAD_IPV4_CKSUM |
3363 DEV_TX_OFFLOAD_UDP_CKSUM |
3364 DEV_TX_OFFLOAD_TCP_CKSUM |
3365 DEV_TX_OFFLOAD_SCTP_CKSUM |
3366 DEV_TX_OFFLOAD_TCP_TSO;
3368 if (hw->mac.type == ixgbe_mac_82599EB ||
3369 hw->mac.type == ixgbe_mac_X540)
3370 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3372 if (hw->mac.type == ixgbe_mac_X550 ||
3373 hw->mac.type == ixgbe_mac_X550EM_x ||
3374 hw->mac.type == ixgbe_mac_X550EM_a)
3375 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3377 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3379 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3380 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3381 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3383 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3387 dev_info->default_txconf = (struct rte_eth_txconf) {
3389 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3390 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3391 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3393 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3394 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3395 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3396 ETH_TXQ_FLAGS_NOOFFLOADS,
3399 dev_info->rx_desc_lim = rx_desc_lim;
3400 dev_info->tx_desc_lim = tx_desc_lim;
3402 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3403 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3404 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3406 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3407 if (hw->mac.type == ixgbe_mac_X540 ||
3408 hw->mac.type == ixgbe_mac_X540_vf ||
3409 hw->mac.type == ixgbe_mac_X550 ||
3410 hw->mac.type == ixgbe_mac_X550_vf) {
3411 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3415 static const uint32_t *
3416 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3418 static const uint32_t ptypes[] = {
3419 /* For non-vec functions,
3420 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3421 * for vec functions,
3422 * refers to _recv_raw_pkts_vec().
3426 RTE_PTYPE_L3_IPV4_EXT,
3428 RTE_PTYPE_L3_IPV6_EXT,
3432 RTE_PTYPE_TUNNEL_IP,
3433 RTE_PTYPE_INNER_L3_IPV6,
3434 RTE_PTYPE_INNER_L3_IPV6_EXT,
3435 RTE_PTYPE_INNER_L4_TCP,
3436 RTE_PTYPE_INNER_L4_UDP,
3440 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3441 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3442 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3443 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3449 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3450 struct rte_eth_dev_info *dev_info)
3452 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3453 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3455 dev_info->pci_dev = pci_dev;
3456 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3457 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3458 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3459 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3460 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3461 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3462 dev_info->max_vfs = pci_dev->max_vfs;
3463 if (hw->mac.type == ixgbe_mac_82598EB)
3464 dev_info->max_vmdq_pools = ETH_16_POOLS;
3466 dev_info->max_vmdq_pools = ETH_64_POOLS;
3467 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3468 DEV_RX_OFFLOAD_IPV4_CKSUM |
3469 DEV_RX_OFFLOAD_UDP_CKSUM |
3470 DEV_RX_OFFLOAD_TCP_CKSUM;
3471 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3472 DEV_TX_OFFLOAD_IPV4_CKSUM |
3473 DEV_TX_OFFLOAD_UDP_CKSUM |
3474 DEV_TX_OFFLOAD_TCP_CKSUM |
3475 DEV_TX_OFFLOAD_SCTP_CKSUM |
3476 DEV_TX_OFFLOAD_TCP_TSO;
3478 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3480 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3481 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3482 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3484 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3488 dev_info->default_txconf = (struct rte_eth_txconf) {
3490 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3491 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3492 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3494 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3495 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3496 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3497 ETH_TXQ_FLAGS_NOOFFLOADS,
3500 dev_info->rx_desc_lim = rx_desc_lim;
3501 dev_info->tx_desc_lim = tx_desc_lim;
3504 /* return 0 means link status changed, -1 means not changed */
3506 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3508 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3509 struct rte_eth_link link, old;
3510 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3514 link.link_status = ETH_LINK_DOWN;
3515 link.link_speed = 0;
3516 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3517 memset(&old, 0, sizeof(old));
3518 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3520 hw->mac.get_link_status = true;
3522 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3523 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3524 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3526 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3529 link.link_speed = ETH_SPEED_NUM_100M;
3530 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3531 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3532 if (link.link_status == old.link_status)
3538 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3539 if (link.link_status == old.link_status)
3543 link.link_status = ETH_LINK_UP;
3544 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3546 switch (link_speed) {
3548 case IXGBE_LINK_SPEED_UNKNOWN:
3549 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3550 link.link_speed = ETH_SPEED_NUM_100M;
3553 case IXGBE_LINK_SPEED_100_FULL:
3554 link.link_speed = ETH_SPEED_NUM_100M;
3557 case IXGBE_LINK_SPEED_1GB_FULL:
3558 link.link_speed = ETH_SPEED_NUM_1G;
3561 case IXGBE_LINK_SPEED_10GB_FULL:
3562 link.link_speed = ETH_SPEED_NUM_10G;
3565 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3567 if (link.link_status == old.link_status)
3574 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3576 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3579 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3580 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3581 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3585 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3587 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3590 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3591 fctrl &= (~IXGBE_FCTRL_UPE);
3592 if (dev->data->all_multicast == 1)
3593 fctrl |= IXGBE_FCTRL_MPE;
3595 fctrl &= (~IXGBE_FCTRL_MPE);
3596 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3600 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3602 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3606 fctrl |= IXGBE_FCTRL_MPE;
3607 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3611 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3613 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3616 if (dev->data->promiscuous == 1)
3617 return; /* must remain in all_multicast mode */
3619 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3620 fctrl &= (~IXGBE_FCTRL_MPE);
3621 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3625 * It clears the interrupt causes and enables the interrupt.
3626 * It will be called once only during nic initialized.
3629 * Pointer to struct rte_eth_dev.
3632 * - On success, zero.
3633 * - On failure, a negative value.
3636 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3638 struct ixgbe_interrupt *intr =
3639 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3641 ixgbe_dev_link_status_print(dev);
3642 intr->mask |= IXGBE_EICR_LSC;
3648 * It clears the interrupt causes and enables the interrupt.
3649 * It will be called once only during nic initialized.
3652 * Pointer to struct rte_eth_dev.
3655 * - On success, zero.
3656 * - On failure, a negative value.
3659 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3661 struct ixgbe_interrupt *intr =
3662 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3664 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3670 * It clears the interrupt causes and enables the interrupt.
3671 * It will be called once only during nic initialized.
3674 * Pointer to struct rte_eth_dev.
3677 * - On success, zero.
3678 * - On failure, a negative value.
3681 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3683 struct ixgbe_interrupt *intr =
3684 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3686 intr->mask |= IXGBE_EICR_LINKSEC;
3692 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3695 * Pointer to struct rte_eth_dev.
3698 * - On success, zero.
3699 * - On failure, a negative value.
3702 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3705 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3706 struct ixgbe_interrupt *intr =
3707 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3709 /* clear all cause mask */
3710 ixgbe_disable_intr(hw);
3712 /* read-on-clear nic registers here */
3713 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3714 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3718 /* set flag for async link update */
3719 if (eicr & IXGBE_EICR_LSC)
3720 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3722 if (eicr & IXGBE_EICR_MAILBOX)
3723 intr->flags |= IXGBE_FLAG_MAILBOX;
3725 if (eicr & IXGBE_EICR_LINKSEC)
3726 intr->flags |= IXGBE_FLAG_MACSEC;
3728 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3729 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3730 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3731 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3737 * It gets and then prints the link status.
3740 * Pointer to struct rte_eth_dev.
3743 * - On success, zero.
3744 * - On failure, a negative value.
3747 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3749 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3750 struct rte_eth_link link;
3752 memset(&link, 0, sizeof(link));
3753 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3754 if (link.link_status) {
3755 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3756 (int)(dev->data->port_id),
3757 (unsigned)link.link_speed,
3758 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3759 "full-duplex" : "half-duplex");
3761 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3762 (int)(dev->data->port_id));
3764 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3765 pci_dev->addr.domain,
3767 pci_dev->addr.devid,
3768 pci_dev->addr.function);
3772 * It executes link_update after knowing an interrupt occurred.
3775 * Pointer to struct rte_eth_dev.
3778 * - On success, zero.
3779 * - On failure, a negative value.
3782 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3783 struct rte_intr_handle *intr_handle)
3785 struct ixgbe_interrupt *intr =
3786 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3788 struct rte_eth_link link;
3789 int intr_enable_delay = false;
3790 struct ixgbe_hw *hw =
3791 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3793 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3795 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3796 ixgbe_pf_mbx_process(dev);
3797 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3800 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3801 ixgbe_handle_lasi(hw);
3802 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3805 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3806 /* get the link status before link update, for predicting later */
3807 memset(&link, 0, sizeof(link));
3808 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3810 ixgbe_dev_link_update(dev, 0);
3813 if (!link.link_status)
3814 /* handle it 1 sec later, wait it being stable */
3815 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3816 /* likely to down */
3818 /* handle it 4 sec later, wait it being stable */
3819 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3821 ixgbe_dev_link_status_print(dev);
3823 intr_enable_delay = true;
3826 if (intr_enable_delay) {
3827 if (rte_eal_alarm_set(timeout * 1000,
3828 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3829 PMD_DRV_LOG(ERR, "Error setting alarm");
3831 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3832 ixgbe_enable_intr(dev);
3833 rte_intr_enable(intr_handle);
3841 * Interrupt handler which shall be registered for alarm callback for delayed
3842 * handling specific interrupt to wait for the stable nic state. As the
3843 * NIC interrupt state is not stable for ixgbe after link is just down,
3844 * it needs to wait 4 seconds to get the stable status.
3847 * Pointer to interrupt handle.
3849 * The address of parameter (struct rte_eth_dev *) regsitered before.
3855 ixgbe_dev_interrupt_delayed_handler(void *param)
3857 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3858 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3859 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3860 struct ixgbe_interrupt *intr =
3861 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3862 struct ixgbe_hw *hw =
3863 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3866 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3867 if (eicr & IXGBE_EICR_MAILBOX)
3868 ixgbe_pf_mbx_process(dev);
3870 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3871 ixgbe_handle_lasi(hw);
3872 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3875 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3876 ixgbe_dev_link_update(dev, 0);
3877 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3878 ixgbe_dev_link_status_print(dev);
3879 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3882 if (intr->flags & IXGBE_FLAG_MACSEC) {
3883 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3885 intr->flags &= ~IXGBE_FLAG_MACSEC;
3888 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3889 ixgbe_enable_intr(dev);
3890 rte_intr_enable(intr_handle);
3894 * Interrupt handler triggered by NIC for handling
3895 * specific interrupt.
3898 * Pointer to interrupt handle.
3900 * The address of parameter (struct rte_eth_dev *) regsitered before.
3906 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3909 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3911 ixgbe_dev_interrupt_get_status(dev);
3912 ixgbe_dev_interrupt_action(dev, handle);
3916 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3918 struct ixgbe_hw *hw;
3920 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3925 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3927 struct ixgbe_hw *hw;
3929 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3930 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3934 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3936 struct ixgbe_hw *hw;
3942 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944 fc_conf->pause_time = hw->fc.pause_time;
3945 fc_conf->high_water = hw->fc.high_water[0];
3946 fc_conf->low_water = hw->fc.low_water[0];
3947 fc_conf->send_xon = hw->fc.send_xon;
3948 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3951 * Return rx_pause status according to actual setting of
3954 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3955 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3961 * Return tx_pause status according to actual setting of
3964 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3965 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3970 if (rx_pause && tx_pause)
3971 fc_conf->mode = RTE_FC_FULL;
3973 fc_conf->mode = RTE_FC_RX_PAUSE;
3975 fc_conf->mode = RTE_FC_TX_PAUSE;
3977 fc_conf->mode = RTE_FC_NONE;
3983 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3985 struct ixgbe_hw *hw;
3987 uint32_t rx_buf_size;
3988 uint32_t max_high_water;
3990 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3997 PMD_INIT_FUNC_TRACE();
3999 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4000 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4001 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4004 * At least reserve one Ethernet frame for watermark
4005 * high_water/low_water in kilo bytes for ixgbe
4007 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4008 if ((fc_conf->high_water > max_high_water) ||
4009 (fc_conf->high_water < fc_conf->low_water)) {
4010 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4011 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4015 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4016 hw->fc.pause_time = fc_conf->pause_time;
4017 hw->fc.high_water[0] = fc_conf->high_water;
4018 hw->fc.low_water[0] = fc_conf->low_water;
4019 hw->fc.send_xon = fc_conf->send_xon;
4020 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4022 err = ixgbe_fc_enable(hw);
4024 /* Not negotiated is not an error case */
4025 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4027 /* check if we want to forward MAC frames - driver doesn't have native
4028 * capability to do that, so we'll write the registers ourselves */
4030 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4032 /* set or clear MFLCN.PMCF bit depending on configuration */
4033 if (fc_conf->mac_ctrl_frame_fwd != 0)
4034 mflcn |= IXGBE_MFLCN_PMCF;
4036 mflcn &= ~IXGBE_MFLCN_PMCF;
4038 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4039 IXGBE_WRITE_FLUSH(hw);
4044 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4049 * ixgbe_pfc_enable_generic - Enable flow control
4050 * @hw: pointer to hardware structure
4051 * @tc_num: traffic class number
4052 * Enable flow control according to the current settings.
4055 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4058 uint32_t mflcn_reg, fccfg_reg;
4060 uint32_t fcrtl, fcrth;
4064 /* Validate the water mark configuration */
4065 if (!hw->fc.pause_time) {
4066 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4070 /* Low water mark of zero causes XOFF floods */
4071 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4072 /* High/Low water can not be 0 */
4073 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4074 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4075 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4079 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4080 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4081 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4085 /* Negotiate the fc mode to use */
4086 ixgbe_fc_autoneg(hw);
4088 /* Disable any previous flow control settings */
4089 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4090 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4092 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4093 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4095 switch (hw->fc.current_mode) {
4098 * If the count of enabled RX Priority Flow control >1,
4099 * and the TX pause can not be disabled
4102 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4103 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4104 if (reg & IXGBE_FCRTH_FCEN)
4108 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4110 case ixgbe_fc_rx_pause:
4112 * Rx Flow control is enabled and Tx Flow control is
4113 * disabled by software override. Since there really
4114 * isn't a way to advertise that we are capable of RX
4115 * Pause ONLY, we will advertise that we support both
4116 * symmetric and asymmetric Rx PAUSE. Later, we will
4117 * disable the adapter's ability to send PAUSE frames.
4119 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4121 * If the count of enabled RX Priority Flow control >1,
4122 * and the TX pause can not be disabled
4125 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4126 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4127 if (reg & IXGBE_FCRTH_FCEN)
4131 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4133 case ixgbe_fc_tx_pause:
4135 * Tx Flow control is enabled, and Rx Flow control is
4136 * disabled by software override.
4138 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4141 /* Flow control (both Rx and Tx) is enabled by SW override. */
4142 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4143 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4146 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4147 ret_val = IXGBE_ERR_CONFIG;
4151 /* Set 802.3x based flow control settings. */
4152 mflcn_reg |= IXGBE_MFLCN_DPF;
4153 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4154 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4156 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4157 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4158 hw->fc.high_water[tc_num]) {
4159 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4160 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4161 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4163 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4165 * In order to prevent Tx hangs when the internal Tx
4166 * switch is enabled we must set the high water mark
4167 * to the maximum FCRTH value. This allows the Tx
4168 * switch to function even under heavy Rx workloads.
4170 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4172 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4174 /* Configure pause time (2 TCs per register) */
4175 reg = hw->fc.pause_time * 0x00010001;
4176 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4177 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4179 /* Configure flow control refresh threshold value */
4180 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4187 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4189 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4190 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4192 if (hw->mac.type != ixgbe_mac_82598EB) {
4193 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4199 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4202 uint32_t rx_buf_size;
4203 uint32_t max_high_water;
4205 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4206 struct ixgbe_hw *hw =
4207 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4208 struct ixgbe_dcb_config *dcb_config =
4209 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4211 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4218 PMD_INIT_FUNC_TRACE();
4220 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4221 tc_num = map[pfc_conf->priority];
4222 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4223 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4225 * At least reserve one Ethernet frame for watermark
4226 * high_water/low_water in kilo bytes for ixgbe
4228 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4229 if ((pfc_conf->fc.high_water > max_high_water) ||
4230 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4231 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4232 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4236 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4237 hw->fc.pause_time = pfc_conf->fc.pause_time;
4238 hw->fc.send_xon = pfc_conf->fc.send_xon;
4239 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4240 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4242 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4244 /* Not negotiated is not an error case */
4245 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4248 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4253 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4254 struct rte_eth_rss_reta_entry64 *reta_conf,
4257 uint16_t i, sp_reta_size;
4260 uint16_t idx, shift;
4261 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4264 PMD_INIT_FUNC_TRACE();
4266 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4267 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4272 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4273 if (reta_size != sp_reta_size) {
4274 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4275 "(%d) doesn't match the number hardware can supported "
4276 "(%d)\n", reta_size, sp_reta_size);
4280 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4281 idx = i / RTE_RETA_GROUP_SIZE;
4282 shift = i % RTE_RETA_GROUP_SIZE;
4283 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4287 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4288 if (mask == IXGBE_4_BIT_MASK)
4291 r = IXGBE_READ_REG(hw, reta_reg);
4292 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4293 if (mask & (0x1 << j))
4294 reta |= reta_conf[idx].reta[shift + j] <<
4297 reta |= r & (IXGBE_8_BIT_MASK <<
4300 IXGBE_WRITE_REG(hw, reta_reg, reta);
4307 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4308 struct rte_eth_rss_reta_entry64 *reta_conf,
4311 uint16_t i, sp_reta_size;
4314 uint16_t idx, shift;
4315 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4318 PMD_INIT_FUNC_TRACE();
4319 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4320 if (reta_size != sp_reta_size) {
4321 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4322 "(%d) doesn't match the number hardware can supported "
4323 "(%d)\n", reta_size, sp_reta_size);
4327 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4328 idx = i / RTE_RETA_GROUP_SIZE;
4329 shift = i % RTE_RETA_GROUP_SIZE;
4330 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4335 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4336 reta = IXGBE_READ_REG(hw, reta_reg);
4337 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4338 if (mask & (0x1 << j))
4339 reta_conf[idx].reta[shift + j] =
4340 ((reta >> (CHAR_BIT * j)) &
4349 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4350 uint32_t index, uint32_t pool)
4352 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4353 uint32_t enable_addr = 1;
4355 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4359 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4361 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4363 ixgbe_clear_rar(hw, index);
4367 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4369 ixgbe_remove_rar(dev, 0);
4371 ixgbe_add_rar(dev, addr, 0, 0);
4375 is_ixgbe_pmd(const char *driver_name)
4377 if (!strstr(driver_name, "ixgbe"))
4380 if (strstr(driver_name, "ixgbe_vf"))
4387 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4388 struct ether_addr *mac_addr)
4390 struct ixgbe_hw *hw;
4391 struct ixgbe_vf_info *vfinfo;
4393 uint8_t *new_mac = (uint8_t *)(mac_addr);
4394 struct rte_eth_dev *dev;
4395 struct rte_eth_dev_info dev_info;
4397 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4399 dev = &rte_eth_devices[port];
4400 rte_eth_dev_info_get(port, &dev_info);
4402 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4405 if (vf >= dev_info.max_vfs)
4408 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4409 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4410 rar_entry = hw->mac.num_rar_entries - (vf + 1);
4412 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4413 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4415 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4422 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4426 struct ixgbe_hw *hw;
4427 struct rte_eth_dev_info dev_info;
4428 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4430 ixgbe_dev_info_get(dev, &dev_info);
4432 /* check that mtu is within the allowed range */
4433 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4436 /* refuse mtu that requires the support of scattered packets when this
4437 * feature has not been enabled before.
4439 if (!dev->data->scattered_rx &&
4440 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4441 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4444 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4445 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4447 /* switch to jumbo mode if needed */
4448 if (frame_size > ETHER_MAX_LEN) {
4449 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4450 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4452 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4453 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4455 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4457 /* update max frame size */
4458 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4460 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4461 maxfrs &= 0x0000FFFF;
4462 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4463 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4469 * Virtual Function operations
4472 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4474 PMD_INIT_FUNC_TRACE();
4476 /* Clear interrupt mask to stop from interrupts being generated */
4477 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4479 IXGBE_WRITE_FLUSH(hw);
4483 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4485 PMD_INIT_FUNC_TRACE();
4487 /* VF enable interrupt autoclean */
4488 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4489 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4490 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4492 IXGBE_WRITE_FLUSH(hw);
4496 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4498 struct rte_eth_conf *conf = &dev->data->dev_conf;
4499 struct ixgbe_adapter *adapter =
4500 (struct ixgbe_adapter *)dev->data->dev_private;
4502 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4503 dev->data->port_id);
4506 * VF has no ability to enable/disable HW CRC
4507 * Keep the persistent behavior the same as Host PF
4509 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4510 if (!conf->rxmode.hw_strip_crc) {
4511 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4512 conf->rxmode.hw_strip_crc = 1;
4515 if (conf->rxmode.hw_strip_crc) {
4516 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4517 conf->rxmode.hw_strip_crc = 0;
4522 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4523 * allocation or vector Rx preconditions we will reset it.
4525 adapter->rx_bulk_alloc_allowed = true;
4526 adapter->rx_vec_allowed = true;
4532 ixgbevf_dev_start(struct rte_eth_dev *dev)
4534 struct ixgbe_hw *hw =
4535 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4536 uint32_t intr_vector = 0;
4537 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4538 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4542 PMD_INIT_FUNC_TRACE();
4544 hw->mac.ops.reset_hw(hw);
4545 hw->mac.get_link_status = true;
4547 /* negotiate mailbox API version to use with the PF. */
4548 ixgbevf_negotiate_api(hw);
4550 ixgbevf_dev_tx_init(dev);
4552 /* This can fail when allocating mbufs for descriptor rings */
4553 err = ixgbevf_dev_rx_init(dev);
4555 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4556 ixgbe_dev_clear_queues(dev);
4561 ixgbevf_set_vfta_all(dev, 1);
4564 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4565 ETH_VLAN_EXTEND_MASK;
4566 ixgbevf_vlan_offload_set(dev, mask);
4568 ixgbevf_dev_rxtx_start(dev);
4570 /* check and configure queue intr-vector mapping */
4571 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4572 intr_vector = dev->data->nb_rx_queues;
4573 if (rte_intr_efd_enable(intr_handle, intr_vector))
4577 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4578 intr_handle->intr_vec =
4579 rte_zmalloc("intr_vec",
4580 dev->data->nb_rx_queues * sizeof(int), 0);
4581 if (intr_handle->intr_vec == NULL) {
4582 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4583 " intr_vec\n", dev->data->nb_rx_queues);
4587 ixgbevf_configure_msix(dev);
4589 rte_intr_enable(intr_handle);
4591 /* Re-enable interrupt for VF */
4592 ixgbevf_intr_enable(hw);
4598 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4600 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4601 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4602 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4604 PMD_INIT_FUNC_TRACE();
4606 ixgbevf_intr_disable(hw);
4608 hw->adapter_stopped = 1;
4609 ixgbe_stop_adapter(hw);
4612 * Clear what we set, but we still keep shadow_vfta to
4613 * restore after device starts
4615 ixgbevf_set_vfta_all(dev, 0);
4617 /* Clear stored conf */
4618 dev->data->scattered_rx = 0;
4620 ixgbe_dev_clear_queues(dev);
4622 /* Clean datapath event and queue/vec mapping */
4623 rte_intr_efd_disable(intr_handle);
4624 if (intr_handle->intr_vec != NULL) {
4625 rte_free(intr_handle->intr_vec);
4626 intr_handle->intr_vec = NULL;
4631 ixgbevf_dev_close(struct rte_eth_dev *dev)
4633 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4635 PMD_INIT_FUNC_TRACE();
4639 ixgbevf_dev_stop(dev);
4641 ixgbe_dev_free_queues(dev);
4644 * Remove the VF MAC address ro ensure
4645 * that the VF traffic goes to the PF
4646 * after stop, close and detach of the VF
4648 ixgbevf_remove_mac_addr(dev, 0);
4651 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4653 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4654 struct ixgbe_vfta *shadow_vfta =
4655 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4656 int i = 0, j = 0, vfta = 0, mask = 1;
4658 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4659 vfta = shadow_vfta->vfta[i];
4662 for (j = 0; j < 32; j++) {
4664 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4674 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4676 struct ixgbe_hw *hw =
4677 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4678 struct ixgbe_vfta *shadow_vfta =
4679 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4680 uint32_t vid_idx = 0;
4681 uint32_t vid_bit = 0;
4684 PMD_INIT_FUNC_TRACE();
4686 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4687 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4689 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4692 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4693 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4695 /* Save what we set and retore it after device reset */
4697 shadow_vfta->vfta[vid_idx] |= vid_bit;
4699 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4705 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4707 struct ixgbe_hw *hw =
4708 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4711 PMD_INIT_FUNC_TRACE();
4713 if (queue >= hw->mac.max_rx_queues)
4716 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4718 ctrl |= IXGBE_RXDCTL_VME;
4720 ctrl &= ~IXGBE_RXDCTL_VME;
4721 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4723 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4727 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4729 struct ixgbe_hw *hw =
4730 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4734 /* VF function only support hw strip feature, others are not support */
4735 if (mask & ETH_VLAN_STRIP_MASK) {
4736 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4738 for (i = 0; i < hw->mac.max_rx_queues; i++)
4739 ixgbevf_vlan_strip_queue_set(dev, i, on);
4744 ixgbe_vt_check(struct ixgbe_hw *hw)
4748 /* if Virtualization Technology is enabled */
4749 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4750 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4751 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4759 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4761 uint32_t vector = 0;
4763 switch (hw->mac.mc_filter_type) {
4764 case 0: /* use bits [47:36] of the address */
4765 vector = ((uc_addr->addr_bytes[4] >> 4) |
4766 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4768 case 1: /* use bits [46:35] of the address */
4769 vector = ((uc_addr->addr_bytes[4] >> 3) |
4770 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4772 case 2: /* use bits [45:34] of the address */
4773 vector = ((uc_addr->addr_bytes[4] >> 2) |
4774 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4776 case 3: /* use bits [43:32] of the address */
4777 vector = ((uc_addr->addr_bytes[4]) |
4778 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4780 default: /* Invalid mc_filter_type */
4784 /* vector can only be 12-bits or boundary will be exceeded */
4790 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4798 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4799 const uint32_t ixgbe_uta_bit_shift = 5;
4800 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4801 const uint32_t bit1 = 0x1;
4803 struct ixgbe_hw *hw =
4804 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4805 struct ixgbe_uta_info *uta_info =
4806 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4808 /* The UTA table only exists on 82599 hardware and newer */
4809 if (hw->mac.type < ixgbe_mac_82599EB)
4812 vector = ixgbe_uta_vector(hw, mac_addr);
4813 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4814 uta_shift = vector & ixgbe_uta_bit_mask;
4816 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4820 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4822 uta_info->uta_in_use++;
4823 reg_val |= (bit1 << uta_shift);
4824 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4826 uta_info->uta_in_use--;
4827 reg_val &= ~(bit1 << uta_shift);
4828 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4831 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4833 if (uta_info->uta_in_use > 0)
4834 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4835 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4837 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4843 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4846 struct ixgbe_hw *hw =
4847 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4848 struct ixgbe_uta_info *uta_info =
4849 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4851 /* The UTA table only exists on 82599 hardware and newer */
4852 if (hw->mac.type < ixgbe_mac_82599EB)
4856 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4857 uta_info->uta_shadow[i] = ~0;
4858 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4861 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4862 uta_info->uta_shadow[i] = 0;
4863 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4871 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4873 uint32_t new_val = orig_val;
4875 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4876 new_val |= IXGBE_VMOLR_AUPE;
4877 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4878 new_val |= IXGBE_VMOLR_ROMPE;
4879 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4880 new_val |= IXGBE_VMOLR_ROPE;
4881 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4882 new_val |= IXGBE_VMOLR_BAM;
4883 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4884 new_val |= IXGBE_VMOLR_MPE;
4891 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4893 struct ixgbe_hw *hw;
4894 struct ixgbe_mac_info *mac;
4895 struct rte_eth_dev *dev;
4896 struct rte_eth_dev_info dev_info;
4898 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4900 dev = &rte_eth_devices[port];
4901 rte_eth_dev_info_get(port, &dev_info);
4903 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4906 if (vf >= dev_info.max_vfs)
4912 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4915 mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4921 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4923 struct ixgbe_hw *hw;
4924 struct ixgbe_mac_info *mac;
4925 struct rte_eth_dev *dev;
4926 struct rte_eth_dev_info dev_info;
4928 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4930 dev = &rte_eth_devices[port];
4931 rte_eth_dev_info_get(port, &dev_info);
4933 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4936 if (vf >= dev_info.max_vfs)
4942 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4944 mac->ops.set_mac_anti_spoofing(hw, on, vf);
4950 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4952 struct ixgbe_hw *hw;
4954 struct rte_eth_dev *dev;
4955 struct rte_eth_dev_info dev_info;
4957 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4959 dev = &rte_eth_devices[port];
4960 rte_eth_dev_info_get(port, &dev_info);
4962 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4965 if (vf >= dev_info.max_vfs)
4968 if (vlan_id > ETHER_MAX_VLAN_ID)
4971 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4972 ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4975 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4980 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4986 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4988 struct ixgbe_hw *hw;
4990 struct rte_eth_dev *dev;
4991 struct rte_eth_dev_info dev_info;
4993 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4995 dev = &rte_eth_devices[port];
4996 rte_eth_dev_info_get(port, &dev_info);
4998 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5004 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5005 ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5006 /* enable or disable VMDQ loopback */
5008 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5010 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5012 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5018 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5020 struct ixgbe_hw *hw;
5023 int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5024 struct rte_eth_dev *dev;
5025 struct rte_eth_dev_info dev_info;
5027 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5029 dev = &rte_eth_devices[port];
5030 rte_eth_dev_info_get(port, &dev_info);
5032 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5038 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5039 for (i = 0; i <= num_queues; i++) {
5040 reg_value = IXGBE_QDE_WRITE |
5041 (i << IXGBE_QDE_IDX_SHIFT) |
5042 (on & IXGBE_QDE_ENABLE);
5043 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5050 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5052 struct ixgbe_hw *hw;
5054 struct rte_eth_dev *dev;
5055 struct rte_eth_dev_info dev_info;
5057 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5059 dev = &rte_eth_devices[port];
5060 rte_eth_dev_info_get(port, &dev_info);
5062 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5065 /* only support VF's 0 to 63 */
5066 if ((vf >= dev_info.max_vfs) || (vf > 63))
5072 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5073 reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5075 reg_value |= IXGBE_SRRCTL_DROP_EN;
5077 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5079 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5085 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5087 struct rte_eth_dev *dev;
5088 struct rte_eth_dev_info dev_info;
5089 uint16_t queues_per_pool;
5092 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5094 dev = &rte_eth_devices[port];
5095 rte_eth_dev_info_get(port, &dev_info);
5097 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5100 if (vf >= dev_info.max_vfs)
5106 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5108 /* The PF has 128 queue pairs and in SRIOV configuration
5109 * those queues will be assigned to VF's, so RXDCTL
5110 * registers will be dealing with queues which will be
5112 * Let's say we have SRIOV configured with 31 VF's then the
5113 * first 124 queues 0-123 will be allocated to VF's and only
5114 * the last 4 queues 123-127 will be assigned to the PF.
5117 queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5119 for (q = 0; q < queues_per_pool; q++)
5120 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5121 q + vf * queues_per_pool, on);
5126 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5129 struct rte_eth_dev *dev;
5130 struct rte_eth_dev_info dev_info;
5131 struct ixgbe_hw *hw;
5134 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5136 dev = &rte_eth_devices[port];
5137 rte_eth_dev_info_get(port, &dev_info);
5139 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5142 if (vf >= dev_info.max_vfs)
5148 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5149 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5151 if (hw->mac.type == ixgbe_mac_82598EB) {
5152 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5153 " on 82599 hardware and newer");
5156 if (ixgbe_vt_check(hw) < 0)
5159 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5166 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5172 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5174 struct rte_eth_dev *dev;
5175 struct rte_eth_dev_info dev_info;
5178 const uint8_t bit1 = 0x1;
5179 struct ixgbe_hw *hw;
5181 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5183 dev = &rte_eth_devices[port];
5184 rte_eth_dev_info_get(port, &dev_info);
5186 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5189 if (vf >= dev_info.max_vfs)
5195 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5197 if (ixgbe_vt_check(hw) < 0)
5200 /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5202 addr = IXGBE_VFRE(1);
5203 val = bit1 << (vf - 32);
5205 addr = IXGBE_VFRE(0);
5209 reg = IXGBE_READ_REG(hw, addr);
5216 IXGBE_WRITE_REG(hw, addr, reg);
5222 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5224 struct rte_eth_dev *dev;
5225 struct rte_eth_dev_info dev_info;
5228 const uint8_t bit1 = 0x1;
5230 struct ixgbe_hw *hw;
5232 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5234 dev = &rte_eth_devices[port];
5235 rte_eth_dev_info_get(port, &dev_info);
5237 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5240 if (vf >= dev_info.max_vfs)
5246 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5247 if (ixgbe_vt_check(hw) < 0)
5250 /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5252 addr = IXGBE_VFTE(1);
5253 val = bit1 << (vf - 32);
5255 addr = IXGBE_VFTE(0);
5259 reg = IXGBE_READ_REG(hw, addr);
5266 IXGBE_WRITE_REG(hw, addr, reg);
5272 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5273 uint64_t vf_mask, uint8_t vlan_on)
5275 struct rte_eth_dev *dev;
5276 struct rte_eth_dev_info dev_info;
5279 struct ixgbe_hw *hw;
5281 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5283 dev = &rte_eth_devices[port];
5284 rte_eth_dev_info_get(port, &dev_info);
5286 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5289 if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5292 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5293 if (ixgbe_vt_check(hw) < 0)
5296 for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5297 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5298 ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5308 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5309 uint16_t tx_rate, uint64_t q_msk)
5311 struct rte_eth_dev *dev;
5312 struct rte_eth_dev_info dev_info;
5313 struct ixgbe_hw *hw;
5314 struct ixgbe_vf_info *vfinfo;
5315 struct rte_eth_link link;
5316 uint8_t nb_q_per_pool;
5317 uint32_t queue_stride;
5318 uint32_t queue_idx, idx = 0, vf_idx;
5320 uint16_t total_rate = 0;
5321 struct rte_pci_device *pci_dev;
5323 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5325 dev = &rte_eth_devices[port];
5326 rte_eth_dev_info_get(port, &dev_info);
5327 rte_eth_link_get_nowait(port, &link);
5329 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5332 if (vf >= dev_info.max_vfs)
5335 if (tx_rate > link.link_speed)
5341 pci_dev = IXGBE_DEV_TO_PCI(dev);
5342 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5343 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5344 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5345 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5346 queue_idx = vf * queue_stride;
5347 queue_end = queue_idx + nb_q_per_pool - 1;
5348 if (queue_end >= hw->mac.max_tx_queues)
5352 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5355 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5357 total_rate += vfinfo[vf_idx].tx_rate[idx];
5363 /* Store tx_rate for this vf. */
5364 for (idx = 0; idx < nb_q_per_pool; idx++) {
5365 if (((uint64_t)0x1 << idx) & q_msk) {
5366 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5367 vfinfo[vf].tx_rate[idx] = tx_rate;
5368 total_rate += tx_rate;
5372 if (total_rate > dev->data->dev_link.link_speed) {
5373 /* Reset stored TX rate of the VF if it causes exceed
5376 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5380 /* Set RTTBCNRC of each queue/pool for vf X */
5381 for (; queue_idx <= queue_end; queue_idx++) {
5383 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5390 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5391 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5392 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5393 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5394 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5395 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5396 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5399 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5400 struct rte_eth_mirror_conf *mirror_conf,
5401 uint8_t rule_id, uint8_t on)
5403 uint32_t mr_ctl, vlvf;
5404 uint32_t mp_lsb = 0;
5405 uint32_t mv_msb = 0;
5406 uint32_t mv_lsb = 0;
5407 uint32_t mp_msb = 0;
5410 uint64_t vlan_mask = 0;
5412 const uint8_t pool_mask_offset = 32;
5413 const uint8_t vlan_mask_offset = 32;
5414 const uint8_t dst_pool_offset = 8;
5415 const uint8_t rule_mr_offset = 4;
5416 const uint8_t mirror_rule_mask = 0x0F;
5418 struct ixgbe_mirror_info *mr_info =
5419 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5420 struct ixgbe_hw *hw =
5421 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5422 uint8_t mirror_type = 0;
5424 if (ixgbe_vt_check(hw) < 0)
5427 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5430 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5431 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5432 mirror_conf->rule_type);
5436 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5437 mirror_type |= IXGBE_MRCTL_VLME;
5438 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5439 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5440 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5441 /* search vlan id related pool vlan filter index */
5442 reg_index = ixgbe_find_vlvf_slot(hw,
5443 mirror_conf->vlan.vlan_id[i],
5447 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5448 if ((vlvf & IXGBE_VLVF_VIEN) &&
5449 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5450 mirror_conf->vlan.vlan_id[i]))
5451 vlan_mask |= (1ULL << reg_index);
5458 mv_lsb = vlan_mask & 0xFFFFFFFF;
5459 mv_msb = vlan_mask >> vlan_mask_offset;
5461 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5462 mirror_conf->vlan.vlan_mask;
5463 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5464 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5465 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5466 mirror_conf->vlan.vlan_id[i];
5471 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5472 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5473 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5478 * if enable pool mirror, write related pool mask register,if disable
5479 * pool mirror, clear PFMRVM register
5481 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5482 mirror_type |= IXGBE_MRCTL_VPME;
5484 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5485 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5486 mr_info->mr_conf[rule_id].pool_mask =
5487 mirror_conf->pool_mask;
5492 mr_info->mr_conf[rule_id].pool_mask = 0;
5495 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5496 mirror_type |= IXGBE_MRCTL_UPME;
5497 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5498 mirror_type |= IXGBE_MRCTL_DPME;
5500 /* read mirror control register and recalculate it */
5501 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5504 mr_ctl |= mirror_type;
5505 mr_ctl &= mirror_rule_mask;
5506 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5508 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5510 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5511 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5513 /* write mirrror control register */
5514 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5516 /* write pool mirrror control register */
5517 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5518 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5519 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5522 /* write VLAN mirrror control register */
5523 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5524 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5525 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5533 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5536 uint32_t lsb_val = 0;
5537 uint32_t msb_val = 0;
5538 const uint8_t rule_mr_offset = 4;
5540 struct ixgbe_hw *hw =
5541 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5542 struct ixgbe_mirror_info *mr_info =
5543 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5545 if (ixgbe_vt_check(hw) < 0)
5548 memset(&mr_info->mr_conf[rule_id], 0,
5549 sizeof(struct rte_eth_mirror_conf));
5551 /* clear PFVMCTL register */
5552 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5554 /* clear pool mask register */
5555 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5556 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5558 /* clear vlan mask register */
5559 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5560 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5566 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5568 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5569 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5571 struct ixgbe_hw *hw =
5572 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5574 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5575 mask |= (1 << IXGBE_MISC_VEC_ID);
5576 RTE_SET_USED(queue_id);
5577 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5579 rte_intr_enable(intr_handle);
5585 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5588 struct ixgbe_hw *hw =
5589 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5591 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5592 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5593 RTE_SET_USED(queue_id);
5594 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5600 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5602 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5603 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5605 struct ixgbe_hw *hw =
5606 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5607 struct ixgbe_interrupt *intr =
5608 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5610 if (queue_id < 16) {
5611 ixgbe_disable_intr(hw);
5612 intr->mask |= (1 << queue_id);
5613 ixgbe_enable_intr(dev);
5614 } else if (queue_id < 32) {
5615 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5616 mask &= (1 << queue_id);
5617 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5618 } else if (queue_id < 64) {
5619 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5620 mask &= (1 << (queue_id - 32));
5621 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5623 rte_intr_enable(intr_handle);
5629 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5632 struct ixgbe_hw *hw =
5633 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5634 struct ixgbe_interrupt *intr =
5635 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5637 if (queue_id < 16) {
5638 ixgbe_disable_intr(hw);
5639 intr->mask &= ~(1 << queue_id);
5640 ixgbe_enable_intr(dev);
5641 } else if (queue_id < 32) {
5642 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5643 mask &= ~(1 << queue_id);
5644 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5645 } else if (queue_id < 64) {
5646 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5647 mask &= ~(1 << (queue_id - 32));
5648 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5655 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5656 uint8_t queue, uint8_t msix_vector)
5660 if (direction == -1) {
5662 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5663 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5666 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5668 /* rx or tx cause */
5669 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5670 idx = ((16 * (queue & 1)) + (8 * direction));
5671 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5672 tmp &= ~(0xFF << idx);
5673 tmp |= (msix_vector << idx);
5674 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5679 * set the IVAR registers, mapping interrupt causes to vectors
5681 * pointer to ixgbe_hw struct
5683 * 0 for Rx, 1 for Tx, -1 for other causes
5685 * queue to map the corresponding interrupt to
5687 * the vector to map to the corresponding queue
5690 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5691 uint8_t queue, uint8_t msix_vector)
5695 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5696 if (hw->mac.type == ixgbe_mac_82598EB) {
5697 if (direction == -1)
5699 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5700 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5701 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5702 tmp |= (msix_vector << (8 * (queue & 0x3)));
5703 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5704 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5705 (hw->mac.type == ixgbe_mac_X540)) {
5706 if (direction == -1) {
5708 idx = ((queue & 1) * 8);
5709 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5710 tmp &= ~(0xFF << idx);
5711 tmp |= (msix_vector << idx);
5712 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5714 /* rx or tx causes */
5715 idx = ((16 * (queue & 1)) + (8 * direction));
5716 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5717 tmp &= ~(0xFF << idx);
5718 tmp |= (msix_vector << idx);
5719 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5725 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5727 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5728 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5729 struct ixgbe_hw *hw =
5730 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5732 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5734 /* Configure VF other cause ivar */
5735 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5737 /* won't configure msix register if no mapping is done
5738 * between intr vector and event fd.
5740 if (!rte_intr_dp_is_en(intr_handle))
5743 /* Configure all RX queues of VF */
5744 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5745 /* Force all queue use vector 0,
5746 * as IXGBE_VF_MAXMSIVECOTR = 1
5748 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5749 intr_handle->intr_vec[q_idx] = vector_idx;
5754 * Sets up the hardware to properly generate MSI-X interrupts
5756 * board private structure
5759 ixgbe_configure_msix(struct rte_eth_dev *dev)
5761 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5762 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5763 struct ixgbe_hw *hw =
5764 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5765 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5766 uint32_t vec = IXGBE_MISC_VEC_ID;
5770 /* won't configure msix register if no mapping is done
5771 * between intr vector and event fd
5773 if (!rte_intr_dp_is_en(intr_handle))
5776 if (rte_intr_allow_others(intr_handle))
5777 vec = base = IXGBE_RX_VEC_START;
5779 /* setup GPIE for MSI-x mode */
5780 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5781 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5782 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5783 /* auto clearing and auto setting corresponding bits in EIMS
5784 * when MSI-X interrupt is triggered
5786 if (hw->mac.type == ixgbe_mac_82598EB) {
5787 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5789 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5790 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5792 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5794 /* Populate the IVAR table and set the ITR values to the
5795 * corresponding register.
5797 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5799 /* by default, 1:1 mapping */
5800 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5801 intr_handle->intr_vec[queue_id] = vec;
5802 if (vec < base + intr_handle->nb_efd - 1)
5806 switch (hw->mac.type) {
5807 case ixgbe_mac_82598EB:
5808 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5811 case ixgbe_mac_82599EB:
5812 case ixgbe_mac_X540:
5813 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5818 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5819 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5821 /* set up to autoclear timer, and the vectors */
5822 mask = IXGBE_EIMS_ENABLE_MASK;
5823 mask &= ~(IXGBE_EIMS_OTHER |
5824 IXGBE_EIMS_MAILBOX |
5827 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5830 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5831 uint16_t queue_idx, uint16_t tx_rate)
5833 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5834 uint32_t rf_dec, rf_int;
5836 uint16_t link_speed = dev->data->dev_link.link_speed;
5838 if (queue_idx >= hw->mac.max_tx_queues)
5842 /* Calculate the rate factor values to set */
5843 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5844 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5845 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5847 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5848 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5849 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5850 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5856 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5857 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5860 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5861 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5862 IXGBE_MAX_JUMBO_FRAME_SIZE))
5863 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5864 IXGBE_MMW_SIZE_JUMBO_FRAME);
5866 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5867 IXGBE_MMW_SIZE_DEFAULT);
5869 /* Set RTTBCNRC of queue X */
5870 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5871 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5872 IXGBE_WRITE_FLUSH(hw);
5878 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5879 __attribute__((unused)) uint32_t index,
5880 __attribute__((unused)) uint32_t pool)
5882 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5886 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5887 * operation. Trap this case to avoid exhausting the [very limited]
5888 * set of PF resources used to store VF MAC addresses.
5890 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5892 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5895 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5899 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5901 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5902 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5903 struct ether_addr *mac_addr;
5908 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5909 * not support the deletion of a given MAC address.
5910 * Instead, it imposes to delete all MAC addresses, then to add again
5911 * all MAC addresses with the exception of the one to be deleted.
5913 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5916 * Add again all MAC addresses, with the exception of the deleted one
5917 * and of the permanent MAC address.
5919 for (i = 0, mac_addr = dev->data->mac_addrs;
5920 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5921 /* Skip the deleted MAC address */
5924 /* Skip NULL MAC addresses */
5925 if (is_zero_ether_addr(mac_addr))
5927 /* Skip the permanent MAC address */
5928 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5930 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5933 "Adding again MAC address "
5934 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5936 mac_addr->addr_bytes[0],
5937 mac_addr->addr_bytes[1],
5938 mac_addr->addr_bytes[2],
5939 mac_addr->addr_bytes[3],
5940 mac_addr->addr_bytes[4],
5941 mac_addr->addr_bytes[5],
5947 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5949 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5951 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5954 #define MAC_TYPE_FILTER_SUP(type) do {\
5955 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5956 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5957 (type) != ixgbe_mac_X550EM_a)\
5962 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5963 struct rte_eth_syn_filter *filter,
5966 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5967 struct ixgbe_filter_info *filter_info =
5968 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5972 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5975 syn_info = filter_info->syn_info;
5978 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5980 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5981 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5983 if (filter->hig_pri)
5984 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5986 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5988 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5989 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5991 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5994 filter_info->syn_info = synqf;
5995 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5996 IXGBE_WRITE_FLUSH(hw);
6001 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6002 struct rte_eth_syn_filter *filter)
6004 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6005 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6007 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6008 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6009 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6016 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6017 enum rte_filter_op filter_op,
6020 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6023 MAC_TYPE_FILTER_SUP(hw->mac.type);
6025 if (filter_op == RTE_ETH_FILTER_NOP)
6029 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6034 switch (filter_op) {
6035 case RTE_ETH_FILTER_ADD:
6036 ret = ixgbe_syn_filter_set(dev,
6037 (struct rte_eth_syn_filter *)arg,
6040 case RTE_ETH_FILTER_DELETE:
6041 ret = ixgbe_syn_filter_set(dev,
6042 (struct rte_eth_syn_filter *)arg,
6045 case RTE_ETH_FILTER_GET:
6046 ret = ixgbe_syn_filter_get(dev,
6047 (struct rte_eth_syn_filter *)arg);
6050 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6059 static inline enum ixgbe_5tuple_protocol
6060 convert_protocol_type(uint8_t protocol_value)
6062 if (protocol_value == IPPROTO_TCP)
6063 return IXGBE_FILTER_PROTOCOL_TCP;
6064 else if (protocol_value == IPPROTO_UDP)
6065 return IXGBE_FILTER_PROTOCOL_UDP;
6066 else if (protocol_value == IPPROTO_SCTP)
6067 return IXGBE_FILTER_PROTOCOL_SCTP;
6069 return IXGBE_FILTER_PROTOCOL_NONE;
6072 /* inject a 5-tuple filter to HW */
6074 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6075 struct ixgbe_5tuple_filter *filter)
6077 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6079 uint32_t ftqf, sdpqf;
6080 uint32_t l34timir = 0;
6081 uint8_t mask = 0xff;
6085 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6086 IXGBE_SDPQF_DSTPORT_SHIFT);
6087 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6089 ftqf = (uint32_t)(filter->filter_info.proto &
6090 IXGBE_FTQF_PROTOCOL_MASK);
6091 ftqf |= (uint32_t)((filter->filter_info.priority &
6092 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6093 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6094 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6095 if (filter->filter_info.dst_ip_mask == 0)
6096 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6097 if (filter->filter_info.src_port_mask == 0)
6098 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6099 if (filter->filter_info.dst_port_mask == 0)
6100 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6101 if (filter->filter_info.proto_mask == 0)
6102 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6103 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6104 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6105 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6107 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6108 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6109 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6110 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6112 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6113 l34timir |= (uint32_t)(filter->queue <<
6114 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6115 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6119 * add a 5tuple filter
6122 * dev: Pointer to struct rte_eth_dev.
6123 * index: the index the filter allocates.
6124 * filter: ponter to the filter that will be added.
6125 * rx_queue: the queue id the filter assigned to.
6128 * - On success, zero.
6129 * - On failure, a negative value.
6132 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6133 struct ixgbe_5tuple_filter *filter)
6135 struct ixgbe_filter_info *filter_info =
6136 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6140 * look for an unused 5tuple filter index,
6141 * and insert the filter to list.
6143 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6144 idx = i / (sizeof(uint32_t) * NBBY);
6145 shift = i % (sizeof(uint32_t) * NBBY);
6146 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6147 filter_info->fivetuple_mask[idx] |= 1 << shift;
6149 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6155 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6156 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6160 ixgbe_inject_5tuple_filter(dev, filter);
6166 * remove a 5tuple filter
6169 * dev: Pointer to struct rte_eth_dev.
6170 * filter: the pointer of the filter will be removed.
6173 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6174 struct ixgbe_5tuple_filter *filter)
6176 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6177 struct ixgbe_filter_info *filter_info =
6178 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6179 uint16_t index = filter->index;
6181 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6182 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6183 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6186 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6187 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6188 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6189 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6190 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6194 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6196 struct ixgbe_hw *hw;
6197 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6199 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6201 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6204 /* refuse mtu that requires the support of scattered packets when this
6205 * feature has not been enabled before.
6207 if (!dev->data->scattered_rx &&
6208 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6209 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6213 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6214 * request of the version 2.0 of the mailbox API.
6215 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6216 * of the mailbox API.
6217 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6218 * prior to 3.11.33 which contains the following change:
6219 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6221 ixgbevf_rlpml_set_vf(hw, max_frame);
6223 /* update max frame size */
6224 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6228 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
6229 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6233 static inline struct ixgbe_5tuple_filter *
6234 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6235 struct ixgbe_5tuple_filter_info *key)
6237 struct ixgbe_5tuple_filter *it;
6239 TAILQ_FOREACH(it, filter_list, entries) {
6240 if (memcmp(key, &it->filter_info,
6241 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6248 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6250 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6251 struct ixgbe_5tuple_filter_info *filter_info)
6253 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6254 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6255 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6258 switch (filter->dst_ip_mask) {
6260 filter_info->dst_ip_mask = 0;
6261 filter_info->dst_ip = filter->dst_ip;
6264 filter_info->dst_ip_mask = 1;
6267 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6271 switch (filter->src_ip_mask) {
6273 filter_info->src_ip_mask = 0;
6274 filter_info->src_ip = filter->src_ip;
6277 filter_info->src_ip_mask = 1;
6280 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6284 switch (filter->dst_port_mask) {
6286 filter_info->dst_port_mask = 0;
6287 filter_info->dst_port = filter->dst_port;
6290 filter_info->dst_port_mask = 1;
6293 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6297 switch (filter->src_port_mask) {
6299 filter_info->src_port_mask = 0;
6300 filter_info->src_port = filter->src_port;
6303 filter_info->src_port_mask = 1;
6306 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6310 switch (filter->proto_mask) {
6312 filter_info->proto_mask = 0;
6313 filter_info->proto =
6314 convert_protocol_type(filter->proto);
6317 filter_info->proto_mask = 1;
6320 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6324 filter_info->priority = (uint8_t)filter->priority;
6329 * add or delete a ntuple filter
6332 * dev: Pointer to struct rte_eth_dev.
6333 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6334 * add: if true, add filter, if false, remove filter
6337 * - On success, zero.
6338 * - On failure, a negative value.
6341 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6342 struct rte_eth_ntuple_filter *ntuple_filter,
6345 struct ixgbe_filter_info *filter_info =
6346 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6347 struct ixgbe_5tuple_filter_info filter_5tuple;
6348 struct ixgbe_5tuple_filter *filter;
6351 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6352 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6356 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6357 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6361 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6363 if (filter != NULL && add) {
6364 PMD_DRV_LOG(ERR, "filter exists.");
6367 if (filter == NULL && !add) {
6368 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6373 filter = rte_zmalloc("ixgbe_5tuple_filter",
6374 sizeof(struct ixgbe_5tuple_filter), 0);
6377 (void)rte_memcpy(&filter->filter_info,
6379 sizeof(struct ixgbe_5tuple_filter_info));
6380 filter->queue = ntuple_filter->queue;
6381 ret = ixgbe_add_5tuple_filter(dev, filter);
6387 ixgbe_remove_5tuple_filter(dev, filter);
6393 * get a ntuple filter
6396 * dev: Pointer to struct rte_eth_dev.
6397 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6400 * - On success, zero.
6401 * - On failure, a negative value.
6404 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6405 struct rte_eth_ntuple_filter *ntuple_filter)
6407 struct ixgbe_filter_info *filter_info =
6408 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6409 struct ixgbe_5tuple_filter_info filter_5tuple;
6410 struct ixgbe_5tuple_filter *filter;
6413 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6414 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6418 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6419 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6423 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6425 if (filter == NULL) {
6426 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6429 ntuple_filter->queue = filter->queue;
6434 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6435 * @dev: pointer to rte_eth_dev structure
6436 * @filter_op:operation will be taken.
6437 * @arg: a pointer to specific structure corresponding to the filter_op
6440 * - On success, zero.
6441 * - On failure, a negative value.
6444 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6445 enum rte_filter_op filter_op,
6448 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6451 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6453 if (filter_op == RTE_ETH_FILTER_NOP)
6457 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6462 switch (filter_op) {
6463 case RTE_ETH_FILTER_ADD:
6464 ret = ixgbe_add_del_ntuple_filter(dev,
6465 (struct rte_eth_ntuple_filter *)arg,
6468 case RTE_ETH_FILTER_DELETE:
6469 ret = ixgbe_add_del_ntuple_filter(dev,
6470 (struct rte_eth_ntuple_filter *)arg,
6473 case RTE_ETH_FILTER_GET:
6474 ret = ixgbe_get_ntuple_filter(dev,
6475 (struct rte_eth_ntuple_filter *)arg);
6478 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6486 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6487 struct rte_eth_ethertype_filter *filter,
6490 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6491 struct ixgbe_filter_info *filter_info =
6492 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6496 struct ixgbe_ethertype_filter ethertype_filter;
6498 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6501 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6502 filter->ether_type == ETHER_TYPE_IPv6) {
6503 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6504 " ethertype filter.", filter->ether_type);
6508 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6509 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6512 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6513 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6517 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6518 if (ret >= 0 && add) {
6519 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6520 filter->ether_type);
6523 if (ret < 0 && !add) {
6524 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6525 filter->ether_type);
6530 etqf = IXGBE_ETQF_FILTER_EN;
6531 etqf |= (uint32_t)filter->ether_type;
6532 etqs |= (uint32_t)((filter->queue <<
6533 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6534 IXGBE_ETQS_RX_QUEUE);
6535 etqs |= IXGBE_ETQS_QUEUE_EN;
6537 ethertype_filter.ethertype = filter->ether_type;
6538 ethertype_filter.etqf = etqf;
6539 ethertype_filter.etqs = etqs;
6540 ethertype_filter.conf = FALSE;
6541 ret = ixgbe_ethertype_filter_insert(filter_info,
6544 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6548 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6552 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6553 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6554 IXGBE_WRITE_FLUSH(hw);
6560 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6561 struct rte_eth_ethertype_filter *filter)
6563 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6564 struct ixgbe_filter_info *filter_info =
6565 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6566 uint32_t etqf, etqs;
6569 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6571 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6572 filter->ether_type);
6576 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6577 if (etqf & IXGBE_ETQF_FILTER_EN) {
6578 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6579 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6581 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6582 IXGBE_ETQS_RX_QUEUE_SHIFT;
6589 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6590 * @dev: pointer to rte_eth_dev structure
6591 * @filter_op:operation will be taken.
6592 * @arg: a pointer to specific structure corresponding to the filter_op
6595 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6596 enum rte_filter_op filter_op,
6599 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6602 MAC_TYPE_FILTER_SUP(hw->mac.type);
6604 if (filter_op == RTE_ETH_FILTER_NOP)
6608 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6613 switch (filter_op) {
6614 case RTE_ETH_FILTER_ADD:
6615 ret = ixgbe_add_del_ethertype_filter(dev,
6616 (struct rte_eth_ethertype_filter *)arg,
6619 case RTE_ETH_FILTER_DELETE:
6620 ret = ixgbe_add_del_ethertype_filter(dev,
6621 (struct rte_eth_ethertype_filter *)arg,
6624 case RTE_ETH_FILTER_GET:
6625 ret = ixgbe_get_ethertype_filter(dev,
6626 (struct rte_eth_ethertype_filter *)arg);
6629 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6637 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6638 enum rte_filter_type filter_type,
6639 enum rte_filter_op filter_op,
6644 switch (filter_type) {
6645 case RTE_ETH_FILTER_NTUPLE:
6646 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6648 case RTE_ETH_FILTER_ETHERTYPE:
6649 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6651 case RTE_ETH_FILTER_SYN:
6652 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6654 case RTE_ETH_FILTER_FDIR:
6655 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6657 case RTE_ETH_FILTER_L2_TUNNEL:
6658 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6660 case RTE_ETH_FILTER_GENERIC:
6661 if (filter_op != RTE_ETH_FILTER_GET)
6663 *(const void **)arg = &ixgbe_flow_ops;
6666 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6676 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6677 u8 **mc_addr_ptr, u32 *vmdq)
6682 mc_addr = *mc_addr_ptr;
6683 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6688 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6689 struct ether_addr *mc_addr_set,
6690 uint32_t nb_mc_addr)
6692 struct ixgbe_hw *hw;
6695 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6696 mc_addr_list = (u8 *)mc_addr_set;
6697 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6698 ixgbe_dev_addr_list_itr, TRUE);
6702 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6704 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6705 uint64_t systime_cycles;
6707 switch (hw->mac.type) {
6708 case ixgbe_mac_X550:
6709 case ixgbe_mac_X550EM_x:
6710 case ixgbe_mac_X550EM_a:
6711 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6712 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6713 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6717 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6718 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6722 return systime_cycles;
6726 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6728 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6729 uint64_t rx_tstamp_cycles;
6731 switch (hw->mac.type) {
6732 case ixgbe_mac_X550:
6733 case ixgbe_mac_X550EM_x:
6734 case ixgbe_mac_X550EM_a:
6735 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6736 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6737 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6741 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6742 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6743 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6747 return rx_tstamp_cycles;
6751 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6753 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6754 uint64_t tx_tstamp_cycles;
6756 switch (hw->mac.type) {
6757 case ixgbe_mac_X550:
6758 case ixgbe_mac_X550EM_x:
6759 case ixgbe_mac_X550EM_a:
6760 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6761 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6762 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6766 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6767 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6768 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6772 return tx_tstamp_cycles;
6776 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6778 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6779 struct ixgbe_adapter *adapter =
6780 (struct ixgbe_adapter *)dev->data->dev_private;
6781 struct rte_eth_link link;
6782 uint32_t incval = 0;
6785 /* Get current link speed. */
6786 memset(&link, 0, sizeof(link));
6787 ixgbe_dev_link_update(dev, 1);
6788 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6790 switch (link.link_speed) {
6791 case ETH_SPEED_NUM_100M:
6792 incval = IXGBE_INCVAL_100;
6793 shift = IXGBE_INCVAL_SHIFT_100;
6795 case ETH_SPEED_NUM_1G:
6796 incval = IXGBE_INCVAL_1GB;
6797 shift = IXGBE_INCVAL_SHIFT_1GB;
6799 case ETH_SPEED_NUM_10G:
6801 incval = IXGBE_INCVAL_10GB;
6802 shift = IXGBE_INCVAL_SHIFT_10GB;
6806 switch (hw->mac.type) {
6807 case ixgbe_mac_X550:
6808 case ixgbe_mac_X550EM_x:
6809 case ixgbe_mac_X550EM_a:
6810 /* Independent of link speed. */
6812 /* Cycles read will be interpreted as ns. */
6815 case ixgbe_mac_X540:
6816 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6818 case ixgbe_mac_82599EB:
6819 incval >>= IXGBE_INCVAL_SHIFT_82599;
6820 shift -= IXGBE_INCVAL_SHIFT_82599;
6821 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6822 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6825 /* Not supported. */
6829 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6830 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6831 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6833 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6834 adapter->systime_tc.cc_shift = shift;
6835 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6837 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6838 adapter->rx_tstamp_tc.cc_shift = shift;
6839 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6841 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6842 adapter->tx_tstamp_tc.cc_shift = shift;
6843 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6847 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6849 struct ixgbe_adapter *adapter =
6850 (struct ixgbe_adapter *)dev->data->dev_private;
6852 adapter->systime_tc.nsec += delta;
6853 adapter->rx_tstamp_tc.nsec += delta;
6854 adapter->tx_tstamp_tc.nsec += delta;
6860 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6863 struct ixgbe_adapter *adapter =
6864 (struct ixgbe_adapter *)dev->data->dev_private;
6866 ns = rte_timespec_to_ns(ts);
6867 /* Set the timecounters to a new value. */
6868 adapter->systime_tc.nsec = ns;
6869 adapter->rx_tstamp_tc.nsec = ns;
6870 adapter->tx_tstamp_tc.nsec = ns;
6876 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6878 uint64_t ns, systime_cycles;
6879 struct ixgbe_adapter *adapter =
6880 (struct ixgbe_adapter *)dev->data->dev_private;
6882 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6883 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6884 *ts = rte_ns_to_timespec(ns);
6890 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6892 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6896 /* Stop the timesync system time. */
6897 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6898 /* Reset the timesync system time value. */
6899 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6900 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6902 /* Enable system time for platforms where it isn't on by default. */
6903 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6904 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6905 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6907 ixgbe_start_timecounters(dev);
6909 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6910 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6912 IXGBE_ETQF_FILTER_EN |
6915 /* Enable timestamping of received PTP packets. */
6916 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6917 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6918 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6920 /* Enable timestamping of transmitted PTP packets. */
6921 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6922 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6923 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6925 IXGBE_WRITE_FLUSH(hw);
6931 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6933 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6936 /* Disable timestamping of transmitted PTP packets. */
6937 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6938 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6939 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6941 /* Disable timestamping of received PTP packets. */
6942 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6943 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6944 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6946 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6947 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6949 /* Stop incrementating the System Time registers. */
6950 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6956 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6957 struct timespec *timestamp,
6958 uint32_t flags __rte_unused)
6960 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6961 struct ixgbe_adapter *adapter =
6962 (struct ixgbe_adapter *)dev->data->dev_private;
6963 uint32_t tsync_rxctl;
6964 uint64_t rx_tstamp_cycles;
6967 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6968 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6971 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6972 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6973 *timestamp = rte_ns_to_timespec(ns);
6979 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6980 struct timespec *timestamp)
6982 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6983 struct ixgbe_adapter *adapter =
6984 (struct ixgbe_adapter *)dev->data->dev_private;
6985 uint32_t tsync_txctl;
6986 uint64_t tx_tstamp_cycles;
6989 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6990 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6993 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6994 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6995 *timestamp = rte_ns_to_timespec(ns);
7001 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7003 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7006 const struct reg_info *reg_group;
7007 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7008 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7010 while ((reg_group = reg_set[g_ind++]))
7011 count += ixgbe_regs_group_count(reg_group);
7017 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7021 const struct reg_info *reg_group;
7023 while ((reg_group = ixgbevf_regs[g_ind++]))
7024 count += ixgbe_regs_group_count(reg_group);
7030 ixgbe_get_regs(struct rte_eth_dev *dev,
7031 struct rte_dev_reg_info *regs)
7033 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7034 uint32_t *data = regs->data;
7037 const struct reg_info *reg_group;
7038 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7039 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7042 regs->length = ixgbe_get_reg_length(dev);
7043 regs->width = sizeof(uint32_t);
7047 /* Support only full register dump */
7048 if ((regs->length == 0) ||
7049 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7050 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7052 while ((reg_group = reg_set[g_ind++]))
7053 count += ixgbe_read_regs_group(dev, &data[count],
7062 ixgbevf_get_regs(struct rte_eth_dev *dev,
7063 struct rte_dev_reg_info *regs)
7065 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7066 uint32_t *data = regs->data;
7069 const struct reg_info *reg_group;
7072 regs->length = ixgbevf_get_reg_length(dev);
7073 regs->width = sizeof(uint32_t);
7077 /* Support only full register dump */
7078 if ((regs->length == 0) ||
7079 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7080 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7082 while ((reg_group = ixgbevf_regs[g_ind++]))
7083 count += ixgbe_read_regs_group(dev, &data[count],
7092 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7094 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7096 /* Return unit is byte count */
7097 return hw->eeprom.word_size * 2;
7101 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7102 struct rte_dev_eeprom_info *in_eeprom)
7104 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7105 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7106 uint16_t *data = in_eeprom->data;
7109 first = in_eeprom->offset >> 1;
7110 length = in_eeprom->length >> 1;
7111 if ((first > hw->eeprom.word_size) ||
7112 ((first + length) > hw->eeprom.word_size))
7115 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7117 return eeprom->ops.read_buffer(hw, first, length, data);
7121 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7122 struct rte_dev_eeprom_info *in_eeprom)
7124 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7125 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7126 uint16_t *data = in_eeprom->data;
7129 first = in_eeprom->offset >> 1;
7130 length = in_eeprom->length >> 1;
7131 if ((first > hw->eeprom.word_size) ||
7132 ((first + length) > hw->eeprom.word_size))
7135 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7137 return eeprom->ops.write_buffer(hw, first, length, data);
7141 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7143 case ixgbe_mac_X550:
7144 case ixgbe_mac_X550EM_x:
7145 case ixgbe_mac_X550EM_a:
7146 return ETH_RSS_RETA_SIZE_512;
7147 case ixgbe_mac_X550_vf:
7148 case ixgbe_mac_X550EM_x_vf:
7149 case ixgbe_mac_X550EM_a_vf:
7150 return ETH_RSS_RETA_SIZE_64;
7152 return ETH_RSS_RETA_SIZE_128;
7157 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7159 case ixgbe_mac_X550:
7160 case ixgbe_mac_X550EM_x:
7161 case ixgbe_mac_X550EM_a:
7162 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7163 return IXGBE_RETA(reta_idx >> 2);
7165 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7166 case ixgbe_mac_X550_vf:
7167 case ixgbe_mac_X550EM_x_vf:
7168 case ixgbe_mac_X550EM_a_vf:
7169 return IXGBE_VFRETA(reta_idx >> 2);
7171 return IXGBE_RETA(reta_idx >> 2);
7176 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7178 case ixgbe_mac_X550_vf:
7179 case ixgbe_mac_X550EM_x_vf:
7180 case ixgbe_mac_X550EM_a_vf:
7181 return IXGBE_VFMRQC;
7188 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7190 case ixgbe_mac_X550_vf:
7191 case ixgbe_mac_X550EM_x_vf:
7192 case ixgbe_mac_X550EM_a_vf:
7193 return IXGBE_VFRSSRK(i);
7195 return IXGBE_RSSRK(i);
7200 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7202 case ixgbe_mac_82599_vf:
7203 case ixgbe_mac_X540_vf:
7211 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7212 struct rte_eth_dcb_info *dcb_info)
7214 struct ixgbe_dcb_config *dcb_config =
7215 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7216 struct ixgbe_dcb_tc_config *tc;
7219 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7220 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7222 dcb_info->nb_tcs = 1;
7224 if (dcb_config->vt_mode) { /* vt is enabled*/
7225 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7226 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7227 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7228 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7229 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7230 for (j = 0; j < dcb_info->nb_tcs; j++) {
7231 dcb_info->tc_queue.tc_rxq[i][j].base =
7232 i * dcb_info->nb_tcs + j;
7233 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7234 dcb_info->tc_queue.tc_txq[i][j].base =
7235 i * dcb_info->nb_tcs + j;
7236 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7239 } else { /* vt is disabled*/
7240 struct rte_eth_dcb_rx_conf *rx_conf =
7241 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7242 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7243 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7244 if (dcb_info->nb_tcs == ETH_4_TCS) {
7245 for (i = 0; i < dcb_info->nb_tcs; i++) {
7246 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7247 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7249 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7250 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7251 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7252 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7253 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7254 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7255 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7256 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7257 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7258 for (i = 0; i < dcb_info->nb_tcs; i++) {
7259 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7260 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7262 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7263 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7264 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7265 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7266 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7267 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7268 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7269 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7270 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7271 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7272 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7273 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7274 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7275 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7276 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7277 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7280 for (i = 0; i < dcb_info->nb_tcs; i++) {
7281 tc = &dcb_config->tc_config[i];
7282 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7287 /* Update e-tag ether type */
7289 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7290 uint16_t ether_type)
7292 uint32_t etag_etype;
7294 if (hw->mac.type != ixgbe_mac_X550 &&
7295 hw->mac.type != ixgbe_mac_X550EM_x &&
7296 hw->mac.type != ixgbe_mac_X550EM_a) {
7300 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7301 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7302 etag_etype |= ether_type;
7303 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7304 IXGBE_WRITE_FLUSH(hw);
7309 /* Config l2 tunnel ether type */
7311 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7312 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7315 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7316 struct ixgbe_l2_tn_info *l2_tn_info =
7317 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7319 if (l2_tunnel == NULL)
7322 switch (l2_tunnel->l2_tunnel_type) {
7323 case RTE_L2_TUNNEL_TYPE_E_TAG:
7324 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7325 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7328 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7336 /* Enable e-tag tunnel */
7338 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7340 uint32_t etag_etype;
7342 if (hw->mac.type != ixgbe_mac_X550 &&
7343 hw->mac.type != ixgbe_mac_X550EM_x &&
7344 hw->mac.type != ixgbe_mac_X550EM_a) {
7348 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7349 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7350 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7351 IXGBE_WRITE_FLUSH(hw);
7356 /* Enable l2 tunnel */
7358 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7359 enum rte_eth_tunnel_type l2_tunnel_type)
7362 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7363 struct ixgbe_l2_tn_info *l2_tn_info =
7364 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7366 switch (l2_tunnel_type) {
7367 case RTE_L2_TUNNEL_TYPE_E_TAG:
7368 l2_tn_info->e_tag_en = TRUE;
7369 ret = ixgbe_e_tag_enable(hw);
7372 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7380 /* Disable e-tag tunnel */
7382 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7384 uint32_t etag_etype;
7386 if (hw->mac.type != ixgbe_mac_X550 &&
7387 hw->mac.type != ixgbe_mac_X550EM_x &&
7388 hw->mac.type != ixgbe_mac_X550EM_a) {
7392 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7393 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7394 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7395 IXGBE_WRITE_FLUSH(hw);
7400 /* Disable l2 tunnel */
7402 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7403 enum rte_eth_tunnel_type l2_tunnel_type)
7406 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7407 struct ixgbe_l2_tn_info *l2_tn_info =
7408 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7410 switch (l2_tunnel_type) {
7411 case RTE_L2_TUNNEL_TYPE_E_TAG:
7412 l2_tn_info->e_tag_en = FALSE;
7413 ret = ixgbe_e_tag_disable(hw);
7416 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7425 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7426 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7429 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7430 uint32_t i, rar_entries;
7431 uint32_t rar_low, rar_high;
7433 if (hw->mac.type != ixgbe_mac_X550 &&
7434 hw->mac.type != ixgbe_mac_X550EM_x &&
7435 hw->mac.type != ixgbe_mac_X550EM_a) {
7439 rar_entries = ixgbe_get_num_rx_addrs(hw);
7441 for (i = 1; i < rar_entries; i++) {
7442 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7443 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7444 if ((rar_high & IXGBE_RAH_AV) &&
7445 (rar_high & IXGBE_RAH_ADTYPE) &&
7446 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7447 l2_tunnel->tunnel_id)) {
7448 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7449 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7451 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7461 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7462 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7465 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7466 uint32_t i, rar_entries;
7467 uint32_t rar_low, rar_high;
7469 if (hw->mac.type != ixgbe_mac_X550 &&
7470 hw->mac.type != ixgbe_mac_X550EM_x &&
7471 hw->mac.type != ixgbe_mac_X550EM_a) {
7475 /* One entry for one tunnel. Try to remove potential existing entry. */
7476 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7478 rar_entries = ixgbe_get_num_rx_addrs(hw);
7480 for (i = 1; i < rar_entries; i++) {
7481 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7482 if (rar_high & IXGBE_RAH_AV) {
7485 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7486 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7487 rar_low = l2_tunnel->tunnel_id;
7489 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7490 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7496 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7497 " Please remove a rule before adding a new one.");
7501 static inline struct ixgbe_l2_tn_filter *
7502 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7503 struct ixgbe_l2_tn_key *key)
7507 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7511 return l2_tn_info->hash_map[ret];
7515 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7516 struct ixgbe_l2_tn_filter *l2_tn_filter)
7520 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7521 &l2_tn_filter->key);
7525 "Failed to insert L2 tunnel filter"
7526 " to hash table %d!",
7531 l2_tn_info->hash_map[ret] = l2_tn_filter;
7533 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7539 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7540 struct ixgbe_l2_tn_key *key)
7543 struct ixgbe_l2_tn_filter *l2_tn_filter;
7545 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7549 "No such L2 tunnel filter to delete %d!",
7554 l2_tn_filter = l2_tn_info->hash_map[ret];
7555 l2_tn_info->hash_map[ret] = NULL;
7557 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7558 rte_free(l2_tn_filter);
7563 /* Add l2 tunnel filter */
7565 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7566 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7570 struct ixgbe_l2_tn_info *l2_tn_info =
7571 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7572 struct ixgbe_l2_tn_key key;
7573 struct ixgbe_l2_tn_filter *node;
7576 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7577 key.tn_id = l2_tunnel->tunnel_id;
7579 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7583 "The L2 tunnel filter already exists!");
7587 node = rte_zmalloc("ixgbe_l2_tn",
7588 sizeof(struct ixgbe_l2_tn_filter),
7593 (void)rte_memcpy(&node->key,
7595 sizeof(struct ixgbe_l2_tn_key));
7596 node->pool = l2_tunnel->pool;
7597 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7604 switch (l2_tunnel->l2_tunnel_type) {
7605 case RTE_L2_TUNNEL_TYPE_E_TAG:
7606 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7609 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7614 if ((!restore) && (ret < 0))
7615 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7620 /* Delete l2 tunnel filter */
7622 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7623 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7626 struct ixgbe_l2_tn_info *l2_tn_info =
7627 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7628 struct ixgbe_l2_tn_key key;
7630 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7631 key.tn_id = l2_tunnel->tunnel_id;
7632 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7636 switch (l2_tunnel->l2_tunnel_type) {
7637 case RTE_L2_TUNNEL_TYPE_E_TAG:
7638 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7641 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7650 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7651 * @dev: pointer to rte_eth_dev structure
7652 * @filter_op:operation will be taken.
7653 * @arg: a pointer to specific structure corresponding to the filter_op
7656 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7657 enum rte_filter_op filter_op,
7662 if (filter_op == RTE_ETH_FILTER_NOP)
7666 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7671 switch (filter_op) {
7672 case RTE_ETH_FILTER_ADD:
7673 ret = ixgbe_dev_l2_tunnel_filter_add
7675 (struct rte_eth_l2_tunnel_conf *)arg,
7678 case RTE_ETH_FILTER_DELETE:
7679 ret = ixgbe_dev_l2_tunnel_filter_del
7681 (struct rte_eth_l2_tunnel_conf *)arg);
7684 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7692 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7696 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7698 if (hw->mac.type != ixgbe_mac_X550 &&
7699 hw->mac.type != ixgbe_mac_X550EM_x &&
7700 hw->mac.type != ixgbe_mac_X550EM_a) {
7704 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7705 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7707 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7708 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7713 /* Enable l2 tunnel forwarding */
7715 ixgbe_dev_l2_tunnel_forwarding_enable
7716 (struct rte_eth_dev *dev,
7717 enum rte_eth_tunnel_type l2_tunnel_type)
7719 struct ixgbe_l2_tn_info *l2_tn_info =
7720 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7723 switch (l2_tunnel_type) {
7724 case RTE_L2_TUNNEL_TYPE_E_TAG:
7725 l2_tn_info->e_tag_fwd_en = TRUE;
7726 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7729 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7737 /* Disable l2 tunnel forwarding */
7739 ixgbe_dev_l2_tunnel_forwarding_disable
7740 (struct rte_eth_dev *dev,
7741 enum rte_eth_tunnel_type l2_tunnel_type)
7743 struct ixgbe_l2_tn_info *l2_tn_info =
7744 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7747 switch (l2_tunnel_type) {
7748 case RTE_L2_TUNNEL_TYPE_E_TAG:
7749 l2_tn_info->e_tag_fwd_en = FALSE;
7750 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7753 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7762 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7763 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7766 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7768 uint32_t vmtir, vmvir;
7769 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7771 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7773 "VF id %u should be less than %u",
7779 if (hw->mac.type != ixgbe_mac_X550 &&
7780 hw->mac.type != ixgbe_mac_X550EM_x &&
7781 hw->mac.type != ixgbe_mac_X550EM_a) {
7786 vmtir = l2_tunnel->tunnel_id;
7790 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7792 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7793 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7795 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7796 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7801 /* Enable l2 tunnel tag insertion */
7803 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7804 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7808 switch (l2_tunnel->l2_tunnel_type) {
7809 case RTE_L2_TUNNEL_TYPE_E_TAG:
7810 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7813 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7821 /* Disable l2 tunnel tag insertion */
7823 ixgbe_dev_l2_tunnel_insertion_disable
7824 (struct rte_eth_dev *dev,
7825 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7829 switch (l2_tunnel->l2_tunnel_type) {
7830 case RTE_L2_TUNNEL_TYPE_E_TAG:
7831 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7834 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7843 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7848 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7850 if (hw->mac.type != ixgbe_mac_X550 &&
7851 hw->mac.type != ixgbe_mac_X550EM_x &&
7852 hw->mac.type != ixgbe_mac_X550EM_a) {
7856 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7858 qde |= IXGBE_QDE_STRIP_TAG;
7860 qde &= ~IXGBE_QDE_STRIP_TAG;
7861 qde &= ~IXGBE_QDE_READ;
7862 qde |= IXGBE_QDE_WRITE;
7863 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7868 /* Enable l2 tunnel tag stripping */
7870 ixgbe_dev_l2_tunnel_stripping_enable
7871 (struct rte_eth_dev *dev,
7872 enum rte_eth_tunnel_type l2_tunnel_type)
7876 switch (l2_tunnel_type) {
7877 case RTE_L2_TUNNEL_TYPE_E_TAG:
7878 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7881 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7889 /* Disable l2 tunnel tag stripping */
7891 ixgbe_dev_l2_tunnel_stripping_disable
7892 (struct rte_eth_dev *dev,
7893 enum rte_eth_tunnel_type l2_tunnel_type)
7897 switch (l2_tunnel_type) {
7898 case RTE_L2_TUNNEL_TYPE_E_TAG:
7899 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7902 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7910 /* Enable/disable l2 tunnel offload functions */
7912 ixgbe_dev_l2_tunnel_offload_set
7913 (struct rte_eth_dev *dev,
7914 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7920 if (l2_tunnel == NULL)
7924 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7926 ret = ixgbe_dev_l2_tunnel_enable(
7928 l2_tunnel->l2_tunnel_type);
7930 ret = ixgbe_dev_l2_tunnel_disable(
7932 l2_tunnel->l2_tunnel_type);
7935 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7937 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7941 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7946 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7948 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7950 l2_tunnel->l2_tunnel_type);
7952 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7954 l2_tunnel->l2_tunnel_type);
7957 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7959 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7961 l2_tunnel->l2_tunnel_type);
7963 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7965 l2_tunnel->l2_tunnel_type);
7972 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7975 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7976 IXGBE_WRITE_FLUSH(hw);
7981 /* There's only one register for VxLAN UDP port.
7982 * So, we cannot add several ports. Will update it.
7985 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7989 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7993 return ixgbe_update_vxlan_port(hw, port);
7996 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7997 * UDP port, it must have a value.
7998 * So, will reset it to the original value 0.
8001 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8006 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8008 if (cur_port != port) {
8009 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8013 return ixgbe_update_vxlan_port(hw, 0);
8016 /* Add UDP tunneling port */
8018 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8019 struct rte_eth_udp_tunnel *udp_tunnel)
8022 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8024 if (hw->mac.type != ixgbe_mac_X550 &&
8025 hw->mac.type != ixgbe_mac_X550EM_x &&
8026 hw->mac.type != ixgbe_mac_X550EM_a) {
8030 if (udp_tunnel == NULL)
8033 switch (udp_tunnel->prot_type) {
8034 case RTE_TUNNEL_TYPE_VXLAN:
8035 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8038 case RTE_TUNNEL_TYPE_GENEVE:
8039 case RTE_TUNNEL_TYPE_TEREDO:
8040 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8045 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8053 /* Remove UDP tunneling port */
8055 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8056 struct rte_eth_udp_tunnel *udp_tunnel)
8059 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8061 if (hw->mac.type != ixgbe_mac_X550 &&
8062 hw->mac.type != ixgbe_mac_X550EM_x &&
8063 hw->mac.type != ixgbe_mac_X550EM_a) {
8067 if (udp_tunnel == NULL)
8070 switch (udp_tunnel->prot_type) {
8071 case RTE_TUNNEL_TYPE_VXLAN:
8072 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8074 case RTE_TUNNEL_TYPE_GENEVE:
8075 case RTE_TUNNEL_TYPE_TEREDO:
8076 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8080 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8089 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8091 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8093 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8097 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8099 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8101 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8104 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8106 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8109 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8112 /* PF reset VF event */
8113 if (in_msg == IXGBE_PF_CONTROL_MSG)
8114 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8118 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8122 struct ixgbe_interrupt *intr =
8123 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8124 ixgbevf_intr_disable(hw);
8126 /* read-on-clear nic registers here */
8127 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8130 /* only one misc vector supported - mailbox */
8131 eicr &= IXGBE_VTEICR_MASK;
8132 if (eicr == IXGBE_MISC_VEC_ID)
8133 intr->flags |= IXGBE_FLAG_MAILBOX;
8139 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8141 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8142 struct ixgbe_interrupt *intr =
8143 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8145 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8146 ixgbevf_mbx_process(dev);
8147 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8150 ixgbevf_intr_enable(hw);
8156 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8159 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8161 ixgbevf_dev_interrupt_get_status(dev);
8162 ixgbevf_dev_interrupt_action(dev);
8166 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8167 * @hw: pointer to hardware structure
8169 * Stops the transmit data path and waits for the HW to internally empty
8170 * the Tx security block
8172 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8174 #define IXGBE_MAX_SECTX_POLL 40
8179 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8180 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8181 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8182 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8183 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8184 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8186 /* Use interrupt-safe sleep just in case */
8190 /* For informational purposes only */
8191 if (i >= IXGBE_MAX_SECTX_POLL)
8192 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8193 "path fully disabled. Continuing with init.\n");
8195 return IXGBE_SUCCESS;
8199 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8200 * @hw: pointer to hardware structure
8202 * Enables the transmit data path.
8204 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8208 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8209 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8210 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8211 IXGBE_WRITE_FLUSH(hw);
8213 return IXGBE_SUCCESS;
8217 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8219 struct ixgbe_hw *hw;
8220 struct rte_eth_dev *dev;
8223 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8225 dev = &rte_eth_devices[port];
8226 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8228 /* Stop the data paths */
8229 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8233 * As no ixgbe_disable_sec_rx_path equivalent is
8234 * implemented for tx in the base code, and we are
8235 * not allowed to modify the base code in DPDK, so
8236 * just call the hand-written one directly for now.
8237 * The hardware support has been checked by
8238 * ixgbe_disable_sec_rx_path().
8240 ixgbe_disable_sec_tx_path_generic(hw);
8242 /* Enable Ethernet CRC (required by MACsec offload) */
8243 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8244 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8245 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8247 /* Enable the TX and RX crypto engines */
8248 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8249 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8250 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8252 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8253 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8254 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8256 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8257 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8259 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8261 /* Enable SA lookup */
8262 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8263 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8264 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8265 IXGBE_LSECTXCTRL_AUTH;
8266 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8267 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8268 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8269 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8271 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8272 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8273 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8274 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8276 ctrl |= IXGBE_LSECRXCTRL_RP;
8278 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8279 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8281 /* Start the data paths */
8282 ixgbe_enable_sec_rx_path(hw);
8285 * As no ixgbe_enable_sec_rx_path equivalent is
8286 * implemented for tx in the base code, and we are
8287 * not allowed to modify the base code in DPDK, so
8288 * just call the hand-written one directly for now.
8290 ixgbe_enable_sec_tx_path_generic(hw);
8296 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8298 struct ixgbe_hw *hw;
8299 struct rte_eth_dev *dev;
8302 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8304 dev = &rte_eth_devices[port];
8305 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8307 /* Stop the data paths */
8308 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8312 * As no ixgbe_disable_sec_rx_path equivalent is
8313 * implemented for tx in the base code, and we are
8314 * not allowed to modify the base code in DPDK, so
8315 * just call the hand-written one directly for now.
8316 * The hardware support has been checked by
8317 * ixgbe_disable_sec_rx_path().
8319 ixgbe_disable_sec_tx_path_generic(hw);
8321 /* Disable the TX and RX crypto engines */
8322 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8323 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8324 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8326 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8327 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8328 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8330 /* Disable SA lookup */
8331 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8332 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8333 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8334 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8336 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8337 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8338 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8339 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8341 /* Start the data paths */
8342 ixgbe_enable_sec_rx_path(hw);
8345 * As no ixgbe_enable_sec_rx_path equivalent is
8346 * implemented for tx in the base code, and we are
8347 * not allowed to modify the base code in DPDK, so
8348 * just call the hand-written one directly for now.
8350 ixgbe_enable_sec_tx_path_generic(hw);
8356 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8358 struct ixgbe_hw *hw;
8359 struct rte_eth_dev *dev;
8362 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8364 dev = &rte_eth_devices[port];
8365 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8367 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8368 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8370 ctrl = mac[4] | (mac[5] << 8);
8371 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8377 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8379 struct ixgbe_hw *hw;
8380 struct rte_eth_dev *dev;
8383 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8385 dev = &rte_eth_devices[port];
8386 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8388 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8389 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8391 pi = rte_cpu_to_be_16(pi);
8392 ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8393 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8399 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8400 uint32_t pn, uint8_t *key)
8402 struct ixgbe_hw *hw;
8403 struct rte_eth_dev *dev;
8406 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8408 dev = &rte_eth_devices[port];
8409 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8411 if (idx != 0 && idx != 1)
8417 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8419 /* Set the PN and key */
8420 pn = rte_cpu_to_be_32(pn);
8422 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8424 for (i = 0; i < 4; i++) {
8425 ctrl = (key[i * 4 + 0] << 0) |
8426 (key[i * 4 + 1] << 8) |
8427 (key[i * 4 + 2] << 16) |
8428 (key[i * 4 + 3] << 24);
8429 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8432 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8434 for (i = 0; i < 4; i++) {
8435 ctrl = (key[i * 4 + 0] << 0) |
8436 (key[i * 4 + 1] << 8) |
8437 (key[i * 4 + 2] << 16) |
8438 (key[i * 4 + 3] << 24);
8439 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8443 /* Set AN and select the SA */
8444 ctrl = (an << idx * 2) | (idx << 4);
8445 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8451 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8452 uint32_t pn, uint8_t *key)
8454 struct ixgbe_hw *hw;
8455 struct rte_eth_dev *dev;
8458 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8460 dev = &rte_eth_devices[port];
8461 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8463 if (idx != 0 && idx != 1)
8470 pn = rte_cpu_to_be_32(pn);
8471 IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8474 for (i = 0; i < 4; i++) {
8475 ctrl = (key[i * 4 + 0] << 0) |
8476 (key[i * 4 + 1] << 8) |
8477 (key[i * 4 + 2] << 16) |
8478 (key[i * 4 + 3] << 24);
8479 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8482 /* Set the AN and validate the SA */
8483 ctrl = an | (1 << 2);
8484 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8489 /* restore n-tuple filter */
8491 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8493 struct ixgbe_filter_info *filter_info =
8494 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8495 struct ixgbe_5tuple_filter *node;
8497 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8498 ixgbe_inject_5tuple_filter(dev, node);
8502 /* restore ethernet type filter */
8504 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8506 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8507 struct ixgbe_filter_info *filter_info =
8508 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8511 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8512 if (filter_info->ethertype_mask & (1 << i)) {
8513 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8514 filter_info->ethertype_filters[i].etqf);
8515 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8516 filter_info->ethertype_filters[i].etqs);
8517 IXGBE_WRITE_FLUSH(hw);
8522 /* restore SYN filter */
8524 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8526 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8527 struct ixgbe_filter_info *filter_info =
8528 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8531 synqf = filter_info->syn_info;
8533 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8534 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8535 IXGBE_WRITE_FLUSH(hw);
8539 /* restore L2 tunnel filter */
8541 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8543 struct ixgbe_l2_tn_info *l2_tn_info =
8544 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8545 struct ixgbe_l2_tn_filter *node;
8546 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8548 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8549 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8550 l2_tn_conf.tunnel_id = node->key.tn_id;
8551 l2_tn_conf.pool = node->pool;
8552 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8557 ixgbe_filter_restore(struct rte_eth_dev *dev)
8559 ixgbe_ntuple_filter_restore(dev);
8560 ixgbe_ethertype_filter_restore(dev);
8561 ixgbe_syn_filter_restore(dev);
8562 ixgbe_fdir_filter_restore(dev);
8563 ixgbe_l2_tn_filter_restore(dev);
8569 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8571 struct ixgbe_l2_tn_info *l2_tn_info =
8572 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8573 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8575 if (l2_tn_info->e_tag_en)
8576 (void)ixgbe_e_tag_enable(hw);
8578 if (l2_tn_info->e_tag_fwd_en)
8579 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8581 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8584 /* remove all the n-tuple filters */
8586 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8588 struct ixgbe_filter_info *filter_info =
8589 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8590 struct ixgbe_5tuple_filter *p_5tuple;
8592 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8593 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8596 /* remove all the ether type filters */
8598 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8600 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8601 struct ixgbe_filter_info *filter_info =
8602 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8605 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8606 if (filter_info->ethertype_mask & (1 << i) &&
8607 !filter_info->ethertype_filters[i].conf) {
8608 (void)ixgbe_ethertype_filter_remove(filter_info,
8610 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8611 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8612 IXGBE_WRITE_FLUSH(hw);
8617 /* remove the SYN filter */
8619 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8621 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8622 struct ixgbe_filter_info *filter_info =
8623 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8625 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8626 filter_info->syn_info = 0;
8628 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8629 IXGBE_WRITE_FLUSH(hw);
8633 /* remove all the L2 tunnel filters */
8635 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8637 struct ixgbe_l2_tn_info *l2_tn_info =
8638 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8639 struct ixgbe_l2_tn_filter *l2_tn_filter;
8640 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8643 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8644 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8645 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8646 l2_tn_conf.pool = l2_tn_filter->pool;
8647 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8655 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8656 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8657 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8658 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8659 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8660 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");