drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <ethdev_driver.h>
  31 #include <ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIB_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 304                         struct ixgbe_5tuple_filter *filter);
 305 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 306                         struct ixgbe_5tuple_filter *filter);
 307 static int ixgbe_dev_flow_ops_get(struct rte_eth_dev *dev,
 308                                   const struct rte_flow_ops **ops);
 309 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 310
 311 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 312                                       struct rte_ether_addr *mc_addr_set,
 313                                       uint32_t nb_mc_addr);
 314 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 315                                    struct rte_eth_dcb_info *dcb_info);
 316
 317 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 318 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 319                             struct rte_dev_reg_info *regs);
 320 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 321 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 322                                 struct rte_dev_eeprom_info *eeprom);
 323 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325
 326 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 327                                  struct rte_eth_dev_module_info *modinfo);
 328 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 329                                    struct rte_dev_eeprom_info *info);
 330
 331 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 332 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 333                                 struct rte_dev_reg_info *regs);
 334
 335 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 337 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 338                                             struct timespec *timestamp,
 339                                             uint32_t flags);
 340 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 341                                             struct timespec *timestamp);
 342 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 343 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 344                                    struct timespec *timestamp);
 345 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 346                                    const struct timespec *timestamp);
 347 static void ixgbevf_dev_interrupt_handler(void *param);
 348
 349 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 350                                          struct rte_eth_udp_tunnel *udp_tunnel);
 351 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 352                                          struct rte_eth_udp_tunnel *udp_tunnel);
 353 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 354 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 355 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 356
 357 /*
 358  * Define VF Stats MACRO for Non "cleared on read" register
 359  */
 360 #define UPDATE_VF_STAT(reg, last, cur)                          \
 361 {                                                               \
 362         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 363         cur += (latest - last) & UINT_MAX;                      \
 364         last = latest;                                          \
 365 }
 366
 367 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 368 {                                                                \
 369         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 370         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 371         u64 latest = ((new_msb << 32) | new_lsb);                \
 372         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 373         last = latest;                                           \
 374 }
 375
 376 #define IXGBE_SET_HWSTRIP(h, q) do {\
 377                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 378                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 379                 (h)->bitmap[idx] |= 1 << bit;\
 380         } while (0)
 381
 382 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 383                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 384                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 385                 (h)->bitmap[idx] &= ~(1 << bit);\
 386         } while (0)
 387
 388 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 389                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 390                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 391                 (r) = (h)->bitmap[idx] >> bit & 1;\
 392         } while (0)
 393
 394 /*
 395  * The set of PCI devices this driver supports
 396  */
 397 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 398         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 399         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 400         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 401         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 402         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 403         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 404         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 405         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 406         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 407         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 408         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 446 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 448 #endif
 449         { .vendor_id = 0, /* sentinel */ },
 450 };
 451
 452 /*
 453  * The set of PCI devices this driver supports (for 82599 VF)
 454  */
 455 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 466         { .vendor_id = 0, /* sentinel */ },
 467 };
 468
 469 static const struct rte_eth_desc_lim rx_desc_lim = {
 470         .nb_max = IXGBE_MAX_RING_DESC,
 471         .nb_min = IXGBE_MIN_RING_DESC,
 472         .nb_align = IXGBE_RXD_ALIGN,
 473 };
 474
 475 static const struct rte_eth_desc_lim tx_desc_lim = {
 476         .nb_max = IXGBE_MAX_RING_DESC,
 477         .nb_min = IXGBE_MIN_RING_DESC,
 478         .nb_align = IXGBE_TXD_ALIGN,
 479         .nb_seg_max = IXGBE_TX_MAX_SEG,
 480         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 481 };
 482
 483 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 484         .dev_configure        = ixgbe_dev_configure,
 485         .dev_start            = ixgbe_dev_start,
 486         .dev_stop             = ixgbe_dev_stop,
 487         .dev_set_link_up    = ixgbe_dev_set_link_up,
 488         .dev_set_link_down  = ixgbe_dev_set_link_down,
 489         .dev_close            = ixgbe_dev_close,
 490         .dev_reset            = ixgbe_dev_reset,
 491         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 492         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 493         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 494         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 495         .link_update          = ixgbe_dev_link_update,
 496         .stats_get            = ixgbe_dev_stats_get,
 497         .xstats_get           = ixgbe_dev_xstats_get,
 498         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 499         .stats_reset          = ixgbe_dev_stats_reset,
 500         .xstats_reset         = ixgbe_dev_xstats_reset,
 501         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 502         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 503         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 504         .fw_version_get       = ixgbe_fw_version_get,
 505         .dev_infos_get        = ixgbe_dev_info_get,
 506         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 507         .mtu_set              = ixgbe_dev_mtu_set,
 508         .vlan_filter_set      = ixgbe_vlan_filter_set,
 509         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 510         .vlan_offload_set     = ixgbe_vlan_offload_set,
 511         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 512         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 513         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 514         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 515         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 516         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 517         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 518         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 519         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 520         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 521         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 522         .dev_led_on           = ixgbe_dev_led_on,
 523         .dev_led_off          = ixgbe_dev_led_off,
 524         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 525         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 526         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 527         .mac_addr_add         = ixgbe_add_rar,
 528         .mac_addr_remove      = ixgbe_remove_rar,
 529         .mac_addr_set         = ixgbe_set_default_mac_addr,
 530         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 531         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 532         .mirror_rule_set      = ixgbe_mirror_rule_set,
 533         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 534         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 535         .reta_update          = ixgbe_dev_rss_reta_update,
 536         .reta_query           = ixgbe_dev_rss_reta_query,
 537         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 538         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 539         .flow_ops_get         = ixgbe_dev_flow_ops_get,
 540         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 541         .rxq_info_get         = ixgbe_rxq_info_get,
 542         .txq_info_get         = ixgbe_txq_info_get,
 543         .timesync_enable      = ixgbe_timesync_enable,
 544         .timesync_disable     = ixgbe_timesync_disable,
 545         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 546         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 547         .get_reg              = ixgbe_get_regs,
 548         .get_eeprom_length    = ixgbe_get_eeprom_length,
 549         .get_eeprom           = ixgbe_get_eeprom,
 550         .set_eeprom           = ixgbe_set_eeprom,
 551         .get_module_info      = ixgbe_get_module_info,
 552         .get_module_eeprom    = ixgbe_get_module_eeprom,
 553         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 554         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 555         .timesync_read_time   = ixgbe_timesync_read_time,
 556         .timesync_write_time  = ixgbe_timesync_write_time,
 557         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 558         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 559         .tm_ops_get           = ixgbe_tm_ops_get,
 560         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 561         .get_monitor_addr     = ixgbe_get_monitor_addr,
 562 };
 563
 564 /*
 565  * dev_ops for virtual function, bare necessities for basic vf
 566  * operation have been implemented
 567  */
 568 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 569         .dev_configure        = ixgbevf_dev_configure,
 570         .dev_start            = ixgbevf_dev_start,
 571         .dev_stop             = ixgbevf_dev_stop,
 572         .link_update          = ixgbevf_dev_link_update,
 573         .stats_get            = ixgbevf_dev_stats_get,
 574         .xstats_get           = ixgbevf_dev_xstats_get,
 575         .stats_reset          = ixgbevf_dev_stats_reset,
 576         .xstats_reset         = ixgbevf_dev_stats_reset,
 577         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 578         .dev_close            = ixgbevf_dev_close,
 579         .dev_reset            = ixgbevf_dev_reset,
 580         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 581         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 582         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 583         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 584         .dev_infos_get        = ixgbevf_dev_info_get,
 585         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 586         .mtu_set              = ixgbevf_dev_set_mtu,
 587         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 588         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 589         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 590         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 591         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 592         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 593         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 594         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 595         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 596         .mac_addr_add         = ixgbevf_add_mac_addr,
 597         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 598         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 599         .rxq_info_get         = ixgbe_rxq_info_get,
 600         .txq_info_get         = ixgbe_txq_info_get,
 601         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 602         .get_reg              = ixgbevf_get_regs,
 603         .reta_update          = ixgbe_dev_rss_reta_update,
 604         .reta_query           = ixgbe_dev_rss_reta_query,
 605         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 606         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 607         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 608 };
 609
 610 /* store statistics names and its offset in stats structure */
 611 struct rte_ixgbe_xstats_name_off {
 612         char name[RTE_ETH_XSTATS_NAME_SIZE];
 613         unsigned offset;
 614 };
 615
 616 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 617         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 618         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 619         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 620         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 621         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 622         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 623         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 624         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 625         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 626         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 627         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 628         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 629         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 630         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 631         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 632                 prc1023)},
 633         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 634                 prc1522)},
 635         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 636         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 637         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 638         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 639         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 640         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 641         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 642         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 643         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 644         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 645         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 646         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 647         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 648         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 649         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 650         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 651         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 652                 ptc1023)},
 653         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 654                 ptc1522)},
 655         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 656         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 657         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 658         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 659
 660         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 661                 fdirustat_add)},
 662         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 663                 fdirustat_remove)},
 664         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 665                 fdirfstat_fadd)},
 666         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 667                 fdirfstat_fremove)},
 668         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 669                 fdirmatch)},
 670         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 671                 fdirmiss)},
 672
 673         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 674         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 675         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 676                 fclast)},
 677         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 678         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 679         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 680         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 681         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 682                 fcoe_noddp)},
 683         {"rx_fcoe_no_direct_data_placement_ext_buff",
 684                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 685
 686         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 687                 lxontxc)},
 688         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 689                 lxonrxc)},
 690         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 691                 lxofftxc)},
 692         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 693                 lxoffrxc)},
 694         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 695 };
 696
 697 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 698                            sizeof(rte_ixgbe_stats_strings[0]))
 699
 700 /* MACsec statistics */
 701 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 702         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 703                 out_pkts_untagged)},
 704         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 705                 out_pkts_encrypted)},
 706         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 707                 out_pkts_protected)},
 708         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 709                 out_octets_encrypted)},
 710         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 711                 out_octets_protected)},
 712         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 713                 in_pkts_untagged)},
 714         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 715                 in_pkts_badtag)},
 716         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 717                 in_pkts_nosci)},
 718         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 719                 in_pkts_unknownsci)},
 720         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 721                 in_octets_decrypted)},
 722         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 723                 in_octets_validated)},
 724         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 725                 in_pkts_unchecked)},
 726         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_delayed)},
 728         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_late)},
 730         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_ok)},
 732         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_invalid)},
 734         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 735                 in_pkts_notvalid)},
 736         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 737                 in_pkts_unusedsa)},
 738         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_notusingsa)},
 740 };
 741
 742 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 743                            sizeof(rte_ixgbe_macsec_strings[0]))
 744
 745 /* Per-queue statistics */
 746 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 747         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 748         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 749         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 750         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 751 };
 752
 753 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 754                            sizeof(rte_ixgbe_rxq_strings[0]))
 755 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 756
 757 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 758         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 759         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 760         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 761                 pxon2offc)},
 762 };
 763
 764 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 765                            sizeof(rte_ixgbe_txq_strings[0]))
 766 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 767
 768 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 769         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 770 };
 771
 772 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 773                 sizeof(rte_ixgbevf_stats_strings[0]))
 774
 775 /*
 776  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 777  */
 778 static inline int
 779 ixgbe_is_sfp(struct ixgbe_hw *hw)
 780 {
 781         switch (hw->phy.type) {
 782         case ixgbe_phy_sfp_avago:
 783         case ixgbe_phy_sfp_ftl:
 784         case ixgbe_phy_sfp_intel:
 785         case ixgbe_phy_sfp_unknown:
 786         case ixgbe_phy_sfp_passive_tyco:
 787         case ixgbe_phy_sfp_passive_unknown:
 788                 return 1;
 789         default:
 790                 return 0;
 791         }
 792 }
 793
 794 static inline int32_t
 795 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 796 {
 797         uint32_t ctrl_ext;
 798         int32_t status;
 799
 800         status = ixgbe_reset_hw(hw);
 801
 802         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 803         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 804         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 805         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 806         IXGBE_WRITE_FLUSH(hw);
 807
 808         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 809                 status = IXGBE_SUCCESS;
 810         return status;
 811 }
 812
 813 static inline void
 814 ixgbe_enable_intr(struct rte_eth_dev *dev)
 815 {
 816         struct ixgbe_interrupt *intr =
 817                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 818         struct ixgbe_hw *hw =
 819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 820
 821         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 822         IXGBE_WRITE_FLUSH(hw);
 823 }
 824
 825 /*
 826  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 827  */
 828 static void
 829 ixgbe_disable_intr(struct ixgbe_hw *hw)
 830 {
 831         PMD_INIT_FUNC_TRACE();
 832
 833         if (hw->mac.type == ixgbe_mac_82598EB) {
 834                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 835         } else {
 836                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 837                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 838                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 839         }
 840         IXGBE_WRITE_FLUSH(hw);
 841 }
 842
 843 /*
 844  * This function resets queue statistics mapping registers.
 845  * From Niantic datasheet, Initialization of Statistics section:
 846  * "...if software requires the queue counters, the RQSMR and TQSM registers
 847  * must be re-programmed following a device reset.
 848  */
 849 static void
 850 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 851 {
 852         uint32_t i;
 853
 854         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 855                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 856                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 857         }
 858 }
 859
 860
 861 static int
 862 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 863                                   uint16_t queue_id,
 864                                   uint8_t stat_idx,
 865                                   uint8_t is_rx)
 866 {
 867 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 868 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 869 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 870
 871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 872         struct ixgbe_stat_mapping_registers *stat_mappings =
 873                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 874         uint32_t qsmr_mask = 0;
 875         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 876         uint32_t q_map;
 877         uint8_t n, offset;
 878
 879         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 880                 (hw->mac.type != ixgbe_mac_X540) &&
 881                 (hw->mac.type != ixgbe_mac_X550) &&
 882                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 883                 (hw->mac.type != ixgbe_mac_X550EM_a))
 884                 return -ENOSYS;
 885
 886         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 887                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 888                      queue_id, stat_idx);
 889
 890         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 891         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 892                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 893                 return -EIO;
 894         }
 895         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 896
 897         /* Now clear any previous stat_idx set */
 898         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 899         if (!is_rx)
 900                 stat_mappings->tqsm[n] &= ~clearing_mask;
 901         else
 902                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 903
 904         q_map = (uint32_t)stat_idx;
 905         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 906         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 907         if (!is_rx)
 908                 stat_mappings->tqsm[n] |= qsmr_mask;
 909         else
 910                 stat_mappings->rqsmr[n] |= qsmr_mask;
 911
 912         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 913                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 914                      queue_id, stat_idx);
 915         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 916                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 917
 918         /* Now write the mapping in the appropriate register */
 919         if (is_rx) {
 920                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 921                              stat_mappings->rqsmr[n], n);
 922                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 923         } else {
 924                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 925                              stat_mappings->tqsm[n], n);
 926                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 927         }
 928         return 0;
 929 }
 930
 931 static void
 932 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 933 {
 934         struct ixgbe_stat_mapping_registers *stat_mappings =
 935                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 936         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 937         int i;
 938
 939         /* write whatever was in stat mapping table to the NIC */
 940         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 941                 /* rx */
 942                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 943
 944                 /* tx */
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 946         }
 947 }
 948
 949 static void
 950 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 951 {
 952         uint8_t i;
 953         struct ixgbe_dcb_tc_config *tc;
 954         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 955
 956         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 957         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 958         for (i = 0; i < dcb_max_tc; i++) {
 959                 tc = &dcb_config->tc_config[i];
 960                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 961                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 962                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 963                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 964                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 965                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 966                 tc->pfc = ixgbe_dcb_pfc_disabled;
 967         }
 968
 969         /* Initialize default user to priority mapping, UPx->TC0 */
 970         tc = &dcb_config->tc_config[0];
 971         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 972         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 973         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 974                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 975                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 976         }
 977         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 978         dcb_config->pfc_mode_enable = false;
 979         dcb_config->vt_mode = true;
 980         dcb_config->round_robin_enable = false;
 981         /* support all DCB capabilities in 82599 */
 982         dcb_config->support.capabilities = 0xFF;
 983
 984         /*we only support 4 Tcs for X540, X550 */
 985         if (hw->mac.type == ixgbe_mac_X540 ||
 986                 hw->mac.type == ixgbe_mac_X550 ||
 987                 hw->mac.type == ixgbe_mac_X550EM_x ||
 988                 hw->mac.type == ixgbe_mac_X550EM_a) {
 989                 dcb_config->num_tcs.pg_tcs = 4;
 990                 dcb_config->num_tcs.pfc_tcs = 4;
 991         }
 992 }
 993
 994 /*
 995  * Ensure that all locks are released before first NVM or PHY access
 996  */
 997 static void
 998 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 999 {
1000         uint16_t mask;
1001
1002         /*
1003          * Phy lock should not fail in this early stage. If this is the case,
1004          * it is due to an improper exit of the application.
1005          * So force the release of the faulty lock. Release of common lock
1006          * is done automatically by swfw_sync function.
1007          */
1008         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1009         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1010                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1011         }
1012         ixgbe_release_swfw_semaphore(hw, mask);
1013
1014         /*
1015          * These ones are more tricky since they are common to all ports; but
1016          * swfw_sync retries last long enough (1s) to be almost sure that if
1017          * lock can not be taken it is due to an improper lock of the
1018          * semaphore.
1019          */
1020         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1021         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1022                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1023         }
1024         ixgbe_release_swfw_semaphore(hw, mask);
1025 }
1026
1027 /*
1028  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1029  * It returns 0 on success.
1030  */
1031 static int
1032 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1033 {
1034         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1035         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1036         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1037         struct ixgbe_hw *hw =
1038                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1039         struct ixgbe_vfta *shadow_vfta =
1040                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1041         struct ixgbe_hwstrip *hwstrip =
1042                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1043         struct ixgbe_dcb_config *dcb_config =
1044                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1045         struct ixgbe_filter_info *filter_info =
1046                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1047         struct ixgbe_bw_conf *bw_conf =
1048                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1049         uint32_t ctrl_ext;
1050         uint16_t csum;
1051         int diag, i, ret;
1052
1053         PMD_INIT_FUNC_TRACE();
1054
1055         ixgbe_dev_macsec_setting_reset(eth_dev);
1056
1057         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1058         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1059         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1060         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1061         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1062         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1063         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1064         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1065
1066         /*
1067          * For secondary processes, we don't initialise any further as primary
1068          * has already done this work. Only check we don't need a different
1069          * RX and TX function.
1070          */
1071         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1072                 struct ixgbe_tx_queue *txq;
1073                 /* TX queue function in primary, set by last queue initialized
1074                  * Tx queue may not initialized by primary process
1075                  */
1076                 if (eth_dev->data->tx_queues) {
1077                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1078                         ixgbe_set_tx_function(eth_dev, txq);
1079                 } else {
1080                         /* Use default TX function if we get here */
1081                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1082                                      "Using default TX function.");
1083                 }
1084
1085                 ixgbe_set_rx_function(eth_dev);
1086
1087                 return 0;
1088         }
1089
1090         rte_atomic32_clear(&ad->link_thread_running);
1091         rte_eth_copy_pci_info(eth_dev, pci_dev);
1092         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1093
1094         /* Vendor and Device ID need to be set before init of shared code */
1095         hw->device_id = pci_dev->id.device_id;
1096         hw->vendor_id = pci_dev->id.vendor_id;
1097         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1098         hw->allow_unsupported_sfp = 1;
1099
1100         /* Initialize the shared code (base driver) */
1101 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1102         diag = ixgbe_bypass_init_shared_code(hw);
1103 #else
1104         diag = ixgbe_init_shared_code(hw);
1105 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1106
1107         if (diag != IXGBE_SUCCESS) {
1108                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1109                 return -EIO;
1110         }
1111
1112         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1113                 PMD_INIT_LOG(ERR, "\nERROR: "
1114                         "Firmware recovery mode detected. Limiting functionality.\n"
1115                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1116                         "User Guide for details on firmware recovery mode.");
1117                 return -EIO;
1118         }
1119
1120         /* pick up the PCI bus settings for reporting later */
1121         ixgbe_get_bus_info(hw);
1122
1123         /* Unlock any pending hardware semaphore */
1124         ixgbe_swfw_lock_reset(hw);
1125
1126 #ifdef RTE_LIB_SECURITY
1127         /* Initialize security_ctx only for primary process*/
1128         if (ixgbe_ipsec_ctx_create(eth_dev))
1129                 return -ENOMEM;
1130 #endif
1131
1132         /* Initialize DCB configuration*/
1133         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1134         ixgbe_dcb_init(hw, dcb_config);
1135         /* Get Hardware Flow Control setting */
1136         hw->fc.requested_mode = ixgbe_fc_none;
1137         hw->fc.current_mode = ixgbe_fc_none;
1138         hw->fc.pause_time = IXGBE_FC_PAUSE;
1139         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1140                 hw->fc.low_water[i] = IXGBE_FC_LO;
1141                 hw->fc.high_water[i] = IXGBE_FC_HI;
1142         }
1143         hw->fc.send_xon = 1;
1144
1145         /* Make sure we have a good EEPROM before we read from it */
1146         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1147         if (diag != IXGBE_SUCCESS) {
1148                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1149                 return -EIO;
1150         }
1151
1152 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1153         diag = ixgbe_bypass_init_hw(hw);
1154 #else
1155         diag = ixgbe_init_hw(hw);
1156 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1157
1158         /*
1159          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1160          * is called too soon after the kernel driver unbinding/binding occurs.
1161          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1162          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1163          * also called. See ixgbe_identify_phy_82599(). The reason for the
1164          * failure is not known, and only occuts when virtualisation features
1165          * are disabled in the bios. A delay of 100ms  was found to be enough by
1166          * trial-and-error, and is doubled to be safe.
1167          */
1168         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1169                 rte_delay_ms(200);
1170                 diag = ixgbe_init_hw(hw);
1171         }
1172
1173         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1174                 diag = IXGBE_SUCCESS;
1175
1176         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1177                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1178                              "LOM.  Please be aware there may be issues associated "
1179                              "with your hardware.");
1180                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1181                              "please contact your Intel or hardware representative "
1182                              "who provided you with this hardware.");
1183         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1184                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1185         if (diag) {
1186                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1187                 return -EIO;
1188         }
1189
1190         /* Reset the hw statistics */
1191         ixgbe_dev_stats_reset(eth_dev);
1192
1193         /* disable interrupt */
1194         ixgbe_disable_intr(hw);
1195
1196         /* reset mappings for queue statistics hw counters*/
1197         ixgbe_reset_qstat_mappings(hw);
1198
1199         /* Allocate memory for storing MAC addresses */
1200         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1201                                                hw->mac.num_rar_entries, 0);
1202         if (eth_dev->data->mac_addrs == NULL) {
1203                 PMD_INIT_LOG(ERR,
1204                              "Failed to allocate %u bytes needed to store "
1205                              "MAC addresses",
1206                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1207                 return -ENOMEM;
1208         }
1209         /* Copy the permanent MAC address */
1210         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1211                         &eth_dev->data->mac_addrs[0]);
1212
1213         /* Allocate memory for storing hash filter MAC addresses */
1214         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1215                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1216         if (eth_dev->data->hash_mac_addrs == NULL) {
1217                 PMD_INIT_LOG(ERR,
1218                              "Failed to allocate %d bytes needed to store MAC addresses",
1219                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1220                 return -ENOMEM;
1221         }
1222
1223         /* initialize the vfta */
1224         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1225
1226         /* initialize the hw strip bitmap*/
1227         memset(hwstrip, 0, sizeof(*hwstrip));
1228
1229         /* initialize PF if max_vfs not zero */
1230         ret = ixgbe_pf_host_init(eth_dev);
1231         if (ret) {
1232                 rte_free(eth_dev->data->mac_addrs);
1233                 eth_dev->data->mac_addrs = NULL;
1234                 rte_free(eth_dev->data->hash_mac_addrs);
1235                 eth_dev->data->hash_mac_addrs = NULL;
1236                 return ret;
1237         }
1238
1239         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1240         /* let hardware know driver is loaded */
1241         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1242         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1243         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1244         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1245         IXGBE_WRITE_FLUSH(hw);
1246
1247         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1248                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1249                              (int) hw->mac.type, (int) hw->phy.type,
1250                              (int) hw->phy.sfp_type);
1251         else
1252                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1253                              (int) hw->mac.type, (int) hw->phy.type);
1254
1255         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1256                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1257                      pci_dev->id.device_id);
1258
1259         rte_intr_callback_register(intr_handle,
1260                                    ixgbe_dev_interrupt_handler, eth_dev);
1261
1262         /* enable uio/vfio intr/eventfd mapping */
1263         rte_intr_enable(intr_handle);
1264
1265         /* enable support intr */
1266         ixgbe_enable_intr(eth_dev);
1267
1268         /* initialize filter info */
1269         memset(filter_info, 0,
1270                sizeof(struct ixgbe_filter_info));
1271
1272         /* initialize 5tuple filter list */
1273         TAILQ_INIT(&filter_info->fivetuple_list);
1274
1275         /* initialize flow director filter list & hash */
1276         ixgbe_fdir_filter_init(eth_dev);
1277
1278         /* initialize l2 tunnel filter list & hash */
1279         ixgbe_l2_tn_filter_init(eth_dev);
1280
1281         /* initialize flow filter lists */
1282         ixgbe_filterlist_init();
1283
1284         /* initialize bandwidth configuration info */
1285         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1286
1287         /* initialize Traffic Manager configuration */
1288         ixgbe_tm_conf_init(eth_dev);
1289
1290         return 0;
1291 }
1292
1293 static int
1294 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1295 {
1296         PMD_INIT_FUNC_TRACE();
1297
1298         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1299                 return 0;
1300
1301         ixgbe_dev_close(eth_dev);
1302
1303         return 0;
1304 }
1305
1306 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1307 {
1308         struct ixgbe_filter_info *filter_info =
1309                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1310         struct ixgbe_5tuple_filter *p_5tuple;
1311
1312         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1313                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1314                              p_5tuple,
1315                              entries);
1316                 rte_free(p_5tuple);
1317         }
1318         memset(filter_info->fivetuple_mask, 0,
1319                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1320
1321         return 0;
1322 }
1323
1324 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1325 {
1326         struct ixgbe_hw_fdir_info *fdir_info =
1327                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1328         struct ixgbe_fdir_filter *fdir_filter;
1329
1330                 if (fdir_info->hash_map)
1331                 rte_free(fdir_info->hash_map);
1332         if (fdir_info->hash_handle)
1333                 rte_hash_free(fdir_info->hash_handle);
1334
1335         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1336                 TAILQ_REMOVE(&fdir_info->fdir_list,
1337                              fdir_filter,
1338                              entries);
1339                 rte_free(fdir_filter);
1340         }
1341
1342         return 0;
1343 }
1344
1345 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1346 {
1347         struct ixgbe_l2_tn_info *l2_tn_info =
1348                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1349         struct ixgbe_l2_tn_filter *l2_tn_filter;
1350
1351         if (l2_tn_info->hash_map)
1352                 rte_free(l2_tn_info->hash_map);
1353         if (l2_tn_info->hash_handle)
1354                 rte_hash_free(l2_tn_info->hash_handle);
1355
1356         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1357                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1358                              l2_tn_filter,
1359                              entries);
1360                 rte_free(l2_tn_filter);
1361         }
1362
1363         return 0;
1364 }
1365
1366 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1367 {
1368         struct ixgbe_hw_fdir_info *fdir_info =
1369                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1370         char fdir_hash_name[RTE_HASH_NAMESIZE];
1371         struct rte_hash_parameters fdir_hash_params = {
1372                 .name = fdir_hash_name,
1373                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1374                 .key_len = sizeof(union ixgbe_atr_input),
1375                 .hash_func = rte_hash_crc,
1376                 .hash_func_init_val = 0,
1377                 .socket_id = rte_socket_id(),
1378         };
1379
1380         TAILQ_INIT(&fdir_info->fdir_list);
1381         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1382                  "fdir_%s", eth_dev->device->name);
1383         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1384         if (!fdir_info->hash_handle) {
1385                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1386                 return -EINVAL;
1387         }
1388         fdir_info->hash_map = rte_zmalloc("ixgbe",
1389                                           sizeof(struct ixgbe_fdir_filter *) *
1390                                           IXGBE_MAX_FDIR_FILTER_NUM,
1391                                           0);
1392         if (!fdir_info->hash_map) {
1393                 PMD_INIT_LOG(ERR,
1394                              "Failed to allocate memory for fdir hash map!");
1395                 return -ENOMEM;
1396         }
1397         fdir_info->mask_added = FALSE;
1398
1399         return 0;
1400 }
1401
1402 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1403 {
1404         struct ixgbe_l2_tn_info *l2_tn_info =
1405                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1406         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1407         struct rte_hash_parameters l2_tn_hash_params = {
1408                 .name = l2_tn_hash_name,
1409                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1410                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1411                 .hash_func = rte_hash_crc,
1412                 .hash_func_init_val = 0,
1413                 .socket_id = rte_socket_id(),
1414         };
1415
1416         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1417         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1418                  "l2_tn_%s", eth_dev->device->name);
1419         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1420         if (!l2_tn_info->hash_handle) {
1421                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1422                 return -EINVAL;
1423         }
1424         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1425                                    sizeof(struct ixgbe_l2_tn_filter *) *
1426                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1427                                    0);
1428         if (!l2_tn_info->hash_map) {
1429                 PMD_INIT_LOG(ERR,
1430                         "Failed to allocate memory for L2 TN hash map!");
1431                 return -ENOMEM;
1432         }
1433         l2_tn_info->e_tag_en = FALSE;
1434         l2_tn_info->e_tag_fwd_en = FALSE;
1435         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1436
1437         return 0;
1438 }
1439 /*
1440  * Negotiate mailbox API version with the PF.
1441  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1442  * Then we try to negotiate starting with the most recent one.
1443  * If all negotiation attempts fail, then we will proceed with
1444  * the default one (ixgbe_mbox_api_10).
1445  */
1446 static void
1447 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1448 {
1449         int32_t i;
1450
1451         /* start with highest supported, proceed down */
1452         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1453                 ixgbe_mbox_api_13,
1454                 ixgbe_mbox_api_12,
1455                 ixgbe_mbox_api_11,
1456                 ixgbe_mbox_api_10,
1457         };
1458
1459         for (i = 0;
1460                         i != RTE_DIM(sup_ver) &&
1461                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1462                         i++)
1463                 ;
1464 }
1465
1466 static void
1467 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1468 {
1469         uint64_t random;
1470
1471         /* Set Organizationally Unique Identifier (OUI) prefix. */
1472         mac_addr->addr_bytes[0] = 0x00;
1473         mac_addr->addr_bytes[1] = 0x09;
1474         mac_addr->addr_bytes[2] = 0xC0;
1475         /* Force indication of locally assigned MAC address. */
1476         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1477         /* Generate the last 3 bytes of the MAC address with a random number. */
1478         random = rte_rand();
1479         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1480 }
1481
1482 static int
1483 devarg_handle_int(__rte_unused const char *key, const char *value,
1484                   void *extra_args)
1485 {
1486         uint16_t *n = extra_args;
1487
1488         if (value == NULL || extra_args == NULL)
1489                 return -EINVAL;
1490
1491         *n = (uint16_t)strtoul(value, NULL, 0);
1492         if (*n == USHRT_MAX && errno == ERANGE)
1493                 return -1;
1494
1495         return 0;
1496 }
1497
1498 static void
1499 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1500                       struct rte_devargs *devargs)
1501 {
1502         struct rte_kvargs *kvlist;
1503         uint16_t pflink_fullchk;
1504
1505         if (devargs == NULL)
1506                 return;
1507
1508         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1509         if (kvlist == NULL)
1510                 return;
1511
1512         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1513             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1514                                devarg_handle_int, &pflink_fullchk) == 0 &&
1515             pflink_fullchk == 1)
1516                 adapter->pflink_fullchk = 1;
1517
1518         rte_kvargs_free(kvlist);
1519 }
1520
1521 /*
1522  * Virtual Function device init
1523  */
1524 static int
1525 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1526 {
1527         int diag;
1528         uint32_t tc, tcs;
1529         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1530         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1531         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1532         struct ixgbe_hw *hw =
1533                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1534         struct ixgbe_vfta *shadow_vfta =
1535                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1536         struct ixgbe_hwstrip *hwstrip =
1537                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1538         struct rte_ether_addr *perm_addr =
1539                 (struct rte_ether_addr *)hw->mac.perm_addr;
1540
1541         PMD_INIT_FUNC_TRACE();
1542
1543         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1544         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1545         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1546         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1547         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1548         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1549
1550         /* for secondary processes, we don't initialise any further as primary
1551          * has already done this work. Only check we don't need a different
1552          * RX function
1553          */
1554         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1555                 struct ixgbe_tx_queue *txq;
1556                 /* TX queue function in primary, set by last queue initialized
1557                  * Tx queue may not initialized by primary process
1558                  */
1559                 if (eth_dev->data->tx_queues) {
1560                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1561                         ixgbe_set_tx_function(eth_dev, txq);
1562                 } else {
1563                         /* Use default TX function if we get here */
1564                         PMD_INIT_LOG(NOTICE,
1565                                      "No TX queues configured yet. Using default TX function.");
1566                 }
1567
1568                 ixgbe_set_rx_function(eth_dev);
1569
1570                 return 0;
1571         }
1572
1573         rte_atomic32_clear(&ad->link_thread_running);
1574         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1575                               pci_dev->device.devargs);
1576
1577         rte_eth_copy_pci_info(eth_dev, pci_dev);
1578         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1579
1580         hw->device_id = pci_dev->id.device_id;
1581         hw->vendor_id = pci_dev->id.vendor_id;
1582         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1583
1584         /* initialize the vfta */
1585         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1586
1587         /* initialize the hw strip bitmap*/
1588         memset(hwstrip, 0, sizeof(*hwstrip));
1589
1590         /* Initialize the shared code (base driver) */
1591         diag = ixgbe_init_shared_code(hw);
1592         if (diag != IXGBE_SUCCESS) {
1593                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1594                 return -EIO;
1595         }
1596
1597         /* init_mailbox_params */
1598         hw->mbx.ops.init_params(hw);
1599
1600         /* Reset the hw statistics */
1601         ixgbevf_dev_stats_reset(eth_dev);
1602
1603         /* Disable the interrupts for VF */
1604         ixgbevf_intr_disable(eth_dev);
1605
1606         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1607         diag = hw->mac.ops.reset_hw(hw);
1608
1609         /*
1610          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1611          * the underlying PF driver has not assigned a MAC address to the VF.
1612          * In this case, assign a random MAC address.
1613          */
1614         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1615                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1616                 /*
1617                  * This error code will be propagated to the app by
1618                  * rte_eth_dev_reset, so use a public error code rather than
1619                  * the internal-only IXGBE_ERR_RESET_FAILED
1620                  */
1621                 return -EAGAIN;
1622         }
1623
1624         /* negotiate mailbox API version to use with the PF. */
1625         ixgbevf_negotiate_api(hw);
1626
1627         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1628         ixgbevf_get_queues(hw, &tcs, &tc);
1629
1630         /* Allocate memory for storing MAC addresses */
1631         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1632                                                hw->mac.num_rar_entries, 0);
1633         if (eth_dev->data->mac_addrs == NULL) {
1634                 PMD_INIT_LOG(ERR,
1635                              "Failed to allocate %u bytes needed to store "
1636                              "MAC addresses",
1637                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1638                 return -ENOMEM;
1639         }
1640
1641         /* Generate a random MAC address, if none was assigned by PF. */
1642         if (rte_is_zero_ether_addr(perm_addr)) {
1643                 generate_random_mac_addr(perm_addr);
1644                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1645                 if (diag) {
1646                         rte_free(eth_dev->data->mac_addrs);
1647                         eth_dev->data->mac_addrs = NULL;
1648                         return diag;
1649                 }
1650                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1651                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1652                              "%02x:%02x:%02x:%02x:%02x:%02x",
1653                              perm_addr->addr_bytes[0],
1654                              perm_addr->addr_bytes[1],
1655                              perm_addr->addr_bytes[2],
1656                              perm_addr->addr_bytes[3],
1657                              perm_addr->addr_bytes[4],
1658                              perm_addr->addr_bytes[5]);
1659         }
1660
1661         /* Copy the permanent MAC address */
1662         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1663
1664         /* reset the hardware with the new settings */
1665         diag = hw->mac.ops.start_hw(hw);
1666         switch (diag) {
1667         case  0:
1668                 break;
1669
1670         default:
1671                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1672                 return -EIO;
1673         }
1674
1675         rte_intr_callback_register(intr_handle,
1676                                    ixgbevf_dev_interrupt_handler, eth_dev);
1677         rte_intr_enable(intr_handle);
1678         ixgbevf_intr_enable(eth_dev);
1679
1680         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1681                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1682                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1683
1684         return 0;
1685 }
1686
1687 /* Virtual Function device uninit */
1688
1689 static int
1690 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1691 {
1692         PMD_INIT_FUNC_TRACE();
1693
1694         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1695                 return 0;
1696
1697         ixgbevf_dev_close(eth_dev);
1698
1699         return 0;
1700 }
1701
1702 static int
1703 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1704                 struct rte_pci_device *pci_dev)
1705 {
1706         char name[RTE_ETH_NAME_MAX_LEN];
1707         struct rte_eth_dev *pf_ethdev;
1708         struct rte_eth_devargs eth_da;
1709         int i, retval;
1710
1711         if (pci_dev->device.devargs) {
1712                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1713                                 &eth_da);
1714                 if (retval)
1715                         return retval;
1716         } else
1717                 memset(&eth_da, 0, sizeof(eth_da));
1718
1719         if (eth_da.nb_representor_ports > 0 &&
1720             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
1721                 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
1722                             pci_dev->device.devargs->args);
1723                 return -ENOTSUP;
1724         }
1725
1726         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1727                 sizeof(struct ixgbe_adapter),
1728                 eth_dev_pci_specific_init, pci_dev,
1729                 eth_ixgbe_dev_init, NULL);
1730
1731         if (retval || eth_da.nb_representor_ports < 1)
1732                 return retval;
1733
1734         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1735         if (pf_ethdev == NULL)
1736                 return -ENODEV;
1737
1738         /* probe VF representor ports */
1739         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1740                 struct ixgbe_vf_info *vfinfo;
1741                 struct ixgbe_vf_representor representor;
1742
1743                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1744                         pf_ethdev->data->dev_private);
1745                 if (vfinfo == NULL) {
1746                         PMD_DRV_LOG(ERR,
1747                                 "no virtual functions supported by PF");
1748                         break;
1749                 }
1750
1751                 representor.vf_id = eth_da.representor_ports[i];
1752                 representor.switch_domain_id = vfinfo->switch_domain_id;
1753                 representor.pf_ethdev = pf_ethdev;
1754
1755                 /* representor port net_bdf_port */
1756                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1757                         pci_dev->device.name,
1758                         eth_da.representor_ports[i]);
1759
1760                 retval = rte_eth_dev_create(&pci_dev->device, name,
1761                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1762                         ixgbe_vf_representor_init, &representor);
1763
1764                 if (retval)
1765                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1766                                 "representor %s.", name);
1767         }
1768
1769         return 0;
1770 }
1771
1772 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1773 {
1774         struct rte_eth_dev *ethdev;
1775
1776         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1777         if (!ethdev)
1778                 return 0;
1779
1780         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1781                 return rte_eth_dev_pci_generic_remove(pci_dev,
1782                                         ixgbe_vf_representor_uninit);
1783         else
1784                 return rte_eth_dev_pci_generic_remove(pci_dev,
1785                                                 eth_ixgbe_dev_uninit);
1786 }
1787
1788 static struct rte_pci_driver rte_ixgbe_pmd = {
1789         .id_table = pci_id_ixgbe_map,
1790         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1791         .probe = eth_ixgbe_pci_probe,
1792         .remove = eth_ixgbe_pci_remove,
1793 };
1794
1795 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1796         struct rte_pci_device *pci_dev)
1797 {
1798         return rte_eth_dev_pci_generic_probe(pci_dev,
1799                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1800 }
1801
1802 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1803 {
1804         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1805 }
1806
1807 /*
1808  * virtual function driver struct
1809  */
1810 static struct rte_pci_driver rte_ixgbevf_pmd = {
1811         .id_table = pci_id_ixgbevf_map,
1812         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1813         .probe = eth_ixgbevf_pci_probe,
1814         .remove = eth_ixgbevf_pci_remove,
1815 };
1816
1817 static int
1818 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1819 {
1820         struct ixgbe_hw *hw =
1821                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1822         struct ixgbe_vfta *shadow_vfta =
1823                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1824         uint32_t vfta;
1825         uint32_t vid_idx;
1826         uint32_t vid_bit;
1827
1828         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1829         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1830         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1831         if (on)
1832                 vfta |= vid_bit;
1833         else
1834                 vfta &= ~vid_bit;
1835         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1836
1837         /* update local VFTA copy */
1838         shadow_vfta->vfta[vid_idx] = vfta;
1839
1840         return 0;
1841 }
1842
1843 static void
1844 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1845 {
1846         if (on)
1847                 ixgbe_vlan_hw_strip_enable(dev, queue);
1848         else
1849                 ixgbe_vlan_hw_strip_disable(dev, queue);
1850 }
1851
1852 static int
1853 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1854                     enum rte_vlan_type vlan_type,
1855                     uint16_t tpid)
1856 {
1857         struct ixgbe_hw *hw =
1858                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859         int ret = 0;
1860         uint32_t reg;
1861         uint32_t qinq;
1862
1863         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1864         qinq &= IXGBE_DMATXCTL_GDV;
1865
1866         switch (vlan_type) {
1867         case ETH_VLAN_TYPE_INNER:
1868                 if (qinq) {
1869                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1870                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1871                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1872                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1873                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1874                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1875                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1876                 } else {
1877                         ret = -ENOTSUP;
1878                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1879                                     " by single VLAN");
1880                 }
1881                 break;
1882         case ETH_VLAN_TYPE_OUTER:
1883                 if (qinq) {
1884                         /* Only the high 16-bits is valid */
1885                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1886                                         IXGBE_EXVET_VET_EXT_SHIFT);
1887                 } else {
1888                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1889                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1890                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1891                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1892                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1893                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1894                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1895                 }
1896
1897                 break;
1898         default:
1899                 ret = -EINVAL;
1900                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1901                 break;
1902         }
1903
1904         return ret;
1905 }
1906
1907 void
1908 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1909 {
1910         struct ixgbe_hw *hw =
1911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912         uint32_t vlnctrl;
1913
1914         PMD_INIT_FUNC_TRACE();
1915
1916         /* Filter Table Disable */
1917         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1918         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1919
1920         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1921 }
1922
1923 void
1924 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1925 {
1926         struct ixgbe_hw *hw =
1927                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         struct ixgbe_vfta *shadow_vfta =
1929                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1930         uint32_t vlnctrl;
1931         uint16_t i;
1932
1933         PMD_INIT_FUNC_TRACE();
1934
1935         /* Filter Table Enable */
1936         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1937         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1938         vlnctrl |= IXGBE_VLNCTRL_VFE;
1939
1940         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1941
1942         /* write whatever is in local vfta copy */
1943         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1944                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1945 }
1946
1947 static void
1948 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1949 {
1950         struct ixgbe_hwstrip *hwstrip =
1951                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1952         struct ixgbe_rx_queue *rxq;
1953
1954         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1955                 return;
1956
1957         if (on)
1958                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1959         else
1960                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1961
1962         if (queue >= dev->data->nb_rx_queues)
1963                 return;
1964
1965         rxq = dev->data->rx_queues[queue];
1966
1967         if (on) {
1968                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1969                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1970         } else {
1971                 rxq->vlan_flags = PKT_RX_VLAN;
1972                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1973         }
1974 }
1975
1976 static void
1977 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1978 {
1979         struct ixgbe_hw *hw =
1980                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1981         uint32_t ctrl;
1982
1983         PMD_INIT_FUNC_TRACE();
1984
1985         if (hw->mac.type == ixgbe_mac_82598EB) {
1986                 /* No queue level support */
1987                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1988                 return;
1989         }
1990
1991         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1992         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1993         ctrl &= ~IXGBE_RXDCTL_VME;
1994         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1995
1996         /* record those setting for HW strip per queue */
1997         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1998 }
1999
2000 static void
2001 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2002 {
2003         struct ixgbe_hw *hw =
2004                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005         uint32_t ctrl;
2006
2007         PMD_INIT_FUNC_TRACE();
2008
2009         if (hw->mac.type == ixgbe_mac_82598EB) {
2010                 /* No queue level supported */
2011                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2012                 return;
2013         }
2014
2015         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2016         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2017         ctrl |= IXGBE_RXDCTL_VME;
2018         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2019
2020         /* record those setting for HW strip per queue */
2021         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2022 }
2023
2024 static void
2025 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2026 {
2027         struct ixgbe_hw *hw =
2028                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         uint32_t ctrl;
2030
2031         PMD_INIT_FUNC_TRACE();
2032
2033         /* DMATXCTRL: Geric Double VLAN Disable */
2034         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2035         ctrl &= ~IXGBE_DMATXCTL_GDV;
2036         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2037
2038         /* CTRL_EXT: Global Double VLAN Disable */
2039         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2040         ctrl &= ~IXGBE_EXTENDED_VLAN;
2041         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2042
2043 }
2044
2045 static void
2046 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2047 {
2048         struct ixgbe_hw *hw =
2049                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2050         uint32_t ctrl;
2051
2052         PMD_INIT_FUNC_TRACE();
2053
2054         /* DMATXCTRL: Geric Double VLAN Enable */
2055         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2056         ctrl |= IXGBE_DMATXCTL_GDV;
2057         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2058
2059         /* CTRL_EXT: Global Double VLAN Enable */
2060         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2061         ctrl |= IXGBE_EXTENDED_VLAN;
2062         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2063
2064         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2065         if (hw->mac.type == ixgbe_mac_X550 ||
2066             hw->mac.type == ixgbe_mac_X550EM_x ||
2067             hw->mac.type == ixgbe_mac_X550EM_a) {
2068                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2069                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2070                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2071         }
2072
2073         /*
2074          * VET EXT field in the EXVET register = 0x8100 by default
2075          * So no need to change. Same to VT field of DMATXCTL register
2076          */
2077 }
2078
2079 void
2080 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2081 {
2082         struct ixgbe_hw *hw =
2083                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2085         uint32_t ctrl;
2086         uint16_t i;
2087         struct ixgbe_rx_queue *rxq;
2088         bool on;
2089
2090         PMD_INIT_FUNC_TRACE();
2091
2092         if (hw->mac.type == ixgbe_mac_82598EB) {
2093                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2094                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2095                         ctrl |= IXGBE_VLNCTRL_VME;
2096                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2097                 } else {
2098                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2099                         ctrl &= ~IXGBE_VLNCTRL_VME;
2100                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2101                 }
2102         } else {
2103                 /*
2104                  * Other 10G NIC, the VLAN strip can be setup
2105                  * per queue in RXDCTL
2106                  */
2107                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2108                         rxq = dev->data->rx_queues[i];
2109                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2110                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2111                                 ctrl |= IXGBE_RXDCTL_VME;
2112                                 on = TRUE;
2113                         } else {
2114                                 ctrl &= ~IXGBE_RXDCTL_VME;
2115                                 on = FALSE;
2116                         }
2117                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2118
2119                         /* record those setting for HW strip per queue */
2120                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2121                 }
2122         }
2123 }
2124
2125 static void
2126 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2127 {
2128         uint16_t i;
2129         struct rte_eth_rxmode *rxmode;
2130         struct ixgbe_rx_queue *rxq;
2131
2132         if (mask & ETH_VLAN_STRIP_MASK) {
2133                 rxmode = &dev->data->dev_conf.rxmode;
2134                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2135                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2136                                 rxq = dev->data->rx_queues[i];
2137                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2138                         }
2139                 else
2140                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2141                                 rxq = dev->data->rx_queues[i];
2142                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2143                         }
2144         }
2145 }
2146
2147 static int
2148 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2149 {
2150         struct rte_eth_rxmode *rxmode;
2151         rxmode = &dev->data->dev_conf.rxmode;
2152
2153         if (mask & ETH_VLAN_STRIP_MASK) {
2154                 ixgbe_vlan_hw_strip_config(dev);
2155         }
2156
2157         if (mask & ETH_VLAN_FILTER_MASK) {
2158                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2159                         ixgbe_vlan_hw_filter_enable(dev);
2160                 else
2161                         ixgbe_vlan_hw_filter_disable(dev);
2162         }
2163
2164         if (mask & ETH_VLAN_EXTEND_MASK) {
2165                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2166                         ixgbe_vlan_hw_extend_enable(dev);
2167                 else
2168                         ixgbe_vlan_hw_extend_disable(dev);
2169         }
2170
2171         return 0;
2172 }
2173
2174 static int
2175 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2176 {
2177         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2178
2179         ixgbe_vlan_offload_config(dev, mask);
2180
2181         return 0;
2182 }
2183
2184 static void
2185 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2186 {
2187         struct ixgbe_hw *hw =
2188                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2190         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2191
2192         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2193         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2194 }
2195
2196 static int
2197 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2198 {
2199         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2200
2201         switch (nb_rx_q) {
2202         case 1:
2203         case 2:
2204                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2205                 break;
2206         case 4:
2207                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2208                 break;
2209         default:
2210                 return -EINVAL;
2211         }
2212
2213         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2214                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2215         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2216                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2217         return 0;
2218 }
2219
2220 static int
2221 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2222 {
2223         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2225         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2226         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2227
2228         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2229                 /* check multi-queue mode */
2230                 switch (dev_conf->rxmode.mq_mode) {
2231                 case ETH_MQ_RX_VMDQ_DCB:
2232                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2233                         break;
2234                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2235                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2236                         PMD_INIT_LOG(ERR, "SRIOV active,"
2237                                         " unsupported mq_mode rx %d.",
2238                                         dev_conf->rxmode.mq_mode);
2239                         return -EINVAL;
2240                 case ETH_MQ_RX_RSS:
2241                 case ETH_MQ_RX_VMDQ_RSS:
2242                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2243                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2244                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2245                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2246                                                 " invalid queue number"
2247                                                 " for VMDQ RSS, allowed"
2248                                                 " value are 1, 2 or 4.");
2249                                         return -EINVAL;
2250                                 }
2251                         break;
2252                 case ETH_MQ_RX_VMDQ_ONLY:
2253                 case ETH_MQ_RX_NONE:
2254                         /* if nothing mq mode configure, use default scheme */
2255                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2256                         break;
2257                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2258                         /* SRIOV only works in VMDq enable mode */
2259                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2260                                         " wrong mq_mode rx %d.",
2261                                         dev_conf->rxmode.mq_mode);
2262                         return -EINVAL;
2263                 }
2264
2265                 switch (dev_conf->txmode.mq_mode) {
2266                 case ETH_MQ_TX_VMDQ_DCB:
2267                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2268                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2269                         break;
2270                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2271                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2272                         break;
2273                 }
2274
2275                 /* check valid queue number */
2276                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2277                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2278                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2279                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2280                                         " must be less than or equal to %d.",
2281                                         nb_rx_q, nb_tx_q,
2282                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2283                         return -EINVAL;
2284                 }
2285         } else {
2286                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2287                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2288                                           " not supported.");
2289                         return -EINVAL;
2290                 }
2291                 /* check configuration for vmdb+dcb mode */
2292                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2293                         const struct rte_eth_vmdq_dcb_conf *conf;
2294
2295                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2296                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2297                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2298                                 return -EINVAL;
2299                         }
2300                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2301                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2302                                conf->nb_queue_pools == ETH_32_POOLS)) {
2303                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2304                                                 " nb_queue_pools must be %d or %d.",
2305                                                 ETH_16_POOLS, ETH_32_POOLS);
2306                                 return -EINVAL;
2307                         }
2308                 }
2309                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2310                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2311
2312                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2313                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2314                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2315                                 return -EINVAL;
2316                         }
2317                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2318                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2319                                conf->nb_queue_pools == ETH_32_POOLS)) {
2320                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2321                                                 " nb_queue_pools != %d and"
2322                                                 " nb_queue_pools != %d.",
2323                                                 ETH_16_POOLS, ETH_32_POOLS);
2324                                 return -EINVAL;
2325                         }
2326                 }
2327
2328                 /* For DCB mode check our configuration before we go further */
2329                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2330                         const struct rte_eth_dcb_rx_conf *conf;
2331
2332                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2333                         if (!(conf->nb_tcs == ETH_4_TCS ||
2334                                conf->nb_tcs == ETH_8_TCS)) {
2335                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2336                                                 " and nb_tcs != %d.",
2337                                                 ETH_4_TCS, ETH_8_TCS);
2338                                 return -EINVAL;
2339                         }
2340                 }
2341
2342                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2343                         const struct rte_eth_dcb_tx_conf *conf;
2344
2345                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2346                         if (!(conf->nb_tcs == ETH_4_TCS ||
2347                                conf->nb_tcs == ETH_8_TCS)) {
2348                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2349                                                 " and nb_tcs != %d.",
2350                                                 ETH_4_TCS, ETH_8_TCS);
2351                                 return -EINVAL;
2352                         }
2353                 }
2354
2355                 /*
2356                  * When DCB/VT is off, maximum number of queues changes,
2357                  * except for 82598EB, which remains constant.
2358                  */
2359                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2360                                 hw->mac.type != ixgbe_mac_82598EB) {
2361                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2362                                 PMD_INIT_LOG(ERR,
2363                                              "Neither VT nor DCB are enabled, "
2364                                              "nb_tx_q > %d.",
2365                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2366                                 return -EINVAL;
2367                         }
2368                 }
2369         }
2370         return 0;
2371 }
2372
2373 static int
2374 ixgbe_dev_configure(struct rte_eth_dev *dev)
2375 {
2376         struct ixgbe_interrupt *intr =
2377                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2378         struct ixgbe_adapter *adapter = dev->data->dev_private;
2379         int ret;
2380
2381         PMD_INIT_FUNC_TRACE();
2382
2383         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2384                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2385
2386         /* multipe queue mode checking */
2387         ret  = ixgbe_check_mq_mode(dev);
2388         if (ret != 0) {
2389                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2390                             ret);
2391                 return ret;
2392         }
2393
2394         /* set flag to update link status after init */
2395         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2396
2397         /*
2398          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2399          * allocation or vector Rx preconditions we will reset it.
2400          */
2401         adapter->rx_bulk_alloc_allowed = true;
2402         adapter->rx_vec_allowed = true;
2403
2404         return 0;
2405 }
2406
2407 static void
2408 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2409 {
2410         struct ixgbe_hw *hw =
2411                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412         struct ixgbe_interrupt *intr =
2413                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2414         uint32_t gpie;
2415
2416         /* only set up it on X550EM_X */
2417         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2418                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2419                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2420                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2421                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2422                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2423         }
2424 }
2425
2426 int
2427 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2428                         uint16_t tx_rate, uint64_t q_msk)
2429 {
2430         struct ixgbe_hw *hw;
2431         struct ixgbe_vf_info *vfinfo;
2432         struct rte_eth_link link;
2433         uint8_t  nb_q_per_pool;
2434         uint32_t queue_stride;
2435         uint32_t queue_idx, idx = 0, vf_idx;
2436         uint32_t queue_end;
2437         uint16_t total_rate = 0;
2438         struct rte_pci_device *pci_dev;
2439         int ret;
2440
2441         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2442         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2443         if (ret < 0)
2444                 return ret;
2445
2446         if (vf >= pci_dev->max_vfs)
2447                 return -EINVAL;
2448
2449         if (tx_rate > link.link_speed)
2450                 return -EINVAL;
2451
2452         if (q_msk == 0)
2453                 return 0;
2454
2455         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2457         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2458         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2459         queue_idx = vf * queue_stride;
2460         queue_end = queue_idx + nb_q_per_pool - 1;
2461         if (queue_end >= hw->mac.max_tx_queues)
2462                 return -EINVAL;
2463
2464         if (vfinfo) {
2465                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2466                         if (vf_idx == vf)
2467                                 continue;
2468                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2469                                 idx++)
2470                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2471                 }
2472         } else {
2473                 return -EINVAL;
2474         }
2475
2476         /* Store tx_rate for this vf. */
2477         for (idx = 0; idx < nb_q_per_pool; idx++) {
2478                 if (((uint64_t)0x1 << idx) & q_msk) {
2479                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2480                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2481                         total_rate += tx_rate;
2482                 }
2483         }
2484
2485         if (total_rate > dev->data->dev_link.link_speed) {
2486                 /* Reset stored TX rate of the VF if it causes exceed
2487                  * link speed.
2488                  */
2489                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2490                 return -EINVAL;
2491         }
2492
2493         /* Set RTTBCNRC of each queue/pool for vf X  */
2494         for (; queue_idx <= queue_end; queue_idx++) {
2495                 if (0x1 & q_msk)
2496                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2497                 q_msk = q_msk >> 1;
2498         }
2499
2500         return 0;
2501 }
2502
2503 static int
2504 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2505 {
2506         struct ixgbe_adapter *adapter = dev->data->dev_private;
2507         int err;
2508         uint32_t mflcn;
2509
2510         ixgbe_setup_fc(hw);
2511
2512         err = ixgbe_fc_enable(hw);
2513
2514         /* Not negotiated is not an error case */
2515         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2516                 /*
2517                  *check if we want to forward MAC frames - driver doesn't
2518                  *have native capability to do that,
2519                  *so we'll write the registers ourselves
2520                  */
2521
2522                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2523
2524                 /* set or clear MFLCN.PMCF bit depending on configuration */
2525                 if (adapter->mac_ctrl_frame_fwd != 0)
2526                         mflcn |= IXGBE_MFLCN_PMCF;
2527                 else
2528                         mflcn &= ~IXGBE_MFLCN_PMCF;
2529
2530                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2531                 IXGBE_WRITE_FLUSH(hw);
2532
2533                 return 0;
2534         }
2535         return err;
2536 }
2537
2538 /*
2539  * Configure device link speed and setup link.
2540  * It returns 0 on success.
2541  */
2542 static int
2543 ixgbe_dev_start(struct rte_eth_dev *dev)
2544 {
2545         struct ixgbe_hw *hw =
2546                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2547         struct ixgbe_vf_info *vfinfo =
2548                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2549         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2550         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2551         uint32_t intr_vector = 0;
2552         int err;
2553         bool link_up = false, negotiate = 0;
2554         uint32_t speed = 0;
2555         uint32_t allowed_speeds = 0;
2556         int mask = 0;
2557         int status;
2558         uint16_t vf, idx;
2559         uint32_t *link_speeds;
2560         struct ixgbe_tm_conf *tm_conf =
2561                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2562         struct ixgbe_macsec_setting *macsec_setting =
2563                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2564
2565         PMD_INIT_FUNC_TRACE();
2566
2567         /* Stop the link setup handler before resetting the HW. */
2568         ixgbe_dev_wait_setup_link_complete(dev, 0);
2569
2570         /* disable uio/vfio intr/eventfd mapping */
2571         rte_intr_disable(intr_handle);
2572
2573         /* stop adapter */
2574         hw->adapter_stopped = 0;
2575         ixgbe_stop_adapter(hw);
2576
2577         /* reinitialize adapter
2578          * this calls reset and start
2579          */
2580         status = ixgbe_pf_reset_hw(hw);
2581         if (status != 0)
2582                 return -1;
2583         hw->mac.ops.start_hw(hw);
2584         hw->mac.get_link_status = true;
2585
2586         /* configure PF module if SRIOV enabled */
2587         ixgbe_pf_host_configure(dev);
2588
2589         ixgbe_dev_phy_intr_setup(dev);
2590
2591         /* check and configure queue intr-vector mapping */
2592         if ((rte_intr_cap_multiple(intr_handle) ||
2593              !RTE_ETH_DEV_SRIOV(dev).active) &&
2594             dev->data->dev_conf.intr_conf.rxq != 0) {
2595                 intr_vector = dev->data->nb_rx_queues;
2596                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2597                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2598                                         IXGBE_MAX_INTR_QUEUE_NUM);
2599                         return -ENOTSUP;
2600                 }
2601                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2602                         return -1;
2603         }
2604
2605         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2606                 intr_handle->intr_vec =
2607                         rte_zmalloc("intr_vec",
2608                                     dev->data->nb_rx_queues * sizeof(int), 0);
2609                 if (intr_handle->intr_vec == NULL) {
2610                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2611                                      " intr_vec", dev->data->nb_rx_queues);
2612                         return -ENOMEM;
2613                 }
2614         }
2615
2616         /* confiugre msix for sleep until rx interrupt */
2617         ixgbe_configure_msix(dev);
2618
2619         /* initialize transmission unit */
2620         ixgbe_dev_tx_init(dev);
2621
2622         /* This can fail when allocating mbufs for descriptor rings */
2623         err = ixgbe_dev_rx_init(dev);
2624         if (err) {
2625                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2626                 goto error;
2627         }
2628
2629         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2630                 ETH_VLAN_EXTEND_MASK;
2631         err = ixgbe_vlan_offload_config(dev, mask);
2632         if (err) {
2633                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2634                 goto error;
2635         }
2636
2637         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2638                 /* Enable vlan filtering for VMDq */
2639                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2640         }
2641
2642         /* Configure DCB hw */
2643         ixgbe_configure_dcb(dev);
2644
2645         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2646                 err = ixgbe_fdir_configure(dev);
2647                 if (err)
2648                         goto error;
2649         }
2650
2651         /* Restore vf rate limit */
2652         if (vfinfo != NULL) {
2653                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2654                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2655                                 if (vfinfo[vf].tx_rate[idx] != 0)
2656                                         ixgbe_set_vf_rate_limit(
2657                                                 dev, vf,
2658                                                 vfinfo[vf].tx_rate[idx],
2659                                                 1 << idx);
2660         }
2661
2662         ixgbe_restore_statistics_mapping(dev);
2663
2664         err = ixgbe_flow_ctrl_enable(dev, hw);
2665         if (err < 0) {
2666                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2667                 goto error;
2668         }
2669
2670         err = ixgbe_dev_rxtx_start(dev);
2671         if (err < 0) {
2672                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2673                 goto error;
2674         }
2675
2676         /* Skip link setup if loopback mode is enabled. */
2677         if (dev->data->dev_conf.lpbk_mode != 0) {
2678                 err = ixgbe_check_supported_loopback_mode(dev);
2679                 if (err < 0) {
2680                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2681                         goto error;
2682                 } else {
2683                         goto skip_link_setup;
2684                 }
2685         }
2686
2687         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2688                 err = hw->mac.ops.setup_sfp(hw);
2689                 if (err)
2690                         goto error;
2691         }
2692
2693         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2694                 /* Turn on the copper */
2695                 ixgbe_set_phy_power(hw, true);
2696         } else {
2697                 /* Turn on the laser */
2698                 ixgbe_enable_tx_laser(hw);
2699         }
2700
2701         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2702         if (err)
2703                 goto error;
2704         dev->data->dev_link.link_status = link_up;
2705
2706         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2707         if (err)
2708                 goto error;
2709
2710         switch (hw->mac.type) {
2711         case ixgbe_mac_X550:
2712         case ixgbe_mac_X550EM_x:
2713         case ixgbe_mac_X550EM_a:
2714                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2715                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2716                         ETH_LINK_SPEED_10G;
2717                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2718                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2719                         allowed_speeds = ETH_LINK_SPEED_10M |
2720                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2721                 break;
2722         default:
2723                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2724                         ETH_LINK_SPEED_10G;
2725         }
2726
2727         link_speeds = &dev->data->dev_conf.link_speeds;
2728
2729         /* Ignore autoneg flag bit and check the validity of
2730          * link_speed
2731          */
2732         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2733                 PMD_INIT_LOG(ERR, "Invalid link setting");
2734                 goto error;
2735         }
2736
2737         speed = 0x0;
2738         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2739                 switch (hw->mac.type) {
2740                 case ixgbe_mac_82598EB:
2741                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2742                         break;
2743                 case ixgbe_mac_82599EB:
2744                 case ixgbe_mac_X540:
2745                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2746                         break;
2747                 case ixgbe_mac_X550:
2748                 case ixgbe_mac_X550EM_x:
2749                 case ixgbe_mac_X550EM_a:
2750                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2751                         break;
2752                 default:
2753                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2754                 }
2755         } else {
2756                 if (*link_speeds & ETH_LINK_SPEED_10G)
2757                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2758                 if (*link_speeds & ETH_LINK_SPEED_5G)
2759                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2760                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2761                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2762                 if (*link_speeds & ETH_LINK_SPEED_1G)
2763                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2764                 if (*link_speeds & ETH_LINK_SPEED_100M)
2765                         speed |= IXGBE_LINK_SPEED_100_FULL;
2766                 if (*link_speeds & ETH_LINK_SPEED_10M)
2767                         speed |= IXGBE_LINK_SPEED_10_FULL;
2768         }
2769
2770         err = ixgbe_setup_link(hw, speed, link_up);
2771         if (err)
2772                 goto error;
2773
2774 skip_link_setup:
2775
2776         if (rte_intr_allow_others(intr_handle)) {
2777                 /* check if lsc interrupt is enabled */
2778                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2779                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2780                 else
2781                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2782                 ixgbe_dev_macsec_interrupt_setup(dev);
2783         } else {
2784                 rte_intr_callback_unregister(intr_handle,
2785                                              ixgbe_dev_interrupt_handler, dev);
2786                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2787                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2788                                      " no intr multiplex");
2789         }
2790
2791         /* check if rxq interrupt is enabled */
2792         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2793             rte_intr_dp_is_en(intr_handle))
2794                 ixgbe_dev_rxq_interrupt_setup(dev);
2795
2796         /* enable uio/vfio intr/eventfd mapping */
2797         rte_intr_enable(intr_handle);
2798
2799         /* resume enabled intr since hw reset */
2800         ixgbe_enable_intr(dev);
2801         ixgbe_l2_tunnel_conf(dev);
2802         ixgbe_filter_restore(dev);
2803
2804         if (tm_conf->root && !tm_conf->committed)
2805                 PMD_DRV_LOG(WARNING,
2806                             "please call hierarchy_commit() "
2807                             "before starting the port");
2808
2809         /* wait for the controller to acquire link */
2810         err = ixgbe_wait_for_link_up(hw);
2811         if (err)
2812                 goto error;
2813
2814         /*
2815          * Update link status right before return, because it may
2816          * start link configuration process in a separate thread.
2817          */
2818         ixgbe_dev_link_update(dev, 0);
2819
2820         /* setup the macsec setting register */
2821         if (macsec_setting->offload_en)
2822                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2823
2824         return 0;
2825
2826 error:
2827         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2828         ixgbe_dev_clear_queues(dev);
2829         return -EIO;
2830 }
2831
2832 /*
2833  * Stop device: disable rx and tx functions to allow for reconfiguring.
2834  */
2835 static int
2836 ixgbe_dev_stop(struct rte_eth_dev *dev)
2837 {
2838         struct rte_eth_link link;
2839         struct ixgbe_adapter *adapter = dev->data->dev_private;
2840         struct ixgbe_hw *hw =
2841                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842         struct ixgbe_vf_info *vfinfo =
2843                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2844         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2845         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2846         int vf;
2847         struct ixgbe_tm_conf *tm_conf =
2848                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2849
2850         if (hw->adapter_stopped)
2851                 return 0;
2852
2853         PMD_INIT_FUNC_TRACE();
2854
2855         ixgbe_dev_wait_setup_link_complete(dev, 0);
2856
2857         /* disable interrupts */
2858         ixgbe_disable_intr(hw);
2859
2860         /* reset the NIC */
2861         ixgbe_pf_reset_hw(hw);
2862         hw->adapter_stopped = 0;
2863
2864         /* stop adapter */
2865         ixgbe_stop_adapter(hw);
2866
2867         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2868                 vfinfo[vf].clear_to_send = false;
2869
2870         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2871                 /* Turn off the copper */
2872                 ixgbe_set_phy_power(hw, false);
2873         } else {
2874                 /* Turn off the laser */
2875                 ixgbe_disable_tx_laser(hw);
2876         }
2877
2878         ixgbe_dev_clear_queues(dev);
2879
2880         /* Clear stored conf */
2881         dev->data->scattered_rx = 0;
2882         dev->data->lro = 0;
2883
2884         /* Clear recorded link status */
2885         memset(&link, 0, sizeof(link));
2886         rte_eth_linkstatus_set(dev, &link);
2887
2888         if (!rte_intr_allow_others(intr_handle))
2889                 /* resume to the default handler */
2890                 rte_intr_callback_register(intr_handle,
2891                                            ixgbe_dev_interrupt_handler,
2892                                            (void *)dev);
2893
2894         /* Clean datapath event and queue/vec mapping */
2895         rte_intr_efd_disable(intr_handle);
2896         if (intr_handle->intr_vec != NULL) {
2897                 rte_free(intr_handle->intr_vec);
2898                 intr_handle->intr_vec = NULL;
2899         }
2900
2901         /* reset hierarchy commit */
2902         tm_conf->committed = false;
2903
2904         adapter->rss_reta_updated = 0;
2905
2906         hw->adapter_stopped = true;
2907         dev->data->dev_started = 0;
2908
2909         return 0;
2910 }
2911
2912 /*
2913  * Set device link up: enable tx.
2914  */
2915 static int
2916 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2917 {
2918         struct ixgbe_hw *hw =
2919                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920         if (hw->mac.type == ixgbe_mac_82599EB) {
2921 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2922                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2923                         /* Not suported in bypass mode */
2924                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2925                                      "by device id 0x%x", hw->device_id);
2926                         return -ENOTSUP;
2927                 }
2928 #endif
2929         }
2930
2931         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2932                 /* Turn on the copper */
2933                 ixgbe_set_phy_power(hw, true);
2934         } else {
2935                 /* Turn on the laser */
2936                 ixgbe_enable_tx_laser(hw);
2937                 ixgbe_dev_link_update(dev, 0);
2938         }
2939
2940         return 0;
2941 }
2942
2943 /*
2944  * Set device link down: disable tx.
2945  */
2946 static int
2947 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2948 {
2949         struct ixgbe_hw *hw =
2950                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2951         if (hw->mac.type == ixgbe_mac_82599EB) {
2952 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2953                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2954                         /* Not suported in bypass mode */
2955                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2956                                      "by device id 0x%x", hw->device_id);
2957                         return -ENOTSUP;
2958                 }
2959 #endif
2960         }
2961
2962         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2963                 /* Turn off the copper */
2964                 ixgbe_set_phy_power(hw, false);
2965         } else {
2966                 /* Turn off the laser */
2967                 ixgbe_disable_tx_laser(hw);
2968                 ixgbe_dev_link_update(dev, 0);
2969         }
2970
2971         return 0;
2972 }
2973
2974 /*
2975  * Reset and stop device.
2976  */
2977 static int
2978 ixgbe_dev_close(struct rte_eth_dev *dev)
2979 {
2980         struct ixgbe_hw *hw =
2981                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2982         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2983         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2984         int retries = 0;
2985         int ret;
2986
2987         PMD_INIT_FUNC_TRACE();
2988         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2989                 return 0;
2990
2991         ixgbe_pf_reset_hw(hw);
2992
2993         ret = ixgbe_dev_stop(dev);
2994
2995         ixgbe_dev_free_queues(dev);
2996
2997         ixgbe_disable_pcie_master(hw);
2998
2999         /* reprogram the RAR[0] in case user changed it. */
3000         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3001
3002         /* Unlock any pending hardware semaphore */
3003         ixgbe_swfw_lock_reset(hw);
3004
3005         /* disable uio intr before callback unregister */
3006         rte_intr_disable(intr_handle);
3007
3008         do {
3009                 ret = rte_intr_callback_unregister(intr_handle,
3010                                 ixgbe_dev_interrupt_handler, dev);
3011                 if (ret >= 0 || ret == -ENOENT) {
3012                         break;
3013                 } else if (ret != -EAGAIN) {
3014                         PMD_INIT_LOG(ERR,
3015                                 "intr callback unregister failed: %d",
3016                                 ret);
3017                 }
3018                 rte_delay_ms(100);
3019         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3020
3021         /* cancel the delay handler before remove dev */
3022         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3023
3024         /* uninitialize PF if max_vfs not zero */
3025         ixgbe_pf_host_uninit(dev);
3026
3027         /* remove all the fdir filters & hash */
3028         ixgbe_fdir_filter_uninit(dev);
3029
3030         /* remove all the L2 tunnel filters & hash */
3031         ixgbe_l2_tn_filter_uninit(dev);
3032
3033         /* Remove all ntuple filters of the device */
3034         ixgbe_ntuple_filter_uninit(dev);
3035
3036         /* clear all the filters list */
3037         ixgbe_filterlist_flush();
3038
3039         /* Remove all Traffic Manager configuration */
3040         ixgbe_tm_conf_uninit(dev);
3041
3042 #ifdef RTE_LIB_SECURITY
3043         rte_free(dev->security_ctx);
3044 #endif
3045
3046         return ret;
3047 }
3048
3049 /*
3050  * Reset PF device.
3051  */
3052 static int
3053 ixgbe_dev_reset(struct rte_eth_dev *dev)
3054 {
3055         int ret;
3056
3057         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3058          * its VF to make them align with it. The detailed notification
3059          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3060          * To avoid unexpected behavior in VF, currently reset of PF with
3061          * SR-IOV activation is not supported. It might be supported later.
3062          */
3063         if (dev->data->sriov.active)
3064                 return -ENOTSUP;
3065
3066         ret = eth_ixgbe_dev_uninit(dev);
3067         if (ret)
3068                 return ret;
3069
3070         ret = eth_ixgbe_dev_init(dev, NULL);
3071
3072         return ret;
3073 }
3074
3075 static void
3076 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3077                            struct ixgbe_hw_stats *hw_stats,
3078                            struct ixgbe_macsec_stats *macsec_stats,
3079                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3080                            uint64_t *total_qprc, uint64_t *total_qprdc)
3081 {
3082         uint32_t bprc, lxon, lxoff, total;
3083         uint32_t delta_gprc = 0;
3084         unsigned i;
3085         /* Workaround for RX byte count not including CRC bytes when CRC
3086          * strip is enabled. CRC bytes are removed from counters when crc_strip
3087          * is disabled.
3088          */
3089         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3090                         IXGBE_HLREG0_RXCRCSTRP);
3091
3092         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3093         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3094         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3095         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3096
3097         for (i = 0; i < 8; i++) {
3098                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3099
3100                 /* global total per queue */
3101                 hw_stats->mpc[i] += mp;
3102                 /* Running comprehensive total for stats display */
3103                 *total_missed_rx += hw_stats->mpc[i];
3104                 if (hw->mac.type == ixgbe_mac_82598EB) {
3105                         hw_stats->rnbc[i] +=
3106                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3107                         hw_stats->pxonrxc[i] +=
3108                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3109                         hw_stats->pxoffrxc[i] +=
3110                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3111                 } else {
3112                         hw_stats->pxonrxc[i] +=
3113                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3114                         hw_stats->pxoffrxc[i] +=
3115                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3116                         hw_stats->pxon2offc[i] +=
3117                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3118                 }
3119                 hw_stats->pxontxc[i] +=
3120                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3121                 hw_stats->pxofftxc[i] +=
3122                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3123         }
3124         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3125                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3126                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3127                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3128
3129                 delta_gprc += delta_qprc;
3130
3131                 hw_stats->qprc[i] += delta_qprc;
3132                 hw_stats->qptc[i] += delta_qptc;
3133
3134                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3135                 hw_stats->qbrc[i] +=
3136                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3137                 if (crc_strip == 0)
3138                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3139
3140                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3141                 hw_stats->qbtc[i] +=
3142                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3143
3144                 hw_stats->qprdc[i] += delta_qprdc;
3145                 *total_qprdc += hw_stats->qprdc[i];
3146
3147                 *total_qprc += hw_stats->qprc[i];
3148                 *total_qbrc += hw_stats->qbrc[i];
3149         }
3150         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3151         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3152         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3153
3154         /*
3155          * An errata states that gprc actually counts good + missed packets:
3156          * Workaround to set gprc to summated queue packet receives
3157          */
3158         hw_stats->gprc = *total_qprc;
3159
3160         if (hw->mac.type != ixgbe_mac_82598EB) {
3161                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3162                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3163                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3164                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3165                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3166                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3167                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3168                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3169         } else {
3170                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3171                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3172                 /* 82598 only has a counter in the high register */
3173                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3174                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3175                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3176         }
3177         uint64_t old_tpr = hw_stats->tpr;
3178
3179         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3180         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3181
3182         if (crc_strip == 0)
3183                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3184
3185         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3186         hw_stats->gptc += delta_gptc;
3187         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3188         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3189
3190         /*
3191          * Workaround: mprc hardware is incorrectly counting
3192          * broadcasts, so for now we subtract those.
3193          */
3194         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3195         hw_stats->bprc += bprc;
3196         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3197         if (hw->mac.type == ixgbe_mac_82598EB)
3198                 hw_stats->mprc -= bprc;
3199
3200         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3201         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3202         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3203         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3204         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3205         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3206
3207         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3208         hw_stats->lxontxc += lxon;
3209         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3210         hw_stats->lxofftxc += lxoff;
3211         total = lxon + lxoff;
3212
3213         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3214         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3215         hw_stats->gptc -= total;
3216         hw_stats->mptc -= total;
3217         hw_stats->ptc64 -= total;
3218         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3219
3220         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3221         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3222         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3223         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3224         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3225         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3226         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3227         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3228         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3229         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3230         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3231         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3232         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3233         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3234         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3235         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3236         /* Only read FCOE on 82599 */
3237         if (hw->mac.type != ixgbe_mac_82598EB) {
3238                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3239                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3240                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3241                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3242                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3243         }
3244
3245         /* Flow Director Stats registers */
3246         if (hw->mac.type != ixgbe_mac_82598EB) {
3247                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3248                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3249                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3250                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3251                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3252                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3253                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3254                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3255                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3256                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3257         }
3258         /* MACsec Stats registers */
3259         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3260         macsec_stats->out_pkts_encrypted +=
3261                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3262         macsec_stats->out_pkts_protected +=
3263                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3264         macsec_stats->out_octets_encrypted +=
3265                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3266         macsec_stats->out_octets_protected +=
3267                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3268         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3269         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3270         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3271         macsec_stats->in_pkts_unknownsci +=
3272                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3273         macsec_stats->in_octets_decrypted +=
3274                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3275         macsec_stats->in_octets_validated +=
3276                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3277         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3278         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3279         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3280         for (i = 0; i < 2; i++) {
3281                 macsec_stats->in_pkts_ok +=
3282                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3283                 macsec_stats->in_pkts_invalid +=
3284                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3285                 macsec_stats->in_pkts_notvalid +=
3286                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3287         }
3288         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3289         macsec_stats->in_pkts_notusingsa +=
3290                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3291 }
3292
3293 /*
3294  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3295  */
3296 static int
3297 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3298 {
3299         struct ixgbe_hw *hw =
3300                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3301         struct ixgbe_hw_stats *hw_stats =
3302                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3303         struct ixgbe_macsec_stats *macsec_stats =
3304                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3305                                 dev->data->dev_private);
3306         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3307         unsigned i;
3308
3309         total_missed_rx = 0;
3310         total_qbrc = 0;
3311         total_qprc = 0;
3312         total_qprdc = 0;
3313
3314         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3315                         &total_qbrc, &total_qprc, &total_qprdc);
3316
3317         if (stats == NULL)
3318                 return -EINVAL;
3319
3320         /* Fill out the rte_eth_stats statistics structure */
3321         stats->ipackets = total_qprc;
3322         stats->ibytes = total_qbrc;
3323         stats->opackets = hw_stats->gptc;
3324         stats->obytes = hw_stats->gotc;
3325
3326         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3327                 stats->q_ipackets[i] = hw_stats->qprc[i];
3328                 stats->q_opackets[i] = hw_stats->qptc[i];
3329                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3330                 stats->q_obytes[i] = hw_stats->qbtc[i];
3331                 stats->q_errors[i] = hw_stats->qprdc[i];
3332         }
3333
3334         /* Rx Errors */
3335         stats->imissed  = total_missed_rx;
3336         stats->ierrors  = hw_stats->crcerrs +
3337                           hw_stats->mspdc +
3338                           hw_stats->rlec +
3339                           hw_stats->ruc +
3340                           hw_stats->roc +
3341                           hw_stats->illerrc +
3342                           hw_stats->errbc +
3343                           hw_stats->rfc +
3344                           hw_stats->fccrc +
3345                           hw_stats->fclast;
3346
3347         /* Tx Errors */
3348         stats->oerrors  = 0;
3349         return 0;
3350 }
3351
3352 static int
3353 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3354 {
3355         struct ixgbe_hw_stats *stats =
3356                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3357
3358         /* HW registers are cleared on read */
3359         ixgbe_dev_stats_get(dev, NULL);
3360
3361         /* Reset software totals */
3362         memset(stats, 0, sizeof(*stats));
3363
3364         return 0;
3365 }
3366
3367 /* This function calculates the number of xstats based on the current config */
3368 static unsigned
3369 ixgbe_xstats_calc_num(void) {
3370         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3371                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3372                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3373 }
3374
3375 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3376         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3377 {
3378         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3379         unsigned stat, i, count;
3380
3381         if (xstats_names != NULL) {
3382                 count = 0;
3383
3384                 /* Note: limit >= cnt_stats checked upstream
3385                  * in rte_eth_xstats_names()
3386                  */
3387
3388                 /* Extended stats from ixgbe_hw_stats */
3389                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3390                         strlcpy(xstats_names[count].name,
3391                                 rte_ixgbe_stats_strings[i].name,
3392                                 sizeof(xstats_names[count].name));
3393                         count++;
3394                 }
3395
3396                 /* MACsec Stats */
3397                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3398                         strlcpy(xstats_names[count].name,
3399                                 rte_ixgbe_macsec_strings[i].name,
3400                                 sizeof(xstats_names[count].name));
3401                         count++;
3402                 }
3403
3404                 /* RX Priority Stats */
3405                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3406                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3407                                 snprintf(xstats_names[count].name,
3408                                         sizeof(xstats_names[count].name),
3409                                         "rx_priority%u_%s", i,
3410                                         rte_ixgbe_rxq_strings[stat].name);
3411                                 count++;
3412                         }
3413                 }
3414
3415                 /* TX Priority Stats */
3416                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3417                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3418                                 snprintf(xstats_names[count].name,
3419                                         sizeof(xstats_names[count].name),
3420                                         "tx_priority%u_%s", i,
3421                                         rte_ixgbe_txq_strings[stat].name);
3422                                 count++;
3423                         }
3424                 }
3425         }
3426         return cnt_stats;
3427 }
3428
3429 static int ixgbe_dev_xstats_get_names_by_id(
3430         struct rte_eth_dev *dev,
3431         struct rte_eth_xstat_name *xstats_names,
3432         const uint64_t *ids,
3433         unsigned int limit)
3434 {
3435         if (!ids) {
3436                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3437                 unsigned int stat, i, count;
3438
3439                 if (xstats_names != NULL) {
3440                         count = 0;
3441
3442                         /* Note: limit >= cnt_stats checked upstream
3443                          * in rte_eth_xstats_names()
3444                          */
3445
3446                         /* Extended stats from ixgbe_hw_stats */
3447                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3448                                 strlcpy(xstats_names[count].name,
3449                                         rte_ixgbe_stats_strings[i].name,
3450                                         sizeof(xstats_names[count].name));
3451                                 count++;
3452                         }
3453
3454                         /* MACsec Stats */
3455                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3456                                 strlcpy(xstats_names[count].name,
3457                                         rte_ixgbe_macsec_strings[i].name,
3458                                         sizeof(xstats_names[count].name));
3459                                 count++;
3460                         }
3461
3462                         /* RX Priority Stats */
3463                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3464                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3465                                         snprintf(xstats_names[count].name,
3466                                             sizeof(xstats_names[count].name),
3467                                             "rx_priority%u_%s", i,
3468                                             rte_ixgbe_rxq_strings[stat].name);
3469                                         count++;
3470                                 }
3471                         }
3472
3473                         /* TX Priority Stats */
3474                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3475                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3476                                         snprintf(xstats_names[count].name,
3477                                             sizeof(xstats_names[count].name),
3478                                             "tx_priority%u_%s", i,
3479                                             rte_ixgbe_txq_strings[stat].name);
3480                                         count++;
3481                                 }
3482                         }
3483                 }
3484                 return cnt_stats;
3485         }
3486
3487         uint16_t i;
3488         uint16_t size = ixgbe_xstats_calc_num();
3489         struct rte_eth_xstat_name xstats_names_copy[size];
3490
3491         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3492                         size);
3493
3494         for (i = 0; i < limit; i++) {
3495                 if (ids[i] >= size) {
3496                         PMD_INIT_LOG(ERR, "id value isn't valid");
3497                         return -1;
3498                 }
3499                 strcpy(xstats_names[i].name,
3500                                 xstats_names_copy[ids[i]].name);
3501         }
3502         return limit;
3503 }
3504
3505 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3506         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3507 {
3508         unsigned i;
3509
3510         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3511                 return -ENOMEM;
3512
3513         if (xstats_names != NULL)
3514                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3515                         strlcpy(xstats_names[i].name,
3516                                 rte_ixgbevf_stats_strings[i].name,
3517                                 sizeof(xstats_names[i].name));
3518         return IXGBEVF_NB_XSTATS;
3519 }
3520
3521 static int
3522 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3523                                          unsigned n)
3524 {
3525         struct ixgbe_hw *hw =
3526                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3527         struct ixgbe_hw_stats *hw_stats =
3528                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3529         struct ixgbe_macsec_stats *macsec_stats =
3530                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3531                                 dev->data->dev_private);
3532         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3533         unsigned i, stat, count = 0;
3534
3535         count = ixgbe_xstats_calc_num();
3536
3537         if (n < count)
3538                 return count;
3539
3540         total_missed_rx = 0;
3541         total_qbrc = 0;
3542         total_qprc = 0;
3543         total_qprdc = 0;
3544
3545         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3546                         &total_qbrc, &total_qprc, &total_qprdc);
3547
3548         /* If this is a reset xstats is NULL, and we have cleared the
3549          * registers by reading them.
3550          */
3551         if (!xstats)
3552                 return 0;
3553
3554         /* Extended stats from ixgbe_hw_stats */
3555         count = 0;
3556         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3557                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3558                                 rte_ixgbe_stats_strings[i].offset);
3559                 xstats[count].id = count;
3560                 count++;
3561         }
3562
3563         /* MACsec Stats */
3564         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3565                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3566                                 rte_ixgbe_macsec_strings[i].offset);
3567                 xstats[count].id = count;
3568                 count++;
3569         }
3570
3571         /* RX Priority Stats */
3572         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3573                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3574                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3575                                         rte_ixgbe_rxq_strings[stat].offset +
3576                                         (sizeof(uint64_t) * i));
3577                         xstats[count].id = count;
3578                         count++;
3579                 }
3580         }
3581
3582         /* TX Priority Stats */
3583         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3584                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3585                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3586                                         rte_ixgbe_txq_strings[stat].offset +
3587                                         (sizeof(uint64_t) * i));
3588                         xstats[count].id = count;
3589                         count++;
3590                 }
3591         }
3592         return count;
3593 }
3594
3595 static int
3596 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3597                 uint64_t *values, unsigned int n)
3598 {
3599         if (!ids) {
3600                 struct ixgbe_hw *hw =
3601                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3602                 struct ixgbe_hw_stats *hw_stats =
3603                                 IXGBE_DEV_PRIVATE_TO_STATS(
3604                                                 dev->data->dev_private);
3605                 struct ixgbe_macsec_stats *macsec_stats =
3606                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3607                                         dev->data->dev_private);
3608                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3609                 unsigned int i, stat, count = 0;
3610
3611                 count = ixgbe_xstats_calc_num();
3612
3613                 if (!ids && n < count)
3614                         return count;
3615
3616                 total_missed_rx = 0;
3617                 total_qbrc = 0;
3618                 total_qprc = 0;
3619                 total_qprdc = 0;
3620
3621                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3622                                 &total_missed_rx, &total_qbrc, &total_qprc,
3623                                 &total_qprdc);
3624
3625                 /* If this is a reset xstats is NULL, and we have cleared the
3626                  * registers by reading them.
3627                  */
3628                 if (!ids && !values)
3629                         return 0;
3630
3631                 /* Extended stats from ixgbe_hw_stats */
3632                 count = 0;
3633                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3634                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3635                                         rte_ixgbe_stats_strings[i].offset);
3636                         count++;
3637                 }
3638
3639                 /* MACsec Stats */
3640                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3641                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3642                                         rte_ixgbe_macsec_strings[i].offset);
3643                         count++;
3644                 }
3645
3646                 /* RX Priority Stats */
3647                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3648                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3649                                 values[count] =
3650                                         *(uint64_t *)(((char *)hw_stats) +
3651                                         rte_ixgbe_rxq_strings[stat].offset +
3652                                         (sizeof(uint64_t) * i));
3653                                 count++;
3654                         }
3655                 }
3656
3657                 /* TX Priority Stats */
3658                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3659                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3660                                 values[count] =
3661                                         *(uint64_t *)(((char *)hw_stats) +
3662                                         rte_ixgbe_txq_strings[stat].offset +
3663                                         (sizeof(uint64_t) * i));
3664                                 count++;
3665                         }
3666                 }
3667                 return count;
3668         }
3669
3670         uint16_t i;
3671         uint16_t size = ixgbe_xstats_calc_num();
3672         uint64_t values_copy[size];
3673
3674         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3675
3676         for (i = 0; i < n; i++) {
3677                 if (ids[i] >= size) {
3678                         PMD_INIT_LOG(ERR, "id value isn't valid");
3679                         return -1;
3680                 }
3681                 values[i] = values_copy[ids[i]];
3682         }
3683         return n;
3684 }
3685
3686 static int
3687 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3688 {
3689         struct ixgbe_hw_stats *stats =
3690                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3691         struct ixgbe_macsec_stats *macsec_stats =
3692                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3693                                 dev->data->dev_private);
3694
3695         unsigned count = ixgbe_xstats_calc_num();
3696
3697         /* HW registers are cleared on read */
3698         ixgbe_dev_xstats_get(dev, NULL, count);
3699
3700         /* Reset software totals */
3701         memset(stats, 0, sizeof(*stats));
3702         memset(macsec_stats, 0, sizeof(*macsec_stats));
3703
3704         return 0;
3705 }
3706
3707 static void
3708 ixgbevf_update_stats(struct rte_eth_dev *dev)
3709 {
3710         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3711         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3712                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3713
3714         /* Good Rx packet, include VF loopback */
3715         UPDATE_VF_STAT(IXGBE_VFGPRC,
3716             hw_stats->last_vfgprc, hw_stats->vfgprc);
3717
3718         /* Good Rx octets, include VF loopback */
3719         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3720             hw_stats->last_vfgorc, hw_stats->vfgorc);
3721
3722         /* Good Tx packet, include VF loopback */
3723         UPDATE_VF_STAT(IXGBE_VFGPTC,
3724             hw_stats->last_vfgptc, hw_stats->vfgptc);
3725
3726         /* Good Tx octets, include VF loopback */
3727         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3728             hw_stats->last_vfgotc, hw_stats->vfgotc);
3729
3730         /* Rx Multicst Packet */
3731         UPDATE_VF_STAT(IXGBE_VFMPRC,
3732             hw_stats->last_vfmprc, hw_stats->vfmprc);
3733 }
3734
3735 static int
3736 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3737                        unsigned n)
3738 {
3739         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3740                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3741         unsigned i;
3742
3743         if (n < IXGBEVF_NB_XSTATS)
3744                 return IXGBEVF_NB_XSTATS;
3745
3746         ixgbevf_update_stats(dev);
3747
3748         if (!xstats)
3749                 return 0;
3750
3751         /* Extended stats */
3752         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3753                 xstats[i].id = i;
3754                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3755                         rte_ixgbevf_stats_strings[i].offset);
3756         }
3757
3758         return IXGBEVF_NB_XSTATS;
3759 }
3760
3761 static int
3762 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3763 {
3764         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3765                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3766
3767         ixgbevf_update_stats(dev);
3768
3769         if (stats == NULL)
3770                 return -EINVAL;
3771
3772         stats->ipackets = hw_stats->vfgprc;
3773         stats->ibytes = hw_stats->vfgorc;
3774         stats->opackets = hw_stats->vfgptc;
3775         stats->obytes = hw_stats->vfgotc;
3776         return 0;
3777 }
3778
3779 static int
3780 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3781 {
3782         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3783                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3784
3785         /* Sync HW register to the last stats */
3786         ixgbevf_dev_stats_get(dev, NULL);
3787
3788         /* reset HW current stats*/
3789         hw_stats->vfgprc = 0;
3790         hw_stats->vfgorc = 0;
3791         hw_stats->vfgptc = 0;
3792         hw_stats->vfgotc = 0;
3793
3794         return 0;
3795 }
3796
3797 static int
3798 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3799 {
3800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3801         u16 eeprom_verh, eeprom_verl;
3802         u32 etrack_id;
3803         int ret;
3804
3805         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3806         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3807
3808         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3809         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3810
3811         ret += 1; /* add the size of '\0' */
3812         if (fw_size < (u32)ret)
3813                 return ret;
3814         else
3815                 return 0;
3816 }
3817
3818 static int
3819 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3820 {
3821         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3822         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3823         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3824
3825         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3826         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3827         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3828                 /*
3829                  * When DCB/VT is off, maximum number of queues changes,
3830                  * except for 82598EB, which remains constant.
3831                  */
3832                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3833                                 hw->mac.type != ixgbe_mac_82598EB)
3834                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3835         }
3836         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3837         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3838         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3839         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3840         dev_info->max_vfs = pci_dev->max_vfs;
3841         if (hw->mac.type == ixgbe_mac_82598EB)
3842                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3843         else
3844                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3845         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3846         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3847         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3848         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3849         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3850                                      dev_info->rx_queue_offload_capa);
3851         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3852         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3853
3854         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3855                 .rx_thresh = {
3856                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3857                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3858                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3859                 },
3860                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3861                 .rx_drop_en = 0,
3862                 .offloads = 0,
3863         };
3864
3865         dev_info->default_txconf = (struct rte_eth_txconf) {
3866                 .tx_thresh = {
3867                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3868                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3869                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3870                 },
3871                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3872                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3873                 .offloads = 0,
3874         };
3875
3876         dev_info->rx_desc_lim = rx_desc_lim;
3877         dev_info->tx_desc_lim = tx_desc_lim;
3878
3879         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3880         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3881         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3882
3883         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3884         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3885                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3886                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3887                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3888
3889         if (hw->mac.type == ixgbe_mac_X540 ||
3890             hw->mac.type == ixgbe_mac_X540_vf ||
3891             hw->mac.type == ixgbe_mac_X550 ||
3892             hw->mac.type == ixgbe_mac_X550_vf) {
3893                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3894         }
3895         if (hw->mac.type == ixgbe_mac_X550) {
3896                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3897                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3898         }
3899
3900         /* Driver-preferred Rx/Tx parameters */
3901         dev_info->default_rxportconf.burst_size = 32;
3902         dev_info->default_txportconf.burst_size = 32;
3903         dev_info->default_rxportconf.nb_queues = 1;
3904         dev_info->default_txportconf.nb_queues = 1;
3905         dev_info->default_rxportconf.ring_size = 256;
3906         dev_info->default_txportconf.ring_size = 256;
3907
3908         return 0;
3909 }
3910
3911 static const uint32_t *
3912 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3913 {
3914         static const uint32_t ptypes[] = {
3915                 /* For non-vec functions,
3916                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3917                  * for vec functions,
3918                  * refers to _recv_raw_pkts_vec().
3919                  */
3920                 RTE_PTYPE_L2_ETHER,
3921                 RTE_PTYPE_L3_IPV4,
3922                 RTE_PTYPE_L3_IPV4_EXT,
3923                 RTE_PTYPE_L3_IPV6,
3924                 RTE_PTYPE_L3_IPV6_EXT,
3925                 RTE_PTYPE_L4_SCTP,
3926                 RTE_PTYPE_L4_TCP,
3927                 RTE_PTYPE_L4_UDP,
3928                 RTE_PTYPE_TUNNEL_IP,
3929                 RTE_PTYPE_INNER_L3_IPV6,
3930                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3931                 RTE_PTYPE_INNER_L4_TCP,
3932                 RTE_PTYPE_INNER_L4_UDP,
3933                 RTE_PTYPE_UNKNOWN
3934         };
3935
3936         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3937             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3938             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3939             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3940                 return ptypes;
3941
3942 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3943         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3944             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3945                 return ptypes;
3946 #endif
3947         return NULL;
3948 }
3949
3950 static int
3951 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3952                      struct rte_eth_dev_info *dev_info)
3953 {
3954         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3956
3957         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3958         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3959         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3960         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3961         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3962         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3963         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3964         dev_info->max_vfs = pci_dev->max_vfs;
3965         if (hw->mac.type == ixgbe_mac_82598EB)
3966                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3967         else
3968                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3969         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3970         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3971                                      dev_info->rx_queue_offload_capa);
3972         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3973         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3974         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3975         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3976         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3977
3978         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3979                 .rx_thresh = {
3980                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3981                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3982                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3983                 },
3984                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3985                 .rx_drop_en = 0,
3986                 .offloads = 0,
3987         };
3988
3989         dev_info->default_txconf = (struct rte_eth_txconf) {
3990                 .tx_thresh = {
3991                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3992                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3993                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3994                 },
3995                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3996                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3997                 .offloads = 0,
3998         };
3999
4000         dev_info->rx_desc_lim = rx_desc_lim;
4001         dev_info->tx_desc_lim = tx_desc_lim;
4002
4003         return 0;
4004 }
4005
4006 static int
4007 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4008                    bool *link_up, int wait_to_complete)
4009 {
4010         struct ixgbe_adapter *adapter = container_of(hw,
4011                                                      struct ixgbe_adapter, hw);
4012         struct ixgbe_mbx_info *mbx = &hw->mbx;
4013         struct ixgbe_mac_info *mac = &hw->mac;
4014         uint32_t links_reg, in_msg;
4015         int ret_val = 0;
4016
4017         /* If we were hit with a reset drop the link */
4018         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4019                 mac->get_link_status = true;
4020
4021         if (!mac->get_link_status)
4022                 goto out;
4023
4024         /* if link status is down no point in checking to see if pf is up */
4025         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4026         if (!(links_reg & IXGBE_LINKS_UP))
4027                 goto out;
4028
4029         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4030          * before the link status is correct
4031          */
4032         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4033                 int i;
4034
4035                 for (i = 0; i < 5; i++) {
4036                         rte_delay_us(100);
4037                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4038
4039                         if (!(links_reg & IXGBE_LINKS_UP))
4040                                 goto out;
4041                 }
4042         }
4043
4044         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4045         case IXGBE_LINKS_SPEED_10G_82599:
4046                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4047                 if (hw->mac.type >= ixgbe_mac_X550) {
4048                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4049                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4050                 }
4051                 break;
4052         case IXGBE_LINKS_SPEED_1G_82599:
4053                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4054                 break;
4055         case IXGBE_LINKS_SPEED_100_82599:
4056                 *speed = IXGBE_LINK_SPEED_100_FULL;
4057                 if (hw->mac.type == ixgbe_mac_X550) {
4058                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4059                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4060                 }
4061                 break;
4062         case IXGBE_LINKS_SPEED_10_X550EM_A:
4063                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4064                 /* Since Reserved in older MAC's */
4065                 if (hw->mac.type >= ixgbe_mac_X550)
4066                         *speed = IXGBE_LINK_SPEED_10_FULL;
4067                 break;
4068         default:
4069                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4070         }
4071
4072         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4073                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4074                         mac->get_link_status = true;
4075                 else
4076                         mac->get_link_status = false;
4077
4078                 goto out;
4079         }
4080
4081         /* if the read failed it could just be a mailbox collision, best wait
4082          * until we are called again and don't report an error
4083          */
4084         if (mbx->ops.read(hw, &in_msg, 1, 0))
4085                 goto out;
4086
4087         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4088                 /* msg is not CTS and is NACK we must have lost CTS status */
4089                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4090                         mac->get_link_status = false;
4091                 goto out;
4092         }
4093
4094         /* the pf is talking, if we timed out in the past we reinit */
4095         if (!mbx->timeout) {
4096                 ret_val = -1;
4097                 goto out;
4098         }
4099
4100         /* if we passed all the tests above then the link is up and we no
4101          * longer need to check for link
4102          */
4103         mac->get_link_status = false;
4104
4105 out:
4106         *link_up = !mac->get_link_status;
4107         return ret_val;
4108 }
4109
4110 /*
4111  * If @timeout_ms was 0, it means that it will not return until link complete.
4112  * It returns 1 on complete, return 0 on timeout.
4113  */
4114 static int
4115 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4116 {
4117 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4118         struct ixgbe_adapter *ad = dev->data->dev_private;
4119         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4120
4121         while (rte_atomic32_read(&ad->link_thread_running)) {
4122                 msec_delay(1);
4123                 timeout--;
4124
4125                 if (timeout_ms) {
4126                         if (!timeout)
4127                                 return 0;
4128                 } else if (!timeout) {
4129                         /* It will not return until link complete */
4130                         timeout = WARNING_TIMEOUT;
4131                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4132                 }
4133         }
4134
4135         return 1;
4136 }
4137
4138 static void *
4139 ixgbe_dev_setup_link_thread_handler(void *param)
4140 {
4141         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4142         struct ixgbe_adapter *ad = dev->data->dev_private;
4143         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4144         struct ixgbe_interrupt *intr =
4145                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4146         u32 speed;
4147         bool autoneg = false;
4148
4149         pthread_detach(pthread_self());
4150         speed = hw->phy.autoneg_advertised;
4151         if (!speed)
4152                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4153
4154         ixgbe_setup_link(hw, speed, true);
4155
4156         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4157         rte_atomic32_clear(&ad->link_thread_running);
4158         return NULL;
4159 }
4160
4161 /*
4162  * In freebsd environment, nic_uio drivers do not support interrupts,
4163  * rte_intr_callback_register() will fail to register interrupts.
4164  * We can not make link status to change from down to up by interrupt
4165  * callback. So we need to wait for the controller to acquire link
4166  * when ports start.
4167  * It returns 0 on link up.
4168  */
4169 static int
4170 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4171 {
4172 #ifdef RTE_EXEC_ENV_FREEBSD
4173         int err, i;
4174         bool link_up = false;
4175         uint32_t speed = 0;
4176         const int nb_iter = 25;
4177
4178         for (i = 0; i < nb_iter; i++) {
4179                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4180                 if (err)
4181                         return err;
4182                 if (link_up)
4183                         return 0;
4184                 msec_delay(200);
4185         }
4186
4187         return 0;
4188 #else
4189         RTE_SET_USED(hw);
4190         return 0;
4191 #endif
4192 }
4193
4194 /* return 0 means link status changed, -1 means not changed */
4195 int
4196 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4197                             int wait_to_complete, int vf)
4198 {
4199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4200         struct ixgbe_adapter *ad = dev->data->dev_private;
4201         struct rte_eth_link link;
4202         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4203         struct ixgbe_interrupt *intr =
4204                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4205         bool link_up;
4206         int diag;
4207         int wait = 1;
4208         u32 esdp_reg;
4209
4210         memset(&link, 0, sizeof(link));
4211         link.link_status = ETH_LINK_DOWN;
4212         link.link_speed = ETH_SPEED_NUM_NONE;
4213         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4214         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4215                         ETH_LINK_SPEED_FIXED);
4216
4217         hw->mac.get_link_status = true;
4218
4219         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4220                 return rte_eth_linkstatus_set(dev, &link);
4221
4222         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4223         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4224                 wait = 0;
4225
4226 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4227 #ifdef RTE_EXEC_ENV_FREEBSD
4228         wait = 1;
4229 #endif
4230
4231         if (vf)
4232                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4233         else
4234                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4235
4236         if (diag != 0) {
4237                 link.link_speed = ETH_SPEED_NUM_100M;
4238                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4239                 return rte_eth_linkstatus_set(dev, &link);
4240         }
4241
4242         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4243                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4244                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4245                         link_up = 0;
4246         }
4247
4248         if (link_up == 0) {
4249                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4250                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4251                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4252                                 /* To avoid race condition between threads, set
4253                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4254                                  * when there is no link thread running.
4255                                  */
4256                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4257                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4258                                         "ixgbe-link-handler",
4259                                         NULL,
4260                                         ixgbe_dev_setup_link_thread_handler,
4261                                         dev) < 0) {
4262                                         PMD_DRV_LOG(ERR,
4263                                                 "Create link thread failed!");
4264                                         rte_atomic32_clear(&ad->link_thread_running);
4265                                 }
4266                         } else {
4267                                 PMD_DRV_LOG(ERR,
4268                                         "Other link thread is running now!");
4269                         }
4270                 }
4271                 return rte_eth_linkstatus_set(dev, &link);
4272         }
4273
4274         link.link_status = ETH_LINK_UP;
4275         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4276
4277         switch (link_speed) {
4278         default:
4279         case IXGBE_LINK_SPEED_UNKNOWN:
4280                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4281                 break;
4282
4283         case IXGBE_LINK_SPEED_10_FULL:
4284                 link.link_speed = ETH_SPEED_NUM_10M;
4285                 break;
4286
4287         case IXGBE_LINK_SPEED_100_FULL:
4288                 link.link_speed = ETH_SPEED_NUM_100M;
4289                 break;
4290
4291         case IXGBE_LINK_SPEED_1GB_FULL:
4292                 link.link_speed = ETH_SPEED_NUM_1G;
4293                 break;
4294
4295         case IXGBE_LINK_SPEED_2_5GB_FULL:
4296                 link.link_speed = ETH_SPEED_NUM_2_5G;
4297                 break;
4298
4299         case IXGBE_LINK_SPEED_5GB_FULL:
4300                 link.link_speed = ETH_SPEED_NUM_5G;
4301                 break;
4302
4303         case IXGBE_LINK_SPEED_10GB_FULL:
4304                 link.link_speed = ETH_SPEED_NUM_10G;
4305                 break;
4306         }
4307
4308         return rte_eth_linkstatus_set(dev, &link);
4309 }
4310
4311 static int
4312 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4313 {
4314         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4315 }
4316
4317 static int
4318 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4319 {
4320         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4321 }
4322
4323 static int
4324 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4325 {
4326         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4327         uint32_t fctrl;
4328
4329         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4330         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4331         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4332
4333         return 0;
4334 }
4335
4336 static int
4337 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4338 {
4339         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4340         uint32_t fctrl;
4341
4342         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4343         fctrl &= (~IXGBE_FCTRL_UPE);
4344         if (dev->data->all_multicast == 1)
4345                 fctrl |= IXGBE_FCTRL_MPE;
4346         else
4347                 fctrl &= (~IXGBE_FCTRL_MPE);
4348         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4349
4350         return 0;
4351 }
4352
4353 static int
4354 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4355 {
4356         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4357         uint32_t fctrl;
4358
4359         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4360         fctrl |= IXGBE_FCTRL_MPE;
4361         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4362
4363         return 0;
4364 }
4365
4366 static int
4367 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4368 {
4369         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4370         uint32_t fctrl;
4371
4372         if (dev->data->promiscuous == 1)
4373                 return 0; /* must remain in all_multicast mode */
4374
4375         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4376         fctrl &= (~IXGBE_FCTRL_MPE);
4377         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4378
4379         return 0;
4380 }
4381
4382 /**
4383  * It clears the interrupt causes and enables the interrupt.
4384  * It will be called once only during nic initialized.
4385  *
4386  * @param dev
4387  *  Pointer to struct rte_eth_dev.
4388  * @param on
4389  *  Enable or Disable.
4390  *
4391  * @return
4392  *  - On success, zero.
4393  *  - On failure, a negative value.
4394  */
4395 static int
4396 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4397 {
4398         struct ixgbe_interrupt *intr =
4399                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4400
4401         ixgbe_dev_link_status_print(dev);
4402         if (on)
4403                 intr->mask |= IXGBE_EICR_LSC;
4404         else
4405                 intr->mask &= ~IXGBE_EICR_LSC;
4406
4407         return 0;
4408 }
4409
4410 /**
4411  * It clears the interrupt causes and enables the interrupt.
4412  * It will be called once only during nic initialized.
4413  *
4414  * @param dev
4415  *  Pointer to struct rte_eth_dev.
4416  *
4417  * @return
4418  *  - On success, zero.
4419  *  - On failure, a negative value.
4420  */
4421 static int
4422 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4423 {
4424         struct ixgbe_interrupt *intr =
4425                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4426
4427         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4428
4429         return 0;
4430 }
4431
4432 /**
4433  * It clears the interrupt causes and enables the interrupt.
4434  * It will be called once only during nic initialized.
4435  *
4436  * @param dev
4437  *  Pointer to struct rte_eth_dev.
4438  *
4439  * @return
4440  *  - On success, zero.
4441  *  - On failure, a negative value.
4442  */
4443 static int
4444 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4445 {
4446         struct ixgbe_interrupt *intr =
4447                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4448
4449         intr->mask |= IXGBE_EICR_LINKSEC;
4450
4451         return 0;
4452 }
4453
4454 /*
4455  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4456  *
4457  * @param dev
4458  *  Pointer to struct rte_eth_dev.
4459  *
4460  * @return
4461  *  - On success, zero.
4462  *  - On failure, a negative value.
4463  */
4464 static int
4465 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4466 {
4467         uint32_t eicr;
4468         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4469         struct ixgbe_interrupt *intr =
4470                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4471
4472         /* clear all cause mask */
4473         ixgbe_disable_intr(hw);
4474
4475         /* read-on-clear nic registers here */
4476         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4477         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4478
4479         intr->flags = 0;
4480
4481         /* set flag for async link update */
4482         if (eicr & IXGBE_EICR_LSC)
4483                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4484
4485         if (eicr & IXGBE_EICR_MAILBOX)
4486                 intr->flags |= IXGBE_FLAG_MAILBOX;
4487
4488         if (eicr & IXGBE_EICR_LINKSEC)
4489                 intr->flags |= IXGBE_FLAG_MACSEC;
4490
4491         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4492             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4493             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4494                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4495
4496         return 0;
4497 }
4498
4499 /**
4500  * It gets and then prints the link status.
4501  *
4502  * @param dev
4503  *  Pointer to struct rte_eth_dev.
4504  *
4505  * @return
4506  *  - On success, zero.
4507  *  - On failure, a negative value.
4508  */
4509 static void
4510 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4511 {
4512         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4513         struct rte_eth_link link;
4514
4515         rte_eth_linkstatus_get(dev, &link);
4516
4517         if (link.link_status) {
4518                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4519                                         (int)(dev->data->port_id),
4520                                         (unsigned)link.link_speed,
4521                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4522                                         "full-duplex" : "half-duplex");
4523         } else {
4524                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4525                                 (int)(dev->data->port_id));
4526         }
4527         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4528                                 pci_dev->addr.domain,
4529                                 pci_dev->addr.bus,
4530                                 pci_dev->addr.devid,
4531                                 pci_dev->addr.function);
4532 }
4533
4534 /*
4535  * It executes link_update after knowing an interrupt occurred.
4536  *
4537  * @param dev
4538  *  Pointer to struct rte_eth_dev.
4539  *
4540  * @return
4541  *  - On success, zero.
4542  *  - On failure, a negative value.
4543  */
4544 static int
4545 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4546 {
4547         struct ixgbe_interrupt *intr =
4548                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4549         int64_t timeout;
4550         struct ixgbe_hw *hw =
4551                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4552
4553         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4554
4555         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4556                 ixgbe_pf_mbx_process(dev);
4557                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4558         }
4559
4560         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4561                 ixgbe_handle_lasi(hw);
4562                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4563         }
4564
4565         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4566                 struct rte_eth_link link;
4567
4568                 /* get the link status before link update, for predicting later */
4569                 rte_eth_linkstatus_get(dev, &link);
4570
4571                 ixgbe_dev_link_update(dev, 0);
4572
4573                 /* likely to up */
4574                 if (!link.link_status)
4575                         /* handle it 1 sec later, wait it being stable */
4576                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4577                 /* likely to down */
4578                 else
4579                         /* handle it 4 sec later, wait it being stable */
4580                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4581
4582                 ixgbe_dev_link_status_print(dev);
4583                 if (rte_eal_alarm_set(timeout * 1000,
4584                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4585                         PMD_DRV_LOG(ERR, "Error setting alarm");
4586                 else {
4587                         /* remember original mask */
4588                         intr->mask_original = intr->mask;
4589                         /* only disable lsc interrupt */
4590                         intr->mask &= ~IXGBE_EIMS_LSC;
4591                 }
4592         }
4593
4594         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4595         ixgbe_enable_intr(dev);
4596
4597         return 0;
4598 }
4599
4600 /**
4601  * Interrupt handler which shall be registered for alarm callback for delayed
4602  * handling specific interrupt to wait for the stable nic state. As the
4603  * NIC interrupt state is not stable for ixgbe after link is just down,
4604  * it needs to wait 4 seconds to get the stable status.
4605  *
4606  * @param handle
4607  *  Pointer to interrupt handle.
4608  * @param param
4609  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4610  *
4611  * @return
4612  *  void
4613  */
4614 static void
4615 ixgbe_dev_interrupt_delayed_handler(void *param)
4616 {
4617         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4618         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4619         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4620         struct ixgbe_interrupt *intr =
4621                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4622         struct ixgbe_hw *hw =
4623                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4624         uint32_t eicr;
4625
4626         ixgbe_disable_intr(hw);
4627
4628         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4629         if (eicr & IXGBE_EICR_MAILBOX)
4630                 ixgbe_pf_mbx_process(dev);
4631
4632         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4633                 ixgbe_handle_lasi(hw);
4634                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4635         }
4636
4637         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4638                 ixgbe_dev_link_update(dev, 0);
4639                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4640                 ixgbe_dev_link_status_print(dev);
4641                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4642         }
4643
4644         if (intr->flags & IXGBE_FLAG_MACSEC) {
4645                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4646                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4647         }
4648
4649         /* restore original mask */
4650         intr->mask = intr->mask_original;
4651         intr->mask_original = 0;
4652
4653         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4654         ixgbe_enable_intr(dev);
4655         rte_intr_ack(intr_handle);
4656 }
4657
4658 /**
4659  * Interrupt handler triggered by NIC  for handling
4660  * specific interrupt.
4661  *
4662  * @param handle
4663  *  Pointer to interrupt handle.
4664  * @param param
4665  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4666  *
4667  * @return
4668  *  void
4669  */
4670 static void
4671 ixgbe_dev_interrupt_handler(void *param)
4672 {
4673         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4674
4675         ixgbe_dev_interrupt_get_status(dev);
4676         ixgbe_dev_interrupt_action(dev);
4677 }
4678
4679 static int
4680 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4681 {
4682         struct ixgbe_hw *hw;
4683
4684         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4686 }
4687
4688 static int
4689 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4690 {
4691         struct ixgbe_hw *hw;
4692
4693         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4694         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4695 }
4696
4697 static int
4698 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4699 {
4700         struct ixgbe_hw *hw;
4701         uint32_t mflcn_reg;
4702         uint32_t fccfg_reg;
4703         int rx_pause;
4704         int tx_pause;
4705
4706         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4707
4708         fc_conf->pause_time = hw->fc.pause_time;
4709         fc_conf->high_water = hw->fc.high_water[0];
4710         fc_conf->low_water = hw->fc.low_water[0];
4711         fc_conf->send_xon = hw->fc.send_xon;
4712         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4713
4714         /*
4715          * Return rx_pause status according to actual setting of
4716          * MFLCN register.
4717          */
4718         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4719         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4720                 fc_conf->mac_ctrl_frame_fwd = 1;
4721         else
4722                 fc_conf->mac_ctrl_frame_fwd = 0;
4723
4724         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4725                 rx_pause = 1;
4726         else
4727                 rx_pause = 0;
4728
4729         /*
4730          * Return tx_pause status according to actual setting of
4731          * FCCFG register.
4732          */
4733         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4734         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4735                 tx_pause = 1;
4736         else
4737                 tx_pause = 0;
4738
4739         if (rx_pause && tx_pause)
4740                 fc_conf->mode = RTE_FC_FULL;
4741         else if (rx_pause)
4742                 fc_conf->mode = RTE_FC_RX_PAUSE;
4743         else if (tx_pause)
4744                 fc_conf->mode = RTE_FC_TX_PAUSE;
4745         else
4746                 fc_conf->mode = RTE_FC_NONE;
4747
4748         return 0;
4749 }
4750
4751 static int
4752 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4753 {
4754         struct ixgbe_hw *hw;
4755         struct ixgbe_adapter *adapter = dev->data->dev_private;
4756         int err;
4757         uint32_t rx_buf_size;
4758         uint32_t max_high_water;
4759         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4760                 ixgbe_fc_none,
4761                 ixgbe_fc_rx_pause,
4762                 ixgbe_fc_tx_pause,
4763                 ixgbe_fc_full
4764         };
4765
4766         PMD_INIT_FUNC_TRACE();
4767
4768         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4769         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4770         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4771
4772         /*
4773          * At least reserve one Ethernet frame for watermark
4774          * high_water/low_water in kilo bytes for ixgbe
4775          */
4776         max_high_water = (rx_buf_size -
4777                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4778         if ((fc_conf->high_water > max_high_water) ||
4779                 (fc_conf->high_water < fc_conf->low_water)) {
4780                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4781                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4782                 return -EINVAL;
4783         }
4784
4785         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4786         hw->fc.pause_time     = fc_conf->pause_time;
4787         hw->fc.high_water[0]  = fc_conf->high_water;
4788         hw->fc.low_water[0]   = fc_conf->low_water;
4789         hw->fc.send_xon       = fc_conf->send_xon;
4790         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4791         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4792
4793         err = ixgbe_flow_ctrl_enable(dev, hw);
4794         if (err < 0) {
4795                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4796                 return -EIO;
4797         }
4798         return err;
4799 }
4800
4801 /**
4802  *  ixgbe_pfc_enable_generic - Enable flow control
4803  *  @hw: pointer to hardware structure
4804  *  @tc_num: traffic class number
4805  *  Enable flow control according to the current settings.
4806  */
4807 static int
4808 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4809 {
4810         int ret_val = 0;
4811         uint32_t mflcn_reg, fccfg_reg;
4812         uint32_t reg;
4813         uint32_t fcrtl, fcrth;
4814         uint8_t i;
4815         uint8_t nb_rx_en;
4816
4817         /* Validate the water mark configuration */
4818         if (!hw->fc.pause_time) {
4819                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4820                 goto out;
4821         }
4822
4823         /* Low water mark of zero causes XOFF floods */
4824         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4825                  /* High/Low water can not be 0 */
4826                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4827                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4828                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4829                         goto out;
4830                 }
4831
4832                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4833                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4834                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4835                         goto out;
4836                 }
4837         }
4838         /* Negotiate the fc mode to use */
4839         ixgbe_fc_autoneg(hw);
4840
4841         /* Disable any previous flow control settings */
4842         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4843         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4844
4845         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4846         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4847
4848         switch (hw->fc.current_mode) {
4849         case ixgbe_fc_none:
4850                 /*
4851                  * If the count of enabled RX Priority Flow control >1,
4852                  * and the TX pause can not be disabled
4853                  */
4854                 nb_rx_en = 0;
4855                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4856                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4857                         if (reg & IXGBE_FCRTH_FCEN)
4858                                 nb_rx_en++;
4859                 }
4860                 if (nb_rx_en > 1)
4861                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4862                 break;
4863         case ixgbe_fc_rx_pause:
4864                 /*
4865                  * Rx Flow control is enabled and Tx Flow control is
4866                  * disabled by software override. Since there really
4867                  * isn't a way to advertise that we are capable of RX
4868                  * Pause ONLY, we will advertise that we support both
4869                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4870                  * disable the adapter's ability to send PAUSE frames.
4871                  */
4872                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4873                 /*
4874                  * If the count of enabled RX Priority Flow control >1,
4875                  * and the TX pause can not be disabled
4876                  */
4877                 nb_rx_en = 0;
4878                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4879                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4880                         if (reg & IXGBE_FCRTH_FCEN)
4881                                 nb_rx_en++;
4882                 }
4883                 if (nb_rx_en > 1)
4884                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4885                 break;
4886         case ixgbe_fc_tx_pause:
4887                 /*
4888                  * Tx Flow control is enabled, and Rx Flow control is
4889                  * disabled by software override.
4890                  */
4891                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4892                 break;
4893         case ixgbe_fc_full:
4894                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4895                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4896                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4897                 break;
4898         default:
4899                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4900                 ret_val = IXGBE_ERR_CONFIG;
4901                 goto out;
4902         }
4903
4904         /* Set 802.3x based flow control settings. */
4905         mflcn_reg |= IXGBE_MFLCN_DPF;
4906         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4907         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4908
4909         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4910         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4911                 hw->fc.high_water[tc_num]) {
4912                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4913                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4914                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4915         } else {
4916                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4917                 /*
4918                  * In order to prevent Tx hangs when the internal Tx
4919                  * switch is enabled we must set the high water mark
4920                  * to the maximum FCRTH value.  This allows the Tx
4921                  * switch to function even under heavy Rx workloads.
4922                  */
4923                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4924         }
4925         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4926
4927         /* Configure pause time (2 TCs per register) */
4928         reg = hw->fc.pause_time * 0x00010001;
4929         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4930                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4931
4932         /* Configure flow control refresh threshold value */
4933         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4934
4935 out:
4936         return ret_val;
4937 }
4938
4939 static int
4940 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4941 {
4942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4943         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4944
4945         if (hw->mac.type != ixgbe_mac_82598EB) {
4946                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4947         }
4948         return ret_val;
4949 }
4950
4951 static int
4952 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4953 {
4954         int err;
4955         uint32_t rx_buf_size;
4956         uint32_t max_high_water;
4957         uint8_t tc_num;
4958         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4959         struct ixgbe_hw *hw =
4960                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4961         struct ixgbe_dcb_config *dcb_config =
4962                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4963
4964         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4965                 ixgbe_fc_none,
4966                 ixgbe_fc_rx_pause,
4967                 ixgbe_fc_tx_pause,
4968                 ixgbe_fc_full
4969         };
4970
4971         PMD_INIT_FUNC_TRACE();
4972
4973         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4974         tc_num = map[pfc_conf->priority];
4975         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4976         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4977         /*
4978          * At least reserve one Ethernet frame for watermark
4979          * high_water/low_water in kilo bytes for ixgbe
4980          */
4981         max_high_water = (rx_buf_size -
4982                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4983         if ((pfc_conf->fc.high_water > max_high_water) ||
4984             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4985                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4986                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4987                 return -EINVAL;
4988         }
4989
4990         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4991         hw->fc.pause_time = pfc_conf->fc.pause_time;
4992         hw->fc.send_xon = pfc_conf->fc.send_xon;
4993         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4994         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4995
4996         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4997
4998         /* Not negotiated is not an error case */
4999         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5000                 return 0;
5001
5002         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5003         return -EIO;
5004 }
5005
5006 static int
5007 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5008                           struct rte_eth_rss_reta_entry64 *reta_conf,
5009                           uint16_t reta_size)
5010 {
5011         uint16_t i, sp_reta_size;
5012         uint8_t j, mask;
5013         uint32_t reta, r;
5014         uint16_t idx, shift;
5015         struct ixgbe_adapter *adapter = dev->data->dev_private;
5016         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5017         uint32_t reta_reg;
5018
5019         PMD_INIT_FUNC_TRACE();
5020
5021         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5022                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5023                         "NIC.");
5024                 return -ENOTSUP;
5025         }
5026
5027         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5028         if (reta_size != sp_reta_size) {
5029                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5030                         "(%d) doesn't match the number hardware can supported "
5031                         "(%d)", reta_size, sp_reta_size);
5032                 return -EINVAL;
5033         }
5034
5035         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5036                 idx = i / RTE_RETA_GROUP_SIZE;
5037                 shift = i % RTE_RETA_GROUP_SIZE;
5038                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5039                                                 IXGBE_4_BIT_MASK);
5040                 if (!mask)
5041                         continue;
5042                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5043                 if (mask == IXGBE_4_BIT_MASK)
5044                         r = 0;
5045                 else
5046                         r = IXGBE_READ_REG(hw, reta_reg);
5047                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5048                         if (mask & (0x1 << j))
5049                                 reta |= reta_conf[idx].reta[shift + j] <<
5050                                                         (CHAR_BIT * j);
5051                         else
5052                                 reta |= r & (IXGBE_8_BIT_MASK <<
5053                                                 (CHAR_BIT * j));
5054                 }
5055                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5056         }
5057         adapter->rss_reta_updated = 1;
5058
5059         return 0;
5060 }
5061
5062 static int
5063 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5064                          struct rte_eth_rss_reta_entry64 *reta_conf,
5065                          uint16_t reta_size)
5066 {
5067         uint16_t i, sp_reta_size;
5068         uint8_t j, mask;
5069         uint32_t reta;
5070         uint16_t idx, shift;
5071         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5072         uint32_t reta_reg;
5073
5074         PMD_INIT_FUNC_TRACE();
5075         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5076         if (reta_size != sp_reta_size) {
5077                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5078                         "(%d) doesn't match the number hardware can supported "
5079                         "(%d)", reta_size, sp_reta_size);
5080                 return -EINVAL;
5081         }
5082
5083         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5084                 idx = i / RTE_RETA_GROUP_SIZE;
5085                 shift = i % RTE_RETA_GROUP_SIZE;
5086                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5087                                                 IXGBE_4_BIT_MASK);
5088                 if (!mask)
5089                         continue;
5090
5091                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5092                 reta = IXGBE_READ_REG(hw, reta_reg);
5093                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5094                         if (mask & (0x1 << j))
5095                                 reta_conf[idx].reta[shift + j] =
5096                                         ((reta >> (CHAR_BIT * j)) &
5097                                                 IXGBE_8_BIT_MASK);
5098                 }
5099         }
5100
5101         return 0;
5102 }
5103
5104 static int
5105 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5106                                 uint32_t index, uint32_t pool)
5107 {
5108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109         uint32_t enable_addr = 1;
5110
5111         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5112                              pool, enable_addr);
5113 }
5114
5115 static void
5116 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5117 {
5118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5119
5120         ixgbe_clear_rar(hw, index);
5121 }
5122
5123 static int
5124 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5125 {
5126         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5127
5128         ixgbe_remove_rar(dev, 0);
5129         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5130
5131         return 0;
5132 }
5133
5134 static bool
5135 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5136 {
5137         if (strcmp(dev->device->driver->name, drv->driver.name))
5138                 return false;
5139
5140         return true;
5141 }
5142
5143 bool
5144 is_ixgbe_supported(struct rte_eth_dev *dev)
5145 {
5146         return is_device_supported(dev, &rte_ixgbe_pmd);
5147 }
5148
5149 static int
5150 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5151 {
5152         uint32_t hlreg0;
5153         uint32_t maxfrs;
5154         struct ixgbe_hw *hw;
5155         struct rte_eth_dev_info dev_info;
5156         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5157         struct rte_eth_dev_data *dev_data = dev->data;
5158         int ret;
5159
5160         ret = ixgbe_dev_info_get(dev, &dev_info);
5161         if (ret != 0)
5162                 return ret;
5163
5164         /* check that mtu is within the allowed range */
5165         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5166                 return -EINVAL;
5167
5168         /* If device is started, refuse mtu that requires the support of
5169          * scattered packets when this feature has not been enabled before.
5170          */
5171         if (dev_data->dev_started && !dev_data->scattered_rx &&
5172             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5173              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5174                 PMD_INIT_LOG(ERR, "Stop port first.");
5175                 return -EINVAL;
5176         }
5177
5178         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5179         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5180
5181         /* switch to jumbo mode if needed */
5182         if (frame_size > IXGBE_ETH_MAX_LEN) {
5183                 dev->data->dev_conf.rxmode.offloads |=
5184                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5185                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5186         } else {
5187                 dev->data->dev_conf.rxmode.offloads &=
5188                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5189                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5190         }
5191         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5192
5193         /* update max frame size */
5194         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5195
5196         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5197         maxfrs &= 0x0000FFFF;
5198         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5199         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5200
5201         return 0;
5202 }
5203
5204 /*
5205  * Virtual Function operations
5206  */
5207 static void
5208 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5209 {
5210         struct ixgbe_interrupt *intr =
5211                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5212         struct ixgbe_hw *hw =
5213                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5214
5215         PMD_INIT_FUNC_TRACE();
5216
5217         /* Clear interrupt mask to stop from interrupts being generated */
5218         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5219
5220         IXGBE_WRITE_FLUSH(hw);
5221
5222         /* Clear mask value. */
5223         intr->mask = 0;
5224 }
5225
5226 static void
5227 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5228 {
5229         struct ixgbe_interrupt *intr =
5230                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5231         struct ixgbe_hw *hw =
5232                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5233
5234         PMD_INIT_FUNC_TRACE();
5235
5236         /* VF enable interrupt autoclean */
5237         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5238         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5239         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5240
5241         IXGBE_WRITE_FLUSH(hw);
5242
5243         /* Save IXGBE_VTEIMS value to mask. */
5244         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5245 }
5246
5247 static int
5248 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5249 {
5250         struct rte_eth_conf *conf = &dev->data->dev_conf;
5251         struct ixgbe_adapter *adapter = dev->data->dev_private;
5252
5253         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5254                      dev->data->port_id);
5255
5256         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5257                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5258
5259         /*
5260          * VF has no ability to enable/disable HW CRC
5261          * Keep the persistent behavior the same as Host PF
5262          */
5263 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5264         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5265                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5266                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5267         }
5268 #else
5269         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5270                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5271                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5272         }
5273 #endif
5274
5275         /*
5276          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5277          * allocation or vector Rx preconditions we will reset it.
5278          */
5279         adapter->rx_bulk_alloc_allowed = true;
5280         adapter->rx_vec_allowed = true;
5281
5282         return 0;
5283 }
5284
5285 static int
5286 ixgbevf_dev_start(struct rte_eth_dev *dev)
5287 {
5288         struct ixgbe_hw *hw =
5289                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5290         uint32_t intr_vector = 0;
5291         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5292         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5293
5294         int err, mask = 0;
5295
5296         PMD_INIT_FUNC_TRACE();
5297
5298         /* Stop the link setup handler before resetting the HW. */
5299         ixgbe_dev_wait_setup_link_complete(dev, 0);
5300
5301         err = hw->mac.ops.reset_hw(hw);
5302
5303         /**
5304          * In this case, reuses the MAC address assigned by VF
5305          * initialization.
5306          */
5307         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5308                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5309                 return err;
5310         }
5311
5312         hw->mac.get_link_status = true;
5313
5314         /* negotiate mailbox API version to use with the PF. */
5315         ixgbevf_negotiate_api(hw);
5316
5317         ixgbevf_dev_tx_init(dev);
5318
5319         /* This can fail when allocating mbufs for descriptor rings */
5320         err = ixgbevf_dev_rx_init(dev);
5321         if (err) {
5322                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5323                 ixgbe_dev_clear_queues(dev);
5324                 return err;
5325         }
5326
5327         /* Set vfta */
5328         ixgbevf_set_vfta_all(dev, 1);
5329
5330         /* Set HW strip */
5331         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5332                 ETH_VLAN_EXTEND_MASK;
5333         err = ixgbevf_vlan_offload_config(dev, mask);
5334         if (err) {
5335                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5336                 ixgbe_dev_clear_queues(dev);
5337                 return err;
5338         }
5339
5340         ixgbevf_dev_rxtx_start(dev);
5341
5342         /* check and configure queue intr-vector mapping */
5343         if (rte_intr_cap_multiple(intr_handle) &&
5344             dev->data->dev_conf.intr_conf.rxq) {
5345                 /* According to datasheet, only vector 0/1/2 can be used,
5346                  * now only one vector is used for Rx queue
5347                  */
5348                 intr_vector = 1;
5349                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5350                         return -1;
5351         }
5352
5353         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5354                 intr_handle->intr_vec =
5355                         rte_zmalloc("intr_vec",
5356                                     dev->data->nb_rx_queues * sizeof(int), 0);
5357                 if (intr_handle->intr_vec == NULL) {
5358                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5359                                      " intr_vec", dev->data->nb_rx_queues);
5360                         return -ENOMEM;
5361                 }
5362         }
5363         ixgbevf_configure_msix(dev);
5364
5365         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5366          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5367          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5368          * is not cleared, it will fail when following rte_intr_enable( ) tries
5369          * to map Rx queue interrupt to other VFIO vectors.
5370          * So clear uio/vfio intr/evevnfd first to avoid failure.
5371          */
5372         rte_intr_disable(intr_handle);
5373
5374         rte_intr_enable(intr_handle);
5375
5376         /* Re-enable interrupt for VF */
5377         ixgbevf_intr_enable(dev);
5378
5379         /*
5380          * Update link status right before return, because it may
5381          * start link configuration process in a separate thread.
5382          */
5383         ixgbevf_dev_link_update(dev, 0);
5384
5385         hw->adapter_stopped = false;
5386
5387         return 0;
5388 }
5389
5390 static int
5391 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5392 {
5393         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5394         struct ixgbe_adapter *adapter = dev->data->dev_private;
5395         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5396         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5397
5398         if (hw->adapter_stopped)
5399                 return 0;
5400
5401         PMD_INIT_FUNC_TRACE();
5402
5403         ixgbe_dev_wait_setup_link_complete(dev, 0);
5404
5405         ixgbevf_intr_disable(dev);
5406
5407         dev->data->dev_started = 0;
5408         hw->adapter_stopped = 1;
5409         ixgbe_stop_adapter(hw);
5410
5411         /*
5412           * Clear what we set, but we still keep shadow_vfta to
5413           * restore after device starts
5414           */
5415         ixgbevf_set_vfta_all(dev, 0);
5416
5417         /* Clear stored conf */
5418         dev->data->scattered_rx = 0;
5419
5420         ixgbe_dev_clear_queues(dev);
5421
5422         /* Clean datapath event and queue/vec mapping */
5423         rte_intr_efd_disable(intr_handle);
5424         if (intr_handle->intr_vec != NULL) {
5425                 rte_free(intr_handle->intr_vec);
5426                 intr_handle->intr_vec = NULL;
5427         }
5428
5429         adapter->rss_reta_updated = 0;
5430
5431         return 0;
5432 }
5433
5434 static int
5435 ixgbevf_dev_close(struct rte_eth_dev *dev)
5436 {
5437         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5438         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5439         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5440         int ret;
5441
5442         PMD_INIT_FUNC_TRACE();
5443         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5444                 return 0;
5445
5446         ixgbe_reset_hw(hw);
5447
5448         ret = ixgbevf_dev_stop(dev);
5449
5450         ixgbe_dev_free_queues(dev);
5451
5452         /**
5453          * Remove the VF MAC address ro ensure
5454          * that the VF traffic goes to the PF
5455          * after stop, close and detach of the VF
5456          **/
5457         ixgbevf_remove_mac_addr(dev, 0);
5458
5459         rte_intr_disable(intr_handle);
5460         rte_intr_callback_unregister(intr_handle,
5461                                      ixgbevf_dev_interrupt_handler, dev);
5462
5463         return ret;
5464 }
5465
5466 /*
5467  * Reset VF device
5468  */
5469 static int
5470 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5471 {
5472         int ret;
5473
5474         ret = eth_ixgbevf_dev_uninit(dev);
5475         if (ret)
5476                 return ret;
5477
5478         ret = eth_ixgbevf_dev_init(dev);
5479
5480         return ret;
5481 }
5482
5483 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5484 {
5485         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5486         struct ixgbe_vfta *shadow_vfta =
5487                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5488         int i = 0, j = 0, vfta = 0, mask = 1;
5489
5490         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5491                 vfta = shadow_vfta->vfta[i];
5492                 if (vfta) {
5493                         mask = 1;
5494                         for (j = 0; j < 32; j++) {
5495                                 if (vfta & mask)
5496                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5497                                                        on, false);
5498                                 mask <<= 1;
5499                         }
5500                 }
5501         }
5502
5503 }
5504
5505 static int
5506 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5507 {
5508         struct ixgbe_hw *hw =
5509                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5510         struct ixgbe_vfta *shadow_vfta =
5511                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5512         uint32_t vid_idx = 0;
5513         uint32_t vid_bit = 0;
5514         int ret = 0;
5515
5516         PMD_INIT_FUNC_TRACE();
5517
5518         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5519         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5520         if (ret) {
5521                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5522                 return ret;
5523         }
5524         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5525         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5526
5527         /* Save what we set and retore it after device reset */
5528         if (on)
5529                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5530         else
5531                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5532
5533         return 0;
5534 }
5535
5536 static void
5537 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5538 {
5539         struct ixgbe_hw *hw =
5540                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5541         uint32_t ctrl;
5542
5543         PMD_INIT_FUNC_TRACE();
5544
5545         if (queue >= hw->mac.max_rx_queues)
5546                 return;
5547
5548         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5549         if (on)
5550                 ctrl |= IXGBE_RXDCTL_VME;
5551         else
5552                 ctrl &= ~IXGBE_RXDCTL_VME;
5553         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5554
5555         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5556 }
5557
5558 static int
5559 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5560 {
5561         struct ixgbe_rx_queue *rxq;
5562         uint16_t i;
5563         int on = 0;
5564
5565         /* VF function only support hw strip feature, others are not support */
5566         if (mask & ETH_VLAN_STRIP_MASK) {
5567                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5568                         rxq = dev->data->rx_queues[i];
5569                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5570                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5571                 }
5572         }
5573
5574         return 0;
5575 }
5576
5577 static int
5578 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5579 {
5580         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5581
5582         ixgbevf_vlan_offload_config(dev, mask);
5583
5584         return 0;
5585 }
5586
5587 int
5588 ixgbe_vt_check(struct ixgbe_hw *hw)
5589 {
5590         uint32_t reg_val;
5591
5592         /* if Virtualization Technology is enabled */
5593         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5594         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5595                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5596                 return -1;
5597         }
5598
5599         return 0;
5600 }
5601
5602 static uint32_t
5603 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5604 {
5605         uint32_t vector = 0;
5606
5607         switch (hw->mac.mc_filter_type) {
5608         case 0:   /* use bits [47:36] of the address */
5609                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5610                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5611                 break;
5612         case 1:   /* use bits [46:35] of the address */
5613                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5614                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5615                 break;
5616         case 2:   /* use bits [45:34] of the address */
5617                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5618                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5619                 break;
5620         case 3:   /* use bits [43:32] of the address */
5621                 vector = ((uc_addr->addr_bytes[4]) |
5622                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5623                 break;
5624         default:  /* Invalid mc_filter_type */
5625                 break;
5626         }
5627
5628         /* vector can only be 12-bits or boundary will be exceeded */
5629         vector &= 0xFFF;
5630         return vector;
5631 }
5632
5633 static int
5634 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5635                         struct rte_ether_addr *mac_addr, uint8_t on)
5636 {
5637         uint32_t vector;
5638         uint32_t uta_idx;
5639         uint32_t reg_val;
5640         uint32_t uta_shift;
5641         uint32_t rc;
5642         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5643         const uint32_t ixgbe_uta_bit_shift = 5;
5644         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5645         const uint32_t bit1 = 0x1;
5646
5647         struct ixgbe_hw *hw =
5648                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649         struct ixgbe_uta_info *uta_info =
5650                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5651
5652         /* The UTA table only exists on 82599 hardware and newer */
5653         if (hw->mac.type < ixgbe_mac_82599EB)
5654                 return -ENOTSUP;
5655
5656         vector = ixgbe_uta_vector(hw, mac_addr);
5657         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5658         uta_shift = vector & ixgbe_uta_bit_mask;
5659
5660         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5661         if (rc == on)
5662                 return 0;
5663
5664         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5665         if (on) {
5666                 uta_info->uta_in_use++;
5667                 reg_val |= (bit1 << uta_shift);
5668                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5669         } else {
5670                 uta_info->uta_in_use--;
5671                 reg_val &= ~(bit1 << uta_shift);
5672                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5673         }
5674
5675         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5676
5677         if (uta_info->uta_in_use > 0)
5678                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5679                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5680         else
5681                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5682
5683         return 0;
5684 }
5685
5686 static int
5687 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5688 {
5689         int i;
5690         struct ixgbe_hw *hw =
5691                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5692         struct ixgbe_uta_info *uta_info =
5693                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5694
5695         /* The UTA table only exists on 82599 hardware and newer */
5696         if (hw->mac.type < ixgbe_mac_82599EB)
5697                 return -ENOTSUP;
5698
5699         if (on) {
5700                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5701                         uta_info->uta_shadow[i] = ~0;
5702                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5703                 }
5704         } else {
5705                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5706                         uta_info->uta_shadow[i] = 0;
5707                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5708                 }
5709         }
5710         return 0;
5711
5712 }
5713
5714 uint32_t
5715 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5716 {
5717         uint32_t new_val = orig_val;
5718
5719         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5720                 new_val |= IXGBE_VMOLR_AUPE;
5721         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5722                 new_val |= IXGBE_VMOLR_ROMPE;
5723         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5724                 new_val |= IXGBE_VMOLR_ROPE;
5725         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5726                 new_val |= IXGBE_VMOLR_BAM;
5727         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5728                 new_val |= IXGBE_VMOLR_MPE;
5729
5730         return new_val;
5731 }
5732
5733 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5734 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5735 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5736 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5737 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5738         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5739         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5740
5741 static int
5742 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5743                       struct rte_eth_mirror_conf *mirror_conf,
5744                       uint8_t rule_id, uint8_t on)
5745 {
5746         uint32_t mr_ctl, vlvf;
5747         uint32_t mp_lsb = 0;
5748         uint32_t mv_msb = 0;
5749         uint32_t mv_lsb = 0;
5750         uint32_t mp_msb = 0;
5751         uint8_t i = 0;
5752         int reg_index = 0;
5753         uint64_t vlan_mask = 0;
5754
5755         const uint8_t pool_mask_offset = 32;
5756         const uint8_t vlan_mask_offset = 32;
5757         const uint8_t dst_pool_offset = 8;
5758         const uint8_t rule_mr_offset  = 4;
5759         const uint8_t mirror_rule_mask = 0x0F;
5760
5761         struct ixgbe_mirror_info *mr_info =
5762                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5763         struct ixgbe_hw *hw =
5764                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5765         uint8_t mirror_type = 0;
5766
5767         if (ixgbe_vt_check(hw) < 0)
5768                 return -ENOTSUP;
5769
5770         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5771                 return -EINVAL;
5772
5773         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5774                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5775                             mirror_conf->rule_type);
5776                 return -EINVAL;
5777         }
5778
5779         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5780                 mirror_type |= IXGBE_MRCTL_VLME;
5781                 /* Check if vlan id is valid and find conresponding VLAN ID
5782                  * index in VLVF
5783                  */
5784                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5785                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5786                                 /* search vlan id related pool vlan filter
5787                                  * index
5788                                  */
5789                                 reg_index = ixgbe_find_vlvf_slot(
5790                                                 hw,
5791                                                 mirror_conf->vlan.vlan_id[i],
5792                                                 false);
5793                                 if (reg_index < 0)
5794                                         return -EINVAL;
5795                                 vlvf = IXGBE_READ_REG(hw,
5796                                                       IXGBE_VLVF(reg_index));
5797                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5798                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5799                                       mirror_conf->vlan.vlan_id[i]))
5800                                         vlan_mask |= (1ULL << reg_index);
5801                                 else
5802                                         return -EINVAL;
5803                         }
5804                 }
5805
5806                 if (on) {
5807                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5808                         mv_msb = vlan_mask >> vlan_mask_offset;
5809
5810                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5811                                                 mirror_conf->vlan.vlan_mask;
5812                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5813                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5814                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5815                                                 mirror_conf->vlan.vlan_id[i];
5816                         }
5817                 } else {
5818                         mv_lsb = 0;
5819                         mv_msb = 0;
5820                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5821                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5822                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5823                 }
5824         }
5825
5826         /**
5827          * if enable pool mirror, write related pool mask register,if disable
5828          * pool mirror, clear PFMRVM register
5829          */
5830         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5831                 mirror_type |= IXGBE_MRCTL_VPME;
5832                 if (on) {
5833                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5834                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5835                         mr_info->mr_conf[rule_id].pool_mask =
5836                                         mirror_conf->pool_mask;
5837
5838                 } else {
5839                         mp_lsb = 0;
5840                         mp_msb = 0;
5841                         mr_info->mr_conf[rule_id].pool_mask = 0;
5842                 }
5843         }
5844         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5845                 mirror_type |= IXGBE_MRCTL_UPME;
5846         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5847                 mirror_type |= IXGBE_MRCTL_DPME;
5848
5849         /* read  mirror control register and recalculate it */
5850         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5851
5852         if (on) {
5853                 mr_ctl |= mirror_type;
5854                 mr_ctl &= mirror_rule_mask;
5855                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5856         } else {
5857                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5858         }
5859
5860         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5861         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5862
5863         /* write mirrror control  register */
5864         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5865
5866         /* write pool mirrror control  register */
5867         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5868                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5869                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5870                                 mp_msb);
5871         }
5872         /* write VLAN mirrror control  register */
5873         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5874                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5875                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5876                                 mv_msb);
5877         }
5878
5879         return 0;
5880 }
5881
5882 static int
5883 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5884 {
5885         int mr_ctl = 0;
5886         uint32_t lsb_val = 0;
5887         uint32_t msb_val = 0;
5888         const uint8_t rule_mr_offset = 4;
5889
5890         struct ixgbe_hw *hw =
5891                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5892         struct ixgbe_mirror_info *mr_info =
5893                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5894
5895         if (ixgbe_vt_check(hw) < 0)
5896                 return -ENOTSUP;
5897
5898         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5899                 return -EINVAL;
5900
5901         memset(&mr_info->mr_conf[rule_id], 0,
5902                sizeof(struct rte_eth_mirror_conf));
5903
5904         /* clear PFVMCTL register */
5905         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5906
5907         /* clear pool mask register */
5908         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5909         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5910
5911         /* clear vlan mask register */
5912         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5913         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5914
5915         return 0;
5916 }
5917
5918 static int
5919 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5920 {
5921         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5922         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5923         struct ixgbe_interrupt *intr =
5924                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5925         struct ixgbe_hw *hw =
5926                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5927         uint32_t vec = IXGBE_MISC_VEC_ID;
5928
5929         if (rte_intr_allow_others(intr_handle))
5930                 vec = IXGBE_RX_VEC_START;
5931         intr->mask |= (1 << vec);
5932         RTE_SET_USED(queue_id);
5933         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5934
5935         rte_intr_ack(intr_handle);
5936
5937         return 0;
5938 }
5939
5940 static int
5941 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5942 {
5943         struct ixgbe_interrupt *intr =
5944                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5945         struct ixgbe_hw *hw =
5946                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5947         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5948         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5949         uint32_t vec = IXGBE_MISC_VEC_ID;
5950
5951         if (rte_intr_allow_others(intr_handle))
5952                 vec = IXGBE_RX_VEC_START;
5953         intr->mask &= ~(1 << vec);
5954         RTE_SET_USED(queue_id);
5955         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5956
5957         return 0;
5958 }
5959
5960 static int
5961 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5962 {
5963         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5964         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5965         uint32_t mask;
5966         struct ixgbe_hw *hw =
5967                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5968         struct ixgbe_interrupt *intr =
5969                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5970
5971         if (queue_id < 16) {
5972                 ixgbe_disable_intr(hw);
5973                 intr->mask |= (1 << queue_id);
5974                 ixgbe_enable_intr(dev);
5975         } else if (queue_id < 32) {
5976                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5977                 mask &= (1 << queue_id);
5978                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5979         } else if (queue_id < 64) {
5980                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5981                 mask &= (1 << (queue_id - 32));
5982                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5983         }
5984         rte_intr_ack(intr_handle);
5985
5986         return 0;
5987 }
5988
5989 static int
5990 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5991 {
5992         uint32_t mask;
5993         struct ixgbe_hw *hw =
5994                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5995         struct ixgbe_interrupt *intr =
5996                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5997
5998         if (queue_id < 16) {
5999                 ixgbe_disable_intr(hw);
6000                 intr->mask &= ~(1 << queue_id);
6001                 ixgbe_enable_intr(dev);
6002         } else if (queue_id < 32) {
6003                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6004                 mask &= ~(1 << queue_id);
6005                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6006         } else if (queue_id < 64) {
6007                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6008                 mask &= ~(1 << (queue_id - 32));
6009                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6010         }
6011
6012         return 0;
6013 }
6014
6015 static void
6016 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6017                      uint8_t queue, uint8_t msix_vector)
6018 {
6019         uint32_t tmp, idx;
6020
6021         if (direction == -1) {
6022                 /* other causes */
6023                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6024                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6025                 tmp &= ~0xFF;
6026                 tmp |= msix_vector;
6027                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6028         } else {
6029                 /* rx or tx cause */
6030                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6031                 idx = ((16 * (queue & 1)) + (8 * direction));
6032                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6033                 tmp &= ~(0xFF << idx);
6034                 tmp |= (msix_vector << idx);
6035                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6036         }
6037 }
6038
6039 /**
6040  * set the IVAR registers, mapping interrupt causes to vectors
6041  * @param hw
6042  *  pointer to ixgbe_hw struct
6043  * @direction
6044  *  0 for Rx, 1 for Tx, -1 for other causes
6045  * @queue
6046  *  queue to map the corresponding interrupt to
6047  * @msix_vector
6048  *  the vector to map to the corresponding queue
6049  */
6050 static void
6051 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6052                    uint8_t queue, uint8_t msix_vector)
6053 {
6054         uint32_t tmp, idx;
6055
6056         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6057         if (hw->mac.type == ixgbe_mac_82598EB) {
6058                 if (direction == -1)
6059                         direction = 0;
6060                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6061                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6062                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6063                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6064                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6065         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6066                         (hw->mac.type == ixgbe_mac_X540) ||
6067                         (hw->mac.type == ixgbe_mac_X550) ||
6068                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6069                 if (direction == -1) {
6070                         /* other causes */
6071                         idx = ((queue & 1) * 8);
6072                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6073                         tmp &= ~(0xFF << idx);
6074                         tmp |= (msix_vector << idx);
6075                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6076                 } else {
6077                         /* rx or tx causes */
6078                         idx = ((16 * (queue & 1)) + (8 * direction));
6079                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6080                         tmp &= ~(0xFF << idx);
6081                         tmp |= (msix_vector << idx);
6082                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6083                 }
6084         }
6085 }
6086
6087 static void
6088 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6089 {
6090         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6091         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6092         struct ixgbe_hw *hw =
6093                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6094         uint32_t q_idx;
6095         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6096         uint32_t base = IXGBE_MISC_VEC_ID;
6097
6098         /* Configure VF other cause ivar */
6099         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6100
6101         /* won't configure msix register if no mapping is done
6102          * between intr vector and event fd.
6103          */
6104         if (!rte_intr_dp_is_en(intr_handle))
6105                 return;
6106
6107         if (rte_intr_allow_others(intr_handle)) {
6108                 base = IXGBE_RX_VEC_START;
6109                 vector_idx = IXGBE_RX_VEC_START;
6110         }
6111
6112         /* Configure all RX queues of VF */
6113         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6114                 /* Force all queue use vector 0,
6115                  * as IXGBE_VF_MAXMSIVECOTR = 1
6116                  */
6117                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6118                 intr_handle->intr_vec[q_idx] = vector_idx;
6119                 if (vector_idx < base + intr_handle->nb_efd - 1)
6120                         vector_idx++;
6121         }
6122
6123         /* As RX queue setting above show, all queues use the vector 0.
6124          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6125          */
6126         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6127                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6128                         | IXGBE_EITR_CNT_WDIS);
6129 }
6130
6131 /**
6132  * Sets up the hardware to properly generate MSI-X interrupts
6133  * @hw
6134  *  board private structure
6135  */
6136 static void
6137 ixgbe_configure_msix(struct rte_eth_dev *dev)
6138 {
6139         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6140         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6141         struct ixgbe_hw *hw =
6142                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6143         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6144         uint32_t vec = IXGBE_MISC_VEC_ID;
6145         uint32_t mask;
6146         uint32_t gpie;
6147
6148         /* won't configure msix register if no mapping is done
6149          * between intr vector and event fd
6150          * but if misx has been enabled already, need to configure
6151          * auto clean, auto mask and throttling.
6152          */
6153         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6154         if (!rte_intr_dp_is_en(intr_handle) &&
6155             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6156                 return;
6157
6158         if (rte_intr_allow_others(intr_handle))
6159                 vec = base = IXGBE_RX_VEC_START;
6160
6161         /* setup GPIE for MSI-x mode */
6162         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6163         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6164                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6165         /* auto clearing and auto setting corresponding bits in EIMS
6166          * when MSI-X interrupt is triggered
6167          */
6168         if (hw->mac.type == ixgbe_mac_82598EB) {
6169                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6170         } else {
6171                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6172                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6173         }
6174         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6175
6176         /* Populate the IVAR table and set the ITR values to the
6177          * corresponding register.
6178          */
6179         if (rte_intr_dp_is_en(intr_handle)) {
6180                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6181                         queue_id++) {
6182                         /* by default, 1:1 mapping */
6183                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6184                         intr_handle->intr_vec[queue_id] = vec;
6185                         if (vec < base + intr_handle->nb_efd - 1)
6186                                 vec++;
6187                 }
6188
6189                 switch (hw->mac.type) {
6190                 case ixgbe_mac_82598EB:
6191                         ixgbe_set_ivar_map(hw, -1,
6192                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6193                                            IXGBE_MISC_VEC_ID);
6194                         break;
6195                 case ixgbe_mac_82599EB:
6196                 case ixgbe_mac_X540:
6197                 case ixgbe_mac_X550:
6198                 case ixgbe_mac_X550EM_x:
6199                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6200                         break;
6201                 default:
6202                         break;
6203                 }
6204         }
6205         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6206                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6207                         | IXGBE_EITR_CNT_WDIS);
6208
6209         /* set up to autoclear timer, and the vectors */
6210         mask = IXGBE_EIMS_ENABLE_MASK;
6211         mask &= ~(IXGBE_EIMS_OTHER |
6212                   IXGBE_EIMS_MAILBOX |
6213                   IXGBE_EIMS_LSC);
6214
6215         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6216 }
6217
6218 int
6219 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6220                            uint16_t queue_idx, uint16_t tx_rate)
6221 {
6222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6223         struct rte_eth_rxmode *rxmode;
6224         uint32_t rf_dec, rf_int;
6225         uint32_t bcnrc_val;
6226         uint16_t link_speed = dev->data->dev_link.link_speed;
6227
6228         if (queue_idx >= hw->mac.max_tx_queues)
6229                 return -EINVAL;
6230
6231         if (tx_rate != 0) {
6232                 /* Calculate the rate factor values to set */
6233                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6234                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6235                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6236
6237                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6238                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6239                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6240                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6241         } else {
6242                 bcnrc_val = 0;
6243         }
6244
6245         rxmode = &dev->data->dev_conf.rxmode;
6246         /*
6247          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6248          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6249          * set as 0x4.
6250          */
6251         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6252             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6253                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6254                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6255         else
6256                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6257                         IXGBE_MMW_SIZE_DEFAULT);
6258
6259         /* Set RTTBCNRC of queue X */
6260         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6261         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6262         IXGBE_WRITE_FLUSH(hw);
6263
6264         return 0;
6265 }
6266
6267 static int
6268 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6269                      __rte_unused uint32_t index,
6270                      __rte_unused uint32_t pool)
6271 {
6272         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6273         int diag;
6274
6275         /*
6276          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6277          * operation. Trap this case to avoid exhausting the [very limited]
6278          * set of PF resources used to store VF MAC addresses.
6279          */
6280         if (memcmp(hw->mac.perm_addr, mac_addr,
6281                         sizeof(struct rte_ether_addr)) == 0)
6282                 return -1;
6283         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6284         if (diag != 0)
6285                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6286                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6287                             mac_addr->addr_bytes[0],
6288                             mac_addr->addr_bytes[1],
6289                             mac_addr->addr_bytes[2],
6290                             mac_addr->addr_bytes[3],
6291                             mac_addr->addr_bytes[4],
6292                             mac_addr->addr_bytes[5],
6293                             diag);
6294         return diag;
6295 }
6296
6297 static void
6298 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6299 {
6300         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6301         struct rte_ether_addr *perm_addr =
6302                 (struct rte_ether_addr *)hw->mac.perm_addr;
6303         struct rte_ether_addr *mac_addr;
6304         uint32_t i;
6305         int diag;
6306
6307         /*
6308          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6309          * not support the deletion of a given MAC address.
6310          * Instead, it imposes to delete all MAC addresses, then to add again
6311          * all MAC addresses with the exception of the one to be deleted.
6312          */
6313         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6314
6315         /*
6316          * Add again all MAC addresses, with the exception of the deleted one
6317          * and of the permanent MAC address.
6318          */
6319         for (i = 0, mac_addr = dev->data->mac_addrs;
6320              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6321                 /* Skip the deleted MAC address */
6322                 if (i == index)
6323                         continue;
6324                 /* Skip NULL MAC addresses */
6325                 if (rte_is_zero_ether_addr(mac_addr))
6326                         continue;
6327                 /* Skip the permanent MAC address */
6328                 if (memcmp(perm_addr, mac_addr,
6329                                 sizeof(struct rte_ether_addr)) == 0)
6330                         continue;
6331                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6332                 if (diag != 0)
6333                         PMD_DRV_LOG(ERR,
6334                                     "Adding again MAC address "
6335                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6336                                     "diag=%d",
6337                                     mac_addr->addr_bytes[0],
6338                                     mac_addr->addr_bytes[1],
6339                                     mac_addr->addr_bytes[2],
6340                                     mac_addr->addr_bytes[3],
6341                                     mac_addr->addr_bytes[4],
6342                                     mac_addr->addr_bytes[5],
6343                                     diag);
6344         }
6345 }
6346
6347 static int
6348 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6349                         struct rte_ether_addr *addr)
6350 {
6351         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6352
6353         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6354
6355         return 0;
6356 }
6357
6358 int
6359 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6360                         struct rte_eth_syn_filter *filter,
6361                         bool add)
6362 {
6363         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6364         struct ixgbe_filter_info *filter_info =
6365                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6366         uint32_t syn_info;
6367         uint32_t synqf;
6368
6369         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6370                 return -EINVAL;
6371
6372         syn_info = filter_info->syn_info;
6373
6374         if (add) {
6375                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6376                         return -EINVAL;
6377                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6378                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6379
6380                 if (filter->hig_pri)
6381                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6382                 else
6383                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6384         } else {
6385                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6386                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6387                         return -ENOENT;
6388                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6389         }
6390
6391         filter_info->syn_info = synqf;
6392         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6393         IXGBE_WRITE_FLUSH(hw);
6394         return 0;
6395 }
6396
6397
6398 static inline enum ixgbe_5tuple_protocol
6399 convert_protocol_type(uint8_t protocol_value)
6400 {
6401         if (protocol_value == IPPROTO_TCP)
6402                 return IXGBE_FILTER_PROTOCOL_TCP;
6403         else if (protocol_value == IPPROTO_UDP)
6404                 return IXGBE_FILTER_PROTOCOL_UDP;
6405         else if (protocol_value == IPPROTO_SCTP)
6406                 return IXGBE_FILTER_PROTOCOL_SCTP;
6407         else
6408                 return IXGBE_FILTER_PROTOCOL_NONE;
6409 }
6410
6411 /* inject a 5-tuple filter to HW */
6412 static inline void
6413 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6414                            struct ixgbe_5tuple_filter *filter)
6415 {
6416         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6417         int i;
6418         uint32_t ftqf, sdpqf;
6419         uint32_t l34timir = 0;
6420         uint8_t mask = 0xff;
6421
6422         i = filter->index;
6423
6424         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6425                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6426         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6427
6428         ftqf = (uint32_t)(filter->filter_info.proto &
6429                 IXGBE_FTQF_PROTOCOL_MASK);
6430         ftqf |= (uint32_t)((filter->filter_info.priority &
6431                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6432         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6433                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6434         if (filter->filter_info.dst_ip_mask == 0)
6435                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6436         if (filter->filter_info.src_port_mask == 0)
6437                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6438         if (filter->filter_info.dst_port_mask == 0)
6439                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6440         if (filter->filter_info.proto_mask == 0)
6441                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6442         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6443         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6444         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6445
6446         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6447         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6448         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6449         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6450
6451         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6452         l34timir |= (uint32_t)(filter->queue <<
6453                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6454         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6455 }
6456
6457 /*
6458  * add a 5tuple filter
6459  *
6460  * @param
6461  * dev: Pointer to struct rte_eth_dev.
6462  * index: the index the filter allocates.
6463  * filter: ponter to the filter that will be added.
6464  * rx_queue: the queue id the filter assigned to.
6465  *
6466  * @return
6467  *    - On success, zero.
6468  *    - On failure, a negative value.
6469  */
6470 static int
6471 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6472                         struct ixgbe_5tuple_filter *filter)
6473 {
6474         struct ixgbe_filter_info *filter_info =
6475                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6476         int i, idx, shift;
6477
6478         /*
6479          * look for an unused 5tuple filter index,
6480          * and insert the filter to list.
6481          */
6482         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6483                 idx = i / (sizeof(uint32_t) * NBBY);
6484                 shift = i % (sizeof(uint32_t) * NBBY);
6485                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6486                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6487                         filter->index = i;
6488                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6489                                           filter,
6490                                           entries);
6491                         break;
6492                 }
6493         }
6494         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6495                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6496                 return -ENOSYS;
6497         }
6498
6499         ixgbe_inject_5tuple_filter(dev, filter);
6500
6501         return 0;
6502 }
6503
6504 /*
6505  * remove a 5tuple filter
6506  *
6507  * @param
6508  * dev: Pointer to struct rte_eth_dev.
6509  * filter: the pointer of the filter will be removed.
6510  */
6511 static void
6512 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6513                         struct ixgbe_5tuple_filter *filter)
6514 {
6515         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6516         struct ixgbe_filter_info *filter_info =
6517                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6518         uint16_t index = filter->index;
6519
6520         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6521                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6522         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6523         rte_free(filter);
6524
6525         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6526         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6527         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6528         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6529         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6530 }
6531
6532 static int
6533 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6534 {
6535         struct ixgbe_hw *hw;
6536         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6537         struct rte_eth_dev_data *dev_data = dev->data;
6538
6539         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6540
6541         if (mtu < RTE_ETHER_MIN_MTU ||
6542                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6543                 return -EINVAL;
6544
6545         /* If device is started, refuse mtu that requires the support of
6546          * scattered packets when this feature has not been enabled before.
6547          */
6548         if (dev_data->dev_started && !dev_data->scattered_rx &&
6549             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6550              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6551                 PMD_INIT_LOG(ERR, "Stop port first.");
6552                 return -EINVAL;
6553         }
6554
6555         /*
6556          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6557          * request of the version 2.0 of the mailbox API.
6558          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6559          * of the mailbox API.
6560          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6561          * prior to 3.11.33 which contains the following change:
6562          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6563          */
6564         if (ixgbevf_rlpml_set_vf(hw, max_frame))
6565                 return -EINVAL;
6566
6567         /* update max frame size */
6568         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6569         return 0;
6570 }
6571
6572 static inline struct ixgbe_5tuple_filter *
6573 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6574                         struct ixgbe_5tuple_filter_info *key)
6575 {
6576         struct ixgbe_5tuple_filter *it;
6577
6578         TAILQ_FOREACH(it, filter_list, entries) {
6579                 if (memcmp(key, &it->filter_info,
6580                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6581                         return it;
6582                 }
6583         }
6584         return NULL;
6585 }
6586
6587 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6588 static inline int
6589 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6590                         struct ixgbe_5tuple_filter_info *filter_info)
6591 {
6592         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6593                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6594                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6595                 return -EINVAL;
6596
6597         switch (filter->dst_ip_mask) {
6598         case UINT32_MAX:
6599                 filter_info->dst_ip_mask = 0;
6600                 filter_info->dst_ip = filter->dst_ip;
6601                 break;
6602         case 0:
6603                 filter_info->dst_ip_mask = 1;
6604                 break;
6605         default:
6606                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6607                 return -EINVAL;
6608         }
6609
6610         switch (filter->src_ip_mask) {
6611         case UINT32_MAX:
6612                 filter_info->src_ip_mask = 0;
6613                 filter_info->src_ip = filter->src_ip;
6614                 break;
6615         case 0:
6616                 filter_info->src_ip_mask = 1;
6617                 break;
6618         default:
6619                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6620                 return -EINVAL;
6621         }
6622
6623         switch (filter->dst_port_mask) {
6624         case UINT16_MAX:
6625                 filter_info->dst_port_mask = 0;
6626                 filter_info->dst_port = filter->dst_port;
6627                 break;
6628         case 0:
6629                 filter_info->dst_port_mask = 1;
6630                 break;
6631         default:
6632                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6633                 return -EINVAL;
6634         }
6635
6636         switch (filter->src_port_mask) {
6637         case UINT16_MAX:
6638                 filter_info->src_port_mask = 0;
6639                 filter_info->src_port = filter->src_port;
6640                 break;
6641         case 0:
6642                 filter_info->src_port_mask = 1;
6643                 break;
6644         default:
6645                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6646                 return -EINVAL;
6647         }
6648
6649         switch (filter->proto_mask) {
6650         case UINT8_MAX:
6651                 filter_info->proto_mask = 0;
6652                 filter_info->proto =
6653                         convert_protocol_type(filter->proto);
6654                 break;
6655         case 0:
6656                 filter_info->proto_mask = 1;
6657                 break;
6658         default:
6659                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6660                 return -EINVAL;
6661         }
6662
6663         filter_info->priority = (uint8_t)filter->priority;
6664         return 0;
6665 }
6666
6667 /*
6668  * add or delete a ntuple filter
6669  *
6670  * @param
6671  * dev: Pointer to struct rte_eth_dev.
6672  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6673  * add: if true, add filter, if false, remove filter
6674  *
6675  * @return
6676  *    - On success, zero.
6677  *    - On failure, a negative value.
6678  */
6679 int
6680 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6681                         struct rte_eth_ntuple_filter *ntuple_filter,
6682                         bool add)
6683 {
6684         struct ixgbe_filter_info *filter_info =
6685                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6686         struct ixgbe_5tuple_filter_info filter_5tuple;
6687         struct ixgbe_5tuple_filter *filter;
6688         int ret;
6689
6690         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6691                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6692                 return -EINVAL;
6693         }
6694
6695         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6696         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6697         if (ret < 0)
6698                 return ret;
6699
6700         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6701                                          &filter_5tuple);
6702         if (filter != NULL && add) {
6703                 PMD_DRV_LOG(ERR, "filter exists.");
6704                 return -EEXIST;
6705         }
6706         if (filter == NULL && !add) {
6707                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6708                 return -ENOENT;
6709         }
6710
6711         if (add) {
6712                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6713                                 sizeof(struct ixgbe_5tuple_filter), 0);
6714                 if (filter == NULL)
6715                         return -ENOMEM;
6716                 rte_memcpy(&filter->filter_info,
6717                                  &filter_5tuple,
6718                                  sizeof(struct ixgbe_5tuple_filter_info));
6719                 filter->queue = ntuple_filter->queue;
6720                 ret = ixgbe_add_5tuple_filter(dev, filter);
6721                 if (ret < 0) {
6722                         rte_free(filter);
6723                         return ret;
6724                 }
6725         } else
6726                 ixgbe_remove_5tuple_filter(dev, filter);
6727
6728         return 0;
6729 }
6730
6731 int
6732 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6733                         struct rte_eth_ethertype_filter *filter,
6734                         bool add)
6735 {
6736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6737         struct ixgbe_filter_info *filter_info =
6738                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6739         uint32_t etqf = 0;
6740         uint32_t etqs = 0;
6741         int ret;
6742         struct ixgbe_ethertype_filter ethertype_filter;
6743
6744         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6745                 return -EINVAL;
6746
6747         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6748                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6749                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6750                         " ethertype filter.", filter->ether_type);
6751                 return -EINVAL;
6752         }
6753
6754         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6755                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6756                 return -EINVAL;
6757         }
6758         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6759                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6760                 return -EINVAL;
6761         }
6762
6763         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6764         if (ret >= 0 && add) {
6765                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6766                             filter->ether_type);
6767                 return -EEXIST;
6768         }
6769         if (ret < 0 && !add) {
6770                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6771                             filter->ether_type);
6772                 return -ENOENT;
6773         }
6774
6775         if (add) {
6776                 etqf = IXGBE_ETQF_FILTER_EN;
6777                 etqf |= (uint32_t)filter->ether_type;
6778                 etqs |= (uint32_t)((filter->queue <<
6779                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6780                                     IXGBE_ETQS_RX_QUEUE);
6781                 etqs |= IXGBE_ETQS_QUEUE_EN;
6782
6783                 ethertype_filter.ethertype = filter->ether_type;
6784                 ethertype_filter.etqf = etqf;
6785                 ethertype_filter.etqs = etqs;
6786                 ethertype_filter.conf = FALSE;
6787                 ret = ixgbe_ethertype_filter_insert(filter_info,
6788                                                     &ethertype_filter);
6789                 if (ret < 0) {
6790                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6791                         return -ENOSPC;
6792                 }
6793         } else {
6794                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6795                 if (ret < 0)
6796                         return -ENOSYS;
6797         }
6798         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6799         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6800         IXGBE_WRITE_FLUSH(hw);
6801
6802         return 0;
6803 }
6804
6805 static int
6806 ixgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
6807                        const struct rte_flow_ops **ops)
6808 {
6809         *ops = &ixgbe_flow_ops;
6810         return 0;
6811 }
6812
6813 static u8 *
6814 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6815                         u8 **mc_addr_ptr, u32 *vmdq)
6816 {
6817         u8 *mc_addr;
6818
6819         *vmdq = 0;
6820         mc_addr = *mc_addr_ptr;
6821         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6822         return mc_addr;
6823 }
6824
6825 static int
6826 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6827                           struct rte_ether_addr *mc_addr_set,
6828                           uint32_t nb_mc_addr)
6829 {
6830         struct ixgbe_hw *hw;
6831         u8 *mc_addr_list;
6832
6833         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6834         mc_addr_list = (u8 *)mc_addr_set;
6835         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6836                                          ixgbe_dev_addr_list_itr, TRUE);
6837 }
6838
6839 static uint64_t
6840 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6841 {
6842         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6843         uint64_t systime_cycles;
6844
6845         switch (hw->mac.type) {
6846         case ixgbe_mac_X550:
6847         case ixgbe_mac_X550EM_x:
6848         case ixgbe_mac_X550EM_a:
6849                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6850                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6851                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6852                                 * NSEC_PER_SEC;
6853                 break;
6854         default:
6855                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6856                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6857                                 << 32;
6858         }
6859
6860         return systime_cycles;
6861 }
6862
6863 static uint64_t
6864 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6865 {
6866         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6867         uint64_t rx_tstamp_cycles;
6868
6869         switch (hw->mac.type) {
6870         case ixgbe_mac_X550:
6871         case ixgbe_mac_X550EM_x:
6872         case ixgbe_mac_X550EM_a:
6873                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6874                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6875                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6876                                 * NSEC_PER_SEC;
6877                 break;
6878         default:
6879                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6880                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6881                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6882                                 << 32;
6883         }
6884
6885         return rx_tstamp_cycles;
6886 }
6887
6888 static uint64_t
6889 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6890 {
6891         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6892         uint64_t tx_tstamp_cycles;
6893
6894         switch (hw->mac.type) {
6895         case ixgbe_mac_X550:
6896         case ixgbe_mac_X550EM_x:
6897         case ixgbe_mac_X550EM_a:
6898                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6899                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6900                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6901                                 * NSEC_PER_SEC;
6902                 break;
6903         default:
6904                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6905                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6906                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6907                                 << 32;
6908         }
6909
6910         return tx_tstamp_cycles;
6911 }
6912
6913 static void
6914 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6915 {
6916         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6917         struct ixgbe_adapter *adapter = dev->data->dev_private;
6918         struct rte_eth_link link;
6919         uint32_t incval = 0;
6920         uint32_t shift = 0;
6921
6922         /* Get current link speed. */
6923         ixgbe_dev_link_update(dev, 1);
6924         rte_eth_linkstatus_get(dev, &link);
6925
6926         switch (link.link_speed) {
6927         case ETH_SPEED_NUM_100M:
6928                 incval = IXGBE_INCVAL_100;
6929                 shift = IXGBE_INCVAL_SHIFT_100;
6930                 break;
6931         case ETH_SPEED_NUM_1G:
6932                 incval = IXGBE_INCVAL_1GB;
6933                 shift = IXGBE_INCVAL_SHIFT_1GB;
6934                 break;
6935         case ETH_SPEED_NUM_10G:
6936         default:
6937                 incval = IXGBE_INCVAL_10GB;
6938                 shift = IXGBE_INCVAL_SHIFT_10GB;
6939                 break;
6940         }
6941
6942         switch (hw->mac.type) {
6943         case ixgbe_mac_X550:
6944         case ixgbe_mac_X550EM_x:
6945         case ixgbe_mac_X550EM_a:
6946                 /* Independent of link speed. */
6947                 incval = 1;
6948                 /* Cycles read will be interpreted as ns. */
6949                 shift = 0;
6950                 /* Fall-through */
6951         case ixgbe_mac_X540:
6952                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6953                 break;
6954         case ixgbe_mac_82599EB:
6955                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6956                 shift -= IXGBE_INCVAL_SHIFT_82599;
6957                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6958                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6959                 break;
6960         default:
6961                 /* Not supported. */
6962                 return;
6963         }
6964
6965         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6966         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6967         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6968
6969         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6970         adapter->systime_tc.cc_shift = shift;
6971         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6972
6973         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6974         adapter->rx_tstamp_tc.cc_shift = shift;
6975         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6976
6977         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6978         adapter->tx_tstamp_tc.cc_shift = shift;
6979         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6980 }
6981
6982 static int
6983 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6984 {
6985         struct ixgbe_adapter *adapter = dev->data->dev_private;
6986
6987         adapter->systime_tc.nsec += delta;
6988         adapter->rx_tstamp_tc.nsec += delta;
6989         adapter->tx_tstamp_tc.nsec += delta;
6990
6991         return 0;
6992 }
6993
6994 static int
6995 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6996 {
6997         uint64_t ns;
6998         struct ixgbe_adapter *adapter = dev->data->dev_private;
6999
7000         ns = rte_timespec_to_ns(ts);
7001         /* Set the timecounters to a new value. */
7002         adapter->systime_tc.nsec = ns;
7003         adapter->rx_tstamp_tc.nsec = ns;
7004         adapter->tx_tstamp_tc.nsec = ns;
7005
7006         return 0;
7007 }
7008
7009 static int
7010 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7011 {
7012         uint64_t ns, systime_cycles;
7013         struct ixgbe_adapter *adapter = dev->data->dev_private;
7014
7015         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7016         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7017         *ts = rte_ns_to_timespec(ns);
7018
7019         return 0;
7020 }
7021
7022 static int
7023 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7024 {
7025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7026         uint32_t tsync_ctl;
7027         uint32_t tsauxc;
7028
7029         /* Stop the timesync system time. */
7030         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7031         /* Reset the timesync system time value. */
7032         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7033         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7034
7035         /* Enable system time for platforms where it isn't on by default. */
7036         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7037         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7038         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7039
7040         ixgbe_start_timecounters(dev);
7041
7042         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7043         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7044                         (RTE_ETHER_TYPE_1588 |
7045                          IXGBE_ETQF_FILTER_EN |
7046                          IXGBE_ETQF_1588));
7047
7048         /* Enable timestamping of received PTP packets. */
7049         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7050         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7051         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7052
7053         /* Enable timestamping of transmitted PTP packets. */
7054         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7055         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7056         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7057
7058         IXGBE_WRITE_FLUSH(hw);
7059
7060         return 0;
7061 }
7062
7063 static int
7064 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7065 {
7066         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7067         uint32_t tsync_ctl;
7068
7069         /* Disable timestamping of transmitted PTP packets. */
7070         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7071         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7072         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7073
7074         /* Disable timestamping of received PTP packets. */
7075         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7076         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7077         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7078
7079         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7080         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7081
7082         /* Stop incrementating the System Time registers. */
7083         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7084
7085         return 0;
7086 }
7087
7088 static int
7089 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7090                                  struct timespec *timestamp,
7091                                  uint32_t flags __rte_unused)
7092 {
7093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7094         struct ixgbe_adapter *adapter = dev->data->dev_private;
7095         uint32_t tsync_rxctl;
7096         uint64_t rx_tstamp_cycles;
7097         uint64_t ns;
7098
7099         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7100         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7101                 return -EINVAL;
7102
7103         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7104         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7105         *timestamp = rte_ns_to_timespec(ns);
7106
7107         return  0;
7108 }
7109
7110 static int
7111 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7112                                  struct timespec *timestamp)
7113 {
7114         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7115         struct ixgbe_adapter *adapter = dev->data->dev_private;
7116         uint32_t tsync_txctl;
7117         uint64_t tx_tstamp_cycles;
7118         uint64_t ns;
7119
7120         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7121         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7122                 return -EINVAL;
7123
7124         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7125         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7126         *timestamp = rte_ns_to_timespec(ns);
7127
7128         return 0;
7129 }
7130
7131 static int
7132 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7133 {
7134         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7135         int count = 0;
7136         int g_ind = 0;
7137         const struct reg_info *reg_group;
7138         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7139                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7140
7141         while ((reg_group = reg_set[g_ind++]))
7142                 count += ixgbe_regs_group_count(reg_group);
7143
7144         return count;
7145 }
7146
7147 static int
7148 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7149 {
7150         int count = 0;
7151         int g_ind = 0;
7152         const struct reg_info *reg_group;
7153
7154         while ((reg_group = ixgbevf_regs[g_ind++]))
7155                 count += ixgbe_regs_group_count(reg_group);
7156
7157         return count;
7158 }
7159
7160 static int
7161 ixgbe_get_regs(struct rte_eth_dev *dev,
7162               struct rte_dev_reg_info *regs)
7163 {
7164         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7165         uint32_t *data = regs->data;
7166         int g_ind = 0;
7167         int count = 0;
7168         const struct reg_info *reg_group;
7169         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7170                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7171
7172         if (data == NULL) {
7173                 regs->length = ixgbe_get_reg_length(dev);
7174                 regs->width = sizeof(uint32_t);
7175                 return 0;
7176         }
7177
7178         /* Support only full register dump */
7179         if ((regs->length == 0) ||
7180             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7181                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7182                         hw->device_id;
7183                 while ((reg_group = reg_set[g_ind++]))
7184                         count += ixgbe_read_regs_group(dev, &data[count],
7185                                 reg_group);
7186                 return 0;
7187         }
7188
7189         return -ENOTSUP;
7190 }
7191
7192 static int
7193 ixgbevf_get_regs(struct rte_eth_dev *dev,
7194                 struct rte_dev_reg_info *regs)
7195 {
7196         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7197         uint32_t *data = regs->data;
7198         int g_ind = 0;
7199         int count = 0;
7200         const struct reg_info *reg_group;
7201
7202         if (data == NULL) {
7203                 regs->length = ixgbevf_get_reg_length(dev);
7204                 regs->width = sizeof(uint32_t);
7205                 return 0;
7206         }
7207
7208         /* Support only full register dump */
7209         if ((regs->length == 0) ||
7210             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7211                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7212                         hw->device_id;
7213                 while ((reg_group = ixgbevf_regs[g_ind++]))
7214                         count += ixgbe_read_regs_group(dev, &data[count],
7215                                                       reg_group);
7216                 return 0;
7217         }
7218
7219         return -ENOTSUP;
7220 }
7221
7222 static int
7223 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7224 {
7225         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7226
7227         /* Return unit is byte count */
7228         return hw->eeprom.word_size * 2;
7229 }
7230
7231 static int
7232 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7233                 struct rte_dev_eeprom_info *in_eeprom)
7234 {
7235         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7236         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7237         uint16_t *data = in_eeprom->data;
7238         int first, length;
7239
7240         first = in_eeprom->offset >> 1;
7241         length = in_eeprom->length >> 1;
7242         if ((first > hw->eeprom.word_size) ||
7243             ((first + length) > hw->eeprom.word_size))
7244                 return -EINVAL;
7245
7246         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7247
7248         return eeprom->ops.read_buffer(hw, first, length, data);
7249 }
7250
7251 static int
7252 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7253                 struct rte_dev_eeprom_info *in_eeprom)
7254 {
7255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7256         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7257         uint16_t *data = in_eeprom->data;
7258         int first, length;
7259
7260         first = in_eeprom->offset >> 1;
7261         length = in_eeprom->length >> 1;
7262         if ((first > hw->eeprom.word_size) ||
7263             ((first + length) > hw->eeprom.word_size))
7264                 return -EINVAL;
7265
7266         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7267
7268         return eeprom->ops.write_buffer(hw,  first, length, data);
7269 }
7270
7271 static int
7272 ixgbe_get_module_info(struct rte_eth_dev *dev,
7273                       struct rte_eth_dev_module_info *modinfo)
7274 {
7275         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7276         uint32_t status;
7277         uint8_t sff8472_rev, addr_mode;
7278         bool page_swap = false;
7279
7280         /* Check whether we support SFF-8472 or not */
7281         status = hw->phy.ops.read_i2c_eeprom(hw,
7282                                              IXGBE_SFF_SFF_8472_COMP,
7283                                              &sff8472_rev);
7284         if (status != 0)
7285                 return -EIO;
7286
7287         /* addressing mode is not supported */
7288         status = hw->phy.ops.read_i2c_eeprom(hw,
7289                                              IXGBE_SFF_SFF_8472_SWAP,
7290                                              &addr_mode);
7291         if (status != 0)
7292                 return -EIO;
7293
7294         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7295                 PMD_DRV_LOG(ERR,
7296                             "Address change required to access page 0xA2, "
7297                             "but not supported. Please report the module "
7298                             "type to the driver maintainers.");
7299                 page_swap = true;
7300         }
7301
7302         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7303                 /* We have a SFP, but it does not support SFF-8472 */
7304                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7305                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7306         } else {
7307                 /* We have a SFP which supports a revision of SFF-8472. */
7308                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7309                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7310         }
7311
7312         return 0;
7313 }
7314
7315 static int
7316 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7317                         struct rte_dev_eeprom_info *info)
7318 {
7319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7320         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7321         uint8_t databyte = 0xFF;
7322         uint8_t *data = info->data;
7323         uint32_t i = 0;
7324
7325         if (info->length == 0)
7326                 return -EINVAL;
7327
7328         for (i = info->offset; i < info->offset + info->length; i++) {
7329                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7330                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7331                 else
7332                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7333
7334                 if (status != 0)
7335                         return -EIO;
7336
7337                 data[i - info->offset] = databyte;
7338         }
7339
7340         return 0;
7341 }
7342
7343 uint16_t
7344 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7345         switch (mac_type) {
7346         case ixgbe_mac_X550:
7347         case ixgbe_mac_X550EM_x:
7348         case ixgbe_mac_X550EM_a:
7349                 return ETH_RSS_RETA_SIZE_512;
7350         case ixgbe_mac_X550_vf:
7351         case ixgbe_mac_X550EM_x_vf:
7352         case ixgbe_mac_X550EM_a_vf:
7353                 return ETH_RSS_RETA_SIZE_64;
7354         case ixgbe_mac_X540_vf:
7355         case ixgbe_mac_82599_vf:
7356                 return 0;
7357         default:
7358                 return ETH_RSS_RETA_SIZE_128;
7359         }
7360 }
7361
7362 uint32_t
7363 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7364         switch (mac_type) {
7365         case ixgbe_mac_X550:
7366         case ixgbe_mac_X550EM_x:
7367         case ixgbe_mac_X550EM_a:
7368                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7369                         return IXGBE_RETA(reta_idx >> 2);
7370                 else
7371                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7372         case ixgbe_mac_X550_vf:
7373         case ixgbe_mac_X550EM_x_vf:
7374         case ixgbe_mac_X550EM_a_vf:
7375                 return IXGBE_VFRETA(reta_idx >> 2);
7376         default:
7377                 return IXGBE_RETA(reta_idx >> 2);
7378         }
7379 }
7380
7381 uint32_t
7382 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7383         switch (mac_type) {
7384         case ixgbe_mac_X550_vf:
7385         case ixgbe_mac_X550EM_x_vf:
7386         case ixgbe_mac_X550EM_a_vf:
7387                 return IXGBE_VFMRQC;
7388         default:
7389                 return IXGBE_MRQC;
7390         }
7391 }
7392
7393 uint32_t
7394 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7395         switch (mac_type) {
7396         case ixgbe_mac_X550_vf:
7397         case ixgbe_mac_X550EM_x_vf:
7398         case ixgbe_mac_X550EM_a_vf:
7399                 return IXGBE_VFRSSRK(i);
7400         default:
7401                 return IXGBE_RSSRK(i);
7402         }
7403 }
7404
7405 bool
7406 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7407         switch (mac_type) {
7408         case ixgbe_mac_82599_vf:
7409         case ixgbe_mac_X540_vf:
7410                 return 0;
7411         default:
7412                 return 1;
7413         }
7414 }
7415
7416 static int
7417 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7418                         struct rte_eth_dcb_info *dcb_info)
7419 {
7420         struct ixgbe_dcb_config *dcb_config =
7421                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7422         struct ixgbe_dcb_tc_config *tc;
7423         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7424         uint8_t nb_tcs;
7425         uint8_t i, j;
7426
7427         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7428                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7429         else
7430                 dcb_info->nb_tcs = 1;
7431
7432         tc_queue = &dcb_info->tc_queue;
7433         nb_tcs = dcb_info->nb_tcs;
7434
7435         if (dcb_config->vt_mode) { /* vt is enabled*/
7436                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7437                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7438                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7439                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7440                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7441                         for (j = 0; j < nb_tcs; j++) {
7442                                 tc_queue->tc_rxq[0][j].base = j;
7443                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7444                                 tc_queue->tc_txq[0][j].base = j;
7445                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7446                         }
7447                 } else {
7448                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7449                                 for (j = 0; j < nb_tcs; j++) {
7450                                         tc_queue->tc_rxq[i][j].base =
7451                                                 i * nb_tcs + j;
7452                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7453                                         tc_queue->tc_txq[i][j].base =
7454                                                 i * nb_tcs + j;
7455                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7456                                 }
7457                         }
7458                 }
7459         } else { /* vt is disabled*/
7460                 struct rte_eth_dcb_rx_conf *rx_conf =
7461                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7462                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7463                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7464                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7465                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7466                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7467                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7468                         }
7469                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7470                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7471                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7472                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7473                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7474                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7475                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7476                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7477                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7478                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7479                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7480                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7481                         }
7482                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7483                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7484                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7485                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7486                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7487                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7488                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7489                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7490                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7491                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7492                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7493                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7494                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7495                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7496                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7497                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7498                 }
7499         }
7500         for (i = 0; i < dcb_info->nb_tcs; i++) {
7501                 tc = &dcb_config->tc_config[i];
7502                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7503         }
7504         return 0;
7505 }
7506
7507 /* Update e-tag ether type */
7508 static int
7509 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7510                             uint16_t ether_type)
7511 {
7512         uint32_t etag_etype;
7513
7514         if (hw->mac.type != ixgbe_mac_X550 &&
7515             hw->mac.type != ixgbe_mac_X550EM_x &&
7516             hw->mac.type != ixgbe_mac_X550EM_a) {
7517                 return -ENOTSUP;
7518         }
7519
7520         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7521         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7522         etag_etype |= ether_type;
7523         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7524         IXGBE_WRITE_FLUSH(hw);
7525
7526         return 0;
7527 }
7528
7529 /* Enable e-tag tunnel */
7530 static int
7531 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7532 {
7533         uint32_t etag_etype;
7534
7535         if (hw->mac.type != ixgbe_mac_X550 &&
7536             hw->mac.type != ixgbe_mac_X550EM_x &&
7537             hw->mac.type != ixgbe_mac_X550EM_a) {
7538                 return -ENOTSUP;
7539         }
7540
7541         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7542         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7543         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7544         IXGBE_WRITE_FLUSH(hw);
7545
7546         return 0;
7547 }
7548
7549 static int
7550 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7551                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7552 {
7553         int ret = 0;
7554         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7555         uint32_t i, rar_entries;
7556         uint32_t rar_low, rar_high;
7557
7558         if (hw->mac.type != ixgbe_mac_X550 &&
7559             hw->mac.type != ixgbe_mac_X550EM_x &&
7560             hw->mac.type != ixgbe_mac_X550EM_a) {
7561                 return -ENOTSUP;
7562         }
7563
7564         rar_entries = ixgbe_get_num_rx_addrs(hw);
7565
7566         for (i = 1; i < rar_entries; i++) {
7567                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7568                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7569                 if ((rar_high & IXGBE_RAH_AV) &&
7570                     (rar_high & IXGBE_RAH_ADTYPE) &&
7571                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7572                      l2_tunnel->tunnel_id)) {
7573                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7574                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7575
7576                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7577
7578                         return ret;
7579                 }
7580         }
7581
7582         return ret;
7583 }
7584
7585 static int
7586 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7587                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7588 {
7589         int ret = 0;
7590         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7591         uint32_t i, rar_entries;
7592         uint32_t rar_low, rar_high;
7593
7594         if (hw->mac.type != ixgbe_mac_X550 &&
7595             hw->mac.type != ixgbe_mac_X550EM_x &&
7596             hw->mac.type != ixgbe_mac_X550EM_a) {
7597                 return -ENOTSUP;
7598         }
7599
7600         /* One entry for one tunnel. Try to remove potential existing entry. */
7601         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7602
7603         rar_entries = ixgbe_get_num_rx_addrs(hw);
7604
7605         for (i = 1; i < rar_entries; i++) {
7606                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7607                 if (rar_high & IXGBE_RAH_AV) {
7608                         continue;
7609                 } else {
7610                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7611                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7612                         rar_low = l2_tunnel->tunnel_id;
7613
7614                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7615                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7616
7617                         return ret;
7618                 }
7619         }
7620
7621         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7622                      " Please remove a rule before adding a new one.");
7623         return -EINVAL;
7624 }
7625
7626 static inline struct ixgbe_l2_tn_filter *
7627 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7628                           struct ixgbe_l2_tn_key *key)
7629 {
7630         int ret;
7631
7632         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7633         if (ret < 0)
7634                 return NULL;
7635
7636         return l2_tn_info->hash_map[ret];
7637 }
7638
7639 static inline int
7640 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7641                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7642 {
7643         int ret;
7644
7645         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7646                                &l2_tn_filter->key);
7647
7648         if (ret < 0) {
7649                 PMD_DRV_LOG(ERR,
7650                             "Failed to insert L2 tunnel filter"
7651                             " to hash table %d!",
7652                             ret);
7653                 return ret;
7654         }
7655
7656         l2_tn_info->hash_map[ret] = l2_tn_filter;
7657
7658         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7659
7660         return 0;
7661 }
7662
7663 static inline int
7664 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7665                           struct ixgbe_l2_tn_key *key)
7666 {
7667         int ret;
7668         struct ixgbe_l2_tn_filter *l2_tn_filter;
7669
7670         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7671
7672         if (ret < 0) {
7673                 PMD_DRV_LOG(ERR,
7674                             "No such L2 tunnel filter to delete %d!",
7675                             ret);
7676                 return ret;
7677         }
7678
7679         l2_tn_filter = l2_tn_info->hash_map[ret];
7680         l2_tn_info->hash_map[ret] = NULL;
7681
7682         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7683         rte_free(l2_tn_filter);
7684
7685         return 0;
7686 }
7687
7688 /* Add l2 tunnel filter */
7689 int
7690 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7691                                struct ixgbe_l2_tunnel_conf *l2_tunnel,
7692                                bool restore)
7693 {
7694         int ret;
7695         struct ixgbe_l2_tn_info *l2_tn_info =
7696                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7697         struct ixgbe_l2_tn_key key;
7698         struct ixgbe_l2_tn_filter *node;
7699
7700         if (!restore) {
7701                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7702                 key.tn_id = l2_tunnel->tunnel_id;
7703
7704                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7705
7706                 if (node) {
7707                         PMD_DRV_LOG(ERR,
7708                                     "The L2 tunnel filter already exists!");
7709                         return -EINVAL;
7710                 }
7711
7712                 node = rte_zmalloc("ixgbe_l2_tn",
7713                                    sizeof(struct ixgbe_l2_tn_filter),
7714                                    0);
7715                 if (!node)
7716                         return -ENOMEM;
7717
7718                 rte_memcpy(&node->key,
7719                                  &key,
7720                                  sizeof(struct ixgbe_l2_tn_key));
7721                 node->pool = l2_tunnel->pool;
7722                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7723                 if (ret < 0) {
7724                         rte_free(node);
7725                         return ret;
7726                 }
7727         }
7728
7729         switch (l2_tunnel->l2_tunnel_type) {
7730         case RTE_L2_TUNNEL_TYPE_E_TAG:
7731                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7732                 break;
7733         default:
7734                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7735                 ret = -EINVAL;
7736                 break;
7737         }
7738
7739         if ((!restore) && (ret < 0))
7740                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7741
7742         return ret;
7743 }
7744
7745 /* Delete l2 tunnel filter */
7746 int
7747 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7748                                struct ixgbe_l2_tunnel_conf *l2_tunnel)
7749 {
7750         int ret;
7751         struct ixgbe_l2_tn_info *l2_tn_info =
7752                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7753         struct ixgbe_l2_tn_key key;
7754
7755         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7756         key.tn_id = l2_tunnel->tunnel_id;
7757         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7758         if (ret < 0)
7759                 return ret;
7760
7761         switch (l2_tunnel->l2_tunnel_type) {
7762         case RTE_L2_TUNNEL_TYPE_E_TAG:
7763                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7764                 break;
7765         default:
7766                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7767                 ret = -EINVAL;
7768                 break;
7769         }
7770
7771         return ret;
7772 }
7773
7774 static int
7775 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7776 {
7777         int ret = 0;
7778         uint32_t ctrl;
7779         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7780
7781         if (hw->mac.type != ixgbe_mac_X550 &&
7782             hw->mac.type != ixgbe_mac_X550EM_x &&
7783             hw->mac.type != ixgbe_mac_X550EM_a) {
7784                 return -ENOTSUP;
7785         }
7786
7787         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7788         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7789         if (en)
7790                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7791         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7792
7793         return ret;
7794 }
7795
7796 static int
7797 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7798                         uint16_t port)
7799 {
7800         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7801         IXGBE_WRITE_FLUSH(hw);
7802
7803         return 0;
7804 }
7805
7806 /* There's only one register for VxLAN UDP port.
7807  * So, we cannot add several ports. Will update it.
7808  */
7809 static int
7810 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7811                      uint16_t port)
7812 {
7813         if (port == 0) {
7814                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7815                 return -EINVAL;
7816         }
7817
7818         return ixgbe_update_vxlan_port(hw, port);
7819 }
7820
7821 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7822  * UDP port, it must have a value.
7823  * So, will reset it to the original value 0.
7824  */
7825 static int
7826 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7827                      uint16_t port)
7828 {
7829         uint16_t cur_port;
7830
7831         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7832
7833         if (cur_port != port) {
7834                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7835                 return -EINVAL;
7836         }
7837
7838         return ixgbe_update_vxlan_port(hw, 0);
7839 }
7840
7841 /* Add UDP tunneling port */
7842 static int
7843 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7844                               struct rte_eth_udp_tunnel *udp_tunnel)
7845 {
7846         int ret = 0;
7847         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7848
7849         if (hw->mac.type != ixgbe_mac_X550 &&
7850             hw->mac.type != ixgbe_mac_X550EM_x &&
7851             hw->mac.type != ixgbe_mac_X550EM_a) {
7852                 return -ENOTSUP;
7853         }
7854
7855         if (udp_tunnel == NULL)
7856                 return -EINVAL;
7857
7858         switch (udp_tunnel->prot_type) {
7859         case RTE_TUNNEL_TYPE_VXLAN:
7860                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7861                 break;
7862
7863         case RTE_TUNNEL_TYPE_GENEVE:
7864         case RTE_TUNNEL_TYPE_TEREDO:
7865                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7866                 ret = -EINVAL;
7867                 break;
7868
7869         default:
7870                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7871                 ret = -EINVAL;
7872                 break;
7873         }
7874
7875         return ret;
7876 }
7877
7878 /* Remove UDP tunneling port */
7879 static int
7880 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7881                               struct rte_eth_udp_tunnel *udp_tunnel)
7882 {
7883         int ret = 0;
7884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7885
7886         if (hw->mac.type != ixgbe_mac_X550 &&
7887             hw->mac.type != ixgbe_mac_X550EM_x &&
7888             hw->mac.type != ixgbe_mac_X550EM_a) {
7889                 return -ENOTSUP;
7890         }
7891
7892         if (udp_tunnel == NULL)
7893                 return -EINVAL;
7894
7895         switch (udp_tunnel->prot_type) {
7896         case RTE_TUNNEL_TYPE_VXLAN:
7897                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7898                 break;
7899         case RTE_TUNNEL_TYPE_GENEVE:
7900         case RTE_TUNNEL_TYPE_TEREDO:
7901                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7902                 ret = -EINVAL;
7903                 break;
7904         default:
7905                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7906                 ret = -EINVAL;
7907                 break;
7908         }
7909
7910         return ret;
7911 }
7912
7913 static int
7914 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
7915 {
7916         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7917         int ret;
7918
7919         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
7920         case IXGBE_SUCCESS:
7921                 ret = 0;
7922                 break;
7923         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7924                 ret = -ENOTSUP;
7925                 break;
7926         default:
7927                 ret = -EAGAIN;
7928                 break;
7929         }
7930
7931         return ret;
7932 }
7933
7934 static int
7935 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
7936 {
7937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7938         int ret;
7939
7940         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
7941         case IXGBE_SUCCESS:
7942                 ret = 0;
7943                 break;
7944         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7945                 ret = -ENOTSUP;
7946                 break;
7947         default:
7948                 ret = -EAGAIN;
7949                 break;
7950         }
7951
7952         return ret;
7953 }
7954
7955 static int
7956 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7957 {
7958         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7959         int ret;
7960         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
7961
7962         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
7963         case IXGBE_SUCCESS:
7964                 ret = 0;
7965                 break;
7966         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7967                 ret = -ENOTSUP;
7968                 break;
7969         default:
7970                 ret = -EAGAIN;
7971                 break;
7972         }
7973
7974         return ret;
7975 }
7976
7977 static int
7978 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7979 {
7980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7981         int ret;
7982
7983         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
7984         case IXGBE_SUCCESS:
7985                 ret = 0;
7986                 break;
7987         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7988                 ret = -ENOTSUP;
7989                 break;
7990         default:
7991                 ret = -EAGAIN;
7992                 break;
7993         }
7994
7995         return ret;
7996 }
7997
7998 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7999 {
8000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8001         u32 in_msg = 0;
8002
8003         /* peek the message first */
8004         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8005
8006         /* PF reset VF event */
8007         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8008                 /* dummy mbx read to ack pf */
8009                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8010                         return;
8011                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8012                                              NULL);
8013         }
8014 }
8015
8016 static int
8017 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8018 {
8019         uint32_t eicr;
8020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8021         struct ixgbe_interrupt *intr =
8022                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8023         ixgbevf_intr_disable(dev);
8024
8025         /* read-on-clear nic registers here */
8026         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8027         intr->flags = 0;
8028
8029         /* only one misc vector supported - mailbox */
8030         eicr &= IXGBE_VTEICR_MASK;
8031         if (eicr == IXGBE_MISC_VEC_ID)
8032                 intr->flags |= IXGBE_FLAG_MAILBOX;
8033
8034         return 0;
8035 }
8036
8037 static int
8038 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8039 {
8040         struct ixgbe_interrupt *intr =
8041                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8042
8043         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8044                 ixgbevf_mbx_process(dev);
8045                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8046         }
8047
8048         ixgbevf_intr_enable(dev);
8049
8050         return 0;
8051 }
8052
8053 static void
8054 ixgbevf_dev_interrupt_handler(void *param)
8055 {
8056         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8057
8058         ixgbevf_dev_interrupt_get_status(dev);
8059         ixgbevf_dev_interrupt_action(dev);
8060 }
8061
8062 /**
8063  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8064  *  @hw: pointer to hardware structure
8065  *
8066  *  Stops the transmit data path and waits for the HW to internally empty
8067  *  the Tx security block
8068  **/
8069 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8070 {
8071 #define IXGBE_MAX_SECTX_POLL 40
8072
8073         int i;
8074         int sectxreg;
8075
8076         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8077         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8078         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8079         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8080                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8081                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8082                         break;
8083                 /* Use interrupt-safe sleep just in case */
8084                 usec_delay(1000);
8085         }
8086
8087         /* For informational purposes only */
8088         if (i >= IXGBE_MAX_SECTX_POLL)
8089                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8090                          "path fully disabled.  Continuing with init.");
8091
8092         return IXGBE_SUCCESS;
8093 }
8094
8095 /**
8096  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8097  *  @hw: pointer to hardware structure
8098  *
8099  *  Enables the transmit data path.
8100  **/
8101 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8102 {
8103         uint32_t sectxreg;
8104
8105         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8106         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8107         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8108         IXGBE_WRITE_FLUSH(hw);
8109
8110         return IXGBE_SUCCESS;
8111 }
8112
8113 /* restore n-tuple filter */
8114 static inline void
8115 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8116 {
8117         struct ixgbe_filter_info *filter_info =
8118                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8119         struct ixgbe_5tuple_filter *node;
8120
8121         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8122                 ixgbe_inject_5tuple_filter(dev, node);
8123         }
8124 }
8125
8126 /* restore ethernet type filter */
8127 static inline void
8128 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8129 {
8130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8131         struct ixgbe_filter_info *filter_info =
8132                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8133         int i;
8134
8135         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8136                 if (filter_info->ethertype_mask & (1 << i)) {
8137                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8138                                         filter_info->ethertype_filters[i].etqf);
8139                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8140                                         filter_info->ethertype_filters[i].etqs);
8141                         IXGBE_WRITE_FLUSH(hw);
8142                 }
8143         }
8144 }
8145
8146 /* restore SYN filter */
8147 static inline void
8148 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8149 {
8150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8151         struct ixgbe_filter_info *filter_info =
8152                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8153         uint32_t synqf;
8154
8155         synqf = filter_info->syn_info;
8156
8157         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8158                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8159                 IXGBE_WRITE_FLUSH(hw);
8160         }
8161 }
8162
8163 /* restore L2 tunnel filter */
8164 static inline void
8165 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8166 {
8167         struct ixgbe_l2_tn_info *l2_tn_info =
8168                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8169         struct ixgbe_l2_tn_filter *node;
8170         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8171
8172         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8173                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8174                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8175                 l2_tn_conf.pool           = node->pool;
8176                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8177         }
8178 }
8179
8180 /* restore rss filter */
8181 static inline void
8182 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8183 {
8184         struct ixgbe_filter_info *filter_info =
8185                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8186
8187         if (filter_info->rss_info.conf.queue_num)
8188                 ixgbe_config_rss_filter(dev,
8189                         &filter_info->rss_info, TRUE);
8190 }
8191
8192 static int
8193 ixgbe_filter_restore(struct rte_eth_dev *dev)
8194 {
8195         ixgbe_ntuple_filter_restore(dev);
8196         ixgbe_ethertype_filter_restore(dev);
8197         ixgbe_syn_filter_restore(dev);
8198         ixgbe_fdir_filter_restore(dev);
8199         ixgbe_l2_tn_filter_restore(dev);
8200         ixgbe_rss_filter_restore(dev);
8201
8202         return 0;
8203 }
8204
8205 static void
8206 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8207 {
8208         struct ixgbe_l2_tn_info *l2_tn_info =
8209                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8211
8212         if (l2_tn_info->e_tag_en)
8213                 (void)ixgbe_e_tag_enable(hw);
8214
8215         if (l2_tn_info->e_tag_fwd_en)
8216                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8217
8218         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8219 }
8220
8221 /* remove all the n-tuple filters */
8222 void
8223 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8224 {
8225         struct ixgbe_filter_info *filter_info =
8226                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8227         struct ixgbe_5tuple_filter *p_5tuple;
8228
8229         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8230                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8231 }
8232
8233 /* remove all the ether type filters */
8234 void
8235 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8236 {
8237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8238         struct ixgbe_filter_info *filter_info =
8239                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8240         int i;
8241
8242         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8243                 if (filter_info->ethertype_mask & (1 << i) &&
8244                     !filter_info->ethertype_filters[i].conf) {
8245                         (void)ixgbe_ethertype_filter_remove(filter_info,
8246                                                             (uint8_t)i);
8247                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8248                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8249                         IXGBE_WRITE_FLUSH(hw);
8250                 }
8251         }
8252 }
8253
8254 /* remove the SYN filter */
8255 void
8256 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8257 {
8258         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8259         struct ixgbe_filter_info *filter_info =
8260                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8261
8262         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8263                 filter_info->syn_info = 0;
8264
8265                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8266                 IXGBE_WRITE_FLUSH(hw);
8267         }
8268 }
8269
8270 /* remove all the L2 tunnel filters */
8271 int
8272 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8273 {
8274         struct ixgbe_l2_tn_info *l2_tn_info =
8275                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8276         struct ixgbe_l2_tn_filter *l2_tn_filter;
8277         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8278         int ret = 0;
8279
8280         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8281                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8282                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8283                 l2_tn_conf.pool           = l2_tn_filter->pool;
8284                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8285                 if (ret < 0)
8286                         return ret;
8287         }
8288
8289         return 0;
8290 }
8291
8292 void
8293 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8294                                 struct ixgbe_macsec_setting *macsec_setting)
8295 {
8296         struct ixgbe_macsec_setting *macsec =
8297                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8298
8299         macsec->offload_en = macsec_setting->offload_en;
8300         macsec->encrypt_en = macsec_setting->encrypt_en;
8301         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8302 }
8303
8304 void
8305 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8306 {
8307         struct ixgbe_macsec_setting *macsec =
8308                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8309
8310         macsec->offload_en = 0;
8311         macsec->encrypt_en = 0;
8312         macsec->replayprotect_en = 0;
8313 }
8314
8315 void
8316 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8317                                 struct ixgbe_macsec_setting *macsec_setting)
8318 {
8319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8320         uint32_t ctrl;
8321         uint8_t en = macsec_setting->encrypt_en;
8322         uint8_t rp = macsec_setting->replayprotect_en;
8323
8324         /**
8325          * Workaround:
8326          * As no ixgbe_disable_sec_rx_path equivalent is
8327          * implemented for tx in the base code, and we are
8328          * not allowed to modify the base code in DPDK, so
8329          * just call the hand-written one directly for now.
8330          * The hardware support has been checked by
8331          * ixgbe_disable_sec_rx_path().
8332          */
8333         ixgbe_disable_sec_tx_path_generic(hw);
8334
8335         /* Enable Ethernet CRC (required by MACsec offload) */
8336         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8337         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8338         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8339
8340         /* Enable the TX and RX crypto engines */
8341         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8342         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8343         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8344
8345         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8346         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8347         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8348
8349         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8350         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8351         ctrl |= 0x3;
8352         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8353
8354         /* Enable SA lookup */
8355         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8356         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8357         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8358                      IXGBE_LSECTXCTRL_AUTH;
8359         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8360         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8361         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8362         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8363
8364         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8365         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8366         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8367         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8368         if (rp)
8369                 ctrl |= IXGBE_LSECRXCTRL_RP;
8370         else
8371                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8372         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8373
8374         /* Start the data paths */
8375         ixgbe_enable_sec_rx_path(hw);
8376         /**
8377          * Workaround:
8378          * As no ixgbe_enable_sec_rx_path equivalent is
8379          * implemented for tx in the base code, and we are
8380          * not allowed to modify the base code in DPDK, so
8381          * just call the hand-written one directly for now.
8382          */
8383         ixgbe_enable_sec_tx_path_generic(hw);
8384 }
8385
8386 void
8387 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8388 {
8389         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8390         uint32_t ctrl;
8391
8392         /**
8393          * Workaround:
8394          * As no ixgbe_disable_sec_rx_path equivalent is
8395          * implemented for tx in the base code, and we are
8396          * not allowed to modify the base code in DPDK, so
8397          * just call the hand-written one directly for now.
8398          * The hardware support has been checked by
8399          * ixgbe_disable_sec_rx_path().
8400          */
8401         ixgbe_disable_sec_tx_path_generic(hw);
8402
8403         /* Disable the TX and RX crypto engines */
8404         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8405         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8406         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8407
8408         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8409         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8410         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8411
8412         /* Disable SA lookup */
8413         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8414         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8415         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8416         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8417
8418         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8419         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8420         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8421         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8422
8423         /* Start the data paths */
8424         ixgbe_enable_sec_rx_path(hw);
8425         /**
8426          * Workaround:
8427          * As no ixgbe_enable_sec_rx_path equivalent is
8428          * implemented for tx in the base code, and we are
8429          * not allowed to modify the base code in DPDK, so
8430          * just call the hand-written one directly for now.
8431          */
8432         ixgbe_enable_sec_tx_path_generic(hw);
8433 }
8434
8435 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8436 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8437 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8438 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8439 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8440 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8441 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8442                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8443
8444 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
8445 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
8446
8447 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
8448 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
8449 #endif
8450 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
8451 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
8452 #endif
8453 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
8454 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
8455 #endif