4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define NSEC_PER_SEC 1000000000L
130 #define IXGBE_INCVAL_10GB 0x66666666
131 #define IXGBE_INCVAL_1GB 0x40000000
132 #define IXGBE_INCVAL_100 0x50000000
133 #define IXGBE_INCVAL_SHIFT_10GB 28
134 #define IXGBE_INCVAL_SHIFT_1GB 24
135 #define IXGBE_INCVAL_SHIFT_100 21
136 #define IXGBE_INCVAL_SHIFT_82599 7
137 #define IXGBE_INCPER_SHIFT_82599 24
139 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
141 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
143 #define DEFAULT_ETAG_ETYPE 0x893f
144 #define IXGBE_ETAG_ETYPE 0x00005084
145 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
146 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
147 #define IXGBE_RAH_ADTYPE 0x40000000
148 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
149 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
152 #define IXGBE_QDE_STRIP_TAG 0x00000004
154 enum ixgbevf_xcast_modes {
155 IXGBEVF_XCAST_MODE_NONE = 0,
156 IXGBEVF_XCAST_MODE_MULTI,
157 IXGBEVF_XCAST_MODE_ALLMULTI,
160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
162 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
163 static int ixgbe_dev_start(struct rte_eth_dev *dev);
164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
165 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
166 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
173 int wait_to_complete);
174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
175 struct rte_eth_stats *stats);
176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
177 struct rte_eth_xstats *xstats, unsigned n);
178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
179 struct rte_eth_xstats *xstats, unsigned n);
180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
187 struct rte_eth_dev_info *dev_info);
188 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
202 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
203 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
204 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
205 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
207 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
208 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
209 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
210 struct rte_eth_fc_conf *fc_conf);
211 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
212 struct rte_eth_fc_conf *fc_conf);
213 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
214 struct rte_eth_pfc_conf *pfc_conf);
215 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
216 struct rte_eth_rss_reta_entry64 *reta_conf,
218 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
222 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
223 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
224 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
225 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
226 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
228 static void ixgbe_dev_interrupt_delayed_handler(void *param);
229 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
230 uint32_t index, uint32_t pool);
231 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
232 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
233 struct ether_addr *mac_addr);
234 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
236 /* For Virtual Function support */
237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
239 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
240 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
243 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
244 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
245 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
246 struct rte_eth_stats *stats);
247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
249 uint16_t vlan_id, int on);
250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
251 uint16_t queue, int on);
252 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
259 uint8_t queue, uint8_t msix_vector);
260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
264 /* For Eth VMDQ APIs support */
265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
266 ether_addr* mac_addr,uint8_t on);
267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
268 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
269 uint16_t rx_mask, uint8_t on);
270 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
271 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
272 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
273 uint64_t pool_mask,uint8_t vlan_on);
274 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
275 struct rte_eth_mirror_conf *mirror_conf,
276 uint8_t rule_id, uint8_t on);
277 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
279 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
281 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
283 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
284 uint8_t queue, uint8_t msix_vector);
285 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
287 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
288 uint16_t queue_idx, uint16_t tx_rate);
289 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
290 uint16_t tx_rate, uint64_t q_msk);
292 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
293 struct ether_addr *mac_addr,
294 uint32_t index, uint32_t pool);
295 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
296 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
297 struct ether_addr *mac_addr);
298 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
299 struct rte_eth_syn_filter *filter,
301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
302 struct rte_eth_syn_filter *filter);
303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
304 enum rte_filter_op filter_op,
306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
307 struct ixgbe_5tuple_filter *filter);
308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
309 struct ixgbe_5tuple_filter *filter);
310 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
311 struct rte_eth_ntuple_filter *filter,
313 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
314 enum rte_filter_op filter_op,
316 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
317 struct rte_eth_ntuple_filter *filter);
318 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
319 struct rte_eth_ethertype_filter *filter,
321 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
322 enum rte_filter_op filter_op,
324 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
325 struct rte_eth_ethertype_filter *filter);
326 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
327 enum rte_filter_type filter_type,
328 enum rte_filter_op filter_op,
330 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
332 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
333 struct ether_addr *mc_addr_set,
334 uint32_t nb_mc_addr);
335 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
336 struct rte_eth_dcb_info *dcb_info);
338 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
339 static int ixgbe_get_regs(struct rte_eth_dev *dev,
340 struct rte_dev_reg_info *regs);
341 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
342 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
343 struct rte_dev_eeprom_info *eeprom);
344 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
345 struct rte_dev_eeprom_info *eeprom);
347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
349 struct rte_dev_reg_info *regs);
351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
354 struct timespec *timestamp,
356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
357 struct timespec *timestamp);
358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
360 struct timespec *timestamp);
361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
362 const struct timespec *timestamp);
364 static int ixgbe_dev_l2_tunnel_eth_type_conf
365 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
366 static int ixgbe_dev_l2_tunnel_offload_set
367 (struct rte_eth_dev *dev,
368 struct rte_eth_l2_tunnel_conf *l2_tunnel,
371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
372 enum rte_filter_op filter_op,
375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
376 struct rte_eth_udp_tunnel *udp_tunnel);
377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
378 struct rte_eth_udp_tunnel *udp_tunnel);
381 * Define VF Stats MACRO for Non "cleared on read" register
383 #define UPDATE_VF_STAT(reg, last, cur) \
385 uint32_t latest = IXGBE_READ_REG(hw, reg); \
386 cur += (latest - last) & UINT_MAX; \
390 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
392 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
393 u64 new_msb = IXGBE_READ_REG(hw, msb); \
394 u64 latest = ((new_msb << 32) | new_lsb); \
395 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
399 #define IXGBE_SET_HWSTRIP(h, q) do{\
400 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
401 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
402 (h)->bitmap[idx] |= 1 << bit;\
405 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
406 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
407 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
408 (h)->bitmap[idx] &= ~(1 << bit);\
411 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
412 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
413 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
414 (r) = (h)->bitmap[idx] >> bit & 1;\
418 * The set of PCI devices this driver supports
420 static const struct rte_pci_id pci_id_ixgbe_map[] = {
422 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
423 #include "rte_pci_dev_ids.h"
425 { .vendor_id = 0, /* sentinel */ },
430 * The set of PCI devices this driver supports (for 82599 VF)
432 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
434 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
435 #include "rte_pci_dev_ids.h"
436 { .vendor_id = 0, /* sentinel */ },
440 static const struct rte_eth_desc_lim rx_desc_lim = {
441 .nb_max = IXGBE_MAX_RING_DESC,
442 .nb_min = IXGBE_MIN_RING_DESC,
443 .nb_align = IXGBE_RXD_ALIGN,
446 static const struct rte_eth_desc_lim tx_desc_lim = {
447 .nb_max = IXGBE_MAX_RING_DESC,
448 .nb_min = IXGBE_MIN_RING_DESC,
449 .nb_align = IXGBE_TXD_ALIGN,
452 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
453 .dev_configure = ixgbe_dev_configure,
454 .dev_start = ixgbe_dev_start,
455 .dev_stop = ixgbe_dev_stop,
456 .dev_set_link_up = ixgbe_dev_set_link_up,
457 .dev_set_link_down = ixgbe_dev_set_link_down,
458 .dev_close = ixgbe_dev_close,
459 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
460 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
461 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
462 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
463 .link_update = ixgbe_dev_link_update,
464 .stats_get = ixgbe_dev_stats_get,
465 .xstats_get = ixgbe_dev_xstats_get,
466 .stats_reset = ixgbe_dev_stats_reset,
467 .xstats_reset = ixgbe_dev_xstats_reset,
468 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
469 .dev_infos_get = ixgbe_dev_info_get,
470 .mtu_set = ixgbe_dev_mtu_set,
471 .vlan_filter_set = ixgbe_vlan_filter_set,
472 .vlan_tpid_set = ixgbe_vlan_tpid_set,
473 .vlan_offload_set = ixgbe_vlan_offload_set,
474 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
475 .rx_queue_start = ixgbe_dev_rx_queue_start,
476 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
477 .tx_queue_start = ixgbe_dev_tx_queue_start,
478 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
479 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
480 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
481 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
482 .rx_queue_release = ixgbe_dev_rx_queue_release,
483 .rx_queue_count = ixgbe_dev_rx_queue_count,
484 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
485 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
486 .tx_queue_release = ixgbe_dev_tx_queue_release,
487 .dev_led_on = ixgbe_dev_led_on,
488 .dev_led_off = ixgbe_dev_led_off,
489 .flow_ctrl_get = ixgbe_flow_ctrl_get,
490 .flow_ctrl_set = ixgbe_flow_ctrl_set,
491 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
492 .mac_addr_add = ixgbe_add_rar,
493 .mac_addr_remove = ixgbe_remove_rar,
494 .mac_addr_set = ixgbe_set_default_mac_addr,
495 .uc_hash_table_set = ixgbe_uc_hash_table_set,
496 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
497 .mirror_rule_set = ixgbe_mirror_rule_set,
498 .mirror_rule_reset = ixgbe_mirror_rule_reset,
499 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
500 .set_vf_rx = ixgbe_set_pool_rx,
501 .set_vf_tx = ixgbe_set_pool_tx,
502 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
503 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
504 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
505 .reta_update = ixgbe_dev_rss_reta_update,
506 .reta_query = ixgbe_dev_rss_reta_query,
507 #ifdef RTE_NIC_BYPASS
508 .bypass_init = ixgbe_bypass_init,
509 .bypass_state_set = ixgbe_bypass_state_store,
510 .bypass_state_show = ixgbe_bypass_state_show,
511 .bypass_event_set = ixgbe_bypass_event_store,
512 .bypass_event_show = ixgbe_bypass_event_show,
513 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
514 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
515 .bypass_ver_show = ixgbe_bypass_ver_show,
516 .bypass_wd_reset = ixgbe_bypass_wd_reset,
517 #endif /* RTE_NIC_BYPASS */
518 .rss_hash_update = ixgbe_dev_rss_hash_update,
519 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
520 .filter_ctrl = ixgbe_dev_filter_ctrl,
521 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
522 .rxq_info_get = ixgbe_rxq_info_get,
523 .txq_info_get = ixgbe_txq_info_get,
524 .timesync_enable = ixgbe_timesync_enable,
525 .timesync_disable = ixgbe_timesync_disable,
526 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
527 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
528 .get_reg_length = ixgbe_get_reg_length,
529 .get_reg = ixgbe_get_regs,
530 .get_eeprom_length = ixgbe_get_eeprom_length,
531 .get_eeprom = ixgbe_get_eeprom,
532 .set_eeprom = ixgbe_set_eeprom,
533 .get_dcb_info = ixgbe_dev_get_dcb_info,
534 .timesync_adjust_time = ixgbe_timesync_adjust_time,
535 .timesync_read_time = ixgbe_timesync_read_time,
536 .timesync_write_time = ixgbe_timesync_write_time,
537 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
538 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
539 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
540 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
544 * dev_ops for virtual function, bare necessities for basic vf
545 * operation have been implemented
547 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
548 .dev_configure = ixgbevf_dev_configure,
549 .dev_start = ixgbevf_dev_start,
550 .dev_stop = ixgbevf_dev_stop,
551 .link_update = ixgbe_dev_link_update,
552 .stats_get = ixgbevf_dev_stats_get,
553 .xstats_get = ixgbevf_dev_xstats_get,
554 .stats_reset = ixgbevf_dev_stats_reset,
555 .xstats_reset = ixgbevf_dev_stats_reset,
556 .dev_close = ixgbevf_dev_close,
557 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
558 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
559 .dev_infos_get = ixgbevf_dev_info_get,
560 .mtu_set = ixgbevf_dev_set_mtu,
561 .vlan_filter_set = ixgbevf_vlan_filter_set,
562 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
563 .vlan_offload_set = ixgbevf_vlan_offload_set,
564 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
565 .rx_queue_release = ixgbe_dev_rx_queue_release,
566 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
567 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
568 .tx_queue_release = ixgbe_dev_tx_queue_release,
569 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
570 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
571 .mac_addr_add = ixgbevf_add_mac_addr,
572 .mac_addr_remove = ixgbevf_remove_mac_addr,
573 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
574 .rxq_info_get = ixgbe_rxq_info_get,
575 .txq_info_get = ixgbe_txq_info_get,
576 .mac_addr_set = ixgbevf_set_default_mac_addr,
577 .get_reg_length = ixgbevf_get_reg_length,
578 .get_reg = ixgbevf_get_regs,
579 .reta_update = ixgbe_dev_rss_reta_update,
580 .reta_query = ixgbe_dev_rss_reta_query,
581 .rss_hash_update = ixgbe_dev_rss_hash_update,
582 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
585 /* store statistics names and its offset in stats structure */
586 struct rte_ixgbe_xstats_name_off {
587 char name[RTE_ETH_XSTATS_NAME_SIZE];
591 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
592 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
593 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
594 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
595 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
596 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
597 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
598 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
599 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
600 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
601 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
602 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
603 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
604 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
605 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
606 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
608 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
610 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
611 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
612 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
613 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
614 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
615 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
616 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
617 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
618 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
619 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
620 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
621 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
622 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
623 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
624 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
625 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
626 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
628 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
630 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
631 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
632 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
633 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
635 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
637 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
639 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
641 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
643 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
645 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
648 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
649 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
650 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
652 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
653 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
654 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
655 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
656 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
658 {"rx_fcoe_no_direct_data_placement_ext_buff",
659 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
661 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
663 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
665 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
667 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
669 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
672 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
673 sizeof(rte_ixgbe_stats_strings[0]))
675 /* Per-queue statistics */
676 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
677 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
678 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
679 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
680 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
683 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
684 sizeof(rte_ixgbe_rxq_strings[0]))
686 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
687 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
688 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
689 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
693 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
694 sizeof(rte_ixgbe_txq_strings[0]))
696 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
697 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
700 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
701 sizeof(rte_ixgbevf_stats_strings[0]))
704 * Atomically reads the link status information from global
705 * structure rte_eth_dev.
708 * - Pointer to the structure rte_eth_dev to read from.
709 * - Pointer to the buffer to be saved with the link status.
712 * - On success, zero.
713 * - On failure, negative value.
716 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
717 struct rte_eth_link *link)
719 struct rte_eth_link *dst = link;
720 struct rte_eth_link *src = &(dev->data->dev_link);
722 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
723 *(uint64_t *)src) == 0)
730 * Atomically writes the link status information into global
731 * structure rte_eth_dev.
734 * - Pointer to the structure rte_eth_dev to read from.
735 * - Pointer to the buffer to be saved with the link status.
738 * - On success, zero.
739 * - On failure, negative value.
742 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
743 struct rte_eth_link *link)
745 struct rte_eth_link *dst = &(dev->data->dev_link);
746 struct rte_eth_link *src = link;
748 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
749 *(uint64_t *)src) == 0)
756 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
759 ixgbe_is_sfp(struct ixgbe_hw *hw)
761 switch (hw->phy.type) {
762 case ixgbe_phy_sfp_avago:
763 case ixgbe_phy_sfp_ftl:
764 case ixgbe_phy_sfp_intel:
765 case ixgbe_phy_sfp_unknown:
766 case ixgbe_phy_sfp_passive_tyco:
767 case ixgbe_phy_sfp_passive_unknown:
774 static inline int32_t
775 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
780 status = ixgbe_reset_hw(hw);
782 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
783 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
784 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
785 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
786 IXGBE_WRITE_FLUSH(hw);
792 ixgbe_enable_intr(struct rte_eth_dev *dev)
794 struct ixgbe_interrupt *intr =
795 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
796 struct ixgbe_hw *hw =
797 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
799 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
800 IXGBE_WRITE_FLUSH(hw);
804 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
807 ixgbe_disable_intr(struct ixgbe_hw *hw)
809 PMD_INIT_FUNC_TRACE();
811 if (hw->mac.type == ixgbe_mac_82598EB) {
812 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
814 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
815 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
816 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
818 IXGBE_WRITE_FLUSH(hw);
822 * This function resets queue statistics mapping registers.
823 * From Niantic datasheet, Initialization of Statistics section:
824 * "...if software requires the queue counters, the RQSMR and TQSM registers
825 * must be re-programmed following a device reset.
828 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
832 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
833 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
834 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
840 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
845 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
846 #define NB_QMAP_FIELDS_PER_QSM_REG 4
847 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
849 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
850 struct ixgbe_stat_mapping_registers *stat_mappings =
851 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
852 uint32_t qsmr_mask = 0;
853 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
857 if ((hw->mac.type != ixgbe_mac_82599EB) &&
858 (hw->mac.type != ixgbe_mac_X540) &&
859 (hw->mac.type != ixgbe_mac_X550) &&
860 (hw->mac.type != ixgbe_mac_X550EM_x) &&
861 (hw->mac.type != ixgbe_mac_X550EM_a))
864 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
865 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
868 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
869 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
870 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
873 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
875 /* Now clear any previous stat_idx set */
876 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
878 stat_mappings->tqsm[n] &= ~clearing_mask;
880 stat_mappings->rqsmr[n] &= ~clearing_mask;
882 q_map = (uint32_t)stat_idx;
883 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
884 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
886 stat_mappings->tqsm[n] |= qsmr_mask;
888 stat_mappings->rqsmr[n] |= qsmr_mask;
890 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
891 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
893 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
894 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
896 /* Now write the mapping in the appropriate register */
898 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
899 stat_mappings->rqsmr[n], n);
900 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
903 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
904 stat_mappings->tqsm[n], n);
905 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
911 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
913 struct ixgbe_stat_mapping_registers *stat_mappings =
914 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
915 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
918 /* write whatever was in stat mapping table to the NIC */
919 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
921 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
924 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
929 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
932 struct ixgbe_dcb_tc_config *tc;
933 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
935 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
936 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
937 for (i = 0; i < dcb_max_tc; i++) {
938 tc = &dcb_config->tc_config[i];
939 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
940 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
941 (uint8_t)(100/dcb_max_tc + (i & 1));
942 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
943 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
944 (uint8_t)(100/dcb_max_tc + (i & 1));
945 tc->pfc = ixgbe_dcb_pfc_disabled;
948 /* Initialize default user to priority mapping, UPx->TC0 */
949 tc = &dcb_config->tc_config[0];
950 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
951 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
952 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
953 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
954 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
956 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
957 dcb_config->pfc_mode_enable = false;
958 dcb_config->vt_mode = true;
959 dcb_config->round_robin_enable = false;
960 /* support all DCB capabilities in 82599 */
961 dcb_config->support.capabilities = 0xFF;
963 /*we only support 4 Tcs for X540, X550 */
964 if (hw->mac.type == ixgbe_mac_X540 ||
965 hw->mac.type == ixgbe_mac_X550 ||
966 hw->mac.type == ixgbe_mac_X550EM_x ||
967 hw->mac.type == ixgbe_mac_X550EM_a) {
968 dcb_config->num_tcs.pg_tcs = 4;
969 dcb_config->num_tcs.pfc_tcs = 4;
974 * Ensure that all locks are released before first NVM or PHY access
977 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
982 * Phy lock should not fail in this early stage. If this is the case,
983 * it is due to an improper exit of the application.
984 * So force the release of the faulty lock. Release of common lock
985 * is done automatically by swfw_sync function.
987 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
988 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
989 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
991 ixgbe_release_swfw_semaphore(hw, mask);
994 * These ones are more tricky since they are common to all ports; but
995 * swfw_sync retries last long enough (1s) to be almost sure that if
996 * lock can not be taken it is due to an improper lock of the
999 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1000 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1001 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1003 ixgbe_release_swfw_semaphore(hw, mask);
1007 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1008 * It returns 0 on success.
1011 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1013 struct rte_pci_device *pci_dev;
1014 struct ixgbe_hw *hw =
1015 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1016 struct ixgbe_vfta * shadow_vfta =
1017 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1018 struct ixgbe_hwstrip *hwstrip =
1019 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1020 struct ixgbe_dcb_config *dcb_config =
1021 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1022 struct ixgbe_filter_info *filter_info =
1023 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1028 PMD_INIT_FUNC_TRACE();
1030 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1031 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1032 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1035 * For secondary processes, we don't initialise any further as primary
1036 * has already done this work. Only check we don't need a different
1037 * RX and TX function.
1039 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1040 struct ixgbe_tx_queue *txq;
1041 /* TX queue function in primary, set by last queue initialized
1042 * Tx queue may not initialized by primary process */
1043 if (eth_dev->data->tx_queues) {
1044 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1045 ixgbe_set_tx_function(eth_dev, txq);
1047 /* Use default TX function if we get here */
1048 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1049 "Using default TX function.");
1052 ixgbe_set_rx_function(eth_dev);
1056 pci_dev = eth_dev->pci_dev;
1058 rte_eth_copy_pci_info(eth_dev, pci_dev);
1060 /* Vendor and Device ID need to be set before init of shared code */
1061 hw->device_id = pci_dev->id.device_id;
1062 hw->vendor_id = pci_dev->id.vendor_id;
1063 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1064 hw->allow_unsupported_sfp = 1;
1066 /* Initialize the shared code (base driver) */
1067 #ifdef RTE_NIC_BYPASS
1068 diag = ixgbe_bypass_init_shared_code(hw);
1070 diag = ixgbe_init_shared_code(hw);
1071 #endif /* RTE_NIC_BYPASS */
1073 if (diag != IXGBE_SUCCESS) {
1074 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1078 /* pick up the PCI bus settings for reporting later */
1079 ixgbe_get_bus_info(hw);
1081 /* Unlock any pending hardware semaphore */
1082 ixgbe_swfw_lock_reset(hw);
1084 /* Initialize DCB configuration*/
1085 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1086 ixgbe_dcb_init(hw,dcb_config);
1087 /* Get Hardware Flow Control setting */
1088 hw->fc.requested_mode = ixgbe_fc_full;
1089 hw->fc.current_mode = ixgbe_fc_full;
1090 hw->fc.pause_time = IXGBE_FC_PAUSE;
1091 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1092 hw->fc.low_water[i] = IXGBE_FC_LO;
1093 hw->fc.high_water[i] = IXGBE_FC_HI;
1095 hw->fc.send_xon = 1;
1097 /* Make sure we have a good EEPROM before we read from it */
1098 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1099 if (diag != IXGBE_SUCCESS) {
1100 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1104 #ifdef RTE_NIC_BYPASS
1105 diag = ixgbe_bypass_init_hw(hw);
1107 diag = ixgbe_init_hw(hw);
1108 #endif /* RTE_NIC_BYPASS */
1111 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1112 * is called too soon after the kernel driver unbinding/binding occurs.
1113 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1114 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1115 * also called. See ixgbe_identify_phy_82599(). The reason for the
1116 * failure is not known, and only occuts when virtualisation features
1117 * are disabled in the bios. A delay of 100ms was found to be enough by
1118 * trial-and-error, and is doubled to be safe.
1120 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1122 diag = ixgbe_init_hw(hw);
1125 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1126 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1127 "LOM. Please be aware there may be issues associated "
1128 "with your hardware.");
1129 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1130 "please contact your Intel or hardware representative "
1131 "who provided you with this hardware.");
1132 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1133 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1135 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1139 /* Reset the hw statistics */
1140 ixgbe_dev_stats_reset(eth_dev);
1142 /* disable interrupt */
1143 ixgbe_disable_intr(hw);
1145 /* reset mappings for queue statistics hw counters*/
1146 ixgbe_reset_qstat_mappings(hw);
1148 /* Allocate memory for storing MAC addresses */
1149 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1150 hw->mac.num_rar_entries, 0);
1151 if (eth_dev->data->mac_addrs == NULL) {
1153 "Failed to allocate %u bytes needed to store "
1155 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1158 /* Copy the permanent MAC address */
1159 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1160 ð_dev->data->mac_addrs[0]);
1162 /* Allocate memory for storing hash filter MAC addresses */
1163 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1164 IXGBE_VMDQ_NUM_UC_MAC, 0);
1165 if (eth_dev->data->hash_mac_addrs == NULL) {
1167 "Failed to allocate %d bytes needed to store MAC addresses",
1168 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1172 /* initialize the vfta */
1173 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1175 /* initialize the hw strip bitmap*/
1176 memset(hwstrip, 0, sizeof(*hwstrip));
1178 /* initialize PF if max_vfs not zero */
1179 ixgbe_pf_host_init(eth_dev);
1181 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1182 /* let hardware know driver is loaded */
1183 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1184 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1185 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1186 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1187 IXGBE_WRITE_FLUSH(hw);
1189 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1190 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1191 (int) hw->mac.type, (int) hw->phy.type,
1192 (int) hw->phy.sfp_type);
1194 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1195 (int) hw->mac.type, (int) hw->phy.type);
1197 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1198 eth_dev->data->port_id, pci_dev->id.vendor_id,
1199 pci_dev->id.device_id);
1201 rte_intr_callback_register(&pci_dev->intr_handle,
1202 ixgbe_dev_interrupt_handler,
1205 /* enable uio/vfio intr/eventfd mapping */
1206 rte_intr_enable(&pci_dev->intr_handle);
1208 /* enable support intr */
1209 ixgbe_enable_intr(eth_dev);
1211 /* initialize 5tuple filter list */
1212 TAILQ_INIT(&filter_info->fivetuple_list);
1213 memset(filter_info->fivetuple_mask, 0,
1214 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1220 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1222 struct rte_pci_device *pci_dev;
1223 struct ixgbe_hw *hw;
1225 PMD_INIT_FUNC_TRACE();
1227 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1230 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1231 pci_dev = eth_dev->pci_dev;
1233 if (hw->adapter_stopped == 0)
1234 ixgbe_dev_close(eth_dev);
1236 eth_dev->dev_ops = NULL;
1237 eth_dev->rx_pkt_burst = NULL;
1238 eth_dev->tx_pkt_burst = NULL;
1240 /* Unlock any pending hardware semaphore */
1241 ixgbe_swfw_lock_reset(hw);
1243 /* disable uio intr before callback unregister */
1244 rte_intr_disable(&(pci_dev->intr_handle));
1245 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1246 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1248 /* uninitialize PF if max_vfs not zero */
1249 ixgbe_pf_host_uninit(eth_dev);
1251 rte_free(eth_dev->data->mac_addrs);
1252 eth_dev->data->mac_addrs = NULL;
1254 rte_free(eth_dev->data->hash_mac_addrs);
1255 eth_dev->data->hash_mac_addrs = NULL;
1261 * Negotiate mailbox API version with the PF.
1262 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1263 * Then we try to negotiate starting with the most recent one.
1264 * If all negotiation attempts fail, then we will proceed with
1265 * the default one (ixgbe_mbox_api_10).
1268 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1272 /* start with highest supported, proceed down */
1273 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1280 i != RTE_DIM(sup_ver) &&
1281 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1287 generate_random_mac_addr(struct ether_addr *mac_addr)
1291 /* Set Organizationally Unique Identifier (OUI) prefix. */
1292 mac_addr->addr_bytes[0] = 0x00;
1293 mac_addr->addr_bytes[1] = 0x09;
1294 mac_addr->addr_bytes[2] = 0xC0;
1295 /* Force indication of locally assigned MAC address. */
1296 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1297 /* Generate the last 3 bytes of the MAC address with a random number. */
1298 random = rte_rand();
1299 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1303 * Virtual Function device init
1306 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1310 struct rte_pci_device *pci_dev;
1311 struct ixgbe_hw *hw =
1312 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1313 struct ixgbe_vfta * shadow_vfta =
1314 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1315 struct ixgbe_hwstrip *hwstrip =
1316 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1317 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1319 PMD_INIT_FUNC_TRACE();
1321 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1322 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1323 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1325 /* for secondary processes, we don't initialise any further as primary
1326 * has already done this work. Only check we don't need a different
1328 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1329 struct ixgbe_tx_queue *txq;
1330 /* TX queue function in primary, set by last queue initialized
1331 * Tx queue may not initialized by primary process
1333 if (eth_dev->data->tx_queues) {
1334 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1335 ixgbe_set_tx_function(eth_dev, txq);
1337 /* Use default TX function if we get here */
1338 PMD_INIT_LOG(NOTICE,
1339 "No TX queues configured yet. Using default TX function.");
1342 ixgbe_set_rx_function(eth_dev);
1347 pci_dev = eth_dev->pci_dev;
1349 rte_eth_copy_pci_info(eth_dev, pci_dev);
1351 hw->device_id = pci_dev->id.device_id;
1352 hw->vendor_id = pci_dev->id.vendor_id;
1353 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1355 /* initialize the vfta */
1356 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1358 /* initialize the hw strip bitmap*/
1359 memset(hwstrip, 0, sizeof(*hwstrip));
1361 /* Initialize the shared code (base driver) */
1362 diag = ixgbe_init_shared_code(hw);
1363 if (diag != IXGBE_SUCCESS) {
1364 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1368 /* init_mailbox_params */
1369 hw->mbx.ops.init_params(hw);
1371 /* Reset the hw statistics */
1372 ixgbevf_dev_stats_reset(eth_dev);
1374 /* Disable the interrupts for VF */
1375 ixgbevf_intr_disable(hw);
1377 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1378 diag = hw->mac.ops.reset_hw(hw);
1381 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1382 * the underlying PF driver has not assigned a MAC address to the VF.
1383 * In this case, assign a random MAC address.
1385 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1386 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1390 /* negotiate mailbox API version to use with the PF. */
1391 ixgbevf_negotiate_api(hw);
1393 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1394 ixgbevf_get_queues(hw, &tcs, &tc);
1396 /* Allocate memory for storing MAC addresses */
1397 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1398 hw->mac.num_rar_entries, 0);
1399 if (eth_dev->data->mac_addrs == NULL) {
1401 "Failed to allocate %u bytes needed to store "
1403 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1407 /* Generate a random MAC address, if none was assigned by PF. */
1408 if (is_zero_ether_addr(perm_addr)) {
1409 generate_random_mac_addr(perm_addr);
1410 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1412 rte_free(eth_dev->data->mac_addrs);
1413 eth_dev->data->mac_addrs = NULL;
1416 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1417 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1418 "%02x:%02x:%02x:%02x:%02x:%02x",
1419 perm_addr->addr_bytes[0],
1420 perm_addr->addr_bytes[1],
1421 perm_addr->addr_bytes[2],
1422 perm_addr->addr_bytes[3],
1423 perm_addr->addr_bytes[4],
1424 perm_addr->addr_bytes[5]);
1427 /* Copy the permanent MAC address */
1428 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1430 /* reset the hardware with the new settings */
1431 diag = hw->mac.ops.start_hw(hw);
1437 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1441 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1442 eth_dev->data->port_id, pci_dev->id.vendor_id,
1443 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1448 /* Virtual Function device uninit */
1451 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1453 struct ixgbe_hw *hw;
1455 PMD_INIT_FUNC_TRACE();
1457 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1460 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1462 if (hw->adapter_stopped == 0)
1463 ixgbevf_dev_close(eth_dev);
1465 eth_dev->dev_ops = NULL;
1466 eth_dev->rx_pkt_burst = NULL;
1467 eth_dev->tx_pkt_burst = NULL;
1469 /* Disable the interrupts for VF */
1470 ixgbevf_intr_disable(hw);
1472 rte_free(eth_dev->data->mac_addrs);
1473 eth_dev->data->mac_addrs = NULL;
1478 static struct eth_driver rte_ixgbe_pmd = {
1480 .name = "rte_ixgbe_pmd",
1481 .id_table = pci_id_ixgbe_map,
1482 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1483 RTE_PCI_DRV_DETACHABLE,
1485 .eth_dev_init = eth_ixgbe_dev_init,
1486 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1487 .dev_private_size = sizeof(struct ixgbe_adapter),
1491 * virtual function driver struct
1493 static struct eth_driver rte_ixgbevf_pmd = {
1495 .name = "rte_ixgbevf_pmd",
1496 .id_table = pci_id_ixgbevf_map,
1497 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1499 .eth_dev_init = eth_ixgbevf_dev_init,
1500 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1501 .dev_private_size = sizeof(struct ixgbe_adapter),
1505 * Driver initialization routine.
1506 * Invoked once at EAL init time.
1507 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1510 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1512 PMD_INIT_FUNC_TRACE();
1514 rte_eth_driver_register(&rte_ixgbe_pmd);
1519 * VF Driver initialization routine.
1520 * Invoked one at EAL init time.
1521 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1524 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1526 PMD_INIT_FUNC_TRACE();
1528 rte_eth_driver_register(&rte_ixgbevf_pmd);
1533 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1535 struct ixgbe_hw *hw =
1536 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537 struct ixgbe_vfta * shadow_vfta =
1538 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1543 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1544 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1545 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1550 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1552 /* update local VFTA copy */
1553 shadow_vfta->vfta[vid_idx] = vfta;
1559 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1562 ixgbe_vlan_hw_strip_enable(dev, queue);
1564 ixgbe_vlan_hw_strip_disable(dev, queue);
1568 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1569 enum rte_vlan_type vlan_type,
1572 struct ixgbe_hw *hw =
1573 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1576 switch (vlan_type) {
1577 case ETH_VLAN_TYPE_INNER:
1578 /* Only the high 16-bits is valid */
1579 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1583 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1591 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1593 struct ixgbe_hw *hw =
1594 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597 PMD_INIT_FUNC_TRACE();
1599 /* Filter Table Disable */
1600 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1601 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1603 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1607 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1609 struct ixgbe_hw *hw =
1610 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611 struct ixgbe_vfta * shadow_vfta =
1612 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1616 PMD_INIT_FUNC_TRACE();
1618 /* Filter Table Enable */
1619 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1620 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1621 vlnctrl |= IXGBE_VLNCTRL_VFE;
1623 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1625 /* write whatever is in local vfta copy */
1626 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1627 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1631 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1633 struct ixgbe_hwstrip *hwstrip =
1634 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1636 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1640 IXGBE_SET_HWSTRIP(hwstrip, queue);
1642 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1646 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1648 struct ixgbe_hw *hw =
1649 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1652 PMD_INIT_FUNC_TRACE();
1654 if (hw->mac.type == ixgbe_mac_82598EB) {
1655 /* No queue level support */
1656 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1660 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1661 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1662 ctrl &= ~IXGBE_RXDCTL_VME;
1663 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1665 /* record those setting for HW strip per queue */
1666 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1670 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1672 struct ixgbe_hw *hw =
1673 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1676 PMD_INIT_FUNC_TRACE();
1678 if (hw->mac.type == ixgbe_mac_82598EB) {
1679 /* No queue level supported */
1680 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1684 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1685 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1686 ctrl |= IXGBE_RXDCTL_VME;
1687 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1689 /* record those setting for HW strip per queue */
1690 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1694 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1696 struct ixgbe_hw *hw =
1697 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701 PMD_INIT_FUNC_TRACE();
1703 if (hw->mac.type == ixgbe_mac_82598EB) {
1704 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1705 ctrl &= ~IXGBE_VLNCTRL_VME;
1706 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1709 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1710 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1711 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1712 ctrl &= ~IXGBE_RXDCTL_VME;
1713 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1715 /* record those setting for HW strip per queue */
1716 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1722 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1724 struct ixgbe_hw *hw =
1725 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729 PMD_INIT_FUNC_TRACE();
1731 if (hw->mac.type == ixgbe_mac_82598EB) {
1732 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1733 ctrl |= IXGBE_VLNCTRL_VME;
1734 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1737 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1738 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1739 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1740 ctrl |= IXGBE_RXDCTL_VME;
1741 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1743 /* record those setting for HW strip per queue */
1744 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1750 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1752 struct ixgbe_hw *hw =
1753 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1756 PMD_INIT_FUNC_TRACE();
1758 /* DMATXCTRL: Geric Double VLAN Disable */
1759 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1760 ctrl &= ~IXGBE_DMATXCTL_GDV;
1761 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1763 /* CTRL_EXT: Global Double VLAN Disable */
1764 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1765 ctrl &= ~IXGBE_EXTENDED_VLAN;
1766 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1771 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1773 struct ixgbe_hw *hw =
1774 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1777 PMD_INIT_FUNC_TRACE();
1779 /* DMATXCTRL: Geric Double VLAN Enable */
1780 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1781 ctrl |= IXGBE_DMATXCTL_GDV;
1782 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1784 /* CTRL_EXT: Global Double VLAN Enable */
1785 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1786 ctrl |= IXGBE_EXTENDED_VLAN;
1787 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1789 /* Clear pooling mode of PFVTCTL. It's required by X550. */
1790 if (hw->mac.type == ixgbe_mac_X550 ||
1791 hw->mac.type == ixgbe_mac_X550EM_x) {
1792 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1793 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1794 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1798 * VET EXT field in the EXVET register = 0x8100 by default
1799 * So no need to change. Same to VT field of DMATXCTL register
1804 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1806 if (mask & ETH_VLAN_STRIP_MASK) {
1807 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1808 ixgbe_vlan_hw_strip_enable_all(dev);
1810 ixgbe_vlan_hw_strip_disable_all(dev);
1813 if (mask & ETH_VLAN_FILTER_MASK) {
1814 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1815 ixgbe_vlan_hw_filter_enable(dev);
1817 ixgbe_vlan_hw_filter_disable(dev);
1820 if (mask & ETH_VLAN_EXTEND_MASK) {
1821 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1822 ixgbe_vlan_hw_extend_enable(dev);
1824 ixgbe_vlan_hw_extend_disable(dev);
1829 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1831 struct ixgbe_hw *hw =
1832 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1834 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1835 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1836 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1840 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1845 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1848 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1854 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1855 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1861 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1863 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1864 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1865 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1867 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1868 /* check multi-queue mode */
1869 switch (dev_conf->rxmode.mq_mode) {
1870 case ETH_MQ_RX_VMDQ_DCB:
1871 case ETH_MQ_RX_VMDQ_DCB_RSS:
1872 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1873 PMD_INIT_LOG(ERR, "SRIOV active,"
1874 " unsupported mq_mode rx %d.",
1875 dev_conf->rxmode.mq_mode);
1878 case ETH_MQ_RX_VMDQ_RSS:
1879 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1880 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1881 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1882 PMD_INIT_LOG(ERR, "SRIOV is active,"
1883 " invalid queue number"
1884 " for VMDQ RSS, allowed"
1885 " value are 1, 2 or 4.");
1889 case ETH_MQ_RX_VMDQ_ONLY:
1890 case ETH_MQ_RX_NONE:
1891 /* if nothing mq mode configure, use default scheme */
1892 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1893 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1894 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1896 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1897 /* SRIOV only works in VMDq enable mode */
1898 PMD_INIT_LOG(ERR, "SRIOV is active,"
1899 " wrong mq_mode rx %d.",
1900 dev_conf->rxmode.mq_mode);
1904 switch (dev_conf->txmode.mq_mode) {
1905 case ETH_MQ_TX_VMDQ_DCB:
1906 /* DCB VMDQ in SRIOV mode, not implement yet */
1907 PMD_INIT_LOG(ERR, "SRIOV is active,"
1908 " unsupported VMDQ mq_mode tx %d.",
1909 dev_conf->txmode.mq_mode);
1911 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1912 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1916 /* check valid queue number */
1917 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1918 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1919 PMD_INIT_LOG(ERR, "SRIOV is active,"
1920 " nb_rx_q=%d nb_tx_q=%d queue number"
1921 " must be less than or equal to %d.",
1923 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1927 /* check configuration for vmdb+dcb mode */
1928 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1929 const struct rte_eth_vmdq_dcb_conf *conf;
1931 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1932 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1933 IXGBE_VMDQ_DCB_NB_QUEUES);
1936 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1937 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1938 conf->nb_queue_pools == ETH_32_POOLS)) {
1939 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1940 " nb_queue_pools must be %d or %d.",
1941 ETH_16_POOLS, ETH_32_POOLS);
1945 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1946 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1948 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1949 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1950 IXGBE_VMDQ_DCB_NB_QUEUES);
1953 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1954 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1955 conf->nb_queue_pools == ETH_32_POOLS)) {
1956 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1957 " nb_queue_pools != %d and"
1958 " nb_queue_pools != %d.",
1959 ETH_16_POOLS, ETH_32_POOLS);
1964 /* For DCB mode check our configuration before we go further */
1965 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1966 const struct rte_eth_dcb_rx_conf *conf;
1968 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1969 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1970 IXGBE_DCB_NB_QUEUES);
1973 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1974 if (!(conf->nb_tcs == ETH_4_TCS ||
1975 conf->nb_tcs == ETH_8_TCS)) {
1976 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1977 " and nb_tcs != %d.",
1978 ETH_4_TCS, ETH_8_TCS);
1983 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1984 const struct rte_eth_dcb_tx_conf *conf;
1986 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1987 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1988 IXGBE_DCB_NB_QUEUES);
1991 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1992 if (!(conf->nb_tcs == ETH_4_TCS ||
1993 conf->nb_tcs == ETH_8_TCS)) {
1994 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1995 " and nb_tcs != %d.",
1996 ETH_4_TCS, ETH_8_TCS);
2005 ixgbe_dev_configure(struct rte_eth_dev *dev)
2007 struct ixgbe_interrupt *intr =
2008 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2009 struct ixgbe_adapter *adapter =
2010 (struct ixgbe_adapter *)dev->data->dev_private;
2013 PMD_INIT_FUNC_TRACE();
2014 /* multipe queue mode checking */
2015 ret = ixgbe_check_mq_mode(dev);
2017 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2022 /* set flag to update link status after init */
2023 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2026 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2027 * allocation or vector Rx preconditions we will reset it.
2029 adapter->rx_bulk_alloc_allowed = true;
2030 adapter->rx_vec_allowed = true;
2036 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2038 struct ixgbe_hw *hw =
2039 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2040 struct ixgbe_interrupt *intr =
2041 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2044 /* only set up it on X550EM_X */
2045 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2046 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2047 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2048 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2049 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2050 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2055 * Configure device link speed and setup link.
2056 * It returns 0 on success.
2059 ixgbe_dev_start(struct rte_eth_dev *dev)
2061 struct ixgbe_hw *hw =
2062 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063 struct ixgbe_vf_info *vfinfo =
2064 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2065 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2066 uint32_t intr_vector = 0;
2067 int err, link_up = 0, negotiate = 0;
2073 PMD_INIT_FUNC_TRACE();
2075 /* IXGBE devices don't support half duplex */
2076 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2077 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2078 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2079 dev->data->dev_conf.link_duplex,
2080 dev->data->port_id);
2084 /* disable uio/vfio intr/eventfd mapping */
2085 rte_intr_disable(intr_handle);
2088 hw->adapter_stopped = 0;
2089 ixgbe_stop_adapter(hw);
2091 /* reinitialize adapter
2092 * this calls reset and start */
2093 status = ixgbe_pf_reset_hw(hw);
2096 hw->mac.ops.start_hw(hw);
2097 hw->mac.get_link_status = true;
2099 /* configure PF module if SRIOV enabled */
2100 ixgbe_pf_host_configure(dev);
2102 ixgbe_dev_phy_intr_setup(dev);
2104 /* check and configure queue intr-vector mapping */
2105 if ((rte_intr_cap_multiple(intr_handle) ||
2106 !RTE_ETH_DEV_SRIOV(dev).active) &&
2107 dev->data->dev_conf.intr_conf.rxq != 0) {
2108 intr_vector = dev->data->nb_rx_queues;
2109 if (rte_intr_efd_enable(intr_handle, intr_vector))
2113 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2114 intr_handle->intr_vec =
2115 rte_zmalloc("intr_vec",
2116 dev->data->nb_rx_queues * sizeof(int), 0);
2117 if (intr_handle->intr_vec == NULL) {
2118 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2119 " intr_vec\n", dev->data->nb_rx_queues);
2124 /* confiugre msix for sleep until rx interrupt */
2125 ixgbe_configure_msix(dev);
2127 /* initialize transmission unit */
2128 ixgbe_dev_tx_init(dev);
2130 /* This can fail when allocating mbufs for descriptor rings */
2131 err = ixgbe_dev_rx_init(dev);
2133 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2137 err = ixgbe_dev_rxtx_start(dev);
2139 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2143 /* Skip link setup if loopback mode is enabled for 82599. */
2144 if (hw->mac.type == ixgbe_mac_82599EB &&
2145 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2146 goto skip_link_setup;
2148 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2149 err = hw->mac.ops.setup_sfp(hw);
2154 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2155 /* Turn on the copper */
2156 ixgbe_set_phy_power(hw, true);
2158 /* Turn on the laser */
2159 ixgbe_enable_tx_laser(hw);
2162 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2165 dev->data->dev_link.link_status = link_up;
2167 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2171 switch(dev->data->dev_conf.link_speed) {
2172 case ETH_LINK_SPEED_AUTONEG:
2173 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2174 IXGBE_LINK_SPEED_82599_AUTONEG :
2175 IXGBE_LINK_SPEED_82598_AUTONEG;
2177 case ETH_LINK_SPEED_100:
2179 * Invalid for 82598 but error will be detected by
2180 * ixgbe_setup_link()
2182 speed = IXGBE_LINK_SPEED_100_FULL;
2184 case ETH_LINK_SPEED_1000:
2185 speed = IXGBE_LINK_SPEED_1GB_FULL;
2187 case ETH_LINK_SPEED_10000:
2188 speed = IXGBE_LINK_SPEED_10GB_FULL;
2191 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2192 dev->data->dev_conf.link_speed,
2193 dev->data->port_id);
2197 err = ixgbe_setup_link(hw, speed, link_up);
2203 if (rte_intr_allow_others(intr_handle)) {
2204 /* check if lsc interrupt is enabled */
2205 if (dev->data->dev_conf.intr_conf.lsc != 0)
2206 ixgbe_dev_lsc_interrupt_setup(dev);
2208 rte_intr_callback_unregister(intr_handle,
2209 ixgbe_dev_interrupt_handler,
2211 if (dev->data->dev_conf.intr_conf.lsc != 0)
2212 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2213 " no intr multiplex\n");
2216 /* check if rxq interrupt is enabled */
2217 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2218 rte_intr_dp_is_en(intr_handle))
2219 ixgbe_dev_rxq_interrupt_setup(dev);
2221 /* enable uio/vfio intr/eventfd mapping */
2222 rte_intr_enable(intr_handle);
2224 /* resume enabled intr since hw reset */
2225 ixgbe_enable_intr(dev);
2227 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2228 ETH_VLAN_EXTEND_MASK;
2229 ixgbe_vlan_offload_set(dev, mask);
2231 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2232 /* Enable vlan filtering for VMDq */
2233 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2236 /* Configure DCB hw */
2237 ixgbe_configure_dcb(dev);
2239 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2240 err = ixgbe_fdir_configure(dev);
2245 /* Restore vf rate limit */
2246 if (vfinfo != NULL) {
2247 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2248 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2249 if (vfinfo[vf].tx_rate[idx] != 0)
2250 ixgbe_set_vf_rate_limit(dev, vf,
2251 vfinfo[vf].tx_rate[idx],
2255 ixgbe_restore_statistics_mapping(dev);
2260 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2261 ixgbe_dev_clear_queues(dev);
2266 * Stop device: disable rx and tx functions to allow for reconfiguring.
2269 ixgbe_dev_stop(struct rte_eth_dev *dev)
2271 struct rte_eth_link link;
2272 struct ixgbe_hw *hw =
2273 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2274 struct ixgbe_vf_info *vfinfo =
2275 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2276 struct ixgbe_filter_info *filter_info =
2277 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2278 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2279 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2282 PMD_INIT_FUNC_TRACE();
2284 /* disable interrupts */
2285 ixgbe_disable_intr(hw);
2288 ixgbe_pf_reset_hw(hw);
2289 hw->adapter_stopped = 0;
2292 ixgbe_stop_adapter(hw);
2294 for (vf = 0; vfinfo != NULL &&
2295 vf < dev->pci_dev->max_vfs; vf++)
2296 vfinfo[vf].clear_to_send = false;
2298 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2299 /* Turn off the copper */
2300 ixgbe_set_phy_power(hw, false);
2302 /* Turn off the laser */
2303 ixgbe_disable_tx_laser(hw);
2306 ixgbe_dev_clear_queues(dev);
2308 /* Clear stored conf */
2309 dev->data->scattered_rx = 0;
2312 /* Clear recorded link status */
2313 memset(&link, 0, sizeof(link));
2314 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2316 /* Remove all ntuple filters of the device */
2317 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2318 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2319 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2320 TAILQ_REMOVE(&filter_info->fivetuple_list,
2324 memset(filter_info->fivetuple_mask, 0,
2325 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2327 if (!rte_intr_allow_others(intr_handle))
2328 /* resume to the default handler */
2329 rte_intr_callback_register(intr_handle,
2330 ixgbe_dev_interrupt_handler,
2333 /* Clean datapath event and queue/vec mapping */
2334 rte_intr_efd_disable(intr_handle);
2335 if (intr_handle->intr_vec != NULL) {
2336 rte_free(intr_handle->intr_vec);
2337 intr_handle->intr_vec = NULL;
2342 * Set device link up: enable tx.
2345 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2347 struct ixgbe_hw *hw =
2348 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2349 if (hw->mac.type == ixgbe_mac_82599EB) {
2350 #ifdef RTE_NIC_BYPASS
2351 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2352 /* Not suported in bypass mode */
2353 PMD_INIT_LOG(ERR, "Set link up is not supported "
2354 "by device id 0x%x", hw->device_id);
2360 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2361 /* Turn on the copper */
2362 ixgbe_set_phy_power(hw, true);
2364 /* Turn on the laser */
2365 ixgbe_enable_tx_laser(hw);
2372 * Set device link down: disable tx.
2375 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2377 struct ixgbe_hw *hw =
2378 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379 if (hw->mac.type == ixgbe_mac_82599EB) {
2380 #ifdef RTE_NIC_BYPASS
2381 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2382 /* Not suported in bypass mode */
2383 PMD_INIT_LOG(ERR, "Set link down is not supported "
2384 "by device id 0x%x", hw->device_id);
2390 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2391 /* Turn off the copper */
2392 ixgbe_set_phy_power(hw, false);
2394 /* Turn off the laser */
2395 ixgbe_disable_tx_laser(hw);
2402 * Reest and stop device.
2405 ixgbe_dev_close(struct rte_eth_dev *dev)
2407 struct ixgbe_hw *hw =
2408 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2410 PMD_INIT_FUNC_TRACE();
2412 ixgbe_pf_reset_hw(hw);
2414 ixgbe_dev_stop(dev);
2415 hw->adapter_stopped = 1;
2417 ixgbe_dev_free_queues(dev);
2419 ixgbe_disable_pcie_master(hw);
2421 /* reprogram the RAR[0] in case user changed it. */
2422 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2426 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2427 struct ixgbe_hw_stats *hw_stats,
2428 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2429 uint64_t *total_qprc, uint64_t *total_qprdc)
2431 uint32_t bprc, lxon, lxoff, total;
2432 uint32_t delta_gprc = 0;
2434 /* Workaround for RX byte count not including CRC bytes when CRC
2435 + * strip is enabled. CRC bytes are removed from counters when crc_strip
2438 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2439 IXGBE_HLREG0_RXCRCSTRP);
2441 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2442 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2443 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2444 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2446 for (i = 0; i < 8; i++) {
2448 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2449 /* global total per queue */
2450 hw_stats->mpc[i] += mp;
2451 /* Running comprehensive total for stats display */
2452 *total_missed_rx += hw_stats->mpc[i];
2453 if (hw->mac.type == ixgbe_mac_82598EB) {
2454 hw_stats->rnbc[i] +=
2455 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2456 hw_stats->pxonrxc[i] +=
2457 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2458 hw_stats->pxoffrxc[i] +=
2459 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2461 hw_stats->pxonrxc[i] +=
2462 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2463 hw_stats->pxoffrxc[i] +=
2464 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2465 hw_stats->pxon2offc[i] +=
2466 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2468 hw_stats->pxontxc[i] +=
2469 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2470 hw_stats->pxofftxc[i] +=
2471 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2473 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2474 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2475 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2476 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2478 delta_gprc += delta_qprc;
2480 hw_stats->qprc[i] += delta_qprc;
2481 hw_stats->qptc[i] += delta_qptc;
2483 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2484 hw_stats->qbrc[i] +=
2485 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2487 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2489 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2490 hw_stats->qbtc[i] +=
2491 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2493 hw_stats->qprdc[i] += delta_qprdc;
2494 *total_qprdc += hw_stats->qprdc[i];
2496 *total_qprc += hw_stats->qprc[i];
2497 *total_qbrc += hw_stats->qbrc[i];
2499 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2500 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2501 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2504 * An errata states that gprc actually counts good + missed packets:
2505 * Workaround to set gprc to summated queue packet receives
2507 hw_stats->gprc = *total_qprc;
2509 if (hw->mac.type != ixgbe_mac_82598EB) {
2510 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2511 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2512 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2513 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2514 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2515 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2516 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2517 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2519 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2520 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2521 /* 82598 only has a counter in the high register */
2522 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2523 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2524 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2526 uint64_t old_tpr = hw_stats->tpr;
2528 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2529 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2532 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2534 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2535 hw_stats->gptc += delta_gptc;
2536 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2537 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2540 * Workaround: mprc hardware is incorrectly counting
2541 * broadcasts, so for now we subtract those.
2543 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2544 hw_stats->bprc += bprc;
2545 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2546 if (hw->mac.type == ixgbe_mac_82598EB)
2547 hw_stats->mprc -= bprc;
2549 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2550 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2551 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2552 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2553 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2554 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2556 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2557 hw_stats->lxontxc += lxon;
2558 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2559 hw_stats->lxofftxc += lxoff;
2560 total = lxon + lxoff;
2562 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2563 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2564 hw_stats->gptc -= total;
2565 hw_stats->mptc -= total;
2566 hw_stats->ptc64 -= total;
2567 hw_stats->gotc -= total * ETHER_MIN_LEN;
2569 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2570 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2571 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2572 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2573 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2574 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2575 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2576 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2577 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2578 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2579 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2580 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2581 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2582 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2583 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2584 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2585 /* Only read FCOE on 82599 */
2586 if (hw->mac.type != ixgbe_mac_82598EB) {
2587 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2588 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2589 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2590 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2591 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2594 /* Flow Director Stats registers */
2595 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2596 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2600 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2603 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2605 struct ixgbe_hw *hw =
2606 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2607 struct ixgbe_hw_stats *hw_stats =
2608 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2609 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2612 total_missed_rx = 0;
2617 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2618 &total_qprc, &total_qprdc);
2623 /* Fill out the rte_eth_stats statistics structure */
2624 stats->ipackets = total_qprc;
2625 stats->ibytes = total_qbrc;
2626 stats->opackets = hw_stats->gptc;
2627 stats->obytes = hw_stats->gotc;
2629 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2630 stats->q_ipackets[i] = hw_stats->qprc[i];
2631 stats->q_opackets[i] = hw_stats->qptc[i];
2632 stats->q_ibytes[i] = hw_stats->qbrc[i];
2633 stats->q_obytes[i] = hw_stats->qbtc[i];
2634 stats->q_errors[i] = hw_stats->qprdc[i];
2638 stats->imissed = total_missed_rx;
2639 stats->ierrors = hw_stats->crcerrs +
2656 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2658 struct ixgbe_hw_stats *stats =
2659 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2661 /* HW registers are cleared on read */
2662 ixgbe_dev_stats_get(dev, NULL);
2664 /* Reset software totals */
2665 memset(stats, 0, sizeof(*stats));
2668 /* This function calculates the number of xstats based on the current config */
2670 ixgbe_xstats_calc_num(void) {
2671 return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2672 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2676 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2679 struct ixgbe_hw *hw =
2680 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681 struct ixgbe_hw_stats *hw_stats =
2682 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2683 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2684 unsigned i, stat, count = 0;
2686 count = ixgbe_xstats_calc_num();
2691 total_missed_rx = 0;
2696 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2697 &total_qprc, &total_qprdc);
2699 /* If this is a reset xstats is NULL, and we have cleared the
2700 * registers by reading them.
2705 /* Extended stats from ixgbe_hw_stats */
2707 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2708 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2709 rte_ixgbe_stats_strings[i].name);
2710 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2711 rte_ixgbe_stats_strings[i].offset);
2715 /* RX Priority Stats */
2716 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2717 for (i = 0; i < 8; i++) {
2718 snprintf(xstats[count].name, sizeof(xstats[count].name),
2719 "rx_priority%u_%s", i,
2720 rte_ixgbe_rxq_strings[stat].name);
2721 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2722 rte_ixgbe_rxq_strings[stat].offset +
2723 (sizeof(uint64_t) * i));
2728 /* TX Priority Stats */
2729 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2730 for (i = 0; i < 8; i++) {
2731 snprintf(xstats[count].name, sizeof(xstats[count].name),
2732 "tx_priority%u_%s", i,
2733 rte_ixgbe_txq_strings[stat].name);
2734 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2735 rte_ixgbe_txq_strings[stat].offset +
2736 (sizeof(uint64_t) * i));
2745 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2747 struct ixgbe_hw_stats *stats =
2748 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2750 unsigned count = ixgbe_xstats_calc_num();
2752 /* HW registers are cleared on read */
2753 ixgbe_dev_xstats_get(dev, NULL, count);
2755 /* Reset software totals */
2756 memset(stats, 0, sizeof(*stats));
2760 ixgbevf_update_stats(struct rte_eth_dev *dev)
2762 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2763 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2764 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2766 /* Good Rx packet, include VF loopback */
2767 UPDATE_VF_STAT(IXGBE_VFGPRC,
2768 hw_stats->last_vfgprc, hw_stats->vfgprc);
2770 /* Good Rx octets, include VF loopback */
2771 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2772 hw_stats->last_vfgorc, hw_stats->vfgorc);
2774 /* Good Tx packet, include VF loopback */
2775 UPDATE_VF_STAT(IXGBE_VFGPTC,
2776 hw_stats->last_vfgptc, hw_stats->vfgptc);
2778 /* Good Tx octets, include VF loopback */
2779 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2780 hw_stats->last_vfgotc, hw_stats->vfgotc);
2782 /* Rx Multicst Packet */
2783 UPDATE_VF_STAT(IXGBE_VFMPRC,
2784 hw_stats->last_vfmprc, hw_stats->vfmprc);
2788 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2791 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2792 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2795 if (n < IXGBEVF_NB_XSTATS)
2796 return IXGBEVF_NB_XSTATS;
2798 ixgbevf_update_stats(dev);
2803 /* Extended stats */
2804 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2805 snprintf(xstats[i].name, sizeof(xstats[i].name),
2806 "%s", rte_ixgbevf_stats_strings[i].name);
2807 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2808 rte_ixgbevf_stats_strings[i].offset);
2811 return IXGBEVF_NB_XSTATS;
2815 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2817 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2818 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2820 ixgbevf_update_stats(dev);
2825 stats->ipackets = hw_stats->vfgprc;
2826 stats->ibytes = hw_stats->vfgorc;
2827 stats->opackets = hw_stats->vfgptc;
2828 stats->obytes = hw_stats->vfgotc;
2829 stats->imcasts = hw_stats->vfmprc;
2830 /* stats->imcasts should be removed as imcasts is deprecated */
2834 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2836 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2837 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2839 /* Sync HW register to the last stats */
2840 ixgbevf_dev_stats_get(dev, NULL);
2842 /* reset HW current stats*/
2843 hw_stats->vfgprc = 0;
2844 hw_stats->vfgorc = 0;
2845 hw_stats->vfgptc = 0;
2846 hw_stats->vfgotc = 0;
2847 hw_stats->vfmprc = 0;
2852 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2854 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2856 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2857 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2858 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2859 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2860 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2861 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2862 dev_info->max_vfs = dev->pci_dev->max_vfs;
2863 if (hw->mac.type == ixgbe_mac_82598EB)
2864 dev_info->max_vmdq_pools = ETH_16_POOLS;
2866 dev_info->max_vmdq_pools = ETH_64_POOLS;
2867 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2868 dev_info->rx_offload_capa =
2869 DEV_RX_OFFLOAD_VLAN_STRIP |
2870 DEV_RX_OFFLOAD_IPV4_CKSUM |
2871 DEV_RX_OFFLOAD_UDP_CKSUM |
2872 DEV_RX_OFFLOAD_TCP_CKSUM;
2875 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2878 if ((hw->mac.type == ixgbe_mac_82599EB ||
2879 hw->mac.type == ixgbe_mac_X540) &&
2880 !RTE_ETH_DEV_SRIOV(dev).active)
2881 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2883 if (hw->mac.type == ixgbe_mac_X550 ||
2884 hw->mac.type == ixgbe_mac_X550EM_x)
2885 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2887 dev_info->tx_offload_capa =
2888 DEV_TX_OFFLOAD_VLAN_INSERT |
2889 DEV_TX_OFFLOAD_IPV4_CKSUM |
2890 DEV_TX_OFFLOAD_UDP_CKSUM |
2891 DEV_TX_OFFLOAD_TCP_CKSUM |
2892 DEV_TX_OFFLOAD_SCTP_CKSUM |
2893 DEV_TX_OFFLOAD_TCP_TSO;
2895 if (hw->mac.type == ixgbe_mac_X550 ||
2896 hw->mac.type == ixgbe_mac_X550EM_x)
2897 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2899 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2901 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2902 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2903 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2905 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2909 dev_info->default_txconf = (struct rte_eth_txconf) {
2911 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2912 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2913 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2915 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2916 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2917 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2918 ETH_TXQ_FLAGS_NOOFFLOADS,
2921 dev_info->rx_desc_lim = rx_desc_lim;
2922 dev_info->tx_desc_lim = tx_desc_lim;
2924 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2925 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2926 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2930 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2931 struct rte_eth_dev_info *dev_info)
2933 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2935 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2936 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2937 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2938 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2939 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2940 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2941 dev_info->max_vfs = dev->pci_dev->max_vfs;
2942 if (hw->mac.type == ixgbe_mac_82598EB)
2943 dev_info->max_vmdq_pools = ETH_16_POOLS;
2945 dev_info->max_vmdq_pools = ETH_64_POOLS;
2946 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2947 DEV_RX_OFFLOAD_IPV4_CKSUM |
2948 DEV_RX_OFFLOAD_UDP_CKSUM |
2949 DEV_RX_OFFLOAD_TCP_CKSUM;
2950 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2951 DEV_TX_OFFLOAD_IPV4_CKSUM |
2952 DEV_TX_OFFLOAD_UDP_CKSUM |
2953 DEV_TX_OFFLOAD_TCP_CKSUM |
2954 DEV_TX_OFFLOAD_SCTP_CKSUM |
2955 DEV_TX_OFFLOAD_TCP_TSO;
2957 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2959 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2960 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2961 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2963 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2967 dev_info->default_txconf = (struct rte_eth_txconf) {
2969 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2970 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2971 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2973 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2974 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2975 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2976 ETH_TXQ_FLAGS_NOOFFLOADS,
2979 dev_info->rx_desc_lim = rx_desc_lim;
2980 dev_info->tx_desc_lim = tx_desc_lim;
2983 /* return 0 means link status changed, -1 means not changed */
2985 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2987 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2988 struct rte_eth_link link, old;
2989 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2993 link.link_status = 0;
2994 link.link_speed = 0;
2995 link.link_duplex = 0;
2996 memset(&old, 0, sizeof(old));
2997 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2999 hw->mac.get_link_status = true;
3001 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3002 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3003 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3005 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3008 link.link_speed = ETH_LINK_SPEED_100;
3009 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3010 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3011 if (link.link_status == old.link_status)
3017 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3018 if (link.link_status == old.link_status)
3022 link.link_status = 1;
3023 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3025 switch (link_speed) {
3027 case IXGBE_LINK_SPEED_UNKNOWN:
3028 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3029 link.link_speed = ETH_LINK_SPEED_100;
3032 case IXGBE_LINK_SPEED_100_FULL:
3033 link.link_speed = ETH_LINK_SPEED_100;
3036 case IXGBE_LINK_SPEED_1GB_FULL:
3037 link.link_speed = ETH_LINK_SPEED_1000;
3040 case IXGBE_LINK_SPEED_10GB_FULL:
3041 link.link_speed = ETH_LINK_SPEED_10000;
3044 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3046 if (link.link_status == old.link_status)
3053 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3055 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3058 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3059 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3060 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3064 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3066 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3070 fctrl &= (~IXGBE_FCTRL_UPE);
3071 if (dev->data->all_multicast == 1)
3072 fctrl |= IXGBE_FCTRL_MPE;
3074 fctrl &= (~IXGBE_FCTRL_MPE);
3075 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3079 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3081 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3084 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3085 fctrl |= IXGBE_FCTRL_MPE;
3086 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3090 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3092 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3095 if (dev->data->promiscuous == 1)
3096 return; /* must remain in all_multicast mode */
3098 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3099 fctrl &= (~IXGBE_FCTRL_MPE);
3100 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3104 * It clears the interrupt causes and enables the interrupt.
3105 * It will be called once only during nic initialized.
3108 * Pointer to struct rte_eth_dev.
3111 * - On success, zero.
3112 * - On failure, a negative value.
3115 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3117 struct ixgbe_interrupt *intr =
3118 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3120 ixgbe_dev_link_status_print(dev);
3121 intr->mask |= IXGBE_EICR_LSC;
3127 * It clears the interrupt causes and enables the interrupt.
3128 * It will be called once only during nic initialized.
3131 * Pointer to struct rte_eth_dev.
3134 * - On success, zero.
3135 * - On failure, a negative value.
3138 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3140 struct ixgbe_interrupt *intr =
3141 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3143 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3149 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3152 * Pointer to struct rte_eth_dev.
3155 * - On success, zero.
3156 * - On failure, a negative value.
3159 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3162 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3163 struct ixgbe_interrupt *intr =
3164 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3166 /* clear all cause mask */
3167 ixgbe_disable_intr(hw);
3169 /* read-on-clear nic registers here */
3170 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3171 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3175 /* set flag for async link update */
3176 if (eicr & IXGBE_EICR_LSC)
3177 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3179 if (eicr & IXGBE_EICR_MAILBOX)
3180 intr->flags |= IXGBE_FLAG_MAILBOX;
3182 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3183 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3184 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3185 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3191 * It gets and then prints the link status.
3194 * Pointer to struct rte_eth_dev.
3197 * - On success, zero.
3198 * - On failure, a negative value.
3201 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3203 struct rte_eth_link link;
3205 memset(&link, 0, sizeof(link));
3206 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3207 if (link.link_status) {
3208 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3209 (int)(dev->data->port_id),
3210 (unsigned)link.link_speed,
3211 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3212 "full-duplex" : "half-duplex");
3214 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3215 (int)(dev->data->port_id));
3217 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3218 dev->pci_dev->addr.domain,
3219 dev->pci_dev->addr.bus,
3220 dev->pci_dev->addr.devid,
3221 dev->pci_dev->addr.function);
3225 * It executes link_update after knowing an interrupt occurred.
3228 * Pointer to struct rte_eth_dev.
3231 * - On success, zero.
3232 * - On failure, a negative value.
3235 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3237 struct ixgbe_interrupt *intr =
3238 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3240 struct rte_eth_link link;
3241 int intr_enable_delay = false;
3242 struct ixgbe_hw *hw =
3243 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3245 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3247 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3248 ixgbe_pf_mbx_process(dev);
3249 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3252 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3253 ixgbe_handle_lasi(hw);
3254 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3257 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3258 /* get the link status before link update, for predicting later */
3259 memset(&link, 0, sizeof(link));
3260 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3262 ixgbe_dev_link_update(dev, 0);
3265 if (!link.link_status)
3266 /* handle it 1 sec later, wait it being stable */
3267 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3268 /* likely to down */
3270 /* handle it 4 sec later, wait it being stable */
3271 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3273 ixgbe_dev_link_status_print(dev);
3275 intr_enable_delay = true;
3278 if (intr_enable_delay) {
3279 if (rte_eal_alarm_set(timeout * 1000,
3280 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3281 PMD_DRV_LOG(ERR, "Error setting alarm");
3283 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3284 ixgbe_enable_intr(dev);
3285 rte_intr_enable(&(dev->pci_dev->intr_handle));
3293 * Interrupt handler which shall be registered for alarm callback for delayed
3294 * handling specific interrupt to wait for the stable nic state. As the
3295 * NIC interrupt state is not stable for ixgbe after link is just down,
3296 * it needs to wait 4 seconds to get the stable status.
3299 * Pointer to interrupt handle.
3301 * The address of parameter (struct rte_eth_dev *) regsitered before.
3307 ixgbe_dev_interrupt_delayed_handler(void *param)
3309 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3310 struct ixgbe_interrupt *intr =
3311 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3312 struct ixgbe_hw *hw =
3313 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3316 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3317 if (eicr & IXGBE_EICR_MAILBOX)
3318 ixgbe_pf_mbx_process(dev);
3320 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3321 ixgbe_handle_lasi(hw);
3322 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3325 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3326 ixgbe_dev_link_update(dev, 0);
3327 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3328 ixgbe_dev_link_status_print(dev);
3329 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3332 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3333 ixgbe_enable_intr(dev);
3334 rte_intr_enable(&(dev->pci_dev->intr_handle));
3338 * Interrupt handler triggered by NIC for handling
3339 * specific interrupt.
3342 * Pointer to interrupt handle.
3344 * The address of parameter (struct rte_eth_dev *) regsitered before.
3350 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3353 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3355 ixgbe_dev_interrupt_get_status(dev);
3356 ixgbe_dev_interrupt_action(dev);
3360 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3362 struct ixgbe_hw *hw;
3364 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3365 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3369 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3371 struct ixgbe_hw *hw;
3373 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3378 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3380 struct ixgbe_hw *hw;
3386 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3388 fc_conf->pause_time = hw->fc.pause_time;
3389 fc_conf->high_water = hw->fc.high_water[0];
3390 fc_conf->low_water = hw->fc.low_water[0];
3391 fc_conf->send_xon = hw->fc.send_xon;
3392 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3395 * Return rx_pause status according to actual setting of
3398 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3399 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3405 * Return tx_pause status according to actual setting of
3408 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3409 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3414 if (rx_pause && tx_pause)
3415 fc_conf->mode = RTE_FC_FULL;
3417 fc_conf->mode = RTE_FC_RX_PAUSE;
3419 fc_conf->mode = RTE_FC_TX_PAUSE;
3421 fc_conf->mode = RTE_FC_NONE;
3427 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3429 struct ixgbe_hw *hw;
3431 uint32_t rx_buf_size;
3432 uint32_t max_high_water;
3434 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3441 PMD_INIT_FUNC_TRACE();
3443 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3445 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3448 * At least reserve one Ethernet frame for watermark
3449 * high_water/low_water in kilo bytes for ixgbe
3451 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3452 if ((fc_conf->high_water > max_high_water) ||
3453 (fc_conf->high_water < fc_conf->low_water)) {
3454 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3455 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3459 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3460 hw->fc.pause_time = fc_conf->pause_time;
3461 hw->fc.high_water[0] = fc_conf->high_water;
3462 hw->fc.low_water[0] = fc_conf->low_water;
3463 hw->fc.send_xon = fc_conf->send_xon;
3464 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3466 err = ixgbe_fc_enable(hw);
3468 /* Not negotiated is not an error case */
3469 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3471 /* check if we want to forward MAC frames - driver doesn't have native
3472 * capability to do that, so we'll write the registers ourselves */
3474 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3476 /* set or clear MFLCN.PMCF bit depending on configuration */
3477 if (fc_conf->mac_ctrl_frame_fwd != 0)
3478 mflcn |= IXGBE_MFLCN_PMCF;
3480 mflcn &= ~IXGBE_MFLCN_PMCF;
3482 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3483 IXGBE_WRITE_FLUSH(hw);
3488 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3493 * ixgbe_pfc_enable_generic - Enable flow control
3494 * @hw: pointer to hardware structure
3495 * @tc_num: traffic class number
3496 * Enable flow control according to the current settings.
3499 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3502 uint32_t mflcn_reg, fccfg_reg;
3504 uint32_t fcrtl, fcrth;
3508 /* Validate the water mark configuration */
3509 if (!hw->fc.pause_time) {
3510 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3514 /* Low water mark of zero causes XOFF floods */
3515 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3516 /* High/Low water can not be 0 */
3517 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3518 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3519 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3523 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3524 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3525 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3529 /* Negotiate the fc mode to use */
3530 ixgbe_fc_autoneg(hw);
3532 /* Disable any previous flow control settings */
3533 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3534 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3536 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3537 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3539 switch (hw->fc.current_mode) {
3542 * If the count of enabled RX Priority Flow control >1,
3543 * and the TX pause can not be disabled
3546 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3547 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3548 if (reg & IXGBE_FCRTH_FCEN)
3552 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3554 case ixgbe_fc_rx_pause:
3556 * Rx Flow control is enabled and Tx Flow control is
3557 * disabled by software override. Since there really
3558 * isn't a way to advertise that we are capable of RX
3559 * Pause ONLY, we will advertise that we support both
3560 * symmetric and asymmetric Rx PAUSE. Later, we will
3561 * disable the adapter's ability to send PAUSE frames.
3563 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3565 * If the count of enabled RX Priority Flow control >1,
3566 * and the TX pause can not be disabled
3569 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3570 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3571 if (reg & IXGBE_FCRTH_FCEN)
3575 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3577 case ixgbe_fc_tx_pause:
3579 * Tx Flow control is enabled, and Rx Flow control is
3580 * disabled by software override.
3582 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3585 /* Flow control (both Rx and Tx) is enabled by SW override. */
3586 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3587 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3590 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3591 ret_val = IXGBE_ERR_CONFIG;
3596 /* Set 802.3x based flow control settings. */
3597 mflcn_reg |= IXGBE_MFLCN_DPF;
3598 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3599 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3601 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3602 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3603 hw->fc.high_water[tc_num]) {
3604 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3605 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3606 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3608 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3610 * In order to prevent Tx hangs when the internal Tx
3611 * switch is enabled we must set the high water mark
3612 * to the maximum FCRTH value. This allows the Tx
3613 * switch to function even under heavy Rx workloads.
3615 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3617 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3619 /* Configure pause time (2 TCs per register) */
3620 reg = hw->fc.pause_time * 0x00010001;
3621 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3622 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3624 /* Configure flow control refresh threshold value */
3625 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3632 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3634 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3637 if (hw->mac.type != ixgbe_mac_82598EB) {
3638 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3644 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3647 uint32_t rx_buf_size;
3648 uint32_t max_high_water;
3650 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3651 struct ixgbe_hw *hw =
3652 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3653 struct ixgbe_dcb_config *dcb_config =
3654 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3656 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3663 PMD_INIT_FUNC_TRACE();
3665 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3666 tc_num = map[pfc_conf->priority];
3667 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3668 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3670 * At least reserve one Ethernet frame for watermark
3671 * high_water/low_water in kilo bytes for ixgbe
3673 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3674 if ((pfc_conf->fc.high_water > max_high_water) ||
3675 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3676 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3677 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3681 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3682 hw->fc.pause_time = pfc_conf->fc.pause_time;
3683 hw->fc.send_xon = pfc_conf->fc.send_xon;
3684 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3685 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3687 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3689 /* Not negotiated is not an error case */
3690 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3693 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3698 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3699 struct rte_eth_rss_reta_entry64 *reta_conf,
3704 uint16_t idx, shift;
3705 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3706 uint16_t sp_reta_size;
3709 PMD_INIT_FUNC_TRACE();
3711 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3712 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3717 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3718 if (reta_size != sp_reta_size) {
3719 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3720 "(%d) doesn't match the number hardware can supported "
3721 "(%d)\n", reta_size, sp_reta_size);
3725 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3726 idx = i / RTE_RETA_GROUP_SIZE;
3727 shift = i % RTE_RETA_GROUP_SIZE;
3728 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3732 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3733 if (mask == IXGBE_4_BIT_MASK)
3736 r = IXGBE_READ_REG(hw, reta_reg);
3737 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3738 if (mask & (0x1 << j))
3739 reta |= reta_conf[idx].reta[shift + j] <<
3742 reta |= r & (IXGBE_8_BIT_MASK <<
3745 IXGBE_WRITE_REG(hw, reta_reg, reta);
3752 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3753 struct rte_eth_rss_reta_entry64 *reta_conf,
3758 uint16_t idx, shift;
3759 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3760 uint16_t sp_reta_size;
3763 PMD_INIT_FUNC_TRACE();
3764 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3765 if (reta_size != sp_reta_size) {
3766 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3767 "(%d) doesn't match the number hardware can supported "
3768 "(%d)\n", reta_size, sp_reta_size);
3772 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3773 idx = i / RTE_RETA_GROUP_SIZE;
3774 shift = i % RTE_RETA_GROUP_SIZE;
3775 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3780 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3781 reta = IXGBE_READ_REG(hw, reta_reg);
3782 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3783 if (mask & (0x1 << j))
3784 reta_conf[idx].reta[shift + j] =
3785 ((reta >> (CHAR_BIT * j)) &
3794 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3795 uint32_t index, uint32_t pool)
3797 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3798 uint32_t enable_addr = 1;
3800 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3804 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3806 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3808 ixgbe_clear_rar(hw, index);
3812 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3814 ixgbe_remove_rar(dev, 0);
3816 ixgbe_add_rar(dev, addr, 0, 0);
3820 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3824 struct ixgbe_hw *hw;
3825 struct rte_eth_dev_info dev_info;
3826 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3828 ixgbe_dev_info_get(dev, &dev_info);
3830 /* check that mtu is within the allowed range */
3831 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3834 /* refuse mtu that requires the support of scattered packets when this
3835 * feature has not been enabled before. */
3836 if (!dev->data->scattered_rx &&
3837 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3838 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3841 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3842 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3844 /* switch to jumbo mode if needed */
3845 if (frame_size > ETHER_MAX_LEN) {
3846 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3847 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3849 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3850 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3852 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3854 /* update max frame size */
3855 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3857 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3858 maxfrs &= 0x0000FFFF;
3859 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3860 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3866 * Virtual Function operations
3869 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3871 PMD_INIT_FUNC_TRACE();
3873 /* Clear interrupt mask to stop from interrupts being generated */
3874 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3876 IXGBE_WRITE_FLUSH(hw);
3880 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3882 PMD_INIT_FUNC_TRACE();
3884 /* VF enable interrupt autoclean */
3885 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3886 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3887 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3889 IXGBE_WRITE_FLUSH(hw);
3893 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3895 struct rte_eth_conf* conf = &dev->data->dev_conf;
3896 struct ixgbe_adapter *adapter =
3897 (struct ixgbe_adapter *)dev->data->dev_private;
3899 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3900 dev->data->port_id);
3903 * VF has no ability to enable/disable HW CRC
3904 * Keep the persistent behavior the same as Host PF
3906 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3907 if (!conf->rxmode.hw_strip_crc) {
3908 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3909 conf->rxmode.hw_strip_crc = 1;
3912 if (conf->rxmode.hw_strip_crc) {
3913 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3914 conf->rxmode.hw_strip_crc = 0;
3919 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3920 * allocation or vector Rx preconditions we will reset it.
3922 adapter->rx_bulk_alloc_allowed = true;
3923 adapter->rx_vec_allowed = true;
3929 ixgbevf_dev_start(struct rte_eth_dev *dev)
3931 struct ixgbe_hw *hw =
3932 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3933 uint32_t intr_vector = 0;
3934 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3938 PMD_INIT_FUNC_TRACE();
3940 hw->mac.ops.reset_hw(hw);
3941 hw->mac.get_link_status = true;
3943 /* negotiate mailbox API version to use with the PF. */
3944 ixgbevf_negotiate_api(hw);
3946 ixgbevf_dev_tx_init(dev);
3948 /* This can fail when allocating mbufs for descriptor rings */
3949 err = ixgbevf_dev_rx_init(dev);
3951 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3952 ixgbe_dev_clear_queues(dev);
3957 ixgbevf_set_vfta_all(dev,1);
3960 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3961 ETH_VLAN_EXTEND_MASK;
3962 ixgbevf_vlan_offload_set(dev, mask);
3964 ixgbevf_dev_rxtx_start(dev);
3966 /* check and configure queue intr-vector mapping */
3967 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3968 intr_vector = dev->data->nb_rx_queues;
3969 if (rte_intr_efd_enable(intr_handle, intr_vector))
3973 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3974 intr_handle->intr_vec =
3975 rte_zmalloc("intr_vec",
3976 dev->data->nb_rx_queues * sizeof(int), 0);
3977 if (intr_handle->intr_vec == NULL) {
3978 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3979 " intr_vec\n", dev->data->nb_rx_queues);
3983 ixgbevf_configure_msix(dev);
3985 rte_intr_enable(intr_handle);
3987 /* Re-enable interrupt for VF */
3988 ixgbevf_intr_enable(hw);
3994 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3996 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3997 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3999 PMD_INIT_FUNC_TRACE();
4001 hw->adapter_stopped = 1;
4002 ixgbe_stop_adapter(hw);
4005 * Clear what we set, but we still keep shadow_vfta to
4006 * restore after device starts
4008 ixgbevf_set_vfta_all(dev,0);
4010 /* Clear stored conf */
4011 dev->data->scattered_rx = 0;
4013 ixgbe_dev_clear_queues(dev);
4015 /* Clean datapath event and queue/vec mapping */
4016 rte_intr_efd_disable(intr_handle);
4017 if (intr_handle->intr_vec != NULL) {
4018 rte_free(intr_handle->intr_vec);
4019 intr_handle->intr_vec = NULL;
4024 ixgbevf_dev_close(struct rte_eth_dev *dev)
4026 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4028 PMD_INIT_FUNC_TRACE();
4032 ixgbevf_dev_stop(dev);
4034 ixgbe_dev_free_queues(dev);
4036 /* reprogram the RAR[0] in case user changed it. */
4037 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4040 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4042 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4043 struct ixgbe_vfta * shadow_vfta =
4044 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4045 int i = 0, j = 0, vfta = 0, mask = 1;
4047 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4048 vfta = shadow_vfta->vfta[i];
4051 for (j = 0; j < 32; j++){
4053 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4062 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4064 struct ixgbe_hw *hw =
4065 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4066 struct ixgbe_vfta * shadow_vfta =
4067 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4068 uint32_t vid_idx = 0;
4069 uint32_t vid_bit = 0;
4072 PMD_INIT_FUNC_TRACE();
4074 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4075 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4077 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4080 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4081 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4083 /* Save what we set and retore it after device reset */
4085 shadow_vfta->vfta[vid_idx] |= vid_bit;
4087 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4093 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4095 struct ixgbe_hw *hw =
4096 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4099 PMD_INIT_FUNC_TRACE();
4101 if (queue >= hw->mac.max_rx_queues)
4104 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4106 ctrl |= IXGBE_RXDCTL_VME;
4108 ctrl &= ~IXGBE_RXDCTL_VME;
4109 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4111 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4115 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4117 struct ixgbe_hw *hw =
4118 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4122 /* VF function only support hw strip feature, others are not support */
4123 if (mask & ETH_VLAN_STRIP_MASK) {
4124 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4126 for (i = 0; i < hw->mac.max_rx_queues; i++)
4127 ixgbevf_vlan_strip_queue_set(dev,i,on);
4132 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4136 /* we only need to do this if VMDq is enabled */
4137 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4138 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4139 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4147 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4149 uint32_t vector = 0;
4150 switch (hw->mac.mc_filter_type) {
4151 case 0: /* use bits [47:36] of the address */
4152 vector = ((uc_addr->addr_bytes[4] >> 4) |
4153 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4155 case 1: /* use bits [46:35] of the address */
4156 vector = ((uc_addr->addr_bytes[4] >> 3) |
4157 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4159 case 2: /* use bits [45:34] of the address */
4160 vector = ((uc_addr->addr_bytes[4] >> 2) |
4161 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4163 case 3: /* use bits [43:32] of the address */
4164 vector = ((uc_addr->addr_bytes[4]) |
4165 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4167 default: /* Invalid mc_filter_type */
4171 /* vector can only be 12-bits or boundary will be exceeded */
4177 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4185 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4186 const uint32_t ixgbe_uta_bit_shift = 5;
4187 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4188 const uint32_t bit1 = 0x1;
4190 struct ixgbe_hw *hw =
4191 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4192 struct ixgbe_uta_info *uta_info =
4193 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4195 /* The UTA table only exists on 82599 hardware and newer */
4196 if (hw->mac.type < ixgbe_mac_82599EB)
4199 vector = ixgbe_uta_vector(hw,mac_addr);
4200 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4201 uta_shift = vector & ixgbe_uta_bit_mask;
4203 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4207 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4209 uta_info->uta_in_use++;
4210 reg_val |= (bit1 << uta_shift);
4211 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4213 uta_info->uta_in_use--;
4214 reg_val &= ~(bit1 << uta_shift);
4215 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4218 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4220 if (uta_info->uta_in_use > 0)
4221 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4222 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4224 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4230 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4233 struct ixgbe_hw *hw =
4234 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235 struct ixgbe_uta_info *uta_info =
4236 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4238 /* The UTA table only exists on 82599 hardware and newer */
4239 if (hw->mac.type < ixgbe_mac_82599EB)
4243 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4244 uta_info->uta_shadow[i] = ~0;
4245 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4248 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4249 uta_info->uta_shadow[i] = 0;
4250 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4258 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4260 uint32_t new_val = orig_val;
4262 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4263 new_val |= IXGBE_VMOLR_AUPE;
4264 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4265 new_val |= IXGBE_VMOLR_ROMPE;
4266 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4267 new_val |= IXGBE_VMOLR_ROPE;
4268 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4269 new_val |= IXGBE_VMOLR_BAM;
4270 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4271 new_val |= IXGBE_VMOLR_MPE;
4277 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4278 uint16_t rx_mask, uint8_t on)
4282 struct ixgbe_hw *hw =
4283 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4284 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4286 if (hw->mac.type == ixgbe_mac_82598EB) {
4287 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4288 " on 82599 hardware and newer");
4291 if (ixgbe_vmdq_mode_check(hw) < 0)
4294 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4301 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4307 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4311 const uint8_t bit1 = 0x1;
4313 struct ixgbe_hw *hw =
4314 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4316 if (ixgbe_vmdq_mode_check(hw) < 0)
4319 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4320 reg = IXGBE_READ_REG(hw, addr);
4328 IXGBE_WRITE_REG(hw, addr,reg);
4334 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4338 const uint8_t bit1 = 0x1;
4340 struct ixgbe_hw *hw =
4341 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4343 if (ixgbe_vmdq_mode_check(hw) < 0)
4346 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4347 reg = IXGBE_READ_REG(hw, addr);
4355 IXGBE_WRITE_REG(hw, addr,reg);
4361 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4362 uint64_t pool_mask, uint8_t vlan_on)
4366 struct ixgbe_hw *hw =
4367 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4369 if (ixgbe_vmdq_mode_check(hw) < 0)
4371 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4372 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4373 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4381 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4382 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4383 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4384 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4385 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4386 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4387 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4390 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4391 struct rte_eth_mirror_conf *mirror_conf,
4392 uint8_t rule_id, uint8_t on)
4394 uint32_t mr_ctl,vlvf;
4395 uint32_t mp_lsb = 0;
4396 uint32_t mv_msb = 0;
4397 uint32_t mv_lsb = 0;
4398 uint32_t mp_msb = 0;
4401 uint64_t vlan_mask = 0;
4403 const uint8_t pool_mask_offset = 32;
4404 const uint8_t vlan_mask_offset = 32;
4405 const uint8_t dst_pool_offset = 8;
4406 const uint8_t rule_mr_offset = 4;
4407 const uint8_t mirror_rule_mask= 0x0F;
4409 struct ixgbe_mirror_info *mr_info =
4410 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4411 struct ixgbe_hw *hw =
4412 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4413 uint8_t mirror_type = 0;
4415 if (ixgbe_vmdq_mode_check(hw) < 0)
4418 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4421 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4422 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4423 mirror_conf->rule_type);
4427 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4428 mirror_type |= IXGBE_MRCTL_VLME;
4429 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4430 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4431 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4432 /* search vlan id related pool vlan filter index */
4433 reg_index = ixgbe_find_vlvf_slot(hw,
4434 mirror_conf->vlan.vlan_id[i]);
4437 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4438 if ((vlvf & IXGBE_VLVF_VIEN) &&
4439 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4440 mirror_conf->vlan.vlan_id[i]))
4441 vlan_mask |= (1ULL << reg_index);
4448 mv_lsb = vlan_mask & 0xFFFFFFFF;
4449 mv_msb = vlan_mask >> vlan_mask_offset;
4451 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4452 mirror_conf->vlan.vlan_mask;
4453 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4454 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4455 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4456 mirror_conf->vlan.vlan_id[i];
4461 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4462 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4463 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4468 * if enable pool mirror, write related pool mask register,if disable
4469 * pool mirror, clear PFMRVM register
4471 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4472 mirror_type |= IXGBE_MRCTL_VPME;
4474 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4475 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4476 mr_info->mr_conf[rule_id].pool_mask =
4477 mirror_conf->pool_mask;
4482 mr_info->mr_conf[rule_id].pool_mask = 0;
4485 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4486 mirror_type |= IXGBE_MRCTL_UPME;
4487 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4488 mirror_type |= IXGBE_MRCTL_DPME;
4490 /* read mirror control register and recalculate it */
4491 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4494 mr_ctl |= mirror_type;
4495 mr_ctl &= mirror_rule_mask;
4496 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4498 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4500 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4501 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4503 /* write mirrror control register */
4504 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4506 /* write pool mirrror control register */
4507 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4508 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4509 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4512 /* write VLAN mirrror control register */
4513 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4514 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4515 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4523 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4526 uint32_t lsb_val = 0;
4527 uint32_t msb_val = 0;
4528 const uint8_t rule_mr_offset = 4;
4530 struct ixgbe_hw *hw =
4531 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4532 struct ixgbe_mirror_info *mr_info =
4533 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4535 if (ixgbe_vmdq_mode_check(hw) < 0)
4538 memset(&mr_info->mr_conf[rule_id], 0,
4539 sizeof(struct rte_eth_mirror_conf));
4541 /* clear PFVMCTL register */
4542 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4544 /* clear pool mask register */
4545 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4546 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4548 /* clear vlan mask register */
4549 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4550 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4556 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4559 struct ixgbe_hw *hw =
4560 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4562 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4563 mask |= (1 << IXGBE_MISC_VEC_ID);
4564 RTE_SET_USED(queue_id);
4565 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4567 rte_intr_enable(&dev->pci_dev->intr_handle);
4573 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4576 struct ixgbe_hw *hw =
4577 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4579 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4580 mask &= ~(1 << IXGBE_MISC_VEC_ID);
4581 RTE_SET_USED(queue_id);
4582 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4588 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4591 struct ixgbe_hw *hw =
4592 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4593 struct ixgbe_interrupt *intr =
4594 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4596 if (queue_id < 16) {
4597 ixgbe_disable_intr(hw);
4598 intr->mask |= (1 << queue_id);
4599 ixgbe_enable_intr(dev);
4600 } else if (queue_id < 32) {
4601 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4602 mask &= (1 << queue_id);
4603 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4604 } else if (queue_id < 64) {
4605 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4606 mask &= (1 << (queue_id - 32));
4607 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4609 rte_intr_enable(&dev->pci_dev->intr_handle);
4615 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4618 struct ixgbe_hw *hw =
4619 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4620 struct ixgbe_interrupt *intr =
4621 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4623 if (queue_id < 16) {
4624 ixgbe_disable_intr(hw);
4625 intr->mask &= ~(1 << queue_id);
4626 ixgbe_enable_intr(dev);
4627 } else if (queue_id < 32) {
4628 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4629 mask &= ~(1 << queue_id);
4630 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4631 } else if (queue_id < 64) {
4632 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4633 mask &= ~(1 << (queue_id - 32));
4634 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4641 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4642 uint8_t queue, uint8_t msix_vector)
4646 if (direction == -1) {
4648 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4649 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4652 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4654 /* rx or tx cause */
4655 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4656 idx = ((16 * (queue & 1)) + (8 * direction));
4657 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4658 tmp &= ~(0xFF << idx);
4659 tmp |= (msix_vector << idx);
4660 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4665 * set the IVAR registers, mapping interrupt causes to vectors
4667 * pointer to ixgbe_hw struct
4669 * 0 for Rx, 1 for Tx, -1 for other causes
4671 * queue to map the corresponding interrupt to
4673 * the vector to map to the corresponding queue
4676 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4677 uint8_t queue, uint8_t msix_vector)
4681 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4682 if (hw->mac.type == ixgbe_mac_82598EB) {
4683 if (direction == -1)
4685 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4686 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4687 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4688 tmp |= (msix_vector << (8 * (queue & 0x3)));
4689 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4690 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4691 (hw->mac.type == ixgbe_mac_X540)) {
4692 if (direction == -1) {
4694 idx = ((queue & 1) * 8);
4695 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4696 tmp &= ~(0xFF << idx);
4697 tmp |= (msix_vector << idx);
4698 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4700 /* rx or tx causes */
4701 idx = ((16 * (queue & 1)) + (8 * direction));
4702 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4703 tmp &= ~(0xFF << idx);
4704 tmp |= (msix_vector << idx);
4705 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4711 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4713 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4714 struct ixgbe_hw *hw =
4715 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4717 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4719 /* won't configure msix register if no mapping is done
4720 * between intr vector and event fd.
4722 if (!rte_intr_dp_is_en(intr_handle))
4725 /* Configure all RX queues of VF */
4726 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4727 /* Force all queue use vector 0,
4728 * as IXGBE_VF_MAXMSIVECOTR = 1
4730 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4731 intr_handle->intr_vec[q_idx] = vector_idx;
4734 /* Configure VF other cause ivar */
4735 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4739 * Sets up the hardware to properly generate MSI-X interrupts
4741 * board private structure
4744 ixgbe_configure_msix(struct rte_eth_dev *dev)
4746 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4747 struct ixgbe_hw *hw =
4748 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4749 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4750 uint32_t vec = IXGBE_MISC_VEC_ID;
4754 /* won't configure msix register if no mapping is done
4755 * between intr vector and event fd
4757 if (!rte_intr_dp_is_en(intr_handle))
4760 if (rte_intr_allow_others(intr_handle))
4761 vec = base = IXGBE_RX_VEC_START;
4763 /* setup GPIE for MSI-x mode */
4764 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4765 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4766 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4767 /* auto clearing and auto setting corresponding bits in EIMS
4768 * when MSI-X interrupt is triggered
4770 if (hw->mac.type == ixgbe_mac_82598EB) {
4771 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4773 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4774 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4776 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4778 /* Populate the IVAR table and set the ITR values to the
4779 * corresponding register.
4781 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4783 /* by default, 1:1 mapping */
4784 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4785 intr_handle->intr_vec[queue_id] = vec;
4786 if (vec < base + intr_handle->nb_efd - 1)
4790 switch (hw->mac.type) {
4791 case ixgbe_mac_82598EB:
4792 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4795 case ixgbe_mac_82599EB:
4796 case ixgbe_mac_X540:
4797 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4802 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4803 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4805 /* set up to autoclear timer, and the vectors */
4806 mask = IXGBE_EIMS_ENABLE_MASK;
4807 mask &= ~(IXGBE_EIMS_OTHER |
4808 IXGBE_EIMS_MAILBOX |
4811 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4814 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4815 uint16_t queue_idx, uint16_t tx_rate)
4817 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4818 uint32_t rf_dec, rf_int;
4820 uint16_t link_speed = dev->data->dev_link.link_speed;
4822 if (queue_idx >= hw->mac.max_tx_queues)
4826 /* Calculate the rate factor values to set */
4827 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4828 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4829 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4831 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4832 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4833 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4834 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4840 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4841 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4844 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4845 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4846 IXGBE_MAX_JUMBO_FRAME_SIZE))
4847 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4848 IXGBE_MMW_SIZE_JUMBO_FRAME);
4850 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4851 IXGBE_MMW_SIZE_DEFAULT);
4853 /* Set RTTBCNRC of queue X */
4854 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4855 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4856 IXGBE_WRITE_FLUSH(hw);
4861 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4862 uint16_t tx_rate, uint64_t q_msk)
4864 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4865 struct ixgbe_vf_info *vfinfo =
4866 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4867 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4868 uint32_t queue_stride =
4869 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4870 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4871 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4872 uint16_t total_rate = 0;
4874 if (queue_end >= hw->mac.max_tx_queues)
4877 if (vfinfo != NULL) {
4878 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4881 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4883 total_rate += vfinfo[vf_idx].tx_rate[idx];
4888 /* Store tx_rate for this vf. */
4889 for (idx = 0; idx < nb_q_per_pool; idx++) {
4890 if (((uint64_t)0x1 << idx) & q_msk) {
4891 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4892 vfinfo[vf].tx_rate[idx] = tx_rate;
4893 total_rate += tx_rate;
4897 if (total_rate > dev->data->dev_link.link_speed) {
4899 * Reset stored TX rate of the VF if it causes exceed
4902 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4906 /* Set RTTBCNRC of each queue/pool for vf X */
4907 for (; queue_idx <= queue_end; queue_idx++) {
4909 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4917 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4918 __attribute__((unused)) uint32_t index,
4919 __attribute__((unused)) uint32_t pool)
4921 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4925 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4926 * operation. Trap this case to avoid exhausting the [very limited]
4927 * set of PF resources used to store VF MAC addresses.
4929 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4931 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4934 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4938 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4940 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4941 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4942 struct ether_addr *mac_addr;
4947 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4948 * not support the deletion of a given MAC address.
4949 * Instead, it imposes to delete all MAC addresses, then to add again
4950 * all MAC addresses with the exception of the one to be deleted.
4952 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4955 * Add again all MAC addresses, with the exception of the deleted one
4956 * and of the permanent MAC address.
4958 for (i = 0, mac_addr = dev->data->mac_addrs;
4959 i < hw->mac.num_rar_entries; i++, mac_addr++) {
4960 /* Skip the deleted MAC address */
4963 /* Skip NULL MAC addresses */
4964 if (is_zero_ether_addr(mac_addr))
4966 /* Skip the permanent MAC address */
4967 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4969 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4972 "Adding again MAC address "
4973 "%02x:%02x:%02x:%02x:%02x:%02x failed "
4975 mac_addr->addr_bytes[0],
4976 mac_addr->addr_bytes[1],
4977 mac_addr->addr_bytes[2],
4978 mac_addr->addr_bytes[3],
4979 mac_addr->addr_bytes[4],
4980 mac_addr->addr_bytes[5],
4986 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4988 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4990 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4993 #define MAC_TYPE_FILTER_SUP(type) do {\
4994 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4995 (type) != ixgbe_mac_X550)\
5000 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5001 struct rte_eth_syn_filter *filter,
5004 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5007 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5010 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5013 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5015 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5016 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5018 if (filter->hig_pri)
5019 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5021 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5023 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5025 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5027 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5028 IXGBE_WRITE_FLUSH(hw);
5033 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5034 struct rte_eth_syn_filter *filter)
5036 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5037 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5039 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5040 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5041 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5048 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5049 enum rte_filter_op filter_op,
5052 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5055 MAC_TYPE_FILTER_SUP(hw->mac.type);
5057 if (filter_op == RTE_ETH_FILTER_NOP)
5061 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5066 switch (filter_op) {
5067 case RTE_ETH_FILTER_ADD:
5068 ret = ixgbe_syn_filter_set(dev,
5069 (struct rte_eth_syn_filter *)arg,
5072 case RTE_ETH_FILTER_DELETE:
5073 ret = ixgbe_syn_filter_set(dev,
5074 (struct rte_eth_syn_filter *)arg,
5077 case RTE_ETH_FILTER_GET:
5078 ret = ixgbe_syn_filter_get(dev,
5079 (struct rte_eth_syn_filter *)arg);
5082 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5091 static inline enum ixgbe_5tuple_protocol
5092 convert_protocol_type(uint8_t protocol_value)
5094 if (protocol_value == IPPROTO_TCP)
5095 return IXGBE_FILTER_PROTOCOL_TCP;
5096 else if (protocol_value == IPPROTO_UDP)
5097 return IXGBE_FILTER_PROTOCOL_UDP;
5098 else if (protocol_value == IPPROTO_SCTP)
5099 return IXGBE_FILTER_PROTOCOL_SCTP;
5101 return IXGBE_FILTER_PROTOCOL_NONE;
5105 * add a 5tuple filter
5108 * dev: Pointer to struct rte_eth_dev.
5109 * index: the index the filter allocates.
5110 * filter: ponter to the filter that will be added.
5111 * rx_queue: the queue id the filter assigned to.
5114 * - On success, zero.
5115 * - On failure, a negative value.
5118 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5119 struct ixgbe_5tuple_filter *filter)
5121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5122 struct ixgbe_filter_info *filter_info =
5123 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5125 uint32_t ftqf, sdpqf;
5126 uint32_t l34timir = 0;
5127 uint8_t mask = 0xff;
5130 * look for an unused 5tuple filter index,
5131 * and insert the filter to list.
5133 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5134 idx = i / (sizeof(uint32_t) * NBBY);
5135 shift = i % (sizeof(uint32_t) * NBBY);
5136 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5137 filter_info->fivetuple_mask[idx] |= 1 << shift;
5139 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5145 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5146 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5150 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5151 IXGBE_SDPQF_DSTPORT_SHIFT);
5152 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5154 ftqf = (uint32_t)(filter->filter_info.proto &
5155 IXGBE_FTQF_PROTOCOL_MASK);
5156 ftqf |= (uint32_t)((filter->filter_info.priority &
5157 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5158 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5159 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5160 if (filter->filter_info.dst_ip_mask == 0)
5161 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5162 if (filter->filter_info.src_port_mask == 0)
5163 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5164 if (filter->filter_info.dst_port_mask == 0)
5165 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5166 if (filter->filter_info.proto_mask == 0)
5167 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5168 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5169 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5170 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5172 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5173 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5174 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5175 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5177 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5178 l34timir |= (uint32_t)(filter->queue <<
5179 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5180 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5185 * remove a 5tuple filter
5188 * dev: Pointer to struct rte_eth_dev.
5189 * filter: the pointer of the filter will be removed.
5192 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5193 struct ixgbe_5tuple_filter *filter)
5195 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5196 struct ixgbe_filter_info *filter_info =
5197 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5198 uint16_t index = filter->index;
5200 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5201 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5202 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5205 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5206 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5207 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5208 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5209 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5213 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5215 struct ixgbe_hw *hw;
5216 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5218 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5220 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5223 /* refuse mtu that requires the support of scattered packets when this
5224 * feature has not been enabled before. */
5225 if (!dev->data->scattered_rx &&
5226 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5227 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5231 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5232 * request of the version 2.0 of the mailbox API.
5233 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5234 * of the mailbox API.
5235 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5236 * prior to 3.11.33 which contains the following change:
5237 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5239 ixgbevf_rlpml_set_vf(hw, max_frame);
5241 /* update max frame size */
5242 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5246 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5247 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5251 static inline struct ixgbe_5tuple_filter *
5252 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5253 struct ixgbe_5tuple_filter_info *key)
5255 struct ixgbe_5tuple_filter *it;
5257 TAILQ_FOREACH(it, filter_list, entries) {
5258 if (memcmp(key, &it->filter_info,
5259 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5266 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5268 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5269 struct ixgbe_5tuple_filter_info *filter_info)
5271 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5272 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5273 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5276 switch (filter->dst_ip_mask) {
5278 filter_info->dst_ip_mask = 0;
5279 filter_info->dst_ip = filter->dst_ip;
5282 filter_info->dst_ip_mask = 1;
5285 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5289 switch (filter->src_ip_mask) {
5291 filter_info->src_ip_mask = 0;
5292 filter_info->src_ip = filter->src_ip;
5295 filter_info->src_ip_mask = 1;
5298 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5302 switch (filter->dst_port_mask) {
5304 filter_info->dst_port_mask = 0;
5305 filter_info->dst_port = filter->dst_port;
5308 filter_info->dst_port_mask = 1;
5311 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5315 switch (filter->src_port_mask) {
5317 filter_info->src_port_mask = 0;
5318 filter_info->src_port = filter->src_port;
5321 filter_info->src_port_mask = 1;
5324 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5328 switch (filter->proto_mask) {
5330 filter_info->proto_mask = 0;
5331 filter_info->proto =
5332 convert_protocol_type(filter->proto);
5335 filter_info->proto_mask = 1;
5338 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5342 filter_info->priority = (uint8_t)filter->priority;
5347 * add or delete a ntuple filter
5350 * dev: Pointer to struct rte_eth_dev.
5351 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5352 * add: if true, add filter, if false, remove filter
5355 * - On success, zero.
5356 * - On failure, a negative value.
5359 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5360 struct rte_eth_ntuple_filter *ntuple_filter,
5363 struct ixgbe_filter_info *filter_info =
5364 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5365 struct ixgbe_5tuple_filter_info filter_5tuple;
5366 struct ixgbe_5tuple_filter *filter;
5369 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5370 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5374 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5375 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5379 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5381 if (filter != NULL && add) {
5382 PMD_DRV_LOG(ERR, "filter exists.");
5385 if (filter == NULL && !add) {
5386 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5391 filter = rte_zmalloc("ixgbe_5tuple_filter",
5392 sizeof(struct ixgbe_5tuple_filter), 0);
5395 (void)rte_memcpy(&filter->filter_info,
5397 sizeof(struct ixgbe_5tuple_filter_info));
5398 filter->queue = ntuple_filter->queue;
5399 ret = ixgbe_add_5tuple_filter(dev, filter);
5405 ixgbe_remove_5tuple_filter(dev, filter);
5411 * get a ntuple filter
5414 * dev: Pointer to struct rte_eth_dev.
5415 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5418 * - On success, zero.
5419 * - On failure, a negative value.
5422 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5423 struct rte_eth_ntuple_filter *ntuple_filter)
5425 struct ixgbe_filter_info *filter_info =
5426 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5427 struct ixgbe_5tuple_filter_info filter_5tuple;
5428 struct ixgbe_5tuple_filter *filter;
5431 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5432 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5436 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5437 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5441 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5443 if (filter == NULL) {
5444 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5447 ntuple_filter->queue = filter->queue;
5452 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5453 * @dev: pointer to rte_eth_dev structure
5454 * @filter_op:operation will be taken.
5455 * @arg: a pointer to specific structure corresponding to the filter_op
5458 * - On success, zero.
5459 * - On failure, a negative value.
5462 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5463 enum rte_filter_op filter_op,
5466 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5469 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5471 if (filter_op == RTE_ETH_FILTER_NOP)
5475 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5480 switch (filter_op) {
5481 case RTE_ETH_FILTER_ADD:
5482 ret = ixgbe_add_del_ntuple_filter(dev,
5483 (struct rte_eth_ntuple_filter *)arg,
5486 case RTE_ETH_FILTER_DELETE:
5487 ret = ixgbe_add_del_ntuple_filter(dev,
5488 (struct rte_eth_ntuple_filter *)arg,
5491 case RTE_ETH_FILTER_GET:
5492 ret = ixgbe_get_ntuple_filter(dev,
5493 (struct rte_eth_ntuple_filter *)arg);
5496 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5504 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5509 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5510 if (filter_info->ethertype_filters[i] == ethertype &&
5511 (filter_info->ethertype_mask & (1 << i)))
5518 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5523 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5524 if (!(filter_info->ethertype_mask & (1 << i))) {
5525 filter_info->ethertype_mask |= 1 << i;
5526 filter_info->ethertype_filters[i] = ethertype;
5534 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5537 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5539 filter_info->ethertype_mask &= ~(1 << idx);
5540 filter_info->ethertype_filters[idx] = 0;
5545 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5546 struct rte_eth_ethertype_filter *filter,
5549 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5550 struct ixgbe_filter_info *filter_info =
5551 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5556 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5559 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5560 filter->ether_type == ETHER_TYPE_IPv6) {
5561 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5562 " ethertype filter.", filter->ether_type);
5566 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5567 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5570 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5571 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5575 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5576 if (ret >= 0 && add) {
5577 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5578 filter->ether_type);
5581 if (ret < 0 && !add) {
5582 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5583 filter->ether_type);
5588 ret = ixgbe_ethertype_filter_insert(filter_info,
5589 filter->ether_type);
5591 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5594 etqf = IXGBE_ETQF_FILTER_EN;
5595 etqf |= (uint32_t)filter->ether_type;
5596 etqs |= (uint32_t)((filter->queue <<
5597 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5598 IXGBE_ETQS_RX_QUEUE);
5599 etqs |= IXGBE_ETQS_QUEUE_EN;
5601 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5605 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5606 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5607 IXGBE_WRITE_FLUSH(hw);
5613 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5614 struct rte_eth_ethertype_filter *filter)
5616 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5617 struct ixgbe_filter_info *filter_info =
5618 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5619 uint32_t etqf, etqs;
5622 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5624 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5625 filter->ether_type);
5629 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5630 if (etqf & IXGBE_ETQF_FILTER_EN) {
5631 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5632 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5634 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5635 IXGBE_ETQS_RX_QUEUE_SHIFT;
5642 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5643 * @dev: pointer to rte_eth_dev structure
5644 * @filter_op:operation will be taken.
5645 * @arg: a pointer to specific structure corresponding to the filter_op
5648 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5649 enum rte_filter_op filter_op,
5652 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5655 MAC_TYPE_FILTER_SUP(hw->mac.type);
5657 if (filter_op == RTE_ETH_FILTER_NOP)
5661 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5666 switch (filter_op) {
5667 case RTE_ETH_FILTER_ADD:
5668 ret = ixgbe_add_del_ethertype_filter(dev,
5669 (struct rte_eth_ethertype_filter *)arg,
5672 case RTE_ETH_FILTER_DELETE:
5673 ret = ixgbe_add_del_ethertype_filter(dev,
5674 (struct rte_eth_ethertype_filter *)arg,
5677 case RTE_ETH_FILTER_GET:
5678 ret = ixgbe_get_ethertype_filter(dev,
5679 (struct rte_eth_ethertype_filter *)arg);
5682 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5690 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5691 enum rte_filter_type filter_type,
5692 enum rte_filter_op filter_op,
5697 switch (filter_type) {
5698 case RTE_ETH_FILTER_NTUPLE:
5699 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5701 case RTE_ETH_FILTER_ETHERTYPE:
5702 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5704 case RTE_ETH_FILTER_SYN:
5705 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5707 case RTE_ETH_FILTER_FDIR:
5708 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5710 case RTE_ETH_FILTER_L2_TUNNEL:
5711 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5714 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5723 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5724 u8 **mc_addr_ptr, u32 *vmdq)
5729 mc_addr = *mc_addr_ptr;
5730 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5735 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5736 struct ether_addr *mc_addr_set,
5737 uint32_t nb_mc_addr)
5739 struct ixgbe_hw *hw;
5742 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5743 mc_addr_list = (u8 *)mc_addr_set;
5744 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5745 ixgbe_dev_addr_list_itr, TRUE);
5749 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5751 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5752 uint64_t systime_cycles;
5754 switch (hw->mac.type) {
5755 case ixgbe_mac_X550:
5756 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5757 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5758 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5762 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5763 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5767 return systime_cycles;
5771 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5773 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5774 uint64_t rx_tstamp_cycles;
5776 switch (hw->mac.type) {
5777 case ixgbe_mac_X550:
5778 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5779 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5780 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5784 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5785 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5786 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5790 return rx_tstamp_cycles;
5794 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5796 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5797 uint64_t tx_tstamp_cycles;
5799 switch (hw->mac.type) {
5800 case ixgbe_mac_X550:
5801 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5802 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5803 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5807 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5808 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5809 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5813 return tx_tstamp_cycles;
5817 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5819 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5820 struct ixgbe_adapter *adapter =
5821 (struct ixgbe_adapter *)dev->data->dev_private;
5822 struct rte_eth_link link;
5823 uint32_t incval = 0;
5826 /* Get current link speed. */
5827 memset(&link, 0, sizeof(link));
5828 ixgbe_dev_link_update(dev, 1);
5829 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5831 switch (link.link_speed) {
5832 case ETH_LINK_SPEED_100:
5833 incval = IXGBE_INCVAL_100;
5834 shift = IXGBE_INCVAL_SHIFT_100;
5836 case ETH_LINK_SPEED_1000:
5837 incval = IXGBE_INCVAL_1GB;
5838 shift = IXGBE_INCVAL_SHIFT_1GB;
5840 case ETH_LINK_SPEED_10000:
5842 incval = IXGBE_INCVAL_10GB;
5843 shift = IXGBE_INCVAL_SHIFT_10GB;
5847 switch (hw->mac.type) {
5848 case ixgbe_mac_X550:
5849 /* Independent of link speed. */
5851 /* Cycles read will be interpreted as ns. */
5854 case ixgbe_mac_X540:
5855 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5857 case ixgbe_mac_82599EB:
5858 incval >>= IXGBE_INCVAL_SHIFT_82599;
5859 shift -= IXGBE_INCVAL_SHIFT_82599;
5860 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5861 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5864 /* Not supported. */
5868 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5869 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5870 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5872 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5873 adapter->systime_tc.cc_shift = shift;
5874 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5876 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5877 adapter->rx_tstamp_tc.cc_shift = shift;
5878 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5880 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5881 adapter->tx_tstamp_tc.cc_shift = shift;
5882 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5886 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5888 struct ixgbe_adapter *adapter =
5889 (struct ixgbe_adapter *)dev->data->dev_private;
5891 adapter->systime_tc.nsec += delta;
5892 adapter->rx_tstamp_tc.nsec += delta;
5893 adapter->tx_tstamp_tc.nsec += delta;
5899 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5902 struct ixgbe_adapter *adapter =
5903 (struct ixgbe_adapter *)dev->data->dev_private;
5905 ns = rte_timespec_to_ns(ts);
5906 /* Set the timecounters to a new value. */
5907 adapter->systime_tc.nsec = ns;
5908 adapter->rx_tstamp_tc.nsec = ns;
5909 adapter->tx_tstamp_tc.nsec = ns;
5915 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5917 uint64_t ns, systime_cycles;
5918 struct ixgbe_adapter *adapter =
5919 (struct ixgbe_adapter *)dev->data->dev_private;
5921 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5922 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5923 *ts = rte_ns_to_timespec(ns);
5929 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5931 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5935 /* Stop the timesync system time. */
5936 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5937 /* Reset the timesync system time value. */
5938 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5939 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5941 /* Enable system time for platforms where it isn't on by default. */
5942 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5943 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5944 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5946 ixgbe_start_timecounters(dev);
5948 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5949 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5951 IXGBE_ETQF_FILTER_EN |
5954 /* Enable timestamping of received PTP packets. */
5955 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5956 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5957 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5959 /* Enable timestamping of transmitted PTP packets. */
5960 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5961 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5962 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5964 IXGBE_WRITE_FLUSH(hw);
5970 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5972 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5975 /* Disable timestamping of transmitted PTP packets. */
5976 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5977 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5978 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5980 /* Disable timestamping of received PTP packets. */
5981 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5982 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5983 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5985 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5986 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5988 /* Stop incrementating the System Time registers. */
5989 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5995 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5996 struct timespec *timestamp,
5997 uint32_t flags __rte_unused)
5999 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6000 struct ixgbe_adapter *adapter =
6001 (struct ixgbe_adapter *)dev->data->dev_private;
6002 uint32_t tsync_rxctl;
6003 uint64_t rx_tstamp_cycles;
6006 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6007 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6010 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6011 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6012 *timestamp = rte_ns_to_timespec(ns);
6018 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6019 struct timespec *timestamp)
6021 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6022 struct ixgbe_adapter *adapter =
6023 (struct ixgbe_adapter *)dev->data->dev_private;
6024 uint32_t tsync_txctl;
6025 uint64_t tx_tstamp_cycles;
6028 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6029 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6032 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6033 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6034 *timestamp = rte_ns_to_timespec(ns);
6040 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6042 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6045 const struct reg_info *reg_group;
6046 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6047 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6049 while ((reg_group = reg_set[g_ind++]))
6050 count += ixgbe_regs_group_count(reg_group);
6056 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6060 const struct reg_info *reg_group;
6062 while ((reg_group = ixgbevf_regs[g_ind++]))
6063 count += ixgbe_regs_group_count(reg_group);
6069 ixgbe_get_regs(struct rte_eth_dev *dev,
6070 struct rte_dev_reg_info *regs)
6072 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6073 uint32_t *data = regs->data;
6076 const struct reg_info *reg_group;
6077 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6078 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6080 /* Support only full register dump */
6081 if ((regs->length == 0) ||
6082 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6083 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6085 while ((reg_group = reg_set[g_ind++]))
6086 count += ixgbe_read_regs_group(dev, &data[count],
6095 ixgbevf_get_regs(struct rte_eth_dev *dev,
6096 struct rte_dev_reg_info *regs)
6098 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6099 uint32_t *data = regs->data;
6102 const struct reg_info *reg_group;
6104 /* Support only full register dump */
6105 if ((regs->length == 0) ||
6106 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6107 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6109 while ((reg_group = ixgbevf_regs[g_ind++]))
6110 count += ixgbe_read_regs_group(dev, &data[count],
6119 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6123 /* Return unit is byte count */
6124 return hw->eeprom.word_size * 2;
6128 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6129 struct rte_dev_eeprom_info *in_eeprom)
6131 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6132 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6133 uint16_t *data = in_eeprom->data;
6136 first = in_eeprom->offset >> 1;
6137 length = in_eeprom->length >> 1;
6138 if ((first > hw->eeprom.word_size) ||
6139 ((first + length) > hw->eeprom.word_size))
6142 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6144 return eeprom->ops.read_buffer(hw, first, length, data);
6148 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6149 struct rte_dev_eeprom_info *in_eeprom)
6151 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6152 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6153 uint16_t *data = in_eeprom->data;
6156 first = in_eeprom->offset >> 1;
6157 length = in_eeprom->length >> 1;
6158 if ((first > hw->eeprom.word_size) ||
6159 ((first + length) > hw->eeprom.word_size))
6162 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6164 return eeprom->ops.write_buffer(hw, first, length, data);
6168 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6170 case ixgbe_mac_X550:
6171 case ixgbe_mac_X550EM_x:
6172 case ixgbe_mac_X550EM_a:
6173 return ETH_RSS_RETA_SIZE_512;
6174 case ixgbe_mac_X550_vf:
6175 case ixgbe_mac_X550EM_x_vf:
6176 case ixgbe_mac_X550EM_a_vf:
6177 return ETH_RSS_RETA_SIZE_64;
6179 return ETH_RSS_RETA_SIZE_128;
6184 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6186 case ixgbe_mac_X550:
6187 case ixgbe_mac_X550EM_x:
6188 case ixgbe_mac_X550EM_a:
6189 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6190 return IXGBE_RETA(reta_idx >> 2);
6192 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6193 case ixgbe_mac_X550_vf:
6194 case ixgbe_mac_X550EM_x_vf:
6195 case ixgbe_mac_X550EM_a_vf:
6196 return IXGBE_VFRETA(reta_idx >> 2);
6198 return IXGBE_RETA(reta_idx >> 2);
6203 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6205 case ixgbe_mac_X550_vf:
6206 case ixgbe_mac_X550EM_x_vf:
6207 case ixgbe_mac_X550EM_a_vf:
6208 return IXGBE_VFMRQC;
6215 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6217 case ixgbe_mac_X550_vf:
6218 case ixgbe_mac_X550EM_x_vf:
6219 case ixgbe_mac_X550EM_a_vf:
6220 return IXGBE_VFRSSRK(i);
6222 return IXGBE_RSSRK(i);
6227 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6229 case ixgbe_mac_82599_vf:
6230 case ixgbe_mac_X540_vf:
6238 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6239 struct rte_eth_dcb_info *dcb_info)
6241 struct ixgbe_dcb_config *dcb_config =
6242 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6243 struct ixgbe_dcb_tc_config *tc;
6246 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6247 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6249 dcb_info->nb_tcs = 1;
6251 if (dcb_config->vt_mode) { /* vt is enabled*/
6252 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6253 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6254 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6255 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6256 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6257 for (j = 0; j < dcb_info->nb_tcs; j++) {
6258 dcb_info->tc_queue.tc_rxq[i][j].base =
6259 i * dcb_info->nb_tcs + j;
6260 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6261 dcb_info->tc_queue.tc_txq[i][j].base =
6262 i * dcb_info->nb_tcs + j;
6263 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6266 } else { /* vt is disabled*/
6267 struct rte_eth_dcb_rx_conf *rx_conf =
6268 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6269 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6270 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6271 if (dcb_info->nb_tcs == ETH_4_TCS) {
6272 for (i = 0; i < dcb_info->nb_tcs; i++) {
6273 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6274 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6276 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6277 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6278 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6279 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6280 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6281 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6282 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6283 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6284 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6285 for (i = 0; i < dcb_info->nb_tcs; i++) {
6286 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6287 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6289 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6290 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6291 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6292 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6293 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6294 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6295 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6296 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6297 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6298 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6299 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6300 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6301 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6302 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6303 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6304 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6307 for (i = 0; i < dcb_info->nb_tcs; i++) {
6308 tc = &dcb_config->tc_config[i];
6309 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6314 /* Update e-tag ether type */
6316 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6317 uint16_t ether_type)
6319 uint32_t etag_etype;
6321 if (hw->mac.type != ixgbe_mac_X550 &&
6322 hw->mac.type != ixgbe_mac_X550EM_x) {
6326 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6327 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6328 etag_etype |= ether_type;
6329 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6330 IXGBE_WRITE_FLUSH(hw);
6335 /* Config l2 tunnel ether type */
6337 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6338 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6341 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6343 if (l2_tunnel == NULL)
6346 switch (l2_tunnel->l2_tunnel_type) {
6347 case RTE_L2_TUNNEL_TYPE_E_TAG:
6348 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6351 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6359 /* Enable e-tag tunnel */
6361 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6363 uint32_t etag_etype;
6365 if (hw->mac.type != ixgbe_mac_X550 &&
6366 hw->mac.type != ixgbe_mac_X550EM_x) {
6370 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6371 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6372 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6373 IXGBE_WRITE_FLUSH(hw);
6378 /* Enable l2 tunnel */
6380 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6381 enum rte_eth_tunnel_type l2_tunnel_type)
6384 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6386 switch (l2_tunnel_type) {
6387 case RTE_L2_TUNNEL_TYPE_E_TAG:
6388 ret = ixgbe_e_tag_enable(hw);
6391 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6399 /* Disable e-tag tunnel */
6401 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6403 uint32_t etag_etype;
6405 if (hw->mac.type != ixgbe_mac_X550 &&
6406 hw->mac.type != ixgbe_mac_X550EM_x) {
6410 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6411 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6412 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6413 IXGBE_WRITE_FLUSH(hw);
6418 /* Disable l2 tunnel */
6420 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6421 enum rte_eth_tunnel_type l2_tunnel_type)
6424 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6426 switch (l2_tunnel_type) {
6427 case RTE_L2_TUNNEL_TYPE_E_TAG:
6428 ret = ixgbe_e_tag_disable(hw);
6431 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6440 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6441 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6444 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6445 uint32_t i, rar_entries;
6446 uint32_t rar_low, rar_high;
6448 if (hw->mac.type != ixgbe_mac_X550 &&
6449 hw->mac.type != ixgbe_mac_X550EM_x) {
6453 rar_entries = ixgbe_get_num_rx_addrs(hw);
6455 for (i = 1; i < rar_entries; i++) {
6456 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6457 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6458 if ((rar_high & IXGBE_RAH_AV) &&
6459 (rar_high & IXGBE_RAH_ADTYPE) &&
6460 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6461 l2_tunnel->tunnel_id)) {
6462 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6463 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6465 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6475 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6476 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6479 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6480 uint32_t i, rar_entries;
6481 uint32_t rar_low, rar_high;
6483 if (hw->mac.type != ixgbe_mac_X550 &&
6484 hw->mac.type != ixgbe_mac_X550EM_x) {
6488 /* One entry for one tunnel. Try to remove potential existing entry. */
6489 ixgbe_e_tag_filter_del(dev, l2_tunnel);
6491 rar_entries = ixgbe_get_num_rx_addrs(hw);
6493 for (i = 1; i < rar_entries; i++) {
6494 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6495 if (rar_high & IXGBE_RAH_AV) {
6498 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6499 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6500 rar_low = l2_tunnel->tunnel_id;
6502 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6503 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6509 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6510 " Please remove a rule before adding a new one.");
6514 /* Add l2 tunnel filter */
6516 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6517 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6521 switch (l2_tunnel->l2_tunnel_type) {
6522 case RTE_L2_TUNNEL_TYPE_E_TAG:
6523 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6526 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6534 /* Delete l2 tunnel filter */
6536 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6537 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6541 switch (l2_tunnel->l2_tunnel_type) {
6542 case RTE_L2_TUNNEL_TYPE_E_TAG:
6543 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6546 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6555 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6556 * @dev: pointer to rte_eth_dev structure
6557 * @filter_op:operation will be taken.
6558 * @arg: a pointer to specific structure corresponding to the filter_op
6561 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6562 enum rte_filter_op filter_op,
6567 if (filter_op == RTE_ETH_FILTER_NOP)
6571 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6576 switch (filter_op) {
6577 case RTE_ETH_FILTER_ADD:
6578 ret = ixgbe_dev_l2_tunnel_filter_add
6580 (struct rte_eth_l2_tunnel_conf *)arg);
6582 case RTE_ETH_FILTER_DELETE:
6583 ret = ixgbe_dev_l2_tunnel_filter_del
6585 (struct rte_eth_l2_tunnel_conf *)arg);
6588 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6596 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6600 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6602 if (hw->mac.type != ixgbe_mac_X550 &&
6603 hw->mac.type != ixgbe_mac_X550EM_x) {
6607 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6608 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6610 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6611 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6616 /* Enable l2 tunnel forwarding */
6618 ixgbe_dev_l2_tunnel_forwarding_enable
6619 (struct rte_eth_dev *dev,
6620 enum rte_eth_tunnel_type l2_tunnel_type)
6624 switch (l2_tunnel_type) {
6625 case RTE_L2_TUNNEL_TYPE_E_TAG:
6626 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6629 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6637 /* Disable l2 tunnel forwarding */
6639 ixgbe_dev_l2_tunnel_forwarding_disable
6640 (struct rte_eth_dev *dev,
6641 enum rte_eth_tunnel_type l2_tunnel_type)
6645 switch (l2_tunnel_type) {
6646 case RTE_L2_TUNNEL_TYPE_E_TAG:
6647 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6650 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6659 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6660 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6664 uint32_t vmtir, vmvir;
6665 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6667 if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6669 "VF id %u should be less than %u",
6671 dev->pci_dev->max_vfs);
6675 if (hw->mac.type != ixgbe_mac_X550 &&
6676 hw->mac.type != ixgbe_mac_X550EM_x) {
6681 vmtir = l2_tunnel->tunnel_id;
6685 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6687 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6688 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6690 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6691 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6696 /* Enable l2 tunnel tag insertion */
6698 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6699 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6703 switch (l2_tunnel->l2_tunnel_type) {
6704 case RTE_L2_TUNNEL_TYPE_E_TAG:
6705 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6708 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6716 /* Disable l2 tunnel tag insertion */
6718 ixgbe_dev_l2_tunnel_insertion_disable
6719 (struct rte_eth_dev *dev,
6720 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6724 switch (l2_tunnel->l2_tunnel_type) {
6725 case RTE_L2_TUNNEL_TYPE_E_TAG:
6726 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6729 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6738 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6743 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6745 if (hw->mac.type != ixgbe_mac_X550 &&
6746 hw->mac.type != ixgbe_mac_X550EM_x) {
6750 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6752 qde |= IXGBE_QDE_STRIP_TAG;
6754 qde &= ~IXGBE_QDE_STRIP_TAG;
6755 qde &= ~IXGBE_QDE_READ;
6756 qde |= IXGBE_QDE_WRITE;
6757 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6762 /* Enable l2 tunnel tag stripping */
6764 ixgbe_dev_l2_tunnel_stripping_enable
6765 (struct rte_eth_dev *dev,
6766 enum rte_eth_tunnel_type l2_tunnel_type)
6770 switch (l2_tunnel_type) {
6771 case RTE_L2_TUNNEL_TYPE_E_TAG:
6772 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6775 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6783 /* Disable l2 tunnel tag stripping */
6785 ixgbe_dev_l2_tunnel_stripping_disable
6786 (struct rte_eth_dev *dev,
6787 enum rte_eth_tunnel_type l2_tunnel_type)
6791 switch (l2_tunnel_type) {
6792 case RTE_L2_TUNNEL_TYPE_E_TAG:
6793 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6796 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6804 /* Enable/disable l2 tunnel offload functions */
6806 ixgbe_dev_l2_tunnel_offload_set
6807 (struct rte_eth_dev *dev,
6808 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6814 if (l2_tunnel == NULL)
6818 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6820 ret = ixgbe_dev_l2_tunnel_enable(
6822 l2_tunnel->l2_tunnel_type);
6824 ret = ixgbe_dev_l2_tunnel_disable(
6826 l2_tunnel->l2_tunnel_type);
6829 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6831 ret = ixgbe_dev_l2_tunnel_insertion_enable(
6835 ret = ixgbe_dev_l2_tunnel_insertion_disable(
6840 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6842 ret = ixgbe_dev_l2_tunnel_stripping_enable(
6844 l2_tunnel->l2_tunnel_type);
6846 ret = ixgbe_dev_l2_tunnel_stripping_disable(
6848 l2_tunnel->l2_tunnel_type);
6851 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6853 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6855 l2_tunnel->l2_tunnel_type);
6857 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6859 l2_tunnel->l2_tunnel_type);
6866 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6869 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6870 IXGBE_WRITE_FLUSH(hw);
6875 /* There's only one register for VxLAN UDP port.
6876 * So, we cannot add several ports. Will update it.
6879 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6883 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6887 return ixgbe_update_vxlan_port(hw, port);
6890 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6891 * UDP port, it must have a value.
6892 * So, will reset it to the original value 0.
6895 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6900 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6902 if (cur_port != port) {
6903 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6907 return ixgbe_update_vxlan_port(hw, 0);
6910 /* Add UDP tunneling port */
6912 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6913 struct rte_eth_udp_tunnel *udp_tunnel)
6916 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6918 if (hw->mac.type != ixgbe_mac_X550 &&
6919 hw->mac.type != ixgbe_mac_X550EM_x) {
6923 if (udp_tunnel == NULL)
6926 switch (udp_tunnel->prot_type) {
6927 case RTE_TUNNEL_TYPE_VXLAN:
6928 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6931 case RTE_TUNNEL_TYPE_GENEVE:
6932 case RTE_TUNNEL_TYPE_TEREDO:
6933 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6938 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6946 /* Remove UDP tunneling port */
6948 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6949 struct rte_eth_udp_tunnel *udp_tunnel)
6952 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6954 if (hw->mac.type != ixgbe_mac_X550 &&
6955 hw->mac.type != ixgbe_mac_X550EM_x) {
6959 if (udp_tunnel == NULL)
6962 switch (udp_tunnel->prot_type) {
6963 case RTE_TUNNEL_TYPE_VXLAN:
6964 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
6966 case RTE_TUNNEL_TYPE_GENEVE:
6967 case RTE_TUNNEL_TYPE_TEREDO:
6968 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6972 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6980 /* ixgbevf_update_xcast_mode - Update Multicast mode
6981 * @hw: pointer to the HW structure
6982 * @netdev: pointer to net device structure
6983 * @xcast_mode: new multicast mode
6985 * Updates the Multicast Mode of VF.
6987 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
6990 struct ixgbe_mbx_info *mbx = &hw->mbx;
6994 switch (hw->api_version) {
6995 case ixgbe_mbox_api_12:
7001 msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7002 msgbuf[1] = xcast_mode;
7004 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7008 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7012 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7013 if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7020 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7022 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7024 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7028 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7030 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7032 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7035 static struct rte_driver rte_ixgbe_driver = {
7037 .init = rte_ixgbe_pmd_init,
7040 static struct rte_driver rte_ixgbevf_driver = {
7042 .init = rte_ixgbevf_pmd_init,
7045 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7046 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);