4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_hash_crc.h>
66 #include "ixgbe_logs.h"
67 #include "base/ixgbe_api.h"
68 #include "base/ixgbe_vf.h"
69 #include "base/ixgbe_common.h"
70 #include "ixgbe_ethdev.h"
71 #include "ixgbe_bypass.h"
72 #include "ixgbe_rxtx.h"
73 #include "base/ixgbe_type.h"
74 #include "base/ixgbe_phy.h"
75 #include "ixgbe_regs.h"
78 * High threshold controlling when to start sending XOFF frames. Must be at
79 * least 8 bytes less than receive packet buffer size. This value is in units
82 #define IXGBE_FC_HI 0x80
85 * Low threshold controlling when to start sending XON frames. This value is
86 * in units of 1024 bytes.
88 #define IXGBE_FC_LO 0x40
90 /* Default minimum inter-interrupt interval for EITR configuration */
91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
93 /* Timer value included in XOFF frames. */
94 #define IXGBE_FC_PAUSE 0x680
96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
97 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
98 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
100 #define IXGBE_MMW_SIZE_DEFAULT 0x4
101 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
102 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
105 * Default values for RX/TX configuration
107 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
108 #define IXGBE_DEFAULT_RX_PTHRESH 8
109 #define IXGBE_DEFAULT_RX_HTHRESH 8
110 #define IXGBE_DEFAULT_RX_WTHRESH 0
112 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
113 #define IXGBE_DEFAULT_TX_PTHRESH 32
114 #define IXGBE_DEFAULT_TX_HTHRESH 0
115 #define IXGBE_DEFAULT_TX_WTHRESH 0
116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
118 /* Bit shift and mask */
119 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
120 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
121 #define IXGBE_8_BIT_WIDTH CHAR_BIT
122 #define IXGBE_8_BIT_MASK UINT8_MAX
124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
128 #define IXGBE_HKEY_MAX_INDEX 10
130 /* Additional timesync values. */
131 #define NSEC_PER_SEC 1000000000L
132 #define IXGBE_INCVAL_10GB 0x66666666
133 #define IXGBE_INCVAL_1GB 0x40000000
134 #define IXGBE_INCVAL_100 0x50000000
135 #define IXGBE_INCVAL_SHIFT_10GB 28
136 #define IXGBE_INCVAL_SHIFT_1GB 24
137 #define IXGBE_INCVAL_SHIFT_100 21
138 #define IXGBE_INCVAL_SHIFT_82599 7
139 #define IXGBE_INCPER_SHIFT_82599 24
141 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
143 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
145 #define DEFAULT_ETAG_ETYPE 0x893f
146 #define IXGBE_ETAG_ETYPE 0x00005084
147 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
148 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
149 #define IXGBE_RAH_ADTYPE 0x40000000
150 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
151 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
154 #define IXGBE_QDE_STRIP_TAG 0x00000004
155 #define IXGBE_VTEICR_MASK 0x07
157 #define IXGBE_EXVET_VET_EXT_SHIFT 16
158 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
167 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
168 static int ixgbe_dev_start(struct rte_eth_dev *dev);
169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
171 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
178 int wait_to_complete);
179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
180 struct rte_eth_stats *stats);
181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
182 struct rte_eth_xstat *xstats, unsigned n);
183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
184 struct rte_eth_xstat *xstats, unsigned n);
186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
187 uint64_t *values, unsigned int n);
188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
190 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
191 struct rte_eth_xstat_name *xstats_names,
193 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
194 struct rte_eth_xstat_name *xstats_names, unsigned limit);
195 static int ixgbe_dev_xstats_get_names_by_id(
196 struct rte_eth_dev *dev,
197 struct rte_eth_xstat_name *xstats_names,
200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
207 struct rte_eth_dev_info *dev_info);
208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
210 struct rte_eth_dev_info *dev_info);
211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
214 uint16_t vlan_id, int on);
215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
216 enum rte_vlan_type vlan_type,
218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
219 uint16_t queue, bool on);
220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
231 struct rte_eth_fc_conf *fc_conf);
232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
233 struct rte_eth_fc_conf *fc_conf);
234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
235 struct rte_eth_pfc_conf *pfc_conf);
236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
237 struct rte_eth_rss_reta_entry64 *reta_conf,
239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
240 struct rte_eth_rss_reta_entry64 *reta_conf,
242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
248 struct rte_intr_handle *handle);
249 static void ixgbe_dev_interrupt_handler(void *param);
250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
252 uint32_t index, uint32_t pool);
253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
255 struct ether_addr *mac_addr);
256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
257 static bool is_device_supported(struct rte_eth_dev *dev,
258 struct rte_pci_driver *drv);
260 /* For Virtual Function support */
261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
263 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
264 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
265 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
266 int wait_to_complete);
267 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
268 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
269 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
270 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
271 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
272 struct rte_eth_stats *stats);
273 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
274 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
275 uint16_t vlan_id, int on);
276 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
277 uint16_t queue, int on);
278 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
279 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
280 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
282 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
284 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
285 uint8_t queue, uint8_t msix_vector);
286 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
287 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
288 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
290 /* For Eth VMDQ APIs support */
291 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
292 ether_addr * mac_addr, uint8_t on);
293 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
294 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
295 struct rte_eth_mirror_conf *mirror_conf,
296 uint8_t rule_id, uint8_t on);
297 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
299 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
301 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
303 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
304 uint8_t queue, uint8_t msix_vector);
305 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
307 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
308 uint16_t queue_idx, uint16_t tx_rate);
310 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
311 struct ether_addr *mac_addr,
312 uint32_t index, uint32_t pool);
313 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
314 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
315 struct ether_addr *mac_addr);
316 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
317 struct rte_eth_syn_filter *filter);
318 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
319 enum rte_filter_op filter_op,
321 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
322 struct ixgbe_5tuple_filter *filter);
323 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
324 struct ixgbe_5tuple_filter *filter);
325 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
326 enum rte_filter_op filter_op,
328 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
329 struct rte_eth_ntuple_filter *filter);
330 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
331 enum rte_filter_op filter_op,
333 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
334 struct rte_eth_ethertype_filter *filter);
335 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
336 enum rte_filter_type filter_type,
337 enum rte_filter_op filter_op,
339 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
341 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
342 struct ether_addr *mc_addr_set,
343 uint32_t nb_mc_addr);
344 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
345 struct rte_eth_dcb_info *dcb_info);
347 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
348 static int ixgbe_get_regs(struct rte_eth_dev *dev,
349 struct rte_dev_reg_info *regs);
350 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
351 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
352 struct rte_dev_eeprom_info *eeprom);
353 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
354 struct rte_dev_eeprom_info *eeprom);
356 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
357 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
358 struct rte_dev_reg_info *regs);
360 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
361 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
362 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
363 struct timespec *timestamp,
365 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
366 struct timespec *timestamp);
367 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
368 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
369 struct timespec *timestamp);
370 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
371 const struct timespec *timestamp);
372 static void ixgbevf_dev_interrupt_handler(void *param);
374 static int ixgbe_dev_l2_tunnel_eth_type_conf
375 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
376 static int ixgbe_dev_l2_tunnel_offload_set
377 (struct rte_eth_dev *dev,
378 struct rte_eth_l2_tunnel_conf *l2_tunnel,
381 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
382 enum rte_filter_op filter_op,
385 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
386 struct rte_eth_udp_tunnel *udp_tunnel);
387 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
388 struct rte_eth_udp_tunnel *udp_tunnel);
389 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
390 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
393 * Define VF Stats MACRO for Non "cleared on read" register
395 #define UPDATE_VF_STAT(reg, last, cur) \
397 uint32_t latest = IXGBE_READ_REG(hw, reg); \
398 cur += (latest - last) & UINT_MAX; \
402 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
404 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
405 u64 new_msb = IXGBE_READ_REG(hw, msb); \
406 u64 latest = ((new_msb << 32) | new_lsb); \
407 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
411 #define IXGBE_SET_HWSTRIP(h, q) do {\
412 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
413 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
414 (h)->bitmap[idx] |= 1 << bit;\
417 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
418 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
419 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
420 (h)->bitmap[idx] &= ~(1 << bit);\
423 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
424 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
425 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
426 (r) = (h)->bitmap[idx] >> bit & 1;\
430 * The set of PCI devices this driver supports
432 static const struct rte_pci_id pci_id_ixgbe_map[] = {
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
486 #ifdef RTE_LIBRTE_IXGBE_BYPASS
487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
489 { .vendor_id = 0, /* sentinel */ },
493 * The set of PCI devices this driver supports (for 82599 VF)
495 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
504 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
505 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
506 { .vendor_id = 0, /* sentinel */ },
509 static const struct rte_eth_desc_lim rx_desc_lim = {
510 .nb_max = IXGBE_MAX_RING_DESC,
511 .nb_min = IXGBE_MIN_RING_DESC,
512 .nb_align = IXGBE_RXD_ALIGN,
515 static const struct rte_eth_desc_lim tx_desc_lim = {
516 .nb_max = IXGBE_MAX_RING_DESC,
517 .nb_min = IXGBE_MIN_RING_DESC,
518 .nb_align = IXGBE_TXD_ALIGN,
519 .nb_seg_max = IXGBE_TX_MAX_SEG,
520 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
523 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
524 .dev_configure = ixgbe_dev_configure,
525 .dev_start = ixgbe_dev_start,
526 .dev_stop = ixgbe_dev_stop,
527 .dev_set_link_up = ixgbe_dev_set_link_up,
528 .dev_set_link_down = ixgbe_dev_set_link_down,
529 .dev_close = ixgbe_dev_close,
530 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
531 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
532 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
533 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
534 .link_update = ixgbe_dev_link_update,
535 .stats_get = ixgbe_dev_stats_get,
536 .xstats_get = ixgbe_dev_xstats_get,
537 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
538 .stats_reset = ixgbe_dev_stats_reset,
539 .xstats_reset = ixgbe_dev_xstats_reset,
540 .xstats_get_names = ixgbe_dev_xstats_get_names,
541 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
542 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
543 .fw_version_get = ixgbe_fw_version_get,
544 .dev_infos_get = ixgbe_dev_info_get,
545 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
546 .mtu_set = ixgbe_dev_mtu_set,
547 .vlan_filter_set = ixgbe_vlan_filter_set,
548 .vlan_tpid_set = ixgbe_vlan_tpid_set,
549 .vlan_offload_set = ixgbe_vlan_offload_set,
550 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
551 .rx_queue_start = ixgbe_dev_rx_queue_start,
552 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
553 .tx_queue_start = ixgbe_dev_tx_queue_start,
554 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
555 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
556 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
557 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
558 .rx_queue_release = ixgbe_dev_rx_queue_release,
559 .rx_queue_count = ixgbe_dev_rx_queue_count,
560 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
561 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
562 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
563 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
564 .tx_queue_release = ixgbe_dev_tx_queue_release,
565 .dev_led_on = ixgbe_dev_led_on,
566 .dev_led_off = ixgbe_dev_led_off,
567 .flow_ctrl_get = ixgbe_flow_ctrl_get,
568 .flow_ctrl_set = ixgbe_flow_ctrl_set,
569 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
570 .mac_addr_add = ixgbe_add_rar,
571 .mac_addr_remove = ixgbe_remove_rar,
572 .mac_addr_set = ixgbe_set_default_mac_addr,
573 .uc_hash_table_set = ixgbe_uc_hash_table_set,
574 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
575 .mirror_rule_set = ixgbe_mirror_rule_set,
576 .mirror_rule_reset = ixgbe_mirror_rule_reset,
577 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
578 .reta_update = ixgbe_dev_rss_reta_update,
579 .reta_query = ixgbe_dev_rss_reta_query,
580 .rss_hash_update = ixgbe_dev_rss_hash_update,
581 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
582 .filter_ctrl = ixgbe_dev_filter_ctrl,
583 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
584 .rxq_info_get = ixgbe_rxq_info_get,
585 .txq_info_get = ixgbe_txq_info_get,
586 .timesync_enable = ixgbe_timesync_enable,
587 .timesync_disable = ixgbe_timesync_disable,
588 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
589 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
590 .get_reg = ixgbe_get_regs,
591 .get_eeprom_length = ixgbe_get_eeprom_length,
592 .get_eeprom = ixgbe_get_eeprom,
593 .set_eeprom = ixgbe_set_eeprom,
594 .get_dcb_info = ixgbe_dev_get_dcb_info,
595 .timesync_adjust_time = ixgbe_timesync_adjust_time,
596 .timesync_read_time = ixgbe_timesync_read_time,
597 .timesync_write_time = ixgbe_timesync_write_time,
598 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
599 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
600 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
601 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
602 .tm_ops_get = ixgbe_tm_ops_get,
606 * dev_ops for virtual function, bare necessities for basic vf
607 * operation have been implemented
609 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
610 .dev_configure = ixgbevf_dev_configure,
611 .dev_start = ixgbevf_dev_start,
612 .dev_stop = ixgbevf_dev_stop,
613 .link_update = ixgbevf_dev_link_update,
614 .stats_get = ixgbevf_dev_stats_get,
615 .xstats_get = ixgbevf_dev_xstats_get,
616 .stats_reset = ixgbevf_dev_stats_reset,
617 .xstats_reset = ixgbevf_dev_stats_reset,
618 .xstats_get_names = ixgbevf_dev_xstats_get_names,
619 .dev_close = ixgbevf_dev_close,
620 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
621 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
622 .dev_infos_get = ixgbevf_dev_info_get,
623 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
624 .mtu_set = ixgbevf_dev_set_mtu,
625 .vlan_filter_set = ixgbevf_vlan_filter_set,
626 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
627 .vlan_offload_set = ixgbevf_vlan_offload_set,
628 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
629 .rx_queue_release = ixgbe_dev_rx_queue_release,
630 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
631 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
632 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
633 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
634 .tx_queue_release = ixgbe_dev_tx_queue_release,
635 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
636 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
637 .mac_addr_add = ixgbevf_add_mac_addr,
638 .mac_addr_remove = ixgbevf_remove_mac_addr,
639 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
640 .rxq_info_get = ixgbe_rxq_info_get,
641 .txq_info_get = ixgbe_txq_info_get,
642 .mac_addr_set = ixgbevf_set_default_mac_addr,
643 .get_reg = ixgbevf_get_regs,
644 .reta_update = ixgbe_dev_rss_reta_update,
645 .reta_query = ixgbe_dev_rss_reta_query,
646 .rss_hash_update = ixgbe_dev_rss_hash_update,
647 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
650 /* store statistics names and its offset in stats structure */
651 struct rte_ixgbe_xstats_name_off {
652 char name[RTE_ETH_XSTATS_NAME_SIZE];
656 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
657 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
658 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
659 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
660 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
661 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
662 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
663 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
664 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
665 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
666 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
667 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
668 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
669 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
670 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
671 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
673 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
675 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
676 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
677 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
678 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
679 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
680 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
681 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
682 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
683 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
684 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
685 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
686 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
687 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
688 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
689 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
690 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
691 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
693 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
695 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
696 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
697 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
698 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
700 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
702 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
704 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
706 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
708 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
710 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
713 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
714 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
715 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
717 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
718 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
719 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
720 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
721 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
723 {"rx_fcoe_no_direct_data_placement_ext_buff",
724 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
726 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
728 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
730 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
732 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
734 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
737 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
738 sizeof(rte_ixgbe_stats_strings[0]))
740 /* MACsec statistics */
741 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
742 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
744 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
745 out_pkts_encrypted)},
746 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
747 out_pkts_protected)},
748 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
749 out_octets_encrypted)},
750 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
751 out_octets_protected)},
752 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
754 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
756 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
758 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
759 in_pkts_unknownsci)},
760 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
761 in_octets_decrypted)},
762 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
763 in_octets_validated)},
764 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
766 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
768 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
770 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
772 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
776 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
778 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
779 in_pkts_notusingsa)},
782 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
783 sizeof(rte_ixgbe_macsec_strings[0]))
785 /* Per-queue statistics */
786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
787 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
788 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
789 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
790 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
793 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
794 sizeof(rte_ixgbe_rxq_strings[0]))
795 #define IXGBE_NB_RXQ_PRIO_VALUES 8
797 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
798 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
799 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
800 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
804 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
805 sizeof(rte_ixgbe_txq_strings[0]))
806 #define IXGBE_NB_TXQ_PRIO_VALUES 8
808 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
809 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
812 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
813 sizeof(rte_ixgbevf_stats_strings[0]))
816 * Atomically reads the link status information from global
817 * structure rte_eth_dev.
820 * - Pointer to the structure rte_eth_dev to read from.
821 * - Pointer to the buffer to be saved with the link status.
824 * - On success, zero.
825 * - On failure, negative value.
828 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
829 struct rte_eth_link *link)
831 struct rte_eth_link *dst = link;
832 struct rte_eth_link *src = &(dev->data->dev_link);
834 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
835 *(uint64_t *)src) == 0)
842 * Atomically writes the link status information into global
843 * structure rte_eth_dev.
846 * - Pointer to the structure rte_eth_dev to read from.
847 * - Pointer to the buffer to be saved with the link status.
850 * - On success, zero.
851 * - On failure, negative value.
854 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
855 struct rte_eth_link *link)
857 struct rte_eth_link *dst = &(dev->data->dev_link);
858 struct rte_eth_link *src = link;
860 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
861 *(uint64_t *)src) == 0)
868 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
871 ixgbe_is_sfp(struct ixgbe_hw *hw)
873 switch (hw->phy.type) {
874 case ixgbe_phy_sfp_avago:
875 case ixgbe_phy_sfp_ftl:
876 case ixgbe_phy_sfp_intel:
877 case ixgbe_phy_sfp_unknown:
878 case ixgbe_phy_sfp_passive_tyco:
879 case ixgbe_phy_sfp_passive_unknown:
886 static inline int32_t
887 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
892 status = ixgbe_reset_hw(hw);
894 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
895 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
896 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
897 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
898 IXGBE_WRITE_FLUSH(hw);
900 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
901 status = IXGBE_SUCCESS;
906 ixgbe_enable_intr(struct rte_eth_dev *dev)
908 struct ixgbe_interrupt *intr =
909 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
910 struct ixgbe_hw *hw =
911 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
913 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
914 IXGBE_WRITE_FLUSH(hw);
918 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
921 ixgbe_disable_intr(struct ixgbe_hw *hw)
923 PMD_INIT_FUNC_TRACE();
925 if (hw->mac.type == ixgbe_mac_82598EB) {
926 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
928 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
929 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
930 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
932 IXGBE_WRITE_FLUSH(hw);
936 * This function resets queue statistics mapping registers.
937 * From Niantic datasheet, Initialization of Statistics section:
938 * "...if software requires the queue counters, the RQSMR and TQSM registers
939 * must be re-programmed following a device reset.
942 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
946 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
947 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
948 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
954 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
959 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
960 #define NB_QMAP_FIELDS_PER_QSM_REG 4
961 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
963 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
964 struct ixgbe_stat_mapping_registers *stat_mappings =
965 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
966 uint32_t qsmr_mask = 0;
967 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
971 if ((hw->mac.type != ixgbe_mac_82599EB) &&
972 (hw->mac.type != ixgbe_mac_X540) &&
973 (hw->mac.type != ixgbe_mac_X550) &&
974 (hw->mac.type != ixgbe_mac_X550EM_x) &&
975 (hw->mac.type != ixgbe_mac_X550EM_a))
978 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
979 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
982 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
983 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
984 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
987 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
989 /* Now clear any previous stat_idx set */
990 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
992 stat_mappings->tqsm[n] &= ~clearing_mask;
994 stat_mappings->rqsmr[n] &= ~clearing_mask;
996 q_map = (uint32_t)stat_idx;
997 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
998 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1000 stat_mappings->tqsm[n] |= qsmr_mask;
1002 stat_mappings->rqsmr[n] |= qsmr_mask;
1004 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1005 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1006 queue_id, stat_idx);
1007 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1008 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1010 /* Now write the mapping in the appropriate register */
1012 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1013 stat_mappings->rqsmr[n], n);
1014 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1016 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1017 stat_mappings->tqsm[n], n);
1018 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1024 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1026 struct ixgbe_stat_mapping_registers *stat_mappings =
1027 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1028 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1031 /* write whatever was in stat mapping table to the NIC */
1032 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1034 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1037 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1042 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1045 struct ixgbe_dcb_tc_config *tc;
1046 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1048 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1049 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1050 for (i = 0; i < dcb_max_tc; i++) {
1051 tc = &dcb_config->tc_config[i];
1052 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1053 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1054 (uint8_t)(100/dcb_max_tc + (i & 1));
1055 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1056 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1057 (uint8_t)(100/dcb_max_tc + (i & 1));
1058 tc->pfc = ixgbe_dcb_pfc_disabled;
1061 /* Initialize default user to priority mapping, UPx->TC0 */
1062 tc = &dcb_config->tc_config[0];
1063 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1064 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1065 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1066 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1067 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1069 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1070 dcb_config->pfc_mode_enable = false;
1071 dcb_config->vt_mode = true;
1072 dcb_config->round_robin_enable = false;
1073 /* support all DCB capabilities in 82599 */
1074 dcb_config->support.capabilities = 0xFF;
1076 /*we only support 4 Tcs for X540, X550 */
1077 if (hw->mac.type == ixgbe_mac_X540 ||
1078 hw->mac.type == ixgbe_mac_X550 ||
1079 hw->mac.type == ixgbe_mac_X550EM_x ||
1080 hw->mac.type == ixgbe_mac_X550EM_a) {
1081 dcb_config->num_tcs.pg_tcs = 4;
1082 dcb_config->num_tcs.pfc_tcs = 4;
1087 * Ensure that all locks are released before first NVM or PHY access
1090 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1095 * Phy lock should not fail in this early stage. If this is the case,
1096 * it is due to an improper exit of the application.
1097 * So force the release of the faulty lock. Release of common lock
1098 * is done automatically by swfw_sync function.
1100 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1101 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1102 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1104 ixgbe_release_swfw_semaphore(hw, mask);
1107 * These ones are more tricky since they are common to all ports; but
1108 * swfw_sync retries last long enough (1s) to be almost sure that if
1109 * lock can not be taken it is due to an improper lock of the
1112 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1113 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1114 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1116 ixgbe_release_swfw_semaphore(hw, mask);
1120 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1121 * It returns 0 on success.
1124 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1126 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1127 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1128 struct ixgbe_hw *hw =
1129 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1130 struct ixgbe_vfta *shadow_vfta =
1131 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1132 struct ixgbe_hwstrip *hwstrip =
1133 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1134 struct ixgbe_dcb_config *dcb_config =
1135 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1136 struct ixgbe_filter_info *filter_info =
1137 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1138 struct ixgbe_bw_conf *bw_conf =
1139 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1144 PMD_INIT_FUNC_TRACE();
1146 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1147 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1148 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1149 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1152 * For secondary processes, we don't initialise any further as primary
1153 * has already done this work. Only check we don't need a different
1154 * RX and TX function.
1156 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1157 struct ixgbe_tx_queue *txq;
1158 /* TX queue function in primary, set by last queue initialized
1159 * Tx queue may not initialized by primary process
1161 if (eth_dev->data->tx_queues) {
1162 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1163 ixgbe_set_tx_function(eth_dev, txq);
1165 /* Use default TX function if we get here */
1166 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1167 "Using default TX function.");
1170 ixgbe_set_rx_function(eth_dev);
1175 rte_eth_copy_pci_info(eth_dev, pci_dev);
1176 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1178 /* Vendor and Device ID need to be set before init of shared code */
1179 hw->device_id = pci_dev->id.device_id;
1180 hw->vendor_id = pci_dev->id.vendor_id;
1181 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1182 hw->allow_unsupported_sfp = 1;
1184 /* Initialize the shared code (base driver) */
1185 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1186 diag = ixgbe_bypass_init_shared_code(hw);
1188 diag = ixgbe_init_shared_code(hw);
1189 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1191 if (diag != IXGBE_SUCCESS) {
1192 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1196 /* pick up the PCI bus settings for reporting later */
1197 ixgbe_get_bus_info(hw);
1199 /* Unlock any pending hardware semaphore */
1200 ixgbe_swfw_lock_reset(hw);
1202 /* Initialize DCB configuration*/
1203 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1204 ixgbe_dcb_init(hw, dcb_config);
1205 /* Get Hardware Flow Control setting */
1206 hw->fc.requested_mode = ixgbe_fc_full;
1207 hw->fc.current_mode = ixgbe_fc_full;
1208 hw->fc.pause_time = IXGBE_FC_PAUSE;
1209 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1210 hw->fc.low_water[i] = IXGBE_FC_LO;
1211 hw->fc.high_water[i] = IXGBE_FC_HI;
1213 hw->fc.send_xon = 1;
1215 /* Make sure we have a good EEPROM before we read from it */
1216 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1217 if (diag != IXGBE_SUCCESS) {
1218 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1222 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1223 diag = ixgbe_bypass_init_hw(hw);
1225 diag = ixgbe_init_hw(hw);
1226 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1229 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1230 * is called too soon after the kernel driver unbinding/binding occurs.
1231 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1232 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1233 * also called. See ixgbe_identify_phy_82599(). The reason for the
1234 * failure is not known, and only occuts when virtualisation features
1235 * are disabled in the bios. A delay of 100ms was found to be enough by
1236 * trial-and-error, and is doubled to be safe.
1238 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1240 diag = ixgbe_init_hw(hw);
1243 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1244 diag = IXGBE_SUCCESS;
1246 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1247 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1248 "LOM. Please be aware there may be issues associated "
1249 "with your hardware.");
1250 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1251 "please contact your Intel or hardware representative "
1252 "who provided you with this hardware.");
1253 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1254 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1256 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1260 /* Reset the hw statistics */
1261 ixgbe_dev_stats_reset(eth_dev);
1263 /* disable interrupt */
1264 ixgbe_disable_intr(hw);
1266 /* reset mappings for queue statistics hw counters*/
1267 ixgbe_reset_qstat_mappings(hw);
1269 /* Allocate memory for storing MAC addresses */
1270 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1271 hw->mac.num_rar_entries, 0);
1272 if (eth_dev->data->mac_addrs == NULL) {
1274 "Failed to allocate %u bytes needed to store "
1276 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1279 /* Copy the permanent MAC address */
1280 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1281 ð_dev->data->mac_addrs[0]);
1283 /* Allocate memory for storing hash filter MAC addresses */
1284 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1285 IXGBE_VMDQ_NUM_UC_MAC, 0);
1286 if (eth_dev->data->hash_mac_addrs == NULL) {
1288 "Failed to allocate %d bytes needed to store MAC addresses",
1289 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1293 /* initialize the vfta */
1294 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1296 /* initialize the hw strip bitmap*/
1297 memset(hwstrip, 0, sizeof(*hwstrip));
1299 /* initialize PF if max_vfs not zero */
1300 ixgbe_pf_host_init(eth_dev);
1302 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1303 /* let hardware know driver is loaded */
1304 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1305 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1306 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1307 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1308 IXGBE_WRITE_FLUSH(hw);
1310 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1311 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1312 (int) hw->mac.type, (int) hw->phy.type,
1313 (int) hw->phy.sfp_type);
1315 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1316 (int) hw->mac.type, (int) hw->phy.type);
1318 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1319 eth_dev->data->port_id, pci_dev->id.vendor_id,
1320 pci_dev->id.device_id);
1322 rte_intr_callback_register(intr_handle,
1323 ixgbe_dev_interrupt_handler, eth_dev);
1325 /* enable uio/vfio intr/eventfd mapping */
1326 rte_intr_enable(intr_handle);
1328 /* enable support intr */
1329 ixgbe_enable_intr(eth_dev);
1331 /* initialize filter info */
1332 memset(filter_info, 0,
1333 sizeof(struct ixgbe_filter_info));
1335 /* initialize 5tuple filter list */
1336 TAILQ_INIT(&filter_info->fivetuple_list);
1338 /* initialize flow director filter list & hash */
1339 ixgbe_fdir_filter_init(eth_dev);
1341 /* initialize l2 tunnel filter list & hash */
1342 ixgbe_l2_tn_filter_init(eth_dev);
1344 TAILQ_INIT(&filter_ntuple_list);
1345 TAILQ_INIT(&filter_ethertype_list);
1346 TAILQ_INIT(&filter_syn_list);
1347 TAILQ_INIT(&filter_fdir_list);
1348 TAILQ_INIT(&filter_l2_tunnel_list);
1349 TAILQ_INIT(&ixgbe_flow_list);
1351 /* initialize bandwidth configuration info */
1352 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1354 /* initialize Traffic Manager configuration */
1355 ixgbe_tm_conf_init(eth_dev);
1361 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1363 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1364 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1365 struct ixgbe_hw *hw;
1367 PMD_INIT_FUNC_TRACE();
1369 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1372 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1374 if (hw->adapter_stopped == 0)
1375 ixgbe_dev_close(eth_dev);
1377 eth_dev->dev_ops = NULL;
1378 eth_dev->rx_pkt_burst = NULL;
1379 eth_dev->tx_pkt_burst = NULL;
1381 /* Unlock any pending hardware semaphore */
1382 ixgbe_swfw_lock_reset(hw);
1384 /* disable uio intr before callback unregister */
1385 rte_intr_disable(intr_handle);
1386 rte_intr_callback_unregister(intr_handle,
1387 ixgbe_dev_interrupt_handler, eth_dev);
1389 /* uninitialize PF if max_vfs not zero */
1390 ixgbe_pf_host_uninit(eth_dev);
1392 rte_free(eth_dev->data->mac_addrs);
1393 eth_dev->data->mac_addrs = NULL;
1395 rte_free(eth_dev->data->hash_mac_addrs);
1396 eth_dev->data->hash_mac_addrs = NULL;
1398 /* remove all the fdir filters & hash */
1399 ixgbe_fdir_filter_uninit(eth_dev);
1401 /* remove all the L2 tunnel filters & hash */
1402 ixgbe_l2_tn_filter_uninit(eth_dev);
1404 /* Remove all ntuple filters of the device */
1405 ixgbe_ntuple_filter_uninit(eth_dev);
1407 /* clear all the filters list */
1408 ixgbe_filterlist_flush();
1410 /* Remove all Traffic Manager configuration */
1411 ixgbe_tm_conf_uninit(eth_dev);
1416 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1418 struct ixgbe_filter_info *filter_info =
1419 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1420 struct ixgbe_5tuple_filter *p_5tuple;
1422 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1423 TAILQ_REMOVE(&filter_info->fivetuple_list,
1428 memset(filter_info->fivetuple_mask, 0,
1429 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1434 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1436 struct ixgbe_hw_fdir_info *fdir_info =
1437 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1438 struct ixgbe_fdir_filter *fdir_filter;
1440 if (fdir_info->hash_map)
1441 rte_free(fdir_info->hash_map);
1442 if (fdir_info->hash_handle)
1443 rte_hash_free(fdir_info->hash_handle);
1445 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1446 TAILQ_REMOVE(&fdir_info->fdir_list,
1449 rte_free(fdir_filter);
1455 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1457 struct ixgbe_l2_tn_info *l2_tn_info =
1458 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1459 struct ixgbe_l2_tn_filter *l2_tn_filter;
1461 if (l2_tn_info->hash_map)
1462 rte_free(l2_tn_info->hash_map);
1463 if (l2_tn_info->hash_handle)
1464 rte_hash_free(l2_tn_info->hash_handle);
1466 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1467 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1470 rte_free(l2_tn_filter);
1476 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1478 struct ixgbe_hw_fdir_info *fdir_info =
1479 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1480 char fdir_hash_name[RTE_HASH_NAMESIZE];
1481 struct rte_hash_parameters fdir_hash_params = {
1482 .name = fdir_hash_name,
1483 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1484 .key_len = sizeof(union ixgbe_atr_input),
1485 .hash_func = rte_hash_crc,
1486 .hash_func_init_val = 0,
1487 .socket_id = rte_socket_id(),
1490 TAILQ_INIT(&fdir_info->fdir_list);
1491 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1492 "fdir_%s", eth_dev->device->name);
1493 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1494 if (!fdir_info->hash_handle) {
1495 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1498 fdir_info->hash_map = rte_zmalloc("ixgbe",
1499 sizeof(struct ixgbe_fdir_filter *) *
1500 IXGBE_MAX_FDIR_FILTER_NUM,
1502 if (!fdir_info->hash_map) {
1504 "Failed to allocate memory for fdir hash map!");
1507 fdir_info->mask_added = FALSE;
1512 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1514 struct ixgbe_l2_tn_info *l2_tn_info =
1515 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1516 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1517 struct rte_hash_parameters l2_tn_hash_params = {
1518 .name = l2_tn_hash_name,
1519 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1520 .key_len = sizeof(struct ixgbe_l2_tn_key),
1521 .hash_func = rte_hash_crc,
1522 .hash_func_init_val = 0,
1523 .socket_id = rte_socket_id(),
1526 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1527 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1528 "l2_tn_%s", eth_dev->device->name);
1529 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1530 if (!l2_tn_info->hash_handle) {
1531 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1534 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1535 sizeof(struct ixgbe_l2_tn_filter *) *
1536 IXGBE_MAX_L2_TN_FILTER_NUM,
1538 if (!l2_tn_info->hash_map) {
1540 "Failed to allocate memory for L2 TN hash map!");
1543 l2_tn_info->e_tag_en = FALSE;
1544 l2_tn_info->e_tag_fwd_en = FALSE;
1545 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1550 * Negotiate mailbox API version with the PF.
1551 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1552 * Then we try to negotiate starting with the most recent one.
1553 * If all negotiation attempts fail, then we will proceed with
1554 * the default one (ixgbe_mbox_api_10).
1557 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1561 /* start with highest supported, proceed down */
1562 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1569 i != RTE_DIM(sup_ver) &&
1570 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1576 generate_random_mac_addr(struct ether_addr *mac_addr)
1580 /* Set Organizationally Unique Identifier (OUI) prefix. */
1581 mac_addr->addr_bytes[0] = 0x00;
1582 mac_addr->addr_bytes[1] = 0x09;
1583 mac_addr->addr_bytes[2] = 0xC0;
1584 /* Force indication of locally assigned MAC address. */
1585 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1586 /* Generate the last 3 bytes of the MAC address with a random number. */
1587 random = rte_rand();
1588 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1592 * Virtual Function device init
1595 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1599 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1600 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1601 struct ixgbe_hw *hw =
1602 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1603 struct ixgbe_vfta *shadow_vfta =
1604 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1605 struct ixgbe_hwstrip *hwstrip =
1606 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1607 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1609 PMD_INIT_FUNC_TRACE();
1611 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1612 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1613 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1615 /* for secondary processes, we don't initialise any further as primary
1616 * has already done this work. Only check we don't need a different
1619 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1620 struct ixgbe_tx_queue *txq;
1621 /* TX queue function in primary, set by last queue initialized
1622 * Tx queue may not initialized by primary process
1624 if (eth_dev->data->tx_queues) {
1625 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1626 ixgbe_set_tx_function(eth_dev, txq);
1628 /* Use default TX function if we get here */
1629 PMD_INIT_LOG(NOTICE,
1630 "No TX queues configured yet. Using default TX function.");
1633 ixgbe_set_rx_function(eth_dev);
1638 rte_eth_copy_pci_info(eth_dev, pci_dev);
1639 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1641 hw->device_id = pci_dev->id.device_id;
1642 hw->vendor_id = pci_dev->id.vendor_id;
1643 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1645 /* initialize the vfta */
1646 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1648 /* initialize the hw strip bitmap*/
1649 memset(hwstrip, 0, sizeof(*hwstrip));
1651 /* Initialize the shared code (base driver) */
1652 diag = ixgbe_init_shared_code(hw);
1653 if (diag != IXGBE_SUCCESS) {
1654 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1658 /* init_mailbox_params */
1659 hw->mbx.ops.init_params(hw);
1661 /* Reset the hw statistics */
1662 ixgbevf_dev_stats_reset(eth_dev);
1664 /* Disable the interrupts for VF */
1665 ixgbevf_intr_disable(hw);
1667 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1668 diag = hw->mac.ops.reset_hw(hw);
1671 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1672 * the underlying PF driver has not assigned a MAC address to the VF.
1673 * In this case, assign a random MAC address.
1675 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1676 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1680 /* negotiate mailbox API version to use with the PF. */
1681 ixgbevf_negotiate_api(hw);
1683 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1684 ixgbevf_get_queues(hw, &tcs, &tc);
1686 /* Allocate memory for storing MAC addresses */
1687 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1688 hw->mac.num_rar_entries, 0);
1689 if (eth_dev->data->mac_addrs == NULL) {
1691 "Failed to allocate %u bytes needed to store "
1693 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1697 /* Generate a random MAC address, if none was assigned by PF. */
1698 if (is_zero_ether_addr(perm_addr)) {
1699 generate_random_mac_addr(perm_addr);
1700 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1702 rte_free(eth_dev->data->mac_addrs);
1703 eth_dev->data->mac_addrs = NULL;
1706 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1707 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1708 "%02x:%02x:%02x:%02x:%02x:%02x",
1709 perm_addr->addr_bytes[0],
1710 perm_addr->addr_bytes[1],
1711 perm_addr->addr_bytes[2],
1712 perm_addr->addr_bytes[3],
1713 perm_addr->addr_bytes[4],
1714 perm_addr->addr_bytes[5]);
1717 /* Copy the permanent MAC address */
1718 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1720 /* reset the hardware with the new settings */
1721 diag = hw->mac.ops.start_hw(hw);
1727 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1731 rte_intr_callback_register(intr_handle,
1732 ixgbevf_dev_interrupt_handler, eth_dev);
1733 rte_intr_enable(intr_handle);
1734 ixgbevf_intr_enable(hw);
1736 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1737 eth_dev->data->port_id, pci_dev->id.vendor_id,
1738 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1743 /* Virtual Function device uninit */
1746 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1748 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1749 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1750 struct ixgbe_hw *hw;
1752 PMD_INIT_FUNC_TRACE();
1754 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1757 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1759 if (hw->adapter_stopped == 0)
1760 ixgbevf_dev_close(eth_dev);
1762 eth_dev->dev_ops = NULL;
1763 eth_dev->rx_pkt_burst = NULL;
1764 eth_dev->tx_pkt_burst = NULL;
1766 /* Disable the interrupts for VF */
1767 ixgbevf_intr_disable(hw);
1769 rte_free(eth_dev->data->mac_addrs);
1770 eth_dev->data->mac_addrs = NULL;
1772 rte_intr_disable(intr_handle);
1773 rte_intr_callback_unregister(intr_handle,
1774 ixgbevf_dev_interrupt_handler, eth_dev);
1779 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1780 struct rte_pci_device *pci_dev)
1782 return rte_eth_dev_pci_generic_probe(pci_dev,
1783 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1786 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1788 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1791 static struct rte_pci_driver rte_ixgbe_pmd = {
1792 .id_table = pci_id_ixgbe_map,
1793 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1794 .probe = eth_ixgbe_pci_probe,
1795 .remove = eth_ixgbe_pci_remove,
1798 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1799 struct rte_pci_device *pci_dev)
1801 return rte_eth_dev_pci_generic_probe(pci_dev,
1802 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1805 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1807 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1811 * virtual function driver struct
1813 static struct rte_pci_driver rte_ixgbevf_pmd = {
1814 .id_table = pci_id_ixgbevf_map,
1815 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1816 .probe = eth_ixgbevf_pci_probe,
1817 .remove = eth_ixgbevf_pci_remove,
1821 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1823 struct ixgbe_hw *hw =
1824 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825 struct ixgbe_vfta *shadow_vfta =
1826 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1831 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1832 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1833 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1838 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1840 /* update local VFTA copy */
1841 shadow_vfta->vfta[vid_idx] = vfta;
1847 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1850 ixgbe_vlan_hw_strip_enable(dev, queue);
1852 ixgbe_vlan_hw_strip_disable(dev, queue);
1856 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1857 enum rte_vlan_type vlan_type,
1860 struct ixgbe_hw *hw =
1861 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1866 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867 qinq &= IXGBE_DMATXCTL_GDV;
1869 switch (vlan_type) {
1870 case ETH_VLAN_TYPE_INNER:
1872 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1873 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1874 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1875 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1876 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1877 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1878 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1881 PMD_DRV_LOG(ERR, "Inner type is not supported"
1885 case ETH_VLAN_TYPE_OUTER:
1887 /* Only the high 16-bits is valid */
1888 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1889 IXGBE_EXVET_VET_EXT_SHIFT);
1891 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1892 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1893 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1894 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1895 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1896 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1897 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1903 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1911 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1913 struct ixgbe_hw *hw =
1914 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917 PMD_INIT_FUNC_TRACE();
1919 /* Filter Table Disable */
1920 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1921 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1923 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1927 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1929 struct ixgbe_hw *hw =
1930 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1931 struct ixgbe_vfta *shadow_vfta =
1932 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1936 PMD_INIT_FUNC_TRACE();
1938 /* Filter Table Enable */
1939 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1940 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1941 vlnctrl |= IXGBE_VLNCTRL_VFE;
1943 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1945 /* write whatever is in local vfta copy */
1946 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1947 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1951 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1953 struct ixgbe_hwstrip *hwstrip =
1954 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1955 struct ixgbe_rx_queue *rxq;
1957 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1961 IXGBE_SET_HWSTRIP(hwstrip, queue);
1963 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1965 if (queue >= dev->data->nb_rx_queues)
1968 rxq = dev->data->rx_queues[queue];
1971 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1973 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1977 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1979 struct ixgbe_hw *hw =
1980 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983 PMD_INIT_FUNC_TRACE();
1985 if (hw->mac.type == ixgbe_mac_82598EB) {
1986 /* No queue level support */
1987 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1991 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1992 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1993 ctrl &= ~IXGBE_RXDCTL_VME;
1994 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1996 /* record those setting for HW strip per queue */
1997 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2001 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2003 struct ixgbe_hw *hw =
2004 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2007 PMD_INIT_FUNC_TRACE();
2009 if (hw->mac.type == ixgbe_mac_82598EB) {
2010 /* No queue level supported */
2011 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2015 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2016 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2017 ctrl |= IXGBE_RXDCTL_VME;
2018 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2020 /* record those setting for HW strip per queue */
2021 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2025 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2027 struct ixgbe_hw *hw =
2028 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031 struct ixgbe_rx_queue *rxq;
2033 PMD_INIT_FUNC_TRACE();
2035 if (hw->mac.type == ixgbe_mac_82598EB) {
2036 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2037 ctrl &= ~IXGBE_VLNCTRL_VME;
2038 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2040 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2041 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2042 rxq = dev->data->rx_queues[i];
2043 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2044 ctrl &= ~IXGBE_RXDCTL_VME;
2045 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2047 /* record those setting for HW strip per queue */
2048 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2054 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2056 struct ixgbe_hw *hw =
2057 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060 struct ixgbe_rx_queue *rxq;
2062 PMD_INIT_FUNC_TRACE();
2064 if (hw->mac.type == ixgbe_mac_82598EB) {
2065 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2066 ctrl |= IXGBE_VLNCTRL_VME;
2067 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2069 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2070 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2071 rxq = dev->data->rx_queues[i];
2072 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2073 ctrl |= IXGBE_RXDCTL_VME;
2074 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2076 /* record those setting for HW strip per queue */
2077 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2083 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2085 struct ixgbe_hw *hw =
2086 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089 PMD_INIT_FUNC_TRACE();
2091 /* DMATXCTRL: Geric Double VLAN Disable */
2092 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2093 ctrl &= ~IXGBE_DMATXCTL_GDV;
2094 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2096 /* CTRL_EXT: Global Double VLAN Disable */
2097 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2098 ctrl &= ~IXGBE_EXTENDED_VLAN;
2099 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2104 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2106 struct ixgbe_hw *hw =
2107 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110 PMD_INIT_FUNC_TRACE();
2112 /* DMATXCTRL: Geric Double VLAN Enable */
2113 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2114 ctrl |= IXGBE_DMATXCTL_GDV;
2115 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2117 /* CTRL_EXT: Global Double VLAN Enable */
2118 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2119 ctrl |= IXGBE_EXTENDED_VLAN;
2120 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2122 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2123 if (hw->mac.type == ixgbe_mac_X550 ||
2124 hw->mac.type == ixgbe_mac_X550EM_x ||
2125 hw->mac.type == ixgbe_mac_X550EM_a) {
2126 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2127 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2128 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2132 * VET EXT field in the EXVET register = 0x8100 by default
2133 * So no need to change. Same to VT field of DMATXCTL register
2138 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2140 if (mask & ETH_VLAN_STRIP_MASK) {
2141 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2142 ixgbe_vlan_hw_strip_enable_all(dev);
2144 ixgbe_vlan_hw_strip_disable_all(dev);
2147 if (mask & ETH_VLAN_FILTER_MASK) {
2148 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2149 ixgbe_vlan_hw_filter_enable(dev);
2151 ixgbe_vlan_hw_filter_disable(dev);
2154 if (mask & ETH_VLAN_EXTEND_MASK) {
2155 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2156 ixgbe_vlan_hw_extend_enable(dev);
2158 ixgbe_vlan_hw_extend_disable(dev);
2163 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2165 struct ixgbe_hw *hw =
2166 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2168 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2170 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2171 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2175 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2177 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2182 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2185 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2191 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2192 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2198 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2200 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2201 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2203 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2205 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2206 /* check multi-queue mode */
2207 switch (dev_conf->rxmode.mq_mode) {
2208 case ETH_MQ_RX_VMDQ_DCB:
2209 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2211 case ETH_MQ_RX_VMDQ_DCB_RSS:
2212 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2213 PMD_INIT_LOG(ERR, "SRIOV active,"
2214 " unsupported mq_mode rx %d.",
2215 dev_conf->rxmode.mq_mode);
2218 case ETH_MQ_RX_VMDQ_RSS:
2219 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2220 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2221 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2222 PMD_INIT_LOG(ERR, "SRIOV is active,"
2223 " invalid queue number"
2224 " for VMDQ RSS, allowed"
2225 " value are 1, 2 or 4.");
2229 case ETH_MQ_RX_VMDQ_ONLY:
2230 case ETH_MQ_RX_NONE:
2231 /* if nothing mq mode configure, use default scheme */
2232 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2233 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2234 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2236 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2237 /* SRIOV only works in VMDq enable mode */
2238 PMD_INIT_LOG(ERR, "SRIOV is active,"
2239 " wrong mq_mode rx %d.",
2240 dev_conf->rxmode.mq_mode);
2244 switch (dev_conf->txmode.mq_mode) {
2245 case ETH_MQ_TX_VMDQ_DCB:
2246 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2247 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2249 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2250 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2254 /* check valid queue number */
2255 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2256 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2257 PMD_INIT_LOG(ERR, "SRIOV is active,"
2258 " nb_rx_q=%d nb_tx_q=%d queue number"
2259 " must be less than or equal to %d.",
2261 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2265 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2266 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2270 /* check configuration for vmdb+dcb mode */
2271 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2272 const struct rte_eth_vmdq_dcb_conf *conf;
2274 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2275 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2276 IXGBE_VMDQ_DCB_NB_QUEUES);
2279 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2280 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2281 conf->nb_queue_pools == ETH_32_POOLS)) {
2282 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2283 " nb_queue_pools must be %d or %d.",
2284 ETH_16_POOLS, ETH_32_POOLS);
2288 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2289 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2291 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2292 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2293 IXGBE_VMDQ_DCB_NB_QUEUES);
2296 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2297 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2298 conf->nb_queue_pools == ETH_32_POOLS)) {
2299 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2300 " nb_queue_pools != %d and"
2301 " nb_queue_pools != %d.",
2302 ETH_16_POOLS, ETH_32_POOLS);
2307 /* For DCB mode check our configuration before we go further */
2308 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2309 const struct rte_eth_dcb_rx_conf *conf;
2311 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2312 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2313 IXGBE_DCB_NB_QUEUES);
2316 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2317 if (!(conf->nb_tcs == ETH_4_TCS ||
2318 conf->nb_tcs == ETH_8_TCS)) {
2319 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2320 " and nb_tcs != %d.",
2321 ETH_4_TCS, ETH_8_TCS);
2326 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2327 const struct rte_eth_dcb_tx_conf *conf;
2329 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2330 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2331 IXGBE_DCB_NB_QUEUES);
2334 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2335 if (!(conf->nb_tcs == ETH_4_TCS ||
2336 conf->nb_tcs == ETH_8_TCS)) {
2337 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2338 " and nb_tcs != %d.",
2339 ETH_4_TCS, ETH_8_TCS);
2345 * When DCB/VT is off, maximum number of queues changes,
2346 * except for 82598EB, which remains constant.
2348 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2349 hw->mac.type != ixgbe_mac_82598EB) {
2350 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2352 "Neither VT nor DCB are enabled, "
2354 IXGBE_NONE_MODE_TX_NB_QUEUES);
2363 ixgbe_dev_configure(struct rte_eth_dev *dev)
2365 struct ixgbe_interrupt *intr =
2366 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2367 struct ixgbe_adapter *adapter =
2368 (struct ixgbe_adapter *)dev->data->dev_private;
2371 PMD_INIT_FUNC_TRACE();
2372 /* multipe queue mode checking */
2373 ret = ixgbe_check_mq_mode(dev);
2375 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2380 /* set flag to update link status after init */
2381 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2384 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2385 * allocation or vector Rx preconditions we will reset it.
2387 adapter->rx_bulk_alloc_allowed = true;
2388 adapter->rx_vec_allowed = true;
2394 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2396 struct ixgbe_hw *hw =
2397 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398 struct ixgbe_interrupt *intr =
2399 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2402 /* only set up it on X550EM_X */
2403 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2404 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2405 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2406 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2407 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2408 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2413 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2414 uint16_t tx_rate, uint64_t q_msk)
2416 struct ixgbe_hw *hw;
2417 struct ixgbe_vf_info *vfinfo;
2418 struct rte_eth_link link;
2419 uint8_t nb_q_per_pool;
2420 uint32_t queue_stride;
2421 uint32_t queue_idx, idx = 0, vf_idx;
2423 uint16_t total_rate = 0;
2424 struct rte_pci_device *pci_dev;
2426 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2427 rte_eth_link_get_nowait(dev->data->port_id, &link);
2429 if (vf >= pci_dev->max_vfs)
2432 if (tx_rate > link.link_speed)
2438 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2440 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2441 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2442 queue_idx = vf * queue_stride;
2443 queue_end = queue_idx + nb_q_per_pool - 1;
2444 if (queue_end >= hw->mac.max_tx_queues)
2448 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2451 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2453 total_rate += vfinfo[vf_idx].tx_rate[idx];
2459 /* Store tx_rate for this vf. */
2460 for (idx = 0; idx < nb_q_per_pool; idx++) {
2461 if (((uint64_t)0x1 << idx) & q_msk) {
2462 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2463 vfinfo[vf].tx_rate[idx] = tx_rate;
2464 total_rate += tx_rate;
2468 if (total_rate > dev->data->dev_link.link_speed) {
2469 /* Reset stored TX rate of the VF if it causes exceed
2472 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2476 /* Set RTTBCNRC of each queue/pool for vf X */
2477 for (; queue_idx <= queue_end; queue_idx++) {
2479 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2487 * Configure device link speed and setup link.
2488 * It returns 0 on success.
2491 ixgbe_dev_start(struct rte_eth_dev *dev)
2493 struct ixgbe_hw *hw =
2494 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2495 struct ixgbe_vf_info *vfinfo =
2496 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2497 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2498 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2499 uint32_t intr_vector = 0;
2500 int err, link_up = 0, negotiate = 0;
2505 uint32_t *link_speeds;
2507 PMD_INIT_FUNC_TRACE();
2509 /* IXGBE devices don't support:
2510 * - half duplex (checked afterwards for valid speeds)
2511 * - fixed speed: TODO implement
2513 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2514 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2515 dev->data->port_id);
2519 /* disable uio/vfio intr/eventfd mapping */
2520 rte_intr_disable(intr_handle);
2523 hw->adapter_stopped = 0;
2524 ixgbe_stop_adapter(hw);
2526 /* reinitialize adapter
2527 * this calls reset and start
2529 status = ixgbe_pf_reset_hw(hw);
2532 hw->mac.ops.start_hw(hw);
2533 hw->mac.get_link_status = true;
2535 /* configure PF module if SRIOV enabled */
2536 ixgbe_pf_host_configure(dev);
2538 ixgbe_dev_phy_intr_setup(dev);
2540 /* check and configure queue intr-vector mapping */
2541 if ((rte_intr_cap_multiple(intr_handle) ||
2542 !RTE_ETH_DEV_SRIOV(dev).active) &&
2543 dev->data->dev_conf.intr_conf.rxq != 0) {
2544 intr_vector = dev->data->nb_rx_queues;
2545 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2546 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2547 IXGBE_MAX_INTR_QUEUE_NUM);
2550 if (rte_intr_efd_enable(intr_handle, intr_vector))
2554 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2555 intr_handle->intr_vec =
2556 rte_zmalloc("intr_vec",
2557 dev->data->nb_rx_queues * sizeof(int), 0);
2558 if (intr_handle->intr_vec == NULL) {
2559 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2560 " intr_vec", dev->data->nb_rx_queues);
2565 /* confiugre msix for sleep until rx interrupt */
2566 ixgbe_configure_msix(dev);
2568 /* initialize transmission unit */
2569 ixgbe_dev_tx_init(dev);
2571 /* This can fail when allocating mbufs for descriptor rings */
2572 err = ixgbe_dev_rx_init(dev);
2574 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2578 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2579 ETH_VLAN_EXTEND_MASK;
2580 ixgbe_vlan_offload_set(dev, mask);
2582 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2583 /* Enable vlan filtering for VMDq */
2584 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2587 /* Configure DCB hw */
2588 ixgbe_configure_dcb(dev);
2590 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2591 err = ixgbe_fdir_configure(dev);
2596 /* Restore vf rate limit */
2597 if (vfinfo != NULL) {
2598 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2599 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2600 if (vfinfo[vf].tx_rate[idx] != 0)
2601 ixgbe_set_vf_rate_limit(
2603 vfinfo[vf].tx_rate[idx],
2607 ixgbe_restore_statistics_mapping(dev);
2609 err = ixgbe_dev_rxtx_start(dev);
2611 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2615 /* Skip link setup if loopback mode is enabled for 82599. */
2616 if (hw->mac.type == ixgbe_mac_82599EB &&
2617 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2618 goto skip_link_setup;
2620 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2621 err = hw->mac.ops.setup_sfp(hw);
2626 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2627 /* Turn on the copper */
2628 ixgbe_set_phy_power(hw, true);
2630 /* Turn on the laser */
2631 ixgbe_enable_tx_laser(hw);
2634 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2637 dev->data->dev_link.link_status = link_up;
2639 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2643 link_speeds = &dev->data->dev_conf.link_speeds;
2644 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2645 ETH_LINK_SPEED_10G)) {
2646 PMD_INIT_LOG(ERR, "Invalid link setting");
2651 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2652 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2653 IXGBE_LINK_SPEED_82599_AUTONEG :
2654 IXGBE_LINK_SPEED_82598_AUTONEG;
2656 if (*link_speeds & ETH_LINK_SPEED_10G)
2657 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2658 if (*link_speeds & ETH_LINK_SPEED_1G)
2659 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2660 if (*link_speeds & ETH_LINK_SPEED_100M)
2661 speed |= IXGBE_LINK_SPEED_100_FULL;
2664 err = ixgbe_setup_link(hw, speed, link_up);
2670 if (rte_intr_allow_others(intr_handle)) {
2671 /* check if lsc interrupt is enabled */
2672 if (dev->data->dev_conf.intr_conf.lsc != 0)
2673 ixgbe_dev_lsc_interrupt_setup(dev);
2674 ixgbe_dev_macsec_interrupt_setup(dev);
2676 rte_intr_callback_unregister(intr_handle,
2677 ixgbe_dev_interrupt_handler, dev);
2678 if (dev->data->dev_conf.intr_conf.lsc != 0)
2679 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2680 " no intr multiplex");
2683 /* check if rxq interrupt is enabled */
2684 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2685 rte_intr_dp_is_en(intr_handle))
2686 ixgbe_dev_rxq_interrupt_setup(dev);
2688 /* enable uio/vfio intr/eventfd mapping */
2689 rte_intr_enable(intr_handle);
2691 /* resume enabled intr since hw reset */
2692 ixgbe_enable_intr(dev);
2693 ixgbe_l2_tunnel_conf(dev);
2694 ixgbe_filter_restore(dev);
2699 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2700 ixgbe_dev_clear_queues(dev);
2705 * Stop device: disable rx and tx functions to allow for reconfiguring.
2708 ixgbe_dev_stop(struct rte_eth_dev *dev)
2710 struct rte_eth_link link;
2711 struct ixgbe_hw *hw =
2712 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713 struct ixgbe_vf_info *vfinfo =
2714 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2715 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2716 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2719 PMD_INIT_FUNC_TRACE();
2721 /* disable interrupts */
2722 ixgbe_disable_intr(hw);
2725 ixgbe_pf_reset_hw(hw);
2726 hw->adapter_stopped = 0;
2729 ixgbe_stop_adapter(hw);
2731 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2732 vfinfo[vf].clear_to_send = false;
2734 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2735 /* Turn off the copper */
2736 ixgbe_set_phy_power(hw, false);
2738 /* Turn off the laser */
2739 ixgbe_disable_tx_laser(hw);
2742 ixgbe_dev_clear_queues(dev);
2744 /* Clear stored conf */
2745 dev->data->scattered_rx = 0;
2748 /* Clear recorded link status */
2749 memset(&link, 0, sizeof(link));
2750 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2752 if (!rte_intr_allow_others(intr_handle))
2753 /* resume to the default handler */
2754 rte_intr_callback_register(intr_handle,
2755 ixgbe_dev_interrupt_handler,
2758 /* Clean datapath event and queue/vec mapping */
2759 rte_intr_efd_disable(intr_handle);
2760 if (intr_handle->intr_vec != NULL) {
2761 rte_free(intr_handle->intr_vec);
2762 intr_handle->intr_vec = NULL;
2767 * Set device link up: enable tx.
2770 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2772 struct ixgbe_hw *hw =
2773 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774 if (hw->mac.type == ixgbe_mac_82599EB) {
2775 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2776 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2777 /* Not suported in bypass mode */
2778 PMD_INIT_LOG(ERR, "Set link up is not supported "
2779 "by device id 0x%x", hw->device_id);
2785 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2786 /* Turn on the copper */
2787 ixgbe_set_phy_power(hw, true);
2789 /* Turn on the laser */
2790 ixgbe_enable_tx_laser(hw);
2797 * Set device link down: disable tx.
2800 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2802 struct ixgbe_hw *hw =
2803 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2804 if (hw->mac.type == ixgbe_mac_82599EB) {
2805 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2806 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2807 /* Not suported in bypass mode */
2808 PMD_INIT_LOG(ERR, "Set link down is not supported "
2809 "by device id 0x%x", hw->device_id);
2815 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2816 /* Turn off the copper */
2817 ixgbe_set_phy_power(hw, false);
2819 /* Turn off the laser */
2820 ixgbe_disable_tx_laser(hw);
2827 * Reest and stop device.
2830 ixgbe_dev_close(struct rte_eth_dev *dev)
2832 struct ixgbe_hw *hw =
2833 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2835 PMD_INIT_FUNC_TRACE();
2837 ixgbe_pf_reset_hw(hw);
2839 ixgbe_dev_stop(dev);
2840 hw->adapter_stopped = 1;
2842 ixgbe_dev_free_queues(dev);
2844 ixgbe_disable_pcie_master(hw);
2846 /* reprogram the RAR[0] in case user changed it. */
2847 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2851 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2852 struct ixgbe_hw_stats *hw_stats,
2853 struct ixgbe_macsec_stats *macsec_stats,
2854 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2855 uint64_t *total_qprc, uint64_t *total_qprdc)
2857 uint32_t bprc, lxon, lxoff, total;
2858 uint32_t delta_gprc = 0;
2860 /* Workaround for RX byte count not including CRC bytes when CRC
2861 * strip is enabled. CRC bytes are removed from counters when crc_strip
2864 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2865 IXGBE_HLREG0_RXCRCSTRP);
2867 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2868 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2869 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2870 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2872 for (i = 0; i < 8; i++) {
2873 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2875 /* global total per queue */
2876 hw_stats->mpc[i] += mp;
2877 /* Running comprehensive total for stats display */
2878 *total_missed_rx += hw_stats->mpc[i];
2879 if (hw->mac.type == ixgbe_mac_82598EB) {
2880 hw_stats->rnbc[i] +=
2881 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2882 hw_stats->pxonrxc[i] +=
2883 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2884 hw_stats->pxoffrxc[i] +=
2885 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2887 hw_stats->pxonrxc[i] +=
2888 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2889 hw_stats->pxoffrxc[i] +=
2890 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2891 hw_stats->pxon2offc[i] +=
2892 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2894 hw_stats->pxontxc[i] +=
2895 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2896 hw_stats->pxofftxc[i] +=
2897 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2899 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2900 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2901 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2902 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2904 delta_gprc += delta_qprc;
2906 hw_stats->qprc[i] += delta_qprc;
2907 hw_stats->qptc[i] += delta_qptc;
2909 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2910 hw_stats->qbrc[i] +=
2911 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2913 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2915 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2916 hw_stats->qbtc[i] +=
2917 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2919 hw_stats->qprdc[i] += delta_qprdc;
2920 *total_qprdc += hw_stats->qprdc[i];
2922 *total_qprc += hw_stats->qprc[i];
2923 *total_qbrc += hw_stats->qbrc[i];
2925 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2926 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2927 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2930 * An errata states that gprc actually counts good + missed packets:
2931 * Workaround to set gprc to summated queue packet receives
2933 hw_stats->gprc = *total_qprc;
2935 if (hw->mac.type != ixgbe_mac_82598EB) {
2936 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2937 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2938 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2939 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2940 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2941 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2942 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2943 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2945 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2946 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2947 /* 82598 only has a counter in the high register */
2948 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2949 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2950 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2952 uint64_t old_tpr = hw_stats->tpr;
2954 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2955 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2958 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2960 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2961 hw_stats->gptc += delta_gptc;
2962 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2963 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2966 * Workaround: mprc hardware is incorrectly counting
2967 * broadcasts, so for now we subtract those.
2969 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2970 hw_stats->bprc += bprc;
2971 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2972 if (hw->mac.type == ixgbe_mac_82598EB)
2973 hw_stats->mprc -= bprc;
2975 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2976 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2977 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2978 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2979 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2980 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2982 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2983 hw_stats->lxontxc += lxon;
2984 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2985 hw_stats->lxofftxc += lxoff;
2986 total = lxon + lxoff;
2988 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2989 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2990 hw_stats->gptc -= total;
2991 hw_stats->mptc -= total;
2992 hw_stats->ptc64 -= total;
2993 hw_stats->gotc -= total * ETHER_MIN_LEN;
2995 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2996 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2997 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2998 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2999 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3000 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3001 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3002 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3003 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3004 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3005 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3006 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3007 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3008 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3009 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3010 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3011 /* Only read FCOE on 82599 */
3012 if (hw->mac.type != ixgbe_mac_82598EB) {
3013 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3014 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3015 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3016 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3017 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3020 /* Flow Director Stats registers */
3021 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3022 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3024 /* MACsec Stats registers */
3025 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3026 macsec_stats->out_pkts_encrypted +=
3027 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3028 macsec_stats->out_pkts_protected +=
3029 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3030 macsec_stats->out_octets_encrypted +=
3031 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3032 macsec_stats->out_octets_protected +=
3033 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3034 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3035 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3036 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3037 macsec_stats->in_pkts_unknownsci +=
3038 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3039 macsec_stats->in_octets_decrypted +=
3040 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3041 macsec_stats->in_octets_validated +=
3042 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3043 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3044 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3045 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3046 for (i = 0; i < 2; i++) {
3047 macsec_stats->in_pkts_ok +=
3048 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3049 macsec_stats->in_pkts_invalid +=
3050 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3051 macsec_stats->in_pkts_notvalid +=
3052 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3054 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3055 macsec_stats->in_pkts_notusingsa +=
3056 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3060 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3063 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3065 struct ixgbe_hw *hw =
3066 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067 struct ixgbe_hw_stats *hw_stats =
3068 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3069 struct ixgbe_macsec_stats *macsec_stats =
3070 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3071 dev->data->dev_private);
3072 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3075 total_missed_rx = 0;
3080 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3081 &total_qbrc, &total_qprc, &total_qprdc);
3086 /* Fill out the rte_eth_stats statistics structure */
3087 stats->ipackets = total_qprc;
3088 stats->ibytes = total_qbrc;
3089 stats->opackets = hw_stats->gptc;
3090 stats->obytes = hw_stats->gotc;
3092 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3093 stats->q_ipackets[i] = hw_stats->qprc[i];
3094 stats->q_opackets[i] = hw_stats->qptc[i];
3095 stats->q_ibytes[i] = hw_stats->qbrc[i];
3096 stats->q_obytes[i] = hw_stats->qbtc[i];
3097 stats->q_errors[i] = hw_stats->qprdc[i];
3101 stats->imissed = total_missed_rx;
3102 stats->ierrors = hw_stats->crcerrs +
3118 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3120 struct ixgbe_hw_stats *stats =
3121 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3123 /* HW registers are cleared on read */
3124 ixgbe_dev_stats_get(dev, NULL);
3126 /* Reset software totals */
3127 memset(stats, 0, sizeof(*stats));
3130 /* This function calculates the number of xstats based on the current config */
3132 ixgbe_xstats_calc_num(void) {
3133 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3134 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3135 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3138 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3139 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3141 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3142 unsigned stat, i, count;
3144 if (xstats_names != NULL) {
3147 /* Note: limit >= cnt_stats checked upstream
3148 * in rte_eth_xstats_names()
3151 /* Extended stats from ixgbe_hw_stats */
3152 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3153 snprintf(xstats_names[count].name,
3154 sizeof(xstats_names[count].name),
3156 rte_ixgbe_stats_strings[i].name);
3161 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3162 snprintf(xstats_names[count].name,
3163 sizeof(xstats_names[count].name),
3165 rte_ixgbe_macsec_strings[i].name);
3169 /* RX Priority Stats */
3170 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3171 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3172 snprintf(xstats_names[count].name,
3173 sizeof(xstats_names[count].name),
3174 "rx_priority%u_%s", i,
3175 rte_ixgbe_rxq_strings[stat].name);
3180 /* TX Priority Stats */
3181 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3182 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3183 snprintf(xstats_names[count].name,
3184 sizeof(xstats_names[count].name),
3185 "tx_priority%u_%s", i,
3186 rte_ixgbe_txq_strings[stat].name);
3194 static int ixgbe_dev_xstats_get_names_by_id(
3195 struct rte_eth_dev *dev,
3196 struct rte_eth_xstat_name *xstats_names,
3197 const uint64_t *ids,
3201 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3202 unsigned int stat, i, count;
3204 if (xstats_names != NULL) {
3207 /* Note: limit >= cnt_stats checked upstream
3208 * in rte_eth_xstats_names()
3211 /* Extended stats from ixgbe_hw_stats */
3212 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3213 snprintf(xstats_names[count].name,
3214 sizeof(xstats_names[count].name),
3216 rte_ixgbe_stats_strings[i].name);
3221 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3222 snprintf(xstats_names[count].name,
3223 sizeof(xstats_names[count].name),
3225 rte_ixgbe_macsec_strings[i].name);
3229 /* RX Priority Stats */
3230 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3231 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3232 snprintf(xstats_names[count].name,
3233 sizeof(xstats_names[count].name),
3234 "rx_priority%u_%s", i,
3235 rte_ixgbe_rxq_strings[stat].name);
3240 /* TX Priority Stats */
3241 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3242 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3243 snprintf(xstats_names[count].name,
3244 sizeof(xstats_names[count].name),
3245 "tx_priority%u_%s", i,
3246 rte_ixgbe_txq_strings[stat].name);
3255 uint16_t size = ixgbe_xstats_calc_num();
3256 struct rte_eth_xstat_name xstats_names_copy[size];
3258 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3261 for (i = 0; i < limit; i++) {
3262 if (ids[i] >= size) {
3263 PMD_INIT_LOG(ERR, "id value isn't valid");
3266 strcpy(xstats_names[i].name,
3267 xstats_names_copy[ids[i]].name);
3272 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3273 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3277 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3280 if (xstats_names != NULL)
3281 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3282 snprintf(xstats_names[i].name,
3283 sizeof(xstats_names[i].name),
3284 "%s", rte_ixgbevf_stats_strings[i].name);
3285 return IXGBEVF_NB_XSTATS;
3289 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3292 struct ixgbe_hw *hw =
3293 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3294 struct ixgbe_hw_stats *hw_stats =
3295 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3296 struct ixgbe_macsec_stats *macsec_stats =
3297 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3298 dev->data->dev_private);
3299 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3300 unsigned i, stat, count = 0;
3302 count = ixgbe_xstats_calc_num();
3307 total_missed_rx = 0;
3312 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3313 &total_qbrc, &total_qprc, &total_qprdc);
3315 /* If this is a reset xstats is NULL, and we have cleared the
3316 * registers by reading them.
3321 /* Extended stats from ixgbe_hw_stats */
3323 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3324 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3325 rte_ixgbe_stats_strings[i].offset);
3326 xstats[count].id = count;
3331 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3332 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3333 rte_ixgbe_macsec_strings[i].offset);
3334 xstats[count].id = count;
3338 /* RX Priority Stats */
3339 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3340 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3341 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3342 rte_ixgbe_rxq_strings[stat].offset +
3343 (sizeof(uint64_t) * i));
3344 xstats[count].id = count;
3349 /* TX Priority Stats */
3350 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3351 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3352 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3353 rte_ixgbe_txq_strings[stat].offset +
3354 (sizeof(uint64_t) * i));
3355 xstats[count].id = count;
3363 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3364 uint64_t *values, unsigned int n)
3367 struct ixgbe_hw *hw =
3368 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3369 struct ixgbe_hw_stats *hw_stats =
3370 IXGBE_DEV_PRIVATE_TO_STATS(
3371 dev->data->dev_private);
3372 struct ixgbe_macsec_stats *macsec_stats =
3373 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3374 dev->data->dev_private);
3375 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3376 unsigned int i, stat, count = 0;
3378 count = ixgbe_xstats_calc_num();
3380 if (!ids && n < count)
3383 total_missed_rx = 0;
3388 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3389 &total_missed_rx, &total_qbrc, &total_qprc,
3392 /* If this is a reset xstats is NULL, and we have cleared the
3393 * registers by reading them.
3395 if (!ids && !values)
3398 /* Extended stats from ixgbe_hw_stats */
3400 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3401 values[count] = *(uint64_t *)(((char *)hw_stats) +
3402 rte_ixgbe_stats_strings[i].offset);
3407 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3408 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3409 rte_ixgbe_macsec_strings[i].offset);
3413 /* RX Priority Stats */
3414 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3415 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3417 *(uint64_t *)(((char *)hw_stats) +
3418 rte_ixgbe_rxq_strings[stat].offset +
3419 (sizeof(uint64_t) * i));
3424 /* TX Priority Stats */
3425 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3426 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3428 *(uint64_t *)(((char *)hw_stats) +
3429 rte_ixgbe_txq_strings[stat].offset +
3430 (sizeof(uint64_t) * i));
3438 uint16_t size = ixgbe_xstats_calc_num();
3439 uint64_t values_copy[size];
3441 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3443 for (i = 0; i < n; i++) {
3444 if (ids[i] >= size) {
3445 PMD_INIT_LOG(ERR, "id value isn't valid");
3448 values[i] = values_copy[ids[i]];
3454 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3456 struct ixgbe_hw_stats *stats =
3457 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3458 struct ixgbe_macsec_stats *macsec_stats =
3459 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3460 dev->data->dev_private);
3462 unsigned count = ixgbe_xstats_calc_num();
3464 /* HW registers are cleared on read */
3465 ixgbe_dev_xstats_get(dev, NULL, count);
3467 /* Reset software totals */
3468 memset(stats, 0, sizeof(*stats));
3469 memset(macsec_stats, 0, sizeof(*macsec_stats));
3473 ixgbevf_update_stats(struct rte_eth_dev *dev)
3475 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3476 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3477 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3479 /* Good Rx packet, include VF loopback */
3480 UPDATE_VF_STAT(IXGBE_VFGPRC,
3481 hw_stats->last_vfgprc, hw_stats->vfgprc);
3483 /* Good Rx octets, include VF loopback */
3484 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3485 hw_stats->last_vfgorc, hw_stats->vfgorc);
3487 /* Good Tx packet, include VF loopback */
3488 UPDATE_VF_STAT(IXGBE_VFGPTC,
3489 hw_stats->last_vfgptc, hw_stats->vfgptc);
3491 /* Good Tx octets, include VF loopback */
3492 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3493 hw_stats->last_vfgotc, hw_stats->vfgotc);
3495 /* Rx Multicst Packet */
3496 UPDATE_VF_STAT(IXGBE_VFMPRC,
3497 hw_stats->last_vfmprc, hw_stats->vfmprc);
3501 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3504 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3505 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3508 if (n < IXGBEVF_NB_XSTATS)
3509 return IXGBEVF_NB_XSTATS;
3511 ixgbevf_update_stats(dev);
3516 /* Extended stats */
3517 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3519 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3520 rte_ixgbevf_stats_strings[i].offset);
3523 return IXGBEVF_NB_XSTATS;
3527 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3529 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3530 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3532 ixgbevf_update_stats(dev);
3537 stats->ipackets = hw_stats->vfgprc;
3538 stats->ibytes = hw_stats->vfgorc;
3539 stats->opackets = hw_stats->vfgptc;
3540 stats->obytes = hw_stats->vfgotc;
3544 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3546 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3547 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3549 /* Sync HW register to the last stats */
3550 ixgbevf_dev_stats_get(dev, NULL);
3552 /* reset HW current stats*/
3553 hw_stats->vfgprc = 0;
3554 hw_stats->vfgorc = 0;
3555 hw_stats->vfgptc = 0;
3556 hw_stats->vfgotc = 0;
3560 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3562 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3563 u16 eeprom_verh, eeprom_verl;
3567 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3568 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3570 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3571 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3573 ret += 1; /* add the size of '\0' */
3574 if (fw_size < (u32)ret)
3581 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3583 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3584 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3585 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3587 dev_info->pci_dev = pci_dev;
3588 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3589 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3590 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3592 * When DCB/VT is off, maximum number of queues changes,
3593 * except for 82598EB, which remains constant.
3595 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3596 hw->mac.type != ixgbe_mac_82598EB)
3597 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3599 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3600 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3601 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3602 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3603 dev_info->max_vfs = pci_dev->max_vfs;
3604 if (hw->mac.type == ixgbe_mac_82598EB)
3605 dev_info->max_vmdq_pools = ETH_16_POOLS;
3607 dev_info->max_vmdq_pools = ETH_64_POOLS;
3608 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3609 dev_info->rx_offload_capa =
3610 DEV_RX_OFFLOAD_VLAN_STRIP |
3611 DEV_RX_OFFLOAD_IPV4_CKSUM |
3612 DEV_RX_OFFLOAD_UDP_CKSUM |
3613 DEV_RX_OFFLOAD_TCP_CKSUM;
3616 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3619 if ((hw->mac.type == ixgbe_mac_82599EB ||
3620 hw->mac.type == ixgbe_mac_X540) &&
3621 !RTE_ETH_DEV_SRIOV(dev).active)
3622 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3624 if (hw->mac.type == ixgbe_mac_82599EB ||
3625 hw->mac.type == ixgbe_mac_X540)
3626 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3628 if (hw->mac.type == ixgbe_mac_X550 ||
3629 hw->mac.type == ixgbe_mac_X550EM_x ||
3630 hw->mac.type == ixgbe_mac_X550EM_a)
3631 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3633 dev_info->tx_offload_capa =
3634 DEV_TX_OFFLOAD_VLAN_INSERT |
3635 DEV_TX_OFFLOAD_IPV4_CKSUM |
3636 DEV_TX_OFFLOAD_UDP_CKSUM |
3637 DEV_TX_OFFLOAD_TCP_CKSUM |
3638 DEV_TX_OFFLOAD_SCTP_CKSUM |
3639 DEV_TX_OFFLOAD_TCP_TSO;
3641 if (hw->mac.type == ixgbe_mac_82599EB ||
3642 hw->mac.type == ixgbe_mac_X540)
3643 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3645 if (hw->mac.type == ixgbe_mac_X550 ||
3646 hw->mac.type == ixgbe_mac_X550EM_x ||
3647 hw->mac.type == ixgbe_mac_X550EM_a)
3648 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3650 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3652 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3653 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3654 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3656 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3660 dev_info->default_txconf = (struct rte_eth_txconf) {
3662 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3663 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3664 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3666 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3667 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3668 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3669 ETH_TXQ_FLAGS_NOOFFLOADS,
3672 dev_info->rx_desc_lim = rx_desc_lim;
3673 dev_info->tx_desc_lim = tx_desc_lim;
3675 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3676 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3677 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3679 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3680 if (hw->mac.type == ixgbe_mac_X540 ||
3681 hw->mac.type == ixgbe_mac_X540_vf ||
3682 hw->mac.type == ixgbe_mac_X550 ||
3683 hw->mac.type == ixgbe_mac_X550_vf) {
3684 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3688 static const uint32_t *
3689 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3691 static const uint32_t ptypes[] = {
3692 /* For non-vec functions,
3693 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3694 * for vec functions,
3695 * refers to _recv_raw_pkts_vec().
3699 RTE_PTYPE_L3_IPV4_EXT,
3701 RTE_PTYPE_L3_IPV6_EXT,
3705 RTE_PTYPE_TUNNEL_IP,
3706 RTE_PTYPE_INNER_L3_IPV6,
3707 RTE_PTYPE_INNER_L3_IPV6_EXT,
3708 RTE_PTYPE_INNER_L4_TCP,
3709 RTE_PTYPE_INNER_L4_UDP,
3713 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3714 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3715 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3716 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3719 #if defined(RTE_ARCH_X86)
3720 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3721 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3728 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3729 struct rte_eth_dev_info *dev_info)
3731 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3732 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3734 dev_info->pci_dev = pci_dev;
3735 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3736 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3737 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3738 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3739 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3740 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3741 dev_info->max_vfs = pci_dev->max_vfs;
3742 if (hw->mac.type == ixgbe_mac_82598EB)
3743 dev_info->max_vmdq_pools = ETH_16_POOLS;
3745 dev_info->max_vmdq_pools = ETH_64_POOLS;
3746 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3747 DEV_RX_OFFLOAD_IPV4_CKSUM |
3748 DEV_RX_OFFLOAD_UDP_CKSUM |
3749 DEV_RX_OFFLOAD_TCP_CKSUM;
3750 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3751 DEV_TX_OFFLOAD_IPV4_CKSUM |
3752 DEV_TX_OFFLOAD_UDP_CKSUM |
3753 DEV_TX_OFFLOAD_TCP_CKSUM |
3754 DEV_TX_OFFLOAD_SCTP_CKSUM |
3755 DEV_TX_OFFLOAD_TCP_TSO;
3757 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3759 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3760 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3761 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3763 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3767 dev_info->default_txconf = (struct rte_eth_txconf) {
3769 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3770 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3771 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3773 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3774 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3775 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3776 ETH_TXQ_FLAGS_NOOFFLOADS,
3779 dev_info->rx_desc_lim = rx_desc_lim;
3780 dev_info->tx_desc_lim = tx_desc_lim;
3784 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3785 int *link_up, int wait_to_complete)
3788 * for a quick link status checking, wait_to_compelet == 0,
3789 * skip PF link status checking
3791 bool no_pflink_check = wait_to_complete == 0;
3792 struct ixgbe_mbx_info *mbx = &hw->mbx;
3793 struct ixgbe_mac_info *mac = &hw->mac;
3794 uint32_t links_reg, in_msg;
3797 /* If we were hit with a reset drop the link */
3798 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3799 mac->get_link_status = true;
3801 if (!mac->get_link_status)
3804 /* if link status is down no point in checking to see if pf is up */
3805 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3806 if (!(links_reg & IXGBE_LINKS_UP))
3809 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3810 * before the link status is correct
3812 if (mac->type == ixgbe_mac_82599_vf) {
3815 for (i = 0; i < 5; i++) {
3817 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3819 if (!(links_reg & IXGBE_LINKS_UP))
3824 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3825 case IXGBE_LINKS_SPEED_10G_82599:
3826 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3827 if (hw->mac.type >= ixgbe_mac_X550) {
3828 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3829 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3832 case IXGBE_LINKS_SPEED_1G_82599:
3833 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3835 case IXGBE_LINKS_SPEED_100_82599:
3836 *speed = IXGBE_LINK_SPEED_100_FULL;
3837 if (hw->mac.type == ixgbe_mac_X550) {
3838 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3839 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3842 case IXGBE_LINKS_SPEED_10_X550EM_A:
3843 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3844 /* Since Reserved in older MAC's */
3845 if (hw->mac.type >= ixgbe_mac_X550)
3846 *speed = IXGBE_LINK_SPEED_10_FULL;
3849 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3852 if (no_pflink_check) {
3853 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3854 mac->get_link_status = true;
3856 mac->get_link_status = false;
3860 /* if the read failed it could just be a mailbox collision, best wait
3861 * until we are called again and don't report an error
3863 if (mbx->ops.read(hw, &in_msg, 1, 0))
3866 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3867 /* msg is not CTS and is NACK we must have lost CTS status */
3868 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3873 /* the pf is talking, if we timed out in the past we reinit */
3874 if (!mbx->timeout) {
3879 /* if we passed all the tests above then the link is up and we no
3880 * longer need to check for link
3882 mac->get_link_status = false;
3885 *link_up = !mac->get_link_status;
3889 /* return 0 means link status changed, -1 means not changed */
3891 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3892 int wait_to_complete, int vf)
3894 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3895 struct rte_eth_link link, old;
3896 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3897 struct ixgbe_interrupt *intr =
3898 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3903 bool autoneg = false;
3905 link.link_status = ETH_LINK_DOWN;
3906 link.link_speed = 0;
3907 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3908 memset(&old, 0, sizeof(old));
3909 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3911 hw->mac.get_link_status = true;
3913 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3914 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3915 speed = hw->phy.autoneg_advertised;
3917 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3918 ixgbe_setup_link(hw, speed, true);
3921 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3922 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3926 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3928 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3931 link.link_speed = ETH_SPEED_NUM_100M;
3932 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3933 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3934 if (link.link_status == old.link_status)
3940 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3941 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3942 if (link.link_status == old.link_status)
3946 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3947 link.link_status = ETH_LINK_UP;
3948 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3950 switch (link_speed) {
3952 case IXGBE_LINK_SPEED_UNKNOWN:
3953 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3954 link.link_speed = ETH_SPEED_NUM_100M;
3957 case IXGBE_LINK_SPEED_100_FULL:
3958 link.link_speed = ETH_SPEED_NUM_100M;
3961 case IXGBE_LINK_SPEED_1GB_FULL:
3962 link.link_speed = ETH_SPEED_NUM_1G;
3965 case IXGBE_LINK_SPEED_10GB_FULL:
3966 link.link_speed = ETH_SPEED_NUM_10G;
3969 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3971 if (link.link_status == old.link_status)
3978 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3980 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3984 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3986 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3990 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3992 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3996 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3997 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4001 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4003 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4006 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4007 fctrl &= (~IXGBE_FCTRL_UPE);
4008 if (dev->data->all_multicast == 1)
4009 fctrl |= IXGBE_FCTRL_MPE;
4011 fctrl &= (~IXGBE_FCTRL_MPE);
4012 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4016 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4018 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4021 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4022 fctrl |= IXGBE_FCTRL_MPE;
4023 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4027 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4029 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4032 if (dev->data->promiscuous == 1)
4033 return; /* must remain in all_multicast mode */
4035 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4036 fctrl &= (~IXGBE_FCTRL_MPE);
4037 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4041 * It clears the interrupt causes and enables the interrupt.
4042 * It will be called once only during nic initialized.
4045 * Pointer to struct rte_eth_dev.
4048 * - On success, zero.
4049 * - On failure, a negative value.
4052 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
4054 struct ixgbe_interrupt *intr =
4055 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4057 ixgbe_dev_link_status_print(dev);
4058 intr->mask |= IXGBE_EICR_LSC;
4064 * It clears the interrupt causes and enables the interrupt.
4065 * It will be called once only during nic initialized.
4068 * Pointer to struct rte_eth_dev.
4071 * - On success, zero.
4072 * - On failure, a negative value.
4075 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4077 struct ixgbe_interrupt *intr =
4078 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4080 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4086 * It clears the interrupt causes and enables the interrupt.
4087 * It will be called once only during nic initialized.
4090 * Pointer to struct rte_eth_dev.
4093 * - On success, zero.
4094 * - On failure, a negative value.
4097 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4099 struct ixgbe_interrupt *intr =
4100 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4102 intr->mask |= IXGBE_EICR_LINKSEC;
4108 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4111 * Pointer to struct rte_eth_dev.
4114 * - On success, zero.
4115 * - On failure, a negative value.
4118 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4122 struct ixgbe_interrupt *intr =
4123 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4125 /* clear all cause mask */
4126 ixgbe_disable_intr(hw);
4128 /* read-on-clear nic registers here */
4129 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4130 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4134 /* set flag for async link update */
4135 if (eicr & IXGBE_EICR_LSC)
4136 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4138 if (eicr & IXGBE_EICR_MAILBOX)
4139 intr->flags |= IXGBE_FLAG_MAILBOX;
4141 if (eicr & IXGBE_EICR_LINKSEC)
4142 intr->flags |= IXGBE_FLAG_MACSEC;
4144 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4145 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4146 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4147 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4153 * It gets and then prints the link status.
4156 * Pointer to struct rte_eth_dev.
4159 * - On success, zero.
4160 * - On failure, a negative value.
4163 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4165 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4166 struct rte_eth_link link;
4168 memset(&link, 0, sizeof(link));
4169 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4170 if (link.link_status) {
4171 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4172 (int)(dev->data->port_id),
4173 (unsigned)link.link_speed,
4174 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4175 "full-duplex" : "half-duplex");
4177 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4178 (int)(dev->data->port_id));
4180 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4181 pci_dev->addr.domain,
4183 pci_dev->addr.devid,
4184 pci_dev->addr.function);
4188 * It executes link_update after knowing an interrupt occurred.
4191 * Pointer to struct rte_eth_dev.
4194 * - On success, zero.
4195 * - On failure, a negative value.
4198 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4199 struct rte_intr_handle *intr_handle)
4201 struct ixgbe_interrupt *intr =
4202 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4204 struct rte_eth_link link;
4205 struct ixgbe_hw *hw =
4206 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4208 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4210 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4211 ixgbe_pf_mbx_process(dev);
4212 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4215 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4216 ixgbe_handle_lasi(hw);
4217 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4220 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4221 /* get the link status before link update, for predicting later */
4222 memset(&link, 0, sizeof(link));
4223 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4225 ixgbe_dev_link_update(dev, 0);
4228 if (!link.link_status)
4229 /* handle it 1 sec later, wait it being stable */
4230 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4231 /* likely to down */
4233 /* handle it 4 sec later, wait it being stable */
4234 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4236 ixgbe_dev_link_status_print(dev);
4237 if (rte_eal_alarm_set(timeout * 1000,
4238 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4239 PMD_DRV_LOG(ERR, "Error setting alarm");
4241 /* remember original mask */
4242 intr->mask_original = intr->mask;
4243 /* only disable lsc interrupt */
4244 intr->mask &= ~IXGBE_EIMS_LSC;
4248 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4249 ixgbe_enable_intr(dev);
4250 rte_intr_enable(intr_handle);
4256 * Interrupt handler which shall be registered for alarm callback for delayed
4257 * handling specific interrupt to wait for the stable nic state. As the
4258 * NIC interrupt state is not stable for ixgbe after link is just down,
4259 * it needs to wait 4 seconds to get the stable status.
4262 * Pointer to interrupt handle.
4264 * The address of parameter (struct rte_eth_dev *) regsitered before.
4270 ixgbe_dev_interrupt_delayed_handler(void *param)
4272 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4273 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4274 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4275 struct ixgbe_interrupt *intr =
4276 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4277 struct ixgbe_hw *hw =
4278 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4281 ixgbe_disable_intr(hw);
4283 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4284 if (eicr & IXGBE_EICR_MAILBOX)
4285 ixgbe_pf_mbx_process(dev);
4287 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4288 ixgbe_handle_lasi(hw);
4289 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4292 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4293 ixgbe_dev_link_update(dev, 0);
4294 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4295 ixgbe_dev_link_status_print(dev);
4296 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4300 if (intr->flags & IXGBE_FLAG_MACSEC) {
4301 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4303 intr->flags &= ~IXGBE_FLAG_MACSEC;
4306 /* restore original mask */
4307 intr->mask = intr->mask_original;
4308 intr->mask_original = 0;
4310 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4311 ixgbe_enable_intr(dev);
4312 rte_intr_enable(intr_handle);
4316 * Interrupt handler triggered by NIC for handling
4317 * specific interrupt.
4320 * Pointer to interrupt handle.
4322 * The address of parameter (struct rte_eth_dev *) regsitered before.
4328 ixgbe_dev_interrupt_handler(void *param)
4330 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4332 ixgbe_dev_interrupt_get_status(dev);
4333 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4337 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4339 struct ixgbe_hw *hw;
4341 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4346 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4348 struct ixgbe_hw *hw;
4350 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4355 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4357 struct ixgbe_hw *hw;
4363 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4365 fc_conf->pause_time = hw->fc.pause_time;
4366 fc_conf->high_water = hw->fc.high_water[0];
4367 fc_conf->low_water = hw->fc.low_water[0];
4368 fc_conf->send_xon = hw->fc.send_xon;
4369 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4372 * Return rx_pause status according to actual setting of
4375 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4376 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4382 * Return tx_pause status according to actual setting of
4385 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4386 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4391 if (rx_pause && tx_pause)
4392 fc_conf->mode = RTE_FC_FULL;
4394 fc_conf->mode = RTE_FC_RX_PAUSE;
4396 fc_conf->mode = RTE_FC_TX_PAUSE;
4398 fc_conf->mode = RTE_FC_NONE;
4404 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4406 struct ixgbe_hw *hw;
4408 uint32_t rx_buf_size;
4409 uint32_t max_high_water;
4411 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4418 PMD_INIT_FUNC_TRACE();
4420 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4422 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4425 * At least reserve one Ethernet frame for watermark
4426 * high_water/low_water in kilo bytes for ixgbe
4428 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4429 if ((fc_conf->high_water > max_high_water) ||
4430 (fc_conf->high_water < fc_conf->low_water)) {
4431 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4432 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4436 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4437 hw->fc.pause_time = fc_conf->pause_time;
4438 hw->fc.high_water[0] = fc_conf->high_water;
4439 hw->fc.low_water[0] = fc_conf->low_water;
4440 hw->fc.send_xon = fc_conf->send_xon;
4441 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4443 err = ixgbe_fc_enable(hw);
4445 /* Not negotiated is not an error case */
4446 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4448 /* check if we want to forward MAC frames - driver doesn't have native
4449 * capability to do that, so we'll write the registers ourselves */
4451 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4453 /* set or clear MFLCN.PMCF bit depending on configuration */
4454 if (fc_conf->mac_ctrl_frame_fwd != 0)
4455 mflcn |= IXGBE_MFLCN_PMCF;
4457 mflcn &= ~IXGBE_MFLCN_PMCF;
4459 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4460 IXGBE_WRITE_FLUSH(hw);
4465 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4470 * ixgbe_pfc_enable_generic - Enable flow control
4471 * @hw: pointer to hardware structure
4472 * @tc_num: traffic class number
4473 * Enable flow control according to the current settings.
4476 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4479 uint32_t mflcn_reg, fccfg_reg;
4481 uint32_t fcrtl, fcrth;
4485 /* Validate the water mark configuration */
4486 if (!hw->fc.pause_time) {
4487 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4491 /* Low water mark of zero causes XOFF floods */
4492 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4493 /* High/Low water can not be 0 */
4494 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4495 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4496 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4500 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4501 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4502 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4506 /* Negotiate the fc mode to use */
4507 ixgbe_fc_autoneg(hw);
4509 /* Disable any previous flow control settings */
4510 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4511 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4513 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4514 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4516 switch (hw->fc.current_mode) {
4519 * If the count of enabled RX Priority Flow control >1,
4520 * and the TX pause can not be disabled
4523 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4524 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4525 if (reg & IXGBE_FCRTH_FCEN)
4529 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4531 case ixgbe_fc_rx_pause:
4533 * Rx Flow control is enabled and Tx Flow control is
4534 * disabled by software override. Since there really
4535 * isn't a way to advertise that we are capable of RX
4536 * Pause ONLY, we will advertise that we support both
4537 * symmetric and asymmetric Rx PAUSE. Later, we will
4538 * disable the adapter's ability to send PAUSE frames.
4540 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4542 * If the count of enabled RX Priority Flow control >1,
4543 * and the TX pause can not be disabled
4546 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4547 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4548 if (reg & IXGBE_FCRTH_FCEN)
4552 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4554 case ixgbe_fc_tx_pause:
4556 * Tx Flow control is enabled, and Rx Flow control is
4557 * disabled by software override.
4559 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4562 /* Flow control (both Rx and Tx) is enabled by SW override. */
4563 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4564 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4567 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4568 ret_val = IXGBE_ERR_CONFIG;
4572 /* Set 802.3x based flow control settings. */
4573 mflcn_reg |= IXGBE_MFLCN_DPF;
4574 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4575 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4577 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4578 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4579 hw->fc.high_water[tc_num]) {
4580 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4581 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4582 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4584 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4586 * In order to prevent Tx hangs when the internal Tx
4587 * switch is enabled we must set the high water mark
4588 * to the maximum FCRTH value. This allows the Tx
4589 * switch to function even under heavy Rx workloads.
4591 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4593 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4595 /* Configure pause time (2 TCs per register) */
4596 reg = hw->fc.pause_time * 0x00010001;
4597 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4598 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4600 /* Configure flow control refresh threshold value */
4601 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4608 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4610 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4611 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4613 if (hw->mac.type != ixgbe_mac_82598EB) {
4614 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4620 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4623 uint32_t rx_buf_size;
4624 uint32_t max_high_water;
4626 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4627 struct ixgbe_hw *hw =
4628 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629 struct ixgbe_dcb_config *dcb_config =
4630 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4632 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4639 PMD_INIT_FUNC_TRACE();
4641 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4642 tc_num = map[pfc_conf->priority];
4643 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4644 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4646 * At least reserve one Ethernet frame for watermark
4647 * high_water/low_water in kilo bytes for ixgbe
4649 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4650 if ((pfc_conf->fc.high_water > max_high_water) ||
4651 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4652 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4653 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4657 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4658 hw->fc.pause_time = pfc_conf->fc.pause_time;
4659 hw->fc.send_xon = pfc_conf->fc.send_xon;
4660 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4661 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4663 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4665 /* Not negotiated is not an error case */
4666 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4669 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4674 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4675 struct rte_eth_rss_reta_entry64 *reta_conf,
4678 uint16_t i, sp_reta_size;
4681 uint16_t idx, shift;
4682 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685 PMD_INIT_FUNC_TRACE();
4687 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4688 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4693 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4694 if (reta_size != sp_reta_size) {
4695 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4696 "(%d) doesn't match the number hardware can supported "
4697 "(%d)", reta_size, sp_reta_size);
4701 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4702 idx = i / RTE_RETA_GROUP_SIZE;
4703 shift = i % RTE_RETA_GROUP_SIZE;
4704 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4708 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4709 if (mask == IXGBE_4_BIT_MASK)
4712 r = IXGBE_READ_REG(hw, reta_reg);
4713 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4714 if (mask & (0x1 << j))
4715 reta |= reta_conf[idx].reta[shift + j] <<
4718 reta |= r & (IXGBE_8_BIT_MASK <<
4721 IXGBE_WRITE_REG(hw, reta_reg, reta);
4728 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4729 struct rte_eth_rss_reta_entry64 *reta_conf,
4732 uint16_t i, sp_reta_size;
4735 uint16_t idx, shift;
4736 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4739 PMD_INIT_FUNC_TRACE();
4740 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4741 if (reta_size != sp_reta_size) {
4742 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4743 "(%d) doesn't match the number hardware can supported "
4744 "(%d)", reta_size, sp_reta_size);
4748 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4749 idx = i / RTE_RETA_GROUP_SIZE;
4750 shift = i % RTE_RETA_GROUP_SIZE;
4751 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4756 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4757 reta = IXGBE_READ_REG(hw, reta_reg);
4758 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4759 if (mask & (0x1 << j))
4760 reta_conf[idx].reta[shift + j] =
4761 ((reta >> (CHAR_BIT * j)) &
4770 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4771 uint32_t index, uint32_t pool)
4773 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4774 uint32_t enable_addr = 1;
4776 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4781 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4783 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4785 ixgbe_clear_rar(hw, index);
4789 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4791 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4793 ixgbe_remove_rar(dev, 0);
4795 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4799 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4801 if (strcmp(dev->device->driver->name, drv->driver.name))
4808 is_ixgbe_supported(struct rte_eth_dev *dev)
4810 return is_device_supported(dev, &rte_ixgbe_pmd);
4814 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4818 struct ixgbe_hw *hw;
4819 struct rte_eth_dev_info dev_info;
4820 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4821 struct rte_eth_dev_data *dev_data = dev->data;
4823 ixgbe_dev_info_get(dev, &dev_info);
4825 /* check that mtu is within the allowed range */
4826 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4829 /* If device is started, refuse mtu that requires the support of
4830 * scattered packets when this feature has not been enabled before.
4832 if (dev_data->dev_started && !dev_data->scattered_rx &&
4833 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4834 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4835 PMD_INIT_LOG(ERR, "Stop port first.");
4839 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4840 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4842 /* switch to jumbo mode if needed */
4843 if (frame_size > ETHER_MAX_LEN) {
4844 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4845 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4847 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4848 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4850 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4852 /* update max frame size */
4853 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4855 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4856 maxfrs &= 0x0000FFFF;
4857 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4858 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4864 * Virtual Function operations
4867 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4869 PMD_INIT_FUNC_TRACE();
4871 /* Clear interrupt mask to stop from interrupts being generated */
4872 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4874 IXGBE_WRITE_FLUSH(hw);
4878 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4880 PMD_INIT_FUNC_TRACE();
4882 /* VF enable interrupt autoclean */
4883 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4884 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4885 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4887 IXGBE_WRITE_FLUSH(hw);
4891 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4893 struct rte_eth_conf *conf = &dev->data->dev_conf;
4894 struct ixgbe_adapter *adapter =
4895 (struct ixgbe_adapter *)dev->data->dev_private;
4897 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4898 dev->data->port_id);
4901 * VF has no ability to enable/disable HW CRC
4902 * Keep the persistent behavior the same as Host PF
4904 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4905 if (!conf->rxmode.hw_strip_crc) {
4906 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4907 conf->rxmode.hw_strip_crc = 1;
4910 if (conf->rxmode.hw_strip_crc) {
4911 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4912 conf->rxmode.hw_strip_crc = 0;
4917 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4918 * allocation or vector Rx preconditions we will reset it.
4920 adapter->rx_bulk_alloc_allowed = true;
4921 adapter->rx_vec_allowed = true;
4927 ixgbevf_dev_start(struct rte_eth_dev *dev)
4929 struct ixgbe_hw *hw =
4930 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4931 uint32_t intr_vector = 0;
4932 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4933 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4937 PMD_INIT_FUNC_TRACE();
4939 hw->mac.ops.reset_hw(hw);
4940 hw->mac.get_link_status = true;
4942 /* negotiate mailbox API version to use with the PF. */
4943 ixgbevf_negotiate_api(hw);
4945 ixgbevf_dev_tx_init(dev);
4947 /* This can fail when allocating mbufs for descriptor rings */
4948 err = ixgbevf_dev_rx_init(dev);
4950 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4951 ixgbe_dev_clear_queues(dev);
4956 ixgbevf_set_vfta_all(dev, 1);
4959 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4960 ETH_VLAN_EXTEND_MASK;
4961 ixgbevf_vlan_offload_set(dev, mask);
4963 ixgbevf_dev_rxtx_start(dev);
4965 /* check and configure queue intr-vector mapping */
4966 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4967 intr_vector = dev->data->nb_rx_queues;
4968 if (rte_intr_efd_enable(intr_handle, intr_vector))
4972 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4973 intr_handle->intr_vec =
4974 rte_zmalloc("intr_vec",
4975 dev->data->nb_rx_queues * sizeof(int), 0);
4976 if (intr_handle->intr_vec == NULL) {
4977 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4978 " intr_vec", dev->data->nb_rx_queues);
4982 ixgbevf_configure_msix(dev);
4984 rte_intr_enable(intr_handle);
4986 /* Re-enable interrupt for VF */
4987 ixgbevf_intr_enable(hw);
4993 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4995 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4996 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4997 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4999 PMD_INIT_FUNC_TRACE();
5001 ixgbevf_intr_disable(hw);
5003 hw->adapter_stopped = 1;
5004 ixgbe_stop_adapter(hw);
5007 * Clear what we set, but we still keep shadow_vfta to
5008 * restore after device starts
5010 ixgbevf_set_vfta_all(dev, 0);
5012 /* Clear stored conf */
5013 dev->data->scattered_rx = 0;
5015 ixgbe_dev_clear_queues(dev);
5017 /* Clean datapath event and queue/vec mapping */
5018 rte_intr_efd_disable(intr_handle);
5019 if (intr_handle->intr_vec != NULL) {
5020 rte_free(intr_handle->intr_vec);
5021 intr_handle->intr_vec = NULL;
5026 ixgbevf_dev_close(struct rte_eth_dev *dev)
5028 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5030 PMD_INIT_FUNC_TRACE();
5034 ixgbevf_dev_stop(dev);
5036 ixgbe_dev_free_queues(dev);
5039 * Remove the VF MAC address ro ensure
5040 * that the VF traffic goes to the PF
5041 * after stop, close and detach of the VF
5043 ixgbevf_remove_mac_addr(dev, 0);
5046 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5048 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5049 struct ixgbe_vfta *shadow_vfta =
5050 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5051 int i = 0, j = 0, vfta = 0, mask = 1;
5053 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5054 vfta = shadow_vfta->vfta[i];
5057 for (j = 0; j < 32; j++) {
5059 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5069 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5071 struct ixgbe_hw *hw =
5072 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5073 struct ixgbe_vfta *shadow_vfta =
5074 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5075 uint32_t vid_idx = 0;
5076 uint32_t vid_bit = 0;
5079 PMD_INIT_FUNC_TRACE();
5081 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5082 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5084 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5087 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5088 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5090 /* Save what we set and retore it after device reset */
5092 shadow_vfta->vfta[vid_idx] |= vid_bit;
5094 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5100 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5102 struct ixgbe_hw *hw =
5103 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5106 PMD_INIT_FUNC_TRACE();
5108 if (queue >= hw->mac.max_rx_queues)
5111 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5113 ctrl |= IXGBE_RXDCTL_VME;
5115 ctrl &= ~IXGBE_RXDCTL_VME;
5116 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5118 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5122 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5124 struct ixgbe_hw *hw =
5125 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5129 /* VF function only support hw strip feature, others are not support */
5130 if (mask & ETH_VLAN_STRIP_MASK) {
5131 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5133 for (i = 0; i < hw->mac.max_rx_queues; i++)
5134 ixgbevf_vlan_strip_queue_set(dev, i, on);
5139 ixgbe_vt_check(struct ixgbe_hw *hw)
5143 /* if Virtualization Technology is enabled */
5144 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5145 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5146 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5154 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5156 uint32_t vector = 0;
5158 switch (hw->mac.mc_filter_type) {
5159 case 0: /* use bits [47:36] of the address */
5160 vector = ((uc_addr->addr_bytes[4] >> 4) |
5161 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5163 case 1: /* use bits [46:35] of the address */
5164 vector = ((uc_addr->addr_bytes[4] >> 3) |
5165 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5167 case 2: /* use bits [45:34] of the address */
5168 vector = ((uc_addr->addr_bytes[4] >> 2) |
5169 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5171 case 3: /* use bits [43:32] of the address */
5172 vector = ((uc_addr->addr_bytes[4]) |
5173 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5175 default: /* Invalid mc_filter_type */
5179 /* vector can only be 12-bits or boundary will be exceeded */
5185 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5193 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5194 const uint32_t ixgbe_uta_bit_shift = 5;
5195 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5196 const uint32_t bit1 = 0x1;
5198 struct ixgbe_hw *hw =
5199 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5200 struct ixgbe_uta_info *uta_info =
5201 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5203 /* The UTA table only exists on 82599 hardware and newer */
5204 if (hw->mac.type < ixgbe_mac_82599EB)
5207 vector = ixgbe_uta_vector(hw, mac_addr);
5208 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5209 uta_shift = vector & ixgbe_uta_bit_mask;
5211 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5215 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5217 uta_info->uta_in_use++;
5218 reg_val |= (bit1 << uta_shift);
5219 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5221 uta_info->uta_in_use--;
5222 reg_val &= ~(bit1 << uta_shift);
5223 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5226 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5228 if (uta_info->uta_in_use > 0)
5229 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5230 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5232 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5238 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5241 struct ixgbe_hw *hw =
5242 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5243 struct ixgbe_uta_info *uta_info =
5244 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5246 /* The UTA table only exists on 82599 hardware and newer */
5247 if (hw->mac.type < ixgbe_mac_82599EB)
5251 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5252 uta_info->uta_shadow[i] = ~0;
5253 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5256 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5257 uta_info->uta_shadow[i] = 0;
5258 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5266 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5268 uint32_t new_val = orig_val;
5270 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5271 new_val |= IXGBE_VMOLR_AUPE;
5272 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5273 new_val |= IXGBE_VMOLR_ROMPE;
5274 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5275 new_val |= IXGBE_VMOLR_ROPE;
5276 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5277 new_val |= IXGBE_VMOLR_BAM;
5278 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5279 new_val |= IXGBE_VMOLR_MPE;
5284 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5285 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5286 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5287 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5288 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5289 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5290 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5293 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5294 struct rte_eth_mirror_conf *mirror_conf,
5295 uint8_t rule_id, uint8_t on)
5297 uint32_t mr_ctl, vlvf;
5298 uint32_t mp_lsb = 0;
5299 uint32_t mv_msb = 0;
5300 uint32_t mv_lsb = 0;
5301 uint32_t mp_msb = 0;
5304 uint64_t vlan_mask = 0;
5306 const uint8_t pool_mask_offset = 32;
5307 const uint8_t vlan_mask_offset = 32;
5308 const uint8_t dst_pool_offset = 8;
5309 const uint8_t rule_mr_offset = 4;
5310 const uint8_t mirror_rule_mask = 0x0F;
5312 struct ixgbe_mirror_info *mr_info =
5313 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5314 struct ixgbe_hw *hw =
5315 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5316 uint8_t mirror_type = 0;
5318 if (ixgbe_vt_check(hw) < 0)
5321 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5324 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5325 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5326 mirror_conf->rule_type);
5330 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5331 mirror_type |= IXGBE_MRCTL_VLME;
5332 /* Check if vlan id is valid and find conresponding VLAN ID
5335 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5336 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5337 /* search vlan id related pool vlan filter
5340 reg_index = ixgbe_find_vlvf_slot(
5342 mirror_conf->vlan.vlan_id[i],
5346 vlvf = IXGBE_READ_REG(hw,
5347 IXGBE_VLVF(reg_index));
5348 if ((vlvf & IXGBE_VLVF_VIEN) &&
5349 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5350 mirror_conf->vlan.vlan_id[i]))
5351 vlan_mask |= (1ULL << reg_index);
5358 mv_lsb = vlan_mask & 0xFFFFFFFF;
5359 mv_msb = vlan_mask >> vlan_mask_offset;
5361 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5362 mirror_conf->vlan.vlan_mask;
5363 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5364 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5365 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5366 mirror_conf->vlan.vlan_id[i];
5371 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5372 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5373 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5378 * if enable pool mirror, write related pool mask register,if disable
5379 * pool mirror, clear PFMRVM register
5381 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5382 mirror_type |= IXGBE_MRCTL_VPME;
5384 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5385 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5386 mr_info->mr_conf[rule_id].pool_mask =
5387 mirror_conf->pool_mask;
5392 mr_info->mr_conf[rule_id].pool_mask = 0;
5395 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5396 mirror_type |= IXGBE_MRCTL_UPME;
5397 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5398 mirror_type |= IXGBE_MRCTL_DPME;
5400 /* read mirror control register and recalculate it */
5401 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5404 mr_ctl |= mirror_type;
5405 mr_ctl &= mirror_rule_mask;
5406 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5408 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5411 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5412 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5414 /* write mirrror control register */
5415 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5417 /* write pool mirrror control register */
5418 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5419 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5420 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5423 /* write VLAN mirrror control register */
5424 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5425 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5426 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5434 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5437 uint32_t lsb_val = 0;
5438 uint32_t msb_val = 0;
5439 const uint8_t rule_mr_offset = 4;
5441 struct ixgbe_hw *hw =
5442 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5443 struct ixgbe_mirror_info *mr_info =
5444 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5446 if (ixgbe_vt_check(hw) < 0)
5449 memset(&mr_info->mr_conf[rule_id], 0,
5450 sizeof(struct rte_eth_mirror_conf));
5452 /* clear PFVMCTL register */
5453 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5455 /* clear pool mask register */
5456 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5457 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5459 /* clear vlan mask register */
5460 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5461 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5467 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5469 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5470 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5472 struct ixgbe_hw *hw =
5473 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5475 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5476 mask |= (1 << IXGBE_MISC_VEC_ID);
5477 RTE_SET_USED(queue_id);
5478 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5480 rte_intr_enable(intr_handle);
5486 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5489 struct ixgbe_hw *hw =
5490 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5492 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5493 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5494 RTE_SET_USED(queue_id);
5495 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5501 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5503 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5504 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5506 struct ixgbe_hw *hw =
5507 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5508 struct ixgbe_interrupt *intr =
5509 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5511 if (queue_id < 16) {
5512 ixgbe_disable_intr(hw);
5513 intr->mask |= (1 << queue_id);
5514 ixgbe_enable_intr(dev);
5515 } else if (queue_id < 32) {
5516 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5517 mask &= (1 << queue_id);
5518 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5519 } else if (queue_id < 64) {
5520 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5521 mask &= (1 << (queue_id - 32));
5522 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5524 rte_intr_enable(intr_handle);
5530 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5533 struct ixgbe_hw *hw =
5534 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5535 struct ixgbe_interrupt *intr =
5536 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5538 if (queue_id < 16) {
5539 ixgbe_disable_intr(hw);
5540 intr->mask &= ~(1 << queue_id);
5541 ixgbe_enable_intr(dev);
5542 } else if (queue_id < 32) {
5543 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5544 mask &= ~(1 << queue_id);
5545 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5546 } else if (queue_id < 64) {
5547 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5548 mask &= ~(1 << (queue_id - 32));
5549 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5556 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5557 uint8_t queue, uint8_t msix_vector)
5561 if (direction == -1) {
5563 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5564 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5567 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5569 /* rx or tx cause */
5570 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5571 idx = ((16 * (queue & 1)) + (8 * direction));
5572 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5573 tmp &= ~(0xFF << idx);
5574 tmp |= (msix_vector << idx);
5575 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5580 * set the IVAR registers, mapping interrupt causes to vectors
5582 * pointer to ixgbe_hw struct
5584 * 0 for Rx, 1 for Tx, -1 for other causes
5586 * queue to map the corresponding interrupt to
5588 * the vector to map to the corresponding queue
5591 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5592 uint8_t queue, uint8_t msix_vector)
5596 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5597 if (hw->mac.type == ixgbe_mac_82598EB) {
5598 if (direction == -1)
5600 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5601 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5602 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5603 tmp |= (msix_vector << (8 * (queue & 0x3)));
5604 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5605 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5606 (hw->mac.type == ixgbe_mac_X540)) {
5607 if (direction == -1) {
5609 idx = ((queue & 1) * 8);
5610 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5611 tmp &= ~(0xFF << idx);
5612 tmp |= (msix_vector << idx);
5613 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5615 /* rx or tx causes */
5616 idx = ((16 * (queue & 1)) + (8 * direction));
5617 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5618 tmp &= ~(0xFF << idx);
5619 tmp |= (msix_vector << idx);
5620 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5626 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5628 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5629 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5630 struct ixgbe_hw *hw =
5631 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5633 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5635 /* Configure VF other cause ivar */
5636 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5638 /* won't configure msix register if no mapping is done
5639 * between intr vector and event fd.
5641 if (!rte_intr_dp_is_en(intr_handle))
5644 /* Configure all RX queues of VF */
5645 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5646 /* Force all queue use vector 0,
5647 * as IXGBE_VF_MAXMSIVECOTR = 1
5649 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5650 intr_handle->intr_vec[q_idx] = vector_idx;
5655 * Sets up the hardware to properly generate MSI-X interrupts
5657 * board private structure
5660 ixgbe_configure_msix(struct rte_eth_dev *dev)
5662 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5663 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5664 struct ixgbe_hw *hw =
5665 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5666 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5667 uint32_t vec = IXGBE_MISC_VEC_ID;
5671 /* won't configure msix register if no mapping is done
5672 * between intr vector and event fd
5674 if (!rte_intr_dp_is_en(intr_handle))
5677 if (rte_intr_allow_others(intr_handle))
5678 vec = base = IXGBE_RX_VEC_START;
5680 /* setup GPIE for MSI-x mode */
5681 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5682 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5683 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5684 /* auto clearing and auto setting corresponding bits in EIMS
5685 * when MSI-X interrupt is triggered
5687 if (hw->mac.type == ixgbe_mac_82598EB) {
5688 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5690 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5691 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5693 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5695 /* Populate the IVAR table and set the ITR values to the
5696 * corresponding register.
5698 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5700 /* by default, 1:1 mapping */
5701 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5702 intr_handle->intr_vec[queue_id] = vec;
5703 if (vec < base + intr_handle->nb_efd - 1)
5707 switch (hw->mac.type) {
5708 case ixgbe_mac_82598EB:
5709 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5712 case ixgbe_mac_82599EB:
5713 case ixgbe_mac_X540:
5714 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5719 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5720 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5722 /* set up to autoclear timer, and the vectors */
5723 mask = IXGBE_EIMS_ENABLE_MASK;
5724 mask &= ~(IXGBE_EIMS_OTHER |
5725 IXGBE_EIMS_MAILBOX |
5728 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5731 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5732 uint16_t queue_idx, uint16_t tx_rate)
5734 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5735 uint32_t rf_dec, rf_int;
5737 uint16_t link_speed = dev->data->dev_link.link_speed;
5739 if (queue_idx >= hw->mac.max_tx_queues)
5743 /* Calculate the rate factor values to set */
5744 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5745 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5746 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5748 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5749 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5750 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5751 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5757 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5758 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5761 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5762 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5763 IXGBE_MAX_JUMBO_FRAME_SIZE))
5764 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5765 IXGBE_MMW_SIZE_JUMBO_FRAME);
5767 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5768 IXGBE_MMW_SIZE_DEFAULT);
5770 /* Set RTTBCNRC of queue X */
5771 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5772 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5773 IXGBE_WRITE_FLUSH(hw);
5779 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5780 __attribute__((unused)) uint32_t index,
5781 __attribute__((unused)) uint32_t pool)
5783 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5787 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5788 * operation. Trap this case to avoid exhausting the [very limited]
5789 * set of PF resources used to store VF MAC addresses.
5791 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5793 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5795 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5796 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5797 mac_addr->addr_bytes[0],
5798 mac_addr->addr_bytes[1],
5799 mac_addr->addr_bytes[2],
5800 mac_addr->addr_bytes[3],
5801 mac_addr->addr_bytes[4],
5802 mac_addr->addr_bytes[5],
5808 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5810 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5811 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5812 struct ether_addr *mac_addr;
5817 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5818 * not support the deletion of a given MAC address.
5819 * Instead, it imposes to delete all MAC addresses, then to add again
5820 * all MAC addresses with the exception of the one to be deleted.
5822 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5825 * Add again all MAC addresses, with the exception of the deleted one
5826 * and of the permanent MAC address.
5828 for (i = 0, mac_addr = dev->data->mac_addrs;
5829 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5830 /* Skip the deleted MAC address */
5833 /* Skip NULL MAC addresses */
5834 if (is_zero_ether_addr(mac_addr))
5836 /* Skip the permanent MAC address */
5837 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5839 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5842 "Adding again MAC address "
5843 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5845 mac_addr->addr_bytes[0],
5846 mac_addr->addr_bytes[1],
5847 mac_addr->addr_bytes[2],
5848 mac_addr->addr_bytes[3],
5849 mac_addr->addr_bytes[4],
5850 mac_addr->addr_bytes[5],
5856 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5860 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5864 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5865 struct rte_eth_syn_filter *filter,
5868 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5869 struct ixgbe_filter_info *filter_info =
5870 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5874 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5877 syn_info = filter_info->syn_info;
5880 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5882 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5883 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5885 if (filter->hig_pri)
5886 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5888 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5890 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5891 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5893 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5896 filter_info->syn_info = synqf;
5897 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5898 IXGBE_WRITE_FLUSH(hw);
5903 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5904 struct rte_eth_syn_filter *filter)
5906 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5907 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5909 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5910 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5911 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5918 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5919 enum rte_filter_op filter_op,
5922 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5925 MAC_TYPE_FILTER_SUP(hw->mac.type);
5927 if (filter_op == RTE_ETH_FILTER_NOP)
5931 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5936 switch (filter_op) {
5937 case RTE_ETH_FILTER_ADD:
5938 ret = ixgbe_syn_filter_set(dev,
5939 (struct rte_eth_syn_filter *)arg,
5942 case RTE_ETH_FILTER_DELETE:
5943 ret = ixgbe_syn_filter_set(dev,
5944 (struct rte_eth_syn_filter *)arg,
5947 case RTE_ETH_FILTER_GET:
5948 ret = ixgbe_syn_filter_get(dev,
5949 (struct rte_eth_syn_filter *)arg);
5952 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5961 static inline enum ixgbe_5tuple_protocol
5962 convert_protocol_type(uint8_t protocol_value)
5964 if (protocol_value == IPPROTO_TCP)
5965 return IXGBE_FILTER_PROTOCOL_TCP;
5966 else if (protocol_value == IPPROTO_UDP)
5967 return IXGBE_FILTER_PROTOCOL_UDP;
5968 else if (protocol_value == IPPROTO_SCTP)
5969 return IXGBE_FILTER_PROTOCOL_SCTP;
5971 return IXGBE_FILTER_PROTOCOL_NONE;
5974 /* inject a 5-tuple filter to HW */
5976 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5977 struct ixgbe_5tuple_filter *filter)
5979 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5981 uint32_t ftqf, sdpqf;
5982 uint32_t l34timir = 0;
5983 uint8_t mask = 0xff;
5987 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5988 IXGBE_SDPQF_DSTPORT_SHIFT);
5989 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5991 ftqf = (uint32_t)(filter->filter_info.proto &
5992 IXGBE_FTQF_PROTOCOL_MASK);
5993 ftqf |= (uint32_t)((filter->filter_info.priority &
5994 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5995 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5996 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5997 if (filter->filter_info.dst_ip_mask == 0)
5998 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5999 if (filter->filter_info.src_port_mask == 0)
6000 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6001 if (filter->filter_info.dst_port_mask == 0)
6002 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6003 if (filter->filter_info.proto_mask == 0)
6004 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6005 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6006 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6007 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6009 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6010 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6011 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6012 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6014 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6015 l34timir |= (uint32_t)(filter->queue <<
6016 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6017 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6021 * add a 5tuple filter
6024 * dev: Pointer to struct rte_eth_dev.
6025 * index: the index the filter allocates.
6026 * filter: ponter to the filter that will be added.
6027 * rx_queue: the queue id the filter assigned to.
6030 * - On success, zero.
6031 * - On failure, a negative value.
6034 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6035 struct ixgbe_5tuple_filter *filter)
6037 struct ixgbe_filter_info *filter_info =
6038 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6042 * look for an unused 5tuple filter index,
6043 * and insert the filter to list.
6045 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6046 idx = i / (sizeof(uint32_t) * NBBY);
6047 shift = i % (sizeof(uint32_t) * NBBY);
6048 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6049 filter_info->fivetuple_mask[idx] |= 1 << shift;
6051 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6057 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6058 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6062 ixgbe_inject_5tuple_filter(dev, filter);
6068 * remove a 5tuple filter
6071 * dev: Pointer to struct rte_eth_dev.
6072 * filter: the pointer of the filter will be removed.
6075 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6076 struct ixgbe_5tuple_filter *filter)
6078 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6079 struct ixgbe_filter_info *filter_info =
6080 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6081 uint16_t index = filter->index;
6083 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6084 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6085 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6088 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6089 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6090 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6091 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6092 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6096 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6098 struct ixgbe_hw *hw;
6099 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6100 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6102 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6104 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6107 /* refuse mtu that requires the support of scattered packets when this
6108 * feature has not been enabled before.
6110 if (!rx_conf->enable_scatter &&
6111 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6112 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6116 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6117 * request of the version 2.0 of the mailbox API.
6118 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6119 * of the mailbox API.
6120 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6121 * prior to 3.11.33 which contains the following change:
6122 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6124 ixgbevf_rlpml_set_vf(hw, max_frame);
6126 /* update max frame size */
6127 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6131 static inline struct ixgbe_5tuple_filter *
6132 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6133 struct ixgbe_5tuple_filter_info *key)
6135 struct ixgbe_5tuple_filter *it;
6137 TAILQ_FOREACH(it, filter_list, entries) {
6138 if (memcmp(key, &it->filter_info,
6139 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6146 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6148 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6149 struct ixgbe_5tuple_filter_info *filter_info)
6151 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6152 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6153 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6156 switch (filter->dst_ip_mask) {
6158 filter_info->dst_ip_mask = 0;
6159 filter_info->dst_ip = filter->dst_ip;
6162 filter_info->dst_ip_mask = 1;
6165 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6169 switch (filter->src_ip_mask) {
6171 filter_info->src_ip_mask = 0;
6172 filter_info->src_ip = filter->src_ip;
6175 filter_info->src_ip_mask = 1;
6178 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6182 switch (filter->dst_port_mask) {
6184 filter_info->dst_port_mask = 0;
6185 filter_info->dst_port = filter->dst_port;
6188 filter_info->dst_port_mask = 1;
6191 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6195 switch (filter->src_port_mask) {
6197 filter_info->src_port_mask = 0;
6198 filter_info->src_port = filter->src_port;
6201 filter_info->src_port_mask = 1;
6204 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6208 switch (filter->proto_mask) {
6210 filter_info->proto_mask = 0;
6211 filter_info->proto =
6212 convert_protocol_type(filter->proto);
6215 filter_info->proto_mask = 1;
6218 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6222 filter_info->priority = (uint8_t)filter->priority;
6227 * add or delete a ntuple filter
6230 * dev: Pointer to struct rte_eth_dev.
6231 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6232 * add: if true, add filter, if false, remove filter
6235 * - On success, zero.
6236 * - On failure, a negative value.
6239 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6240 struct rte_eth_ntuple_filter *ntuple_filter,
6243 struct ixgbe_filter_info *filter_info =
6244 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6245 struct ixgbe_5tuple_filter_info filter_5tuple;
6246 struct ixgbe_5tuple_filter *filter;
6249 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6250 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6254 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6255 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6259 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6261 if (filter != NULL && add) {
6262 PMD_DRV_LOG(ERR, "filter exists.");
6265 if (filter == NULL && !add) {
6266 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6271 filter = rte_zmalloc("ixgbe_5tuple_filter",
6272 sizeof(struct ixgbe_5tuple_filter), 0);
6275 (void)rte_memcpy(&filter->filter_info,
6277 sizeof(struct ixgbe_5tuple_filter_info));
6278 filter->queue = ntuple_filter->queue;
6279 ret = ixgbe_add_5tuple_filter(dev, filter);
6285 ixgbe_remove_5tuple_filter(dev, filter);
6291 * get a ntuple filter
6294 * dev: Pointer to struct rte_eth_dev.
6295 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6298 * - On success, zero.
6299 * - On failure, a negative value.
6302 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6303 struct rte_eth_ntuple_filter *ntuple_filter)
6305 struct ixgbe_filter_info *filter_info =
6306 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6307 struct ixgbe_5tuple_filter_info filter_5tuple;
6308 struct ixgbe_5tuple_filter *filter;
6311 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6312 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6316 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6317 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6321 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6323 if (filter == NULL) {
6324 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6327 ntuple_filter->queue = filter->queue;
6332 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6333 * @dev: pointer to rte_eth_dev structure
6334 * @filter_op:operation will be taken.
6335 * @arg: a pointer to specific structure corresponding to the filter_op
6338 * - On success, zero.
6339 * - On failure, a negative value.
6342 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6343 enum rte_filter_op filter_op,
6346 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6349 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6351 if (filter_op == RTE_ETH_FILTER_NOP)
6355 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6360 switch (filter_op) {
6361 case RTE_ETH_FILTER_ADD:
6362 ret = ixgbe_add_del_ntuple_filter(dev,
6363 (struct rte_eth_ntuple_filter *)arg,
6366 case RTE_ETH_FILTER_DELETE:
6367 ret = ixgbe_add_del_ntuple_filter(dev,
6368 (struct rte_eth_ntuple_filter *)arg,
6371 case RTE_ETH_FILTER_GET:
6372 ret = ixgbe_get_ntuple_filter(dev,
6373 (struct rte_eth_ntuple_filter *)arg);
6376 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6384 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6385 struct rte_eth_ethertype_filter *filter,
6388 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6389 struct ixgbe_filter_info *filter_info =
6390 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6394 struct ixgbe_ethertype_filter ethertype_filter;
6396 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6399 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6400 filter->ether_type == ETHER_TYPE_IPv6) {
6401 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6402 " ethertype filter.", filter->ether_type);
6406 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6407 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6410 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6411 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6415 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6416 if (ret >= 0 && add) {
6417 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6418 filter->ether_type);
6421 if (ret < 0 && !add) {
6422 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6423 filter->ether_type);
6428 etqf = IXGBE_ETQF_FILTER_EN;
6429 etqf |= (uint32_t)filter->ether_type;
6430 etqs |= (uint32_t)((filter->queue <<
6431 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6432 IXGBE_ETQS_RX_QUEUE);
6433 etqs |= IXGBE_ETQS_QUEUE_EN;
6435 ethertype_filter.ethertype = filter->ether_type;
6436 ethertype_filter.etqf = etqf;
6437 ethertype_filter.etqs = etqs;
6438 ethertype_filter.conf = FALSE;
6439 ret = ixgbe_ethertype_filter_insert(filter_info,
6442 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6446 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6450 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6451 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6452 IXGBE_WRITE_FLUSH(hw);
6458 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6459 struct rte_eth_ethertype_filter *filter)
6461 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6462 struct ixgbe_filter_info *filter_info =
6463 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6464 uint32_t etqf, etqs;
6467 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6469 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6470 filter->ether_type);
6474 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6475 if (etqf & IXGBE_ETQF_FILTER_EN) {
6476 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6477 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6479 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6480 IXGBE_ETQS_RX_QUEUE_SHIFT;
6487 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6488 * @dev: pointer to rte_eth_dev structure
6489 * @filter_op:operation will be taken.
6490 * @arg: a pointer to specific structure corresponding to the filter_op
6493 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6494 enum rte_filter_op filter_op,
6497 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6500 MAC_TYPE_FILTER_SUP(hw->mac.type);
6502 if (filter_op == RTE_ETH_FILTER_NOP)
6506 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6511 switch (filter_op) {
6512 case RTE_ETH_FILTER_ADD:
6513 ret = ixgbe_add_del_ethertype_filter(dev,
6514 (struct rte_eth_ethertype_filter *)arg,
6517 case RTE_ETH_FILTER_DELETE:
6518 ret = ixgbe_add_del_ethertype_filter(dev,
6519 (struct rte_eth_ethertype_filter *)arg,
6522 case RTE_ETH_FILTER_GET:
6523 ret = ixgbe_get_ethertype_filter(dev,
6524 (struct rte_eth_ethertype_filter *)arg);
6527 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6535 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6536 enum rte_filter_type filter_type,
6537 enum rte_filter_op filter_op,
6542 switch (filter_type) {
6543 case RTE_ETH_FILTER_NTUPLE:
6544 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6546 case RTE_ETH_FILTER_ETHERTYPE:
6547 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6549 case RTE_ETH_FILTER_SYN:
6550 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6552 case RTE_ETH_FILTER_FDIR:
6553 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6555 case RTE_ETH_FILTER_L2_TUNNEL:
6556 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6558 case RTE_ETH_FILTER_GENERIC:
6559 if (filter_op != RTE_ETH_FILTER_GET)
6561 *(const void **)arg = &ixgbe_flow_ops;
6564 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6574 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6575 u8 **mc_addr_ptr, u32 *vmdq)
6580 mc_addr = *mc_addr_ptr;
6581 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6586 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6587 struct ether_addr *mc_addr_set,
6588 uint32_t nb_mc_addr)
6590 struct ixgbe_hw *hw;
6593 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6594 mc_addr_list = (u8 *)mc_addr_set;
6595 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6596 ixgbe_dev_addr_list_itr, TRUE);
6600 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6602 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6603 uint64_t systime_cycles;
6605 switch (hw->mac.type) {
6606 case ixgbe_mac_X550:
6607 case ixgbe_mac_X550EM_x:
6608 case ixgbe_mac_X550EM_a:
6609 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6610 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6611 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6615 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6616 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6620 return systime_cycles;
6624 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6626 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6627 uint64_t rx_tstamp_cycles;
6629 switch (hw->mac.type) {
6630 case ixgbe_mac_X550:
6631 case ixgbe_mac_X550EM_x:
6632 case ixgbe_mac_X550EM_a:
6633 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6634 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6635 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6639 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6640 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6641 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6645 return rx_tstamp_cycles;
6649 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6651 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6652 uint64_t tx_tstamp_cycles;
6654 switch (hw->mac.type) {
6655 case ixgbe_mac_X550:
6656 case ixgbe_mac_X550EM_x:
6657 case ixgbe_mac_X550EM_a:
6658 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6659 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6660 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6664 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6665 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6666 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6670 return tx_tstamp_cycles;
6674 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6676 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6677 struct ixgbe_adapter *adapter =
6678 (struct ixgbe_adapter *)dev->data->dev_private;
6679 struct rte_eth_link link;
6680 uint32_t incval = 0;
6683 /* Get current link speed. */
6684 memset(&link, 0, sizeof(link));
6685 ixgbe_dev_link_update(dev, 1);
6686 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6688 switch (link.link_speed) {
6689 case ETH_SPEED_NUM_100M:
6690 incval = IXGBE_INCVAL_100;
6691 shift = IXGBE_INCVAL_SHIFT_100;
6693 case ETH_SPEED_NUM_1G:
6694 incval = IXGBE_INCVAL_1GB;
6695 shift = IXGBE_INCVAL_SHIFT_1GB;
6697 case ETH_SPEED_NUM_10G:
6699 incval = IXGBE_INCVAL_10GB;
6700 shift = IXGBE_INCVAL_SHIFT_10GB;
6704 switch (hw->mac.type) {
6705 case ixgbe_mac_X550:
6706 case ixgbe_mac_X550EM_x:
6707 case ixgbe_mac_X550EM_a:
6708 /* Independent of link speed. */
6710 /* Cycles read will be interpreted as ns. */
6713 case ixgbe_mac_X540:
6714 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6716 case ixgbe_mac_82599EB:
6717 incval >>= IXGBE_INCVAL_SHIFT_82599;
6718 shift -= IXGBE_INCVAL_SHIFT_82599;
6719 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6720 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6723 /* Not supported. */
6727 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6728 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6729 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6731 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6732 adapter->systime_tc.cc_shift = shift;
6733 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6735 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6736 adapter->rx_tstamp_tc.cc_shift = shift;
6737 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6739 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6740 adapter->tx_tstamp_tc.cc_shift = shift;
6741 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6745 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6747 struct ixgbe_adapter *adapter =
6748 (struct ixgbe_adapter *)dev->data->dev_private;
6750 adapter->systime_tc.nsec += delta;
6751 adapter->rx_tstamp_tc.nsec += delta;
6752 adapter->tx_tstamp_tc.nsec += delta;
6758 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6761 struct ixgbe_adapter *adapter =
6762 (struct ixgbe_adapter *)dev->data->dev_private;
6764 ns = rte_timespec_to_ns(ts);
6765 /* Set the timecounters to a new value. */
6766 adapter->systime_tc.nsec = ns;
6767 adapter->rx_tstamp_tc.nsec = ns;
6768 adapter->tx_tstamp_tc.nsec = ns;
6774 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6776 uint64_t ns, systime_cycles;
6777 struct ixgbe_adapter *adapter =
6778 (struct ixgbe_adapter *)dev->data->dev_private;
6780 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6781 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6782 *ts = rte_ns_to_timespec(ns);
6788 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6790 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6794 /* Stop the timesync system time. */
6795 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6796 /* Reset the timesync system time value. */
6797 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6798 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6800 /* Enable system time for platforms where it isn't on by default. */
6801 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6802 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6803 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6805 ixgbe_start_timecounters(dev);
6807 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6808 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6810 IXGBE_ETQF_FILTER_EN |
6813 /* Enable timestamping of received PTP packets. */
6814 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6815 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6816 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6818 /* Enable timestamping of transmitted PTP packets. */
6819 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6820 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6821 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6823 IXGBE_WRITE_FLUSH(hw);
6829 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6831 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6834 /* Disable timestamping of transmitted PTP packets. */
6835 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6836 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6837 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6839 /* Disable timestamping of received PTP packets. */
6840 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6841 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6842 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6844 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6845 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6847 /* Stop incrementating the System Time registers. */
6848 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6854 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6855 struct timespec *timestamp,
6856 uint32_t flags __rte_unused)
6858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6859 struct ixgbe_adapter *adapter =
6860 (struct ixgbe_adapter *)dev->data->dev_private;
6861 uint32_t tsync_rxctl;
6862 uint64_t rx_tstamp_cycles;
6865 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6866 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6869 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6870 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6871 *timestamp = rte_ns_to_timespec(ns);
6877 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6878 struct timespec *timestamp)
6880 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6881 struct ixgbe_adapter *adapter =
6882 (struct ixgbe_adapter *)dev->data->dev_private;
6883 uint32_t tsync_txctl;
6884 uint64_t tx_tstamp_cycles;
6887 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6888 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6891 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6892 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6893 *timestamp = rte_ns_to_timespec(ns);
6899 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6901 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6904 const struct reg_info *reg_group;
6905 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6906 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6908 while ((reg_group = reg_set[g_ind++]))
6909 count += ixgbe_regs_group_count(reg_group);
6915 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6919 const struct reg_info *reg_group;
6921 while ((reg_group = ixgbevf_regs[g_ind++]))
6922 count += ixgbe_regs_group_count(reg_group);
6928 ixgbe_get_regs(struct rte_eth_dev *dev,
6929 struct rte_dev_reg_info *regs)
6931 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6932 uint32_t *data = regs->data;
6935 const struct reg_info *reg_group;
6936 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6937 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6940 regs->length = ixgbe_get_reg_length(dev);
6941 regs->width = sizeof(uint32_t);
6945 /* Support only full register dump */
6946 if ((regs->length == 0) ||
6947 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6948 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6950 while ((reg_group = reg_set[g_ind++]))
6951 count += ixgbe_read_regs_group(dev, &data[count],
6960 ixgbevf_get_regs(struct rte_eth_dev *dev,
6961 struct rte_dev_reg_info *regs)
6963 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6964 uint32_t *data = regs->data;
6967 const struct reg_info *reg_group;
6970 regs->length = ixgbevf_get_reg_length(dev);
6971 regs->width = sizeof(uint32_t);
6975 /* Support only full register dump */
6976 if ((regs->length == 0) ||
6977 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6978 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6980 while ((reg_group = ixgbevf_regs[g_ind++]))
6981 count += ixgbe_read_regs_group(dev, &data[count],
6990 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6992 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6994 /* Return unit is byte count */
6995 return hw->eeprom.word_size * 2;
6999 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7000 struct rte_dev_eeprom_info *in_eeprom)
7002 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7003 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7004 uint16_t *data = in_eeprom->data;
7007 first = in_eeprom->offset >> 1;
7008 length = in_eeprom->length >> 1;
7009 if ((first > hw->eeprom.word_size) ||
7010 ((first + length) > hw->eeprom.word_size))
7013 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7015 return eeprom->ops.read_buffer(hw, first, length, data);
7019 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7020 struct rte_dev_eeprom_info *in_eeprom)
7022 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7023 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7024 uint16_t *data = in_eeprom->data;
7027 first = in_eeprom->offset >> 1;
7028 length = in_eeprom->length >> 1;
7029 if ((first > hw->eeprom.word_size) ||
7030 ((first + length) > hw->eeprom.word_size))
7033 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7035 return eeprom->ops.write_buffer(hw, first, length, data);
7039 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7041 case ixgbe_mac_X550:
7042 case ixgbe_mac_X550EM_x:
7043 case ixgbe_mac_X550EM_a:
7044 return ETH_RSS_RETA_SIZE_512;
7045 case ixgbe_mac_X550_vf:
7046 case ixgbe_mac_X550EM_x_vf:
7047 case ixgbe_mac_X550EM_a_vf:
7048 return ETH_RSS_RETA_SIZE_64;
7050 return ETH_RSS_RETA_SIZE_128;
7055 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7057 case ixgbe_mac_X550:
7058 case ixgbe_mac_X550EM_x:
7059 case ixgbe_mac_X550EM_a:
7060 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7061 return IXGBE_RETA(reta_idx >> 2);
7063 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7064 case ixgbe_mac_X550_vf:
7065 case ixgbe_mac_X550EM_x_vf:
7066 case ixgbe_mac_X550EM_a_vf:
7067 return IXGBE_VFRETA(reta_idx >> 2);
7069 return IXGBE_RETA(reta_idx >> 2);
7074 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7076 case ixgbe_mac_X550_vf:
7077 case ixgbe_mac_X550EM_x_vf:
7078 case ixgbe_mac_X550EM_a_vf:
7079 return IXGBE_VFMRQC;
7086 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7088 case ixgbe_mac_X550_vf:
7089 case ixgbe_mac_X550EM_x_vf:
7090 case ixgbe_mac_X550EM_a_vf:
7091 return IXGBE_VFRSSRK(i);
7093 return IXGBE_RSSRK(i);
7098 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7100 case ixgbe_mac_82599_vf:
7101 case ixgbe_mac_X540_vf:
7109 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7110 struct rte_eth_dcb_info *dcb_info)
7112 struct ixgbe_dcb_config *dcb_config =
7113 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7114 struct ixgbe_dcb_tc_config *tc;
7117 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7118 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7120 dcb_info->nb_tcs = 1;
7122 if (dcb_config->vt_mode) { /* vt is enabled*/
7123 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7124 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7125 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7126 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7127 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7128 for (j = 0; j < dcb_info->nb_tcs; j++) {
7129 dcb_info->tc_queue.tc_rxq[i][j].base =
7130 i * dcb_info->nb_tcs + j;
7131 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7132 dcb_info->tc_queue.tc_txq[i][j].base =
7133 i * dcb_info->nb_tcs + j;
7134 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7137 } else { /* vt is disabled*/
7138 struct rte_eth_dcb_rx_conf *rx_conf =
7139 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7140 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7141 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7142 if (dcb_info->nb_tcs == ETH_4_TCS) {
7143 for (i = 0; i < dcb_info->nb_tcs; i++) {
7144 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7145 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7147 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7148 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7149 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7150 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7151 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7152 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7153 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7154 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7155 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7156 for (i = 0; i < dcb_info->nb_tcs; i++) {
7157 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7158 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7160 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7161 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7162 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7163 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7164 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7165 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7166 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7167 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7168 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7169 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7170 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7171 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7172 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7173 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7174 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7175 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7178 for (i = 0; i < dcb_info->nb_tcs; i++) {
7179 tc = &dcb_config->tc_config[i];
7180 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7185 /* Update e-tag ether type */
7187 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7188 uint16_t ether_type)
7190 uint32_t etag_etype;
7192 if (hw->mac.type != ixgbe_mac_X550 &&
7193 hw->mac.type != ixgbe_mac_X550EM_x &&
7194 hw->mac.type != ixgbe_mac_X550EM_a) {
7198 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7199 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7200 etag_etype |= ether_type;
7201 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7202 IXGBE_WRITE_FLUSH(hw);
7207 /* Config l2 tunnel ether type */
7209 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7210 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7213 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7214 struct ixgbe_l2_tn_info *l2_tn_info =
7215 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7217 if (l2_tunnel == NULL)
7220 switch (l2_tunnel->l2_tunnel_type) {
7221 case RTE_L2_TUNNEL_TYPE_E_TAG:
7222 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7223 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7226 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7234 /* Enable e-tag tunnel */
7236 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7238 uint32_t etag_etype;
7240 if (hw->mac.type != ixgbe_mac_X550 &&
7241 hw->mac.type != ixgbe_mac_X550EM_x &&
7242 hw->mac.type != ixgbe_mac_X550EM_a) {
7246 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7247 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7248 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7249 IXGBE_WRITE_FLUSH(hw);
7254 /* Enable l2 tunnel */
7256 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7257 enum rte_eth_tunnel_type l2_tunnel_type)
7260 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7261 struct ixgbe_l2_tn_info *l2_tn_info =
7262 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7264 switch (l2_tunnel_type) {
7265 case RTE_L2_TUNNEL_TYPE_E_TAG:
7266 l2_tn_info->e_tag_en = TRUE;
7267 ret = ixgbe_e_tag_enable(hw);
7270 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7278 /* Disable e-tag tunnel */
7280 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7282 uint32_t etag_etype;
7284 if (hw->mac.type != ixgbe_mac_X550 &&
7285 hw->mac.type != ixgbe_mac_X550EM_x &&
7286 hw->mac.type != ixgbe_mac_X550EM_a) {
7290 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7291 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7292 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7293 IXGBE_WRITE_FLUSH(hw);
7298 /* Disable l2 tunnel */
7300 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7301 enum rte_eth_tunnel_type l2_tunnel_type)
7304 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7305 struct ixgbe_l2_tn_info *l2_tn_info =
7306 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7308 switch (l2_tunnel_type) {
7309 case RTE_L2_TUNNEL_TYPE_E_TAG:
7310 l2_tn_info->e_tag_en = FALSE;
7311 ret = ixgbe_e_tag_disable(hw);
7314 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7323 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7324 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7327 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7328 uint32_t i, rar_entries;
7329 uint32_t rar_low, rar_high;
7331 if (hw->mac.type != ixgbe_mac_X550 &&
7332 hw->mac.type != ixgbe_mac_X550EM_x &&
7333 hw->mac.type != ixgbe_mac_X550EM_a) {
7337 rar_entries = ixgbe_get_num_rx_addrs(hw);
7339 for (i = 1; i < rar_entries; i++) {
7340 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7341 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7342 if ((rar_high & IXGBE_RAH_AV) &&
7343 (rar_high & IXGBE_RAH_ADTYPE) &&
7344 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7345 l2_tunnel->tunnel_id)) {
7346 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7347 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7349 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7359 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7360 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7363 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7364 uint32_t i, rar_entries;
7365 uint32_t rar_low, rar_high;
7367 if (hw->mac.type != ixgbe_mac_X550 &&
7368 hw->mac.type != ixgbe_mac_X550EM_x &&
7369 hw->mac.type != ixgbe_mac_X550EM_a) {
7373 /* One entry for one tunnel. Try to remove potential existing entry. */
7374 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7376 rar_entries = ixgbe_get_num_rx_addrs(hw);
7378 for (i = 1; i < rar_entries; i++) {
7379 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7380 if (rar_high & IXGBE_RAH_AV) {
7383 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7384 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7385 rar_low = l2_tunnel->tunnel_id;
7387 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7388 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7394 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7395 " Please remove a rule before adding a new one.");
7399 static inline struct ixgbe_l2_tn_filter *
7400 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7401 struct ixgbe_l2_tn_key *key)
7405 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7409 return l2_tn_info->hash_map[ret];
7413 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7414 struct ixgbe_l2_tn_filter *l2_tn_filter)
7418 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7419 &l2_tn_filter->key);
7423 "Failed to insert L2 tunnel filter"
7424 " to hash table %d!",
7429 l2_tn_info->hash_map[ret] = l2_tn_filter;
7431 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7437 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7438 struct ixgbe_l2_tn_key *key)
7441 struct ixgbe_l2_tn_filter *l2_tn_filter;
7443 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7447 "No such L2 tunnel filter to delete %d!",
7452 l2_tn_filter = l2_tn_info->hash_map[ret];
7453 l2_tn_info->hash_map[ret] = NULL;
7455 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7456 rte_free(l2_tn_filter);
7461 /* Add l2 tunnel filter */
7463 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7464 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7468 struct ixgbe_l2_tn_info *l2_tn_info =
7469 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7470 struct ixgbe_l2_tn_key key;
7471 struct ixgbe_l2_tn_filter *node;
7474 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7475 key.tn_id = l2_tunnel->tunnel_id;
7477 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7481 "The L2 tunnel filter already exists!");
7485 node = rte_zmalloc("ixgbe_l2_tn",
7486 sizeof(struct ixgbe_l2_tn_filter),
7491 (void)rte_memcpy(&node->key,
7493 sizeof(struct ixgbe_l2_tn_key));
7494 node->pool = l2_tunnel->pool;
7495 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7502 switch (l2_tunnel->l2_tunnel_type) {
7503 case RTE_L2_TUNNEL_TYPE_E_TAG:
7504 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7507 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7512 if ((!restore) && (ret < 0))
7513 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7518 /* Delete l2 tunnel filter */
7520 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7521 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7524 struct ixgbe_l2_tn_info *l2_tn_info =
7525 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7526 struct ixgbe_l2_tn_key key;
7528 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7529 key.tn_id = l2_tunnel->tunnel_id;
7530 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7534 switch (l2_tunnel->l2_tunnel_type) {
7535 case RTE_L2_TUNNEL_TYPE_E_TAG:
7536 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7539 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7548 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7549 * @dev: pointer to rte_eth_dev structure
7550 * @filter_op:operation will be taken.
7551 * @arg: a pointer to specific structure corresponding to the filter_op
7554 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7555 enum rte_filter_op filter_op,
7560 if (filter_op == RTE_ETH_FILTER_NOP)
7564 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7569 switch (filter_op) {
7570 case RTE_ETH_FILTER_ADD:
7571 ret = ixgbe_dev_l2_tunnel_filter_add
7573 (struct rte_eth_l2_tunnel_conf *)arg,
7576 case RTE_ETH_FILTER_DELETE:
7577 ret = ixgbe_dev_l2_tunnel_filter_del
7579 (struct rte_eth_l2_tunnel_conf *)arg);
7582 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7590 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7594 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7596 if (hw->mac.type != ixgbe_mac_X550 &&
7597 hw->mac.type != ixgbe_mac_X550EM_x &&
7598 hw->mac.type != ixgbe_mac_X550EM_a) {
7602 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7603 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7605 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7606 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7611 /* Enable l2 tunnel forwarding */
7613 ixgbe_dev_l2_tunnel_forwarding_enable
7614 (struct rte_eth_dev *dev,
7615 enum rte_eth_tunnel_type l2_tunnel_type)
7617 struct ixgbe_l2_tn_info *l2_tn_info =
7618 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7621 switch (l2_tunnel_type) {
7622 case RTE_L2_TUNNEL_TYPE_E_TAG:
7623 l2_tn_info->e_tag_fwd_en = TRUE;
7624 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7627 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7635 /* Disable l2 tunnel forwarding */
7637 ixgbe_dev_l2_tunnel_forwarding_disable
7638 (struct rte_eth_dev *dev,
7639 enum rte_eth_tunnel_type l2_tunnel_type)
7641 struct ixgbe_l2_tn_info *l2_tn_info =
7642 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7645 switch (l2_tunnel_type) {
7646 case RTE_L2_TUNNEL_TYPE_E_TAG:
7647 l2_tn_info->e_tag_fwd_en = FALSE;
7648 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7651 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7660 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7661 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7664 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7666 uint32_t vmtir, vmvir;
7667 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7669 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7671 "VF id %u should be less than %u",
7677 if (hw->mac.type != ixgbe_mac_X550 &&
7678 hw->mac.type != ixgbe_mac_X550EM_x &&
7679 hw->mac.type != ixgbe_mac_X550EM_a) {
7684 vmtir = l2_tunnel->tunnel_id;
7688 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7690 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7691 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7693 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7694 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7699 /* Enable l2 tunnel tag insertion */
7701 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7702 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7706 switch (l2_tunnel->l2_tunnel_type) {
7707 case RTE_L2_TUNNEL_TYPE_E_TAG:
7708 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7711 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7719 /* Disable l2 tunnel tag insertion */
7721 ixgbe_dev_l2_tunnel_insertion_disable
7722 (struct rte_eth_dev *dev,
7723 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7727 switch (l2_tunnel->l2_tunnel_type) {
7728 case RTE_L2_TUNNEL_TYPE_E_TAG:
7729 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7732 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7741 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7746 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7748 if (hw->mac.type != ixgbe_mac_X550 &&
7749 hw->mac.type != ixgbe_mac_X550EM_x &&
7750 hw->mac.type != ixgbe_mac_X550EM_a) {
7754 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7756 qde |= IXGBE_QDE_STRIP_TAG;
7758 qde &= ~IXGBE_QDE_STRIP_TAG;
7759 qde &= ~IXGBE_QDE_READ;
7760 qde |= IXGBE_QDE_WRITE;
7761 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7766 /* Enable l2 tunnel tag stripping */
7768 ixgbe_dev_l2_tunnel_stripping_enable
7769 (struct rte_eth_dev *dev,
7770 enum rte_eth_tunnel_type l2_tunnel_type)
7774 switch (l2_tunnel_type) {
7775 case RTE_L2_TUNNEL_TYPE_E_TAG:
7776 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7779 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7787 /* Disable l2 tunnel tag stripping */
7789 ixgbe_dev_l2_tunnel_stripping_disable
7790 (struct rte_eth_dev *dev,
7791 enum rte_eth_tunnel_type l2_tunnel_type)
7795 switch (l2_tunnel_type) {
7796 case RTE_L2_TUNNEL_TYPE_E_TAG:
7797 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7800 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7808 /* Enable/disable l2 tunnel offload functions */
7810 ixgbe_dev_l2_tunnel_offload_set
7811 (struct rte_eth_dev *dev,
7812 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7818 if (l2_tunnel == NULL)
7822 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7824 ret = ixgbe_dev_l2_tunnel_enable(
7826 l2_tunnel->l2_tunnel_type);
7828 ret = ixgbe_dev_l2_tunnel_disable(
7830 l2_tunnel->l2_tunnel_type);
7833 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7835 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7839 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7844 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7846 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7848 l2_tunnel->l2_tunnel_type);
7850 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7852 l2_tunnel->l2_tunnel_type);
7855 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7857 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7859 l2_tunnel->l2_tunnel_type);
7861 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7863 l2_tunnel->l2_tunnel_type);
7870 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7873 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7874 IXGBE_WRITE_FLUSH(hw);
7879 /* There's only one register for VxLAN UDP port.
7880 * So, we cannot add several ports. Will update it.
7883 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7887 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7891 return ixgbe_update_vxlan_port(hw, port);
7894 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7895 * UDP port, it must have a value.
7896 * So, will reset it to the original value 0.
7899 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7904 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7906 if (cur_port != port) {
7907 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7911 return ixgbe_update_vxlan_port(hw, 0);
7914 /* Add UDP tunneling port */
7916 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7917 struct rte_eth_udp_tunnel *udp_tunnel)
7920 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7922 if (hw->mac.type != ixgbe_mac_X550 &&
7923 hw->mac.type != ixgbe_mac_X550EM_x &&
7924 hw->mac.type != ixgbe_mac_X550EM_a) {
7928 if (udp_tunnel == NULL)
7931 switch (udp_tunnel->prot_type) {
7932 case RTE_TUNNEL_TYPE_VXLAN:
7933 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7936 case RTE_TUNNEL_TYPE_GENEVE:
7937 case RTE_TUNNEL_TYPE_TEREDO:
7938 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7943 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7951 /* Remove UDP tunneling port */
7953 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7954 struct rte_eth_udp_tunnel *udp_tunnel)
7957 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7959 if (hw->mac.type != ixgbe_mac_X550 &&
7960 hw->mac.type != ixgbe_mac_X550EM_x &&
7961 hw->mac.type != ixgbe_mac_X550EM_a) {
7965 if (udp_tunnel == NULL)
7968 switch (udp_tunnel->prot_type) {
7969 case RTE_TUNNEL_TYPE_VXLAN:
7970 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7972 case RTE_TUNNEL_TYPE_GENEVE:
7973 case RTE_TUNNEL_TYPE_TEREDO:
7974 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7978 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7987 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7989 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7991 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7995 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7999 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8002 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8004 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8007 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8010 /* PF reset VF event */
8011 if (in_msg == IXGBE_PF_CONTROL_MSG)
8012 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8017 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8020 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8021 struct ixgbe_interrupt *intr =
8022 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8023 ixgbevf_intr_disable(hw);
8025 /* read-on-clear nic registers here */
8026 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8029 /* only one misc vector supported - mailbox */
8030 eicr &= IXGBE_VTEICR_MASK;
8031 if (eicr == IXGBE_MISC_VEC_ID)
8032 intr->flags |= IXGBE_FLAG_MAILBOX;
8038 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8040 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8041 struct ixgbe_interrupt *intr =
8042 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8044 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8045 ixgbevf_mbx_process(dev);
8046 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8049 ixgbevf_intr_enable(hw);
8055 ixgbevf_dev_interrupt_handler(void *param)
8057 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8059 ixgbevf_dev_interrupt_get_status(dev);
8060 ixgbevf_dev_interrupt_action(dev);
8064 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8065 * @hw: pointer to hardware structure
8067 * Stops the transmit data path and waits for the HW to internally empty
8068 * the Tx security block
8070 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8072 #define IXGBE_MAX_SECTX_POLL 40
8077 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8078 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8079 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8080 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8081 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8082 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8084 /* Use interrupt-safe sleep just in case */
8088 /* For informational purposes only */
8089 if (i >= IXGBE_MAX_SECTX_POLL)
8090 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8091 "path fully disabled. Continuing with init.");
8093 return IXGBE_SUCCESS;
8097 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8098 * @hw: pointer to hardware structure
8100 * Enables the transmit data path.
8102 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8106 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8107 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8108 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8109 IXGBE_WRITE_FLUSH(hw);
8111 return IXGBE_SUCCESS;
8114 /* restore n-tuple filter */
8116 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8118 struct ixgbe_filter_info *filter_info =
8119 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8120 struct ixgbe_5tuple_filter *node;
8122 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8123 ixgbe_inject_5tuple_filter(dev, node);
8127 /* restore ethernet type filter */
8129 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8131 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8132 struct ixgbe_filter_info *filter_info =
8133 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8136 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8137 if (filter_info->ethertype_mask & (1 << i)) {
8138 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8139 filter_info->ethertype_filters[i].etqf);
8140 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8141 filter_info->ethertype_filters[i].etqs);
8142 IXGBE_WRITE_FLUSH(hw);
8147 /* restore SYN filter */
8149 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8151 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8152 struct ixgbe_filter_info *filter_info =
8153 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8156 synqf = filter_info->syn_info;
8158 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8159 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8160 IXGBE_WRITE_FLUSH(hw);
8164 /* restore L2 tunnel filter */
8166 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8168 struct ixgbe_l2_tn_info *l2_tn_info =
8169 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8170 struct ixgbe_l2_tn_filter *node;
8171 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8173 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8174 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8175 l2_tn_conf.tunnel_id = node->key.tn_id;
8176 l2_tn_conf.pool = node->pool;
8177 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8182 ixgbe_filter_restore(struct rte_eth_dev *dev)
8184 ixgbe_ntuple_filter_restore(dev);
8185 ixgbe_ethertype_filter_restore(dev);
8186 ixgbe_syn_filter_restore(dev);
8187 ixgbe_fdir_filter_restore(dev);
8188 ixgbe_l2_tn_filter_restore(dev);
8194 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8196 struct ixgbe_l2_tn_info *l2_tn_info =
8197 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8198 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8200 if (l2_tn_info->e_tag_en)
8201 (void)ixgbe_e_tag_enable(hw);
8203 if (l2_tn_info->e_tag_fwd_en)
8204 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8206 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8209 /* remove all the n-tuple filters */
8211 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8213 struct ixgbe_filter_info *filter_info =
8214 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8215 struct ixgbe_5tuple_filter *p_5tuple;
8217 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8218 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8221 /* remove all the ether type filters */
8223 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8225 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8226 struct ixgbe_filter_info *filter_info =
8227 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8230 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8231 if (filter_info->ethertype_mask & (1 << i) &&
8232 !filter_info->ethertype_filters[i].conf) {
8233 (void)ixgbe_ethertype_filter_remove(filter_info,
8235 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8236 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8237 IXGBE_WRITE_FLUSH(hw);
8242 /* remove the SYN filter */
8244 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8246 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8247 struct ixgbe_filter_info *filter_info =
8248 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8250 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8251 filter_info->syn_info = 0;
8253 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8254 IXGBE_WRITE_FLUSH(hw);
8258 /* remove all the L2 tunnel filters */
8260 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8262 struct ixgbe_l2_tn_info *l2_tn_info =
8263 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8264 struct ixgbe_l2_tn_filter *l2_tn_filter;
8265 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8268 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8269 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8270 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8271 l2_tn_conf.pool = l2_tn_filter->pool;
8272 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8280 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8281 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8282 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8283 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8284 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8285 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");