1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
18 #include <rte_interrupts.h>
20 #include <rte_debug.h>
22 #include <rte_bus_pci.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
31 #include <rte_random.h>
33 #include <rte_hash_crc.h>
34 #ifdef RTE_LIBRTE_SECURITY
35 #include <rte_security_driver.h>
38 #include "ixgbe_logs.h"
39 #include "base/ixgbe_api.h"
40 #include "base/ixgbe_vf.h"
41 #include "base/ixgbe_common.h"
42 #include "ixgbe_ethdev.h"
43 #include "ixgbe_bypass.h"
44 #include "ixgbe_rxtx.h"
45 #include "base/ixgbe_type.h"
46 #include "base/ixgbe_phy.h"
47 #include "ixgbe_regs.h"
50 * High threshold controlling when to start sending XOFF frames. Must be at
51 * least 8 bytes less than receive packet buffer size. This value is in units
54 #define IXGBE_FC_HI 0x80
57 * Low threshold controlling when to start sending XON frames. This value is
58 * in units of 1024 bytes.
60 #define IXGBE_FC_LO 0x40
62 /* Timer value included in XOFF frames. */
63 #define IXGBE_FC_PAUSE 0x680
65 /*Default value of Max Rx Queue*/
66 #define IXGBE_MAX_RX_QUEUE_NUM 128
68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
69 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
70 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
72 #define IXGBE_MMW_SIZE_DEFAULT 0x4
73 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
74 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
77 * Default values for RX/TX configuration
79 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
80 #define IXGBE_DEFAULT_RX_PTHRESH 8
81 #define IXGBE_DEFAULT_RX_HTHRESH 8
82 #define IXGBE_DEFAULT_RX_WTHRESH 0
84 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
85 #define IXGBE_DEFAULT_TX_PTHRESH 32
86 #define IXGBE_DEFAULT_TX_HTHRESH 0
87 #define IXGBE_DEFAULT_TX_WTHRESH 0
88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
90 /* Bit shift and mask */
91 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
92 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
93 #define IXGBE_8_BIT_WIDTH CHAR_BIT
94 #define IXGBE_8_BIT_MASK UINT8_MAX
96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
100 /* Additional timesync values. */
101 #define NSEC_PER_SEC 1000000000L
102 #define IXGBE_INCVAL_10GB 0x66666666
103 #define IXGBE_INCVAL_1GB 0x40000000
104 #define IXGBE_INCVAL_100 0x50000000
105 #define IXGBE_INCVAL_SHIFT_10GB 28
106 #define IXGBE_INCVAL_SHIFT_1GB 24
107 #define IXGBE_INCVAL_SHIFT_100 21
108 #define IXGBE_INCVAL_SHIFT_82599 7
109 #define IXGBE_INCPER_SHIFT_82599 24
111 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
113 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
115 #define IXGBE_ETAG_ETYPE 0x00005084
116 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
117 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
118 #define IXGBE_RAH_ADTYPE 0x40000000
119 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
120 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
123 #define IXGBE_QDE_STRIP_TAG 0x00000004
124 #define IXGBE_VTEICR_MASK 0x07
126 #define IXGBE_EXVET_VET_EXT_SHIFT 16
127 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
148 int wait_to_complete);
149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
150 struct rte_eth_stats *stats);
151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
152 struct rte_eth_xstat *xstats, unsigned n);
153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
154 struct rte_eth_xstat *xstats, unsigned n);
156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
157 uint64_t *values, unsigned int n);
158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
161 struct rte_eth_xstat_name *xstats_names,
163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
164 struct rte_eth_xstat_name *xstats_names, unsigned limit);
165 static int ixgbe_dev_xstats_get_names_by_id(
166 struct rte_eth_dev *dev,
167 struct rte_eth_xstat_name *xstats_names,
170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
177 struct rte_eth_dev_info *dev_info);
178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
180 struct rte_eth_dev_info *dev_info);
181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
184 uint16_t vlan_id, int on);
185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
186 enum rte_vlan_type vlan_type,
188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
189 uint16_t queue, bool on);
190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
204 struct rte_eth_fc_conf *fc_conf);
205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
206 struct rte_eth_fc_conf *fc_conf);
207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
208 struct rte_eth_pfc_conf *pfc_conf);
209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
210 struct rte_eth_rss_reta_entry64 *reta_conf,
212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
221 static void ixgbe_dev_interrupt_handler(void *param);
222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
223 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
224 uint32_t index, uint32_t pool);
225 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
226 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
227 struct ether_addr *mac_addr);
228 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
229 static bool is_device_supported(struct rte_eth_dev *dev,
230 struct rte_pci_driver *drv);
232 /* For Virtual Function support */
233 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
234 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
235 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
236 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
237 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
238 int wait_to_complete);
239 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
240 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
241 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
242 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
243 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
244 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
245 struct rte_eth_stats *stats);
246 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
247 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
248 uint16_t vlan_id, int on);
249 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
250 uint16_t queue, int on);
251 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
252 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
259 uint8_t queue, uint8_t msix_vector);
260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
264 /* For Eth VMDQ APIs support */
265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
266 ether_addr * mac_addr, uint8_t on);
267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
268 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
269 struct rte_eth_mirror_conf *mirror_conf,
270 uint8_t rule_id, uint8_t on);
271 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
273 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
275 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
277 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
278 uint8_t queue, uint8_t msix_vector);
279 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
281 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
282 struct ether_addr *mac_addr,
283 uint32_t index, uint32_t pool);
284 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
285 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
286 struct ether_addr *mac_addr);
287 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
288 struct rte_eth_syn_filter *filter);
289 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
290 enum rte_filter_op filter_op,
292 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
293 struct ixgbe_5tuple_filter *filter);
294 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
295 struct ixgbe_5tuple_filter *filter);
296 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
297 enum rte_filter_op filter_op,
299 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
300 struct rte_eth_ntuple_filter *filter);
301 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
302 enum rte_filter_op filter_op,
304 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
305 struct rte_eth_ethertype_filter *filter);
306 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
307 enum rte_filter_type filter_type,
308 enum rte_filter_op filter_op,
310 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
312 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
313 struct ether_addr *mc_addr_set,
314 uint32_t nb_mc_addr);
315 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
316 struct rte_eth_dcb_info *dcb_info);
318 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
319 static int ixgbe_get_regs(struct rte_eth_dev *dev,
320 struct rte_dev_reg_info *regs);
321 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
322 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
323 struct rte_dev_eeprom_info *eeprom);
324 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
325 struct rte_dev_eeprom_info *eeprom);
327 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
328 struct rte_eth_dev_module_info *modinfo);
329 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
330 struct rte_dev_eeprom_info *info);
332 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
333 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
334 struct rte_dev_reg_info *regs);
336 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
337 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
338 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
339 struct timespec *timestamp,
341 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
342 struct timespec *timestamp);
343 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
344 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
345 struct timespec *timestamp);
346 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
347 const struct timespec *timestamp);
348 static void ixgbevf_dev_interrupt_handler(void *param);
350 static int ixgbe_dev_l2_tunnel_eth_type_conf
351 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
352 static int ixgbe_dev_l2_tunnel_offload_set
353 (struct rte_eth_dev *dev,
354 struct rte_eth_l2_tunnel_conf *l2_tunnel,
357 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
358 enum rte_filter_op filter_op,
361 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
362 struct rte_eth_udp_tunnel *udp_tunnel);
363 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
364 struct rte_eth_udp_tunnel *udp_tunnel);
365 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
366 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
369 * Define VF Stats MACRO for Non "cleared on read" register
371 #define UPDATE_VF_STAT(reg, last, cur) \
373 uint32_t latest = IXGBE_READ_REG(hw, reg); \
374 cur += (latest - last) & UINT_MAX; \
378 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
380 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
381 u64 new_msb = IXGBE_READ_REG(hw, msb); \
382 u64 latest = ((new_msb << 32) | new_lsb); \
383 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
387 #define IXGBE_SET_HWSTRIP(h, q) do {\
388 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
389 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
390 (h)->bitmap[idx] |= 1 << bit;\
393 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
394 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
395 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
396 (h)->bitmap[idx] &= ~(1 << bit);\
399 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
400 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
401 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
402 (r) = (h)->bitmap[idx] >> bit & 1;\
405 int ixgbe_logtype_init;
406 int ixgbe_logtype_driver;
409 * The set of PCI devices this driver supports
411 static const struct rte_pci_id pci_id_ixgbe_map[] = {
412 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
459 #ifdef RTE_LIBRTE_IXGBE_BYPASS
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
462 { .vendor_id = 0, /* sentinel */ },
466 * The set of PCI devices this driver supports (for 82599 VF)
468 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
479 { .vendor_id = 0, /* sentinel */ },
482 static const struct rte_eth_desc_lim rx_desc_lim = {
483 .nb_max = IXGBE_MAX_RING_DESC,
484 .nb_min = IXGBE_MIN_RING_DESC,
485 .nb_align = IXGBE_RXD_ALIGN,
488 static const struct rte_eth_desc_lim tx_desc_lim = {
489 .nb_max = IXGBE_MAX_RING_DESC,
490 .nb_min = IXGBE_MIN_RING_DESC,
491 .nb_align = IXGBE_TXD_ALIGN,
492 .nb_seg_max = IXGBE_TX_MAX_SEG,
493 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
496 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
497 .dev_configure = ixgbe_dev_configure,
498 .dev_start = ixgbe_dev_start,
499 .dev_stop = ixgbe_dev_stop,
500 .dev_set_link_up = ixgbe_dev_set_link_up,
501 .dev_set_link_down = ixgbe_dev_set_link_down,
502 .dev_close = ixgbe_dev_close,
503 .dev_reset = ixgbe_dev_reset,
504 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
505 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
506 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
507 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
508 .link_update = ixgbe_dev_link_update,
509 .stats_get = ixgbe_dev_stats_get,
510 .xstats_get = ixgbe_dev_xstats_get,
511 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
512 .stats_reset = ixgbe_dev_stats_reset,
513 .xstats_reset = ixgbe_dev_xstats_reset,
514 .xstats_get_names = ixgbe_dev_xstats_get_names,
515 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
516 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
517 .fw_version_get = ixgbe_fw_version_get,
518 .dev_infos_get = ixgbe_dev_info_get,
519 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
520 .mtu_set = ixgbe_dev_mtu_set,
521 .vlan_filter_set = ixgbe_vlan_filter_set,
522 .vlan_tpid_set = ixgbe_vlan_tpid_set,
523 .vlan_offload_set = ixgbe_vlan_offload_set,
524 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
525 .rx_queue_start = ixgbe_dev_rx_queue_start,
526 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
527 .tx_queue_start = ixgbe_dev_tx_queue_start,
528 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
529 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
530 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
531 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
532 .rx_queue_release = ixgbe_dev_rx_queue_release,
533 .rx_queue_count = ixgbe_dev_rx_queue_count,
534 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
535 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
536 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
537 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
538 .tx_queue_release = ixgbe_dev_tx_queue_release,
539 .dev_led_on = ixgbe_dev_led_on,
540 .dev_led_off = ixgbe_dev_led_off,
541 .flow_ctrl_get = ixgbe_flow_ctrl_get,
542 .flow_ctrl_set = ixgbe_flow_ctrl_set,
543 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
544 .mac_addr_add = ixgbe_add_rar,
545 .mac_addr_remove = ixgbe_remove_rar,
546 .mac_addr_set = ixgbe_set_default_mac_addr,
547 .uc_hash_table_set = ixgbe_uc_hash_table_set,
548 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
549 .mirror_rule_set = ixgbe_mirror_rule_set,
550 .mirror_rule_reset = ixgbe_mirror_rule_reset,
551 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
552 .reta_update = ixgbe_dev_rss_reta_update,
553 .reta_query = ixgbe_dev_rss_reta_query,
554 .rss_hash_update = ixgbe_dev_rss_hash_update,
555 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
556 .filter_ctrl = ixgbe_dev_filter_ctrl,
557 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
558 .rxq_info_get = ixgbe_rxq_info_get,
559 .txq_info_get = ixgbe_txq_info_get,
560 .timesync_enable = ixgbe_timesync_enable,
561 .timesync_disable = ixgbe_timesync_disable,
562 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
563 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
564 .get_reg = ixgbe_get_regs,
565 .get_eeprom_length = ixgbe_get_eeprom_length,
566 .get_eeprom = ixgbe_get_eeprom,
567 .set_eeprom = ixgbe_set_eeprom,
568 .get_module_info = ixgbe_get_module_info,
569 .get_module_eeprom = ixgbe_get_module_eeprom,
570 .get_dcb_info = ixgbe_dev_get_dcb_info,
571 .timesync_adjust_time = ixgbe_timesync_adjust_time,
572 .timesync_read_time = ixgbe_timesync_read_time,
573 .timesync_write_time = ixgbe_timesync_write_time,
574 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
575 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
576 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
577 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
578 .tm_ops_get = ixgbe_tm_ops_get,
582 * dev_ops for virtual function, bare necessities for basic vf
583 * operation have been implemented
585 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
586 .dev_configure = ixgbevf_dev_configure,
587 .dev_start = ixgbevf_dev_start,
588 .dev_stop = ixgbevf_dev_stop,
589 .link_update = ixgbevf_dev_link_update,
590 .stats_get = ixgbevf_dev_stats_get,
591 .xstats_get = ixgbevf_dev_xstats_get,
592 .stats_reset = ixgbevf_dev_stats_reset,
593 .xstats_reset = ixgbevf_dev_stats_reset,
594 .xstats_get_names = ixgbevf_dev_xstats_get_names,
595 .dev_close = ixgbevf_dev_close,
596 .dev_reset = ixgbevf_dev_reset,
597 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
598 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
599 .dev_infos_get = ixgbevf_dev_info_get,
600 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
601 .mtu_set = ixgbevf_dev_set_mtu,
602 .vlan_filter_set = ixgbevf_vlan_filter_set,
603 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
604 .vlan_offload_set = ixgbevf_vlan_offload_set,
605 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
606 .rx_queue_release = ixgbe_dev_rx_queue_release,
607 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
608 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
609 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
610 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
611 .tx_queue_release = ixgbe_dev_tx_queue_release,
612 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
613 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
614 .mac_addr_add = ixgbevf_add_mac_addr,
615 .mac_addr_remove = ixgbevf_remove_mac_addr,
616 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
617 .rxq_info_get = ixgbe_rxq_info_get,
618 .txq_info_get = ixgbe_txq_info_get,
619 .mac_addr_set = ixgbevf_set_default_mac_addr,
620 .get_reg = ixgbevf_get_regs,
621 .reta_update = ixgbe_dev_rss_reta_update,
622 .reta_query = ixgbe_dev_rss_reta_query,
623 .rss_hash_update = ixgbe_dev_rss_hash_update,
624 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
627 /* store statistics names and its offset in stats structure */
628 struct rte_ixgbe_xstats_name_off {
629 char name[RTE_ETH_XSTATS_NAME_SIZE];
633 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
634 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
635 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
636 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
637 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
638 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
639 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
640 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
641 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
642 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
643 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
644 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
645 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
646 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
647 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
648 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
650 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
652 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
653 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
654 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
655 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
656 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
657 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
658 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
659 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
660 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
661 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
662 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
663 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
664 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
665 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
666 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
667 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
668 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
670 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
672 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
673 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
674 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
675 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
677 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
679 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
681 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
683 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
685 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
687 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
690 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
691 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
692 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
694 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
695 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
696 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
697 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
698 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
700 {"rx_fcoe_no_direct_data_placement_ext_buff",
701 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
703 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
705 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
707 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
709 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
711 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
714 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
715 sizeof(rte_ixgbe_stats_strings[0]))
717 /* MACsec statistics */
718 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
719 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
721 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
722 out_pkts_encrypted)},
723 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
724 out_pkts_protected)},
725 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
726 out_octets_encrypted)},
727 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
728 out_octets_protected)},
729 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
731 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
733 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
735 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
736 in_pkts_unknownsci)},
737 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
738 in_octets_decrypted)},
739 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
740 in_octets_validated)},
741 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
743 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
745 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
747 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
749 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
751 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
753 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
755 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
756 in_pkts_notusingsa)},
759 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
760 sizeof(rte_ixgbe_macsec_strings[0]))
762 /* Per-queue statistics */
763 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
764 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
765 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
766 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
767 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
770 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
771 sizeof(rte_ixgbe_rxq_strings[0]))
772 #define IXGBE_NB_RXQ_PRIO_VALUES 8
774 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
775 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
776 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
777 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
781 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
782 sizeof(rte_ixgbe_txq_strings[0]))
783 #define IXGBE_NB_TXQ_PRIO_VALUES 8
785 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
786 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
789 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
790 sizeof(rte_ixgbevf_stats_strings[0]))
793 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
796 ixgbe_is_sfp(struct ixgbe_hw *hw)
798 switch (hw->phy.type) {
799 case ixgbe_phy_sfp_avago:
800 case ixgbe_phy_sfp_ftl:
801 case ixgbe_phy_sfp_intel:
802 case ixgbe_phy_sfp_unknown:
803 case ixgbe_phy_sfp_passive_tyco:
804 case ixgbe_phy_sfp_passive_unknown:
811 static inline int32_t
812 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
817 status = ixgbe_reset_hw(hw);
819 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
820 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
821 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
822 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
823 IXGBE_WRITE_FLUSH(hw);
825 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
826 status = IXGBE_SUCCESS;
831 ixgbe_enable_intr(struct rte_eth_dev *dev)
833 struct ixgbe_interrupt *intr =
834 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
835 struct ixgbe_hw *hw =
836 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
838 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
839 IXGBE_WRITE_FLUSH(hw);
843 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
846 ixgbe_disable_intr(struct ixgbe_hw *hw)
848 PMD_INIT_FUNC_TRACE();
850 if (hw->mac.type == ixgbe_mac_82598EB) {
851 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
853 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
854 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
855 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
857 IXGBE_WRITE_FLUSH(hw);
861 * This function resets queue statistics mapping registers.
862 * From Niantic datasheet, Initialization of Statistics section:
863 * "...if software requires the queue counters, the RQSMR and TQSM registers
864 * must be re-programmed following a device reset.
867 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
871 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
872 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
873 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
879 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
884 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
885 #define NB_QMAP_FIELDS_PER_QSM_REG 4
886 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
888 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
889 struct ixgbe_stat_mapping_registers *stat_mappings =
890 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
891 uint32_t qsmr_mask = 0;
892 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
896 if ((hw->mac.type != ixgbe_mac_82599EB) &&
897 (hw->mac.type != ixgbe_mac_X540) &&
898 (hw->mac.type != ixgbe_mac_X550) &&
899 (hw->mac.type != ixgbe_mac_X550EM_x) &&
900 (hw->mac.type != ixgbe_mac_X550EM_a))
903 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
904 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
907 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
908 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
909 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
912 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
914 /* Now clear any previous stat_idx set */
915 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
917 stat_mappings->tqsm[n] &= ~clearing_mask;
919 stat_mappings->rqsmr[n] &= ~clearing_mask;
921 q_map = (uint32_t)stat_idx;
922 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
923 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
925 stat_mappings->tqsm[n] |= qsmr_mask;
927 stat_mappings->rqsmr[n] |= qsmr_mask;
929 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
930 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
932 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
933 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
935 /* Now write the mapping in the appropriate register */
937 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
938 stat_mappings->rqsmr[n], n);
939 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
941 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
942 stat_mappings->tqsm[n], n);
943 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
949 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
951 struct ixgbe_stat_mapping_registers *stat_mappings =
952 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
953 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
956 /* write whatever was in stat mapping table to the NIC */
957 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
959 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
962 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
967 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
970 struct ixgbe_dcb_tc_config *tc;
971 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
973 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
974 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
975 for (i = 0; i < dcb_max_tc; i++) {
976 tc = &dcb_config->tc_config[i];
977 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
978 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
979 (uint8_t)(100/dcb_max_tc + (i & 1));
980 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
981 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
982 (uint8_t)(100/dcb_max_tc + (i & 1));
983 tc->pfc = ixgbe_dcb_pfc_disabled;
986 /* Initialize default user to priority mapping, UPx->TC0 */
987 tc = &dcb_config->tc_config[0];
988 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
989 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
990 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
991 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
992 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
994 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
995 dcb_config->pfc_mode_enable = false;
996 dcb_config->vt_mode = true;
997 dcb_config->round_robin_enable = false;
998 /* support all DCB capabilities in 82599 */
999 dcb_config->support.capabilities = 0xFF;
1001 /*we only support 4 Tcs for X540, X550 */
1002 if (hw->mac.type == ixgbe_mac_X540 ||
1003 hw->mac.type == ixgbe_mac_X550 ||
1004 hw->mac.type == ixgbe_mac_X550EM_x ||
1005 hw->mac.type == ixgbe_mac_X550EM_a) {
1006 dcb_config->num_tcs.pg_tcs = 4;
1007 dcb_config->num_tcs.pfc_tcs = 4;
1012 * Ensure that all locks are released before first NVM or PHY access
1015 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1020 * Phy lock should not fail in this early stage. If this is the case,
1021 * it is due to an improper exit of the application.
1022 * So force the release of the faulty lock. Release of common lock
1023 * is done automatically by swfw_sync function.
1025 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1026 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1027 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1029 ixgbe_release_swfw_semaphore(hw, mask);
1032 * These ones are more tricky since they are common to all ports; but
1033 * swfw_sync retries last long enough (1s) to be almost sure that if
1034 * lock can not be taken it is due to an improper lock of the
1037 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1038 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1039 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1041 ixgbe_release_swfw_semaphore(hw, mask);
1045 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1046 * It returns 0 on success.
1049 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1051 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1052 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1053 struct ixgbe_hw *hw =
1054 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1055 struct ixgbe_vfta *shadow_vfta =
1056 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1057 struct ixgbe_hwstrip *hwstrip =
1058 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1059 struct ixgbe_dcb_config *dcb_config =
1060 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1061 struct ixgbe_filter_info *filter_info =
1062 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1063 struct ixgbe_bw_conf *bw_conf =
1064 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1069 PMD_INIT_FUNC_TRACE();
1071 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1072 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1073 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1074 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1077 * For secondary processes, we don't initialise any further as primary
1078 * has already done this work. Only check we don't need a different
1079 * RX and TX function.
1081 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1082 struct ixgbe_tx_queue *txq;
1083 /* TX queue function in primary, set by last queue initialized
1084 * Tx queue may not initialized by primary process
1086 if (eth_dev->data->tx_queues) {
1087 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1088 ixgbe_set_tx_function(eth_dev, txq);
1090 /* Use default TX function if we get here */
1091 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1092 "Using default TX function.");
1095 ixgbe_set_rx_function(eth_dev);
1100 rte_eth_copy_pci_info(eth_dev, pci_dev);
1102 /* Vendor and Device ID need to be set before init of shared code */
1103 hw->device_id = pci_dev->id.device_id;
1104 hw->vendor_id = pci_dev->id.vendor_id;
1105 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1106 hw->allow_unsupported_sfp = 1;
1108 /* Initialize the shared code (base driver) */
1109 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1110 diag = ixgbe_bypass_init_shared_code(hw);
1112 diag = ixgbe_init_shared_code(hw);
1113 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1115 if (diag != IXGBE_SUCCESS) {
1116 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1120 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1121 PMD_INIT_LOG(ERR, "\nERROR: "
1122 "Firmware recovery mode detected. Limiting functionality.\n"
1123 "Refer to the Intel(R) Ethernet Adapters and Devices "
1124 "User Guide for details on firmware recovery mode.");
1128 /* pick up the PCI bus settings for reporting later */
1129 ixgbe_get_bus_info(hw);
1131 /* Unlock any pending hardware semaphore */
1132 ixgbe_swfw_lock_reset(hw);
1134 #ifdef RTE_LIBRTE_SECURITY
1135 /* Initialize security_ctx only for primary process*/
1136 if (ixgbe_ipsec_ctx_create(eth_dev))
1140 /* Initialize DCB configuration*/
1141 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1142 ixgbe_dcb_init(hw, dcb_config);
1143 /* Get Hardware Flow Control setting */
1144 hw->fc.requested_mode = ixgbe_fc_full;
1145 hw->fc.current_mode = ixgbe_fc_full;
1146 hw->fc.pause_time = IXGBE_FC_PAUSE;
1147 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1148 hw->fc.low_water[i] = IXGBE_FC_LO;
1149 hw->fc.high_water[i] = IXGBE_FC_HI;
1151 hw->fc.send_xon = 1;
1153 /* Make sure we have a good EEPROM before we read from it */
1154 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1155 if (diag != IXGBE_SUCCESS) {
1156 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1160 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1161 diag = ixgbe_bypass_init_hw(hw);
1163 diag = ixgbe_init_hw(hw);
1164 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1167 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1168 * is called too soon after the kernel driver unbinding/binding occurs.
1169 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1170 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1171 * also called. See ixgbe_identify_phy_82599(). The reason for the
1172 * failure is not known, and only occuts when virtualisation features
1173 * are disabled in the bios. A delay of 100ms was found to be enough by
1174 * trial-and-error, and is doubled to be safe.
1176 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1178 diag = ixgbe_init_hw(hw);
1181 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1182 diag = IXGBE_SUCCESS;
1184 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1185 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1186 "LOM. Please be aware there may be issues associated "
1187 "with your hardware.");
1188 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1189 "please contact your Intel or hardware representative "
1190 "who provided you with this hardware.");
1191 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1192 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1194 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1198 /* Reset the hw statistics */
1199 ixgbe_dev_stats_reset(eth_dev);
1201 /* disable interrupt */
1202 ixgbe_disable_intr(hw);
1204 /* reset mappings for queue statistics hw counters*/
1205 ixgbe_reset_qstat_mappings(hw);
1207 /* Allocate memory for storing MAC addresses */
1208 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1209 hw->mac.num_rar_entries, 0);
1210 if (eth_dev->data->mac_addrs == NULL) {
1212 "Failed to allocate %u bytes needed to store "
1214 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1217 /* Copy the permanent MAC address */
1218 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1219 ð_dev->data->mac_addrs[0]);
1221 /* Allocate memory for storing hash filter MAC addresses */
1222 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1223 IXGBE_VMDQ_NUM_UC_MAC, 0);
1224 if (eth_dev->data->hash_mac_addrs == NULL) {
1226 "Failed to allocate %d bytes needed to store MAC addresses",
1227 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1231 /* initialize the vfta */
1232 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1234 /* initialize the hw strip bitmap*/
1235 memset(hwstrip, 0, sizeof(*hwstrip));
1237 /* initialize PF if max_vfs not zero */
1238 ixgbe_pf_host_init(eth_dev);
1240 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1241 /* let hardware know driver is loaded */
1242 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1243 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1244 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1245 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1246 IXGBE_WRITE_FLUSH(hw);
1248 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1249 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1250 (int) hw->mac.type, (int) hw->phy.type,
1251 (int) hw->phy.sfp_type);
1253 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1254 (int) hw->mac.type, (int) hw->phy.type);
1256 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1257 eth_dev->data->port_id, pci_dev->id.vendor_id,
1258 pci_dev->id.device_id);
1260 rte_intr_callback_register(intr_handle,
1261 ixgbe_dev_interrupt_handler, eth_dev);
1263 /* enable uio/vfio intr/eventfd mapping */
1264 rte_intr_enable(intr_handle);
1266 /* enable support intr */
1267 ixgbe_enable_intr(eth_dev);
1269 /* initialize filter info */
1270 memset(filter_info, 0,
1271 sizeof(struct ixgbe_filter_info));
1273 /* initialize 5tuple filter list */
1274 TAILQ_INIT(&filter_info->fivetuple_list);
1276 /* initialize flow director filter list & hash */
1277 ixgbe_fdir_filter_init(eth_dev);
1279 /* initialize l2 tunnel filter list & hash */
1280 ixgbe_l2_tn_filter_init(eth_dev);
1282 /* initialize flow filter lists */
1283 ixgbe_filterlist_init();
1285 /* initialize bandwidth configuration info */
1286 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1288 /* initialize Traffic Manager configuration */
1289 ixgbe_tm_conf_init(eth_dev);
1295 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1297 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1298 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1299 struct ixgbe_hw *hw;
1303 PMD_INIT_FUNC_TRACE();
1305 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1308 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1310 if (hw->adapter_stopped == 0)
1311 ixgbe_dev_close(eth_dev);
1313 eth_dev->dev_ops = NULL;
1314 eth_dev->rx_pkt_burst = NULL;
1315 eth_dev->tx_pkt_burst = NULL;
1317 /* Unlock any pending hardware semaphore */
1318 ixgbe_swfw_lock_reset(hw);
1320 /* disable uio intr before callback unregister */
1321 rte_intr_disable(intr_handle);
1324 ret = rte_intr_callback_unregister(intr_handle,
1325 ixgbe_dev_interrupt_handler, eth_dev);
1328 } else if (ret != -EAGAIN) {
1330 "intr callback unregister failed: %d",
1335 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1337 /* uninitialize PF if max_vfs not zero */
1338 ixgbe_pf_host_uninit(eth_dev);
1340 rte_free(eth_dev->data->mac_addrs);
1341 eth_dev->data->mac_addrs = NULL;
1343 rte_free(eth_dev->data->hash_mac_addrs);
1344 eth_dev->data->hash_mac_addrs = NULL;
1346 /* remove all the fdir filters & hash */
1347 ixgbe_fdir_filter_uninit(eth_dev);
1349 /* remove all the L2 tunnel filters & hash */
1350 ixgbe_l2_tn_filter_uninit(eth_dev);
1352 /* Remove all ntuple filters of the device */
1353 ixgbe_ntuple_filter_uninit(eth_dev);
1355 /* clear all the filters list */
1356 ixgbe_filterlist_flush();
1358 /* Remove all Traffic Manager configuration */
1359 ixgbe_tm_conf_uninit(eth_dev);
1361 #ifdef RTE_LIBRTE_SECURITY
1362 rte_free(eth_dev->security_ctx);
1368 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1370 struct ixgbe_filter_info *filter_info =
1371 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1372 struct ixgbe_5tuple_filter *p_5tuple;
1374 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1375 TAILQ_REMOVE(&filter_info->fivetuple_list,
1380 memset(filter_info->fivetuple_mask, 0,
1381 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1386 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1388 struct ixgbe_hw_fdir_info *fdir_info =
1389 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1390 struct ixgbe_fdir_filter *fdir_filter;
1392 if (fdir_info->hash_map)
1393 rte_free(fdir_info->hash_map);
1394 if (fdir_info->hash_handle)
1395 rte_hash_free(fdir_info->hash_handle);
1397 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1398 TAILQ_REMOVE(&fdir_info->fdir_list,
1401 rte_free(fdir_filter);
1407 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1409 struct ixgbe_l2_tn_info *l2_tn_info =
1410 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1411 struct ixgbe_l2_tn_filter *l2_tn_filter;
1413 if (l2_tn_info->hash_map)
1414 rte_free(l2_tn_info->hash_map);
1415 if (l2_tn_info->hash_handle)
1416 rte_hash_free(l2_tn_info->hash_handle);
1418 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1419 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1422 rte_free(l2_tn_filter);
1428 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1430 struct ixgbe_hw_fdir_info *fdir_info =
1431 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1432 char fdir_hash_name[RTE_HASH_NAMESIZE];
1433 struct rte_hash_parameters fdir_hash_params = {
1434 .name = fdir_hash_name,
1435 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1436 .key_len = sizeof(union ixgbe_atr_input),
1437 .hash_func = rte_hash_crc,
1438 .hash_func_init_val = 0,
1439 .socket_id = rte_socket_id(),
1442 TAILQ_INIT(&fdir_info->fdir_list);
1443 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1444 "fdir_%s", eth_dev->device->name);
1445 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1446 if (!fdir_info->hash_handle) {
1447 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1450 fdir_info->hash_map = rte_zmalloc("ixgbe",
1451 sizeof(struct ixgbe_fdir_filter *) *
1452 IXGBE_MAX_FDIR_FILTER_NUM,
1454 if (!fdir_info->hash_map) {
1456 "Failed to allocate memory for fdir hash map!");
1459 fdir_info->mask_added = FALSE;
1464 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1466 struct ixgbe_l2_tn_info *l2_tn_info =
1467 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1468 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1469 struct rte_hash_parameters l2_tn_hash_params = {
1470 .name = l2_tn_hash_name,
1471 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1472 .key_len = sizeof(struct ixgbe_l2_tn_key),
1473 .hash_func = rte_hash_crc,
1474 .hash_func_init_val = 0,
1475 .socket_id = rte_socket_id(),
1478 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1479 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1480 "l2_tn_%s", eth_dev->device->name);
1481 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1482 if (!l2_tn_info->hash_handle) {
1483 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1486 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1487 sizeof(struct ixgbe_l2_tn_filter *) *
1488 IXGBE_MAX_L2_TN_FILTER_NUM,
1490 if (!l2_tn_info->hash_map) {
1492 "Failed to allocate memory for L2 TN hash map!");
1495 l2_tn_info->e_tag_en = FALSE;
1496 l2_tn_info->e_tag_fwd_en = FALSE;
1497 l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1502 * Negotiate mailbox API version with the PF.
1503 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1504 * Then we try to negotiate starting with the most recent one.
1505 * If all negotiation attempts fail, then we will proceed with
1506 * the default one (ixgbe_mbox_api_10).
1509 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1513 /* start with highest supported, proceed down */
1514 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1521 i != RTE_DIM(sup_ver) &&
1522 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1528 generate_random_mac_addr(struct ether_addr *mac_addr)
1532 /* Set Organizationally Unique Identifier (OUI) prefix. */
1533 mac_addr->addr_bytes[0] = 0x00;
1534 mac_addr->addr_bytes[1] = 0x09;
1535 mac_addr->addr_bytes[2] = 0xC0;
1536 /* Force indication of locally assigned MAC address. */
1537 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1538 /* Generate the last 3 bytes of the MAC address with a random number. */
1539 random = rte_rand();
1540 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1544 * Virtual Function device init
1547 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1551 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1552 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1553 struct ixgbe_hw *hw =
1554 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1555 struct ixgbe_vfta *shadow_vfta =
1556 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1557 struct ixgbe_hwstrip *hwstrip =
1558 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1559 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1561 PMD_INIT_FUNC_TRACE();
1563 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1564 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1565 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1567 /* for secondary processes, we don't initialise any further as primary
1568 * has already done this work. Only check we don't need a different
1571 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1572 struct ixgbe_tx_queue *txq;
1573 /* TX queue function in primary, set by last queue initialized
1574 * Tx queue may not initialized by primary process
1576 if (eth_dev->data->tx_queues) {
1577 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1578 ixgbe_set_tx_function(eth_dev, txq);
1580 /* Use default TX function if we get here */
1581 PMD_INIT_LOG(NOTICE,
1582 "No TX queues configured yet. Using default TX function.");
1585 ixgbe_set_rx_function(eth_dev);
1590 rte_eth_copy_pci_info(eth_dev, pci_dev);
1592 hw->device_id = pci_dev->id.device_id;
1593 hw->vendor_id = pci_dev->id.vendor_id;
1594 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1596 /* initialize the vfta */
1597 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1599 /* initialize the hw strip bitmap*/
1600 memset(hwstrip, 0, sizeof(*hwstrip));
1602 /* Initialize the shared code (base driver) */
1603 diag = ixgbe_init_shared_code(hw);
1604 if (diag != IXGBE_SUCCESS) {
1605 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1609 /* init_mailbox_params */
1610 hw->mbx.ops.init_params(hw);
1612 /* Reset the hw statistics */
1613 ixgbevf_dev_stats_reset(eth_dev);
1615 /* Disable the interrupts for VF */
1616 ixgbevf_intr_disable(eth_dev);
1618 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1619 diag = hw->mac.ops.reset_hw(hw);
1622 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1623 * the underlying PF driver has not assigned a MAC address to the VF.
1624 * In this case, assign a random MAC address.
1626 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1627 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1629 * This error code will be propagated to the app by
1630 * rte_eth_dev_reset, so use a public error code rather than
1631 * the internal-only IXGBE_ERR_RESET_FAILED
1636 /* negotiate mailbox API version to use with the PF. */
1637 ixgbevf_negotiate_api(hw);
1639 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1640 ixgbevf_get_queues(hw, &tcs, &tc);
1642 /* Allocate memory for storing MAC addresses */
1643 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1644 hw->mac.num_rar_entries, 0);
1645 if (eth_dev->data->mac_addrs == NULL) {
1647 "Failed to allocate %u bytes needed to store "
1649 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1653 /* Generate a random MAC address, if none was assigned by PF. */
1654 if (is_zero_ether_addr(perm_addr)) {
1655 generate_random_mac_addr(perm_addr);
1656 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1658 rte_free(eth_dev->data->mac_addrs);
1659 eth_dev->data->mac_addrs = NULL;
1662 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1663 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1664 "%02x:%02x:%02x:%02x:%02x:%02x",
1665 perm_addr->addr_bytes[0],
1666 perm_addr->addr_bytes[1],
1667 perm_addr->addr_bytes[2],
1668 perm_addr->addr_bytes[3],
1669 perm_addr->addr_bytes[4],
1670 perm_addr->addr_bytes[5]);
1673 /* Copy the permanent MAC address */
1674 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1676 /* reset the hardware with the new settings */
1677 diag = hw->mac.ops.start_hw(hw);
1683 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1687 rte_intr_callback_register(intr_handle,
1688 ixgbevf_dev_interrupt_handler, eth_dev);
1689 rte_intr_enable(intr_handle);
1690 ixgbevf_intr_enable(eth_dev);
1692 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1693 eth_dev->data->port_id, pci_dev->id.vendor_id,
1694 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1699 /* Virtual Function device uninit */
1702 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1704 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1705 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1706 struct ixgbe_hw *hw;
1708 PMD_INIT_FUNC_TRACE();
1710 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1713 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1715 if (hw->adapter_stopped == 0)
1716 ixgbevf_dev_close(eth_dev);
1718 eth_dev->dev_ops = NULL;
1719 eth_dev->rx_pkt_burst = NULL;
1720 eth_dev->tx_pkt_burst = NULL;
1722 /* Disable the interrupts for VF */
1723 ixgbevf_intr_disable(eth_dev);
1725 rte_free(eth_dev->data->mac_addrs);
1726 eth_dev->data->mac_addrs = NULL;
1728 rte_intr_disable(intr_handle);
1729 rte_intr_callback_unregister(intr_handle,
1730 ixgbevf_dev_interrupt_handler, eth_dev);
1736 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1737 struct rte_pci_device *pci_dev)
1739 char name[RTE_ETH_NAME_MAX_LEN];
1740 struct rte_eth_dev *pf_ethdev;
1741 struct rte_eth_devargs eth_da;
1744 if (pci_dev->device.devargs) {
1745 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1750 memset(ð_da, 0, sizeof(eth_da));
1752 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1753 sizeof(struct ixgbe_adapter),
1754 eth_dev_pci_specific_init, pci_dev,
1755 eth_ixgbe_dev_init, NULL);
1757 if (retval || eth_da.nb_representor_ports < 1)
1760 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1761 if (pf_ethdev == NULL)
1764 /* probe VF representor ports */
1765 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1766 struct ixgbe_vf_info *vfinfo;
1767 struct ixgbe_vf_representor representor;
1769 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1770 pf_ethdev->data->dev_private);
1771 if (vfinfo == NULL) {
1773 "no virtual functions supported by PF");
1777 representor.vf_id = eth_da.representor_ports[i];
1778 representor.switch_domain_id = vfinfo->switch_domain_id;
1779 representor.pf_ethdev = pf_ethdev;
1781 /* representor port net_bdf_port */
1782 snprintf(name, sizeof(name), "net_%s_representor_%d",
1783 pci_dev->device.name,
1784 eth_da.representor_ports[i]);
1786 retval = rte_eth_dev_create(&pci_dev->device, name,
1787 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1788 ixgbe_vf_representor_init, &representor);
1791 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1792 "representor %s.", name);
1798 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1800 struct rte_eth_dev *ethdev;
1802 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1806 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1807 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1809 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1812 static struct rte_pci_driver rte_ixgbe_pmd = {
1813 .id_table = pci_id_ixgbe_map,
1814 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1815 RTE_PCI_DRV_IOVA_AS_VA,
1816 .probe = eth_ixgbe_pci_probe,
1817 .remove = eth_ixgbe_pci_remove,
1820 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1821 struct rte_pci_device *pci_dev)
1823 return rte_eth_dev_pci_generic_probe(pci_dev,
1824 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1827 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1829 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1833 * virtual function driver struct
1835 static struct rte_pci_driver rte_ixgbevf_pmd = {
1836 .id_table = pci_id_ixgbevf_map,
1837 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1838 .probe = eth_ixgbevf_pci_probe,
1839 .remove = eth_ixgbevf_pci_remove,
1843 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1845 struct ixgbe_hw *hw =
1846 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847 struct ixgbe_vfta *shadow_vfta =
1848 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1853 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1854 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1855 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1860 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1862 /* update local VFTA copy */
1863 shadow_vfta->vfta[vid_idx] = vfta;
1869 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1872 ixgbe_vlan_hw_strip_enable(dev, queue);
1874 ixgbe_vlan_hw_strip_disable(dev, queue);
1878 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1879 enum rte_vlan_type vlan_type,
1882 struct ixgbe_hw *hw =
1883 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1888 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1889 qinq &= IXGBE_DMATXCTL_GDV;
1891 switch (vlan_type) {
1892 case ETH_VLAN_TYPE_INNER:
1894 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1895 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1896 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1897 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1898 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1899 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1900 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1903 PMD_DRV_LOG(ERR, "Inner type is not supported"
1907 case ETH_VLAN_TYPE_OUTER:
1909 /* Only the high 16-bits is valid */
1910 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1911 IXGBE_EXVET_VET_EXT_SHIFT);
1913 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1914 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1915 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1916 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1917 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1918 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1919 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1925 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1933 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1935 struct ixgbe_hw *hw =
1936 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939 PMD_INIT_FUNC_TRACE();
1941 /* Filter Table Disable */
1942 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1943 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1945 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1949 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1951 struct ixgbe_hw *hw =
1952 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953 struct ixgbe_vfta *shadow_vfta =
1954 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1958 PMD_INIT_FUNC_TRACE();
1960 /* Filter Table Enable */
1961 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1962 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1963 vlnctrl |= IXGBE_VLNCTRL_VFE;
1965 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1967 /* write whatever is in local vfta copy */
1968 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1969 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1973 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1975 struct ixgbe_hwstrip *hwstrip =
1976 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1977 struct ixgbe_rx_queue *rxq;
1979 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1983 IXGBE_SET_HWSTRIP(hwstrip, queue);
1985 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1987 if (queue >= dev->data->nb_rx_queues)
1990 rxq = dev->data->rx_queues[queue];
1993 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1994 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1996 rxq->vlan_flags = PKT_RX_VLAN;
1997 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2002 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2004 struct ixgbe_hw *hw =
2005 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2008 PMD_INIT_FUNC_TRACE();
2010 if (hw->mac.type == ixgbe_mac_82598EB) {
2011 /* No queue level support */
2012 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2016 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2017 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2018 ctrl &= ~IXGBE_RXDCTL_VME;
2019 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2021 /* record those setting for HW strip per queue */
2022 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2026 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2028 struct ixgbe_hw *hw =
2029 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2032 PMD_INIT_FUNC_TRACE();
2034 if (hw->mac.type == ixgbe_mac_82598EB) {
2035 /* No queue level supported */
2036 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2040 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2041 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2042 ctrl |= IXGBE_RXDCTL_VME;
2043 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2045 /* record those setting for HW strip per queue */
2046 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2050 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2052 struct ixgbe_hw *hw =
2053 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056 PMD_INIT_FUNC_TRACE();
2058 /* DMATXCTRL: Geric Double VLAN Disable */
2059 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2060 ctrl &= ~IXGBE_DMATXCTL_GDV;
2061 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2063 /* CTRL_EXT: Global Double VLAN Disable */
2064 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2065 ctrl &= ~IXGBE_EXTENDED_VLAN;
2066 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2071 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2073 struct ixgbe_hw *hw =
2074 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077 PMD_INIT_FUNC_TRACE();
2079 /* DMATXCTRL: Geric Double VLAN Enable */
2080 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2081 ctrl |= IXGBE_DMATXCTL_GDV;
2082 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2084 /* CTRL_EXT: Global Double VLAN Enable */
2085 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2086 ctrl |= IXGBE_EXTENDED_VLAN;
2087 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2089 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2090 if (hw->mac.type == ixgbe_mac_X550 ||
2091 hw->mac.type == ixgbe_mac_X550EM_x ||
2092 hw->mac.type == ixgbe_mac_X550EM_a) {
2093 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2094 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2095 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2099 * VET EXT field in the EXVET register = 0x8100 by default
2100 * So no need to change. Same to VT field of DMATXCTL register
2105 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2107 struct ixgbe_hw *hw =
2108 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2109 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2112 struct ixgbe_rx_queue *rxq;
2115 PMD_INIT_FUNC_TRACE();
2117 if (hw->mac.type == ixgbe_mac_82598EB) {
2118 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2119 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2120 ctrl |= IXGBE_VLNCTRL_VME;
2121 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2123 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2124 ctrl &= ~IXGBE_VLNCTRL_VME;
2125 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2129 * Other 10G NIC, the VLAN strip can be setup
2130 * per queue in RXDCTL
2132 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2133 rxq = dev->data->rx_queues[i];
2134 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2135 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2136 ctrl |= IXGBE_RXDCTL_VME;
2139 ctrl &= ~IXGBE_RXDCTL_VME;
2142 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2144 /* record those setting for HW strip per queue */
2145 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2151 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2154 struct rte_eth_rxmode *rxmode;
2155 struct ixgbe_rx_queue *rxq;
2157 if (mask & ETH_VLAN_STRIP_MASK) {
2158 rxmode = &dev->data->dev_conf.rxmode;
2159 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2160 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2161 rxq = dev->data->rx_queues[i];
2162 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2165 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2166 rxq = dev->data->rx_queues[i];
2167 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2173 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2175 struct rte_eth_rxmode *rxmode;
2176 rxmode = &dev->data->dev_conf.rxmode;
2178 if (mask & ETH_VLAN_STRIP_MASK) {
2179 ixgbe_vlan_hw_strip_config(dev);
2182 if (mask & ETH_VLAN_FILTER_MASK) {
2183 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2184 ixgbe_vlan_hw_filter_enable(dev);
2186 ixgbe_vlan_hw_filter_disable(dev);
2189 if (mask & ETH_VLAN_EXTEND_MASK) {
2190 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2191 ixgbe_vlan_hw_extend_enable(dev);
2193 ixgbe_vlan_hw_extend_disable(dev);
2200 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2202 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2204 ixgbe_vlan_offload_config(dev, mask);
2210 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2212 struct ixgbe_hw *hw =
2213 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2214 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2215 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2217 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2218 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2222 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2224 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2229 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2232 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2238 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2239 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2240 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2241 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2246 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2248 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2249 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2251 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2253 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2254 /* check multi-queue mode */
2255 switch (dev_conf->rxmode.mq_mode) {
2256 case ETH_MQ_RX_VMDQ_DCB:
2257 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2259 case ETH_MQ_RX_VMDQ_DCB_RSS:
2260 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2261 PMD_INIT_LOG(ERR, "SRIOV active,"
2262 " unsupported mq_mode rx %d.",
2263 dev_conf->rxmode.mq_mode);
2266 case ETH_MQ_RX_VMDQ_RSS:
2267 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2268 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2269 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2270 PMD_INIT_LOG(ERR, "SRIOV is active,"
2271 " invalid queue number"
2272 " for VMDQ RSS, allowed"
2273 " value are 1, 2 or 4.");
2277 case ETH_MQ_RX_VMDQ_ONLY:
2278 case ETH_MQ_RX_NONE:
2279 /* if nothing mq mode configure, use default scheme */
2280 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2282 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2283 /* SRIOV only works in VMDq enable mode */
2284 PMD_INIT_LOG(ERR, "SRIOV is active,"
2285 " wrong mq_mode rx %d.",
2286 dev_conf->rxmode.mq_mode);
2290 switch (dev_conf->txmode.mq_mode) {
2291 case ETH_MQ_TX_VMDQ_DCB:
2292 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2293 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2295 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2296 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2300 /* check valid queue number */
2301 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2302 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2303 PMD_INIT_LOG(ERR, "SRIOV is active,"
2304 " nb_rx_q=%d nb_tx_q=%d queue number"
2305 " must be less than or equal to %d.",
2307 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2311 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2312 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2316 /* check configuration for vmdb+dcb mode */
2317 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2318 const struct rte_eth_vmdq_dcb_conf *conf;
2320 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2321 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2322 IXGBE_VMDQ_DCB_NB_QUEUES);
2325 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2326 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2327 conf->nb_queue_pools == ETH_32_POOLS)) {
2328 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2329 " nb_queue_pools must be %d or %d.",
2330 ETH_16_POOLS, ETH_32_POOLS);
2334 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2335 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2337 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2338 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2339 IXGBE_VMDQ_DCB_NB_QUEUES);
2342 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2343 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2344 conf->nb_queue_pools == ETH_32_POOLS)) {
2345 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2346 " nb_queue_pools != %d and"
2347 " nb_queue_pools != %d.",
2348 ETH_16_POOLS, ETH_32_POOLS);
2353 /* For DCB mode check our configuration before we go further */
2354 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2355 const struct rte_eth_dcb_rx_conf *conf;
2357 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2358 if (!(conf->nb_tcs == ETH_4_TCS ||
2359 conf->nb_tcs == ETH_8_TCS)) {
2360 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2361 " and nb_tcs != %d.",
2362 ETH_4_TCS, ETH_8_TCS);
2367 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2368 const struct rte_eth_dcb_tx_conf *conf;
2370 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2371 if (!(conf->nb_tcs == ETH_4_TCS ||
2372 conf->nb_tcs == ETH_8_TCS)) {
2373 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2374 " and nb_tcs != %d.",
2375 ETH_4_TCS, ETH_8_TCS);
2381 * When DCB/VT is off, maximum number of queues changes,
2382 * except for 82598EB, which remains constant.
2384 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2385 hw->mac.type != ixgbe_mac_82598EB) {
2386 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2388 "Neither VT nor DCB are enabled, "
2390 IXGBE_NONE_MODE_TX_NB_QUEUES);
2399 ixgbe_dev_configure(struct rte_eth_dev *dev)
2401 struct ixgbe_interrupt *intr =
2402 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2403 struct ixgbe_adapter *adapter =
2404 (struct ixgbe_adapter *)dev->data->dev_private;
2407 PMD_INIT_FUNC_TRACE();
2408 /* multipe queue mode checking */
2409 ret = ixgbe_check_mq_mode(dev);
2411 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2416 /* set flag to update link status after init */
2417 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2420 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2421 * allocation or vector Rx preconditions we will reset it.
2423 adapter->rx_bulk_alloc_allowed = true;
2424 adapter->rx_vec_allowed = true;
2430 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2432 struct ixgbe_hw *hw =
2433 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2434 struct ixgbe_interrupt *intr =
2435 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2438 /* only set up it on X550EM_X */
2439 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2440 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2441 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2442 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2443 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2444 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2449 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2450 uint16_t tx_rate, uint64_t q_msk)
2452 struct ixgbe_hw *hw;
2453 struct ixgbe_vf_info *vfinfo;
2454 struct rte_eth_link link;
2455 uint8_t nb_q_per_pool;
2456 uint32_t queue_stride;
2457 uint32_t queue_idx, idx = 0, vf_idx;
2459 uint16_t total_rate = 0;
2460 struct rte_pci_device *pci_dev;
2462 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2463 rte_eth_link_get_nowait(dev->data->port_id, &link);
2465 if (vf >= pci_dev->max_vfs)
2468 if (tx_rate > link.link_speed)
2474 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2476 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2477 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2478 queue_idx = vf * queue_stride;
2479 queue_end = queue_idx + nb_q_per_pool - 1;
2480 if (queue_end >= hw->mac.max_tx_queues)
2484 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2487 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2489 total_rate += vfinfo[vf_idx].tx_rate[idx];
2495 /* Store tx_rate for this vf. */
2496 for (idx = 0; idx < nb_q_per_pool; idx++) {
2497 if (((uint64_t)0x1 << idx) & q_msk) {
2498 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2499 vfinfo[vf].tx_rate[idx] = tx_rate;
2500 total_rate += tx_rate;
2504 if (total_rate > dev->data->dev_link.link_speed) {
2505 /* Reset stored TX rate of the VF if it causes exceed
2508 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2512 /* Set RTTBCNRC of each queue/pool for vf X */
2513 for (; queue_idx <= queue_end; queue_idx++) {
2515 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2523 * Configure device link speed and setup link.
2524 * It returns 0 on success.
2527 ixgbe_dev_start(struct rte_eth_dev *dev)
2529 struct ixgbe_hw *hw =
2530 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531 struct ixgbe_vf_info *vfinfo =
2532 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2533 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2534 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2535 uint32_t intr_vector = 0;
2536 int err, link_up = 0, negotiate = 0;
2538 uint32_t allowed_speeds = 0;
2542 uint32_t *link_speeds;
2543 struct ixgbe_tm_conf *tm_conf =
2544 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2546 PMD_INIT_FUNC_TRACE();
2548 /* IXGBE devices don't support:
2549 * - half duplex (checked afterwards for valid speeds)
2550 * - fixed speed: TODO implement
2552 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2554 "Invalid link_speeds for port %u, fix speed not supported",
2555 dev->data->port_id);
2559 /* disable uio/vfio intr/eventfd mapping */
2560 rte_intr_disable(intr_handle);
2563 hw->adapter_stopped = 0;
2564 ixgbe_stop_adapter(hw);
2566 /* reinitialize adapter
2567 * this calls reset and start
2569 status = ixgbe_pf_reset_hw(hw);
2572 hw->mac.ops.start_hw(hw);
2573 hw->mac.get_link_status = true;
2575 /* configure PF module if SRIOV enabled */
2576 ixgbe_pf_host_configure(dev);
2578 ixgbe_dev_phy_intr_setup(dev);
2580 /* check and configure queue intr-vector mapping */
2581 if ((rte_intr_cap_multiple(intr_handle) ||
2582 !RTE_ETH_DEV_SRIOV(dev).active) &&
2583 dev->data->dev_conf.intr_conf.rxq != 0) {
2584 intr_vector = dev->data->nb_rx_queues;
2585 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2586 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2587 IXGBE_MAX_INTR_QUEUE_NUM);
2590 if (rte_intr_efd_enable(intr_handle, intr_vector))
2594 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2595 intr_handle->intr_vec =
2596 rte_zmalloc("intr_vec",
2597 dev->data->nb_rx_queues * sizeof(int), 0);
2598 if (intr_handle->intr_vec == NULL) {
2599 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2600 " intr_vec", dev->data->nb_rx_queues);
2605 /* confiugre msix for sleep until rx interrupt */
2606 ixgbe_configure_msix(dev);
2608 /* initialize transmission unit */
2609 ixgbe_dev_tx_init(dev);
2611 /* This can fail when allocating mbufs for descriptor rings */
2612 err = ixgbe_dev_rx_init(dev);
2614 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2618 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2619 ETH_VLAN_EXTEND_MASK;
2620 err = ixgbe_vlan_offload_config(dev, mask);
2622 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2626 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2627 /* Enable vlan filtering for VMDq */
2628 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2631 /* Configure DCB hw */
2632 ixgbe_configure_dcb(dev);
2634 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2635 err = ixgbe_fdir_configure(dev);
2640 /* Restore vf rate limit */
2641 if (vfinfo != NULL) {
2642 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2643 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2644 if (vfinfo[vf].tx_rate[idx] != 0)
2645 ixgbe_set_vf_rate_limit(
2647 vfinfo[vf].tx_rate[idx],
2651 ixgbe_restore_statistics_mapping(dev);
2653 err = ixgbe_dev_rxtx_start(dev);
2655 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2659 /* Skip link setup if loopback mode is enabled for 82599. */
2660 if (hw->mac.type == ixgbe_mac_82599EB &&
2661 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2662 goto skip_link_setup;
2664 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2665 err = hw->mac.ops.setup_sfp(hw);
2670 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2671 /* Turn on the copper */
2672 ixgbe_set_phy_power(hw, true);
2674 /* Turn on the laser */
2675 ixgbe_enable_tx_laser(hw);
2678 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2681 dev->data->dev_link.link_status = link_up;
2683 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2687 switch (hw->mac.type) {
2688 case ixgbe_mac_X550:
2689 case ixgbe_mac_X550EM_x:
2690 case ixgbe_mac_X550EM_a:
2691 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2692 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2696 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2700 link_speeds = &dev->data->dev_conf.link_speeds;
2701 if (*link_speeds & ~allowed_speeds) {
2702 PMD_INIT_LOG(ERR, "Invalid link setting");
2707 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2708 switch (hw->mac.type) {
2709 case ixgbe_mac_82598EB:
2710 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2712 case ixgbe_mac_82599EB:
2713 case ixgbe_mac_X540:
2714 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2716 case ixgbe_mac_X550:
2717 case ixgbe_mac_X550EM_x:
2718 case ixgbe_mac_X550EM_a:
2719 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2722 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2725 if (*link_speeds & ETH_LINK_SPEED_10G)
2726 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2727 if (*link_speeds & ETH_LINK_SPEED_5G)
2728 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2729 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2730 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2731 if (*link_speeds & ETH_LINK_SPEED_1G)
2732 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2733 if (*link_speeds & ETH_LINK_SPEED_100M)
2734 speed |= IXGBE_LINK_SPEED_100_FULL;
2737 err = ixgbe_setup_link(hw, speed, link_up);
2741 ixgbe_dev_link_update(dev, 0);
2745 if (rte_intr_allow_others(intr_handle)) {
2746 /* check if lsc interrupt is enabled */
2747 if (dev->data->dev_conf.intr_conf.lsc != 0)
2748 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2750 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2751 ixgbe_dev_macsec_interrupt_setup(dev);
2753 rte_intr_callback_unregister(intr_handle,
2754 ixgbe_dev_interrupt_handler, dev);
2755 if (dev->data->dev_conf.intr_conf.lsc != 0)
2756 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2757 " no intr multiplex");
2760 /* check if rxq interrupt is enabled */
2761 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2762 rte_intr_dp_is_en(intr_handle))
2763 ixgbe_dev_rxq_interrupt_setup(dev);
2765 /* enable uio/vfio intr/eventfd mapping */
2766 rte_intr_enable(intr_handle);
2768 /* resume enabled intr since hw reset */
2769 ixgbe_enable_intr(dev);
2770 ixgbe_l2_tunnel_conf(dev);
2771 ixgbe_filter_restore(dev);
2773 if (tm_conf->root && !tm_conf->committed)
2774 PMD_DRV_LOG(WARNING,
2775 "please call hierarchy_commit() "
2776 "before starting the port");
2781 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2782 ixgbe_dev_clear_queues(dev);
2787 * Stop device: disable rx and tx functions to allow for reconfiguring.
2790 ixgbe_dev_stop(struct rte_eth_dev *dev)
2792 struct rte_eth_link link;
2793 struct ixgbe_hw *hw =
2794 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795 struct ixgbe_vf_info *vfinfo =
2796 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2797 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2798 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2800 struct ixgbe_tm_conf *tm_conf =
2801 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2803 PMD_INIT_FUNC_TRACE();
2805 /* disable interrupts */
2806 ixgbe_disable_intr(hw);
2809 ixgbe_pf_reset_hw(hw);
2810 hw->adapter_stopped = 0;
2813 ixgbe_stop_adapter(hw);
2815 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2816 vfinfo[vf].clear_to_send = false;
2818 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2819 /* Turn off the copper */
2820 ixgbe_set_phy_power(hw, false);
2822 /* Turn off the laser */
2823 ixgbe_disable_tx_laser(hw);
2826 ixgbe_dev_clear_queues(dev);
2828 /* Clear stored conf */
2829 dev->data->scattered_rx = 0;
2832 /* Clear recorded link status */
2833 memset(&link, 0, sizeof(link));
2834 rte_eth_linkstatus_set(dev, &link);
2836 if (!rte_intr_allow_others(intr_handle))
2837 /* resume to the default handler */
2838 rte_intr_callback_register(intr_handle,
2839 ixgbe_dev_interrupt_handler,
2842 /* Clean datapath event and queue/vec mapping */
2843 rte_intr_efd_disable(intr_handle);
2844 if (intr_handle->intr_vec != NULL) {
2845 rte_free(intr_handle->intr_vec);
2846 intr_handle->intr_vec = NULL;
2849 /* reset hierarchy commit */
2850 tm_conf->committed = false;
2854 * Set device link up: enable tx.
2857 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2859 struct ixgbe_hw *hw =
2860 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861 if (hw->mac.type == ixgbe_mac_82599EB) {
2862 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2863 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2864 /* Not suported in bypass mode */
2865 PMD_INIT_LOG(ERR, "Set link up is not supported "
2866 "by device id 0x%x", hw->device_id);
2872 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2873 /* Turn on the copper */
2874 ixgbe_set_phy_power(hw, true);
2876 /* Turn on the laser */
2877 ixgbe_enable_tx_laser(hw);
2884 * Set device link down: disable tx.
2887 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2889 struct ixgbe_hw *hw =
2890 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891 if (hw->mac.type == ixgbe_mac_82599EB) {
2892 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2893 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2894 /* Not suported in bypass mode */
2895 PMD_INIT_LOG(ERR, "Set link down is not supported "
2896 "by device id 0x%x", hw->device_id);
2902 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2903 /* Turn off the copper */
2904 ixgbe_set_phy_power(hw, false);
2906 /* Turn off the laser */
2907 ixgbe_disable_tx_laser(hw);
2914 * Reset and stop device.
2917 ixgbe_dev_close(struct rte_eth_dev *dev)
2919 struct ixgbe_hw *hw =
2920 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2922 PMD_INIT_FUNC_TRACE();
2924 ixgbe_pf_reset_hw(hw);
2926 ixgbe_dev_stop(dev);
2927 hw->adapter_stopped = 1;
2929 ixgbe_dev_free_queues(dev);
2931 ixgbe_disable_pcie_master(hw);
2933 /* reprogram the RAR[0] in case user changed it. */
2934 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2941 ixgbe_dev_reset(struct rte_eth_dev *dev)
2945 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2946 * its VF to make them align with it. The detailed notification
2947 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2948 * To avoid unexpected behavior in VF, currently reset of PF with
2949 * SR-IOV activation is not supported. It might be supported later.
2951 if (dev->data->sriov.active)
2954 ret = eth_ixgbe_dev_uninit(dev);
2958 ret = eth_ixgbe_dev_init(dev, NULL);
2964 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2965 struct ixgbe_hw_stats *hw_stats,
2966 struct ixgbe_macsec_stats *macsec_stats,
2967 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2968 uint64_t *total_qprc, uint64_t *total_qprdc)
2970 uint32_t bprc, lxon, lxoff, total;
2971 uint32_t delta_gprc = 0;
2973 /* Workaround for RX byte count not including CRC bytes when CRC
2974 * strip is enabled. CRC bytes are removed from counters when crc_strip
2977 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2978 IXGBE_HLREG0_RXCRCSTRP);
2980 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2981 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2982 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2983 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2985 for (i = 0; i < 8; i++) {
2986 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2988 /* global total per queue */
2989 hw_stats->mpc[i] += mp;
2990 /* Running comprehensive total for stats display */
2991 *total_missed_rx += hw_stats->mpc[i];
2992 if (hw->mac.type == ixgbe_mac_82598EB) {
2993 hw_stats->rnbc[i] +=
2994 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2995 hw_stats->pxonrxc[i] +=
2996 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2997 hw_stats->pxoffrxc[i] +=
2998 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3000 hw_stats->pxonrxc[i] +=
3001 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3002 hw_stats->pxoffrxc[i] +=
3003 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3004 hw_stats->pxon2offc[i] +=
3005 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3007 hw_stats->pxontxc[i] +=
3008 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3009 hw_stats->pxofftxc[i] +=
3010 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3012 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3013 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3014 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3015 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3017 delta_gprc += delta_qprc;
3019 hw_stats->qprc[i] += delta_qprc;
3020 hw_stats->qptc[i] += delta_qptc;
3022 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3023 hw_stats->qbrc[i] +=
3024 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3026 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3028 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3029 hw_stats->qbtc[i] +=
3030 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3032 hw_stats->qprdc[i] += delta_qprdc;
3033 *total_qprdc += hw_stats->qprdc[i];
3035 *total_qprc += hw_stats->qprc[i];
3036 *total_qbrc += hw_stats->qbrc[i];
3038 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3039 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3040 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3043 * An errata states that gprc actually counts good + missed packets:
3044 * Workaround to set gprc to summated queue packet receives
3046 hw_stats->gprc = *total_qprc;
3048 if (hw->mac.type != ixgbe_mac_82598EB) {
3049 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3050 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3051 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3052 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3053 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3054 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3055 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3056 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3058 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3059 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3060 /* 82598 only has a counter in the high register */
3061 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3062 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3063 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3065 uint64_t old_tpr = hw_stats->tpr;
3067 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3068 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3071 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3073 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3074 hw_stats->gptc += delta_gptc;
3075 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3076 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3079 * Workaround: mprc hardware is incorrectly counting
3080 * broadcasts, so for now we subtract those.
3082 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3083 hw_stats->bprc += bprc;
3084 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3085 if (hw->mac.type == ixgbe_mac_82598EB)
3086 hw_stats->mprc -= bprc;
3088 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3089 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3090 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3091 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3092 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3093 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3095 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3096 hw_stats->lxontxc += lxon;
3097 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3098 hw_stats->lxofftxc += lxoff;
3099 total = lxon + lxoff;
3101 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3102 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3103 hw_stats->gptc -= total;
3104 hw_stats->mptc -= total;
3105 hw_stats->ptc64 -= total;
3106 hw_stats->gotc -= total * ETHER_MIN_LEN;
3108 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3109 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3110 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3111 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3112 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3113 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3114 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3115 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3116 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3117 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3118 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3119 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3120 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3121 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3122 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3123 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3124 /* Only read FCOE on 82599 */
3125 if (hw->mac.type != ixgbe_mac_82598EB) {
3126 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3127 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3128 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3129 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3130 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3133 /* Flow Director Stats registers */
3134 if (hw->mac.type != ixgbe_mac_82598EB) {
3135 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3136 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3137 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3138 IXGBE_FDIRUSTAT) & 0xFFFF;
3139 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3140 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3141 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3142 IXGBE_FDIRFSTAT) & 0xFFFF;
3143 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3144 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3146 /* MACsec Stats registers */
3147 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3148 macsec_stats->out_pkts_encrypted +=
3149 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3150 macsec_stats->out_pkts_protected +=
3151 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3152 macsec_stats->out_octets_encrypted +=
3153 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3154 macsec_stats->out_octets_protected +=
3155 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3156 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3157 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3158 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3159 macsec_stats->in_pkts_unknownsci +=
3160 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3161 macsec_stats->in_octets_decrypted +=
3162 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3163 macsec_stats->in_octets_validated +=
3164 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3165 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3166 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3167 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3168 for (i = 0; i < 2; i++) {
3169 macsec_stats->in_pkts_ok +=
3170 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3171 macsec_stats->in_pkts_invalid +=
3172 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3173 macsec_stats->in_pkts_notvalid +=
3174 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3176 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3177 macsec_stats->in_pkts_notusingsa +=
3178 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3182 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3185 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3187 struct ixgbe_hw *hw =
3188 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3189 struct ixgbe_hw_stats *hw_stats =
3190 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3191 struct ixgbe_macsec_stats *macsec_stats =
3192 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3193 dev->data->dev_private);
3194 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3197 total_missed_rx = 0;
3202 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3203 &total_qbrc, &total_qprc, &total_qprdc);
3208 /* Fill out the rte_eth_stats statistics structure */
3209 stats->ipackets = total_qprc;
3210 stats->ibytes = total_qbrc;
3211 stats->opackets = hw_stats->gptc;
3212 stats->obytes = hw_stats->gotc;
3214 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3215 stats->q_ipackets[i] = hw_stats->qprc[i];
3216 stats->q_opackets[i] = hw_stats->qptc[i];
3217 stats->q_ibytes[i] = hw_stats->qbrc[i];
3218 stats->q_obytes[i] = hw_stats->qbtc[i];
3219 stats->q_errors[i] = hw_stats->qprdc[i];
3223 stats->imissed = total_missed_rx;
3224 stats->ierrors = hw_stats->crcerrs +
3241 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3243 struct ixgbe_hw_stats *stats =
3244 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3246 /* HW registers are cleared on read */
3247 ixgbe_dev_stats_get(dev, NULL);
3249 /* Reset software totals */
3250 memset(stats, 0, sizeof(*stats));
3253 /* This function calculates the number of xstats based on the current config */
3255 ixgbe_xstats_calc_num(void) {
3256 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3257 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3258 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3261 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3262 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3264 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3265 unsigned stat, i, count;
3267 if (xstats_names != NULL) {
3270 /* Note: limit >= cnt_stats checked upstream
3271 * in rte_eth_xstats_names()
3274 /* Extended stats from ixgbe_hw_stats */
3275 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3276 snprintf(xstats_names[count].name,
3277 sizeof(xstats_names[count].name),
3279 rte_ixgbe_stats_strings[i].name);
3284 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3285 snprintf(xstats_names[count].name,
3286 sizeof(xstats_names[count].name),
3288 rte_ixgbe_macsec_strings[i].name);
3292 /* RX Priority Stats */
3293 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3294 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3295 snprintf(xstats_names[count].name,
3296 sizeof(xstats_names[count].name),
3297 "rx_priority%u_%s", i,
3298 rte_ixgbe_rxq_strings[stat].name);
3303 /* TX Priority Stats */
3304 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3305 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3306 snprintf(xstats_names[count].name,
3307 sizeof(xstats_names[count].name),
3308 "tx_priority%u_%s", i,
3309 rte_ixgbe_txq_strings[stat].name);
3317 static int ixgbe_dev_xstats_get_names_by_id(
3318 struct rte_eth_dev *dev,
3319 struct rte_eth_xstat_name *xstats_names,
3320 const uint64_t *ids,
3324 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3325 unsigned int stat, i, count;
3327 if (xstats_names != NULL) {
3330 /* Note: limit >= cnt_stats checked upstream
3331 * in rte_eth_xstats_names()
3334 /* Extended stats from ixgbe_hw_stats */
3335 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3336 snprintf(xstats_names[count].name,
3337 sizeof(xstats_names[count].name),
3339 rte_ixgbe_stats_strings[i].name);
3344 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3345 snprintf(xstats_names[count].name,
3346 sizeof(xstats_names[count].name),
3348 rte_ixgbe_macsec_strings[i].name);
3352 /* RX Priority Stats */
3353 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3354 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3355 snprintf(xstats_names[count].name,
3356 sizeof(xstats_names[count].name),
3357 "rx_priority%u_%s", i,
3358 rte_ixgbe_rxq_strings[stat].name);
3363 /* TX Priority Stats */
3364 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3365 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3366 snprintf(xstats_names[count].name,
3367 sizeof(xstats_names[count].name),
3368 "tx_priority%u_%s", i,
3369 rte_ixgbe_txq_strings[stat].name);
3378 uint16_t size = ixgbe_xstats_calc_num();
3379 struct rte_eth_xstat_name xstats_names_copy[size];
3381 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3384 for (i = 0; i < limit; i++) {
3385 if (ids[i] >= size) {
3386 PMD_INIT_LOG(ERR, "id value isn't valid");
3389 strcpy(xstats_names[i].name,
3390 xstats_names_copy[ids[i]].name);
3395 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3396 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3400 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3403 if (xstats_names != NULL)
3404 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3405 snprintf(xstats_names[i].name,
3406 sizeof(xstats_names[i].name),
3407 "%s", rte_ixgbevf_stats_strings[i].name);
3408 return IXGBEVF_NB_XSTATS;
3412 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3415 struct ixgbe_hw *hw =
3416 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417 struct ixgbe_hw_stats *hw_stats =
3418 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3419 struct ixgbe_macsec_stats *macsec_stats =
3420 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3421 dev->data->dev_private);
3422 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3423 unsigned i, stat, count = 0;
3425 count = ixgbe_xstats_calc_num();
3430 total_missed_rx = 0;
3435 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3436 &total_qbrc, &total_qprc, &total_qprdc);
3438 /* If this is a reset xstats is NULL, and we have cleared the
3439 * registers by reading them.
3444 /* Extended stats from ixgbe_hw_stats */
3446 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3447 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3448 rte_ixgbe_stats_strings[i].offset);
3449 xstats[count].id = count;
3454 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3455 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3456 rte_ixgbe_macsec_strings[i].offset);
3457 xstats[count].id = count;
3461 /* RX Priority Stats */
3462 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3463 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3464 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3465 rte_ixgbe_rxq_strings[stat].offset +
3466 (sizeof(uint64_t) * i));
3467 xstats[count].id = count;
3472 /* TX Priority Stats */
3473 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3474 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3475 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3476 rte_ixgbe_txq_strings[stat].offset +
3477 (sizeof(uint64_t) * i));
3478 xstats[count].id = count;
3486 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3487 uint64_t *values, unsigned int n)
3490 struct ixgbe_hw *hw =
3491 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3492 struct ixgbe_hw_stats *hw_stats =
3493 IXGBE_DEV_PRIVATE_TO_STATS(
3494 dev->data->dev_private);
3495 struct ixgbe_macsec_stats *macsec_stats =
3496 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3497 dev->data->dev_private);
3498 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3499 unsigned int i, stat, count = 0;
3501 count = ixgbe_xstats_calc_num();
3503 if (!ids && n < count)
3506 total_missed_rx = 0;
3511 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3512 &total_missed_rx, &total_qbrc, &total_qprc,
3515 /* If this is a reset xstats is NULL, and we have cleared the
3516 * registers by reading them.
3518 if (!ids && !values)
3521 /* Extended stats from ixgbe_hw_stats */
3523 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3524 values[count] = *(uint64_t *)(((char *)hw_stats) +
3525 rte_ixgbe_stats_strings[i].offset);
3530 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3531 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3532 rte_ixgbe_macsec_strings[i].offset);
3536 /* RX Priority Stats */
3537 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3538 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3540 *(uint64_t *)(((char *)hw_stats) +
3541 rte_ixgbe_rxq_strings[stat].offset +
3542 (sizeof(uint64_t) * i));
3547 /* TX Priority Stats */
3548 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3549 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3551 *(uint64_t *)(((char *)hw_stats) +
3552 rte_ixgbe_txq_strings[stat].offset +
3553 (sizeof(uint64_t) * i));
3561 uint16_t size = ixgbe_xstats_calc_num();
3562 uint64_t values_copy[size];
3564 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3566 for (i = 0; i < n; i++) {
3567 if (ids[i] >= size) {
3568 PMD_INIT_LOG(ERR, "id value isn't valid");
3571 values[i] = values_copy[ids[i]];
3577 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3579 struct ixgbe_hw_stats *stats =
3580 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3581 struct ixgbe_macsec_stats *macsec_stats =
3582 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3583 dev->data->dev_private);
3585 unsigned count = ixgbe_xstats_calc_num();
3587 /* HW registers are cleared on read */
3588 ixgbe_dev_xstats_get(dev, NULL, count);
3590 /* Reset software totals */
3591 memset(stats, 0, sizeof(*stats));
3592 memset(macsec_stats, 0, sizeof(*macsec_stats));
3596 ixgbevf_update_stats(struct rte_eth_dev *dev)
3598 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3599 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3600 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3602 /* Good Rx packet, include VF loopback */
3603 UPDATE_VF_STAT(IXGBE_VFGPRC,
3604 hw_stats->last_vfgprc, hw_stats->vfgprc);
3606 /* Good Rx octets, include VF loopback */
3607 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3608 hw_stats->last_vfgorc, hw_stats->vfgorc);
3610 /* Good Tx packet, include VF loopback */
3611 UPDATE_VF_STAT(IXGBE_VFGPTC,
3612 hw_stats->last_vfgptc, hw_stats->vfgptc);
3614 /* Good Tx octets, include VF loopback */
3615 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3616 hw_stats->last_vfgotc, hw_stats->vfgotc);
3618 /* Rx Multicst Packet */
3619 UPDATE_VF_STAT(IXGBE_VFMPRC,
3620 hw_stats->last_vfmprc, hw_stats->vfmprc);
3624 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3627 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3628 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3631 if (n < IXGBEVF_NB_XSTATS)
3632 return IXGBEVF_NB_XSTATS;
3634 ixgbevf_update_stats(dev);
3639 /* Extended stats */
3640 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3642 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3643 rte_ixgbevf_stats_strings[i].offset);
3646 return IXGBEVF_NB_XSTATS;
3650 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3652 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3653 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3655 ixgbevf_update_stats(dev);
3660 stats->ipackets = hw_stats->vfgprc;
3661 stats->ibytes = hw_stats->vfgorc;
3662 stats->opackets = hw_stats->vfgptc;
3663 stats->obytes = hw_stats->vfgotc;
3668 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3670 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3671 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3673 /* Sync HW register to the last stats */
3674 ixgbevf_dev_stats_get(dev, NULL);
3676 /* reset HW current stats*/
3677 hw_stats->vfgprc = 0;
3678 hw_stats->vfgorc = 0;
3679 hw_stats->vfgptc = 0;
3680 hw_stats->vfgotc = 0;
3684 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3686 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3687 u16 eeprom_verh, eeprom_verl;
3691 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3692 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3694 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3695 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3697 ret += 1; /* add the size of '\0' */
3698 if (fw_size < (u32)ret)
3705 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3707 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3708 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3711 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3712 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3713 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3715 * When DCB/VT is off, maximum number of queues changes,
3716 * except for 82598EB, which remains constant.
3718 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3719 hw->mac.type != ixgbe_mac_82598EB)
3720 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3722 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3723 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3724 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3725 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3726 dev_info->max_vfs = pci_dev->max_vfs;
3727 if (hw->mac.type == ixgbe_mac_82598EB)
3728 dev_info->max_vmdq_pools = ETH_16_POOLS;
3730 dev_info->max_vmdq_pools = ETH_64_POOLS;
3731 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3732 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3733 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3734 dev_info->rx_queue_offload_capa);
3735 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3736 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3738 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3740 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3741 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3742 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3744 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3749 dev_info->default_txconf = (struct rte_eth_txconf) {
3751 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3752 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3753 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3755 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3756 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3760 dev_info->rx_desc_lim = rx_desc_lim;
3761 dev_info->tx_desc_lim = tx_desc_lim;
3763 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3764 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3765 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3767 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3768 if (hw->mac.type == ixgbe_mac_X540 ||
3769 hw->mac.type == ixgbe_mac_X540_vf ||
3770 hw->mac.type == ixgbe_mac_X550 ||
3771 hw->mac.type == ixgbe_mac_X550_vf) {
3772 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3774 if (hw->mac.type == ixgbe_mac_X550) {
3775 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3776 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3779 /* Driver-preferred Rx/Tx parameters */
3780 dev_info->default_rxportconf.burst_size = 32;
3781 dev_info->default_txportconf.burst_size = 32;
3782 dev_info->default_rxportconf.nb_queues = 1;
3783 dev_info->default_txportconf.nb_queues = 1;
3784 dev_info->default_rxportconf.ring_size = 256;
3785 dev_info->default_txportconf.ring_size = 256;
3788 static const uint32_t *
3789 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3791 static const uint32_t ptypes[] = {
3792 /* For non-vec functions,
3793 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3794 * for vec functions,
3795 * refers to _recv_raw_pkts_vec().
3799 RTE_PTYPE_L3_IPV4_EXT,
3801 RTE_PTYPE_L3_IPV6_EXT,
3805 RTE_PTYPE_TUNNEL_IP,
3806 RTE_PTYPE_INNER_L3_IPV6,
3807 RTE_PTYPE_INNER_L3_IPV6_EXT,
3808 RTE_PTYPE_INNER_L4_TCP,
3809 RTE_PTYPE_INNER_L4_UDP,
3813 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3814 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3815 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3816 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3819 #if defined(RTE_ARCH_X86)
3820 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3821 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3828 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3829 struct rte_eth_dev_info *dev_info)
3831 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3832 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3834 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3835 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3836 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3837 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3838 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3839 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3840 dev_info->max_vfs = pci_dev->max_vfs;
3841 if (hw->mac.type == ixgbe_mac_82598EB)
3842 dev_info->max_vmdq_pools = ETH_16_POOLS;
3844 dev_info->max_vmdq_pools = ETH_64_POOLS;
3845 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3846 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3847 dev_info->rx_queue_offload_capa);
3848 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3849 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3851 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3853 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3854 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3855 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3857 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3862 dev_info->default_txconf = (struct rte_eth_txconf) {
3864 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3865 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3866 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3868 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3869 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3873 dev_info->rx_desc_lim = rx_desc_lim;
3874 dev_info->tx_desc_lim = tx_desc_lim;
3878 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3879 int *link_up, int wait_to_complete)
3882 * for a quick link status checking, wait_to_compelet == 0,
3883 * skip PF link status checking
3885 bool no_pflink_check = wait_to_complete == 0;
3886 struct ixgbe_mbx_info *mbx = &hw->mbx;
3887 struct ixgbe_mac_info *mac = &hw->mac;
3888 uint32_t links_reg, in_msg;
3891 /* If we were hit with a reset drop the link */
3892 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3893 mac->get_link_status = true;
3895 if (!mac->get_link_status)
3898 /* if link status is down no point in checking to see if pf is up */
3899 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3900 if (!(links_reg & IXGBE_LINKS_UP))
3903 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3904 * before the link status is correct
3906 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3909 for (i = 0; i < 5; i++) {
3911 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3913 if (!(links_reg & IXGBE_LINKS_UP))
3918 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3919 case IXGBE_LINKS_SPEED_10G_82599:
3920 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3921 if (hw->mac.type >= ixgbe_mac_X550) {
3922 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3923 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3926 case IXGBE_LINKS_SPEED_1G_82599:
3927 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3929 case IXGBE_LINKS_SPEED_100_82599:
3930 *speed = IXGBE_LINK_SPEED_100_FULL;
3931 if (hw->mac.type == ixgbe_mac_X550) {
3932 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3933 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3936 case IXGBE_LINKS_SPEED_10_X550EM_A:
3937 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3938 /* Since Reserved in older MAC's */
3939 if (hw->mac.type >= ixgbe_mac_X550)
3940 *speed = IXGBE_LINK_SPEED_10_FULL;
3943 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3946 if (no_pflink_check) {
3947 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3948 mac->get_link_status = true;
3950 mac->get_link_status = false;
3954 /* if the read failed it could just be a mailbox collision, best wait
3955 * until we are called again and don't report an error
3957 if (mbx->ops.read(hw, &in_msg, 1, 0))
3960 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3961 /* msg is not CTS and is NACK we must have lost CTS status */
3962 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3967 /* the pf is talking, if we timed out in the past we reinit */
3968 if (!mbx->timeout) {
3973 /* if we passed all the tests above then the link is up and we no
3974 * longer need to check for link
3976 mac->get_link_status = false;
3979 *link_up = !mac->get_link_status;
3983 /* return 0 means link status changed, -1 means not changed */
3985 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3986 int wait_to_complete, int vf)
3988 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3989 struct rte_eth_link link;
3990 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3991 struct ixgbe_interrupt *intr =
3992 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3997 bool autoneg = false;
3999 memset(&link, 0, sizeof(link));
4000 link.link_status = ETH_LINK_DOWN;
4001 link.link_speed = ETH_SPEED_NUM_NONE;
4002 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4003 link.link_autoneg = ETH_LINK_AUTONEG;
4005 hw->mac.get_link_status = true;
4007 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
4008 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4009 speed = hw->phy.autoneg_advertised;
4011 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4012 ixgbe_setup_link(hw, speed, true);
4015 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4016 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4020 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4022 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4025 link.link_speed = ETH_SPEED_NUM_100M;
4026 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4027 return rte_eth_linkstatus_set(dev, &link);
4031 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4032 return rte_eth_linkstatus_set(dev, &link);
4035 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4036 link.link_status = ETH_LINK_UP;
4037 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4039 switch (link_speed) {
4041 case IXGBE_LINK_SPEED_UNKNOWN:
4042 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4043 link.link_speed = ETH_SPEED_NUM_100M;
4046 case IXGBE_LINK_SPEED_100_FULL:
4047 link.link_speed = ETH_SPEED_NUM_100M;
4050 case IXGBE_LINK_SPEED_1GB_FULL:
4051 link.link_speed = ETH_SPEED_NUM_1G;
4054 case IXGBE_LINK_SPEED_2_5GB_FULL:
4055 link.link_speed = ETH_SPEED_NUM_2_5G;
4058 case IXGBE_LINK_SPEED_5GB_FULL:
4059 link.link_speed = ETH_SPEED_NUM_5G;
4062 case IXGBE_LINK_SPEED_10GB_FULL:
4063 link.link_speed = ETH_SPEED_NUM_10G;
4067 return rte_eth_linkstatus_set(dev, &link);
4071 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4073 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4077 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4079 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4083 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4085 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4088 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4089 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4090 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4094 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4096 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4099 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4100 fctrl &= (~IXGBE_FCTRL_UPE);
4101 if (dev->data->all_multicast == 1)
4102 fctrl |= IXGBE_FCTRL_MPE;
4104 fctrl &= (~IXGBE_FCTRL_MPE);
4105 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4109 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4111 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4114 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4115 fctrl |= IXGBE_FCTRL_MPE;
4116 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4120 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4122 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4125 if (dev->data->promiscuous == 1)
4126 return; /* must remain in all_multicast mode */
4128 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4129 fctrl &= (~IXGBE_FCTRL_MPE);
4130 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4134 * It clears the interrupt causes and enables the interrupt.
4135 * It will be called once only during nic initialized.
4138 * Pointer to struct rte_eth_dev.
4140 * Enable or Disable.
4143 * - On success, zero.
4144 * - On failure, a negative value.
4147 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4149 struct ixgbe_interrupt *intr =
4150 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4152 ixgbe_dev_link_status_print(dev);
4154 intr->mask |= IXGBE_EICR_LSC;
4156 intr->mask &= ~IXGBE_EICR_LSC;
4162 * It clears the interrupt causes and enables the interrupt.
4163 * It will be called once only during nic initialized.
4166 * Pointer to struct rte_eth_dev.
4169 * - On success, zero.
4170 * - On failure, a negative value.
4173 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4175 struct ixgbe_interrupt *intr =
4176 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4178 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4184 * It clears the interrupt causes and enables the interrupt.
4185 * It will be called once only during nic initialized.
4188 * Pointer to struct rte_eth_dev.
4191 * - On success, zero.
4192 * - On failure, a negative value.
4195 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4197 struct ixgbe_interrupt *intr =
4198 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4200 intr->mask |= IXGBE_EICR_LINKSEC;
4206 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4209 * Pointer to struct rte_eth_dev.
4212 * - On success, zero.
4213 * - On failure, a negative value.
4216 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4219 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4220 struct ixgbe_interrupt *intr =
4221 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4223 /* clear all cause mask */
4224 ixgbe_disable_intr(hw);
4226 /* read-on-clear nic registers here */
4227 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4228 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4232 /* set flag for async link update */
4233 if (eicr & IXGBE_EICR_LSC)
4234 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4236 if (eicr & IXGBE_EICR_MAILBOX)
4237 intr->flags |= IXGBE_FLAG_MAILBOX;
4239 if (eicr & IXGBE_EICR_LINKSEC)
4240 intr->flags |= IXGBE_FLAG_MACSEC;
4242 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4243 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4244 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4245 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4251 * It gets and then prints the link status.
4254 * Pointer to struct rte_eth_dev.
4257 * - On success, zero.
4258 * - On failure, a negative value.
4261 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4263 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4264 struct rte_eth_link link;
4266 rte_eth_linkstatus_get(dev, &link);
4268 if (link.link_status) {
4269 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4270 (int)(dev->data->port_id),
4271 (unsigned)link.link_speed,
4272 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4273 "full-duplex" : "half-duplex");
4275 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4276 (int)(dev->data->port_id));
4278 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4279 pci_dev->addr.domain,
4281 pci_dev->addr.devid,
4282 pci_dev->addr.function);
4286 * It executes link_update after knowing an interrupt occurred.
4289 * Pointer to struct rte_eth_dev.
4292 * - On success, zero.
4293 * - On failure, a negative value.
4296 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4298 struct ixgbe_interrupt *intr =
4299 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4301 struct ixgbe_hw *hw =
4302 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4304 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4306 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4307 ixgbe_pf_mbx_process(dev);
4308 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4311 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4312 ixgbe_handle_lasi(hw);
4313 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4316 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4317 struct rte_eth_link link;
4319 /* get the link status before link update, for predicting later */
4320 rte_eth_linkstatus_get(dev, &link);
4322 ixgbe_dev_link_update(dev, 0);
4325 if (!link.link_status)
4326 /* handle it 1 sec later, wait it being stable */
4327 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4328 /* likely to down */
4330 /* handle it 4 sec later, wait it being stable */
4331 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4333 ixgbe_dev_link_status_print(dev);
4334 if (rte_eal_alarm_set(timeout * 1000,
4335 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4336 PMD_DRV_LOG(ERR, "Error setting alarm");
4338 /* remember original mask */
4339 intr->mask_original = intr->mask;
4340 /* only disable lsc interrupt */
4341 intr->mask &= ~IXGBE_EIMS_LSC;
4345 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4346 ixgbe_enable_intr(dev);
4352 * Interrupt handler which shall be registered for alarm callback for delayed
4353 * handling specific interrupt to wait for the stable nic state. As the
4354 * NIC interrupt state is not stable for ixgbe after link is just down,
4355 * it needs to wait 4 seconds to get the stable status.
4358 * Pointer to interrupt handle.
4360 * The address of parameter (struct rte_eth_dev *) regsitered before.
4366 ixgbe_dev_interrupt_delayed_handler(void *param)
4368 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4369 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4370 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4371 struct ixgbe_interrupt *intr =
4372 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4373 struct ixgbe_hw *hw =
4374 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4377 ixgbe_disable_intr(hw);
4379 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4380 if (eicr & IXGBE_EICR_MAILBOX)
4381 ixgbe_pf_mbx_process(dev);
4383 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4384 ixgbe_handle_lasi(hw);
4385 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4388 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4389 ixgbe_dev_link_update(dev, 0);
4390 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4391 ixgbe_dev_link_status_print(dev);
4392 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4396 if (intr->flags & IXGBE_FLAG_MACSEC) {
4397 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4399 intr->flags &= ~IXGBE_FLAG_MACSEC;
4402 /* restore original mask */
4403 intr->mask = intr->mask_original;
4404 intr->mask_original = 0;
4406 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4407 ixgbe_enable_intr(dev);
4408 rte_intr_enable(intr_handle);
4412 * Interrupt handler triggered by NIC for handling
4413 * specific interrupt.
4416 * Pointer to interrupt handle.
4418 * The address of parameter (struct rte_eth_dev *) regsitered before.
4424 ixgbe_dev_interrupt_handler(void *param)
4426 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4428 ixgbe_dev_interrupt_get_status(dev);
4429 ixgbe_dev_interrupt_action(dev);
4433 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4435 struct ixgbe_hw *hw;
4437 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4438 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4442 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4444 struct ixgbe_hw *hw;
4446 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4451 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4453 struct ixgbe_hw *hw;
4459 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4461 fc_conf->pause_time = hw->fc.pause_time;
4462 fc_conf->high_water = hw->fc.high_water[0];
4463 fc_conf->low_water = hw->fc.low_water[0];
4464 fc_conf->send_xon = hw->fc.send_xon;
4465 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4468 * Return rx_pause status according to actual setting of
4471 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4472 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4478 * Return tx_pause status according to actual setting of
4481 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4482 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4487 if (rx_pause && tx_pause)
4488 fc_conf->mode = RTE_FC_FULL;
4490 fc_conf->mode = RTE_FC_RX_PAUSE;
4492 fc_conf->mode = RTE_FC_TX_PAUSE;
4494 fc_conf->mode = RTE_FC_NONE;
4500 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4502 struct ixgbe_hw *hw;
4504 uint32_t rx_buf_size;
4505 uint32_t max_high_water;
4507 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4514 PMD_INIT_FUNC_TRACE();
4516 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4517 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4518 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4521 * At least reserve one Ethernet frame for watermark
4522 * high_water/low_water in kilo bytes for ixgbe
4524 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4525 if ((fc_conf->high_water > max_high_water) ||
4526 (fc_conf->high_water < fc_conf->low_water)) {
4527 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4528 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4532 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4533 hw->fc.pause_time = fc_conf->pause_time;
4534 hw->fc.high_water[0] = fc_conf->high_water;
4535 hw->fc.low_water[0] = fc_conf->low_water;
4536 hw->fc.send_xon = fc_conf->send_xon;
4537 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4539 err = ixgbe_fc_enable(hw);
4541 /* Not negotiated is not an error case */
4542 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4544 /* check if we want to forward MAC frames - driver doesn't have native
4545 * capability to do that, so we'll write the registers ourselves */
4547 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4549 /* set or clear MFLCN.PMCF bit depending on configuration */
4550 if (fc_conf->mac_ctrl_frame_fwd != 0)
4551 mflcn |= IXGBE_MFLCN_PMCF;
4553 mflcn &= ~IXGBE_MFLCN_PMCF;
4555 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4556 IXGBE_WRITE_FLUSH(hw);
4561 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4566 * ixgbe_pfc_enable_generic - Enable flow control
4567 * @hw: pointer to hardware structure
4568 * @tc_num: traffic class number
4569 * Enable flow control according to the current settings.
4572 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4575 uint32_t mflcn_reg, fccfg_reg;
4577 uint32_t fcrtl, fcrth;
4581 /* Validate the water mark configuration */
4582 if (!hw->fc.pause_time) {
4583 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4587 /* Low water mark of zero causes XOFF floods */
4588 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4589 /* High/Low water can not be 0 */
4590 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4591 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4592 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4596 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4597 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4598 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4602 /* Negotiate the fc mode to use */
4603 ixgbe_fc_autoneg(hw);
4605 /* Disable any previous flow control settings */
4606 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4607 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4609 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4610 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4612 switch (hw->fc.current_mode) {
4615 * If the count of enabled RX Priority Flow control >1,
4616 * and the TX pause can not be disabled
4619 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4620 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4621 if (reg & IXGBE_FCRTH_FCEN)
4625 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4627 case ixgbe_fc_rx_pause:
4629 * Rx Flow control is enabled and Tx Flow control is
4630 * disabled by software override. Since there really
4631 * isn't a way to advertise that we are capable of RX
4632 * Pause ONLY, we will advertise that we support both
4633 * symmetric and asymmetric Rx PAUSE. Later, we will
4634 * disable the adapter's ability to send PAUSE frames.
4636 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4638 * If the count of enabled RX Priority Flow control >1,
4639 * and the TX pause can not be disabled
4642 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4643 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4644 if (reg & IXGBE_FCRTH_FCEN)
4648 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4650 case ixgbe_fc_tx_pause:
4652 * Tx Flow control is enabled, and Rx Flow control is
4653 * disabled by software override.
4655 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4658 /* Flow control (both Rx and Tx) is enabled by SW override. */
4659 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4660 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4663 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4664 ret_val = IXGBE_ERR_CONFIG;
4668 /* Set 802.3x based flow control settings. */
4669 mflcn_reg |= IXGBE_MFLCN_DPF;
4670 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4671 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4673 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4674 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4675 hw->fc.high_water[tc_num]) {
4676 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4677 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4678 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4680 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4682 * In order to prevent Tx hangs when the internal Tx
4683 * switch is enabled we must set the high water mark
4684 * to the maximum FCRTH value. This allows the Tx
4685 * switch to function even under heavy Rx workloads.
4687 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4689 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4691 /* Configure pause time (2 TCs per register) */
4692 reg = hw->fc.pause_time * 0x00010001;
4693 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4694 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4696 /* Configure flow control refresh threshold value */
4697 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4704 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4706 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4707 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4709 if (hw->mac.type != ixgbe_mac_82598EB) {
4710 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4716 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4719 uint32_t rx_buf_size;
4720 uint32_t max_high_water;
4722 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4723 struct ixgbe_hw *hw =
4724 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4725 struct ixgbe_dcb_config *dcb_config =
4726 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4728 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4735 PMD_INIT_FUNC_TRACE();
4737 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4738 tc_num = map[pfc_conf->priority];
4739 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4740 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4742 * At least reserve one Ethernet frame for watermark
4743 * high_water/low_water in kilo bytes for ixgbe
4745 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4746 if ((pfc_conf->fc.high_water > max_high_water) ||
4747 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4748 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4749 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4753 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4754 hw->fc.pause_time = pfc_conf->fc.pause_time;
4755 hw->fc.send_xon = pfc_conf->fc.send_xon;
4756 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4757 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4759 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4761 /* Not negotiated is not an error case */
4762 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4765 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4770 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4771 struct rte_eth_rss_reta_entry64 *reta_conf,
4774 uint16_t i, sp_reta_size;
4777 uint16_t idx, shift;
4778 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4781 PMD_INIT_FUNC_TRACE();
4783 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4784 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4789 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4790 if (reta_size != sp_reta_size) {
4791 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4792 "(%d) doesn't match the number hardware can supported "
4793 "(%d)", reta_size, sp_reta_size);
4797 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4798 idx = i / RTE_RETA_GROUP_SIZE;
4799 shift = i % RTE_RETA_GROUP_SIZE;
4800 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4804 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4805 if (mask == IXGBE_4_BIT_MASK)
4808 r = IXGBE_READ_REG(hw, reta_reg);
4809 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4810 if (mask & (0x1 << j))
4811 reta |= reta_conf[idx].reta[shift + j] <<
4814 reta |= r & (IXGBE_8_BIT_MASK <<
4817 IXGBE_WRITE_REG(hw, reta_reg, reta);
4824 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4825 struct rte_eth_rss_reta_entry64 *reta_conf,
4828 uint16_t i, sp_reta_size;
4831 uint16_t idx, shift;
4832 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4835 PMD_INIT_FUNC_TRACE();
4836 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4837 if (reta_size != sp_reta_size) {
4838 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4839 "(%d) doesn't match the number hardware can supported "
4840 "(%d)", reta_size, sp_reta_size);
4844 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4845 idx = i / RTE_RETA_GROUP_SIZE;
4846 shift = i % RTE_RETA_GROUP_SIZE;
4847 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4852 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4853 reta = IXGBE_READ_REG(hw, reta_reg);
4854 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4855 if (mask & (0x1 << j))
4856 reta_conf[idx].reta[shift + j] =
4857 ((reta >> (CHAR_BIT * j)) &
4866 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4867 uint32_t index, uint32_t pool)
4869 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4870 uint32_t enable_addr = 1;
4872 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4877 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4879 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4881 ixgbe_clear_rar(hw, index);
4885 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4887 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4889 ixgbe_remove_rar(dev, 0);
4890 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4896 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4898 if (strcmp(dev->device->driver->name, drv->driver.name))
4905 is_ixgbe_supported(struct rte_eth_dev *dev)
4907 return is_device_supported(dev, &rte_ixgbe_pmd);
4911 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4915 struct ixgbe_hw *hw;
4916 struct rte_eth_dev_info dev_info;
4917 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4918 struct rte_eth_dev_data *dev_data = dev->data;
4920 ixgbe_dev_info_get(dev, &dev_info);
4922 /* check that mtu is within the allowed range */
4923 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4926 /* If device is started, refuse mtu that requires the support of
4927 * scattered packets when this feature has not been enabled before.
4929 if (dev_data->dev_started && !dev_data->scattered_rx &&
4930 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4931 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4932 PMD_INIT_LOG(ERR, "Stop port first.");
4936 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4937 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4939 /* switch to jumbo mode if needed */
4940 if (frame_size > ETHER_MAX_LEN) {
4941 dev->data->dev_conf.rxmode.offloads |=
4942 DEV_RX_OFFLOAD_JUMBO_FRAME;
4943 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4945 dev->data->dev_conf.rxmode.offloads &=
4946 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4947 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4949 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4951 /* update max frame size */
4952 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4954 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4955 maxfrs &= 0x0000FFFF;
4956 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4957 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4963 * Virtual Function operations
4966 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4968 struct ixgbe_interrupt *intr =
4969 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4970 struct ixgbe_hw *hw =
4971 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4973 PMD_INIT_FUNC_TRACE();
4975 /* Clear interrupt mask to stop from interrupts being generated */
4976 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4978 IXGBE_WRITE_FLUSH(hw);
4980 /* Clear mask value. */
4985 ixgbevf_intr_enable(struct rte_eth_dev *dev)
4987 struct ixgbe_interrupt *intr =
4988 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4989 struct ixgbe_hw *hw =
4990 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992 PMD_INIT_FUNC_TRACE();
4994 /* VF enable interrupt autoclean */
4995 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4996 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4997 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4999 IXGBE_WRITE_FLUSH(hw);
5001 /* Save IXGBE_VTEIMS value to mask. */
5002 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5006 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5008 struct rte_eth_conf *conf = &dev->data->dev_conf;
5009 struct ixgbe_adapter *adapter =
5010 (struct ixgbe_adapter *)dev->data->dev_private;
5012 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5013 dev->data->port_id);
5016 * VF has no ability to enable/disable HW CRC
5017 * Keep the persistent behavior the same as Host PF
5019 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5020 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5021 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5022 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5025 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5026 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5027 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5032 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5033 * allocation or vector Rx preconditions we will reset it.
5035 adapter->rx_bulk_alloc_allowed = true;
5036 adapter->rx_vec_allowed = true;
5042 ixgbevf_dev_start(struct rte_eth_dev *dev)
5044 struct ixgbe_hw *hw =
5045 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5046 uint32_t intr_vector = 0;
5047 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5048 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5052 PMD_INIT_FUNC_TRACE();
5054 err = hw->mac.ops.reset_hw(hw);
5056 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5059 hw->mac.get_link_status = true;
5061 /* negotiate mailbox API version to use with the PF. */
5062 ixgbevf_negotiate_api(hw);
5064 ixgbevf_dev_tx_init(dev);
5066 /* This can fail when allocating mbufs for descriptor rings */
5067 err = ixgbevf_dev_rx_init(dev);
5069 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5070 ixgbe_dev_clear_queues(dev);
5075 ixgbevf_set_vfta_all(dev, 1);
5078 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5079 ETH_VLAN_EXTEND_MASK;
5080 err = ixgbevf_vlan_offload_config(dev, mask);
5082 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5083 ixgbe_dev_clear_queues(dev);
5087 ixgbevf_dev_rxtx_start(dev);
5089 ixgbevf_dev_link_update(dev, 0);
5091 /* check and configure queue intr-vector mapping */
5092 if (rte_intr_cap_multiple(intr_handle) &&
5093 dev->data->dev_conf.intr_conf.rxq) {
5094 /* According to datasheet, only vector 0/1/2 can be used,
5095 * now only one vector is used for Rx queue
5098 if (rte_intr_efd_enable(intr_handle, intr_vector))
5102 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5103 intr_handle->intr_vec =
5104 rte_zmalloc("intr_vec",
5105 dev->data->nb_rx_queues * sizeof(int), 0);
5106 if (intr_handle->intr_vec == NULL) {
5107 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5108 " intr_vec", dev->data->nb_rx_queues);
5112 ixgbevf_configure_msix(dev);
5114 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5115 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5116 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5117 * is not cleared, it will fail when following rte_intr_enable( ) tries
5118 * to map Rx queue interrupt to other VFIO vectors.
5119 * So clear uio/vfio intr/evevnfd first to avoid failure.
5121 rte_intr_disable(intr_handle);
5123 rte_intr_enable(intr_handle);
5125 /* Re-enable interrupt for VF */
5126 ixgbevf_intr_enable(dev);
5132 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5134 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5135 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5136 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5138 PMD_INIT_FUNC_TRACE();
5140 ixgbevf_intr_disable(dev);
5142 hw->adapter_stopped = 1;
5143 ixgbe_stop_adapter(hw);
5146 * Clear what we set, but we still keep shadow_vfta to
5147 * restore after device starts
5149 ixgbevf_set_vfta_all(dev, 0);
5151 /* Clear stored conf */
5152 dev->data->scattered_rx = 0;
5154 ixgbe_dev_clear_queues(dev);
5156 /* Clean datapath event and queue/vec mapping */
5157 rte_intr_efd_disable(intr_handle);
5158 if (intr_handle->intr_vec != NULL) {
5159 rte_free(intr_handle->intr_vec);
5160 intr_handle->intr_vec = NULL;
5165 ixgbevf_dev_close(struct rte_eth_dev *dev)
5167 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5169 PMD_INIT_FUNC_TRACE();
5173 ixgbevf_dev_stop(dev);
5175 ixgbe_dev_free_queues(dev);
5178 * Remove the VF MAC address ro ensure
5179 * that the VF traffic goes to the PF
5180 * after stop, close and detach of the VF
5182 ixgbevf_remove_mac_addr(dev, 0);
5189 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5193 ret = eth_ixgbevf_dev_uninit(dev);
5197 ret = eth_ixgbevf_dev_init(dev);
5202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5204 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205 struct ixgbe_vfta *shadow_vfta =
5206 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5207 int i = 0, j = 0, vfta = 0, mask = 1;
5209 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5210 vfta = shadow_vfta->vfta[i];
5213 for (j = 0; j < 32; j++) {
5215 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5225 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5227 struct ixgbe_hw *hw =
5228 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5229 struct ixgbe_vfta *shadow_vfta =
5230 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5231 uint32_t vid_idx = 0;
5232 uint32_t vid_bit = 0;
5235 PMD_INIT_FUNC_TRACE();
5237 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5238 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5240 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5243 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5244 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5246 /* Save what we set and retore it after device reset */
5248 shadow_vfta->vfta[vid_idx] |= vid_bit;
5250 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5256 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5258 struct ixgbe_hw *hw =
5259 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5262 PMD_INIT_FUNC_TRACE();
5264 if (queue >= hw->mac.max_rx_queues)
5267 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5269 ctrl |= IXGBE_RXDCTL_VME;
5271 ctrl &= ~IXGBE_RXDCTL_VME;
5272 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5274 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5278 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5280 struct ixgbe_rx_queue *rxq;
5284 /* VF function only support hw strip feature, others are not support */
5285 if (mask & ETH_VLAN_STRIP_MASK) {
5286 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5287 rxq = dev->data->rx_queues[i];
5288 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5289 ixgbevf_vlan_strip_queue_set(dev, i, on);
5297 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5299 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5301 ixgbevf_vlan_offload_config(dev, mask);
5307 ixgbe_vt_check(struct ixgbe_hw *hw)
5311 /* if Virtualization Technology is enabled */
5312 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5313 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5314 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5322 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5324 uint32_t vector = 0;
5326 switch (hw->mac.mc_filter_type) {
5327 case 0: /* use bits [47:36] of the address */
5328 vector = ((uc_addr->addr_bytes[4] >> 4) |
5329 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5331 case 1: /* use bits [46:35] of the address */
5332 vector = ((uc_addr->addr_bytes[4] >> 3) |
5333 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5335 case 2: /* use bits [45:34] of the address */
5336 vector = ((uc_addr->addr_bytes[4] >> 2) |
5337 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5339 case 3: /* use bits [43:32] of the address */
5340 vector = ((uc_addr->addr_bytes[4]) |
5341 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5343 default: /* Invalid mc_filter_type */
5347 /* vector can only be 12-bits or boundary will be exceeded */
5353 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5361 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5362 const uint32_t ixgbe_uta_bit_shift = 5;
5363 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5364 const uint32_t bit1 = 0x1;
5366 struct ixgbe_hw *hw =
5367 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5368 struct ixgbe_uta_info *uta_info =
5369 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5371 /* The UTA table only exists on 82599 hardware and newer */
5372 if (hw->mac.type < ixgbe_mac_82599EB)
5375 vector = ixgbe_uta_vector(hw, mac_addr);
5376 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5377 uta_shift = vector & ixgbe_uta_bit_mask;
5379 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5383 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5385 uta_info->uta_in_use++;
5386 reg_val |= (bit1 << uta_shift);
5387 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5389 uta_info->uta_in_use--;
5390 reg_val &= ~(bit1 << uta_shift);
5391 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5394 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5396 if (uta_info->uta_in_use > 0)
5397 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5398 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5400 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5406 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5409 struct ixgbe_hw *hw =
5410 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5411 struct ixgbe_uta_info *uta_info =
5412 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5414 /* The UTA table only exists on 82599 hardware and newer */
5415 if (hw->mac.type < ixgbe_mac_82599EB)
5419 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5420 uta_info->uta_shadow[i] = ~0;
5421 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5424 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5425 uta_info->uta_shadow[i] = 0;
5426 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5434 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5436 uint32_t new_val = orig_val;
5438 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5439 new_val |= IXGBE_VMOLR_AUPE;
5440 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5441 new_val |= IXGBE_VMOLR_ROMPE;
5442 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5443 new_val |= IXGBE_VMOLR_ROPE;
5444 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5445 new_val |= IXGBE_VMOLR_BAM;
5446 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5447 new_val |= IXGBE_VMOLR_MPE;
5452 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5453 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5454 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5455 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5456 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5457 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5458 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5461 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5462 struct rte_eth_mirror_conf *mirror_conf,
5463 uint8_t rule_id, uint8_t on)
5465 uint32_t mr_ctl, vlvf;
5466 uint32_t mp_lsb = 0;
5467 uint32_t mv_msb = 0;
5468 uint32_t mv_lsb = 0;
5469 uint32_t mp_msb = 0;
5472 uint64_t vlan_mask = 0;
5474 const uint8_t pool_mask_offset = 32;
5475 const uint8_t vlan_mask_offset = 32;
5476 const uint8_t dst_pool_offset = 8;
5477 const uint8_t rule_mr_offset = 4;
5478 const uint8_t mirror_rule_mask = 0x0F;
5480 struct ixgbe_mirror_info *mr_info =
5481 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5482 struct ixgbe_hw *hw =
5483 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5484 uint8_t mirror_type = 0;
5486 if (ixgbe_vt_check(hw) < 0)
5489 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5492 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5493 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5494 mirror_conf->rule_type);
5498 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5499 mirror_type |= IXGBE_MRCTL_VLME;
5500 /* Check if vlan id is valid and find conresponding VLAN ID
5503 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5504 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5505 /* search vlan id related pool vlan filter
5508 reg_index = ixgbe_find_vlvf_slot(
5510 mirror_conf->vlan.vlan_id[i],
5514 vlvf = IXGBE_READ_REG(hw,
5515 IXGBE_VLVF(reg_index));
5516 if ((vlvf & IXGBE_VLVF_VIEN) &&
5517 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5518 mirror_conf->vlan.vlan_id[i]))
5519 vlan_mask |= (1ULL << reg_index);
5526 mv_lsb = vlan_mask & 0xFFFFFFFF;
5527 mv_msb = vlan_mask >> vlan_mask_offset;
5529 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5530 mirror_conf->vlan.vlan_mask;
5531 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5532 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5533 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5534 mirror_conf->vlan.vlan_id[i];
5539 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5540 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5541 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5546 * if enable pool mirror, write related pool mask register,if disable
5547 * pool mirror, clear PFMRVM register
5549 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5550 mirror_type |= IXGBE_MRCTL_VPME;
5552 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5553 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5554 mr_info->mr_conf[rule_id].pool_mask =
5555 mirror_conf->pool_mask;
5560 mr_info->mr_conf[rule_id].pool_mask = 0;
5563 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5564 mirror_type |= IXGBE_MRCTL_UPME;
5565 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5566 mirror_type |= IXGBE_MRCTL_DPME;
5568 /* read mirror control register and recalculate it */
5569 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5572 mr_ctl |= mirror_type;
5573 mr_ctl &= mirror_rule_mask;
5574 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5576 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5579 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5580 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5582 /* write mirrror control register */
5583 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5585 /* write pool mirrror control register */
5586 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5587 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5588 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5591 /* write VLAN mirrror control register */
5592 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5593 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5594 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5602 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5605 uint32_t lsb_val = 0;
5606 uint32_t msb_val = 0;
5607 const uint8_t rule_mr_offset = 4;
5609 struct ixgbe_hw *hw =
5610 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5611 struct ixgbe_mirror_info *mr_info =
5612 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5614 if (ixgbe_vt_check(hw) < 0)
5617 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5620 memset(&mr_info->mr_conf[rule_id], 0,
5621 sizeof(struct rte_eth_mirror_conf));
5623 /* clear PFVMCTL register */
5624 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5626 /* clear pool mask register */
5627 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5628 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5630 /* clear vlan mask register */
5631 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5632 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5638 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5640 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5641 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5642 struct ixgbe_interrupt *intr =
5643 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5644 struct ixgbe_hw *hw =
5645 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5646 uint32_t vec = IXGBE_MISC_VEC_ID;
5648 if (rte_intr_allow_others(intr_handle))
5649 vec = IXGBE_RX_VEC_START;
5650 intr->mask |= (1 << vec);
5651 RTE_SET_USED(queue_id);
5652 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5654 rte_intr_enable(intr_handle);
5660 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5662 struct ixgbe_interrupt *intr =
5663 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5664 struct ixgbe_hw *hw =
5665 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5666 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5667 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5668 uint32_t vec = IXGBE_MISC_VEC_ID;
5670 if (rte_intr_allow_others(intr_handle))
5671 vec = IXGBE_RX_VEC_START;
5672 intr->mask &= ~(1 << vec);
5673 RTE_SET_USED(queue_id);
5674 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5680 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5682 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5683 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5685 struct ixgbe_hw *hw =
5686 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5687 struct ixgbe_interrupt *intr =
5688 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5690 if (queue_id < 16) {
5691 ixgbe_disable_intr(hw);
5692 intr->mask |= (1 << queue_id);
5693 ixgbe_enable_intr(dev);
5694 } else if (queue_id < 32) {
5695 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5696 mask &= (1 << queue_id);
5697 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5698 } else if (queue_id < 64) {
5699 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5700 mask &= (1 << (queue_id - 32));
5701 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5703 rte_intr_enable(intr_handle);
5709 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5712 struct ixgbe_hw *hw =
5713 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5714 struct ixgbe_interrupt *intr =
5715 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5717 if (queue_id < 16) {
5718 ixgbe_disable_intr(hw);
5719 intr->mask &= ~(1 << queue_id);
5720 ixgbe_enable_intr(dev);
5721 } else if (queue_id < 32) {
5722 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5723 mask &= ~(1 << queue_id);
5724 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5725 } else if (queue_id < 64) {
5726 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5727 mask &= ~(1 << (queue_id - 32));
5728 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5735 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5736 uint8_t queue, uint8_t msix_vector)
5740 if (direction == -1) {
5742 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5743 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5746 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5748 /* rx or tx cause */
5749 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5750 idx = ((16 * (queue & 1)) + (8 * direction));
5751 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5752 tmp &= ~(0xFF << idx);
5753 tmp |= (msix_vector << idx);
5754 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5759 * set the IVAR registers, mapping interrupt causes to vectors
5761 * pointer to ixgbe_hw struct
5763 * 0 for Rx, 1 for Tx, -1 for other causes
5765 * queue to map the corresponding interrupt to
5767 * the vector to map to the corresponding queue
5770 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5771 uint8_t queue, uint8_t msix_vector)
5775 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5776 if (hw->mac.type == ixgbe_mac_82598EB) {
5777 if (direction == -1)
5779 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5780 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5781 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5782 tmp |= (msix_vector << (8 * (queue & 0x3)));
5783 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5784 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5785 (hw->mac.type == ixgbe_mac_X540) ||
5786 (hw->mac.type == ixgbe_mac_X550)) {
5787 if (direction == -1) {
5789 idx = ((queue & 1) * 8);
5790 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5791 tmp &= ~(0xFF << idx);
5792 tmp |= (msix_vector << idx);
5793 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5795 /* rx or tx causes */
5796 idx = ((16 * (queue & 1)) + (8 * direction));
5797 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5798 tmp &= ~(0xFF << idx);
5799 tmp |= (msix_vector << idx);
5800 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5806 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5808 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5809 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5810 struct ixgbe_hw *hw =
5811 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5813 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5814 uint32_t base = IXGBE_MISC_VEC_ID;
5816 /* Configure VF other cause ivar */
5817 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5819 /* won't configure msix register if no mapping is done
5820 * between intr vector and event fd.
5822 if (!rte_intr_dp_is_en(intr_handle))
5825 if (rte_intr_allow_others(intr_handle)) {
5826 base = IXGBE_RX_VEC_START;
5827 vector_idx = IXGBE_RX_VEC_START;
5830 /* Configure all RX queues of VF */
5831 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5832 /* Force all queue use vector 0,
5833 * as IXGBE_VF_MAXMSIVECOTR = 1
5835 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5836 intr_handle->intr_vec[q_idx] = vector_idx;
5837 if (vector_idx < base + intr_handle->nb_efd - 1)
5841 /* As RX queue setting above show, all queues use the vector 0.
5842 * Set only the ITR value of IXGBE_MISC_VEC_ID.
5844 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5845 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5846 | IXGBE_EITR_CNT_WDIS);
5850 * Sets up the hardware to properly generate MSI-X interrupts
5852 * board private structure
5855 ixgbe_configure_msix(struct rte_eth_dev *dev)
5857 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5858 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5859 struct ixgbe_hw *hw =
5860 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5861 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5862 uint32_t vec = IXGBE_MISC_VEC_ID;
5866 /* won't configure msix register if no mapping is done
5867 * between intr vector and event fd
5868 * but if misx has been enabled already, need to configure
5869 * auto clean, auto mask and throttling.
5871 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5872 if (!rte_intr_dp_is_en(intr_handle) &&
5873 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5876 if (rte_intr_allow_others(intr_handle))
5877 vec = base = IXGBE_RX_VEC_START;
5879 /* setup GPIE for MSI-x mode */
5880 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5881 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5882 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5883 /* auto clearing and auto setting corresponding bits in EIMS
5884 * when MSI-X interrupt is triggered
5886 if (hw->mac.type == ixgbe_mac_82598EB) {
5887 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5889 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5890 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5892 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5894 /* Populate the IVAR table and set the ITR values to the
5895 * corresponding register.
5897 if (rte_intr_dp_is_en(intr_handle)) {
5898 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5900 /* by default, 1:1 mapping */
5901 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5902 intr_handle->intr_vec[queue_id] = vec;
5903 if (vec < base + intr_handle->nb_efd - 1)
5907 switch (hw->mac.type) {
5908 case ixgbe_mac_82598EB:
5909 ixgbe_set_ivar_map(hw, -1,
5910 IXGBE_IVAR_OTHER_CAUSES_INDEX,
5913 case ixgbe_mac_82599EB:
5914 case ixgbe_mac_X540:
5915 case ixgbe_mac_X550:
5916 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5922 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5923 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5924 | IXGBE_EITR_CNT_WDIS);
5926 /* set up to autoclear timer, and the vectors */
5927 mask = IXGBE_EIMS_ENABLE_MASK;
5928 mask &= ~(IXGBE_EIMS_OTHER |
5929 IXGBE_EIMS_MAILBOX |
5932 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5936 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5937 uint16_t queue_idx, uint16_t tx_rate)
5939 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5940 struct rte_eth_rxmode *rxmode;
5941 uint32_t rf_dec, rf_int;
5943 uint16_t link_speed = dev->data->dev_link.link_speed;
5945 if (queue_idx >= hw->mac.max_tx_queues)
5949 /* Calculate the rate factor values to set */
5950 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5951 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5952 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5954 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5955 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5956 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5957 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5962 rxmode = &dev->data->dev_conf.rxmode;
5964 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5965 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5968 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5969 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5970 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5971 IXGBE_MMW_SIZE_JUMBO_FRAME);
5973 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5974 IXGBE_MMW_SIZE_DEFAULT);
5976 /* Set RTTBCNRC of queue X */
5977 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5978 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5979 IXGBE_WRITE_FLUSH(hw);
5985 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5986 __attribute__((unused)) uint32_t index,
5987 __attribute__((unused)) uint32_t pool)
5989 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5993 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5994 * operation. Trap this case to avoid exhausting the [very limited]
5995 * set of PF resources used to store VF MAC addresses.
5997 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5999 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6001 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6002 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6003 mac_addr->addr_bytes[0],
6004 mac_addr->addr_bytes[1],
6005 mac_addr->addr_bytes[2],
6006 mac_addr->addr_bytes[3],
6007 mac_addr->addr_bytes[4],
6008 mac_addr->addr_bytes[5],
6014 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6016 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6017 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6018 struct ether_addr *mac_addr;
6023 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6024 * not support the deletion of a given MAC address.
6025 * Instead, it imposes to delete all MAC addresses, then to add again
6026 * all MAC addresses with the exception of the one to be deleted.
6028 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6031 * Add again all MAC addresses, with the exception of the deleted one
6032 * and of the permanent MAC address.
6034 for (i = 0, mac_addr = dev->data->mac_addrs;
6035 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6036 /* Skip the deleted MAC address */
6039 /* Skip NULL MAC addresses */
6040 if (is_zero_ether_addr(mac_addr))
6042 /* Skip the permanent MAC address */
6043 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6045 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6048 "Adding again MAC address "
6049 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6051 mac_addr->addr_bytes[0],
6052 mac_addr->addr_bytes[1],
6053 mac_addr->addr_bytes[2],
6054 mac_addr->addr_bytes[3],
6055 mac_addr->addr_bytes[4],
6056 mac_addr->addr_bytes[5],
6062 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6064 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6066 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6072 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6073 struct rte_eth_syn_filter *filter,
6076 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6077 struct ixgbe_filter_info *filter_info =
6078 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6082 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6085 syn_info = filter_info->syn_info;
6088 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6090 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6091 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6093 if (filter->hig_pri)
6094 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6096 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6098 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6099 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6101 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6104 filter_info->syn_info = synqf;
6105 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6106 IXGBE_WRITE_FLUSH(hw);
6111 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6112 struct rte_eth_syn_filter *filter)
6114 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6115 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6117 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6118 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6119 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6126 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6127 enum rte_filter_op filter_op,
6130 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6133 MAC_TYPE_FILTER_SUP(hw->mac.type);
6135 if (filter_op == RTE_ETH_FILTER_NOP)
6139 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6144 switch (filter_op) {
6145 case RTE_ETH_FILTER_ADD:
6146 ret = ixgbe_syn_filter_set(dev,
6147 (struct rte_eth_syn_filter *)arg,
6150 case RTE_ETH_FILTER_DELETE:
6151 ret = ixgbe_syn_filter_set(dev,
6152 (struct rte_eth_syn_filter *)arg,
6155 case RTE_ETH_FILTER_GET:
6156 ret = ixgbe_syn_filter_get(dev,
6157 (struct rte_eth_syn_filter *)arg);
6160 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6169 static inline enum ixgbe_5tuple_protocol
6170 convert_protocol_type(uint8_t protocol_value)
6172 if (protocol_value == IPPROTO_TCP)
6173 return IXGBE_FILTER_PROTOCOL_TCP;
6174 else if (protocol_value == IPPROTO_UDP)
6175 return IXGBE_FILTER_PROTOCOL_UDP;
6176 else if (protocol_value == IPPROTO_SCTP)
6177 return IXGBE_FILTER_PROTOCOL_SCTP;
6179 return IXGBE_FILTER_PROTOCOL_NONE;
6182 /* inject a 5-tuple filter to HW */
6184 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6185 struct ixgbe_5tuple_filter *filter)
6187 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6189 uint32_t ftqf, sdpqf;
6190 uint32_t l34timir = 0;
6191 uint8_t mask = 0xff;
6195 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6196 IXGBE_SDPQF_DSTPORT_SHIFT);
6197 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6199 ftqf = (uint32_t)(filter->filter_info.proto &
6200 IXGBE_FTQF_PROTOCOL_MASK);
6201 ftqf |= (uint32_t)((filter->filter_info.priority &
6202 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6203 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6204 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6205 if (filter->filter_info.dst_ip_mask == 0)
6206 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6207 if (filter->filter_info.src_port_mask == 0)
6208 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6209 if (filter->filter_info.dst_port_mask == 0)
6210 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6211 if (filter->filter_info.proto_mask == 0)
6212 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6213 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6214 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6215 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6217 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6218 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6219 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6220 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6222 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6223 l34timir |= (uint32_t)(filter->queue <<
6224 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6225 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6229 * add a 5tuple filter
6232 * dev: Pointer to struct rte_eth_dev.
6233 * index: the index the filter allocates.
6234 * filter: ponter to the filter that will be added.
6235 * rx_queue: the queue id the filter assigned to.
6238 * - On success, zero.
6239 * - On failure, a negative value.
6242 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6243 struct ixgbe_5tuple_filter *filter)
6245 struct ixgbe_filter_info *filter_info =
6246 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6250 * look for an unused 5tuple filter index,
6251 * and insert the filter to list.
6253 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6254 idx = i / (sizeof(uint32_t) * NBBY);
6255 shift = i % (sizeof(uint32_t) * NBBY);
6256 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6257 filter_info->fivetuple_mask[idx] |= 1 << shift;
6259 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6265 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6266 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6270 ixgbe_inject_5tuple_filter(dev, filter);
6276 * remove a 5tuple filter
6279 * dev: Pointer to struct rte_eth_dev.
6280 * filter: the pointer of the filter will be removed.
6283 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6284 struct ixgbe_5tuple_filter *filter)
6286 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6287 struct ixgbe_filter_info *filter_info =
6288 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6289 uint16_t index = filter->index;
6291 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6292 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6293 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6296 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6297 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6298 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6299 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6300 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6304 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6306 struct ixgbe_hw *hw;
6307 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6308 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6310 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6312 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6315 /* refuse mtu that requires the support of scattered packets when this
6316 * feature has not been enabled before.
6318 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6319 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6320 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6324 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6325 * request of the version 2.0 of the mailbox API.
6326 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6327 * of the mailbox API.
6328 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6329 * prior to 3.11.33 which contains the following change:
6330 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6332 ixgbevf_rlpml_set_vf(hw, max_frame);
6334 /* update max frame size */
6335 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6339 static inline struct ixgbe_5tuple_filter *
6340 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6341 struct ixgbe_5tuple_filter_info *key)
6343 struct ixgbe_5tuple_filter *it;
6345 TAILQ_FOREACH(it, filter_list, entries) {
6346 if (memcmp(key, &it->filter_info,
6347 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6354 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6356 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6357 struct ixgbe_5tuple_filter_info *filter_info)
6359 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6360 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6361 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6364 switch (filter->dst_ip_mask) {
6366 filter_info->dst_ip_mask = 0;
6367 filter_info->dst_ip = filter->dst_ip;
6370 filter_info->dst_ip_mask = 1;
6373 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6377 switch (filter->src_ip_mask) {
6379 filter_info->src_ip_mask = 0;
6380 filter_info->src_ip = filter->src_ip;
6383 filter_info->src_ip_mask = 1;
6386 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6390 switch (filter->dst_port_mask) {
6392 filter_info->dst_port_mask = 0;
6393 filter_info->dst_port = filter->dst_port;
6396 filter_info->dst_port_mask = 1;
6399 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6403 switch (filter->src_port_mask) {
6405 filter_info->src_port_mask = 0;
6406 filter_info->src_port = filter->src_port;
6409 filter_info->src_port_mask = 1;
6412 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6416 switch (filter->proto_mask) {
6418 filter_info->proto_mask = 0;
6419 filter_info->proto =
6420 convert_protocol_type(filter->proto);
6423 filter_info->proto_mask = 1;
6426 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6430 filter_info->priority = (uint8_t)filter->priority;
6435 * add or delete a ntuple filter
6438 * dev: Pointer to struct rte_eth_dev.
6439 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6440 * add: if true, add filter, if false, remove filter
6443 * - On success, zero.
6444 * - On failure, a negative value.
6447 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6448 struct rte_eth_ntuple_filter *ntuple_filter,
6451 struct ixgbe_filter_info *filter_info =
6452 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6453 struct ixgbe_5tuple_filter_info filter_5tuple;
6454 struct ixgbe_5tuple_filter *filter;
6457 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6458 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6462 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6463 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6467 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6469 if (filter != NULL && add) {
6470 PMD_DRV_LOG(ERR, "filter exists.");
6473 if (filter == NULL && !add) {
6474 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6479 filter = rte_zmalloc("ixgbe_5tuple_filter",
6480 sizeof(struct ixgbe_5tuple_filter), 0);
6483 rte_memcpy(&filter->filter_info,
6485 sizeof(struct ixgbe_5tuple_filter_info));
6486 filter->queue = ntuple_filter->queue;
6487 ret = ixgbe_add_5tuple_filter(dev, filter);
6493 ixgbe_remove_5tuple_filter(dev, filter);
6499 * get a ntuple filter
6502 * dev: Pointer to struct rte_eth_dev.
6503 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6506 * - On success, zero.
6507 * - On failure, a negative value.
6510 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6511 struct rte_eth_ntuple_filter *ntuple_filter)
6513 struct ixgbe_filter_info *filter_info =
6514 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6515 struct ixgbe_5tuple_filter_info filter_5tuple;
6516 struct ixgbe_5tuple_filter *filter;
6519 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6520 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6524 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6525 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6529 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6531 if (filter == NULL) {
6532 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6535 ntuple_filter->queue = filter->queue;
6540 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6541 * @dev: pointer to rte_eth_dev structure
6542 * @filter_op:operation will be taken.
6543 * @arg: a pointer to specific structure corresponding to the filter_op
6546 * - On success, zero.
6547 * - On failure, a negative value.
6550 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6551 enum rte_filter_op filter_op,
6554 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6557 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6559 if (filter_op == RTE_ETH_FILTER_NOP)
6563 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6568 switch (filter_op) {
6569 case RTE_ETH_FILTER_ADD:
6570 ret = ixgbe_add_del_ntuple_filter(dev,
6571 (struct rte_eth_ntuple_filter *)arg,
6574 case RTE_ETH_FILTER_DELETE:
6575 ret = ixgbe_add_del_ntuple_filter(dev,
6576 (struct rte_eth_ntuple_filter *)arg,
6579 case RTE_ETH_FILTER_GET:
6580 ret = ixgbe_get_ntuple_filter(dev,
6581 (struct rte_eth_ntuple_filter *)arg);
6584 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6592 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6593 struct rte_eth_ethertype_filter *filter,
6596 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6597 struct ixgbe_filter_info *filter_info =
6598 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6602 struct ixgbe_ethertype_filter ethertype_filter;
6604 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6607 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6608 filter->ether_type == ETHER_TYPE_IPv6) {
6609 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6610 " ethertype filter.", filter->ether_type);
6614 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6615 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6618 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6619 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6623 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6624 if (ret >= 0 && add) {
6625 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6626 filter->ether_type);
6629 if (ret < 0 && !add) {
6630 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6631 filter->ether_type);
6636 etqf = IXGBE_ETQF_FILTER_EN;
6637 etqf |= (uint32_t)filter->ether_type;
6638 etqs |= (uint32_t)((filter->queue <<
6639 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6640 IXGBE_ETQS_RX_QUEUE);
6641 etqs |= IXGBE_ETQS_QUEUE_EN;
6643 ethertype_filter.ethertype = filter->ether_type;
6644 ethertype_filter.etqf = etqf;
6645 ethertype_filter.etqs = etqs;
6646 ethertype_filter.conf = FALSE;
6647 ret = ixgbe_ethertype_filter_insert(filter_info,
6650 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6654 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6658 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6659 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6660 IXGBE_WRITE_FLUSH(hw);
6666 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6667 struct rte_eth_ethertype_filter *filter)
6669 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6670 struct ixgbe_filter_info *filter_info =
6671 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6672 uint32_t etqf, etqs;
6675 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6677 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6678 filter->ether_type);
6682 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6683 if (etqf & IXGBE_ETQF_FILTER_EN) {
6684 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6685 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6687 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6688 IXGBE_ETQS_RX_QUEUE_SHIFT;
6695 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6696 * @dev: pointer to rte_eth_dev structure
6697 * @filter_op:operation will be taken.
6698 * @arg: a pointer to specific structure corresponding to the filter_op
6701 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6702 enum rte_filter_op filter_op,
6705 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6708 MAC_TYPE_FILTER_SUP(hw->mac.type);
6710 if (filter_op == RTE_ETH_FILTER_NOP)
6714 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6719 switch (filter_op) {
6720 case RTE_ETH_FILTER_ADD:
6721 ret = ixgbe_add_del_ethertype_filter(dev,
6722 (struct rte_eth_ethertype_filter *)arg,
6725 case RTE_ETH_FILTER_DELETE:
6726 ret = ixgbe_add_del_ethertype_filter(dev,
6727 (struct rte_eth_ethertype_filter *)arg,
6730 case RTE_ETH_FILTER_GET:
6731 ret = ixgbe_get_ethertype_filter(dev,
6732 (struct rte_eth_ethertype_filter *)arg);
6735 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6743 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6744 enum rte_filter_type filter_type,
6745 enum rte_filter_op filter_op,
6750 switch (filter_type) {
6751 case RTE_ETH_FILTER_NTUPLE:
6752 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6754 case RTE_ETH_FILTER_ETHERTYPE:
6755 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6757 case RTE_ETH_FILTER_SYN:
6758 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6760 case RTE_ETH_FILTER_FDIR:
6761 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6763 case RTE_ETH_FILTER_L2_TUNNEL:
6764 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6766 case RTE_ETH_FILTER_GENERIC:
6767 if (filter_op != RTE_ETH_FILTER_GET)
6769 *(const void **)arg = &ixgbe_flow_ops;
6772 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6782 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6783 u8 **mc_addr_ptr, u32 *vmdq)
6788 mc_addr = *mc_addr_ptr;
6789 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6794 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6795 struct ether_addr *mc_addr_set,
6796 uint32_t nb_mc_addr)
6798 struct ixgbe_hw *hw;
6801 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6802 mc_addr_list = (u8 *)mc_addr_set;
6803 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6804 ixgbe_dev_addr_list_itr, TRUE);
6808 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6810 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6811 uint64_t systime_cycles;
6813 switch (hw->mac.type) {
6814 case ixgbe_mac_X550:
6815 case ixgbe_mac_X550EM_x:
6816 case ixgbe_mac_X550EM_a:
6817 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6818 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6819 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6823 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6824 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6828 return systime_cycles;
6832 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6834 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6835 uint64_t rx_tstamp_cycles;
6837 switch (hw->mac.type) {
6838 case ixgbe_mac_X550:
6839 case ixgbe_mac_X550EM_x:
6840 case ixgbe_mac_X550EM_a:
6841 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6842 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6843 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6847 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6848 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6849 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6853 return rx_tstamp_cycles;
6857 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6859 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6860 uint64_t tx_tstamp_cycles;
6862 switch (hw->mac.type) {
6863 case ixgbe_mac_X550:
6864 case ixgbe_mac_X550EM_x:
6865 case ixgbe_mac_X550EM_a:
6866 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6867 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6868 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6872 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6873 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6874 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6878 return tx_tstamp_cycles;
6882 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6884 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6885 struct ixgbe_adapter *adapter =
6886 (struct ixgbe_adapter *)dev->data->dev_private;
6887 struct rte_eth_link link;
6888 uint32_t incval = 0;
6891 /* Get current link speed. */
6892 ixgbe_dev_link_update(dev, 1);
6893 rte_eth_linkstatus_get(dev, &link);
6895 switch (link.link_speed) {
6896 case ETH_SPEED_NUM_100M:
6897 incval = IXGBE_INCVAL_100;
6898 shift = IXGBE_INCVAL_SHIFT_100;
6900 case ETH_SPEED_NUM_1G:
6901 incval = IXGBE_INCVAL_1GB;
6902 shift = IXGBE_INCVAL_SHIFT_1GB;
6904 case ETH_SPEED_NUM_10G:
6906 incval = IXGBE_INCVAL_10GB;
6907 shift = IXGBE_INCVAL_SHIFT_10GB;
6911 switch (hw->mac.type) {
6912 case ixgbe_mac_X550:
6913 case ixgbe_mac_X550EM_x:
6914 case ixgbe_mac_X550EM_a:
6915 /* Independent of link speed. */
6917 /* Cycles read will be interpreted as ns. */
6920 case ixgbe_mac_X540:
6921 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6923 case ixgbe_mac_82599EB:
6924 incval >>= IXGBE_INCVAL_SHIFT_82599;
6925 shift -= IXGBE_INCVAL_SHIFT_82599;
6926 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6927 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6930 /* Not supported. */
6934 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6935 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6936 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6938 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6939 adapter->systime_tc.cc_shift = shift;
6940 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6942 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6943 adapter->rx_tstamp_tc.cc_shift = shift;
6944 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6946 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6947 adapter->tx_tstamp_tc.cc_shift = shift;
6948 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6952 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6954 struct ixgbe_adapter *adapter =
6955 (struct ixgbe_adapter *)dev->data->dev_private;
6957 adapter->systime_tc.nsec += delta;
6958 adapter->rx_tstamp_tc.nsec += delta;
6959 adapter->tx_tstamp_tc.nsec += delta;
6965 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6968 struct ixgbe_adapter *adapter =
6969 (struct ixgbe_adapter *)dev->data->dev_private;
6971 ns = rte_timespec_to_ns(ts);
6972 /* Set the timecounters to a new value. */
6973 adapter->systime_tc.nsec = ns;
6974 adapter->rx_tstamp_tc.nsec = ns;
6975 adapter->tx_tstamp_tc.nsec = ns;
6981 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6983 uint64_t ns, systime_cycles;
6984 struct ixgbe_adapter *adapter =
6985 (struct ixgbe_adapter *)dev->data->dev_private;
6987 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6988 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6989 *ts = rte_ns_to_timespec(ns);
6995 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7001 /* Stop the timesync system time. */
7002 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7003 /* Reset the timesync system time value. */
7004 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7005 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7007 /* Enable system time for platforms where it isn't on by default. */
7008 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7009 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7010 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7012 ixgbe_start_timecounters(dev);
7014 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7015 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7017 IXGBE_ETQF_FILTER_EN |
7020 /* Enable timestamping of received PTP packets. */
7021 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7022 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7023 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7025 /* Enable timestamping of transmitted PTP packets. */
7026 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7027 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7028 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7030 IXGBE_WRITE_FLUSH(hw);
7036 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7038 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7041 /* Disable timestamping of transmitted PTP packets. */
7042 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7043 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7044 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7046 /* Disable timestamping of received PTP packets. */
7047 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7048 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7049 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7051 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7052 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7054 /* Stop incrementating the System Time registers. */
7055 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7061 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7062 struct timespec *timestamp,
7063 uint32_t flags __rte_unused)
7065 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7066 struct ixgbe_adapter *adapter =
7067 (struct ixgbe_adapter *)dev->data->dev_private;
7068 uint32_t tsync_rxctl;
7069 uint64_t rx_tstamp_cycles;
7072 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7073 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7076 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7077 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7078 *timestamp = rte_ns_to_timespec(ns);
7084 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7085 struct timespec *timestamp)
7087 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7088 struct ixgbe_adapter *adapter =
7089 (struct ixgbe_adapter *)dev->data->dev_private;
7090 uint32_t tsync_txctl;
7091 uint64_t tx_tstamp_cycles;
7094 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7095 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7098 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7099 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7100 *timestamp = rte_ns_to_timespec(ns);
7106 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7108 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7111 const struct reg_info *reg_group;
7112 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7113 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7115 while ((reg_group = reg_set[g_ind++]))
7116 count += ixgbe_regs_group_count(reg_group);
7122 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7126 const struct reg_info *reg_group;
7128 while ((reg_group = ixgbevf_regs[g_ind++]))
7129 count += ixgbe_regs_group_count(reg_group);
7135 ixgbe_get_regs(struct rte_eth_dev *dev,
7136 struct rte_dev_reg_info *regs)
7138 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7139 uint32_t *data = regs->data;
7142 const struct reg_info *reg_group;
7143 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7144 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7147 regs->length = ixgbe_get_reg_length(dev);
7148 regs->width = sizeof(uint32_t);
7152 /* Support only full register dump */
7153 if ((regs->length == 0) ||
7154 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7155 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7157 while ((reg_group = reg_set[g_ind++]))
7158 count += ixgbe_read_regs_group(dev, &data[count],
7167 ixgbevf_get_regs(struct rte_eth_dev *dev,
7168 struct rte_dev_reg_info *regs)
7170 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7171 uint32_t *data = regs->data;
7174 const struct reg_info *reg_group;
7177 regs->length = ixgbevf_get_reg_length(dev);
7178 regs->width = sizeof(uint32_t);
7182 /* Support only full register dump */
7183 if ((regs->length == 0) ||
7184 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7185 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7187 while ((reg_group = ixgbevf_regs[g_ind++]))
7188 count += ixgbe_read_regs_group(dev, &data[count],
7197 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7199 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7201 /* Return unit is byte count */
7202 return hw->eeprom.word_size * 2;
7206 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7207 struct rte_dev_eeprom_info *in_eeprom)
7209 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7210 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7211 uint16_t *data = in_eeprom->data;
7214 first = in_eeprom->offset >> 1;
7215 length = in_eeprom->length >> 1;
7216 if ((first > hw->eeprom.word_size) ||
7217 ((first + length) > hw->eeprom.word_size))
7220 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7222 return eeprom->ops.read_buffer(hw, first, length, data);
7226 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7227 struct rte_dev_eeprom_info *in_eeprom)
7229 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7230 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7231 uint16_t *data = in_eeprom->data;
7234 first = in_eeprom->offset >> 1;
7235 length = in_eeprom->length >> 1;
7236 if ((first > hw->eeprom.word_size) ||
7237 ((first + length) > hw->eeprom.word_size))
7240 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7242 return eeprom->ops.write_buffer(hw, first, length, data);
7246 ixgbe_get_module_info(struct rte_eth_dev *dev,
7247 struct rte_eth_dev_module_info *modinfo)
7249 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7251 uint8_t sff8472_rev, addr_mode;
7252 bool page_swap = false;
7254 /* Check whether we support SFF-8472 or not */
7255 status = hw->phy.ops.read_i2c_eeprom(hw,
7256 IXGBE_SFF_SFF_8472_COMP,
7261 /* addressing mode is not supported */
7262 status = hw->phy.ops.read_i2c_eeprom(hw,
7263 IXGBE_SFF_SFF_8472_SWAP,
7268 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7270 "Address change required to access page 0xA2, "
7271 "but not supported. Please report the module "
7272 "type to the driver maintainers.");
7276 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7277 /* We have a SFP, but it does not support SFF-8472 */
7278 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7279 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7281 /* We have a SFP which supports a revision of SFF-8472. */
7282 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7283 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7290 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7291 struct rte_dev_eeprom_info *info)
7293 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7294 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7295 uint8_t databyte = 0xFF;
7296 uint8_t *data = info->data;
7299 if (info->length == 0)
7302 for (i = info->offset; i < info->offset + info->length; i++) {
7303 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7304 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7306 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7311 data[i - info->offset] = databyte;
7318 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7320 case ixgbe_mac_X550:
7321 case ixgbe_mac_X550EM_x:
7322 case ixgbe_mac_X550EM_a:
7323 return ETH_RSS_RETA_SIZE_512;
7324 case ixgbe_mac_X550_vf:
7325 case ixgbe_mac_X550EM_x_vf:
7326 case ixgbe_mac_X550EM_a_vf:
7327 return ETH_RSS_RETA_SIZE_64;
7329 return ETH_RSS_RETA_SIZE_128;
7334 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7336 case ixgbe_mac_X550:
7337 case ixgbe_mac_X550EM_x:
7338 case ixgbe_mac_X550EM_a:
7339 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7340 return IXGBE_RETA(reta_idx >> 2);
7342 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7343 case ixgbe_mac_X550_vf:
7344 case ixgbe_mac_X550EM_x_vf:
7345 case ixgbe_mac_X550EM_a_vf:
7346 return IXGBE_VFRETA(reta_idx >> 2);
7348 return IXGBE_RETA(reta_idx >> 2);
7353 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7355 case ixgbe_mac_X550_vf:
7356 case ixgbe_mac_X550EM_x_vf:
7357 case ixgbe_mac_X550EM_a_vf:
7358 return IXGBE_VFMRQC;
7365 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7367 case ixgbe_mac_X550_vf:
7368 case ixgbe_mac_X550EM_x_vf:
7369 case ixgbe_mac_X550EM_a_vf:
7370 return IXGBE_VFRSSRK(i);
7372 return IXGBE_RSSRK(i);
7377 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7379 case ixgbe_mac_82599_vf:
7380 case ixgbe_mac_X540_vf:
7388 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7389 struct rte_eth_dcb_info *dcb_info)
7391 struct ixgbe_dcb_config *dcb_config =
7392 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7393 struct ixgbe_dcb_tc_config *tc;
7394 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7398 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7399 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7401 dcb_info->nb_tcs = 1;
7403 tc_queue = &dcb_info->tc_queue;
7404 nb_tcs = dcb_info->nb_tcs;
7406 if (dcb_config->vt_mode) { /* vt is enabled*/
7407 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7408 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7409 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7410 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7411 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7412 for (j = 0; j < nb_tcs; j++) {
7413 tc_queue->tc_rxq[0][j].base = j;
7414 tc_queue->tc_rxq[0][j].nb_queue = 1;
7415 tc_queue->tc_txq[0][j].base = j;
7416 tc_queue->tc_txq[0][j].nb_queue = 1;
7419 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7420 for (j = 0; j < nb_tcs; j++) {
7421 tc_queue->tc_rxq[i][j].base =
7423 tc_queue->tc_rxq[i][j].nb_queue = 1;
7424 tc_queue->tc_txq[i][j].base =
7426 tc_queue->tc_txq[i][j].nb_queue = 1;
7430 } else { /* vt is disabled*/
7431 struct rte_eth_dcb_rx_conf *rx_conf =
7432 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7433 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7434 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7435 if (dcb_info->nb_tcs == ETH_4_TCS) {
7436 for (i = 0; i < dcb_info->nb_tcs; i++) {
7437 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7438 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7440 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7441 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7442 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7443 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7444 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7445 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7446 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7447 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7448 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7449 for (i = 0; i < dcb_info->nb_tcs; i++) {
7450 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7451 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7453 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7454 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7455 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7456 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7457 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7458 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7459 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7460 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7461 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7462 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7463 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7464 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7465 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7466 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7467 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7468 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7471 for (i = 0; i < dcb_info->nb_tcs; i++) {
7472 tc = &dcb_config->tc_config[i];
7473 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7478 /* Update e-tag ether type */
7480 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7481 uint16_t ether_type)
7483 uint32_t etag_etype;
7485 if (hw->mac.type != ixgbe_mac_X550 &&
7486 hw->mac.type != ixgbe_mac_X550EM_x &&
7487 hw->mac.type != ixgbe_mac_X550EM_a) {
7491 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7492 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7493 etag_etype |= ether_type;
7494 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7495 IXGBE_WRITE_FLUSH(hw);
7500 /* Config l2 tunnel ether type */
7502 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7503 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7506 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7507 struct ixgbe_l2_tn_info *l2_tn_info =
7508 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7510 if (l2_tunnel == NULL)
7513 switch (l2_tunnel->l2_tunnel_type) {
7514 case RTE_L2_TUNNEL_TYPE_E_TAG:
7515 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7516 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7519 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7527 /* Enable e-tag tunnel */
7529 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7531 uint32_t etag_etype;
7533 if (hw->mac.type != ixgbe_mac_X550 &&
7534 hw->mac.type != ixgbe_mac_X550EM_x &&
7535 hw->mac.type != ixgbe_mac_X550EM_a) {
7539 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7540 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7541 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7542 IXGBE_WRITE_FLUSH(hw);
7547 /* Enable l2 tunnel */
7549 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7550 enum rte_eth_tunnel_type l2_tunnel_type)
7553 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7554 struct ixgbe_l2_tn_info *l2_tn_info =
7555 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7557 switch (l2_tunnel_type) {
7558 case RTE_L2_TUNNEL_TYPE_E_TAG:
7559 l2_tn_info->e_tag_en = TRUE;
7560 ret = ixgbe_e_tag_enable(hw);
7563 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7571 /* Disable e-tag tunnel */
7573 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7575 uint32_t etag_etype;
7577 if (hw->mac.type != ixgbe_mac_X550 &&
7578 hw->mac.type != ixgbe_mac_X550EM_x &&
7579 hw->mac.type != ixgbe_mac_X550EM_a) {
7583 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7584 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7585 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7586 IXGBE_WRITE_FLUSH(hw);
7591 /* Disable l2 tunnel */
7593 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7594 enum rte_eth_tunnel_type l2_tunnel_type)
7597 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7598 struct ixgbe_l2_tn_info *l2_tn_info =
7599 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7601 switch (l2_tunnel_type) {
7602 case RTE_L2_TUNNEL_TYPE_E_TAG:
7603 l2_tn_info->e_tag_en = FALSE;
7604 ret = ixgbe_e_tag_disable(hw);
7607 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7616 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7617 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7620 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7621 uint32_t i, rar_entries;
7622 uint32_t rar_low, rar_high;
7624 if (hw->mac.type != ixgbe_mac_X550 &&
7625 hw->mac.type != ixgbe_mac_X550EM_x &&
7626 hw->mac.type != ixgbe_mac_X550EM_a) {
7630 rar_entries = ixgbe_get_num_rx_addrs(hw);
7632 for (i = 1; i < rar_entries; i++) {
7633 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7634 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7635 if ((rar_high & IXGBE_RAH_AV) &&
7636 (rar_high & IXGBE_RAH_ADTYPE) &&
7637 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7638 l2_tunnel->tunnel_id)) {
7639 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7640 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7642 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7652 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7653 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7656 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7657 uint32_t i, rar_entries;
7658 uint32_t rar_low, rar_high;
7660 if (hw->mac.type != ixgbe_mac_X550 &&
7661 hw->mac.type != ixgbe_mac_X550EM_x &&
7662 hw->mac.type != ixgbe_mac_X550EM_a) {
7666 /* One entry for one tunnel. Try to remove potential existing entry. */
7667 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7669 rar_entries = ixgbe_get_num_rx_addrs(hw);
7671 for (i = 1; i < rar_entries; i++) {
7672 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7673 if (rar_high & IXGBE_RAH_AV) {
7676 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7677 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7678 rar_low = l2_tunnel->tunnel_id;
7680 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7681 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7687 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7688 " Please remove a rule before adding a new one.");
7692 static inline struct ixgbe_l2_tn_filter *
7693 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7694 struct ixgbe_l2_tn_key *key)
7698 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7702 return l2_tn_info->hash_map[ret];
7706 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7707 struct ixgbe_l2_tn_filter *l2_tn_filter)
7711 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7712 &l2_tn_filter->key);
7716 "Failed to insert L2 tunnel filter"
7717 " to hash table %d!",
7722 l2_tn_info->hash_map[ret] = l2_tn_filter;
7724 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7730 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7731 struct ixgbe_l2_tn_key *key)
7734 struct ixgbe_l2_tn_filter *l2_tn_filter;
7736 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7740 "No such L2 tunnel filter to delete %d!",
7745 l2_tn_filter = l2_tn_info->hash_map[ret];
7746 l2_tn_info->hash_map[ret] = NULL;
7748 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7749 rte_free(l2_tn_filter);
7754 /* Add l2 tunnel filter */
7756 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7757 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7761 struct ixgbe_l2_tn_info *l2_tn_info =
7762 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7763 struct ixgbe_l2_tn_key key;
7764 struct ixgbe_l2_tn_filter *node;
7767 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7768 key.tn_id = l2_tunnel->tunnel_id;
7770 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7774 "The L2 tunnel filter already exists!");
7778 node = rte_zmalloc("ixgbe_l2_tn",
7779 sizeof(struct ixgbe_l2_tn_filter),
7784 rte_memcpy(&node->key,
7786 sizeof(struct ixgbe_l2_tn_key));
7787 node->pool = l2_tunnel->pool;
7788 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7795 switch (l2_tunnel->l2_tunnel_type) {
7796 case RTE_L2_TUNNEL_TYPE_E_TAG:
7797 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7800 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7805 if ((!restore) && (ret < 0))
7806 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7811 /* Delete l2 tunnel filter */
7813 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7814 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7817 struct ixgbe_l2_tn_info *l2_tn_info =
7818 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7819 struct ixgbe_l2_tn_key key;
7821 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7822 key.tn_id = l2_tunnel->tunnel_id;
7823 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7827 switch (l2_tunnel->l2_tunnel_type) {
7828 case RTE_L2_TUNNEL_TYPE_E_TAG:
7829 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7832 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7841 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7842 * @dev: pointer to rte_eth_dev structure
7843 * @filter_op:operation will be taken.
7844 * @arg: a pointer to specific structure corresponding to the filter_op
7847 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7848 enum rte_filter_op filter_op,
7853 if (filter_op == RTE_ETH_FILTER_NOP)
7857 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7862 switch (filter_op) {
7863 case RTE_ETH_FILTER_ADD:
7864 ret = ixgbe_dev_l2_tunnel_filter_add
7866 (struct rte_eth_l2_tunnel_conf *)arg,
7869 case RTE_ETH_FILTER_DELETE:
7870 ret = ixgbe_dev_l2_tunnel_filter_del
7872 (struct rte_eth_l2_tunnel_conf *)arg);
7875 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7883 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7887 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7889 if (hw->mac.type != ixgbe_mac_X550 &&
7890 hw->mac.type != ixgbe_mac_X550EM_x &&
7891 hw->mac.type != ixgbe_mac_X550EM_a) {
7895 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7896 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7898 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7899 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7904 /* Enable l2 tunnel forwarding */
7906 ixgbe_dev_l2_tunnel_forwarding_enable
7907 (struct rte_eth_dev *dev,
7908 enum rte_eth_tunnel_type l2_tunnel_type)
7910 struct ixgbe_l2_tn_info *l2_tn_info =
7911 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7914 switch (l2_tunnel_type) {
7915 case RTE_L2_TUNNEL_TYPE_E_TAG:
7916 l2_tn_info->e_tag_fwd_en = TRUE;
7917 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7920 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7928 /* Disable l2 tunnel forwarding */
7930 ixgbe_dev_l2_tunnel_forwarding_disable
7931 (struct rte_eth_dev *dev,
7932 enum rte_eth_tunnel_type l2_tunnel_type)
7934 struct ixgbe_l2_tn_info *l2_tn_info =
7935 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7938 switch (l2_tunnel_type) {
7939 case RTE_L2_TUNNEL_TYPE_E_TAG:
7940 l2_tn_info->e_tag_fwd_en = FALSE;
7941 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7944 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7953 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7954 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7957 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7959 uint32_t vmtir, vmvir;
7960 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7962 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7964 "VF id %u should be less than %u",
7970 if (hw->mac.type != ixgbe_mac_X550 &&
7971 hw->mac.type != ixgbe_mac_X550EM_x &&
7972 hw->mac.type != ixgbe_mac_X550EM_a) {
7977 vmtir = l2_tunnel->tunnel_id;
7981 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7983 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7984 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7986 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7987 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7992 /* Enable l2 tunnel tag insertion */
7994 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7995 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7999 switch (l2_tunnel->l2_tunnel_type) {
8000 case RTE_L2_TUNNEL_TYPE_E_TAG:
8001 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8004 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8012 /* Disable l2 tunnel tag insertion */
8014 ixgbe_dev_l2_tunnel_insertion_disable
8015 (struct rte_eth_dev *dev,
8016 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8020 switch (l2_tunnel->l2_tunnel_type) {
8021 case RTE_L2_TUNNEL_TYPE_E_TAG:
8022 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8025 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8034 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8039 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8041 if (hw->mac.type != ixgbe_mac_X550 &&
8042 hw->mac.type != ixgbe_mac_X550EM_x &&
8043 hw->mac.type != ixgbe_mac_X550EM_a) {
8047 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8049 qde |= IXGBE_QDE_STRIP_TAG;
8051 qde &= ~IXGBE_QDE_STRIP_TAG;
8052 qde &= ~IXGBE_QDE_READ;
8053 qde |= IXGBE_QDE_WRITE;
8054 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8059 /* Enable l2 tunnel tag stripping */
8061 ixgbe_dev_l2_tunnel_stripping_enable
8062 (struct rte_eth_dev *dev,
8063 enum rte_eth_tunnel_type l2_tunnel_type)
8067 switch (l2_tunnel_type) {
8068 case RTE_L2_TUNNEL_TYPE_E_TAG:
8069 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8072 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8080 /* Disable l2 tunnel tag stripping */
8082 ixgbe_dev_l2_tunnel_stripping_disable
8083 (struct rte_eth_dev *dev,
8084 enum rte_eth_tunnel_type l2_tunnel_type)
8088 switch (l2_tunnel_type) {
8089 case RTE_L2_TUNNEL_TYPE_E_TAG:
8090 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8093 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8101 /* Enable/disable l2 tunnel offload functions */
8103 ixgbe_dev_l2_tunnel_offload_set
8104 (struct rte_eth_dev *dev,
8105 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8111 if (l2_tunnel == NULL)
8115 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8117 ret = ixgbe_dev_l2_tunnel_enable(
8119 l2_tunnel->l2_tunnel_type);
8121 ret = ixgbe_dev_l2_tunnel_disable(
8123 l2_tunnel->l2_tunnel_type);
8126 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8128 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8132 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8137 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8139 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8141 l2_tunnel->l2_tunnel_type);
8143 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8145 l2_tunnel->l2_tunnel_type);
8148 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8150 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8152 l2_tunnel->l2_tunnel_type);
8154 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8156 l2_tunnel->l2_tunnel_type);
8163 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8166 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8167 IXGBE_WRITE_FLUSH(hw);
8172 /* There's only one register for VxLAN UDP port.
8173 * So, we cannot add several ports. Will update it.
8176 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8180 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8184 return ixgbe_update_vxlan_port(hw, port);
8187 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8188 * UDP port, it must have a value.
8189 * So, will reset it to the original value 0.
8192 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8197 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8199 if (cur_port != port) {
8200 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8204 return ixgbe_update_vxlan_port(hw, 0);
8207 /* Add UDP tunneling port */
8209 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8210 struct rte_eth_udp_tunnel *udp_tunnel)
8213 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8215 if (hw->mac.type != ixgbe_mac_X550 &&
8216 hw->mac.type != ixgbe_mac_X550EM_x &&
8217 hw->mac.type != ixgbe_mac_X550EM_a) {
8221 if (udp_tunnel == NULL)
8224 switch (udp_tunnel->prot_type) {
8225 case RTE_TUNNEL_TYPE_VXLAN:
8226 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8229 case RTE_TUNNEL_TYPE_GENEVE:
8230 case RTE_TUNNEL_TYPE_TEREDO:
8231 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8236 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8244 /* Remove UDP tunneling port */
8246 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8247 struct rte_eth_udp_tunnel *udp_tunnel)
8250 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8252 if (hw->mac.type != ixgbe_mac_X550 &&
8253 hw->mac.type != ixgbe_mac_X550EM_x &&
8254 hw->mac.type != ixgbe_mac_X550EM_a) {
8258 if (udp_tunnel == NULL)
8261 switch (udp_tunnel->prot_type) {
8262 case RTE_TUNNEL_TYPE_VXLAN:
8263 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8265 case RTE_TUNNEL_TYPE_GENEVE:
8266 case RTE_TUNNEL_TYPE_TEREDO:
8267 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8271 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8280 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8282 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8284 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8288 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8290 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8292 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8295 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8297 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8300 /* peek the message first */
8301 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8303 /* PF reset VF event */
8304 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8305 /* dummy mbx read to ack pf */
8306 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8308 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8314 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8317 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8318 struct ixgbe_interrupt *intr =
8319 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8320 ixgbevf_intr_disable(dev);
8322 /* read-on-clear nic registers here */
8323 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8326 /* only one misc vector supported - mailbox */
8327 eicr &= IXGBE_VTEICR_MASK;
8328 if (eicr == IXGBE_MISC_VEC_ID)
8329 intr->flags |= IXGBE_FLAG_MAILBOX;
8335 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8337 struct ixgbe_interrupt *intr =
8338 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8340 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8341 ixgbevf_mbx_process(dev);
8342 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8345 ixgbevf_intr_enable(dev);
8351 ixgbevf_dev_interrupt_handler(void *param)
8353 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8355 ixgbevf_dev_interrupt_get_status(dev);
8356 ixgbevf_dev_interrupt_action(dev);
8360 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8361 * @hw: pointer to hardware structure
8363 * Stops the transmit data path and waits for the HW to internally empty
8364 * the Tx security block
8366 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8368 #define IXGBE_MAX_SECTX_POLL 40
8373 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8374 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8375 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8376 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8377 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8378 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8380 /* Use interrupt-safe sleep just in case */
8384 /* For informational purposes only */
8385 if (i >= IXGBE_MAX_SECTX_POLL)
8386 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8387 "path fully disabled. Continuing with init.");
8389 return IXGBE_SUCCESS;
8393 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8394 * @hw: pointer to hardware structure
8396 * Enables the transmit data path.
8398 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8402 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8403 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8404 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8405 IXGBE_WRITE_FLUSH(hw);
8407 return IXGBE_SUCCESS;
8410 /* restore n-tuple filter */
8412 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8414 struct ixgbe_filter_info *filter_info =
8415 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8416 struct ixgbe_5tuple_filter *node;
8418 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8419 ixgbe_inject_5tuple_filter(dev, node);
8423 /* restore ethernet type filter */
8425 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8427 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8428 struct ixgbe_filter_info *filter_info =
8429 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8432 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8433 if (filter_info->ethertype_mask & (1 << i)) {
8434 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8435 filter_info->ethertype_filters[i].etqf);
8436 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8437 filter_info->ethertype_filters[i].etqs);
8438 IXGBE_WRITE_FLUSH(hw);
8443 /* restore SYN filter */
8445 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8447 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8448 struct ixgbe_filter_info *filter_info =
8449 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8452 synqf = filter_info->syn_info;
8454 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8455 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8456 IXGBE_WRITE_FLUSH(hw);
8460 /* restore L2 tunnel filter */
8462 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8464 struct ixgbe_l2_tn_info *l2_tn_info =
8465 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8466 struct ixgbe_l2_tn_filter *node;
8467 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8469 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8470 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8471 l2_tn_conf.tunnel_id = node->key.tn_id;
8472 l2_tn_conf.pool = node->pool;
8473 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8477 /* restore rss filter */
8479 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8481 struct ixgbe_filter_info *filter_info =
8482 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8484 if (filter_info->rss_info.conf.queue_num)
8485 ixgbe_config_rss_filter(dev,
8486 &filter_info->rss_info, TRUE);
8490 ixgbe_filter_restore(struct rte_eth_dev *dev)
8492 ixgbe_ntuple_filter_restore(dev);
8493 ixgbe_ethertype_filter_restore(dev);
8494 ixgbe_syn_filter_restore(dev);
8495 ixgbe_fdir_filter_restore(dev);
8496 ixgbe_l2_tn_filter_restore(dev);
8497 ixgbe_rss_filter_restore(dev);
8503 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8505 struct ixgbe_l2_tn_info *l2_tn_info =
8506 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8507 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8509 if (l2_tn_info->e_tag_en)
8510 (void)ixgbe_e_tag_enable(hw);
8512 if (l2_tn_info->e_tag_fwd_en)
8513 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8515 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8518 /* remove all the n-tuple filters */
8520 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8522 struct ixgbe_filter_info *filter_info =
8523 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8524 struct ixgbe_5tuple_filter *p_5tuple;
8526 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8527 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8530 /* remove all the ether type filters */
8532 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8534 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8535 struct ixgbe_filter_info *filter_info =
8536 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8539 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8540 if (filter_info->ethertype_mask & (1 << i) &&
8541 !filter_info->ethertype_filters[i].conf) {
8542 (void)ixgbe_ethertype_filter_remove(filter_info,
8544 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8545 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8546 IXGBE_WRITE_FLUSH(hw);
8551 /* remove the SYN filter */
8553 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8555 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8556 struct ixgbe_filter_info *filter_info =
8557 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8559 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8560 filter_info->syn_info = 0;
8562 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8563 IXGBE_WRITE_FLUSH(hw);
8567 /* remove all the L2 tunnel filters */
8569 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8571 struct ixgbe_l2_tn_info *l2_tn_info =
8572 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8573 struct ixgbe_l2_tn_filter *l2_tn_filter;
8574 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8577 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8578 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8579 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8580 l2_tn_conf.pool = l2_tn_filter->pool;
8581 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8589 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8590 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8591 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8592 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8593 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8594 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8596 RTE_INIT(ixgbe_init_log)
8598 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8599 if (ixgbe_logtype_init >= 0)
8600 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8601 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8602 if (ixgbe_logtype_driver >= 0)
8603 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);