drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_atomic.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_malloc.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_hash_crc.h>
  35 #ifdef RTE_LIBRTE_SECURITY
  36 #include <rte_security_driver.h>
  37 #endif
  38
  39 #include "ixgbe_logs.h"
  40 #include "base/ixgbe_api.h"
  41 #include "base/ixgbe_vf.h"
  42 #include "base/ixgbe_common.h"
  43 #include "ixgbe_ethdev.h"
  44 #include "ixgbe_bypass.h"
  45 #include "ixgbe_rxtx.h"
  46 #include "base/ixgbe_type.h"
  47 #include "base/ixgbe_phy.h"
  48 #include "ixgbe_regs.h"
  49
  50 /*
  51  * High threshold controlling when to start sending XOFF frames. Must be at
  52  * least 8 bytes less than receive packet buffer size. This value is in units
  53  * of 1024 bytes.
  54  */
  55 #define IXGBE_FC_HI    0x80
  56
  57 /*
  58  * Low threshold controlling when to start sending XON frames. This value is
  59  * in units of 1024 bytes.
  60  */
  61 #define IXGBE_FC_LO    0x40
  62
  63 /* Default minimum inter-interrupt interval for EITR configuration */
  64 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  65
  66 /* Timer value included in XOFF frames. */
  67 #define IXGBE_FC_PAUSE 0x680
  68
  69 /*Default value of Max Rx Queue*/
  70 #define IXGBE_MAX_RX_QUEUE_NUM 128
  71
  72 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  73 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  74 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  75
  76 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  77 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  78 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  79
  80 /*
  81  *  Default values for RX/TX configuration
  82  */
  83 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  84 #define IXGBE_DEFAULT_RX_PTHRESH      8
  85 #define IXGBE_DEFAULT_RX_HTHRESH      8
  86 #define IXGBE_DEFAULT_RX_WTHRESH      0
  87
  88 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  89 #define IXGBE_DEFAULT_TX_PTHRESH      32
  90 #define IXGBE_DEFAULT_TX_HTHRESH      0
  91 #define IXGBE_DEFAULT_TX_WTHRESH      0
  92 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  93
  94 /* Bit shift and mask */
  95 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  96 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  97 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  98 #define IXGBE_8_BIT_MASK   UINT8_MAX
  99
 100 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 101
 102 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 103
 104 #define IXGBE_HKEY_MAX_INDEX 10
 105
 106 /* Additional timesync values. */
 107 #define NSEC_PER_SEC             1000000000L
 108 #define IXGBE_INCVAL_10GB        0x66666666
 109 #define IXGBE_INCVAL_1GB         0x40000000
 110 #define IXGBE_INCVAL_100         0x50000000
 111 #define IXGBE_INCVAL_SHIFT_10GB  28
 112 #define IXGBE_INCVAL_SHIFT_1GB   24
 113 #define IXGBE_INCVAL_SHIFT_100   21
 114 #define IXGBE_INCVAL_SHIFT_82599 7
 115 #define IXGBE_INCPER_SHIFT_82599 24
 116
 117 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 118
 119 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 120 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 121 #define DEFAULT_ETAG_ETYPE                     0x893f
 122 #define IXGBE_ETAG_ETYPE                       0x00005084
 123 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 124 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 125 #define IXGBE_RAH_ADTYPE                       0x40000000
 126 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 127 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 128 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 129 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 130 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 131 #define IXGBE_VTEICR_MASK                      0x07
 132
 133 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 134 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 135
 136 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 137 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 143 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 144 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 147 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 153 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 155                                 int wait_to_complete);
 156 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 157                                 struct rte_eth_stats *stats);
 158 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_xstat *xstats, unsigned n);
 160 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 161                                   struct rte_eth_xstat *xstats, unsigned n);
 162 static int
 163 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 164                 uint64_t *values, unsigned int n);
 165 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 166 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 167 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 168         struct rte_eth_xstat_name *xstats_names,
 169         unsigned int size);
 170 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 171         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 172 static int ixgbe_dev_xstats_get_names_by_id(
 173         struct rte_eth_dev *dev,
 174         struct rte_eth_xstat_name *xstats_names,
 175         const uint64_t *ids,
 176         unsigned int limit);
 177 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 178                                              uint16_t queue_id,
 179                                              uint8_t stat_idx,
 180                                              uint8_t is_rx);
 181 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 182                                  size_t fw_size);
 183 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 184                                struct rte_eth_dev_info *dev_info);
 185 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 186 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 187                                  struct rte_eth_dev_info *dev_info);
 188 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 189
 190 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 191                 uint16_t vlan_id, int on);
 192 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 193                                enum rte_vlan_type vlan_type,
 194                                uint16_t tpid_id);
 195 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 196                 uint16_t queue, bool on);
 197 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 198                 int on);
 199 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 200 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 201 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 202 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 203 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 204
 205 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 206 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 207 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 208                                struct rte_eth_fc_conf *fc_conf);
 209 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 210                                struct rte_eth_fc_conf *fc_conf);
 211 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 212                 struct rte_eth_pfc_conf *pfc_conf);
 213 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 214                         struct rte_eth_rss_reta_entry64 *reta_conf,
 215                         uint16_t reta_size);
 216 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 217                         struct rte_eth_rss_reta_entry64 *reta_conf,
 218                         uint16_t reta_size);
 219 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 221 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 225                                       struct rte_intr_handle *handle);
 226 static void ixgbe_dev_interrupt_handler(void *param);
 227 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 228 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 229                          uint32_t index, uint32_t pool);
 230 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 231 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 232                                            struct ether_addr *mac_addr);
 233 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 234 static bool is_device_supported(struct rte_eth_dev *dev,
 235                                 struct rte_pci_driver *drv);
 236
 237 /* For Virtual Function support */
 238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 240 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 241 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 242 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 243                                    int wait_to_complete);
 244 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 245 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 246 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 247 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 248 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 249 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 250                 struct rte_eth_stats *stats);
 251 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 252 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 253                 uint16_t vlan_id, int on);
 254 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 255                 uint16_t queue, int on);
 256 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 257 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 258 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 259                                             uint16_t queue_id);
 260 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 261                                              uint16_t queue_id);
 262 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 263                                  uint8_t queue, uint8_t msix_vector);
 264 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 267
 268 /* For Eth VMDQ APIs support */
 269 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 270                 ether_addr * mac_addr, uint8_t on);
 271 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 272 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 273                 struct rte_eth_mirror_conf *mirror_conf,
 274                 uint8_t rule_id, uint8_t on);
 275 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 276                 uint8_t rule_id);
 277 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 278                                           uint16_t queue_id);
 279 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 280                                            uint16_t queue_id);
 281 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 282                                uint8_t queue, uint8_t msix_vector);
 283 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 284
 285 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 286                                 struct ether_addr *mac_addr,
 287                                 uint32_t index, uint32_t pool);
 288 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 289 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 290                                              struct ether_addr *mac_addr);
 291 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 292                         struct rte_eth_syn_filter *filter);
 293 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 294                         enum rte_filter_op filter_op,
 295                         void *arg);
 296 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 297                         struct ixgbe_5tuple_filter *filter);
 298 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 301                                 enum rte_filter_op filter_op,
 302                                 void *arg);
 303 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 304                         struct rte_eth_ntuple_filter *filter);
 305 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 306                                 enum rte_filter_op filter_op,
 307                                 void *arg);
 308 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 309                         struct rte_eth_ethertype_filter *filter);
 310 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 311                      enum rte_filter_type filter_type,
 312                      enum rte_filter_op filter_op,
 313                      void *arg);
 314 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 315
 316 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 317                                       struct ether_addr *mc_addr_set,
 318                                       uint32_t nb_mc_addr);
 319 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 320                                    struct rte_eth_dcb_info *dcb_info);
 321
 322 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 324                             struct rte_dev_reg_info *regs);
 325 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 326 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 327                                 struct rte_dev_eeprom_info *eeprom);
 328 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 329                                 struct rte_dev_eeprom_info *eeprom);
 330
 331 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 332 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 333                                 struct rte_dev_reg_info *regs);
 334
 335 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 337 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 338                                             struct timespec *timestamp,
 339                                             uint32_t flags);
 340 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 341                                             struct timespec *timestamp);
 342 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 343 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 344                                    struct timespec *timestamp);
 345 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 346                                    const struct timespec *timestamp);
 347 static void ixgbevf_dev_interrupt_handler(void *param);
 348
 349 static int ixgbe_dev_l2_tunnel_eth_type_conf
 350         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 351 static int ixgbe_dev_l2_tunnel_offload_set
 352         (struct rte_eth_dev *dev,
 353          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 354          uint32_t mask,
 355          uint8_t en);
 356 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 357                                              enum rte_filter_op filter_op,
 358                                              void *arg);
 359
 360 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 361                                          struct rte_eth_udp_tunnel *udp_tunnel);
 362 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 363                                          struct rte_eth_udp_tunnel *udp_tunnel);
 364 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 365 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 366
 367 /*
 368  * Define VF Stats MACRO for Non "cleared on read" register
 369  */
 370 #define UPDATE_VF_STAT(reg, last, cur)                          \
 371 {                                                               \
 372         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 373         cur += (latest - last) & UINT_MAX;                      \
 374         last = latest;                                          \
 375 }
 376
 377 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 378 {                                                                \
 379         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 380         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 381         u64 latest = ((new_msb << 32) | new_lsb);                \
 382         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 383         last = latest;                                           \
 384 }
 385
 386 #define IXGBE_SET_HWSTRIP(h, q) do {\
 387                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 388                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 389                 (h)->bitmap[idx] |= 1 << bit;\
 390         } while (0)
 391
 392 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 393                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 394                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 395                 (h)->bitmap[idx] &= ~(1 << bit);\
 396         } while (0)
 397
 398 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 399                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 400                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 401                 (r) = (h)->bitmap[idx] >> bit & 1;\
 402         } while (0)
 403
 404 int ixgbe_logtype_init;
 405 int ixgbe_logtype_driver;
 406
 407 /*
 408  * The set of PCI devices this driver supports
 409  */
 410 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 459 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 461 #endif
 462         { .vendor_id = 0, /* sentinel */ },
 463 };
 464
 465 /*
 466  * The set of PCI devices this driver supports (for 82599 VF)
 467  */
 468 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 479         { .vendor_id = 0, /* sentinel */ },
 480 };
 481
 482 static const struct rte_eth_desc_lim rx_desc_lim = {
 483         .nb_max = IXGBE_MAX_RING_DESC,
 484         .nb_min = IXGBE_MIN_RING_DESC,
 485         .nb_align = IXGBE_RXD_ALIGN,
 486 };
 487
 488 static const struct rte_eth_desc_lim tx_desc_lim = {
 489         .nb_max = IXGBE_MAX_RING_DESC,
 490         .nb_min = IXGBE_MIN_RING_DESC,
 491         .nb_align = IXGBE_TXD_ALIGN,
 492         .nb_seg_max = IXGBE_TX_MAX_SEG,
 493         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 494 };
 495
 496 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 497         .dev_configure        = ixgbe_dev_configure,
 498         .dev_start            = ixgbe_dev_start,
 499         .dev_stop             = ixgbe_dev_stop,
 500         .dev_set_link_up    = ixgbe_dev_set_link_up,
 501         .dev_set_link_down  = ixgbe_dev_set_link_down,
 502         .dev_close            = ixgbe_dev_close,
 503         .dev_reset            = ixgbe_dev_reset,
 504         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 505         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 506         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 507         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 508         .link_update          = ixgbe_dev_link_update,
 509         .stats_get            = ixgbe_dev_stats_get,
 510         .xstats_get           = ixgbe_dev_xstats_get,
 511         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 512         .stats_reset          = ixgbe_dev_stats_reset,
 513         .xstats_reset         = ixgbe_dev_xstats_reset,
 514         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 515         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 516         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 517         .fw_version_get       = ixgbe_fw_version_get,
 518         .dev_infos_get        = ixgbe_dev_info_get,
 519         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 520         .mtu_set              = ixgbe_dev_mtu_set,
 521         .vlan_filter_set      = ixgbe_vlan_filter_set,
 522         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 523         .vlan_offload_set     = ixgbe_vlan_offload_set,
 524         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 525         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 526         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 527         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 528         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 529         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 530         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 531         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 532         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 533         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 534         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 535         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 536         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 537         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 538         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 539         .dev_led_on           = ixgbe_dev_led_on,
 540         .dev_led_off          = ixgbe_dev_led_off,
 541         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 542         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 543         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 544         .mac_addr_add         = ixgbe_add_rar,
 545         .mac_addr_remove      = ixgbe_remove_rar,
 546         .mac_addr_set         = ixgbe_set_default_mac_addr,
 547         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 548         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 549         .mirror_rule_set      = ixgbe_mirror_rule_set,
 550         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 551         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 552         .reta_update          = ixgbe_dev_rss_reta_update,
 553         .reta_query           = ixgbe_dev_rss_reta_query,
 554         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 555         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 556         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 557         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 558         .rxq_info_get         = ixgbe_rxq_info_get,
 559         .txq_info_get         = ixgbe_txq_info_get,
 560         .timesync_enable      = ixgbe_timesync_enable,
 561         .timesync_disable     = ixgbe_timesync_disable,
 562         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 563         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 564         .get_reg              = ixgbe_get_regs,
 565         .get_eeprom_length    = ixgbe_get_eeprom_length,
 566         .get_eeprom           = ixgbe_get_eeprom,
 567         .set_eeprom           = ixgbe_set_eeprom,
 568         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 569         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 570         .timesync_read_time   = ixgbe_timesync_read_time,
 571         .timesync_write_time  = ixgbe_timesync_write_time,
 572         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 573         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 574         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 575         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 576         .tm_ops_get           = ixgbe_tm_ops_get,
 577 };
 578
 579 /*
 580  * dev_ops for virtual function, bare necessities for basic vf
 581  * operation have been implemented
 582  */
 583 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 584         .dev_configure        = ixgbevf_dev_configure,
 585         .dev_start            = ixgbevf_dev_start,
 586         .dev_stop             = ixgbevf_dev_stop,
 587         .link_update          = ixgbevf_dev_link_update,
 588         .stats_get            = ixgbevf_dev_stats_get,
 589         .xstats_get           = ixgbevf_dev_xstats_get,
 590         .stats_reset          = ixgbevf_dev_stats_reset,
 591         .xstats_reset         = ixgbevf_dev_stats_reset,
 592         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 593         .dev_close            = ixgbevf_dev_close,
 594         .dev_reset            = ixgbevf_dev_reset,
 595         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 596         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 597         .dev_infos_get        = ixgbevf_dev_info_get,
 598         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 599         .mtu_set              = ixgbevf_dev_set_mtu,
 600         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 601         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 602         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 603         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 604         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 605         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 606         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 607         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 608         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 609         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 610         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 611         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 612         .mac_addr_add         = ixgbevf_add_mac_addr,
 613         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 614         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 615         .rxq_info_get         = ixgbe_rxq_info_get,
 616         .txq_info_get         = ixgbe_txq_info_get,
 617         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 618         .get_reg              = ixgbevf_get_regs,
 619         .reta_update          = ixgbe_dev_rss_reta_update,
 620         .reta_query           = ixgbe_dev_rss_reta_query,
 621         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 622         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 623 };
 624
 625 /* store statistics names and its offset in stats structure */
 626 struct rte_ixgbe_xstats_name_off {
 627         char name[RTE_ETH_XSTATS_NAME_SIZE];
 628         unsigned offset;
 629 };
 630
 631 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 632         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 633         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 634         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 635         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 636         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 637         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 638         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 639         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 640         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 641         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 642         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 643         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 644         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 645         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 646         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 647                 prc1023)},
 648         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 649                 prc1522)},
 650         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 651         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 652         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 653         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 654         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 655         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 656         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 657         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 658         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 659         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 660         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 661         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 662         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 663         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 664         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 665         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 666         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 667                 ptc1023)},
 668         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 669                 ptc1522)},
 670         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 671         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 672         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 673         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 674
 675         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 676                 fdirustat_add)},
 677         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 678                 fdirustat_remove)},
 679         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 680                 fdirfstat_fadd)},
 681         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 682                 fdirfstat_fremove)},
 683         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 684                 fdirmatch)},
 685         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 686                 fdirmiss)},
 687
 688         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 689         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 690         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 691                 fclast)},
 692         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 693         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 694         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 695         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 696         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 697                 fcoe_noddp)},
 698         {"rx_fcoe_no_direct_data_placement_ext_buff",
 699                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 700
 701         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 702                 lxontxc)},
 703         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 704                 lxonrxc)},
 705         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxofftxc)},
 707         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxoffrxc)},
 709         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 710 };
 711
 712 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 713                            sizeof(rte_ixgbe_stats_strings[0]))
 714
 715 /* MACsec statistics */
 716 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 717         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 718                 out_pkts_untagged)},
 719         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 720                 out_pkts_encrypted)},
 721         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_protected)},
 723         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_octets_encrypted)},
 725         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_octets_protected)},
 727         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 728                 in_pkts_untagged)},
 729         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 730                 in_pkts_badtag)},
 731         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_nosci)},
 733         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_unknownsci)},
 735         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 736                 in_octets_decrypted)},
 737         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 738                 in_octets_validated)},
 739         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_unchecked)},
 741         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_delayed)},
 743         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_late)},
 745         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_ok)},
 747         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_invalid)},
 749         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_notvalid)},
 751         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_unusedsa)},
 753         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notusingsa)},
 755 };
 756
 757 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 758                            sizeof(rte_ixgbe_macsec_strings[0]))
 759
 760 /* Per-queue statistics */
 761 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 762         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 763         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 764         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 765         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 766 };
 767
 768 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 769                            sizeof(rte_ixgbe_rxq_strings[0]))
 770 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 771
 772 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 773         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 774         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 775         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 776                 pxon2offc)},
 777 };
 778
 779 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 780                            sizeof(rte_ixgbe_txq_strings[0]))
 781 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 782
 783 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 784         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 785 };
 786
 787 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 788                 sizeof(rte_ixgbevf_stats_strings[0]))
 789
 790 /**
 791  * Atomically reads the link status information from global
 792  * structure rte_eth_dev.
 793  *
 794  * @param dev
 795  *   - Pointer to the structure rte_eth_dev to read from.
 796  *   - Pointer to the buffer to be saved with the link status.
 797  *
 798  * @return
 799  *   - On success, zero.
 800  *   - On failure, negative value.
 801  */
 802 static inline int
 803 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 804                                 struct rte_eth_link *link)
 805 {
 806         struct rte_eth_link *dst = link;
 807         struct rte_eth_link *src = &(dev->data->dev_link);
 808
 809         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 810                                         *(uint64_t *)src) == 0)
 811                 return -1;
 812
 813         return 0;
 814 }
 815
 816 /**
 817  * Atomically writes the link status information into global
 818  * structure rte_eth_dev.
 819  *
 820  * @param dev
 821  *   - Pointer to the structure rte_eth_dev to read from.
 822  *   - Pointer to the buffer to be saved with the link status.
 823  *
 824  * @return
 825  *   - On success, zero.
 826  *   - On failure, negative value.
 827  */
 828 static inline int
 829 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 830                                 struct rte_eth_link *link)
 831 {
 832         struct rte_eth_link *dst = &(dev->data->dev_link);
 833         struct rte_eth_link *src = link;
 834
 835         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 836                                         *(uint64_t *)src) == 0)
 837                 return -1;
 838
 839         return 0;
 840 }
 841
 842 /*
 843  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 844  */
 845 static inline int
 846 ixgbe_is_sfp(struct ixgbe_hw *hw)
 847 {
 848         switch (hw->phy.type) {
 849         case ixgbe_phy_sfp_avago:
 850         case ixgbe_phy_sfp_ftl:
 851         case ixgbe_phy_sfp_intel:
 852         case ixgbe_phy_sfp_unknown:
 853         case ixgbe_phy_sfp_passive_tyco:
 854         case ixgbe_phy_sfp_passive_unknown:
 855                 return 1;
 856         default:
 857                 return 0;
 858         }
 859 }
 860
 861 static inline int32_t
 862 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 863 {
 864         uint32_t ctrl_ext;
 865         int32_t status;
 866
 867         status = ixgbe_reset_hw(hw);
 868
 869         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 870         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 871         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 872         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 873         IXGBE_WRITE_FLUSH(hw);
 874
 875         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 876                 status = IXGBE_SUCCESS;
 877         return status;
 878 }
 879
 880 static inline void
 881 ixgbe_enable_intr(struct rte_eth_dev *dev)
 882 {
 883         struct ixgbe_interrupt *intr =
 884                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 885         struct ixgbe_hw *hw =
 886                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 887
 888         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 889         IXGBE_WRITE_FLUSH(hw);
 890 }
 891
 892 /*
 893  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 894  */
 895 static void
 896 ixgbe_disable_intr(struct ixgbe_hw *hw)
 897 {
 898         PMD_INIT_FUNC_TRACE();
 899
 900         if (hw->mac.type == ixgbe_mac_82598EB) {
 901                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 902         } else {
 903                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 904                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 905                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 906         }
 907         IXGBE_WRITE_FLUSH(hw);
 908 }
 909
 910 /*
 911  * This function resets queue statistics mapping registers.
 912  * From Niantic datasheet, Initialization of Statistics section:
 913  * "...if software requires the queue counters, the RQSMR and TQSM registers
 914  * must be re-programmed following a device reset.
 915  */
 916 static void
 917 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 918 {
 919         uint32_t i;
 920
 921         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 922                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 923                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 924         }
 925 }
 926
 927
 928 static int
 929 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 930                                   uint16_t queue_id,
 931                                   uint8_t stat_idx,
 932                                   uint8_t is_rx)
 933 {
 934 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 935 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 936 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 937
 938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 939         struct ixgbe_stat_mapping_registers *stat_mappings =
 940                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 941         uint32_t qsmr_mask = 0;
 942         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 943         uint32_t q_map;
 944         uint8_t n, offset;
 945
 946         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 947                 (hw->mac.type != ixgbe_mac_X540) &&
 948                 (hw->mac.type != ixgbe_mac_X550) &&
 949                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 950                 (hw->mac.type != ixgbe_mac_X550EM_a))
 951                 return -ENOSYS;
 952
 953         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 954                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 955                      queue_id, stat_idx);
 956
 957         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 958         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 959                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 960                 return -EIO;
 961         }
 962         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 963
 964         /* Now clear any previous stat_idx set */
 965         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 966         if (!is_rx)
 967                 stat_mappings->tqsm[n] &= ~clearing_mask;
 968         else
 969                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 970
 971         q_map = (uint32_t)stat_idx;
 972         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 973         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 974         if (!is_rx)
 975                 stat_mappings->tqsm[n] |= qsmr_mask;
 976         else
 977                 stat_mappings->rqsmr[n] |= qsmr_mask;
 978
 979         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 980                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 981                      queue_id, stat_idx);
 982         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 983                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 984
 985         /* Now write the mapping in the appropriate register */
 986         if (is_rx) {
 987                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 988                              stat_mappings->rqsmr[n], n);
 989                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 990         } else {
 991                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 992                              stat_mappings->tqsm[n], n);
 993                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 994         }
 995         return 0;
 996 }
 997
 998 static void
 999 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1000 {
1001         struct ixgbe_stat_mapping_registers *stat_mappings =
1002                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1004         int i;
1005
1006         /* write whatever was in stat mapping table to the NIC */
1007         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1008                 /* rx */
1009                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1010
1011                 /* tx */
1012                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1013         }
1014 }
1015
1016 static void
1017 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1018 {
1019         uint8_t i;
1020         struct ixgbe_dcb_tc_config *tc;
1021         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1022
1023         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1024         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1025         for (i = 0; i < dcb_max_tc; i++) {
1026                 tc = &dcb_config->tc_config[i];
1027                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1028                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1029                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1030                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1031                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1032                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1033                 tc->pfc = ixgbe_dcb_pfc_disabled;
1034         }
1035
1036         /* Initialize default user to priority mapping, UPx->TC0 */
1037         tc = &dcb_config->tc_config[0];
1038         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1039         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1040         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1041                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1042                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1043         }
1044         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1045         dcb_config->pfc_mode_enable = false;
1046         dcb_config->vt_mode = true;
1047         dcb_config->round_robin_enable = false;
1048         /* support all DCB capabilities in 82599 */
1049         dcb_config->support.capabilities = 0xFF;
1050
1051         /*we only support 4 Tcs for X540, X550 */
1052         if (hw->mac.type == ixgbe_mac_X540 ||
1053                 hw->mac.type == ixgbe_mac_X550 ||
1054                 hw->mac.type == ixgbe_mac_X550EM_x ||
1055                 hw->mac.type == ixgbe_mac_X550EM_a) {
1056                 dcb_config->num_tcs.pg_tcs = 4;
1057                 dcb_config->num_tcs.pfc_tcs = 4;
1058         }
1059 }
1060
1061 /*
1062  * Ensure that all locks are released before first NVM or PHY access
1063  */
1064 static void
1065 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1066 {
1067         uint16_t mask;
1068
1069         /*
1070          * Phy lock should not fail in this early stage. If this is the case,
1071          * it is due to an improper exit of the application.
1072          * So force the release of the faulty lock. Release of common lock
1073          * is done automatically by swfw_sync function.
1074          */
1075         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1076         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1077                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1078         }
1079         ixgbe_release_swfw_semaphore(hw, mask);
1080
1081         /*
1082          * These ones are more tricky since they are common to all ports; but
1083          * swfw_sync retries last long enough (1s) to be almost sure that if
1084          * lock can not be taken it is due to an improper lock of the
1085          * semaphore.
1086          */
1087         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1088         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1089                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1090         }
1091         ixgbe_release_swfw_semaphore(hw, mask);
1092 }
1093
1094 /*
1095  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1096  * It returns 0 on success.
1097  */
1098 static int
1099 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1100 {
1101         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1102         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1103         struct ixgbe_hw *hw =
1104                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1105         struct ixgbe_vfta *shadow_vfta =
1106                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1107         struct ixgbe_hwstrip *hwstrip =
1108                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1109         struct ixgbe_dcb_config *dcb_config =
1110                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1111         struct ixgbe_filter_info *filter_info =
1112                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1113         struct ixgbe_bw_conf *bw_conf =
1114                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1115         uint32_t ctrl_ext;
1116         uint16_t csum;
1117         int diag, i;
1118
1119         PMD_INIT_FUNC_TRACE();
1120
1121         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1122         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1123         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1124         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1125
1126         /*
1127          * For secondary processes, we don't initialise any further as primary
1128          * has already done this work. Only check we don't need a different
1129          * RX and TX function.
1130          */
1131         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1132                 struct ixgbe_tx_queue *txq;
1133                 /* TX queue function in primary, set by last queue initialized
1134                  * Tx queue may not initialized by primary process
1135                  */
1136                 if (eth_dev->data->tx_queues) {
1137                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1138                         ixgbe_set_tx_function(eth_dev, txq);
1139                 } else {
1140                         /* Use default TX function if we get here */
1141                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1142                                      "Using default TX function.");
1143                 }
1144
1145                 ixgbe_set_rx_function(eth_dev);
1146
1147                 return 0;
1148         }
1149
1150         rte_eth_copy_pci_info(eth_dev, pci_dev);
1151
1152         /* Vendor and Device ID need to be set before init of shared code */
1153         hw->device_id = pci_dev->id.device_id;
1154         hw->vendor_id = pci_dev->id.vendor_id;
1155         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1156         hw->allow_unsupported_sfp = 1;
1157
1158         /* Initialize the shared code (base driver) */
1159 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1160         diag = ixgbe_bypass_init_shared_code(hw);
1161 #else
1162         diag = ixgbe_init_shared_code(hw);
1163 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1164
1165         if (diag != IXGBE_SUCCESS) {
1166                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1167                 return -EIO;
1168         }
1169
1170         /* pick up the PCI bus settings for reporting later */
1171         ixgbe_get_bus_info(hw);
1172
1173         /* Unlock any pending hardware semaphore */
1174         ixgbe_swfw_lock_reset(hw);
1175
1176 #ifdef RTE_LIBRTE_SECURITY
1177         /* Initialize security_ctx only for primary process*/
1178         if (ixgbe_ipsec_ctx_create(eth_dev))
1179                 return -ENOMEM;
1180 #endif
1181
1182         /* Initialize DCB configuration*/
1183         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1184         ixgbe_dcb_init(hw, dcb_config);
1185         /* Get Hardware Flow Control setting */
1186         hw->fc.requested_mode = ixgbe_fc_full;
1187         hw->fc.current_mode = ixgbe_fc_full;
1188         hw->fc.pause_time = IXGBE_FC_PAUSE;
1189         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1190                 hw->fc.low_water[i] = IXGBE_FC_LO;
1191                 hw->fc.high_water[i] = IXGBE_FC_HI;
1192         }
1193         hw->fc.send_xon = 1;
1194
1195         /* Make sure we have a good EEPROM before we read from it */
1196         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1197         if (diag != IXGBE_SUCCESS) {
1198                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1199                 return -EIO;
1200         }
1201
1202 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1203         diag = ixgbe_bypass_init_hw(hw);
1204 #else
1205         diag = ixgbe_init_hw(hw);
1206 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1207
1208         /*
1209          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1210          * is called too soon after the kernel driver unbinding/binding occurs.
1211          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1212          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1213          * also called. See ixgbe_identify_phy_82599(). The reason for the
1214          * failure is not known, and only occuts when virtualisation features
1215          * are disabled in the bios. A delay of 100ms  was found to be enough by
1216          * trial-and-error, and is doubled to be safe.
1217          */
1218         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1219                 rte_delay_ms(200);
1220                 diag = ixgbe_init_hw(hw);
1221         }
1222
1223         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1224                 diag = IXGBE_SUCCESS;
1225
1226         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1227                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1228                              "LOM.  Please be aware there may be issues associated "
1229                              "with your hardware.");
1230                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1231                              "please contact your Intel or hardware representative "
1232                              "who provided you with this hardware.");
1233         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1234                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1235         if (diag) {
1236                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1237                 return -EIO;
1238         }
1239
1240         /* Reset the hw statistics */
1241         ixgbe_dev_stats_reset(eth_dev);
1242
1243         /* disable interrupt */
1244         ixgbe_disable_intr(hw);
1245
1246         /* reset mappings for queue statistics hw counters*/
1247         ixgbe_reset_qstat_mappings(hw);
1248
1249         /* Allocate memory for storing MAC addresses */
1250         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1251                                                hw->mac.num_rar_entries, 0);
1252         if (eth_dev->data->mac_addrs == NULL) {
1253                 PMD_INIT_LOG(ERR,
1254                              "Failed to allocate %u bytes needed to store "
1255                              "MAC addresses",
1256                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1257                 return -ENOMEM;
1258         }
1259         /* Copy the permanent MAC address */
1260         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1261                         &eth_dev->data->mac_addrs[0]);
1262
1263         /* Allocate memory for storing hash filter MAC addresses */
1264         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1265                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1266         if (eth_dev->data->hash_mac_addrs == NULL) {
1267                 PMD_INIT_LOG(ERR,
1268                              "Failed to allocate %d bytes needed to store MAC addresses",
1269                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1270                 return -ENOMEM;
1271         }
1272
1273         /* initialize the vfta */
1274         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1275
1276         /* initialize the hw strip bitmap*/
1277         memset(hwstrip, 0, sizeof(*hwstrip));
1278
1279         /* initialize PF if max_vfs not zero */
1280         ixgbe_pf_host_init(eth_dev);
1281
1282         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1283         /* let hardware know driver is loaded */
1284         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1285         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1286         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1287         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1288         IXGBE_WRITE_FLUSH(hw);
1289
1290         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1291                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1292                              (int) hw->mac.type, (int) hw->phy.type,
1293                              (int) hw->phy.sfp_type);
1294         else
1295                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1296                              (int) hw->mac.type, (int) hw->phy.type);
1297
1298         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1299                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1300                      pci_dev->id.device_id);
1301
1302         rte_intr_callback_register(intr_handle,
1303                                    ixgbe_dev_interrupt_handler, eth_dev);
1304
1305         /* enable uio/vfio intr/eventfd mapping */
1306         rte_intr_enable(intr_handle);
1307
1308         /* enable support intr */
1309         ixgbe_enable_intr(eth_dev);
1310
1311         /* initialize filter info */
1312         memset(filter_info, 0,
1313                sizeof(struct ixgbe_filter_info));
1314
1315         /* initialize 5tuple filter list */
1316         TAILQ_INIT(&filter_info->fivetuple_list);
1317
1318         /* initialize flow director filter list & hash */
1319         ixgbe_fdir_filter_init(eth_dev);
1320
1321         /* initialize l2 tunnel filter list & hash */
1322         ixgbe_l2_tn_filter_init(eth_dev);
1323
1324         /* initialize flow filter lists */
1325         ixgbe_filterlist_init();
1326
1327         /* initialize bandwidth configuration info */
1328         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1329
1330         /* initialize Traffic Manager configuration */
1331         ixgbe_tm_conf_init(eth_dev);
1332
1333         return 0;
1334 }
1335
1336 static int
1337 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1338 {
1339         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1340         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1341         struct ixgbe_hw *hw;
1342
1343         PMD_INIT_FUNC_TRACE();
1344
1345         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1346                 return -EPERM;
1347
1348         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1349
1350         if (hw->adapter_stopped == 0)
1351                 ixgbe_dev_close(eth_dev);
1352
1353         eth_dev->dev_ops = NULL;
1354         eth_dev->rx_pkt_burst = NULL;
1355         eth_dev->tx_pkt_burst = NULL;
1356
1357         /* Unlock any pending hardware semaphore */
1358         ixgbe_swfw_lock_reset(hw);
1359
1360         /* disable uio intr before callback unregister */
1361         rte_intr_disable(intr_handle);
1362         rte_intr_callback_unregister(intr_handle,
1363                                      ixgbe_dev_interrupt_handler, eth_dev);
1364
1365         /* uninitialize PF if max_vfs not zero */
1366         ixgbe_pf_host_uninit(eth_dev);
1367
1368         rte_free(eth_dev->data->mac_addrs);
1369         eth_dev->data->mac_addrs = NULL;
1370
1371         rte_free(eth_dev->data->hash_mac_addrs);
1372         eth_dev->data->hash_mac_addrs = NULL;
1373
1374         /* remove all the fdir filters & hash */
1375         ixgbe_fdir_filter_uninit(eth_dev);
1376
1377         /* remove all the L2 tunnel filters & hash */
1378         ixgbe_l2_tn_filter_uninit(eth_dev);
1379
1380         /* Remove all ntuple filters of the device */
1381         ixgbe_ntuple_filter_uninit(eth_dev);
1382
1383         /* clear all the filters list */
1384         ixgbe_filterlist_flush();
1385
1386         /* Remove all Traffic Manager configuration */
1387         ixgbe_tm_conf_uninit(eth_dev);
1388
1389 #ifdef RTE_LIBRTE_SECURITY
1390         rte_free(eth_dev->security_ctx);
1391 #endif
1392
1393         return 0;
1394 }
1395
1396 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1397 {
1398         struct ixgbe_filter_info *filter_info =
1399                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1400         struct ixgbe_5tuple_filter *p_5tuple;
1401
1402         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1403                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1404                              p_5tuple,
1405                              entries);
1406                 rte_free(p_5tuple);
1407         }
1408         memset(filter_info->fivetuple_mask, 0,
1409                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1410
1411         return 0;
1412 }
1413
1414 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1415 {
1416         struct ixgbe_hw_fdir_info *fdir_info =
1417                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1418         struct ixgbe_fdir_filter *fdir_filter;
1419
1420                 if (fdir_info->hash_map)
1421                 rte_free(fdir_info->hash_map);
1422         if (fdir_info->hash_handle)
1423                 rte_hash_free(fdir_info->hash_handle);
1424
1425         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1426                 TAILQ_REMOVE(&fdir_info->fdir_list,
1427                              fdir_filter,
1428                              entries);
1429                 rte_free(fdir_filter);
1430         }
1431
1432         return 0;
1433 }
1434
1435 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1436 {
1437         struct ixgbe_l2_tn_info *l2_tn_info =
1438                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1439         struct ixgbe_l2_tn_filter *l2_tn_filter;
1440
1441         if (l2_tn_info->hash_map)
1442                 rte_free(l2_tn_info->hash_map);
1443         if (l2_tn_info->hash_handle)
1444                 rte_hash_free(l2_tn_info->hash_handle);
1445
1446         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1447                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1448                              l2_tn_filter,
1449                              entries);
1450                 rte_free(l2_tn_filter);
1451         }
1452
1453         return 0;
1454 }
1455
1456 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1457 {
1458         struct ixgbe_hw_fdir_info *fdir_info =
1459                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1460         char fdir_hash_name[RTE_HASH_NAMESIZE];
1461         struct rte_hash_parameters fdir_hash_params = {
1462                 .name = fdir_hash_name,
1463                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1464                 .key_len = sizeof(union ixgbe_atr_input),
1465                 .hash_func = rte_hash_crc,
1466                 .hash_func_init_val = 0,
1467                 .socket_id = rte_socket_id(),
1468         };
1469
1470         TAILQ_INIT(&fdir_info->fdir_list);
1471         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1472                  "fdir_%s", eth_dev->device->name);
1473         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1474         if (!fdir_info->hash_handle) {
1475                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1476                 return -EINVAL;
1477         }
1478         fdir_info->hash_map = rte_zmalloc("ixgbe",
1479                                           sizeof(struct ixgbe_fdir_filter *) *
1480                                           IXGBE_MAX_FDIR_FILTER_NUM,
1481                                           0);
1482         if (!fdir_info->hash_map) {
1483                 PMD_INIT_LOG(ERR,
1484                              "Failed to allocate memory for fdir hash map!");
1485                 return -ENOMEM;
1486         }
1487         fdir_info->mask_added = FALSE;
1488
1489         return 0;
1490 }
1491
1492 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1493 {
1494         struct ixgbe_l2_tn_info *l2_tn_info =
1495                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1496         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1497         struct rte_hash_parameters l2_tn_hash_params = {
1498                 .name = l2_tn_hash_name,
1499                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1500                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1501                 .hash_func = rte_hash_crc,
1502                 .hash_func_init_val = 0,
1503                 .socket_id = rte_socket_id(),
1504         };
1505
1506         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1507         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1508                  "l2_tn_%s", eth_dev->device->name);
1509         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1510         if (!l2_tn_info->hash_handle) {
1511                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1512                 return -EINVAL;
1513         }
1514         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1515                                    sizeof(struct ixgbe_l2_tn_filter *) *
1516                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1517                                    0);
1518         if (!l2_tn_info->hash_map) {
1519                 PMD_INIT_LOG(ERR,
1520                         "Failed to allocate memory for L2 TN hash map!");
1521                 return -ENOMEM;
1522         }
1523         l2_tn_info->e_tag_en = FALSE;
1524         l2_tn_info->e_tag_fwd_en = FALSE;
1525         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1526
1527         return 0;
1528 }
1529 /*
1530  * Negotiate mailbox API version with the PF.
1531  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1532  * Then we try to negotiate starting with the most recent one.
1533  * If all negotiation attempts fail, then we will proceed with
1534  * the default one (ixgbe_mbox_api_10).
1535  */
1536 static void
1537 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1538 {
1539         int32_t i;
1540
1541         /* start with highest supported, proceed down */
1542         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1543                 ixgbe_mbox_api_12,
1544                 ixgbe_mbox_api_11,
1545                 ixgbe_mbox_api_10,
1546         };
1547
1548         for (i = 0;
1549                         i != RTE_DIM(sup_ver) &&
1550                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1551                         i++)
1552                 ;
1553 }
1554
1555 static void
1556 generate_random_mac_addr(struct ether_addr *mac_addr)
1557 {
1558         uint64_t random;
1559
1560         /* Set Organizationally Unique Identifier (OUI) prefix. */
1561         mac_addr->addr_bytes[0] = 0x00;
1562         mac_addr->addr_bytes[1] = 0x09;
1563         mac_addr->addr_bytes[2] = 0xC0;
1564         /* Force indication of locally assigned MAC address. */
1565         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1566         /* Generate the last 3 bytes of the MAC address with a random number. */
1567         random = rte_rand();
1568         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1569 }
1570
1571 /*
1572  * Virtual Function device init
1573  */
1574 static int
1575 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1576 {
1577         int diag;
1578         uint32_t tc, tcs;
1579         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1580         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1581         struct ixgbe_hw *hw =
1582                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1583         struct ixgbe_vfta *shadow_vfta =
1584                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1585         struct ixgbe_hwstrip *hwstrip =
1586                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1587         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1588
1589         PMD_INIT_FUNC_TRACE();
1590
1591         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1592         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1593         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1594
1595         /* for secondary processes, we don't initialise any further as primary
1596          * has already done this work. Only check we don't need a different
1597          * RX function
1598          */
1599         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1600                 struct ixgbe_tx_queue *txq;
1601                 /* TX queue function in primary, set by last queue initialized
1602                  * Tx queue may not initialized by primary process
1603                  */
1604                 if (eth_dev->data->tx_queues) {
1605                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1606                         ixgbe_set_tx_function(eth_dev, txq);
1607                 } else {
1608                         /* Use default TX function if we get here */
1609                         PMD_INIT_LOG(NOTICE,
1610                                      "No TX queues configured yet. Using default TX function.");
1611                 }
1612
1613                 ixgbe_set_rx_function(eth_dev);
1614
1615                 return 0;
1616         }
1617
1618         rte_eth_copy_pci_info(eth_dev, pci_dev);
1619
1620         hw->device_id = pci_dev->id.device_id;
1621         hw->vendor_id = pci_dev->id.vendor_id;
1622         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1623
1624         /* initialize the vfta */
1625         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1626
1627         /* initialize the hw strip bitmap*/
1628         memset(hwstrip, 0, sizeof(*hwstrip));
1629
1630         /* Initialize the shared code (base driver) */
1631         diag = ixgbe_init_shared_code(hw);
1632         if (diag != IXGBE_SUCCESS) {
1633                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1634                 return -EIO;
1635         }
1636
1637         /* init_mailbox_params */
1638         hw->mbx.ops.init_params(hw);
1639
1640         /* Reset the hw statistics */
1641         ixgbevf_dev_stats_reset(eth_dev);
1642
1643         /* Disable the interrupts for VF */
1644         ixgbevf_intr_disable(hw);
1645
1646         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1647         diag = hw->mac.ops.reset_hw(hw);
1648
1649         /*
1650          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1651          * the underlying PF driver has not assigned a MAC address to the VF.
1652          * In this case, assign a random MAC address.
1653          */
1654         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1655                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1656                 return diag;
1657         }
1658
1659         /* negotiate mailbox API version to use with the PF. */
1660         ixgbevf_negotiate_api(hw);
1661
1662         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1663         ixgbevf_get_queues(hw, &tcs, &tc);
1664
1665         /* Allocate memory for storing MAC addresses */
1666         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1667                                                hw->mac.num_rar_entries, 0);
1668         if (eth_dev->data->mac_addrs == NULL) {
1669                 PMD_INIT_LOG(ERR,
1670                              "Failed to allocate %u bytes needed to store "
1671                              "MAC addresses",
1672                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1673                 return -ENOMEM;
1674         }
1675
1676         /* Generate a random MAC address, if none was assigned by PF. */
1677         if (is_zero_ether_addr(perm_addr)) {
1678                 generate_random_mac_addr(perm_addr);
1679                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1680                 if (diag) {
1681                         rte_free(eth_dev->data->mac_addrs);
1682                         eth_dev->data->mac_addrs = NULL;
1683                         return diag;
1684                 }
1685                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1686                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1687                              "%02x:%02x:%02x:%02x:%02x:%02x",
1688                              perm_addr->addr_bytes[0],
1689                              perm_addr->addr_bytes[1],
1690                              perm_addr->addr_bytes[2],
1691                              perm_addr->addr_bytes[3],
1692                              perm_addr->addr_bytes[4],
1693                              perm_addr->addr_bytes[5]);
1694         }
1695
1696         /* Copy the permanent MAC address */
1697         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1698
1699         /* reset the hardware with the new settings */
1700         diag = hw->mac.ops.start_hw(hw);
1701         switch (diag) {
1702         case  0:
1703                 break;
1704
1705         default:
1706                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1707                 return -EIO;
1708         }
1709
1710         rte_intr_callback_register(intr_handle,
1711                                    ixgbevf_dev_interrupt_handler, eth_dev);
1712         rte_intr_enable(intr_handle);
1713         ixgbevf_intr_enable(hw);
1714
1715         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1716                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1717                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1718
1719         return 0;
1720 }
1721
1722 /* Virtual Function device uninit */
1723
1724 static int
1725 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1726 {
1727         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1728         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1729         struct ixgbe_hw *hw;
1730
1731         PMD_INIT_FUNC_TRACE();
1732
1733         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1734                 return -EPERM;
1735
1736         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1737
1738         if (hw->adapter_stopped == 0)
1739                 ixgbevf_dev_close(eth_dev);
1740
1741         eth_dev->dev_ops = NULL;
1742         eth_dev->rx_pkt_burst = NULL;
1743         eth_dev->tx_pkt_burst = NULL;
1744
1745         /* Disable the interrupts for VF */
1746         ixgbevf_intr_disable(hw);
1747
1748         rte_free(eth_dev->data->mac_addrs);
1749         eth_dev->data->mac_addrs = NULL;
1750
1751         rte_intr_disable(intr_handle);
1752         rte_intr_callback_unregister(intr_handle,
1753                                      ixgbevf_dev_interrupt_handler, eth_dev);
1754
1755         return 0;
1756 }
1757
1758 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1759         struct rte_pci_device *pci_dev)
1760 {
1761         return rte_eth_dev_pci_generic_probe(pci_dev,
1762                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1763 }
1764
1765 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1766 {
1767         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1768 }
1769
1770 static struct rte_pci_driver rte_ixgbe_pmd = {
1771         .id_table = pci_id_ixgbe_map,
1772         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1773                      RTE_PCI_DRV_IOVA_AS_VA,
1774         .probe = eth_ixgbe_pci_probe,
1775         .remove = eth_ixgbe_pci_remove,
1776 };
1777
1778 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1779         struct rte_pci_device *pci_dev)
1780 {
1781         return rte_eth_dev_pci_generic_probe(pci_dev,
1782                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1783 }
1784
1785 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1786 {
1787         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1788 }
1789
1790 /*
1791  * virtual function driver struct
1792  */
1793 static struct rte_pci_driver rte_ixgbevf_pmd = {
1794         .id_table = pci_id_ixgbevf_map,
1795         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1796         .probe = eth_ixgbevf_pci_probe,
1797         .remove = eth_ixgbevf_pci_remove,
1798 };
1799
1800 static int
1801 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1802 {
1803         struct ixgbe_hw *hw =
1804                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1805         struct ixgbe_vfta *shadow_vfta =
1806                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1807         uint32_t vfta;
1808         uint32_t vid_idx;
1809         uint32_t vid_bit;
1810
1811         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1812         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1813         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1814         if (on)
1815                 vfta |= vid_bit;
1816         else
1817                 vfta &= ~vid_bit;
1818         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1819
1820         /* update local VFTA copy */
1821         shadow_vfta->vfta[vid_idx] = vfta;
1822
1823         return 0;
1824 }
1825
1826 static void
1827 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1828 {
1829         if (on)
1830                 ixgbe_vlan_hw_strip_enable(dev, queue);
1831         else
1832                 ixgbe_vlan_hw_strip_disable(dev, queue);
1833 }
1834
1835 static int
1836 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1837                     enum rte_vlan_type vlan_type,
1838                     uint16_t tpid)
1839 {
1840         struct ixgbe_hw *hw =
1841                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842         int ret = 0;
1843         uint32_t reg;
1844         uint32_t qinq;
1845
1846         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1847         qinq &= IXGBE_DMATXCTL_GDV;
1848
1849         switch (vlan_type) {
1850         case ETH_VLAN_TYPE_INNER:
1851                 if (qinq) {
1852                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1853                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1854                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1855                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1856                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1857                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1858                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1859                 } else {
1860                         ret = -ENOTSUP;
1861                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1862                                     " by single VLAN");
1863                 }
1864                 break;
1865         case ETH_VLAN_TYPE_OUTER:
1866                 if (qinq) {
1867                         /* Only the high 16-bits is valid */
1868                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1869                                         IXGBE_EXVET_VET_EXT_SHIFT);
1870                 } else {
1871                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1872                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1873                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1874                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1875                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1876                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1877                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1878                 }
1879
1880                 break;
1881         default:
1882                 ret = -EINVAL;
1883                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1884                 break;
1885         }
1886
1887         return ret;
1888 }
1889
1890 void
1891 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1892 {
1893         struct ixgbe_hw *hw =
1894                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1895         uint32_t vlnctrl;
1896
1897         PMD_INIT_FUNC_TRACE();
1898
1899         /* Filter Table Disable */
1900         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1901         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1902
1903         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1904 }
1905
1906 void
1907 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1908 {
1909         struct ixgbe_hw *hw =
1910                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911         struct ixgbe_vfta *shadow_vfta =
1912                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1913         uint32_t vlnctrl;
1914         uint16_t i;
1915
1916         PMD_INIT_FUNC_TRACE();
1917
1918         /* Filter Table Enable */
1919         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1920         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1921         vlnctrl |= IXGBE_VLNCTRL_VFE;
1922
1923         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1924
1925         /* write whatever is in local vfta copy */
1926         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1927                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1928 }
1929
1930 static void
1931 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1932 {
1933         struct ixgbe_hwstrip *hwstrip =
1934                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1935         struct ixgbe_rx_queue *rxq;
1936
1937         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1938                 return;
1939
1940         if (on)
1941                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1942         else
1943                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1944
1945         if (queue >= dev->data->nb_rx_queues)
1946                 return;
1947
1948         rxq = dev->data->rx_queues[queue];
1949
1950         if (on)
1951                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1952         else
1953                 rxq->vlan_flags = PKT_RX_VLAN;
1954 }
1955
1956 static void
1957 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1958 {
1959         struct ixgbe_hw *hw =
1960                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961         uint32_t ctrl;
1962
1963         PMD_INIT_FUNC_TRACE();
1964
1965         if (hw->mac.type == ixgbe_mac_82598EB) {
1966                 /* No queue level support */
1967                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1968                 return;
1969         }
1970
1971         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1972         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1973         ctrl &= ~IXGBE_RXDCTL_VME;
1974         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1975
1976         /* record those setting for HW strip per queue */
1977         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1978 }
1979
1980 static void
1981 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1982 {
1983         struct ixgbe_hw *hw =
1984                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985         uint32_t ctrl;
1986
1987         PMD_INIT_FUNC_TRACE();
1988
1989         if (hw->mac.type == ixgbe_mac_82598EB) {
1990                 /* No queue level supported */
1991                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1992                 return;
1993         }
1994
1995         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1996         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1997         ctrl |= IXGBE_RXDCTL_VME;
1998         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1999
2000         /* record those setting for HW strip per queue */
2001         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2002 }
2003
2004 void
2005 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2006 {
2007         struct ixgbe_hw *hw =
2008                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009         uint32_t ctrl;
2010         uint16_t i;
2011         struct ixgbe_rx_queue *rxq;
2012
2013         PMD_INIT_FUNC_TRACE();
2014
2015         if (hw->mac.type == ixgbe_mac_82598EB) {
2016                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2017                 ctrl &= ~IXGBE_VLNCTRL_VME;
2018                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2019         } else {
2020                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2021                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2022                         rxq = dev->data->rx_queues[i];
2023                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2024                         ctrl &= ~IXGBE_RXDCTL_VME;
2025                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2026
2027                         /* record those setting for HW strip per queue */
2028                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2029                 }
2030         }
2031 }
2032
2033 void
2034 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2035 {
2036         struct ixgbe_hw *hw =
2037                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2038         uint32_t ctrl;
2039         uint16_t i;
2040         struct ixgbe_rx_queue *rxq;
2041
2042         PMD_INIT_FUNC_TRACE();
2043
2044         if (hw->mac.type == ixgbe_mac_82598EB) {
2045                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2046                 ctrl |= IXGBE_VLNCTRL_VME;
2047                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2048         } else {
2049                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2050                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2051                         rxq = dev->data->rx_queues[i];
2052                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2053                         ctrl |= IXGBE_RXDCTL_VME;
2054                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2055
2056                         /* record those setting for HW strip per queue */
2057                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2058                 }
2059         }
2060 }
2061
2062 static void
2063 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2064 {
2065         struct ixgbe_hw *hw =
2066                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067         uint32_t ctrl;
2068
2069         PMD_INIT_FUNC_TRACE();
2070
2071         /* DMATXCTRL: Geric Double VLAN Disable */
2072         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2073         ctrl &= ~IXGBE_DMATXCTL_GDV;
2074         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2075
2076         /* CTRL_EXT: Global Double VLAN Disable */
2077         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2078         ctrl &= ~IXGBE_EXTENDED_VLAN;
2079         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2080
2081 }
2082
2083 static void
2084 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2085 {
2086         struct ixgbe_hw *hw =
2087                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088         uint32_t ctrl;
2089
2090         PMD_INIT_FUNC_TRACE();
2091
2092         /* DMATXCTRL: Geric Double VLAN Enable */
2093         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2094         ctrl |= IXGBE_DMATXCTL_GDV;
2095         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2096
2097         /* CTRL_EXT: Global Double VLAN Enable */
2098         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2099         ctrl |= IXGBE_EXTENDED_VLAN;
2100         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2101
2102         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2103         if (hw->mac.type == ixgbe_mac_X550 ||
2104             hw->mac.type == ixgbe_mac_X550EM_x ||
2105             hw->mac.type == ixgbe_mac_X550EM_a) {
2106                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2107                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2108                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2109         }
2110
2111         /*
2112          * VET EXT field in the EXVET register = 0x8100 by default
2113          * So no need to change. Same to VT field of DMATXCTL register
2114          */
2115 }
2116
2117 static int
2118 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2119 {
2120         if (mask & ETH_VLAN_STRIP_MASK) {
2121                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2122                         ixgbe_vlan_hw_strip_enable_all(dev);
2123                 else
2124                         ixgbe_vlan_hw_strip_disable_all(dev);
2125         }
2126
2127         if (mask & ETH_VLAN_FILTER_MASK) {
2128                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2129                         ixgbe_vlan_hw_filter_enable(dev);
2130                 else
2131                         ixgbe_vlan_hw_filter_disable(dev);
2132         }
2133
2134         if (mask & ETH_VLAN_EXTEND_MASK) {
2135                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2136                         ixgbe_vlan_hw_extend_enable(dev);
2137                 else
2138                         ixgbe_vlan_hw_extend_disable(dev);
2139         }
2140
2141         return 0;
2142 }
2143
2144 static void
2145 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2146 {
2147         struct ixgbe_hw *hw =
2148                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2150         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2151
2152         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2153         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2154 }
2155
2156 static int
2157 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2158 {
2159         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2160
2161         switch (nb_rx_q) {
2162         case 1:
2163         case 2:
2164                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2165                 break;
2166         case 4:
2167                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2168                 break;
2169         default:
2170                 return -EINVAL;
2171         }
2172
2173         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2174                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2175         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2176                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2177         return 0;
2178 }
2179
2180 static int
2181 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2182 {
2183         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2186         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2187
2188         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2189                 /* check multi-queue mode */
2190                 switch (dev_conf->rxmode.mq_mode) {
2191                 case ETH_MQ_RX_VMDQ_DCB:
2192                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2193                         break;
2194                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2195                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2196                         PMD_INIT_LOG(ERR, "SRIOV active,"
2197                                         " unsupported mq_mode rx %d.",
2198                                         dev_conf->rxmode.mq_mode);
2199                         return -EINVAL;
2200                 case ETH_MQ_RX_RSS:
2201                 case ETH_MQ_RX_VMDQ_RSS:
2202                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2203                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2204                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2205                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2206                                                 " invalid queue number"
2207                                                 " for VMDQ RSS, allowed"
2208                                                 " value are 1, 2 or 4.");
2209                                         return -EINVAL;
2210                                 }
2211                         break;
2212                 case ETH_MQ_RX_VMDQ_ONLY:
2213                 case ETH_MQ_RX_NONE:
2214                         /* if nothing mq mode configure, use default scheme */
2215                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2216                         break;
2217                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2218                         /* SRIOV only works in VMDq enable mode */
2219                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2220                                         " wrong mq_mode rx %d.",
2221                                         dev_conf->rxmode.mq_mode);
2222                         return -EINVAL;
2223                 }
2224
2225                 switch (dev_conf->txmode.mq_mode) {
2226                 case ETH_MQ_TX_VMDQ_DCB:
2227                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2228                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2229                         break;
2230                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2231                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2232                         break;
2233                 }
2234
2235                 /* check valid queue number */
2236                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2237                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2238                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2239                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2240                                         " must be less than or equal to %d.",
2241                                         nb_rx_q, nb_tx_q,
2242                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2243                         return -EINVAL;
2244                 }
2245         } else {
2246                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2247                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2248                                           " not supported.");
2249                         return -EINVAL;
2250                 }
2251                 /* check configuration for vmdb+dcb mode */
2252                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2253                         const struct rte_eth_vmdq_dcb_conf *conf;
2254
2255                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2256                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2257                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2258                                 return -EINVAL;
2259                         }
2260                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2261                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2262                                conf->nb_queue_pools == ETH_32_POOLS)) {
2263                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2264                                                 " nb_queue_pools must be %d or %d.",
2265                                                 ETH_16_POOLS, ETH_32_POOLS);
2266                                 return -EINVAL;
2267                         }
2268                 }
2269                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2270                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2271
2272                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2273                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2274                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2275                                 return -EINVAL;
2276                         }
2277                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2278                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2279                                conf->nb_queue_pools == ETH_32_POOLS)) {
2280                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2281                                                 " nb_queue_pools != %d and"
2282                                                 " nb_queue_pools != %d.",
2283                                                 ETH_16_POOLS, ETH_32_POOLS);
2284                                 return -EINVAL;
2285                         }
2286                 }
2287
2288                 /* For DCB mode check our configuration before we go further */
2289                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2290                         const struct rte_eth_dcb_rx_conf *conf;
2291
2292                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2293                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2294                                                  IXGBE_DCB_NB_QUEUES);
2295                                 return -EINVAL;
2296                         }
2297                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2298                         if (!(conf->nb_tcs == ETH_4_TCS ||
2299                                conf->nb_tcs == ETH_8_TCS)) {
2300                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2301                                                 " and nb_tcs != %d.",
2302                                                 ETH_4_TCS, ETH_8_TCS);
2303                                 return -EINVAL;
2304                         }
2305                 }
2306
2307                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2308                         const struct rte_eth_dcb_tx_conf *conf;
2309
2310                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2311                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2312                                                  IXGBE_DCB_NB_QUEUES);
2313                                 return -EINVAL;
2314                         }
2315                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2316                         if (!(conf->nb_tcs == ETH_4_TCS ||
2317                                conf->nb_tcs == ETH_8_TCS)) {
2318                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2319                                                 " and nb_tcs != %d.",
2320                                                 ETH_4_TCS, ETH_8_TCS);
2321                                 return -EINVAL;
2322                         }
2323                 }
2324
2325                 /*
2326                  * When DCB/VT is off, maximum number of queues changes,
2327                  * except for 82598EB, which remains constant.
2328                  */
2329                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2330                                 hw->mac.type != ixgbe_mac_82598EB) {
2331                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2332                                 PMD_INIT_LOG(ERR,
2333                                              "Neither VT nor DCB are enabled, "
2334                                              "nb_tx_q > %d.",
2335                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2336                                 return -EINVAL;
2337                         }
2338                 }
2339         }
2340         return 0;
2341 }
2342
2343 static int
2344 ixgbe_dev_configure(struct rte_eth_dev *dev)
2345 {
2346         struct ixgbe_interrupt *intr =
2347                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2348         struct ixgbe_adapter *adapter =
2349                 (struct ixgbe_adapter *)dev->data->dev_private;
2350         int ret;
2351
2352         PMD_INIT_FUNC_TRACE();
2353         /* multipe queue mode checking */
2354         ret  = ixgbe_check_mq_mode(dev);
2355         if (ret != 0) {
2356                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2357                             ret);
2358                 return ret;
2359         }
2360
2361         /* set flag to update link status after init */
2362         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2363
2364         /*
2365          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2366          * allocation or vector Rx preconditions we will reset it.
2367          */
2368         adapter->rx_bulk_alloc_allowed = true;
2369         adapter->rx_vec_allowed = true;
2370
2371         return 0;
2372 }
2373
2374 static void
2375 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2376 {
2377         struct ixgbe_hw *hw =
2378                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379         struct ixgbe_interrupt *intr =
2380                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2381         uint32_t gpie;
2382
2383         /* only set up it on X550EM_X */
2384         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2385                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2386                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2387                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2388                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2389                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2390         }
2391 }
2392
2393 int
2394 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2395                         uint16_t tx_rate, uint64_t q_msk)
2396 {
2397         struct ixgbe_hw *hw;
2398         struct ixgbe_vf_info *vfinfo;
2399         struct rte_eth_link link;
2400         uint8_t  nb_q_per_pool;
2401         uint32_t queue_stride;
2402         uint32_t queue_idx, idx = 0, vf_idx;
2403         uint32_t queue_end;
2404         uint16_t total_rate = 0;
2405         struct rte_pci_device *pci_dev;
2406
2407         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2408         rte_eth_link_get_nowait(dev->data->port_id, &link);
2409
2410         if (vf >= pci_dev->max_vfs)
2411                 return -EINVAL;
2412
2413         if (tx_rate > link.link_speed)
2414                 return -EINVAL;
2415
2416         if (q_msk == 0)
2417                 return 0;
2418
2419         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2420         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2421         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2422         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2423         queue_idx = vf * queue_stride;
2424         queue_end = queue_idx + nb_q_per_pool - 1;
2425         if (queue_end >= hw->mac.max_tx_queues)
2426                 return -EINVAL;
2427
2428         if (vfinfo) {
2429                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2430                         if (vf_idx == vf)
2431                                 continue;
2432                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2433                                 idx++)
2434                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2435                 }
2436         } else {
2437                 return -EINVAL;
2438         }
2439
2440         /* Store tx_rate for this vf. */
2441         for (idx = 0; idx < nb_q_per_pool; idx++) {
2442                 if (((uint64_t)0x1 << idx) & q_msk) {
2443                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2444                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2445                         total_rate += tx_rate;
2446                 }
2447         }
2448
2449         if (total_rate > dev->data->dev_link.link_speed) {
2450                 /* Reset stored TX rate of the VF if it causes exceed
2451                  * link speed.
2452                  */
2453                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2454                 return -EINVAL;
2455         }
2456
2457         /* Set RTTBCNRC of each queue/pool for vf X  */
2458         for (; queue_idx <= queue_end; queue_idx++) {
2459                 if (0x1 & q_msk)
2460                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2461                 q_msk = q_msk >> 1;
2462         }
2463
2464         return 0;
2465 }
2466
2467 /*
2468  * Configure device link speed and setup link.
2469  * It returns 0 on success.
2470  */
2471 static int
2472 ixgbe_dev_start(struct rte_eth_dev *dev)
2473 {
2474         struct ixgbe_hw *hw =
2475                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476         struct ixgbe_vf_info *vfinfo =
2477                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2478         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2479         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2480         uint32_t intr_vector = 0;
2481         int err, link_up = 0, negotiate = 0;
2482         uint32_t speed = 0;
2483         int mask = 0;
2484         int status;
2485         uint16_t vf, idx;
2486         uint32_t *link_speeds;
2487         struct ixgbe_tm_conf *tm_conf =
2488                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2489
2490         PMD_INIT_FUNC_TRACE();
2491
2492         /* IXGBE devices don't support:
2493         *    - half duplex (checked afterwards for valid speeds)
2494         *    - fixed speed: TODO implement
2495         */
2496         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2497                 PMD_INIT_LOG(ERR,
2498                 "Invalid link_speeds for port %u, fix speed not supported",
2499                                 dev->data->port_id);
2500                 return -EINVAL;
2501         }
2502
2503         /* disable uio/vfio intr/eventfd mapping */
2504         rte_intr_disable(intr_handle);
2505
2506         /* stop adapter */
2507         hw->adapter_stopped = 0;
2508         ixgbe_stop_adapter(hw);
2509
2510         /* reinitialize adapter
2511          * this calls reset and start
2512          */
2513         status = ixgbe_pf_reset_hw(hw);
2514         if (status != 0)
2515                 return -1;
2516         hw->mac.ops.start_hw(hw);
2517         hw->mac.get_link_status = true;
2518
2519         /* configure PF module if SRIOV enabled */
2520         ixgbe_pf_host_configure(dev);
2521
2522         ixgbe_dev_phy_intr_setup(dev);
2523
2524         /* check and configure queue intr-vector mapping */
2525         if ((rte_intr_cap_multiple(intr_handle) ||
2526              !RTE_ETH_DEV_SRIOV(dev).active) &&
2527             dev->data->dev_conf.intr_conf.rxq != 0) {
2528                 intr_vector = dev->data->nb_rx_queues;
2529                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2530                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2531                                         IXGBE_MAX_INTR_QUEUE_NUM);
2532                         return -ENOTSUP;
2533                 }
2534                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2535                         return -1;
2536         }
2537
2538         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2539                 intr_handle->intr_vec =
2540                         rte_zmalloc("intr_vec",
2541                                     dev->data->nb_rx_queues * sizeof(int), 0);
2542                 if (intr_handle->intr_vec == NULL) {
2543                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2544                                      " intr_vec", dev->data->nb_rx_queues);
2545                         return -ENOMEM;
2546                 }
2547         }
2548
2549         /* confiugre msix for sleep until rx interrupt */
2550         ixgbe_configure_msix(dev);
2551
2552         /* initialize transmission unit */
2553         ixgbe_dev_tx_init(dev);
2554
2555         /* This can fail when allocating mbufs for descriptor rings */
2556         err = ixgbe_dev_rx_init(dev);
2557         if (err) {
2558                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2559                 goto error;
2560         }
2561
2562         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2563                 ETH_VLAN_EXTEND_MASK;
2564         err = ixgbe_vlan_offload_set(dev, mask);
2565         if (err) {
2566                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2567                 goto error;
2568         }
2569
2570         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2571                 /* Enable vlan filtering for VMDq */
2572                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2573         }
2574
2575         /* Configure DCB hw */
2576         ixgbe_configure_dcb(dev);
2577
2578         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2579                 err = ixgbe_fdir_configure(dev);
2580                 if (err)
2581                         goto error;
2582         }
2583
2584         /* Restore vf rate limit */
2585         if (vfinfo != NULL) {
2586                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2587                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2588                                 if (vfinfo[vf].tx_rate[idx] != 0)
2589                                         ixgbe_set_vf_rate_limit(
2590                                                 dev, vf,
2591                                                 vfinfo[vf].tx_rate[idx],
2592                                                 1 << idx);
2593         }
2594
2595         ixgbe_restore_statistics_mapping(dev);
2596
2597         err = ixgbe_dev_rxtx_start(dev);
2598         if (err < 0) {
2599                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2600                 goto error;
2601         }
2602
2603         /* Skip link setup if loopback mode is enabled for 82599. */
2604         if (hw->mac.type == ixgbe_mac_82599EB &&
2605                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2606                 goto skip_link_setup;
2607
2608         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2609                 err = hw->mac.ops.setup_sfp(hw);
2610                 if (err)
2611                         goto error;
2612         }
2613
2614         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2615                 /* Turn on the copper */
2616                 ixgbe_set_phy_power(hw, true);
2617         } else {
2618                 /* Turn on the laser */
2619                 ixgbe_enable_tx_laser(hw);
2620         }
2621
2622         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2623         if (err)
2624                 goto error;
2625         dev->data->dev_link.link_status = link_up;
2626
2627         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2628         if (err)
2629                 goto error;
2630
2631         link_speeds = &dev->data->dev_conf.link_speeds;
2632         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2633                         ETH_LINK_SPEED_10G)) {
2634                 PMD_INIT_LOG(ERR, "Invalid link setting");
2635                 goto error;
2636         }
2637
2638         speed = 0x0;
2639         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2640                 switch (hw->mac.type) {
2641                 case ixgbe_mac_82598EB:
2642                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2643                         break;
2644                 case ixgbe_mac_82599EB:
2645                 case ixgbe_mac_X540:
2646                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2647                         break;
2648                 case ixgbe_mac_X550:
2649                 case ixgbe_mac_X550EM_x:
2650                 case ixgbe_mac_X550EM_a:
2651                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2652                         break;
2653                 default:
2654                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2655                 }
2656         } else {
2657                 if (*link_speeds & ETH_LINK_SPEED_10G)
2658                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2659                 if (*link_speeds & ETH_LINK_SPEED_1G)
2660                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2661                 if (*link_speeds & ETH_LINK_SPEED_100M)
2662                         speed |= IXGBE_LINK_SPEED_100_FULL;
2663         }
2664
2665         err = ixgbe_setup_link(hw, speed, link_up);
2666         if (err)
2667                 goto error;
2668
2669 skip_link_setup:
2670
2671         if (rte_intr_allow_others(intr_handle)) {
2672                 /* check if lsc interrupt is enabled */
2673                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2674                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2675                 else
2676                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2677                 ixgbe_dev_macsec_interrupt_setup(dev);
2678         } else {
2679                 rte_intr_callback_unregister(intr_handle,
2680                                              ixgbe_dev_interrupt_handler, dev);
2681                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2682                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2683                                      " no intr multiplex");
2684         }
2685
2686         /* check if rxq interrupt is enabled */
2687         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2688             rte_intr_dp_is_en(intr_handle))
2689                 ixgbe_dev_rxq_interrupt_setup(dev);
2690
2691         /* enable uio/vfio intr/eventfd mapping */
2692         rte_intr_enable(intr_handle);
2693
2694         /* resume enabled intr since hw reset */
2695         ixgbe_enable_intr(dev);
2696         ixgbe_l2_tunnel_conf(dev);
2697         ixgbe_filter_restore(dev);
2698
2699         if (tm_conf->root && !tm_conf->committed)
2700                 PMD_DRV_LOG(WARNING,
2701                             "please call hierarchy_commit() "
2702                             "before starting the port");
2703
2704         return 0;
2705
2706 error:
2707         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2708         ixgbe_dev_clear_queues(dev);
2709         return -EIO;
2710 }
2711
2712 /*
2713  * Stop device: disable rx and tx functions to allow for reconfiguring.
2714  */
2715 static void
2716 ixgbe_dev_stop(struct rte_eth_dev *dev)
2717 {
2718         struct rte_eth_link link;
2719         struct ixgbe_hw *hw =
2720                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2721         struct ixgbe_vf_info *vfinfo =
2722                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2723         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2724         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2725         int vf;
2726         struct ixgbe_tm_conf *tm_conf =
2727                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2728
2729         PMD_INIT_FUNC_TRACE();
2730
2731         /* disable interrupts */
2732         ixgbe_disable_intr(hw);
2733
2734         /* reset the NIC */
2735         ixgbe_pf_reset_hw(hw);
2736         hw->adapter_stopped = 0;
2737
2738         /* stop adapter */
2739         ixgbe_stop_adapter(hw);
2740
2741         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2742                 vfinfo[vf].clear_to_send = false;
2743
2744         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2745                 /* Turn off the copper */
2746                 ixgbe_set_phy_power(hw, false);
2747         } else {
2748                 /* Turn off the laser */
2749                 ixgbe_disable_tx_laser(hw);
2750         }
2751
2752         ixgbe_dev_clear_queues(dev);
2753
2754         /* Clear stored conf */
2755         dev->data->scattered_rx = 0;
2756         dev->data->lro = 0;
2757
2758         /* Clear recorded link status */
2759         memset(&link, 0, sizeof(link));
2760         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2761
2762         if (!rte_intr_allow_others(intr_handle))
2763                 /* resume to the default handler */
2764                 rte_intr_callback_register(intr_handle,
2765                                            ixgbe_dev_interrupt_handler,
2766                                            (void *)dev);
2767
2768         /* Clean datapath event and queue/vec mapping */
2769         rte_intr_efd_disable(intr_handle);
2770         if (intr_handle->intr_vec != NULL) {
2771                 rte_free(intr_handle->intr_vec);
2772                 intr_handle->intr_vec = NULL;
2773         }
2774
2775         /* reset hierarchy commit */
2776         tm_conf->committed = false;
2777 }
2778
2779 /*
2780  * Set device link up: enable tx.
2781  */
2782 static int
2783 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2784 {
2785         struct ixgbe_hw *hw =
2786                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2787         if (hw->mac.type == ixgbe_mac_82599EB) {
2788 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2789                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2790                         /* Not suported in bypass mode */
2791                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2792                                      "by device id 0x%x", hw->device_id);
2793                         return -ENOTSUP;
2794                 }
2795 #endif
2796         }
2797
2798         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2799                 /* Turn on the copper */
2800                 ixgbe_set_phy_power(hw, true);
2801         } else {
2802                 /* Turn on the laser */
2803                 ixgbe_enable_tx_laser(hw);
2804         }
2805
2806         return 0;
2807 }
2808
2809 /*
2810  * Set device link down: disable tx.
2811  */
2812 static int
2813 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2814 {
2815         struct ixgbe_hw *hw =
2816                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817         if (hw->mac.type == ixgbe_mac_82599EB) {
2818 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2819                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2820                         /* Not suported in bypass mode */
2821                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2822                                      "by device id 0x%x", hw->device_id);
2823                         return -ENOTSUP;
2824                 }
2825 #endif
2826         }
2827
2828         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2829                 /* Turn off the copper */
2830                 ixgbe_set_phy_power(hw, false);
2831         } else {
2832                 /* Turn off the laser */
2833                 ixgbe_disable_tx_laser(hw);
2834         }
2835
2836         return 0;
2837 }
2838
2839 /*
2840  * Reset and stop device.
2841  */
2842 static void
2843 ixgbe_dev_close(struct rte_eth_dev *dev)
2844 {
2845         struct ixgbe_hw *hw =
2846                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847
2848         PMD_INIT_FUNC_TRACE();
2849
2850         ixgbe_pf_reset_hw(hw);
2851
2852         ixgbe_dev_stop(dev);
2853         hw->adapter_stopped = 1;
2854
2855         ixgbe_dev_free_queues(dev);
2856
2857         ixgbe_disable_pcie_master(hw);
2858
2859         /* reprogram the RAR[0] in case user changed it. */
2860         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2861 }
2862
2863 /*
2864  * Reset PF device.
2865  */
2866 static int
2867 ixgbe_dev_reset(struct rte_eth_dev *dev)
2868 {
2869         int ret;
2870
2871         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2872          * its VF to make them align with it. The detailed notification
2873          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2874          * To avoid unexpected behavior in VF, currently reset of PF with
2875          * SR-IOV activation is not supported. It might be supported later.
2876          */
2877         if (dev->data->sriov.active)
2878                 return -ENOTSUP;
2879
2880         ret = eth_ixgbe_dev_uninit(dev);
2881         if (ret)
2882                 return ret;
2883
2884         ret = eth_ixgbe_dev_init(dev);
2885
2886         return ret;
2887 }
2888
2889 static void
2890 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2891                            struct ixgbe_hw_stats *hw_stats,
2892                            struct ixgbe_macsec_stats *macsec_stats,
2893                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2894                            uint64_t *total_qprc, uint64_t *total_qprdc)
2895 {
2896         uint32_t bprc, lxon, lxoff, total;
2897         uint32_t delta_gprc = 0;
2898         unsigned i;
2899         /* Workaround for RX byte count not including CRC bytes when CRC
2900          * strip is enabled. CRC bytes are removed from counters when crc_strip
2901          * is disabled.
2902          */
2903         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2904                         IXGBE_HLREG0_RXCRCSTRP);
2905
2906         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2907         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2908         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2909         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2910
2911         for (i = 0; i < 8; i++) {
2912                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2913
2914                 /* global total per queue */
2915                 hw_stats->mpc[i] += mp;
2916                 /* Running comprehensive total for stats display */
2917                 *total_missed_rx += hw_stats->mpc[i];
2918                 if (hw->mac.type == ixgbe_mac_82598EB) {
2919                         hw_stats->rnbc[i] +=
2920                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2921                         hw_stats->pxonrxc[i] +=
2922                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2923                         hw_stats->pxoffrxc[i] +=
2924                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2925                 } else {
2926                         hw_stats->pxonrxc[i] +=
2927                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2928                         hw_stats->pxoffrxc[i] +=
2929                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2930                         hw_stats->pxon2offc[i] +=
2931                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2932                 }
2933                 hw_stats->pxontxc[i] +=
2934                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2935                 hw_stats->pxofftxc[i] +=
2936                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2937         }
2938         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2939                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2940                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2941                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2942
2943                 delta_gprc += delta_qprc;
2944
2945                 hw_stats->qprc[i] += delta_qprc;
2946                 hw_stats->qptc[i] += delta_qptc;
2947
2948                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2949                 hw_stats->qbrc[i] +=
2950                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2951                 if (crc_strip == 0)
2952                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2953
2954                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2955                 hw_stats->qbtc[i] +=
2956                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2957
2958                 hw_stats->qprdc[i] += delta_qprdc;
2959                 *total_qprdc += hw_stats->qprdc[i];
2960
2961                 *total_qprc += hw_stats->qprc[i];
2962                 *total_qbrc += hw_stats->qbrc[i];
2963         }
2964         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2965         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2966         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2967
2968         /*
2969          * An errata states that gprc actually counts good + missed packets:
2970          * Workaround to set gprc to summated queue packet receives
2971          */
2972         hw_stats->gprc = *total_qprc;
2973
2974         if (hw->mac.type != ixgbe_mac_82598EB) {
2975                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2976                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2977                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2978                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2979                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2980                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2981                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2982                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2983         } else {
2984                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2985                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2986                 /* 82598 only has a counter in the high register */
2987                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2988                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2989                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2990         }
2991         uint64_t old_tpr = hw_stats->tpr;
2992
2993         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2994         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2995
2996         if (crc_strip == 0)
2997                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2998
2999         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3000         hw_stats->gptc += delta_gptc;
3001         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3002         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3003
3004         /*
3005          * Workaround: mprc hardware is incorrectly counting
3006          * broadcasts, so for now we subtract those.
3007          */
3008         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3009         hw_stats->bprc += bprc;
3010         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3011         if (hw->mac.type == ixgbe_mac_82598EB)
3012                 hw_stats->mprc -= bprc;
3013
3014         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3015         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3016         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3017         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3018         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3019         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3020
3021         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3022         hw_stats->lxontxc += lxon;
3023         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3024         hw_stats->lxofftxc += lxoff;
3025         total = lxon + lxoff;
3026
3027         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3028         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3029         hw_stats->gptc -= total;
3030         hw_stats->mptc -= total;
3031         hw_stats->ptc64 -= total;
3032         hw_stats->gotc -= total * ETHER_MIN_LEN;
3033
3034         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3035         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3036         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3037         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3038         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3039         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3040         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3041         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3042         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3043         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3044         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3045         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3046         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3047         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3048         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3049         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3050         /* Only read FCOE on 82599 */
3051         if (hw->mac.type != ixgbe_mac_82598EB) {
3052                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3053                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3054                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3055                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3056                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3057         }
3058
3059         /* Flow Director Stats registers */
3060         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3061         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3062
3063         /* MACsec Stats registers */
3064         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3065         macsec_stats->out_pkts_encrypted +=
3066                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3067         macsec_stats->out_pkts_protected +=
3068                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3069         macsec_stats->out_octets_encrypted +=
3070                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3071         macsec_stats->out_octets_protected +=
3072                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3073         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3074         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3075         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3076         macsec_stats->in_pkts_unknownsci +=
3077                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3078         macsec_stats->in_octets_decrypted +=
3079                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3080         macsec_stats->in_octets_validated +=
3081                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3082         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3083         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3084         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3085         for (i = 0; i < 2; i++) {
3086                 macsec_stats->in_pkts_ok +=
3087                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3088                 macsec_stats->in_pkts_invalid +=
3089                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3090                 macsec_stats->in_pkts_notvalid +=
3091                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3092         }
3093         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3094         macsec_stats->in_pkts_notusingsa +=
3095                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3096 }
3097
3098 /*
3099  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3100  */
3101 static int
3102 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3103 {
3104         struct ixgbe_hw *hw =
3105                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3106         struct ixgbe_hw_stats *hw_stats =
3107                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3108         struct ixgbe_macsec_stats *macsec_stats =
3109                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3110                                 dev->data->dev_private);
3111         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3112         unsigned i;
3113
3114         total_missed_rx = 0;
3115         total_qbrc = 0;
3116         total_qprc = 0;
3117         total_qprdc = 0;
3118
3119         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3120                         &total_qbrc, &total_qprc, &total_qprdc);
3121
3122         if (stats == NULL)
3123                 return -EINVAL;
3124
3125         /* Fill out the rte_eth_stats statistics structure */
3126         stats->ipackets = total_qprc;
3127         stats->ibytes = total_qbrc;
3128         stats->opackets = hw_stats->gptc;
3129         stats->obytes = hw_stats->gotc;
3130
3131         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3132                 stats->q_ipackets[i] = hw_stats->qprc[i];
3133                 stats->q_opackets[i] = hw_stats->qptc[i];
3134                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3135                 stats->q_obytes[i] = hw_stats->qbtc[i];
3136                 stats->q_errors[i] = hw_stats->qprdc[i];
3137         }
3138
3139         /* Rx Errors */
3140         stats->imissed  = total_missed_rx;
3141         stats->ierrors  = hw_stats->crcerrs +
3142                           hw_stats->mspdc +
3143                           hw_stats->rlec +
3144                           hw_stats->ruc +
3145                           hw_stats->roc +
3146                           hw_stats->illerrc +
3147                           hw_stats->errbc +
3148                           hw_stats->rfc +
3149                           hw_stats->fccrc +
3150                           hw_stats->fclast;
3151
3152         /* Tx Errors */
3153         stats->oerrors  = 0;
3154         return 0;
3155 }
3156
3157 static void
3158 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3159 {
3160         struct ixgbe_hw_stats *stats =
3161                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3162
3163         /* HW registers are cleared on read */
3164         ixgbe_dev_stats_get(dev, NULL);
3165
3166         /* Reset software totals */
3167         memset(stats, 0, sizeof(*stats));
3168 }
3169
3170 /* This function calculates the number of xstats based on the current config */
3171 static unsigned
3172 ixgbe_xstats_calc_num(void) {
3173         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3174                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3175                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3176 }
3177
3178 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3179         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3180 {
3181         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3182         unsigned stat, i, count;
3183
3184         if (xstats_names != NULL) {
3185                 count = 0;
3186
3187                 /* Note: limit >= cnt_stats checked upstream
3188                  * in rte_eth_xstats_names()
3189                  */
3190
3191                 /* Extended stats from ixgbe_hw_stats */
3192                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3193                         snprintf(xstats_names[count].name,
3194                                 sizeof(xstats_names[count].name),
3195                                 "%s",
3196                                 rte_ixgbe_stats_strings[i].name);
3197                         count++;
3198                 }
3199
3200                 /* MACsec Stats */
3201                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3202                         snprintf(xstats_names[count].name,
3203                                 sizeof(xstats_names[count].name),
3204                                 "%s",
3205                                 rte_ixgbe_macsec_strings[i].name);
3206                         count++;
3207                 }
3208
3209                 /* RX Priority Stats */
3210                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3211                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3212                                 snprintf(xstats_names[count].name,
3213                                         sizeof(xstats_names[count].name),
3214                                         "rx_priority%u_%s", i,
3215                                         rte_ixgbe_rxq_strings[stat].name);
3216                                 count++;
3217                         }
3218                 }
3219
3220                 /* TX Priority Stats */
3221                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3222                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3223                                 snprintf(xstats_names[count].name,
3224                                         sizeof(xstats_names[count].name),
3225                                         "tx_priority%u_%s", i,
3226                                         rte_ixgbe_txq_strings[stat].name);
3227                                 count++;
3228                         }
3229                 }
3230         }
3231         return cnt_stats;
3232 }
3233
3234 static int ixgbe_dev_xstats_get_names_by_id(
3235         struct rte_eth_dev *dev,
3236         struct rte_eth_xstat_name *xstats_names,
3237         const uint64_t *ids,
3238         unsigned int limit)
3239 {
3240         if (!ids) {
3241                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3242                 unsigned int stat, i, count;
3243
3244                 if (xstats_names != NULL) {
3245                         count = 0;
3246
3247                         /* Note: limit >= cnt_stats checked upstream
3248                          * in rte_eth_xstats_names()
3249                          */
3250
3251                         /* Extended stats from ixgbe_hw_stats */
3252                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3253                                 snprintf(xstats_names[count].name,
3254                                         sizeof(xstats_names[count].name),
3255                                         "%s",
3256                                         rte_ixgbe_stats_strings[i].name);
3257                                 count++;
3258                         }
3259
3260                         /* MACsec Stats */
3261                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3262                                 snprintf(xstats_names[count].name,
3263                                         sizeof(xstats_names[count].name),
3264                                         "%s",
3265                                         rte_ixgbe_macsec_strings[i].name);
3266                                 count++;
3267                         }
3268
3269                         /* RX Priority Stats */
3270                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3271                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3272                                         snprintf(xstats_names[count].name,
3273                                             sizeof(xstats_names[count].name),
3274                                             "rx_priority%u_%s", i,
3275                                             rte_ixgbe_rxq_strings[stat].name);
3276                                         count++;
3277                                 }
3278                         }
3279
3280                         /* TX Priority Stats */
3281                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3282                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3283                                         snprintf(xstats_names[count].name,
3284                                             sizeof(xstats_names[count].name),
3285                                             "tx_priority%u_%s", i,
3286                                             rte_ixgbe_txq_strings[stat].name);
3287                                         count++;
3288                                 }
3289                         }
3290                 }
3291                 return cnt_stats;
3292         }
3293
3294         uint16_t i;
3295         uint16_t size = ixgbe_xstats_calc_num();
3296         struct rte_eth_xstat_name xstats_names_copy[size];
3297
3298         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3299                         size);
3300
3301         for (i = 0; i < limit; i++) {
3302                 if (ids[i] >= size) {
3303                         PMD_INIT_LOG(ERR, "id value isn't valid");
3304                         return -1;
3305                 }
3306                 strcpy(xstats_names[i].name,
3307                                 xstats_names_copy[ids[i]].name);
3308         }
3309         return limit;
3310 }
3311
3312 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3313         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3314 {
3315         unsigned i;
3316
3317         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3318                 return -ENOMEM;
3319
3320         if (xstats_names != NULL)
3321                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3322                         snprintf(xstats_names[i].name,
3323                                 sizeof(xstats_names[i].name),
3324                                 "%s", rte_ixgbevf_stats_strings[i].name);
3325         return IXGBEVF_NB_XSTATS;
3326 }
3327
3328 static int
3329 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3330                                          unsigned n)
3331 {
3332         struct ixgbe_hw *hw =
3333                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3334         struct ixgbe_hw_stats *hw_stats =
3335                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3336         struct ixgbe_macsec_stats *macsec_stats =
3337                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3338                                 dev->data->dev_private);
3339         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3340         unsigned i, stat, count = 0;
3341
3342         count = ixgbe_xstats_calc_num();
3343
3344         if (n < count)
3345                 return count;
3346
3347         total_missed_rx = 0;
3348         total_qbrc = 0;
3349         total_qprc = 0;
3350         total_qprdc = 0;
3351
3352         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3353                         &total_qbrc, &total_qprc, &total_qprdc);
3354
3355         /* If this is a reset xstats is NULL, and we have cleared the
3356          * registers by reading them.
3357          */
3358         if (!xstats)
3359                 return 0;
3360
3361         /* Extended stats from ixgbe_hw_stats */
3362         count = 0;
3363         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3364                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3365                                 rte_ixgbe_stats_strings[i].offset);
3366                 xstats[count].id = count;
3367                 count++;
3368         }
3369
3370         /* MACsec Stats */
3371         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3372                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3373                                 rte_ixgbe_macsec_strings[i].offset);
3374                 xstats[count].id = count;
3375                 count++;
3376         }
3377
3378         /* RX Priority Stats */
3379         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3380                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3381                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3382                                         rte_ixgbe_rxq_strings[stat].offset +
3383                                         (sizeof(uint64_t) * i));
3384                         xstats[count].id = count;
3385                         count++;
3386                 }
3387         }
3388
3389         /* TX Priority Stats */
3390         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3391                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3392                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3393                                         rte_ixgbe_txq_strings[stat].offset +
3394                                         (sizeof(uint64_t) * i));
3395                         xstats[count].id = count;
3396                         count++;
3397                 }
3398         }
3399         return count;
3400 }
3401
3402 static int
3403 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3404                 uint64_t *values, unsigned int n)
3405 {
3406         if (!ids) {
3407                 struct ixgbe_hw *hw =
3408                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3409                 struct ixgbe_hw_stats *hw_stats =
3410                                 IXGBE_DEV_PRIVATE_TO_STATS(
3411                                                 dev->data->dev_private);
3412                 struct ixgbe_macsec_stats *macsec_stats =
3413                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3414                                         dev->data->dev_private);
3415                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3416                 unsigned int i, stat, count = 0;
3417
3418                 count = ixgbe_xstats_calc_num();
3419
3420                 if (!ids && n < count)
3421                         return count;
3422
3423                 total_missed_rx = 0;
3424                 total_qbrc = 0;
3425                 total_qprc = 0;
3426                 total_qprdc = 0;
3427
3428                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3429                                 &total_missed_rx, &total_qbrc, &total_qprc,
3430                                 &total_qprdc);
3431
3432                 /* If this is a reset xstats is NULL, and we have cleared the
3433                  * registers by reading them.
3434                  */
3435                 if (!ids && !values)
3436                         return 0;
3437
3438                 /* Extended stats from ixgbe_hw_stats */
3439                 count = 0;
3440                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3441                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3442                                         rte_ixgbe_stats_strings[i].offset);
3443                         count++;
3444                 }
3445
3446                 /* MACsec Stats */
3447                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3448                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3449                                         rte_ixgbe_macsec_strings[i].offset);
3450                         count++;
3451                 }
3452
3453                 /* RX Priority Stats */
3454                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3455                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3456                                 values[count] =
3457                                         *(uint64_t *)(((char *)hw_stats) +
3458                                         rte_ixgbe_rxq_strings[stat].offset +
3459                                         (sizeof(uint64_t) * i));
3460                                 count++;
3461                         }
3462                 }
3463
3464                 /* TX Priority Stats */
3465                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3466                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3467                                 values[count] =
3468                                         *(uint64_t *)(((char *)hw_stats) +
3469                                         rte_ixgbe_txq_strings[stat].offset +
3470                                         (sizeof(uint64_t) * i));
3471                                 count++;
3472                         }
3473                 }
3474                 return count;
3475         }
3476
3477         uint16_t i;
3478         uint16_t size = ixgbe_xstats_calc_num();
3479         uint64_t values_copy[size];
3480
3481         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3482
3483         for (i = 0; i < n; i++) {
3484                 if (ids[i] >= size) {
3485                         PMD_INIT_LOG(ERR, "id value isn't valid");
3486                         return -1;
3487                 }
3488                 values[i] = values_copy[ids[i]];
3489         }
3490         return n;
3491 }
3492
3493 static void
3494 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3495 {
3496         struct ixgbe_hw_stats *stats =
3497                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3498         struct ixgbe_macsec_stats *macsec_stats =
3499                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3500                                 dev->data->dev_private);
3501
3502         unsigned count = ixgbe_xstats_calc_num();
3503
3504         /* HW registers are cleared on read */
3505         ixgbe_dev_xstats_get(dev, NULL, count);
3506
3507         /* Reset software totals */
3508         memset(stats, 0, sizeof(*stats));
3509         memset(macsec_stats, 0, sizeof(*macsec_stats));
3510 }
3511
3512 static void
3513 ixgbevf_update_stats(struct rte_eth_dev *dev)
3514 {
3515         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3516         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3517                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3518
3519         /* Good Rx packet, include VF loopback */
3520         UPDATE_VF_STAT(IXGBE_VFGPRC,
3521             hw_stats->last_vfgprc, hw_stats->vfgprc);
3522
3523         /* Good Rx octets, include VF loopback */
3524         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3525             hw_stats->last_vfgorc, hw_stats->vfgorc);
3526
3527         /* Good Tx packet, include VF loopback */
3528         UPDATE_VF_STAT(IXGBE_VFGPTC,
3529             hw_stats->last_vfgptc, hw_stats->vfgptc);
3530
3531         /* Good Tx octets, include VF loopback */
3532         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3533             hw_stats->last_vfgotc, hw_stats->vfgotc);
3534
3535         /* Rx Multicst Packet */
3536         UPDATE_VF_STAT(IXGBE_VFMPRC,
3537             hw_stats->last_vfmprc, hw_stats->vfmprc);
3538 }
3539
3540 static int
3541 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3542                        unsigned n)
3543 {
3544         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3545                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3546         unsigned i;
3547
3548         if (n < IXGBEVF_NB_XSTATS)
3549                 return IXGBEVF_NB_XSTATS;
3550
3551         ixgbevf_update_stats(dev);
3552
3553         if (!xstats)
3554                 return 0;
3555
3556         /* Extended stats */
3557         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3558                 xstats[i].id = i;
3559                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3560                         rte_ixgbevf_stats_strings[i].offset);
3561         }
3562
3563         return IXGBEVF_NB_XSTATS;
3564 }
3565
3566 static int
3567 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3568 {
3569         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3570                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3571
3572         ixgbevf_update_stats(dev);
3573
3574         if (stats == NULL)
3575                 return -EINVAL;
3576
3577         stats->ipackets = hw_stats->vfgprc;
3578         stats->ibytes = hw_stats->vfgorc;
3579         stats->opackets = hw_stats->vfgptc;
3580         stats->obytes = hw_stats->vfgotc;
3581         return 0;
3582 }
3583
3584 static void
3585 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3586 {
3587         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3588                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3589
3590         /* Sync HW register to the last stats */
3591         ixgbevf_dev_stats_get(dev, NULL);
3592
3593         /* reset HW current stats*/
3594         hw_stats->vfgprc = 0;
3595         hw_stats->vfgorc = 0;
3596         hw_stats->vfgptc = 0;
3597         hw_stats->vfgotc = 0;
3598 }
3599
3600 static int
3601 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3602 {
3603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3604         u16 eeprom_verh, eeprom_verl;
3605         u32 etrack_id;
3606         int ret;
3607
3608         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3609         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3610
3611         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3612         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3613
3614         ret += 1; /* add the size of '\0' */
3615         if (fw_size < (u32)ret)
3616                 return ret;
3617         else
3618                 return 0;
3619 }
3620
3621 static void
3622 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3623 {
3624         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3626         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3627
3628         dev_info->pci_dev = pci_dev;
3629         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3630         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3631         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3632                 /*
3633                  * When DCB/VT is off, maximum number of queues changes,
3634                  * except for 82598EB, which remains constant.
3635                  */
3636                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3637                                 hw->mac.type != ixgbe_mac_82598EB)
3638                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3639         }
3640         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3641         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3642         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3643         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3644         dev_info->max_vfs = pci_dev->max_vfs;
3645         if (hw->mac.type == ixgbe_mac_82598EB)
3646                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3647         else
3648                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3649         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3650         dev_info->rx_offload_capa =
3651                 DEV_RX_OFFLOAD_VLAN_STRIP |
3652                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3653                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3654                 DEV_RX_OFFLOAD_TCP_CKSUM;
3655
3656         /*
3657          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3658          * mode.
3659          */
3660         if ((hw->mac.type == ixgbe_mac_82599EB ||
3661              hw->mac.type == ixgbe_mac_X540) &&
3662             !RTE_ETH_DEV_SRIOV(dev).active)
3663                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3664
3665         if (hw->mac.type == ixgbe_mac_82599EB ||
3666             hw->mac.type == ixgbe_mac_X540)
3667                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3668
3669         if (hw->mac.type == ixgbe_mac_X550 ||
3670             hw->mac.type == ixgbe_mac_X550EM_x ||
3671             hw->mac.type == ixgbe_mac_X550EM_a)
3672                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3673
3674         dev_info->tx_offload_capa =
3675                 DEV_TX_OFFLOAD_VLAN_INSERT |
3676                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3677                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3678                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3679                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3680                 DEV_TX_OFFLOAD_TCP_TSO;
3681
3682         if (hw->mac.type == ixgbe_mac_82599EB ||
3683             hw->mac.type == ixgbe_mac_X540)
3684                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3685
3686         if (hw->mac.type == ixgbe_mac_X550 ||
3687             hw->mac.type == ixgbe_mac_X550EM_x ||
3688             hw->mac.type == ixgbe_mac_X550EM_a)
3689                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3690
3691 #ifdef RTE_LIBRTE_SECURITY
3692         if (dev->security_ctx) {
3693                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3694                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3695         }
3696 #endif
3697
3698         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3699                 .rx_thresh = {
3700                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3701                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3702                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3703                 },
3704                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3705                 .rx_drop_en = 0,
3706         };
3707
3708         dev_info->default_txconf = (struct rte_eth_txconf) {
3709                 .tx_thresh = {
3710                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3711                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3712                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3713                 },
3714                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3715                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3716                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3717                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3718         };
3719
3720         dev_info->rx_desc_lim = rx_desc_lim;
3721         dev_info->tx_desc_lim = tx_desc_lim;
3722
3723         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3724         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3725         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3726
3727         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3728         if (hw->mac.type == ixgbe_mac_X540 ||
3729             hw->mac.type == ixgbe_mac_X540_vf ||
3730             hw->mac.type == ixgbe_mac_X550 ||
3731             hw->mac.type == ixgbe_mac_X550_vf) {
3732                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3733         }
3734         if (hw->mac.type == ixgbe_mac_X550) {
3735                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3736                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3737         }
3738 }
3739
3740 static const uint32_t *
3741 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3742 {
3743         static const uint32_t ptypes[] = {
3744                 /* For non-vec functions,
3745                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3746                  * for vec functions,
3747                  * refers to _recv_raw_pkts_vec().
3748                  */
3749                 RTE_PTYPE_L2_ETHER,
3750                 RTE_PTYPE_L3_IPV4,
3751                 RTE_PTYPE_L3_IPV4_EXT,
3752                 RTE_PTYPE_L3_IPV6,
3753                 RTE_PTYPE_L3_IPV6_EXT,
3754                 RTE_PTYPE_L4_SCTP,
3755                 RTE_PTYPE_L4_TCP,
3756                 RTE_PTYPE_L4_UDP,
3757                 RTE_PTYPE_TUNNEL_IP,
3758                 RTE_PTYPE_INNER_L3_IPV6,
3759                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3760                 RTE_PTYPE_INNER_L4_TCP,
3761                 RTE_PTYPE_INNER_L4_UDP,
3762                 RTE_PTYPE_UNKNOWN
3763         };
3764
3765         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3766             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3767             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3768             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3769                 return ptypes;
3770
3771 #if defined(RTE_ARCH_X86)
3772         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3773             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3774                 return ptypes;
3775 #endif
3776         return NULL;
3777 }
3778
3779 static void
3780 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3781                      struct rte_eth_dev_info *dev_info)
3782 {
3783         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785
3786         dev_info->pci_dev = pci_dev;
3787         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3788         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3789         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3790         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3791         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3792         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3793         dev_info->max_vfs = pci_dev->max_vfs;
3794         if (hw->mac.type == ixgbe_mac_82598EB)
3795                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3796         else
3797                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3798         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3799                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3800                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3801                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3802         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3803                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3804                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3805                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3806                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3807                                 DEV_TX_OFFLOAD_TCP_TSO;
3808
3809         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3810                 .rx_thresh = {
3811                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3812                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3813                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3814                 },
3815                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3816                 .rx_drop_en = 0,
3817         };
3818
3819         dev_info->default_txconf = (struct rte_eth_txconf) {
3820                 .tx_thresh = {
3821                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3822                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3823                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3824                 },
3825                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3826                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3827                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3828                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3829         };
3830
3831         dev_info->rx_desc_lim = rx_desc_lim;
3832         dev_info->tx_desc_lim = tx_desc_lim;
3833 }
3834
3835 static int
3836 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3837                    int *link_up, int wait_to_complete)
3838 {
3839         /**
3840          * for a quick link status checking, wait_to_compelet == 0,
3841          * skip PF link status checking
3842          */
3843         bool no_pflink_check = wait_to_complete == 0;
3844         struct ixgbe_mbx_info *mbx = &hw->mbx;
3845         struct ixgbe_mac_info *mac = &hw->mac;
3846         uint32_t links_reg, in_msg;
3847         int ret_val = 0;
3848
3849         /* If we were hit with a reset drop the link */
3850         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3851                 mac->get_link_status = true;
3852
3853         if (!mac->get_link_status)
3854                 goto out;
3855
3856         /* if link status is down no point in checking to see if pf is up */
3857         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3858         if (!(links_reg & IXGBE_LINKS_UP))
3859                 goto out;
3860
3861         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3862          * before the link status is correct
3863          */
3864         if (mac->type == ixgbe_mac_82599_vf) {
3865                 int i;
3866
3867                 for (i = 0; i < 5; i++) {
3868                         rte_delay_us(100);
3869                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3870
3871                         if (!(links_reg & IXGBE_LINKS_UP))
3872                                 goto out;
3873                 }
3874         }
3875
3876         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3877         case IXGBE_LINKS_SPEED_10G_82599:
3878                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3879                 if (hw->mac.type >= ixgbe_mac_X550) {
3880                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3881                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3882                 }
3883                 break;
3884         case IXGBE_LINKS_SPEED_1G_82599:
3885                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3886                 break;
3887         case IXGBE_LINKS_SPEED_100_82599:
3888                 *speed = IXGBE_LINK_SPEED_100_FULL;
3889                 if (hw->mac.type == ixgbe_mac_X550) {
3890                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3891                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3892                 }
3893                 break;
3894         case IXGBE_LINKS_SPEED_10_X550EM_A:
3895                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3896                 /* Since Reserved in older MAC's */
3897                 if (hw->mac.type >= ixgbe_mac_X550)
3898                         *speed = IXGBE_LINK_SPEED_10_FULL;
3899                 break;
3900         default:
3901                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3902         }
3903
3904         if (no_pflink_check) {
3905                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3906                         mac->get_link_status = true;
3907                 else
3908                         mac->get_link_status = false;
3909
3910                 goto out;
3911         }
3912         /* if the read failed it could just be a mailbox collision, best wait
3913          * until we are called again and don't report an error
3914          */
3915         if (mbx->ops.read(hw, &in_msg, 1, 0))
3916                 goto out;
3917
3918         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3919                 /* msg is not CTS and is NACK we must have lost CTS status */
3920                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3921                         ret_val = -1;
3922                 goto out;
3923         }
3924
3925         /* the pf is talking, if we timed out in the past we reinit */
3926         if (!mbx->timeout) {
3927                 ret_val = -1;
3928                 goto out;
3929         }
3930
3931         /* if we passed all the tests above then the link is up and we no
3932          * longer need to check for link
3933          */
3934         mac->get_link_status = false;
3935
3936 out:
3937         *link_up = !mac->get_link_status;
3938         return ret_val;
3939 }
3940
3941 /* return 0 means link status changed, -1 means not changed */
3942 static int
3943 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3944                             int wait_to_complete, int vf)
3945 {
3946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3947         struct rte_eth_link link, old;
3948         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3949         struct ixgbe_interrupt *intr =
3950                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3951         int link_up;
3952         int diag;
3953         u32 speed = 0;
3954         int wait = 1;
3955         bool autoneg = false;
3956
3957         link.link_status = ETH_LINK_DOWN;
3958         link.link_speed = 0;
3959         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3960         link.link_autoneg = ETH_LINK_AUTONEG;
3961         memset(&old, 0, sizeof(old));
3962         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3963
3964         hw->mac.get_link_status = true;
3965
3966         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3967                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3968                 speed = hw->phy.autoneg_advertised;
3969                 if (!speed)
3970                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3971                 ixgbe_setup_link(hw, speed, true);
3972         }
3973
3974         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3975         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3976                 wait = 0;
3977
3978         if (vf)
3979                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3980         else
3981                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3982
3983         if (diag != 0) {
3984                 link.link_speed = ETH_SPEED_NUM_100M;
3985                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3986                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3987                 if (link.link_status == old.link_status)
3988                         return -1;
3989                 return 0;
3990         }
3991
3992         if (link_up == 0) {
3993                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3994                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3995                 if (link.link_status == old.link_status)
3996                         return -1;
3997                 return 0;
3998         }
3999         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4000         link.link_status = ETH_LINK_UP;
4001         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4002
4003         switch (link_speed) {
4004         default:
4005         case IXGBE_LINK_SPEED_UNKNOWN:
4006                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4007                 link.link_speed = ETH_SPEED_NUM_100M;
4008                 break;
4009
4010         case IXGBE_LINK_SPEED_100_FULL:
4011                 link.link_speed = ETH_SPEED_NUM_100M;
4012                 break;
4013
4014         case IXGBE_LINK_SPEED_1GB_FULL:
4015                 link.link_speed = ETH_SPEED_NUM_1G;
4016                 break;
4017
4018         case IXGBE_LINK_SPEED_2_5GB_FULL:
4019                 link.link_speed = ETH_SPEED_NUM_2_5G;
4020                 break;
4021
4022         case IXGBE_LINK_SPEED_5GB_FULL:
4023                 link.link_speed = ETH_SPEED_NUM_5G;
4024                 break;
4025
4026         case IXGBE_LINK_SPEED_10GB_FULL:
4027                 link.link_speed = ETH_SPEED_NUM_10G;
4028                 break;
4029         }
4030         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4031
4032         if (link.link_status == old.link_status)
4033                 return -1;
4034
4035         return 0;
4036 }
4037
4038 static int
4039 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4040 {
4041         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4042 }
4043
4044 static int
4045 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4046 {
4047         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4048 }
4049
4050 static void
4051 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4052 {
4053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4054         uint32_t fctrl;
4055
4056         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4057         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4058         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4059 }
4060
4061 static void
4062 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4063 {
4064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4065         uint32_t fctrl;
4066
4067         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4068         fctrl &= (~IXGBE_FCTRL_UPE);
4069         if (dev->data->all_multicast == 1)
4070                 fctrl |= IXGBE_FCTRL_MPE;
4071         else
4072                 fctrl &= (~IXGBE_FCTRL_MPE);
4073         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4074 }
4075
4076 static void
4077 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4078 {
4079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4080         uint32_t fctrl;
4081
4082         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4083         fctrl |= IXGBE_FCTRL_MPE;
4084         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4085 }
4086
4087 static void
4088 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4089 {
4090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4091         uint32_t fctrl;
4092
4093         if (dev->data->promiscuous == 1)
4094                 return; /* must remain in all_multicast mode */
4095
4096         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4097         fctrl &= (~IXGBE_FCTRL_MPE);
4098         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4099 }
4100
4101 /**
4102  * It clears the interrupt causes and enables the interrupt.
4103  * It will be called once only during nic initialized.
4104  *
4105  * @param dev
4106  *  Pointer to struct rte_eth_dev.
4107  * @param on
4108  *  Enable or Disable.
4109  *
4110  * @return
4111  *  - On success, zero.
4112  *  - On failure, a negative value.
4113  */
4114 static int
4115 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4116 {
4117         struct ixgbe_interrupt *intr =
4118                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4119
4120         ixgbe_dev_link_status_print(dev);
4121         if (on)
4122                 intr->mask |= IXGBE_EICR_LSC;
4123         else
4124                 intr->mask &= ~IXGBE_EICR_LSC;
4125
4126         return 0;
4127 }
4128
4129 /**
4130  * It clears the interrupt causes and enables the interrupt.
4131  * It will be called once only during nic initialized.
4132  *
4133  * @param dev
4134  *  Pointer to struct rte_eth_dev.
4135  *
4136  * @return
4137  *  - On success, zero.
4138  *  - On failure, a negative value.
4139  */
4140 static int
4141 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4142 {
4143         struct ixgbe_interrupt *intr =
4144                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4145
4146         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4147
4148         return 0;
4149 }
4150
4151 /**
4152  * It clears the interrupt causes and enables the interrupt.
4153  * It will be called once only during nic initialized.
4154  *
4155  * @param dev
4156  *  Pointer to struct rte_eth_dev.
4157  *
4158  * @return
4159  *  - On success, zero.
4160  *  - On failure, a negative value.
4161  */
4162 static int
4163 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4164 {
4165         struct ixgbe_interrupt *intr =
4166                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4167
4168         intr->mask |= IXGBE_EICR_LINKSEC;
4169
4170         return 0;
4171 }
4172
4173 /*
4174  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4175  *
4176  * @param dev
4177  *  Pointer to struct rte_eth_dev.
4178  *
4179  * @return
4180  *  - On success, zero.
4181  *  - On failure, a negative value.
4182  */
4183 static int
4184 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4185 {
4186         uint32_t eicr;
4187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188         struct ixgbe_interrupt *intr =
4189                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4190
4191         /* clear all cause mask */
4192         ixgbe_disable_intr(hw);
4193
4194         /* read-on-clear nic registers here */
4195         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4196         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4197
4198         intr->flags = 0;
4199
4200         /* set flag for async link update */
4201         if (eicr & IXGBE_EICR_LSC)
4202                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4203
4204         if (eicr & IXGBE_EICR_MAILBOX)
4205                 intr->flags |= IXGBE_FLAG_MAILBOX;
4206
4207         if (eicr & IXGBE_EICR_LINKSEC)
4208                 intr->flags |= IXGBE_FLAG_MACSEC;
4209
4210         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4211             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4212             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4213                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4214
4215         return 0;
4216 }
4217
4218 /**
4219  * It gets and then prints the link status.
4220  *
4221  * @param dev
4222  *  Pointer to struct rte_eth_dev.
4223  *
4224  * @return
4225  *  - On success, zero.
4226  *  - On failure, a negative value.
4227  */
4228 static void
4229 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4230 {
4231         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4232         struct rte_eth_link link;
4233
4234         memset(&link, 0, sizeof(link));
4235         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4236         if (link.link_status) {
4237                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4238                                         (int)(dev->data->port_id),
4239                                         (unsigned)link.link_speed,
4240                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4241                                         "full-duplex" : "half-duplex");
4242         } else {
4243                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4244                                 (int)(dev->data->port_id));
4245         }
4246         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4247                                 pci_dev->addr.domain,
4248                                 pci_dev->addr.bus,
4249                                 pci_dev->addr.devid,
4250                                 pci_dev->addr.function);
4251 }
4252
4253 /*
4254  * It executes link_update after knowing an interrupt occurred.
4255  *
4256  * @param dev
4257  *  Pointer to struct rte_eth_dev.
4258  *
4259  * @return
4260  *  - On success, zero.
4261  *  - On failure, a negative value.
4262  */
4263 static int
4264 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4265                            struct rte_intr_handle *intr_handle)
4266 {
4267         struct ixgbe_interrupt *intr =
4268                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4269         int64_t timeout;
4270         struct rte_eth_link link;
4271         struct ixgbe_hw *hw =
4272                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4273
4274         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4275
4276         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4277                 ixgbe_pf_mbx_process(dev);
4278                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4279         }
4280
4281         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4282                 ixgbe_handle_lasi(hw);
4283                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4284         }
4285
4286         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4287                 /* get the link status before link update, for predicting later */
4288                 memset(&link, 0, sizeof(link));
4289                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4290
4291                 ixgbe_dev_link_update(dev, 0);
4292
4293                 /* likely to up */
4294                 if (!link.link_status)
4295                         /* handle it 1 sec later, wait it being stable */
4296                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4297                 /* likely to down */
4298                 else
4299                         /* handle it 4 sec later, wait it being stable */
4300                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4301
4302                 ixgbe_dev_link_status_print(dev);
4303                 if (rte_eal_alarm_set(timeout * 1000,
4304                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4305                         PMD_DRV_LOG(ERR, "Error setting alarm");
4306                 else {
4307                         /* remember original mask */
4308                         intr->mask_original = intr->mask;
4309                         /* only disable lsc interrupt */
4310                         intr->mask &= ~IXGBE_EIMS_LSC;
4311                 }
4312         }
4313
4314         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4315         ixgbe_enable_intr(dev);
4316         rte_intr_enable(intr_handle);
4317
4318         return 0;
4319 }
4320
4321 /**
4322  * Interrupt handler which shall be registered for alarm callback for delayed
4323  * handling specific interrupt to wait for the stable nic state. As the
4324  * NIC interrupt state is not stable for ixgbe after link is just down,
4325  * it needs to wait 4 seconds to get the stable status.
4326  *
4327  * @param handle
4328  *  Pointer to interrupt handle.
4329  * @param param
4330  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4331  *
4332  * @return
4333  *  void
4334  */
4335 static void
4336 ixgbe_dev_interrupt_delayed_handler(void *param)
4337 {
4338         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4339         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4340         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4341         struct ixgbe_interrupt *intr =
4342                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4343         struct ixgbe_hw *hw =
4344                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4345         uint32_t eicr;
4346
4347         ixgbe_disable_intr(hw);
4348
4349         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4350         if (eicr & IXGBE_EICR_MAILBOX)
4351                 ixgbe_pf_mbx_process(dev);
4352
4353         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4354                 ixgbe_handle_lasi(hw);
4355                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4356         }
4357
4358         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4359                 ixgbe_dev_link_update(dev, 0);
4360                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4361                 ixgbe_dev_link_status_print(dev);
4362                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4363                                               NULL);
4364         }
4365
4366         if (intr->flags & IXGBE_FLAG_MACSEC) {
4367                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4368                                               NULL);
4369                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4370         }
4371
4372         /* restore original mask */
4373         intr->mask = intr->mask_original;
4374         intr->mask_original = 0;
4375
4376         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4377         ixgbe_enable_intr(dev);
4378         rte_intr_enable(intr_handle);
4379 }
4380
4381 /**
4382  * Interrupt handler triggered by NIC  for handling
4383  * specific interrupt.
4384  *
4385  * @param handle
4386  *  Pointer to interrupt handle.
4387  * @param param
4388  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4389  *
4390  * @return
4391  *  void
4392  */
4393 static void
4394 ixgbe_dev_interrupt_handler(void *param)
4395 {
4396         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4397
4398         ixgbe_dev_interrupt_get_status(dev);
4399         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4400 }
4401
4402 static int
4403 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4404 {
4405         struct ixgbe_hw *hw;
4406
4407         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4408         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4409 }
4410
4411 static int
4412 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4413 {
4414         struct ixgbe_hw *hw;
4415
4416         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4417         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4418 }
4419
4420 static int
4421 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4422 {
4423         struct ixgbe_hw *hw;
4424         uint32_t mflcn_reg;
4425         uint32_t fccfg_reg;
4426         int rx_pause;
4427         int tx_pause;
4428
4429         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4430
4431         fc_conf->pause_time = hw->fc.pause_time;
4432         fc_conf->high_water = hw->fc.high_water[0];
4433         fc_conf->low_water = hw->fc.low_water[0];
4434         fc_conf->send_xon = hw->fc.send_xon;
4435         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4436
4437         /*
4438          * Return rx_pause status according to actual setting of
4439          * MFLCN register.
4440          */
4441         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4442         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4443                 rx_pause = 1;
4444         else
4445                 rx_pause = 0;
4446
4447         /*
4448          * Return tx_pause status according to actual setting of
4449          * FCCFG register.
4450          */
4451         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4452         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4453                 tx_pause = 1;
4454         else
4455                 tx_pause = 0;
4456
4457         if (rx_pause && tx_pause)
4458                 fc_conf->mode = RTE_FC_FULL;
4459         else if (rx_pause)
4460                 fc_conf->mode = RTE_FC_RX_PAUSE;
4461         else if (tx_pause)
4462                 fc_conf->mode = RTE_FC_TX_PAUSE;
4463         else
4464                 fc_conf->mode = RTE_FC_NONE;
4465
4466         return 0;
4467 }
4468
4469 static int
4470 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4471 {
4472         struct ixgbe_hw *hw;
4473         int err;
4474         uint32_t rx_buf_size;
4475         uint32_t max_high_water;
4476         uint32_t mflcn;
4477         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4478                 ixgbe_fc_none,
4479                 ixgbe_fc_rx_pause,
4480                 ixgbe_fc_tx_pause,
4481                 ixgbe_fc_full
4482         };
4483
4484         PMD_INIT_FUNC_TRACE();
4485
4486         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4487         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4488         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4489
4490         /*
4491          * At least reserve one Ethernet frame for watermark
4492          * high_water/low_water in kilo bytes for ixgbe
4493          */
4494         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4495         if ((fc_conf->high_water > max_high_water) ||
4496                 (fc_conf->high_water < fc_conf->low_water)) {
4497                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4498                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4499                 return -EINVAL;
4500         }
4501
4502         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4503         hw->fc.pause_time     = fc_conf->pause_time;
4504         hw->fc.high_water[0]  = fc_conf->high_water;
4505         hw->fc.low_water[0]   = fc_conf->low_water;
4506         hw->fc.send_xon       = fc_conf->send_xon;
4507         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4508
4509         err = ixgbe_fc_enable(hw);
4510
4511         /* Not negotiated is not an error case */
4512         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4513
4514                 /* check if we want to forward MAC frames - driver doesn't have native
4515                  * capability to do that, so we'll write the registers ourselves */
4516
4517                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4518
4519                 /* set or clear MFLCN.PMCF bit depending on configuration */
4520                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4521                         mflcn |= IXGBE_MFLCN_PMCF;
4522                 else
4523                         mflcn &= ~IXGBE_MFLCN_PMCF;
4524
4525                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4526                 IXGBE_WRITE_FLUSH(hw);
4527
4528                 return 0;
4529         }
4530
4531         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4532         return -EIO;
4533 }
4534
4535 /**
4536  *  ixgbe_pfc_enable_generic - Enable flow control
4537  *  @hw: pointer to hardware structure
4538  *  @tc_num: traffic class number
4539  *  Enable flow control according to the current settings.
4540  */
4541 static int
4542 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4543 {
4544         int ret_val = 0;
4545         uint32_t mflcn_reg, fccfg_reg;
4546         uint32_t reg;
4547         uint32_t fcrtl, fcrth;
4548         uint8_t i;
4549         uint8_t nb_rx_en;
4550
4551         /* Validate the water mark configuration */
4552         if (!hw->fc.pause_time) {
4553                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4554                 goto out;
4555         }
4556
4557         /* Low water mark of zero causes XOFF floods */
4558         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4559                  /* High/Low water can not be 0 */
4560                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4561                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4562                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4563                         goto out;
4564                 }
4565
4566                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4567                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4568                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4569                         goto out;
4570                 }
4571         }
4572         /* Negotiate the fc mode to use */
4573         ixgbe_fc_autoneg(hw);
4574
4575         /* Disable any previous flow control settings */
4576         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4577         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4578
4579         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4580         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4581
4582         switch (hw->fc.current_mode) {
4583         case ixgbe_fc_none:
4584                 /*
4585                  * If the count of enabled RX Priority Flow control >1,
4586                  * and the TX pause can not be disabled
4587                  */
4588                 nb_rx_en = 0;
4589                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4590                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4591                         if (reg & IXGBE_FCRTH_FCEN)
4592                                 nb_rx_en++;
4593                 }
4594                 if (nb_rx_en > 1)
4595                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4596                 break;
4597         case ixgbe_fc_rx_pause:
4598                 /*
4599                  * Rx Flow control is enabled and Tx Flow control is
4600                  * disabled by software override. Since there really
4601                  * isn't a way to advertise that we are capable of RX
4602                  * Pause ONLY, we will advertise that we support both
4603                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4604                  * disable the adapter's ability to send PAUSE frames.
4605                  */
4606                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4607                 /*
4608                  * If the count of enabled RX Priority Flow control >1,
4609                  * and the TX pause can not be disabled
4610                  */
4611                 nb_rx_en = 0;
4612                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4613                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4614                         if (reg & IXGBE_FCRTH_FCEN)
4615                                 nb_rx_en++;
4616                 }
4617                 if (nb_rx_en > 1)
4618                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4619                 break;
4620         case ixgbe_fc_tx_pause:
4621                 /*
4622                  * Tx Flow control is enabled, and Rx Flow control is
4623                  * disabled by software override.
4624                  */
4625                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4626                 break;
4627         case ixgbe_fc_full:
4628                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4629                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4630                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4631                 break;
4632         default:
4633                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4634                 ret_val = IXGBE_ERR_CONFIG;
4635                 goto out;
4636         }
4637
4638         /* Set 802.3x based flow control settings. */
4639         mflcn_reg |= IXGBE_MFLCN_DPF;
4640         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4641         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4642
4643         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4644         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4645                 hw->fc.high_water[tc_num]) {
4646                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4647                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4648                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4649         } else {
4650                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4651                 /*
4652                  * In order to prevent Tx hangs when the internal Tx
4653                  * switch is enabled we must set the high water mark
4654                  * to the maximum FCRTH value.  This allows the Tx
4655                  * switch to function even under heavy Rx workloads.
4656                  */
4657                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4658         }
4659         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4660
4661         /* Configure pause time (2 TCs per register) */
4662         reg = hw->fc.pause_time * 0x00010001;
4663         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4664                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4665
4666         /* Configure flow control refresh threshold value */
4667         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4668
4669 out:
4670         return ret_val;
4671 }
4672
4673 static int
4674 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4675 {
4676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4678
4679         if (hw->mac.type != ixgbe_mac_82598EB) {
4680                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4681         }
4682         return ret_val;
4683 }
4684
4685 static int
4686 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4687 {
4688         int err;
4689         uint32_t rx_buf_size;
4690         uint32_t max_high_water;
4691         uint8_t tc_num;
4692         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4693         struct ixgbe_hw *hw =
4694                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695         struct ixgbe_dcb_config *dcb_config =
4696                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4697
4698         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4699                 ixgbe_fc_none,
4700                 ixgbe_fc_rx_pause,
4701                 ixgbe_fc_tx_pause,
4702                 ixgbe_fc_full
4703         };
4704
4705         PMD_INIT_FUNC_TRACE();
4706
4707         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4708         tc_num = map[pfc_conf->priority];
4709         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4710         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4711         /*
4712          * At least reserve one Ethernet frame for watermark
4713          * high_water/low_water in kilo bytes for ixgbe
4714          */
4715         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4716         if ((pfc_conf->fc.high_water > max_high_water) ||
4717             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4718                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4719                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4720                 return -EINVAL;
4721         }
4722
4723         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4724         hw->fc.pause_time = pfc_conf->fc.pause_time;
4725         hw->fc.send_xon = pfc_conf->fc.send_xon;
4726         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4727         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4728
4729         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4730
4731         /* Not negotiated is not an error case */
4732         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4733                 return 0;
4734
4735         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4736         return -EIO;
4737 }
4738
4739 static int
4740 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4741                           struct rte_eth_rss_reta_entry64 *reta_conf,
4742                           uint16_t reta_size)
4743 {
4744         uint16_t i, sp_reta_size;
4745         uint8_t j, mask;
4746         uint32_t reta, r;
4747         uint16_t idx, shift;
4748         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4749         uint32_t reta_reg;
4750
4751         PMD_INIT_FUNC_TRACE();
4752
4753         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4754                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4755                         "NIC.");
4756                 return -ENOTSUP;
4757         }
4758
4759         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4760         if (reta_size != sp_reta_size) {
4761                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4762                         "(%d) doesn't match the number hardware can supported "
4763                         "(%d)", reta_size, sp_reta_size);
4764                 return -EINVAL;
4765         }
4766
4767         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4768                 idx = i / RTE_RETA_GROUP_SIZE;
4769                 shift = i % RTE_RETA_GROUP_SIZE;
4770                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4771                                                 IXGBE_4_BIT_MASK);
4772                 if (!mask)
4773                         continue;
4774                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4775                 if (mask == IXGBE_4_BIT_MASK)
4776                         r = 0;
4777                 else
4778                         r = IXGBE_READ_REG(hw, reta_reg);
4779                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4780                         if (mask & (0x1 << j))
4781                                 reta |= reta_conf[idx].reta[shift + j] <<
4782                                                         (CHAR_BIT * j);
4783                         else
4784                                 reta |= r & (IXGBE_8_BIT_MASK <<
4785                                                 (CHAR_BIT * j));
4786                 }
4787                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4788         }
4789
4790         return 0;
4791 }
4792
4793 static int
4794 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4795                          struct rte_eth_rss_reta_entry64 *reta_conf,
4796                          uint16_t reta_size)
4797 {
4798         uint16_t i, sp_reta_size;
4799         uint8_t j, mask;
4800         uint32_t reta;
4801         uint16_t idx, shift;
4802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4803         uint32_t reta_reg;
4804
4805         PMD_INIT_FUNC_TRACE();
4806         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4807         if (reta_size != sp_reta_size) {
4808                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4809                         "(%d) doesn't match the number hardware can supported "
4810                         "(%d)", reta_size, sp_reta_size);
4811                 return -EINVAL;
4812         }
4813
4814         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4815                 idx = i / RTE_RETA_GROUP_SIZE;
4816                 shift = i % RTE_RETA_GROUP_SIZE;
4817                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4818                                                 IXGBE_4_BIT_MASK);
4819                 if (!mask)
4820                         continue;
4821
4822                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4823                 reta = IXGBE_READ_REG(hw, reta_reg);
4824                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4825                         if (mask & (0x1 << j))
4826                                 reta_conf[idx].reta[shift + j] =
4827                                         ((reta >> (CHAR_BIT * j)) &
4828                                                 IXGBE_8_BIT_MASK);
4829                 }
4830         }
4831
4832         return 0;
4833 }
4834
4835 static int
4836 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4837                                 uint32_t index, uint32_t pool)
4838 {
4839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4840         uint32_t enable_addr = 1;
4841
4842         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4843                              pool, enable_addr);
4844 }
4845
4846 static void
4847 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4848 {
4849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850
4851         ixgbe_clear_rar(hw, index);
4852 }
4853
4854 static void
4855 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4856 {
4857         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4858
4859         ixgbe_remove_rar(dev, 0);
4860
4861         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4862 }
4863
4864 static bool
4865 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4866 {
4867         if (strcmp(dev->device->driver->name, drv->driver.name))
4868                 return false;
4869
4870         return true;
4871 }
4872
4873 bool
4874 is_ixgbe_supported(struct rte_eth_dev *dev)
4875 {
4876         return is_device_supported(dev, &rte_ixgbe_pmd);
4877 }
4878
4879 static int
4880 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4881 {
4882         uint32_t hlreg0;
4883         uint32_t maxfrs;
4884         struct ixgbe_hw *hw;
4885         struct rte_eth_dev_info dev_info;
4886         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4887         struct rte_eth_dev_data *dev_data = dev->data;
4888
4889         ixgbe_dev_info_get(dev, &dev_info);
4890
4891         /* check that mtu is within the allowed range */
4892         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4893                 return -EINVAL;
4894
4895         /* If device is started, refuse mtu that requires the support of
4896          * scattered packets when this feature has not been enabled before.
4897          */
4898         if (dev_data->dev_started && !dev_data->scattered_rx &&
4899             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4900              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4901                 PMD_INIT_LOG(ERR, "Stop port first.");
4902                 return -EINVAL;
4903         }
4904
4905         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4906         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4907
4908         /* switch to jumbo mode if needed */
4909         if (frame_size > ETHER_MAX_LEN) {
4910                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4911                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4912         } else {
4913                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4914                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4915         }
4916         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4917
4918         /* update max frame size */
4919         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4920
4921         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4922         maxfrs &= 0x0000FFFF;
4923         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4924         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4925
4926         return 0;
4927 }
4928
4929 /*
4930  * Virtual Function operations
4931  */
4932 static void
4933 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4934 {
4935         PMD_INIT_FUNC_TRACE();
4936
4937         /* Clear interrupt mask to stop from interrupts being generated */
4938         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4939
4940         IXGBE_WRITE_FLUSH(hw);
4941 }
4942
4943 static void
4944 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4945 {
4946         PMD_INIT_FUNC_TRACE();
4947
4948         /* VF enable interrupt autoclean */
4949         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4950         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4951         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4952
4953         IXGBE_WRITE_FLUSH(hw);
4954 }
4955
4956 static int
4957 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4958 {
4959         struct rte_eth_conf *conf = &dev->data->dev_conf;
4960         struct ixgbe_adapter *adapter =
4961                         (struct ixgbe_adapter *)dev->data->dev_private;
4962
4963         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4964                      dev->data->port_id);
4965
4966         /*
4967          * VF has no ability to enable/disable HW CRC
4968          * Keep the persistent behavior the same as Host PF
4969          */
4970 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4971         if (!conf->rxmode.hw_strip_crc) {
4972                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4973                 conf->rxmode.hw_strip_crc = 1;
4974         }
4975 #else
4976         if (conf->rxmode.hw_strip_crc) {
4977                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4978                 conf->rxmode.hw_strip_crc = 0;
4979         }
4980 #endif
4981
4982         /*
4983          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4984          * allocation or vector Rx preconditions we will reset it.
4985          */
4986         adapter->rx_bulk_alloc_allowed = true;
4987         adapter->rx_vec_allowed = true;
4988
4989         return 0;
4990 }
4991
4992 static int
4993 ixgbevf_dev_start(struct rte_eth_dev *dev)
4994 {
4995         struct ixgbe_hw *hw =
4996                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4997         uint32_t intr_vector = 0;
4998         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4999         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5000
5001         int err, mask = 0;
5002
5003         PMD_INIT_FUNC_TRACE();
5004
5005         hw->mac.ops.reset_hw(hw);
5006         hw->mac.get_link_status = true;
5007
5008         /* negotiate mailbox API version to use with the PF. */
5009         ixgbevf_negotiate_api(hw);
5010
5011         ixgbevf_dev_tx_init(dev);
5012
5013         /* This can fail when allocating mbufs for descriptor rings */
5014         err = ixgbevf_dev_rx_init(dev);
5015         if (err) {
5016                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5017                 ixgbe_dev_clear_queues(dev);
5018                 return err;
5019         }
5020
5021         /* Set vfta */
5022         ixgbevf_set_vfta_all(dev, 1);
5023
5024         /* Set HW strip */
5025         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5026                 ETH_VLAN_EXTEND_MASK;
5027         err = ixgbevf_vlan_offload_set(dev, mask);
5028         if (err) {
5029                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5030                 ixgbe_dev_clear_queues(dev);
5031                 return err;
5032         }
5033
5034         ixgbevf_dev_rxtx_start(dev);
5035
5036         /* check and configure queue intr-vector mapping */
5037         if (dev->data->dev_conf.intr_conf.rxq != 0) {
5038                 /* According to datasheet, only vector 0/1/2 can be used,
5039                  * now only one vector is used for Rx queue
5040                  */
5041                 intr_vector = 1;
5042                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5043                         return -1;
5044         }
5045
5046         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5047                 intr_handle->intr_vec =
5048                         rte_zmalloc("intr_vec",
5049                                     dev->data->nb_rx_queues * sizeof(int), 0);
5050                 if (intr_handle->intr_vec == NULL) {
5051                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5052                                      " intr_vec", dev->data->nb_rx_queues);
5053                         return -ENOMEM;
5054                 }
5055         }
5056         ixgbevf_configure_msix(dev);
5057
5058         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5059          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5060          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5061          * is not cleared, it will fail when following rte_intr_enable( ) tries
5062          * to map Rx queue interrupt to other VFIO vectors.
5063          * So clear uio/vfio intr/evevnfd first to avoid failure.
5064          */
5065         rte_intr_disable(intr_handle);
5066
5067         rte_intr_enable(intr_handle);
5068
5069         /* Re-enable interrupt for VF */
5070         ixgbevf_intr_enable(hw);
5071
5072         return 0;
5073 }
5074
5075 static void
5076 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5077 {
5078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5079         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5080         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5081
5082         PMD_INIT_FUNC_TRACE();
5083
5084         ixgbevf_intr_disable(hw);
5085
5086         hw->adapter_stopped = 1;
5087         ixgbe_stop_adapter(hw);
5088
5089         /*
5090           * Clear what we set, but we still keep shadow_vfta to
5091           * restore after device starts
5092           */
5093         ixgbevf_set_vfta_all(dev, 0);
5094
5095         /* Clear stored conf */
5096         dev->data->scattered_rx = 0;
5097
5098         ixgbe_dev_clear_queues(dev);
5099
5100         /* Clean datapath event and queue/vec mapping */
5101         rte_intr_efd_disable(intr_handle);
5102         if (intr_handle->intr_vec != NULL) {
5103                 rte_free(intr_handle->intr_vec);
5104                 intr_handle->intr_vec = NULL;
5105         }
5106 }
5107
5108 static void
5109 ixgbevf_dev_close(struct rte_eth_dev *dev)
5110 {
5111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5112
5113         PMD_INIT_FUNC_TRACE();
5114
5115         ixgbe_reset_hw(hw);
5116
5117         ixgbevf_dev_stop(dev);
5118
5119         ixgbe_dev_free_queues(dev);
5120
5121         /**
5122          * Remove the VF MAC address ro ensure
5123          * that the VF traffic goes to the PF
5124          * after stop, close and detach of the VF
5125          **/
5126         ixgbevf_remove_mac_addr(dev, 0);
5127 }
5128
5129 /*
5130  * Reset VF device
5131  */
5132 static int
5133 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5134 {
5135         int ret;
5136
5137         ret = eth_ixgbevf_dev_uninit(dev);
5138         if (ret)
5139                 return ret;
5140
5141         ret = eth_ixgbevf_dev_init(dev);
5142
5143         return ret;
5144 }
5145
5146 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5147 {
5148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5149         struct ixgbe_vfta *shadow_vfta =
5150                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5151         int i = 0, j = 0, vfta = 0, mask = 1;
5152
5153         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5154                 vfta = shadow_vfta->vfta[i];
5155                 if (vfta) {
5156                         mask = 1;
5157                         for (j = 0; j < 32; j++) {
5158                                 if (vfta & mask)
5159                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5160                                                        on, false);
5161                                 mask <<= 1;
5162                         }
5163                 }
5164         }
5165
5166 }
5167
5168 static int
5169 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5170 {
5171         struct ixgbe_hw *hw =
5172                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5173         struct ixgbe_vfta *shadow_vfta =
5174                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5175         uint32_t vid_idx = 0;
5176         uint32_t vid_bit = 0;
5177         int ret = 0;
5178
5179         PMD_INIT_FUNC_TRACE();
5180
5181         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5182         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5183         if (ret) {
5184                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5185                 return ret;
5186         }
5187         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5188         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5189
5190         /* Save what we set and retore it after device reset */
5191         if (on)
5192                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5193         else
5194                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5195
5196         return 0;
5197 }
5198
5199 static void
5200 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5201 {
5202         struct ixgbe_hw *hw =
5203                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5204         uint32_t ctrl;
5205
5206         PMD_INIT_FUNC_TRACE();
5207
5208         if (queue >= hw->mac.max_rx_queues)
5209                 return;
5210
5211         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5212         if (on)
5213                 ctrl |= IXGBE_RXDCTL_VME;
5214         else
5215                 ctrl &= ~IXGBE_RXDCTL_VME;
5216         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5217
5218         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5219 }
5220
5221 static int
5222 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5223 {
5224         struct ixgbe_hw *hw =
5225                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5226         uint16_t i;
5227         int on = 0;
5228
5229         /* VF function only support hw strip feature, others are not support */
5230         if (mask & ETH_VLAN_STRIP_MASK) {
5231                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5232
5233                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5234                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5235         }
5236
5237         return 0;
5238 }
5239
5240 int
5241 ixgbe_vt_check(struct ixgbe_hw *hw)
5242 {
5243         uint32_t reg_val;
5244
5245         /* if Virtualization Technology is enabled */
5246         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5247         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5248                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5249                 return -1;
5250         }
5251
5252         return 0;
5253 }
5254
5255 static uint32_t
5256 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5257 {
5258         uint32_t vector = 0;
5259
5260         switch (hw->mac.mc_filter_type) {
5261         case 0:   /* use bits [47:36] of the address */
5262                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5263                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5264                 break;
5265         case 1:   /* use bits [46:35] of the address */
5266                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5267                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5268                 break;
5269         case 2:   /* use bits [45:34] of the address */
5270                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5271                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5272                 break;
5273         case 3:   /* use bits [43:32] of the address */
5274                 vector = ((uc_addr->addr_bytes[4]) |
5275                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5276                 break;
5277         default:  /* Invalid mc_filter_type */
5278                 break;
5279         }
5280
5281         /* vector can only be 12-bits or boundary will be exceeded */
5282         vector &= 0xFFF;
5283         return vector;
5284 }
5285
5286 static int
5287 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5288                         uint8_t on)
5289 {
5290         uint32_t vector;
5291         uint32_t uta_idx;
5292         uint32_t reg_val;
5293         uint32_t uta_shift;
5294         uint32_t rc;
5295         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5296         const uint32_t ixgbe_uta_bit_shift = 5;
5297         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5298         const uint32_t bit1 = 0x1;
5299
5300         struct ixgbe_hw *hw =
5301                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5302         struct ixgbe_uta_info *uta_info =
5303                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5304
5305         /* The UTA table only exists on 82599 hardware and newer */
5306         if (hw->mac.type < ixgbe_mac_82599EB)
5307                 return -ENOTSUP;
5308
5309         vector = ixgbe_uta_vector(hw, mac_addr);
5310         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5311         uta_shift = vector & ixgbe_uta_bit_mask;
5312
5313         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5314         if (rc == on)
5315                 return 0;
5316
5317         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5318         if (on) {
5319                 uta_info->uta_in_use++;
5320                 reg_val |= (bit1 << uta_shift);
5321                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5322         } else {
5323                 uta_info->uta_in_use--;
5324                 reg_val &= ~(bit1 << uta_shift);
5325                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5326         }
5327
5328         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5329
5330         if (uta_info->uta_in_use > 0)
5331                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5332                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5333         else
5334                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5335
5336         return 0;
5337 }
5338
5339 static int
5340 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5341 {
5342         int i;
5343         struct ixgbe_hw *hw =
5344                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5345         struct ixgbe_uta_info *uta_info =
5346                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5347
5348         /* The UTA table only exists on 82599 hardware and newer */
5349         if (hw->mac.type < ixgbe_mac_82599EB)
5350                 return -ENOTSUP;
5351
5352         if (on) {
5353                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5354                         uta_info->uta_shadow[i] = ~0;
5355                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5356                 }
5357         } else {
5358                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5359                         uta_info->uta_shadow[i] = 0;
5360                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5361                 }
5362         }
5363         return 0;
5364
5365 }
5366
5367 uint32_t
5368 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5369 {
5370         uint32_t new_val = orig_val;
5371
5372         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5373                 new_val |= IXGBE_VMOLR_AUPE;
5374         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5375                 new_val |= IXGBE_VMOLR_ROMPE;
5376         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5377                 new_val |= IXGBE_VMOLR_ROPE;
5378         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5379                 new_val |= IXGBE_VMOLR_BAM;
5380         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5381                 new_val |= IXGBE_VMOLR_MPE;
5382
5383         return new_val;
5384 }
5385
5386 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5387 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5388 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5389 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5390 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5391         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5392         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5393
5394 static int
5395 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5396                       struct rte_eth_mirror_conf *mirror_conf,
5397                       uint8_t rule_id, uint8_t on)
5398 {
5399         uint32_t mr_ctl, vlvf;
5400         uint32_t mp_lsb = 0;
5401         uint32_t mv_msb = 0;
5402         uint32_t mv_lsb = 0;
5403         uint32_t mp_msb = 0;
5404         uint8_t i = 0;
5405         int reg_index = 0;
5406         uint64_t vlan_mask = 0;
5407
5408         const uint8_t pool_mask_offset = 32;
5409         const uint8_t vlan_mask_offset = 32;
5410         const uint8_t dst_pool_offset = 8;
5411         const uint8_t rule_mr_offset  = 4;
5412         const uint8_t mirror_rule_mask = 0x0F;
5413
5414         struct ixgbe_mirror_info *mr_info =
5415                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5416         struct ixgbe_hw *hw =
5417                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5418         uint8_t mirror_type = 0;
5419
5420         if (ixgbe_vt_check(hw) < 0)
5421                 return -ENOTSUP;
5422
5423         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5424                 return -EINVAL;
5425
5426         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5427                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5428                             mirror_conf->rule_type);
5429                 return -EINVAL;
5430         }
5431
5432         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5433                 mirror_type |= IXGBE_MRCTL_VLME;
5434                 /* Check if vlan id is valid and find conresponding VLAN ID
5435                  * index in VLVF
5436                  */
5437                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5438                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5439                                 /* search vlan id related pool vlan filter
5440                                  * index
5441                                  */
5442                                 reg_index = ixgbe_find_vlvf_slot(
5443                                                 hw,
5444                                                 mirror_conf->vlan.vlan_id[i],
5445                                                 false);
5446                                 if (reg_index < 0)
5447                                         return -EINVAL;
5448                                 vlvf = IXGBE_READ_REG(hw,
5449                                                       IXGBE_VLVF(reg_index));
5450                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5451                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5452                                       mirror_conf->vlan.vlan_id[i]))
5453                                         vlan_mask |= (1ULL << reg_index);
5454                                 else
5455                                         return -EINVAL;
5456                         }
5457                 }
5458
5459                 if (on) {
5460                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5461                         mv_msb = vlan_mask >> vlan_mask_offset;
5462
5463                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5464                                                 mirror_conf->vlan.vlan_mask;
5465                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5466                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5467                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5468                                                 mirror_conf->vlan.vlan_id[i];
5469                         }
5470                 } else {
5471                         mv_lsb = 0;
5472                         mv_msb = 0;
5473                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5474                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5475                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5476                 }
5477         }
5478
5479         /**
5480          * if enable pool mirror, write related pool mask register,if disable
5481          * pool mirror, clear PFMRVM register
5482          */
5483         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5484                 mirror_type |= IXGBE_MRCTL_VPME;
5485                 if (on) {
5486                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5487                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5488                         mr_info->mr_conf[rule_id].pool_mask =
5489                                         mirror_conf->pool_mask;
5490
5491                 } else {
5492                         mp_lsb = 0;
5493                         mp_msb = 0;
5494                         mr_info->mr_conf[rule_id].pool_mask = 0;
5495                 }
5496         }
5497         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5498                 mirror_type |= IXGBE_MRCTL_UPME;
5499         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5500                 mirror_type |= IXGBE_MRCTL_DPME;
5501
5502         /* read  mirror control register and recalculate it */
5503         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5504
5505         if (on) {
5506                 mr_ctl |= mirror_type;
5507                 mr_ctl &= mirror_rule_mask;
5508                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5509         } else {
5510                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5511         }
5512
5513         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5514         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5515
5516         /* write mirrror control  register */
5517         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5518
5519         /* write pool mirrror control  register */
5520         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5521                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5522                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5523                                 mp_msb);
5524         }
5525         /* write VLAN mirrror control  register */
5526         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5527                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5528                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5529                                 mv_msb);
5530         }
5531
5532         return 0;
5533 }
5534
5535 static int
5536 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5537 {
5538         int mr_ctl = 0;
5539         uint32_t lsb_val = 0;
5540         uint32_t msb_val = 0;
5541         const uint8_t rule_mr_offset = 4;
5542
5543         struct ixgbe_hw *hw =
5544                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5545         struct ixgbe_mirror_info *mr_info =
5546                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5547
5548         if (ixgbe_vt_check(hw) < 0)
5549                 return -ENOTSUP;
5550
5551         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5552                 return -EINVAL;
5553
5554         memset(&mr_info->mr_conf[rule_id], 0,
5555                sizeof(struct rte_eth_mirror_conf));
5556
5557         /* clear PFVMCTL register */
5558         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5559
5560         /* clear pool mask register */
5561         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5562         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5563
5564         /* clear vlan mask register */
5565         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5566         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5567
5568         return 0;
5569 }
5570
5571 static int
5572 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5573 {
5574         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5575         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5576         uint32_t mask;
5577         struct ixgbe_hw *hw =
5578                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5579         uint32_t vec = IXGBE_MISC_VEC_ID;
5580
5581         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5582         if (rte_intr_allow_others(intr_handle))
5583                 vec = IXGBE_RX_VEC_START;
5584         mask |= (1 << vec);
5585         RTE_SET_USED(queue_id);
5586         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5587
5588         rte_intr_enable(intr_handle);
5589
5590         return 0;
5591 }
5592
5593 static int
5594 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5595 {
5596         uint32_t mask;
5597         struct ixgbe_hw *hw =
5598                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5599         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5600         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5601         uint32_t vec = IXGBE_MISC_VEC_ID;
5602
5603         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5604         if (rte_intr_allow_others(intr_handle))
5605                 vec = IXGBE_RX_VEC_START;
5606         mask &= ~(1 << vec);
5607         RTE_SET_USED(queue_id);
5608         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5609
5610         return 0;
5611 }
5612
5613 static int
5614 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5615 {
5616         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5617         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5618         uint32_t mask;
5619         struct ixgbe_hw *hw =
5620                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5621         struct ixgbe_interrupt *intr =
5622                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5623
5624         if (queue_id < 16) {
5625                 ixgbe_disable_intr(hw);
5626                 intr->mask |= (1 << queue_id);
5627                 ixgbe_enable_intr(dev);
5628         } else if (queue_id < 32) {
5629                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5630                 mask &= (1 << queue_id);
5631                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5632         } else if (queue_id < 64) {
5633                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5634                 mask &= (1 << (queue_id - 32));
5635                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5636         }
5637         rte_intr_enable(intr_handle);
5638
5639         return 0;
5640 }
5641
5642 static int
5643 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5644 {
5645         uint32_t mask;
5646         struct ixgbe_hw *hw =
5647                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5648         struct ixgbe_interrupt *intr =
5649                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5650
5651         if (queue_id < 16) {
5652                 ixgbe_disable_intr(hw);
5653                 intr->mask &= ~(1 << queue_id);
5654                 ixgbe_enable_intr(dev);
5655         } else if (queue_id < 32) {
5656                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5657                 mask &= ~(1 << queue_id);
5658                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5659         } else if (queue_id < 64) {
5660                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5661                 mask &= ~(1 << (queue_id - 32));
5662                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5663         }
5664
5665         return 0;
5666 }
5667
5668 static void
5669 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5670                      uint8_t queue, uint8_t msix_vector)
5671 {
5672         uint32_t tmp, idx;
5673
5674         if (direction == -1) {
5675                 /* other causes */
5676                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5677                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5678                 tmp &= ~0xFF;
5679                 tmp |= msix_vector;
5680                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5681         } else {
5682                 /* rx or tx cause */
5683                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5684                 idx = ((16 * (queue & 1)) + (8 * direction));
5685                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5686                 tmp &= ~(0xFF << idx);
5687                 tmp |= (msix_vector << idx);
5688                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5689         }
5690 }
5691
5692 /**
5693  * set the IVAR registers, mapping interrupt causes to vectors
5694  * @param hw
5695  *  pointer to ixgbe_hw struct
5696  * @direction
5697  *  0 for Rx, 1 for Tx, -1 for other causes
5698  * @queue
5699  *  queue to map the corresponding interrupt to
5700  * @msix_vector
5701  *  the vector to map to the corresponding queue
5702  */
5703 static void
5704 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5705                    uint8_t queue, uint8_t msix_vector)
5706 {
5707         uint32_t tmp, idx;
5708
5709         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5710         if (hw->mac.type == ixgbe_mac_82598EB) {
5711                 if (direction == -1)
5712                         direction = 0;
5713                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5714                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5715                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5716                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5717                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5718         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5719                         (hw->mac.type == ixgbe_mac_X540) ||
5720                         (hw->mac.type == ixgbe_mac_X550)) {
5721                 if (direction == -1) {
5722                         /* other causes */
5723                         idx = ((queue & 1) * 8);
5724                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5725                         tmp &= ~(0xFF << idx);
5726                         tmp |= (msix_vector << idx);
5727                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5728                 } else {
5729                         /* rx or tx causes */
5730                         idx = ((16 * (queue & 1)) + (8 * direction));
5731                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5732                         tmp &= ~(0xFF << idx);
5733                         tmp |= (msix_vector << idx);
5734                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5735                 }
5736         }
5737 }
5738
5739 static void
5740 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5741 {
5742         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5743         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5744         struct ixgbe_hw *hw =
5745                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746         uint32_t q_idx;
5747         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5748         uint32_t base = IXGBE_MISC_VEC_ID;
5749
5750         /* Configure VF other cause ivar */
5751         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5752
5753         /* won't configure msix register if no mapping is done
5754          * between intr vector and event fd.
5755          */
5756         if (!rte_intr_dp_is_en(intr_handle))
5757                 return;
5758
5759         if (rte_intr_allow_others(intr_handle)) {
5760                 base = IXGBE_RX_VEC_START;
5761                 vector_idx = IXGBE_RX_VEC_START;
5762         }
5763
5764         /* Configure all RX queues of VF */
5765         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5766                 /* Force all queue use vector 0,
5767                  * as IXGBE_VF_MAXMSIVECOTR = 1
5768                  */
5769                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5770                 intr_handle->intr_vec[q_idx] = vector_idx;
5771                 if (vector_idx < base + intr_handle->nb_efd - 1)
5772                         vector_idx++;
5773         }
5774 }
5775
5776 /**
5777  * Sets up the hardware to properly generate MSI-X interrupts
5778  * @hw
5779  *  board private structure
5780  */
5781 static void
5782 ixgbe_configure_msix(struct rte_eth_dev *dev)
5783 {
5784         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5785         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5786         struct ixgbe_hw *hw =
5787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5788         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5789         uint32_t vec = IXGBE_MISC_VEC_ID;
5790         uint32_t mask;
5791         uint32_t gpie;
5792
5793         /* won't configure msix register if no mapping is done
5794          * between intr vector and event fd
5795          */
5796         if (!rte_intr_dp_is_en(intr_handle))
5797                 return;
5798
5799         if (rte_intr_allow_others(intr_handle))
5800                 vec = base = IXGBE_RX_VEC_START;
5801
5802         /* setup GPIE for MSI-x mode */
5803         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5804         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5805                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5806         /* auto clearing and auto setting corresponding bits in EIMS
5807          * when MSI-X interrupt is triggered
5808          */
5809         if (hw->mac.type == ixgbe_mac_82598EB) {
5810                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5811         } else {
5812                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5813                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5814         }
5815         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5816
5817         /* Populate the IVAR table and set the ITR values to the
5818          * corresponding register.
5819          */
5820         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5821              queue_id++) {
5822                 /* by default, 1:1 mapping */
5823                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5824                 intr_handle->intr_vec[queue_id] = vec;
5825                 if (vec < base + intr_handle->nb_efd - 1)
5826                         vec++;
5827         }
5828
5829         switch (hw->mac.type) {
5830         case ixgbe_mac_82598EB:
5831                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5832                                    IXGBE_MISC_VEC_ID);
5833                 break;
5834         case ixgbe_mac_82599EB:
5835         case ixgbe_mac_X540:
5836         case ixgbe_mac_X550:
5837                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5838                 break;
5839         default:
5840                 break;
5841         }
5842         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5843                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5844
5845         /* set up to autoclear timer, and the vectors */
5846         mask = IXGBE_EIMS_ENABLE_MASK;
5847         mask &= ~(IXGBE_EIMS_OTHER |
5848                   IXGBE_EIMS_MAILBOX |
5849                   IXGBE_EIMS_LSC);
5850
5851         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5852 }
5853
5854 int
5855 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5856                            uint16_t queue_idx, uint16_t tx_rate)
5857 {
5858         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5859         uint32_t rf_dec, rf_int;
5860         uint32_t bcnrc_val;
5861         uint16_t link_speed = dev->data->dev_link.link_speed;
5862
5863         if (queue_idx >= hw->mac.max_tx_queues)
5864                 return -EINVAL;
5865
5866         if (tx_rate != 0) {
5867                 /* Calculate the rate factor values to set */
5868                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5869                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5870                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5871
5872                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5873                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5874                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5875                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5876         } else {
5877                 bcnrc_val = 0;
5878         }
5879
5880         /*
5881          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5882          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5883          * set as 0x4.
5884          */
5885         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5886                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5887                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5888                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5889                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5890         else
5891                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5892                         IXGBE_MMW_SIZE_DEFAULT);
5893
5894         /* Set RTTBCNRC of queue X */
5895         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5896         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5897         IXGBE_WRITE_FLUSH(hw);
5898
5899         return 0;
5900 }
5901
5902 static int
5903 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5904                      __attribute__((unused)) uint32_t index,
5905                      __attribute__((unused)) uint32_t pool)
5906 {
5907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5908         int diag;
5909
5910         /*
5911          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5912          * operation. Trap this case to avoid exhausting the [very limited]
5913          * set of PF resources used to store VF MAC addresses.
5914          */
5915         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5916                 return -1;
5917         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5918         if (diag != 0)
5919                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5920                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5921                             mac_addr->addr_bytes[0],
5922                             mac_addr->addr_bytes[1],
5923                             mac_addr->addr_bytes[2],
5924                             mac_addr->addr_bytes[3],
5925                             mac_addr->addr_bytes[4],
5926                             mac_addr->addr_bytes[5],
5927                             diag);
5928         return diag;
5929 }
5930
5931 static void
5932 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5933 {
5934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5935         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5936         struct ether_addr *mac_addr;
5937         uint32_t i;
5938         int diag;
5939
5940         /*
5941          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5942          * not support the deletion of a given MAC address.
5943          * Instead, it imposes to delete all MAC addresses, then to add again
5944          * all MAC addresses with the exception of the one to be deleted.
5945          */
5946         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5947
5948         /*
5949          * Add again all MAC addresses, with the exception of the deleted one
5950          * and of the permanent MAC address.
5951          */
5952         for (i = 0, mac_addr = dev->data->mac_addrs;
5953              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5954                 /* Skip the deleted MAC address */
5955                 if (i == index)
5956                         continue;
5957                 /* Skip NULL MAC addresses */
5958                 if (is_zero_ether_addr(mac_addr))
5959                         continue;
5960                 /* Skip the permanent MAC address */
5961                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5962                         continue;
5963                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5964                 if (diag != 0)
5965                         PMD_DRV_LOG(ERR,
5966                                     "Adding again MAC address "
5967                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5968                                     "diag=%d",
5969                                     mac_addr->addr_bytes[0],
5970                                     mac_addr->addr_bytes[1],
5971                                     mac_addr->addr_bytes[2],
5972                                     mac_addr->addr_bytes[3],
5973                                     mac_addr->addr_bytes[4],
5974                                     mac_addr->addr_bytes[5],
5975                                     diag);
5976         }
5977 }
5978
5979 static void
5980 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5981 {
5982         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5983
5984         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5985 }
5986
5987 int
5988 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5989                         struct rte_eth_syn_filter *filter,
5990                         bool add)
5991 {
5992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5993         struct ixgbe_filter_info *filter_info =
5994                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5995         uint32_t syn_info;
5996         uint32_t synqf;
5997
5998         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5999                 return -EINVAL;
6000
6001         syn_info = filter_info->syn_info;
6002
6003         if (add) {
6004                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6005                         return -EINVAL;
6006                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6007                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6008
6009                 if (filter->hig_pri)
6010                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6011                 else
6012                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6013         } else {
6014                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6015                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6016                         return -ENOENT;
6017                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6018         }
6019
6020         filter_info->syn_info = synqf;
6021         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6022         IXGBE_WRITE_FLUSH(hw);
6023         return 0;
6024 }
6025
6026 static int
6027 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6028                         struct rte_eth_syn_filter *filter)
6029 {
6030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6031         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6032
6033         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6034                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6035                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6036                 return 0;
6037         }
6038         return -ENOENT;
6039 }
6040
6041 static int
6042 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6043                         enum rte_filter_op filter_op,
6044                         void *arg)
6045 {
6046         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6047         int ret;
6048
6049         MAC_TYPE_FILTER_SUP(hw->mac.type);
6050
6051         if (filter_op == RTE_ETH_FILTER_NOP)
6052                 return 0;
6053
6054         if (arg == NULL) {
6055                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6056                             filter_op);
6057                 return -EINVAL;
6058         }
6059
6060         switch (filter_op) {
6061         case RTE_ETH_FILTER_ADD:
6062                 ret = ixgbe_syn_filter_set(dev,
6063                                 (struct rte_eth_syn_filter *)arg,
6064                                 TRUE);
6065                 break;
6066         case RTE_ETH_FILTER_DELETE:
6067                 ret = ixgbe_syn_filter_set(dev,
6068                                 (struct rte_eth_syn_filter *)arg,
6069                                 FALSE);
6070                 break;
6071         case RTE_ETH_FILTER_GET:
6072                 ret = ixgbe_syn_filter_get(dev,
6073                                 (struct rte_eth_syn_filter *)arg);
6074                 break;
6075         default:
6076                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6077                 ret = -EINVAL;
6078                 break;
6079         }
6080
6081         return ret;
6082 }
6083
6084
6085 static inline enum ixgbe_5tuple_protocol
6086 convert_protocol_type(uint8_t protocol_value)
6087 {
6088         if (protocol_value == IPPROTO_TCP)
6089                 return IXGBE_FILTER_PROTOCOL_TCP;
6090         else if (protocol_value == IPPROTO_UDP)
6091                 return IXGBE_FILTER_PROTOCOL_UDP;
6092         else if (protocol_value == IPPROTO_SCTP)
6093                 return IXGBE_FILTER_PROTOCOL_SCTP;
6094         else
6095                 return IXGBE_FILTER_PROTOCOL_NONE;
6096 }
6097
6098 /* inject a 5-tuple filter to HW */
6099 static inline void
6100 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6101                            struct ixgbe_5tuple_filter *filter)
6102 {
6103         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6104         int i;
6105         uint32_t ftqf, sdpqf;
6106         uint32_t l34timir = 0;
6107         uint8_t mask = 0xff;
6108
6109         i = filter->index;
6110
6111         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6112                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6113         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6114
6115         ftqf = (uint32_t)(filter->filter_info.proto &
6116                 IXGBE_FTQF_PROTOCOL_MASK);
6117         ftqf |= (uint32_t)((filter->filter_info.priority &
6118                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6119         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6120                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6121         if (filter->filter_info.dst_ip_mask == 0)
6122                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6123         if (filter->filter_info.src_port_mask == 0)
6124                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6125         if (filter->filter_info.dst_port_mask == 0)
6126                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6127         if (filter->filter_info.proto_mask == 0)
6128                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6129         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6130         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6131         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6132
6133         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6134         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6135         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6136         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6137
6138         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6139         l34timir |= (uint32_t)(filter->queue <<
6140                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6141         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6142 }
6143
6144 /*
6145  * add a 5tuple filter
6146  *
6147  * @param
6148  * dev: Pointer to struct rte_eth_dev.
6149  * index: the index the filter allocates.
6150  * filter: ponter to the filter that will be added.
6151  * rx_queue: the queue id the filter assigned to.
6152  *
6153  * @return
6154  *    - On success, zero.
6155  *    - On failure, a negative value.
6156  */
6157 static int
6158 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6159                         struct ixgbe_5tuple_filter *filter)
6160 {
6161         struct ixgbe_filter_info *filter_info =
6162                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6163         int i, idx, shift;
6164
6165         /*
6166          * look for an unused 5tuple filter index,
6167          * and insert the filter to list.
6168          */
6169         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6170                 idx = i / (sizeof(uint32_t) * NBBY);
6171                 shift = i % (sizeof(uint32_t) * NBBY);
6172                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6173                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6174                         filter->index = i;
6175                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6176                                           filter,
6177                                           entries);
6178                         break;
6179                 }
6180         }
6181         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6182                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6183                 return -ENOSYS;
6184         }
6185
6186         ixgbe_inject_5tuple_filter(dev, filter);
6187
6188         return 0;
6189 }
6190
6191 /*
6192  * remove a 5tuple filter
6193  *
6194  * @param
6195  * dev: Pointer to struct rte_eth_dev.
6196  * filter: the pointer of the filter will be removed.
6197  */
6198 static void
6199 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6200                         struct ixgbe_5tuple_filter *filter)
6201 {
6202         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6203         struct ixgbe_filter_info *filter_info =
6204                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6205         uint16_t index = filter->index;
6206
6207         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6208                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6209         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6210         rte_free(filter);
6211
6212         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6213         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6214         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6215         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6216         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6217 }
6218
6219 static int
6220 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6221 {
6222         struct ixgbe_hw *hw;
6223         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6224         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6225
6226         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6227
6228         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6229                 return -EINVAL;
6230
6231         /* refuse mtu that requires the support of scattered packets when this
6232          * feature has not been enabled before.
6233          */
6234         if (!rx_conf->enable_scatter &&
6235             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6236              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6237                 return -EINVAL;
6238
6239         /*
6240          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6241          * request of the version 2.0 of the mailbox API.
6242          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6243          * of the mailbox API.
6244          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6245          * prior to 3.11.33 which contains the following change:
6246          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6247          */
6248         ixgbevf_rlpml_set_vf(hw, max_frame);
6249
6250         /* update max frame size */
6251         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6252         return 0;
6253 }
6254
6255 static inline struct ixgbe_5tuple_filter *
6256 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6257                         struct ixgbe_5tuple_filter_info *key)
6258 {
6259         struct ixgbe_5tuple_filter *it;
6260
6261         TAILQ_FOREACH(it, filter_list, entries) {
6262                 if (memcmp(key, &it->filter_info,
6263                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6264                         return it;
6265                 }
6266         }
6267         return NULL;
6268 }
6269
6270 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6271 static inline int
6272 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6273                         struct ixgbe_5tuple_filter_info *filter_info)
6274 {
6275         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6276                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6277                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6278                 return -EINVAL;
6279
6280         switch (filter->dst_ip_mask) {
6281         case UINT32_MAX:
6282                 filter_info->dst_ip_mask = 0;
6283                 filter_info->dst_ip = filter->dst_ip;
6284                 break;
6285         case 0:
6286                 filter_info->dst_ip_mask = 1;
6287                 break;
6288         default:
6289                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6290                 return -EINVAL;
6291         }
6292
6293         switch (filter->src_ip_mask) {
6294         case UINT32_MAX:
6295                 filter_info->src_ip_mask = 0;
6296                 filter_info->src_ip = filter->src_ip;
6297                 break;
6298         case 0:
6299                 filter_info->src_ip_mask = 1;
6300                 break;
6301         default:
6302                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6303                 return -EINVAL;
6304         }
6305
6306         switch (filter->dst_port_mask) {
6307         case UINT16_MAX:
6308                 filter_info->dst_port_mask = 0;
6309                 filter_info->dst_port = filter->dst_port;
6310                 break;
6311         case 0:
6312                 filter_info->dst_port_mask = 1;
6313                 break;
6314         default:
6315                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6316                 return -EINVAL;
6317         }
6318
6319         switch (filter->src_port_mask) {
6320         case UINT16_MAX:
6321                 filter_info->src_port_mask = 0;
6322                 filter_info->src_port = filter->src_port;
6323                 break;
6324         case 0:
6325                 filter_info->src_port_mask = 1;
6326                 break;
6327         default:
6328                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6329                 return -EINVAL;
6330         }
6331
6332         switch (filter->proto_mask) {
6333         case UINT8_MAX:
6334                 filter_info->proto_mask = 0;
6335                 filter_info->proto =
6336                         convert_protocol_type(filter->proto);
6337                 break;
6338         case 0:
6339                 filter_info->proto_mask = 1;
6340                 break;
6341         default:
6342                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6343                 return -EINVAL;
6344         }
6345
6346         filter_info->priority = (uint8_t)filter->priority;
6347         return 0;
6348 }
6349
6350 /*
6351  * add or delete a ntuple filter
6352  *
6353  * @param
6354  * dev: Pointer to struct rte_eth_dev.
6355  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6356  * add: if true, add filter, if false, remove filter
6357  *
6358  * @return
6359  *    - On success, zero.
6360  *    - On failure, a negative value.
6361  */
6362 int
6363 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6364                         struct rte_eth_ntuple_filter *ntuple_filter,
6365                         bool add)
6366 {
6367         struct ixgbe_filter_info *filter_info =
6368                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6369         struct ixgbe_5tuple_filter_info filter_5tuple;
6370         struct ixgbe_5tuple_filter *filter;
6371         int ret;
6372
6373         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6374                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6375                 return -EINVAL;
6376         }
6377
6378         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6379         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6380         if (ret < 0)
6381                 return ret;
6382
6383         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6384                                          &filter_5tuple);
6385         if (filter != NULL && add) {
6386                 PMD_DRV_LOG(ERR, "filter exists.");
6387                 return -EEXIST;
6388         }
6389         if (filter == NULL && !add) {
6390                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6391                 return -ENOENT;
6392         }
6393
6394         if (add) {
6395                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6396                                 sizeof(struct ixgbe_5tuple_filter), 0);
6397                 if (filter == NULL)
6398                         return -ENOMEM;
6399                 rte_memcpy(&filter->filter_info,
6400                                  &filter_5tuple,
6401                                  sizeof(struct ixgbe_5tuple_filter_info));
6402                 filter->queue = ntuple_filter->queue;
6403                 ret = ixgbe_add_5tuple_filter(dev, filter);
6404                 if (ret < 0) {
6405                         rte_free(filter);
6406                         return ret;
6407                 }
6408         } else
6409                 ixgbe_remove_5tuple_filter(dev, filter);
6410
6411         return 0;
6412 }
6413
6414 /*
6415  * get a ntuple filter
6416  *
6417  * @param
6418  * dev: Pointer to struct rte_eth_dev.
6419  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6420  *
6421  * @return
6422  *    - On success, zero.
6423  *    - On failure, a negative value.
6424  */
6425 static int
6426 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6427                         struct rte_eth_ntuple_filter *ntuple_filter)
6428 {
6429         struct ixgbe_filter_info *filter_info =
6430                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6431         struct ixgbe_5tuple_filter_info filter_5tuple;
6432         struct ixgbe_5tuple_filter *filter;
6433         int ret;
6434
6435         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6436                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6437                 return -EINVAL;
6438         }
6439
6440         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6441         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6442         if (ret < 0)
6443                 return ret;
6444
6445         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6446                                          &filter_5tuple);
6447         if (filter == NULL) {
6448                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6449                 return -ENOENT;
6450         }
6451         ntuple_filter->queue = filter->queue;
6452         return 0;
6453 }
6454
6455 /*
6456  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6457  * @dev: pointer to rte_eth_dev structure
6458  * @filter_op:operation will be taken.
6459  * @arg: a pointer to specific structure corresponding to the filter_op
6460  *
6461  * @return
6462  *    - On success, zero.
6463  *    - On failure, a negative value.
6464  */
6465 static int
6466 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6467                                 enum rte_filter_op filter_op,
6468                                 void *arg)
6469 {
6470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6471         int ret;
6472
6473         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6474
6475         if (filter_op == RTE_ETH_FILTER_NOP)
6476                 return 0;
6477
6478         if (arg == NULL) {
6479                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6480                             filter_op);
6481                 return -EINVAL;
6482         }
6483
6484         switch (filter_op) {
6485         case RTE_ETH_FILTER_ADD:
6486                 ret = ixgbe_add_del_ntuple_filter(dev,
6487                         (struct rte_eth_ntuple_filter *)arg,
6488                         TRUE);
6489                 break;
6490         case RTE_ETH_FILTER_DELETE:
6491                 ret = ixgbe_add_del_ntuple_filter(dev,
6492                         (struct rte_eth_ntuple_filter *)arg,
6493                         FALSE);
6494                 break;
6495         case RTE_ETH_FILTER_GET:
6496                 ret = ixgbe_get_ntuple_filter(dev,
6497                         (struct rte_eth_ntuple_filter *)arg);
6498                 break;
6499         default:
6500                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6501                 ret = -EINVAL;
6502                 break;
6503         }
6504         return ret;
6505 }
6506
6507 int
6508 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6509                         struct rte_eth_ethertype_filter *filter,
6510                         bool add)
6511 {
6512         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6513         struct ixgbe_filter_info *filter_info =
6514                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6515         uint32_t etqf = 0;
6516         uint32_t etqs = 0;
6517         int ret;
6518         struct ixgbe_ethertype_filter ethertype_filter;
6519
6520         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6521                 return -EINVAL;
6522
6523         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6524                 filter->ether_type == ETHER_TYPE_IPv6) {
6525                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6526                         " ethertype filter.", filter->ether_type);
6527                 return -EINVAL;
6528         }
6529
6530         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6531                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6532                 return -EINVAL;
6533         }
6534         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6535                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6536                 return -EINVAL;
6537         }
6538
6539         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6540         if (ret >= 0 && add) {
6541                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6542                             filter->ether_type);
6543                 return -EEXIST;
6544         }
6545         if (ret < 0 && !add) {
6546                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6547                             filter->ether_type);
6548                 return -ENOENT;
6549         }
6550
6551         if (add) {
6552                 etqf = IXGBE_ETQF_FILTER_EN;
6553                 etqf |= (uint32_t)filter->ether_type;
6554                 etqs |= (uint32_t)((filter->queue <<
6555                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6556                                     IXGBE_ETQS_RX_QUEUE);
6557                 etqs |= IXGBE_ETQS_QUEUE_EN;
6558
6559                 ethertype_filter.ethertype = filter->ether_type;
6560                 ethertype_filter.etqf = etqf;
6561                 ethertype_filter.etqs = etqs;
6562                 ethertype_filter.conf = FALSE;
6563                 ret = ixgbe_ethertype_filter_insert(filter_info,
6564                                                     &ethertype_filter);
6565                 if (ret < 0) {
6566                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6567                         return -ENOSPC;
6568                 }
6569         } else {
6570                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6571                 if (ret < 0)
6572                         return -ENOSYS;
6573         }
6574         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6575         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6576         IXGBE_WRITE_FLUSH(hw);
6577
6578         return 0;
6579 }
6580
6581 static int
6582 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6583                         struct rte_eth_ethertype_filter *filter)
6584 {
6585         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6586         struct ixgbe_filter_info *filter_info =
6587                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6588         uint32_t etqf, etqs;
6589         int ret;
6590
6591         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6592         if (ret < 0) {
6593                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6594                             filter->ether_type);
6595                 return -ENOENT;
6596         }
6597
6598         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6599         if (etqf & IXGBE_ETQF_FILTER_EN) {
6600                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6601                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6602                 filter->flags = 0;
6603                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6604                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6605                 return 0;
6606         }
6607         return -ENOENT;
6608 }
6609
6610 /*
6611  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6612  * @dev: pointer to rte_eth_dev structure
6613  * @filter_op:operation will be taken.
6614  * @arg: a pointer to specific structure corresponding to the filter_op
6615  */
6616 static int
6617 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6618                                 enum rte_filter_op filter_op,
6619                                 void *arg)
6620 {
6621         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6622         int ret;
6623
6624         MAC_TYPE_FILTER_SUP(hw->mac.type);
6625
6626         if (filter_op == RTE_ETH_FILTER_NOP)
6627                 return 0;
6628
6629         if (arg == NULL) {
6630                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6631                             filter_op);
6632                 return -EINVAL;
6633         }
6634
6635         switch (filter_op) {
6636         case RTE_ETH_FILTER_ADD:
6637                 ret = ixgbe_add_del_ethertype_filter(dev,
6638                         (struct rte_eth_ethertype_filter *)arg,
6639                         TRUE);
6640                 break;
6641         case RTE_ETH_FILTER_DELETE:
6642                 ret = ixgbe_add_del_ethertype_filter(dev,
6643                         (struct rte_eth_ethertype_filter *)arg,
6644                         FALSE);
6645                 break;
6646         case RTE_ETH_FILTER_GET:
6647                 ret = ixgbe_get_ethertype_filter(dev,
6648                         (struct rte_eth_ethertype_filter *)arg);
6649                 break;
6650         default:
6651                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6652                 ret = -EINVAL;
6653                 break;
6654         }
6655         return ret;
6656 }
6657
6658 static int
6659 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6660                      enum rte_filter_type filter_type,
6661                      enum rte_filter_op filter_op,
6662                      void *arg)
6663 {
6664         int ret = 0;
6665
6666         switch (filter_type) {
6667         case RTE_ETH_FILTER_NTUPLE:
6668                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6669                 break;
6670         case RTE_ETH_FILTER_ETHERTYPE:
6671                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6672                 break;
6673         case RTE_ETH_FILTER_SYN:
6674                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6675                 break;
6676         case RTE_ETH_FILTER_FDIR:
6677                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6678                 break;
6679         case RTE_ETH_FILTER_L2_TUNNEL:
6680                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6681                 break;
6682         case RTE_ETH_FILTER_GENERIC:
6683                 if (filter_op != RTE_ETH_FILTER_GET)
6684                         return -EINVAL;
6685                 *(const void **)arg = &ixgbe_flow_ops;
6686                 break;
6687         default:
6688                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6689                                                         filter_type);
6690                 ret = -EINVAL;
6691                 break;
6692         }
6693
6694         return ret;
6695 }
6696
6697 static u8 *
6698 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6699                         u8 **mc_addr_ptr, u32 *vmdq)
6700 {
6701         u8 *mc_addr;
6702
6703         *vmdq = 0;
6704         mc_addr = *mc_addr_ptr;
6705         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6706         return mc_addr;
6707 }
6708
6709 static int
6710 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6711                           struct ether_addr *mc_addr_set,
6712                           uint32_t nb_mc_addr)
6713 {
6714         struct ixgbe_hw *hw;
6715         u8 *mc_addr_list;
6716
6717         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6718         mc_addr_list = (u8 *)mc_addr_set;
6719         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6720                                          ixgbe_dev_addr_list_itr, TRUE);
6721 }
6722
6723 static uint64_t
6724 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6725 {
6726         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6727         uint64_t systime_cycles;
6728
6729         switch (hw->mac.type) {
6730         case ixgbe_mac_X550:
6731         case ixgbe_mac_X550EM_x:
6732         case ixgbe_mac_X550EM_a:
6733                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6734                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6735                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6736                                 * NSEC_PER_SEC;
6737                 break;
6738         default:
6739                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6740                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6741                                 << 32;
6742         }
6743
6744         return systime_cycles;
6745 }
6746
6747 static uint64_t
6748 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6749 {
6750         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6751         uint64_t rx_tstamp_cycles;
6752
6753         switch (hw->mac.type) {
6754         case ixgbe_mac_X550:
6755         case ixgbe_mac_X550EM_x:
6756         case ixgbe_mac_X550EM_a:
6757                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6758                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6759                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6760                                 * NSEC_PER_SEC;
6761                 break;
6762         default:
6763                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6764                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6765                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6766                                 << 32;
6767         }
6768
6769         return rx_tstamp_cycles;
6770 }
6771
6772 static uint64_t
6773 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6774 {
6775         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6776         uint64_t tx_tstamp_cycles;
6777
6778         switch (hw->mac.type) {
6779         case ixgbe_mac_X550:
6780         case ixgbe_mac_X550EM_x:
6781         case ixgbe_mac_X550EM_a:
6782                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6783                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6784                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6785                                 * NSEC_PER_SEC;
6786                 break;
6787         default:
6788                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6789                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6790                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6791                                 << 32;
6792         }
6793
6794         return tx_tstamp_cycles;
6795 }
6796
6797 static void
6798 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6799 {
6800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6801         struct ixgbe_adapter *adapter =
6802                 (struct ixgbe_adapter *)dev->data->dev_private;
6803         struct rte_eth_link link;
6804         uint32_t incval = 0;
6805         uint32_t shift = 0;
6806
6807         /* Get current link speed. */
6808         memset(&link, 0, sizeof(link));
6809         ixgbe_dev_link_update(dev, 1);
6810         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6811
6812         switch (link.link_speed) {
6813         case ETH_SPEED_NUM_100M:
6814                 incval = IXGBE_INCVAL_100;
6815                 shift = IXGBE_INCVAL_SHIFT_100;
6816                 break;
6817         case ETH_SPEED_NUM_1G:
6818                 incval = IXGBE_INCVAL_1GB;
6819                 shift = IXGBE_INCVAL_SHIFT_1GB;
6820                 break;
6821         case ETH_SPEED_NUM_10G:
6822         default:
6823                 incval = IXGBE_INCVAL_10GB;
6824                 shift = IXGBE_INCVAL_SHIFT_10GB;
6825                 break;
6826         }
6827
6828         switch (hw->mac.type) {
6829         case ixgbe_mac_X550:
6830         case ixgbe_mac_X550EM_x:
6831         case ixgbe_mac_X550EM_a:
6832                 /* Independent of link speed. */
6833                 incval = 1;
6834                 /* Cycles read will be interpreted as ns. */
6835                 shift = 0;
6836                 /* Fall-through */
6837         case ixgbe_mac_X540:
6838                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6839                 break;
6840         case ixgbe_mac_82599EB:
6841                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6842                 shift -= IXGBE_INCVAL_SHIFT_82599;
6843                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6844                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6845                 break;
6846         default:
6847                 /* Not supported. */
6848                 return;
6849         }
6850
6851         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6852         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6853         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6854
6855         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6856         adapter->systime_tc.cc_shift = shift;
6857         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6858
6859         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6860         adapter->rx_tstamp_tc.cc_shift = shift;
6861         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6862
6863         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6864         adapter->tx_tstamp_tc.cc_shift = shift;
6865         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6866 }
6867
6868 static int
6869 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6870 {
6871         struct ixgbe_adapter *adapter =
6872                         (struct ixgbe_adapter *)dev->data->dev_private;
6873
6874         adapter->systime_tc.nsec += delta;
6875         adapter->rx_tstamp_tc.nsec += delta;
6876         adapter->tx_tstamp_tc.nsec += delta;
6877
6878         return 0;
6879 }
6880
6881 static int
6882 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6883 {
6884         uint64_t ns;
6885         struct ixgbe_adapter *adapter =
6886                         (struct ixgbe_adapter *)dev->data->dev_private;
6887
6888         ns = rte_timespec_to_ns(ts);
6889         /* Set the timecounters to a new value. */
6890         adapter->systime_tc.nsec = ns;
6891         adapter->rx_tstamp_tc.nsec = ns;
6892         adapter->tx_tstamp_tc.nsec = ns;
6893
6894         return 0;
6895 }
6896
6897 static int
6898 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6899 {
6900         uint64_t ns, systime_cycles;
6901         struct ixgbe_adapter *adapter =
6902                         (struct ixgbe_adapter *)dev->data->dev_private;
6903
6904         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6905         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6906         *ts = rte_ns_to_timespec(ns);
6907
6908         return 0;
6909 }
6910
6911 static int
6912 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6913 {
6914         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6915         uint32_t tsync_ctl;
6916         uint32_t tsauxc;
6917
6918         /* Stop the timesync system time. */
6919         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6920         /* Reset the timesync system time value. */
6921         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6922         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6923
6924         /* Enable system time for platforms where it isn't on by default. */
6925         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6926         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6927         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6928
6929         ixgbe_start_timecounters(dev);
6930
6931         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6932         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6933                         (ETHER_TYPE_1588 |
6934                          IXGBE_ETQF_FILTER_EN |
6935                          IXGBE_ETQF_1588));
6936
6937         /* Enable timestamping of received PTP packets. */
6938         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6939         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6940         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6941
6942         /* Enable timestamping of transmitted PTP packets. */
6943         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6944         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6945         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6946
6947         IXGBE_WRITE_FLUSH(hw);
6948
6949         return 0;
6950 }
6951
6952 static int
6953 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6954 {
6955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6956         uint32_t tsync_ctl;
6957
6958         /* Disable timestamping of transmitted PTP packets. */
6959         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6960         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6961         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6962
6963         /* Disable timestamping of received PTP packets. */
6964         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6965         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6966         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6967
6968         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6969         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6970
6971         /* Stop incrementating the System Time registers. */
6972         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6973
6974         return 0;
6975 }
6976
6977 static int
6978 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6979                                  struct timespec *timestamp,
6980                                  uint32_t flags __rte_unused)
6981 {
6982         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6983         struct ixgbe_adapter *adapter =
6984                 (struct ixgbe_adapter *)dev->data->dev_private;
6985         uint32_t tsync_rxctl;
6986         uint64_t rx_tstamp_cycles;
6987         uint64_t ns;
6988
6989         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6990         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6991                 return -EINVAL;
6992
6993         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6994         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6995         *timestamp = rte_ns_to_timespec(ns);
6996
6997         return  0;
6998 }
6999
7000 static int
7001 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7002                                  struct timespec *timestamp)
7003 {
7004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7005         struct ixgbe_adapter *adapter =
7006                 (struct ixgbe_adapter *)dev->data->dev_private;
7007         uint32_t tsync_txctl;
7008         uint64_t tx_tstamp_cycles;
7009         uint64_t ns;
7010
7011         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7012         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7013                 return -EINVAL;
7014
7015         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7016         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7017         *timestamp = rte_ns_to_timespec(ns);
7018
7019         return 0;
7020 }
7021
7022 static int
7023 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7024 {
7025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7026         int count = 0;
7027         int g_ind = 0;
7028         const struct reg_info *reg_group;
7029         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7030                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7031
7032         while ((reg_group = reg_set[g_ind++]))
7033                 count += ixgbe_regs_group_count(reg_group);
7034
7035         return count;
7036 }
7037
7038 static int
7039 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7040 {
7041         int count = 0;
7042         int g_ind = 0;
7043         const struct reg_info *reg_group;
7044
7045         while ((reg_group = ixgbevf_regs[g_ind++]))
7046                 count += ixgbe_regs_group_count(reg_group);
7047
7048         return count;
7049 }
7050
7051 static int
7052 ixgbe_get_regs(struct rte_eth_dev *dev,
7053               struct rte_dev_reg_info *regs)
7054 {
7055         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7056         uint32_t *data = regs->data;
7057         int g_ind = 0;
7058         int count = 0;
7059         const struct reg_info *reg_group;
7060         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7061                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7062
7063         if (data == NULL) {
7064                 regs->length = ixgbe_get_reg_length(dev);
7065                 regs->width = sizeof(uint32_t);
7066                 return 0;
7067         }
7068
7069         /* Support only full register dump */
7070         if ((regs->length == 0) ||
7071             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7072                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7073                         hw->device_id;
7074                 while ((reg_group = reg_set[g_ind++]))
7075                         count += ixgbe_read_regs_group(dev, &data[count],
7076                                 reg_group);
7077                 return 0;
7078         }
7079
7080         return -ENOTSUP;
7081 }
7082
7083 static int
7084 ixgbevf_get_regs(struct rte_eth_dev *dev,
7085                 struct rte_dev_reg_info *regs)
7086 {
7087         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7088         uint32_t *data = regs->data;
7089         int g_ind = 0;
7090         int count = 0;
7091         const struct reg_info *reg_group;
7092
7093         if (data == NULL) {
7094                 regs->length = ixgbevf_get_reg_length(dev);
7095                 regs->width = sizeof(uint32_t);
7096                 return 0;
7097         }
7098
7099         /* Support only full register dump */
7100         if ((regs->length == 0) ||
7101             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7102                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7103                         hw->device_id;
7104                 while ((reg_group = ixgbevf_regs[g_ind++]))
7105                         count += ixgbe_read_regs_group(dev, &data[count],
7106                                                       reg_group);
7107                 return 0;
7108         }
7109
7110         return -ENOTSUP;
7111 }
7112
7113 static int
7114 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7115 {
7116         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7117
7118         /* Return unit is byte count */
7119         return hw->eeprom.word_size * 2;
7120 }
7121
7122 static int
7123 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7124                 struct rte_dev_eeprom_info *in_eeprom)
7125 {
7126         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7127         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7128         uint16_t *data = in_eeprom->data;
7129         int first, length;
7130
7131         first = in_eeprom->offset >> 1;
7132         length = in_eeprom->length >> 1;
7133         if ((first > hw->eeprom.word_size) ||
7134             ((first + length) > hw->eeprom.word_size))
7135                 return -EINVAL;
7136
7137         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7138
7139         return eeprom->ops.read_buffer(hw, first, length, data);
7140 }
7141
7142 static int
7143 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7144                 struct rte_dev_eeprom_info *in_eeprom)
7145 {
7146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7147         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7148         uint16_t *data = in_eeprom->data;
7149         int first, length;
7150
7151         first = in_eeprom->offset >> 1;
7152         length = in_eeprom->length >> 1;
7153         if ((first > hw->eeprom.word_size) ||
7154             ((first + length) > hw->eeprom.word_size))
7155                 return -EINVAL;
7156
7157         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7158
7159         return eeprom->ops.write_buffer(hw,  first, length, data);
7160 }
7161
7162 uint16_t
7163 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7164         switch (mac_type) {
7165         case ixgbe_mac_X550:
7166         case ixgbe_mac_X550EM_x:
7167         case ixgbe_mac_X550EM_a:
7168                 return ETH_RSS_RETA_SIZE_512;
7169         case ixgbe_mac_X550_vf:
7170         case ixgbe_mac_X550EM_x_vf:
7171         case ixgbe_mac_X550EM_a_vf:
7172                 return ETH_RSS_RETA_SIZE_64;
7173         default:
7174                 return ETH_RSS_RETA_SIZE_128;
7175         }
7176 }
7177
7178 uint32_t
7179 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7180         switch (mac_type) {
7181         case ixgbe_mac_X550:
7182         case ixgbe_mac_X550EM_x:
7183         case ixgbe_mac_X550EM_a:
7184                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7185                         return IXGBE_RETA(reta_idx >> 2);
7186                 else
7187                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7188         case ixgbe_mac_X550_vf:
7189         case ixgbe_mac_X550EM_x_vf:
7190         case ixgbe_mac_X550EM_a_vf:
7191                 return IXGBE_VFRETA(reta_idx >> 2);
7192         default:
7193                 return IXGBE_RETA(reta_idx >> 2);
7194         }
7195 }
7196
7197 uint32_t
7198 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7199         switch (mac_type) {
7200         case ixgbe_mac_X550_vf:
7201         case ixgbe_mac_X550EM_x_vf:
7202         case ixgbe_mac_X550EM_a_vf:
7203                 return IXGBE_VFMRQC;
7204         default:
7205                 return IXGBE_MRQC;
7206         }
7207 }
7208
7209 uint32_t
7210 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7211         switch (mac_type) {
7212         case ixgbe_mac_X550_vf:
7213         case ixgbe_mac_X550EM_x_vf:
7214         case ixgbe_mac_X550EM_a_vf:
7215                 return IXGBE_VFRSSRK(i);
7216         default:
7217                 return IXGBE_RSSRK(i);
7218         }
7219 }
7220
7221 bool
7222 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7223         switch (mac_type) {
7224         case ixgbe_mac_82599_vf:
7225         case ixgbe_mac_X540_vf:
7226                 return 0;
7227         default:
7228                 return 1;
7229         }
7230 }
7231
7232 static int
7233 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7234                         struct rte_eth_dcb_info *dcb_info)
7235 {
7236         struct ixgbe_dcb_config *dcb_config =
7237                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7238         struct ixgbe_dcb_tc_config *tc;
7239         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7240         uint8_t nb_tcs;
7241         uint8_t i, j;
7242
7243         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7244                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7245         else
7246                 dcb_info->nb_tcs = 1;
7247
7248         tc_queue = &dcb_info->tc_queue;
7249         nb_tcs = dcb_info->nb_tcs;
7250
7251         if (dcb_config->vt_mode) { /* vt is enabled*/
7252                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7253                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7254                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7255                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7256                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7257                         for (j = 0; j < nb_tcs; j++) {
7258                                 tc_queue->tc_rxq[0][j].base = j;
7259                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7260                                 tc_queue->tc_txq[0][j].base = j;
7261                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7262                         }
7263                 } else {
7264                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7265                                 for (j = 0; j < nb_tcs; j++) {
7266                                         tc_queue->tc_rxq[i][j].base =
7267                                                 i * nb_tcs + j;
7268                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7269                                         tc_queue->tc_txq[i][j].base =
7270                                                 i * nb_tcs + j;
7271                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7272                                 }
7273                         }
7274                 }
7275         } else { /* vt is disabled*/
7276                 struct rte_eth_dcb_rx_conf *rx_conf =
7277                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7278                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7279                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7280                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7281                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7282                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7283                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7284                         }
7285                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7286                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7287                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7288                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7289                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7290                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7291                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7292                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7293                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7294                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7295                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7296                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7297                         }
7298                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7299                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7300                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7301                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7302                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7303                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7304                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7305                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7306                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7307                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7308                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7309                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7310                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7311                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7312                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7313                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7314                 }
7315         }
7316         for (i = 0; i < dcb_info->nb_tcs; i++) {
7317                 tc = &dcb_config->tc_config[i];
7318                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7319         }
7320         return 0;
7321 }
7322
7323 /* Update e-tag ether type */
7324 static int
7325 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7326                             uint16_t ether_type)
7327 {
7328         uint32_t etag_etype;
7329
7330         if (hw->mac.type != ixgbe_mac_X550 &&
7331             hw->mac.type != ixgbe_mac_X550EM_x &&
7332             hw->mac.type != ixgbe_mac_X550EM_a) {
7333                 return -ENOTSUP;
7334         }
7335
7336         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7337         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7338         etag_etype |= ether_type;
7339         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7340         IXGBE_WRITE_FLUSH(hw);
7341
7342         return 0;
7343 }
7344
7345 /* Config l2 tunnel ether type */
7346 static int
7347 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7348                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7349 {
7350         int ret = 0;
7351         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7352         struct ixgbe_l2_tn_info *l2_tn_info =
7353                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7354
7355         if (l2_tunnel == NULL)
7356                 return -EINVAL;
7357
7358         switch (l2_tunnel->l2_tunnel_type) {
7359         case RTE_L2_TUNNEL_TYPE_E_TAG:
7360                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7361                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7362                 break;
7363         default:
7364                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7365                 ret = -EINVAL;
7366                 break;
7367         }
7368
7369         return ret;
7370 }
7371
7372 /* Enable e-tag tunnel */
7373 static int
7374 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7375 {
7376         uint32_t etag_etype;
7377
7378         if (hw->mac.type != ixgbe_mac_X550 &&
7379             hw->mac.type != ixgbe_mac_X550EM_x &&
7380             hw->mac.type != ixgbe_mac_X550EM_a) {
7381                 return -ENOTSUP;
7382         }
7383
7384         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7385         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7386         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7387         IXGBE_WRITE_FLUSH(hw);
7388
7389         return 0;
7390 }
7391
7392 /* Enable l2 tunnel */
7393 static int
7394 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7395                            enum rte_eth_tunnel_type l2_tunnel_type)
7396 {
7397         int ret = 0;
7398         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7399         struct ixgbe_l2_tn_info *l2_tn_info =
7400                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7401
7402         switch (l2_tunnel_type) {
7403         case RTE_L2_TUNNEL_TYPE_E_TAG:
7404                 l2_tn_info->e_tag_en = TRUE;
7405                 ret = ixgbe_e_tag_enable(hw);
7406                 break;
7407         default:
7408                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7409                 ret = -EINVAL;
7410                 break;
7411         }
7412
7413         return ret;
7414 }
7415
7416 /* Disable e-tag tunnel */
7417 static int
7418 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7419 {
7420         uint32_t etag_etype;
7421
7422         if (hw->mac.type != ixgbe_mac_X550 &&
7423             hw->mac.type != ixgbe_mac_X550EM_x &&
7424             hw->mac.type != ixgbe_mac_X550EM_a) {
7425                 return -ENOTSUP;
7426         }
7427
7428         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7429         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7430         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7431         IXGBE_WRITE_FLUSH(hw);
7432
7433         return 0;
7434 }
7435
7436 /* Disable l2 tunnel */
7437 static int
7438 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7439                             enum rte_eth_tunnel_type l2_tunnel_type)
7440 {
7441         int ret = 0;
7442         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7443         struct ixgbe_l2_tn_info *l2_tn_info =
7444                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7445
7446         switch (l2_tunnel_type) {
7447         case RTE_L2_TUNNEL_TYPE_E_TAG:
7448                 l2_tn_info->e_tag_en = FALSE;
7449                 ret = ixgbe_e_tag_disable(hw);
7450                 break;
7451         default:
7452                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7453                 ret = -EINVAL;
7454                 break;
7455         }
7456
7457         return ret;
7458 }
7459
7460 static int
7461 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7462                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7463 {
7464         int ret = 0;
7465         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7466         uint32_t i, rar_entries;
7467         uint32_t rar_low, rar_high;
7468
7469         if (hw->mac.type != ixgbe_mac_X550 &&
7470             hw->mac.type != ixgbe_mac_X550EM_x &&
7471             hw->mac.type != ixgbe_mac_X550EM_a) {
7472                 return -ENOTSUP;
7473         }
7474
7475         rar_entries = ixgbe_get_num_rx_addrs(hw);
7476
7477         for (i = 1; i < rar_entries; i++) {
7478                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7479                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7480                 if ((rar_high & IXGBE_RAH_AV) &&
7481                     (rar_high & IXGBE_RAH_ADTYPE) &&
7482                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7483                      l2_tunnel->tunnel_id)) {
7484                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7485                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7486
7487                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7488
7489                         return ret;
7490                 }
7491         }
7492
7493         return ret;
7494 }
7495
7496 static int
7497 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7498                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7499 {
7500         int ret = 0;
7501         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7502         uint32_t i, rar_entries;
7503         uint32_t rar_low, rar_high;
7504
7505         if (hw->mac.type != ixgbe_mac_X550 &&
7506             hw->mac.type != ixgbe_mac_X550EM_x &&
7507             hw->mac.type != ixgbe_mac_X550EM_a) {
7508                 return -ENOTSUP;
7509         }
7510
7511         /* One entry for one tunnel. Try to remove potential existing entry. */
7512         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7513
7514         rar_entries = ixgbe_get_num_rx_addrs(hw);
7515
7516         for (i = 1; i < rar_entries; i++) {
7517                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7518                 if (rar_high & IXGBE_RAH_AV) {
7519                         continue;
7520                 } else {
7521                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7522                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7523                         rar_low = l2_tunnel->tunnel_id;
7524
7525                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7526                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7527
7528                         return ret;
7529                 }
7530         }
7531
7532         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7533                      " Please remove a rule before adding a new one.");
7534         return -EINVAL;
7535 }
7536
7537 static inline struct ixgbe_l2_tn_filter *
7538 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7539                           struct ixgbe_l2_tn_key *key)
7540 {
7541         int ret;
7542
7543         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7544         if (ret < 0)
7545                 return NULL;
7546
7547         return l2_tn_info->hash_map[ret];
7548 }
7549
7550 static inline int
7551 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7552                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7553 {
7554         int ret;
7555
7556         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7557                                &l2_tn_filter->key);
7558
7559         if (ret < 0) {
7560                 PMD_DRV_LOG(ERR,
7561                             "Failed to insert L2 tunnel filter"
7562                             " to hash table %d!",
7563                             ret);
7564                 return ret;
7565         }
7566
7567         l2_tn_info->hash_map[ret] = l2_tn_filter;
7568
7569         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7570
7571         return 0;
7572 }
7573
7574 static inline int
7575 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7576                           struct ixgbe_l2_tn_key *key)
7577 {
7578         int ret;
7579         struct ixgbe_l2_tn_filter *l2_tn_filter;
7580
7581         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7582
7583         if (ret < 0) {
7584                 PMD_DRV_LOG(ERR,
7585                             "No such L2 tunnel filter to delete %d!",
7586                             ret);
7587                 return ret;
7588         }
7589
7590         l2_tn_filter = l2_tn_info->hash_map[ret];
7591         l2_tn_info->hash_map[ret] = NULL;
7592
7593         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7594         rte_free(l2_tn_filter);
7595
7596         return 0;
7597 }
7598
7599 /* Add l2 tunnel filter */
7600 int
7601 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7602                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7603                                bool restore)
7604 {
7605         int ret;
7606         struct ixgbe_l2_tn_info *l2_tn_info =
7607                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7608         struct ixgbe_l2_tn_key key;
7609         struct ixgbe_l2_tn_filter *node;
7610
7611         if (!restore) {
7612                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7613                 key.tn_id = l2_tunnel->tunnel_id;
7614
7615                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7616
7617                 if (node) {
7618                         PMD_DRV_LOG(ERR,
7619                                     "The L2 tunnel filter already exists!");
7620                         return -EINVAL;
7621                 }
7622
7623                 node = rte_zmalloc("ixgbe_l2_tn",
7624                                    sizeof(struct ixgbe_l2_tn_filter),
7625                                    0);
7626                 if (!node)
7627                         return -ENOMEM;
7628
7629                 rte_memcpy(&node->key,
7630                                  &key,
7631                                  sizeof(struct ixgbe_l2_tn_key));
7632                 node->pool = l2_tunnel->pool;
7633                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7634                 if (ret < 0) {
7635                         rte_free(node);
7636                         return ret;
7637                 }
7638         }
7639
7640         switch (l2_tunnel->l2_tunnel_type) {
7641         case RTE_L2_TUNNEL_TYPE_E_TAG:
7642                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7643                 break;
7644         default:
7645                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7646                 ret = -EINVAL;
7647                 break;
7648         }
7649
7650         if ((!restore) && (ret < 0))
7651                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7652
7653         return ret;
7654 }
7655
7656 /* Delete l2 tunnel filter */
7657 int
7658 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7659                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7660 {
7661         int ret;
7662         struct ixgbe_l2_tn_info *l2_tn_info =
7663                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7664         struct ixgbe_l2_tn_key key;
7665
7666         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7667         key.tn_id = l2_tunnel->tunnel_id;
7668         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7669         if (ret < 0)
7670                 return ret;
7671
7672         switch (l2_tunnel->l2_tunnel_type) {
7673         case RTE_L2_TUNNEL_TYPE_E_TAG:
7674                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7675                 break;
7676         default:
7677                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7678                 ret = -EINVAL;
7679                 break;
7680         }
7681
7682         return ret;
7683 }
7684
7685 /**
7686  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7687  * @dev: pointer to rte_eth_dev structure
7688  * @filter_op:operation will be taken.
7689  * @arg: a pointer to specific structure corresponding to the filter_op
7690  */
7691 static int
7692 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7693                                   enum rte_filter_op filter_op,
7694                                   void *arg)
7695 {
7696         int ret;
7697
7698         if (filter_op == RTE_ETH_FILTER_NOP)
7699                 return 0;
7700
7701         if (arg == NULL) {
7702                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7703                             filter_op);
7704                 return -EINVAL;
7705         }
7706
7707         switch (filter_op) {
7708         case RTE_ETH_FILTER_ADD:
7709                 ret = ixgbe_dev_l2_tunnel_filter_add
7710                         (dev,
7711                          (struct rte_eth_l2_tunnel_conf *)arg,
7712                          FALSE);
7713                 break;
7714         case RTE_ETH_FILTER_DELETE:
7715                 ret = ixgbe_dev_l2_tunnel_filter_del
7716                         (dev,
7717                          (struct rte_eth_l2_tunnel_conf *)arg);
7718                 break;
7719         default:
7720                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7721                 ret = -EINVAL;
7722                 break;
7723         }
7724         return ret;
7725 }
7726
7727 static int
7728 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7729 {
7730         int ret = 0;
7731         uint32_t ctrl;
7732         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7733
7734         if (hw->mac.type != ixgbe_mac_X550 &&
7735             hw->mac.type != ixgbe_mac_X550EM_x &&
7736             hw->mac.type != ixgbe_mac_X550EM_a) {
7737                 return -ENOTSUP;
7738         }
7739
7740         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7741         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7742         if (en)
7743                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7744         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7745
7746         return ret;
7747 }
7748
7749 /* Enable l2 tunnel forwarding */
7750 static int
7751 ixgbe_dev_l2_tunnel_forwarding_enable
7752         (struct rte_eth_dev *dev,
7753          enum rte_eth_tunnel_type l2_tunnel_type)
7754 {
7755         struct ixgbe_l2_tn_info *l2_tn_info =
7756                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7757         int ret = 0;
7758
7759         switch (l2_tunnel_type) {
7760         case RTE_L2_TUNNEL_TYPE_E_TAG:
7761                 l2_tn_info->e_tag_fwd_en = TRUE;
7762                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7763                 break;
7764         default:
7765                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7766                 ret = -EINVAL;
7767                 break;
7768         }
7769
7770         return ret;
7771 }
7772
7773 /* Disable l2 tunnel forwarding */
7774 static int
7775 ixgbe_dev_l2_tunnel_forwarding_disable
7776         (struct rte_eth_dev *dev,
7777          enum rte_eth_tunnel_type l2_tunnel_type)
7778 {
7779         struct ixgbe_l2_tn_info *l2_tn_info =
7780                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7781         int ret = 0;
7782
7783         switch (l2_tunnel_type) {
7784         case RTE_L2_TUNNEL_TYPE_E_TAG:
7785                 l2_tn_info->e_tag_fwd_en = FALSE;
7786                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7787                 break;
7788         default:
7789                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7790                 ret = -EINVAL;
7791                 break;
7792         }
7793
7794         return ret;
7795 }
7796
7797 static int
7798 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7799                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7800                              bool en)
7801 {
7802         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7803         int ret = 0;
7804         uint32_t vmtir, vmvir;
7805         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7806
7807         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7808                 PMD_DRV_LOG(ERR,
7809                             "VF id %u should be less than %u",
7810                             l2_tunnel->vf_id,
7811                             pci_dev->max_vfs);
7812                 return -EINVAL;
7813         }
7814
7815         if (hw->mac.type != ixgbe_mac_X550 &&
7816             hw->mac.type != ixgbe_mac_X550EM_x &&
7817             hw->mac.type != ixgbe_mac_X550EM_a) {
7818                 return -ENOTSUP;
7819         }
7820
7821         if (en)
7822                 vmtir = l2_tunnel->tunnel_id;
7823         else
7824                 vmtir = 0;
7825
7826         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7827
7828         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7829         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7830         if (en)
7831                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7832         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7833
7834         return ret;
7835 }
7836
7837 /* Enable l2 tunnel tag insertion */
7838 static int
7839 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7840                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7841 {
7842         int ret = 0;
7843
7844         switch (l2_tunnel->l2_tunnel_type) {
7845         case RTE_L2_TUNNEL_TYPE_E_TAG:
7846                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7847                 break;
7848         default:
7849                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7850                 ret = -EINVAL;
7851                 break;
7852         }
7853
7854         return ret;
7855 }
7856
7857 /* Disable l2 tunnel tag insertion */
7858 static int
7859 ixgbe_dev_l2_tunnel_insertion_disable
7860         (struct rte_eth_dev *dev,
7861          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7862 {
7863         int ret = 0;
7864
7865         switch (l2_tunnel->l2_tunnel_type) {
7866         case RTE_L2_TUNNEL_TYPE_E_TAG:
7867                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7868                 break;
7869         default:
7870                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7871                 ret = -EINVAL;
7872                 break;
7873         }
7874
7875         return ret;
7876 }
7877
7878 static int
7879 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7880                              bool en)
7881 {
7882         int ret = 0;
7883         uint32_t qde;
7884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7885
7886         if (hw->mac.type != ixgbe_mac_X550 &&
7887             hw->mac.type != ixgbe_mac_X550EM_x &&
7888             hw->mac.type != ixgbe_mac_X550EM_a) {
7889                 return -ENOTSUP;
7890         }
7891
7892         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7893         if (en)
7894                 qde |= IXGBE_QDE_STRIP_TAG;
7895         else
7896                 qde &= ~IXGBE_QDE_STRIP_TAG;
7897         qde &= ~IXGBE_QDE_READ;
7898         qde |= IXGBE_QDE_WRITE;
7899         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7900
7901         return ret;
7902 }
7903
7904 /* Enable l2 tunnel tag stripping */
7905 static int
7906 ixgbe_dev_l2_tunnel_stripping_enable
7907         (struct rte_eth_dev *dev,
7908          enum rte_eth_tunnel_type l2_tunnel_type)
7909 {
7910         int ret = 0;
7911
7912         switch (l2_tunnel_type) {
7913         case RTE_L2_TUNNEL_TYPE_E_TAG:
7914                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7915                 break;
7916         default:
7917                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7918                 ret = -EINVAL;
7919                 break;
7920         }
7921
7922         return ret;
7923 }
7924
7925 /* Disable l2 tunnel tag stripping */
7926 static int
7927 ixgbe_dev_l2_tunnel_stripping_disable
7928         (struct rte_eth_dev *dev,
7929          enum rte_eth_tunnel_type l2_tunnel_type)
7930 {
7931         int ret = 0;
7932
7933         switch (l2_tunnel_type) {
7934         case RTE_L2_TUNNEL_TYPE_E_TAG:
7935                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7936                 break;
7937         default:
7938                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7939                 ret = -EINVAL;
7940                 break;
7941         }
7942
7943         return ret;
7944 }
7945
7946 /* Enable/disable l2 tunnel offload functions */
7947 static int
7948 ixgbe_dev_l2_tunnel_offload_set
7949         (struct rte_eth_dev *dev,
7950          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7951          uint32_t mask,
7952          uint8_t en)
7953 {
7954         int ret = 0;
7955
7956         if (l2_tunnel == NULL)
7957                 return -EINVAL;
7958
7959         ret = -EINVAL;
7960         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7961                 if (en)
7962                         ret = ixgbe_dev_l2_tunnel_enable(
7963                                 dev,
7964                                 l2_tunnel->l2_tunnel_type);
7965                 else
7966                         ret = ixgbe_dev_l2_tunnel_disable(
7967                                 dev,
7968                                 l2_tunnel->l2_tunnel_type);
7969         }
7970
7971         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7972                 if (en)
7973                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7974                                 dev,
7975                                 l2_tunnel);
7976                 else
7977                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7978                                 dev,
7979                                 l2_tunnel);
7980         }
7981
7982         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7983                 if (en)
7984                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7985                                 dev,
7986                                 l2_tunnel->l2_tunnel_type);
7987                 else
7988                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7989                                 dev,
7990                                 l2_tunnel->l2_tunnel_type);
7991         }
7992
7993         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7994                 if (en)
7995                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7996                                 dev,
7997                                 l2_tunnel->l2_tunnel_type);
7998                 else
7999                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8000                                 dev,
8001                                 l2_tunnel->l2_tunnel_type);
8002         }
8003
8004         return ret;
8005 }
8006
8007 static int
8008 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8009                         uint16_t port)
8010 {
8011         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8012         IXGBE_WRITE_FLUSH(hw);
8013
8014         return 0;
8015 }
8016
8017 /* There's only one register for VxLAN UDP port.
8018  * So, we cannot add several ports. Will update it.
8019  */
8020 static int
8021 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8022                      uint16_t port)
8023 {
8024         if (port == 0) {
8025                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8026                 return -EINVAL;
8027         }
8028
8029         return ixgbe_update_vxlan_port(hw, port);
8030 }
8031
8032 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8033  * UDP port, it must have a value.
8034  * So, will reset it to the original value 0.
8035  */
8036 static int
8037 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8038                      uint16_t port)
8039 {
8040         uint16_t cur_port;
8041
8042         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8043
8044         if (cur_port != port) {
8045                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8046                 return -EINVAL;
8047         }
8048
8049         return ixgbe_update_vxlan_port(hw, 0);
8050 }
8051
8052 /* Add UDP tunneling port */
8053 static int
8054 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8055                               struct rte_eth_udp_tunnel *udp_tunnel)
8056 {
8057         int ret = 0;
8058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8059
8060         if (hw->mac.type != ixgbe_mac_X550 &&
8061             hw->mac.type != ixgbe_mac_X550EM_x &&
8062             hw->mac.type != ixgbe_mac_X550EM_a) {
8063                 return -ENOTSUP;
8064         }
8065
8066         if (udp_tunnel == NULL)
8067                 return -EINVAL;
8068
8069         switch (udp_tunnel->prot_type) {
8070         case RTE_TUNNEL_TYPE_VXLAN:
8071                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8072                 break;
8073
8074         case RTE_TUNNEL_TYPE_GENEVE:
8075         case RTE_TUNNEL_TYPE_TEREDO:
8076                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8077                 ret = -EINVAL;
8078                 break;
8079
8080         default:
8081                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8082                 ret = -EINVAL;
8083                 break;
8084         }
8085
8086         return ret;
8087 }
8088
8089 /* Remove UDP tunneling port */
8090 static int
8091 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8092                               struct rte_eth_udp_tunnel *udp_tunnel)
8093 {
8094         int ret = 0;
8095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8096
8097         if (hw->mac.type != ixgbe_mac_X550 &&
8098             hw->mac.type != ixgbe_mac_X550EM_x &&
8099             hw->mac.type != ixgbe_mac_X550EM_a) {
8100                 return -ENOTSUP;
8101         }
8102
8103         if (udp_tunnel == NULL)
8104                 return -EINVAL;
8105
8106         switch (udp_tunnel->prot_type) {
8107         case RTE_TUNNEL_TYPE_VXLAN:
8108                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8109                 break;
8110         case RTE_TUNNEL_TYPE_GENEVE:
8111         case RTE_TUNNEL_TYPE_TEREDO:
8112                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8113                 ret = -EINVAL;
8114                 break;
8115         default:
8116                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8117                 ret = -EINVAL;
8118                 break;
8119         }
8120
8121         return ret;
8122 }
8123
8124 static void
8125 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8126 {
8127         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8128
8129         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8130 }
8131
8132 static void
8133 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8134 {
8135         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8136
8137         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8138 }
8139
8140 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8141 {
8142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8143         u32 in_msg = 0;
8144
8145         /* peek the message first */
8146         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8147
8148         /* PF reset VF event */
8149         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8150                 /* dummy mbx read to ack pf */
8151                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8152                         return;
8153                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8154                                               NULL);
8155         }
8156 }
8157
8158 static int
8159 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8160 {
8161         uint32_t eicr;
8162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8163         struct ixgbe_interrupt *intr =
8164                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8165         ixgbevf_intr_disable(hw);
8166
8167         /* read-on-clear nic registers here */
8168         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8169         intr->flags = 0;
8170
8171         /* only one misc vector supported - mailbox */
8172         eicr &= IXGBE_VTEICR_MASK;
8173         if (eicr == IXGBE_MISC_VEC_ID)
8174                 intr->flags |= IXGBE_FLAG_MAILBOX;
8175
8176         return 0;
8177 }
8178
8179 static int
8180 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8181 {
8182         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8183         struct ixgbe_interrupt *intr =
8184                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8185
8186         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8187                 ixgbevf_mbx_process(dev);
8188                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8189         }
8190
8191         ixgbevf_intr_enable(hw);
8192
8193         return 0;
8194 }
8195
8196 static void
8197 ixgbevf_dev_interrupt_handler(void *param)
8198 {
8199         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8200
8201         ixgbevf_dev_interrupt_get_status(dev);
8202         ixgbevf_dev_interrupt_action(dev);
8203 }
8204
8205 /**
8206  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8207  *  @hw: pointer to hardware structure
8208  *
8209  *  Stops the transmit data path and waits for the HW to internally empty
8210  *  the Tx security block
8211  **/
8212 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8213 {
8214 #define IXGBE_MAX_SECTX_POLL 40
8215
8216         int i;
8217         int sectxreg;
8218
8219         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8220         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8221         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8222         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8223                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8224                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8225                         break;
8226                 /* Use interrupt-safe sleep just in case */
8227                 usec_delay(1000);
8228         }
8229
8230         /* For informational purposes only */
8231         if (i >= IXGBE_MAX_SECTX_POLL)
8232                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8233                          "path fully disabled.  Continuing with init.");
8234
8235         return IXGBE_SUCCESS;
8236 }
8237
8238 /**
8239  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8240  *  @hw: pointer to hardware structure
8241  *
8242  *  Enables the transmit data path.
8243  **/
8244 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8245 {
8246         uint32_t sectxreg;
8247
8248         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8249         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8250         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8251         IXGBE_WRITE_FLUSH(hw);
8252
8253         return IXGBE_SUCCESS;
8254 }
8255
8256 /* restore n-tuple filter */
8257 static inline void
8258 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8259 {
8260         struct ixgbe_filter_info *filter_info =
8261                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8262         struct ixgbe_5tuple_filter *node;
8263
8264         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8265                 ixgbe_inject_5tuple_filter(dev, node);
8266         }
8267 }
8268
8269 /* restore ethernet type filter */
8270 static inline void
8271 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8272 {
8273         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8274         struct ixgbe_filter_info *filter_info =
8275                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8276         int i;
8277
8278         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8279                 if (filter_info->ethertype_mask & (1 << i)) {
8280                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8281                                         filter_info->ethertype_filters[i].etqf);
8282                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8283                                         filter_info->ethertype_filters[i].etqs);
8284                         IXGBE_WRITE_FLUSH(hw);
8285                 }
8286         }
8287 }
8288
8289 /* restore SYN filter */
8290 static inline void
8291 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8292 {
8293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8294         struct ixgbe_filter_info *filter_info =
8295                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8296         uint32_t synqf;
8297
8298         synqf = filter_info->syn_info;
8299
8300         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8301                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8302                 IXGBE_WRITE_FLUSH(hw);
8303         }
8304 }
8305
8306 /* restore L2 tunnel filter */
8307 static inline void
8308 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8309 {
8310         struct ixgbe_l2_tn_info *l2_tn_info =
8311                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8312         struct ixgbe_l2_tn_filter *node;
8313         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8314
8315         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8316                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8317                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8318                 l2_tn_conf.pool           = node->pool;
8319                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8320         }
8321 }
8322
8323 /* restore rss filter */
8324 static inline void
8325 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8326 {
8327         struct ixgbe_filter_info *filter_info =
8328                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8329
8330         if (filter_info->rss_info.num)
8331                 ixgbe_config_rss_filter(dev,
8332                         &filter_info->rss_info, TRUE);
8333 }
8334
8335 static int
8336 ixgbe_filter_restore(struct rte_eth_dev *dev)
8337 {
8338         ixgbe_ntuple_filter_restore(dev);
8339         ixgbe_ethertype_filter_restore(dev);
8340         ixgbe_syn_filter_restore(dev);
8341         ixgbe_fdir_filter_restore(dev);
8342         ixgbe_l2_tn_filter_restore(dev);
8343         ixgbe_rss_filter_restore(dev);
8344
8345         return 0;
8346 }
8347
8348 static void
8349 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8350 {
8351         struct ixgbe_l2_tn_info *l2_tn_info =
8352                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8353         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8354
8355         if (l2_tn_info->e_tag_en)
8356                 (void)ixgbe_e_tag_enable(hw);
8357
8358         if (l2_tn_info->e_tag_fwd_en)
8359                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8360
8361         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8362 }
8363
8364 /* remove all the n-tuple filters */
8365 void
8366 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8367 {
8368         struct ixgbe_filter_info *filter_info =
8369                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8370         struct ixgbe_5tuple_filter *p_5tuple;
8371
8372         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8373                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8374 }
8375
8376 /* remove all the ether type filters */
8377 void
8378 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8379 {
8380         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8381         struct ixgbe_filter_info *filter_info =
8382                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8383         int i;
8384
8385         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8386                 if (filter_info->ethertype_mask & (1 << i) &&
8387                     !filter_info->ethertype_filters[i].conf) {
8388                         (void)ixgbe_ethertype_filter_remove(filter_info,
8389                                                             (uint8_t)i);
8390                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8391                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8392                         IXGBE_WRITE_FLUSH(hw);
8393                 }
8394         }
8395 }
8396
8397 /* remove the SYN filter */
8398 void
8399 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8400 {
8401         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8402         struct ixgbe_filter_info *filter_info =
8403                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8404
8405         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8406                 filter_info->syn_info = 0;
8407
8408                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8409                 IXGBE_WRITE_FLUSH(hw);
8410         }
8411 }
8412
8413 /* remove all the L2 tunnel filters */
8414 int
8415 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8416 {
8417         struct ixgbe_l2_tn_info *l2_tn_info =
8418                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8419         struct ixgbe_l2_tn_filter *l2_tn_filter;
8420         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8421         int ret = 0;
8422
8423         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8424                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8425                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8426                 l2_tn_conf.pool           = l2_tn_filter->pool;
8427                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8428                 if (ret < 0)
8429                         return ret;
8430         }
8431
8432         return 0;
8433 }
8434
8435 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8436 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8437 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8438 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8439 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8440 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8441
8442 RTE_INIT(ixgbe_init_log);
8443 static void
8444 ixgbe_init_log(void)
8445 {
8446         ixgbe_logtype_init = rte_log_register("pmd.ixgbe.init");
8447         if (ixgbe_logtype_init >= 0)
8448                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8449         ixgbe_logtype_driver = rte_log_register("pmd.ixgbe.driver");
8450         if (ixgbe_logtype_driver >= 0)
8451                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8452 }