4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define IXGBE_TIMINCA_16NS_SHIFT 24
130 #define IXGBE_TIMINCA_INCVALUE 16000000
131 #define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
132 | IXGBE_TIMINCA_INCVALUE)
134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
147 int wait_to_complete);
148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
149 struct rte_eth_stats *stats);
150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
151 struct rte_eth_xstats *xstats, unsigned n);
152 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
153 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
154 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
158 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
159 struct rte_eth_dev_info *dev_info);
160 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
161 struct rte_eth_dev_info *dev_info);
162 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
164 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
165 uint16_t vlan_id, int on);
166 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
167 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
168 uint16_t queue, bool on);
169 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
171 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
172 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
173 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
174 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
175 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
177 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
178 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
179 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
180 struct rte_eth_fc_conf *fc_conf);
181 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
182 struct rte_eth_fc_conf *fc_conf);
183 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
184 struct rte_eth_pfc_conf *pfc_conf);
185 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
188 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
189 struct rte_eth_rss_reta_entry64 *reta_conf,
191 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
192 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
194 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
196 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
197 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
198 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
200 static void ixgbe_dev_interrupt_delayed_handler(void *param);
201 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
202 uint32_t index, uint32_t pool);
203 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
204 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
205 struct ether_addr *mac_addr);
206 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
208 /* For Virtual Function support */
209 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
210 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
211 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
212 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
213 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
214 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
215 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
216 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
217 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
218 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
219 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
220 struct rte_eth_stats *stats);
221 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
222 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
223 uint16_t vlan_id, int on);
224 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
225 uint16_t queue, int on);
226 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
227 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
228 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
231 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
233 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
235 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
236 uint8_t queue, uint8_t msix_vector);
238 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
240 /* For Eth VMDQ APIs support */
241 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
242 ether_addr* mac_addr,uint8_t on);
243 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
244 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
245 uint16_t rx_mask, uint8_t on);
246 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
247 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
248 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
249 uint64_t pool_mask,uint8_t vlan_on);
250 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
251 struct rte_eth_mirror_conf *mirror_conf,
252 uint8_t rule_id, uint8_t on);
253 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
256 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
258 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
260 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
261 uint8_t queue, uint8_t msix_vector);
263 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
265 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
266 uint16_t queue_idx, uint16_t tx_rate);
267 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
268 uint16_t tx_rate, uint64_t q_msk);
270 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
271 struct ether_addr *mac_addr,
272 uint32_t index, uint32_t pool);
273 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
274 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
275 struct ether_addr *mac_addr);
276 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
277 struct rte_eth_syn_filter *filter,
279 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
280 struct rte_eth_syn_filter *filter);
281 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
282 enum rte_filter_op filter_op,
284 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
285 struct ixgbe_5tuple_filter *filter);
286 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
287 struct ixgbe_5tuple_filter *filter);
288 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
289 struct rte_eth_ntuple_filter *filter,
291 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
292 enum rte_filter_op filter_op,
294 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
295 struct rte_eth_ntuple_filter *filter);
296 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
297 struct rte_eth_ethertype_filter *filter,
299 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
300 enum rte_filter_op filter_op,
302 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
303 struct rte_eth_ethertype_filter *filter);
304 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
305 enum rte_filter_type filter_type,
306 enum rte_filter_op filter_op,
308 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
310 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
311 struct ether_addr *mc_addr_set,
312 uint32_t nb_mc_addr);
314 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
315 static int ixgbe_get_regs(struct rte_eth_dev *dev,
316 struct rte_dev_reg_info *regs);
317 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
318 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
319 struct rte_dev_eeprom_info *eeprom);
320 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
321 struct rte_dev_eeprom_info *eeprom);
323 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
324 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
325 struct rte_dev_reg_info *regs);
327 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
328 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
329 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
330 struct timespec *timestamp,
332 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
333 struct timespec *timestamp);
336 * Define VF Stats MACRO for Non "cleared on read" register
338 #define UPDATE_VF_STAT(reg, last, cur) \
340 uint32_t latest = IXGBE_READ_REG(hw, reg); \
341 cur += latest - last; \
345 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
347 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
348 u64 new_msb = IXGBE_READ_REG(hw, msb); \
349 u64 latest = ((new_msb << 32) | new_lsb); \
350 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
354 #define IXGBE_SET_HWSTRIP(h, q) do{\
355 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
356 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
357 (h)->bitmap[idx] |= 1 << bit;\
360 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
361 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
362 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
363 (h)->bitmap[idx] &= ~(1 << bit);\
366 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
367 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
368 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
369 (r) = (h)->bitmap[idx] >> bit & 1;\
373 * The set of PCI devices this driver supports
375 static const struct rte_pci_id pci_id_ixgbe_map[] = {
377 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
378 #include "rte_pci_dev_ids.h"
380 { .vendor_id = 0, /* sentinel */ },
385 * The set of PCI devices this driver supports (for 82599 VF)
387 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
389 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
390 #include "rte_pci_dev_ids.h"
391 { .vendor_id = 0, /* sentinel */ },
395 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
396 .dev_configure = ixgbe_dev_configure,
397 .dev_start = ixgbe_dev_start,
398 .dev_stop = ixgbe_dev_stop,
399 .dev_set_link_up = ixgbe_dev_set_link_up,
400 .dev_set_link_down = ixgbe_dev_set_link_down,
401 .dev_close = ixgbe_dev_close,
402 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
403 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
404 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
405 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
406 .link_update = ixgbe_dev_link_update,
407 .stats_get = ixgbe_dev_stats_get,
408 .xstats_get = ixgbe_dev_xstats_get,
409 .stats_reset = ixgbe_dev_stats_reset,
410 .xstats_reset = ixgbe_dev_xstats_reset,
411 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
412 .dev_infos_get = ixgbe_dev_info_get,
413 .mtu_set = ixgbe_dev_mtu_set,
414 .vlan_filter_set = ixgbe_vlan_filter_set,
415 .vlan_tpid_set = ixgbe_vlan_tpid_set,
416 .vlan_offload_set = ixgbe_vlan_offload_set,
417 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
418 .rx_queue_start = ixgbe_dev_rx_queue_start,
419 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
420 .tx_queue_start = ixgbe_dev_tx_queue_start,
421 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
422 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
424 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
425 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
427 .rx_queue_release = ixgbe_dev_rx_queue_release,
428 .rx_queue_count = ixgbe_dev_rx_queue_count,
429 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
430 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
431 .tx_queue_release = ixgbe_dev_tx_queue_release,
432 .dev_led_on = ixgbe_dev_led_on,
433 .dev_led_off = ixgbe_dev_led_off,
434 .flow_ctrl_get = ixgbe_flow_ctrl_get,
435 .flow_ctrl_set = ixgbe_flow_ctrl_set,
436 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
437 .mac_addr_add = ixgbe_add_rar,
438 .mac_addr_remove = ixgbe_remove_rar,
439 .mac_addr_set = ixgbe_set_default_mac_addr,
440 .uc_hash_table_set = ixgbe_uc_hash_table_set,
441 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
442 .mirror_rule_set = ixgbe_mirror_rule_set,
443 .mirror_rule_reset = ixgbe_mirror_rule_reset,
444 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
445 .set_vf_rx = ixgbe_set_pool_rx,
446 .set_vf_tx = ixgbe_set_pool_tx,
447 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
448 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
449 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
450 .reta_update = ixgbe_dev_rss_reta_update,
451 .reta_query = ixgbe_dev_rss_reta_query,
452 #ifdef RTE_NIC_BYPASS
453 .bypass_init = ixgbe_bypass_init,
454 .bypass_state_set = ixgbe_bypass_state_store,
455 .bypass_state_show = ixgbe_bypass_state_show,
456 .bypass_event_set = ixgbe_bypass_event_store,
457 .bypass_event_show = ixgbe_bypass_event_show,
458 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
459 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
460 .bypass_ver_show = ixgbe_bypass_ver_show,
461 .bypass_wd_reset = ixgbe_bypass_wd_reset,
462 #endif /* RTE_NIC_BYPASS */
463 .rss_hash_update = ixgbe_dev_rss_hash_update,
464 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
465 .filter_ctrl = ixgbe_dev_filter_ctrl,
466 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
467 .timesync_enable = ixgbe_timesync_enable,
468 .timesync_disable = ixgbe_timesync_disable,
469 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
470 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
471 .get_reg_length = ixgbe_get_reg_length,
472 .get_reg = ixgbe_get_regs,
473 .get_eeprom_length = ixgbe_get_eeprom_length,
474 .get_eeprom = ixgbe_get_eeprom,
475 .set_eeprom = ixgbe_set_eeprom,
479 * dev_ops for virtual function, bare necessities for basic vf
480 * operation have been implemented
482 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
483 .dev_configure = ixgbevf_dev_configure,
484 .dev_start = ixgbevf_dev_start,
485 .dev_stop = ixgbevf_dev_stop,
486 .link_update = ixgbe_dev_link_update,
487 .stats_get = ixgbevf_dev_stats_get,
488 .stats_reset = ixgbevf_dev_stats_reset,
489 .dev_close = ixgbevf_dev_close,
490 .dev_infos_get = ixgbevf_dev_info_get,
491 .mtu_set = ixgbevf_dev_set_mtu,
492 .vlan_filter_set = ixgbevf_vlan_filter_set,
493 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
494 .vlan_offload_set = ixgbevf_vlan_offload_set,
495 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
496 .rx_queue_release = ixgbe_dev_rx_queue_release,
497 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
498 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
499 .tx_queue_release = ixgbe_dev_tx_queue_release,
501 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
502 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
504 .mac_addr_add = ixgbevf_add_mac_addr,
505 .mac_addr_remove = ixgbevf_remove_mac_addr,
506 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
507 .mac_addr_set = ixgbevf_set_default_mac_addr,
508 .get_reg_length = ixgbevf_get_reg_length,
509 .get_reg = ixgbevf_get_regs,
512 /* store statistics names and its offset in stats structure */
513 struct rte_ixgbe_xstats_name_off {
514 char name[RTE_ETH_XSTATS_NAME_SIZE];
518 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
519 {"rx_illegal_byte_err", offsetof(struct ixgbe_hw_stats, errbc)},
520 {"rx_len_err", offsetof(struct ixgbe_hw_stats, rlec)},
521 {"rx_undersize_count", offsetof(struct ixgbe_hw_stats, ruc)},
522 {"rx_oversize_count", offsetof(struct ixgbe_hw_stats, roc)},
523 {"rx_fragment_count", offsetof(struct ixgbe_hw_stats, rfc)},
524 {"rx_jabber_count", offsetof(struct ixgbe_hw_stats, rjc)},
525 {"l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
526 {"mac_local_fault", offsetof(struct ixgbe_hw_stats, mlfc)},
527 {"mac_remote_fault", offsetof(struct ixgbe_hw_stats, mrfc)},
528 {"mac_short_pkt_discard", offsetof(struct ixgbe_hw_stats, mspdc)},
529 {"fccrc_error", offsetof(struct ixgbe_hw_stats, fccrc)},
530 {"fcoe_drop", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
531 {"fc_last_error", offsetof(struct ixgbe_hw_stats, fclast)},
532 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
533 {"rx_phy_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
534 {"mgmt_pkts_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
535 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
536 {"fdir_match", offsetof(struct ixgbe_hw_stats, fdirmatch)},
537 {"fdir_miss", offsetof(struct ixgbe_hw_stats, fdirmiss)},
538 {"tx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxontxc)},
539 {"rx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxonrxc)},
540 {"tx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxofftxc)},
541 {"rx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
544 #define IXGBE_NB_XSTATS (sizeof(rte_ixgbe_stats_strings) / \
545 sizeof(rte_ixgbe_stats_strings[0]))
548 * Atomically reads the link status information from global
549 * structure rte_eth_dev.
552 * - Pointer to the structure rte_eth_dev to read from.
553 * - Pointer to the buffer to be saved with the link status.
556 * - On success, zero.
557 * - On failure, negative value.
560 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
561 struct rte_eth_link *link)
563 struct rte_eth_link *dst = link;
564 struct rte_eth_link *src = &(dev->data->dev_link);
566 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
567 *(uint64_t *)src) == 0)
574 * Atomically writes the link status information into global
575 * structure rte_eth_dev.
578 * - Pointer to the structure rte_eth_dev to read from.
579 * - Pointer to the buffer to be saved with the link status.
582 * - On success, zero.
583 * - On failure, negative value.
586 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
587 struct rte_eth_link *link)
589 struct rte_eth_link *dst = &(dev->data->dev_link);
590 struct rte_eth_link *src = link;
592 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
593 *(uint64_t *)src) == 0)
600 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
603 ixgbe_is_sfp(struct ixgbe_hw *hw)
605 switch (hw->phy.type) {
606 case ixgbe_phy_sfp_avago:
607 case ixgbe_phy_sfp_ftl:
608 case ixgbe_phy_sfp_intel:
609 case ixgbe_phy_sfp_unknown:
610 case ixgbe_phy_sfp_passive_tyco:
611 case ixgbe_phy_sfp_passive_unknown:
618 static inline int32_t
619 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
624 status = ixgbe_reset_hw(hw);
626 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
627 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
628 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
629 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
630 IXGBE_WRITE_FLUSH(hw);
636 ixgbe_enable_intr(struct rte_eth_dev *dev)
638 struct ixgbe_interrupt *intr =
639 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
640 struct ixgbe_hw *hw =
641 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
643 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
644 IXGBE_WRITE_FLUSH(hw);
648 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
651 ixgbe_disable_intr(struct ixgbe_hw *hw)
653 PMD_INIT_FUNC_TRACE();
655 if (hw->mac.type == ixgbe_mac_82598EB) {
656 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
658 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
659 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
660 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
662 IXGBE_WRITE_FLUSH(hw);
666 * This function resets queue statistics mapping registers.
667 * From Niantic datasheet, Initialization of Statistics section:
668 * "...if software requires the queue counters, the RQSMR and TQSM registers
669 * must be re-programmed following a device reset.
672 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
676 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
677 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
678 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
684 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
689 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
690 #define NB_QMAP_FIELDS_PER_QSM_REG 4
691 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
693 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
694 struct ixgbe_stat_mapping_registers *stat_mappings =
695 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
696 uint32_t qsmr_mask = 0;
697 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
701 if ((hw->mac.type != ixgbe_mac_82599EB) &&
702 (hw->mac.type != ixgbe_mac_X540) &&
703 (hw->mac.type != ixgbe_mac_X550) &&
704 (hw->mac.type != ixgbe_mac_X550EM_x))
707 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
708 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
711 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
712 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
713 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
716 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
718 /* Now clear any previous stat_idx set */
719 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
721 stat_mappings->tqsm[n] &= ~clearing_mask;
723 stat_mappings->rqsmr[n] &= ~clearing_mask;
725 q_map = (uint32_t)stat_idx;
726 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
727 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
729 stat_mappings->tqsm[n] |= qsmr_mask;
731 stat_mappings->rqsmr[n] |= qsmr_mask;
733 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
734 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
736 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
737 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
739 /* Now write the mapping in the appropriate register */
741 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
742 stat_mappings->rqsmr[n], n);
743 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
746 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
747 stat_mappings->tqsm[n], n);
748 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
754 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
756 struct ixgbe_stat_mapping_registers *stat_mappings =
757 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
758 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
761 /* write whatever was in stat mapping table to the NIC */
762 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
764 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
767 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
772 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
775 struct ixgbe_dcb_tc_config *tc;
776 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
778 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
779 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
780 for (i = 0; i < dcb_max_tc; i++) {
781 tc = &dcb_config->tc_config[i];
782 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
783 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
784 (uint8_t)(100/dcb_max_tc + (i & 1));
785 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
786 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
787 (uint8_t)(100/dcb_max_tc + (i & 1));
788 tc->pfc = ixgbe_dcb_pfc_disabled;
791 /* Initialize default user to priority mapping, UPx->TC0 */
792 tc = &dcb_config->tc_config[0];
793 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
794 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
795 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
796 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
797 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
799 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
800 dcb_config->pfc_mode_enable = false;
801 dcb_config->vt_mode = true;
802 dcb_config->round_robin_enable = false;
803 /* support all DCB capabilities in 82599 */
804 dcb_config->support.capabilities = 0xFF;
806 /*we only support 4 Tcs for X540, X550 */
807 if (hw->mac.type == ixgbe_mac_X540 ||
808 hw->mac.type == ixgbe_mac_X550 ||
809 hw->mac.type == ixgbe_mac_X550EM_x) {
810 dcb_config->num_tcs.pg_tcs = 4;
811 dcb_config->num_tcs.pfc_tcs = 4;
816 * Ensure that all locks are released before first NVM or PHY access
819 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
824 * Phy lock should not fail in this early stage. If this is the case,
825 * it is due to an improper exit of the application.
826 * So force the release of the faulty lock. Release of common lock
827 * is done automatically by swfw_sync function.
829 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
830 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
831 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
833 ixgbe_release_swfw_semaphore(hw, mask);
836 * These ones are more tricky since they are common to all ports; but
837 * swfw_sync retries last long enough (1s) to be almost sure that if
838 * lock can not be taken it is due to an improper lock of the
841 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
842 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
843 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
845 ixgbe_release_swfw_semaphore(hw, mask);
849 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
850 * It returns 0 on success.
853 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
855 struct rte_pci_device *pci_dev;
856 struct ixgbe_hw *hw =
857 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
858 struct ixgbe_vfta * shadow_vfta =
859 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
860 struct ixgbe_hwstrip *hwstrip =
861 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
862 struct ixgbe_dcb_config *dcb_config =
863 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
864 struct ixgbe_filter_info *filter_info =
865 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
870 PMD_INIT_FUNC_TRACE();
872 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
873 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
874 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
877 * For secondary processes, we don't initialise any further as primary
878 * has already done this work. Only check we don't need a different
879 * RX and TX function.
881 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
882 struct ixgbe_tx_queue *txq;
883 /* TX queue function in primary, set by last queue initialized
884 * Tx queue may not initialized by primary process */
885 if (eth_dev->data->tx_queues) {
886 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
887 ixgbe_set_tx_function(eth_dev, txq);
889 /* Use default TX function if we get here */
890 PMD_INIT_LOG(INFO, "No TX queues configured yet. "
891 "Using default TX function.");
894 ixgbe_set_rx_function(eth_dev);
898 pci_dev = eth_dev->pci_dev;
900 /* Vendor and Device ID need to be set before init of shared code */
901 hw->device_id = pci_dev->id.device_id;
902 hw->vendor_id = pci_dev->id.vendor_id;
903 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
904 hw->allow_unsupported_sfp = 1;
906 /* Initialize the shared code (base driver) */
907 #ifdef RTE_NIC_BYPASS
908 diag = ixgbe_bypass_init_shared_code(hw);
910 diag = ixgbe_init_shared_code(hw);
911 #endif /* RTE_NIC_BYPASS */
913 if (diag != IXGBE_SUCCESS) {
914 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
918 /* pick up the PCI bus settings for reporting later */
919 ixgbe_get_bus_info(hw);
921 /* Unlock any pending hardware semaphore */
922 ixgbe_swfw_lock_reset(hw);
924 /* Initialize DCB configuration*/
925 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
926 ixgbe_dcb_init(hw,dcb_config);
927 /* Get Hardware Flow Control setting */
928 hw->fc.requested_mode = ixgbe_fc_full;
929 hw->fc.current_mode = ixgbe_fc_full;
930 hw->fc.pause_time = IXGBE_FC_PAUSE;
931 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
932 hw->fc.low_water[i] = IXGBE_FC_LO;
933 hw->fc.high_water[i] = IXGBE_FC_HI;
937 /* Make sure we have a good EEPROM before we read from it */
938 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
939 if (diag != IXGBE_SUCCESS) {
940 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
944 #ifdef RTE_NIC_BYPASS
945 diag = ixgbe_bypass_init_hw(hw);
947 diag = ixgbe_init_hw(hw);
948 #endif /* RTE_NIC_BYPASS */
951 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
952 * is called too soon after the kernel driver unbinding/binding occurs.
953 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
954 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
955 * also called. See ixgbe_identify_phy_82599(). The reason for the
956 * failure is not known, and only occuts when virtualisation features
957 * are disabled in the bios. A delay of 100ms was found to be enough by
958 * trial-and-error, and is doubled to be safe.
960 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
962 diag = ixgbe_init_hw(hw);
965 if (diag == IXGBE_ERR_EEPROM_VERSION) {
966 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
967 "LOM. Please be aware there may be issues associated "
968 "with your hardware.");
969 PMD_INIT_LOG(ERR, "If you are experiencing problems "
970 "please contact your Intel or hardware representative "
971 "who provided you with this hardware.");
972 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
973 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
975 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
979 /* Reset the hw statistics */
980 ixgbe_dev_stats_reset(eth_dev);
982 /* disable interrupt */
983 ixgbe_disable_intr(hw);
985 /* reset mappings for queue statistics hw counters*/
986 ixgbe_reset_qstat_mappings(hw);
988 /* Allocate memory for storing MAC addresses */
989 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
990 hw->mac.num_rar_entries, 0);
991 if (eth_dev->data->mac_addrs == NULL) {
993 "Failed to allocate %u bytes needed to store "
995 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
998 /* Copy the permanent MAC address */
999 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1000 ð_dev->data->mac_addrs[0]);
1002 /* Allocate memory for storing hash filter MAC addresses */
1003 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1004 IXGBE_VMDQ_NUM_UC_MAC, 0);
1005 if (eth_dev->data->hash_mac_addrs == NULL) {
1007 "Failed to allocate %d bytes needed to store MAC addresses",
1008 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1012 /* initialize the vfta */
1013 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1015 /* initialize the hw strip bitmap*/
1016 memset(hwstrip, 0, sizeof(*hwstrip));
1018 /* initialize PF if max_vfs not zero */
1019 ixgbe_pf_host_init(eth_dev);
1021 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1022 /* let hardware know driver is loaded */
1023 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1024 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1025 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1026 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1027 IXGBE_WRITE_FLUSH(hw);
1029 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1030 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1031 (int) hw->mac.type, (int) hw->phy.type,
1032 (int) hw->phy.sfp_type);
1034 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1035 (int) hw->mac.type, (int) hw->phy.type);
1037 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1038 eth_dev->data->port_id, pci_dev->id.vendor_id,
1039 pci_dev->id.device_id);
1041 /* enable support intr */
1042 ixgbe_enable_intr(eth_dev);
1044 /* initialize 5tuple filter list */
1045 TAILQ_INIT(&filter_info->fivetuple_list);
1046 memset(filter_info->fivetuple_mask, 0,
1047 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1053 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1055 struct rte_pci_device *pci_dev;
1056 struct ixgbe_hw *hw;
1058 PMD_INIT_FUNC_TRACE();
1060 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1063 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1064 pci_dev = eth_dev->pci_dev;
1066 if (hw->adapter_stopped == 0)
1067 ixgbe_dev_close(eth_dev);
1069 eth_dev->dev_ops = NULL;
1070 eth_dev->rx_pkt_burst = NULL;
1071 eth_dev->tx_pkt_burst = NULL;
1073 /* Unlock any pending hardware semaphore */
1074 ixgbe_swfw_lock_reset(hw);
1076 /* disable uio intr before callback unregister */
1077 rte_intr_disable(&(pci_dev->intr_handle));
1078 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1079 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1081 /* uninitialize PF if max_vfs not zero */
1082 ixgbe_pf_host_uninit(eth_dev);
1084 rte_free(eth_dev->data->mac_addrs);
1085 eth_dev->data->mac_addrs = NULL;
1087 rte_free(eth_dev->data->hash_mac_addrs);
1088 eth_dev->data->hash_mac_addrs = NULL;
1094 * Negotiate mailbox API version with the PF.
1095 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1096 * Then we try to negotiate starting with the most recent one.
1097 * If all negotiation attempts fail, then we will proceed with
1098 * the default one (ixgbe_mbox_api_10).
1101 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1105 /* start with highest supported, proceed down */
1106 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1112 i != RTE_DIM(sup_ver) &&
1113 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1119 generate_random_mac_addr(struct ether_addr *mac_addr)
1123 /* Set Organizationally Unique Identifier (OUI) prefix. */
1124 mac_addr->addr_bytes[0] = 0x00;
1125 mac_addr->addr_bytes[1] = 0x09;
1126 mac_addr->addr_bytes[2] = 0xC0;
1127 /* Force indication of locally assigned MAC address. */
1128 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1129 /* Generate the last 3 bytes of the MAC address with a random number. */
1130 random = rte_rand();
1131 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1135 * Virtual Function device init
1138 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1142 struct rte_pci_device *pci_dev;
1143 struct ixgbe_hw *hw =
1144 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1145 struct ixgbe_vfta * shadow_vfta =
1146 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1147 struct ixgbe_hwstrip *hwstrip =
1148 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1149 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1151 PMD_INIT_FUNC_TRACE();
1153 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1154 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1155 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1157 /* for secondary processes, we don't initialise any further as primary
1158 * has already done this work. Only check we don't need a different
1160 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1161 if (eth_dev->data->scattered_rx)
1162 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1166 pci_dev = eth_dev->pci_dev;
1168 hw->device_id = pci_dev->id.device_id;
1169 hw->vendor_id = pci_dev->id.vendor_id;
1170 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1172 /* initialize the vfta */
1173 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1175 /* initialize the hw strip bitmap*/
1176 memset(hwstrip, 0, sizeof(*hwstrip));
1178 /* Initialize the shared code (base driver) */
1179 diag = ixgbe_init_shared_code(hw);
1180 if (diag != IXGBE_SUCCESS) {
1181 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1185 /* init_mailbox_params */
1186 hw->mbx.ops.init_params(hw);
1188 /* Reset the hw statistics */
1189 ixgbevf_dev_stats_reset(eth_dev);
1191 /* Disable the interrupts for VF */
1192 ixgbevf_intr_disable(hw);
1194 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1195 diag = hw->mac.ops.reset_hw(hw);
1198 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1199 * the underlying PF driver has not assigned a MAC address to the VF.
1200 * In this case, assign a random MAC address.
1202 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1203 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1207 /* negotiate mailbox API version to use with the PF. */
1208 ixgbevf_negotiate_api(hw);
1210 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1211 ixgbevf_get_queues(hw, &tcs, &tc);
1213 /* Allocate memory for storing MAC addresses */
1214 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1215 hw->mac.num_rar_entries, 0);
1216 if (eth_dev->data->mac_addrs == NULL) {
1218 "Failed to allocate %u bytes needed to store "
1220 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1224 /* Generate a random MAC address, if none was assigned by PF. */
1225 if (is_zero_ether_addr(perm_addr)) {
1226 generate_random_mac_addr(perm_addr);
1227 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1229 rte_free(eth_dev->data->mac_addrs);
1230 eth_dev->data->mac_addrs = NULL;
1233 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1234 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1235 "%02x:%02x:%02x:%02x:%02x:%02x",
1236 perm_addr->addr_bytes[0],
1237 perm_addr->addr_bytes[1],
1238 perm_addr->addr_bytes[2],
1239 perm_addr->addr_bytes[3],
1240 perm_addr->addr_bytes[4],
1241 perm_addr->addr_bytes[5]);
1244 /* Copy the permanent MAC address */
1245 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1247 /* reset the hardware with the new settings */
1248 diag = hw->mac.ops.start_hw(hw);
1254 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1258 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1259 eth_dev->data->port_id, pci_dev->id.vendor_id,
1260 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1265 /* Virtual Function device uninit */
1268 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1270 struct ixgbe_hw *hw;
1273 PMD_INIT_FUNC_TRACE();
1275 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1278 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1280 if (hw->adapter_stopped == 0)
1281 ixgbevf_dev_close(eth_dev);
1283 eth_dev->dev_ops = NULL;
1284 eth_dev->rx_pkt_burst = NULL;
1285 eth_dev->tx_pkt_burst = NULL;
1287 /* Disable the interrupts for VF */
1288 ixgbevf_intr_disable(hw);
1290 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1291 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1292 eth_dev->data->rx_queues[i] = NULL;
1294 eth_dev->data->nb_rx_queues = 0;
1296 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1297 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1298 eth_dev->data->tx_queues[i] = NULL;
1300 eth_dev->data->nb_tx_queues = 0;
1302 rte_free(eth_dev->data->mac_addrs);
1303 eth_dev->data->mac_addrs = NULL;
1308 static struct eth_driver rte_ixgbe_pmd = {
1310 .name = "rte_ixgbe_pmd",
1311 .id_table = pci_id_ixgbe_map,
1312 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1313 RTE_PCI_DRV_DETACHABLE,
1315 .eth_dev_init = eth_ixgbe_dev_init,
1316 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1317 .dev_private_size = sizeof(struct ixgbe_adapter),
1321 * virtual function driver struct
1323 static struct eth_driver rte_ixgbevf_pmd = {
1325 .name = "rte_ixgbevf_pmd",
1326 .id_table = pci_id_ixgbevf_map,
1327 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1329 .eth_dev_init = eth_ixgbevf_dev_init,
1330 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1331 .dev_private_size = sizeof(struct ixgbe_adapter),
1335 * Driver initialization routine.
1336 * Invoked once at EAL init time.
1337 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1340 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1342 PMD_INIT_FUNC_TRACE();
1344 rte_eth_driver_register(&rte_ixgbe_pmd);
1349 * VF Driver initialization routine.
1350 * Invoked one at EAL init time.
1351 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1354 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1356 PMD_INIT_FUNC_TRACE();
1358 rte_eth_driver_register(&rte_ixgbevf_pmd);
1363 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1365 struct ixgbe_hw *hw =
1366 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1367 struct ixgbe_vfta * shadow_vfta =
1368 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1373 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1374 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1375 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1380 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1382 /* update local VFTA copy */
1383 shadow_vfta->vfta[vid_idx] = vfta;
1389 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1392 ixgbe_vlan_hw_strip_enable(dev, queue);
1394 ixgbe_vlan_hw_strip_disable(dev, queue);
1398 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1400 struct ixgbe_hw *hw =
1401 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1403 /* Only the high 16-bits is valid */
1404 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1408 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1410 struct ixgbe_hw *hw =
1411 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414 PMD_INIT_FUNC_TRACE();
1416 /* Filter Table Disable */
1417 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1418 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1420 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1424 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1426 struct ixgbe_hw *hw =
1427 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428 struct ixgbe_vfta * shadow_vfta =
1429 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1433 PMD_INIT_FUNC_TRACE();
1435 /* Filter Table Enable */
1436 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1437 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1438 vlnctrl |= IXGBE_VLNCTRL_VFE;
1440 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1442 /* write whatever is in local vfta copy */
1443 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1444 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1448 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1450 struct ixgbe_hwstrip *hwstrip =
1451 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1453 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1457 IXGBE_SET_HWSTRIP(hwstrip, queue);
1459 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1463 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1465 struct ixgbe_hw *hw =
1466 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1469 PMD_INIT_FUNC_TRACE();
1471 if (hw->mac.type == ixgbe_mac_82598EB) {
1472 /* No queue level support */
1473 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1477 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1478 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1479 ctrl &= ~IXGBE_RXDCTL_VME;
1480 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1482 /* record those setting for HW strip per queue */
1483 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1487 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1489 struct ixgbe_hw *hw =
1490 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1493 PMD_INIT_FUNC_TRACE();
1495 if (hw->mac.type == ixgbe_mac_82598EB) {
1496 /* No queue level supported */
1497 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1501 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1502 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1503 ctrl |= IXGBE_RXDCTL_VME;
1504 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1506 /* record those setting for HW strip per queue */
1507 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1511 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1513 struct ixgbe_hw *hw =
1514 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518 PMD_INIT_FUNC_TRACE();
1520 if (hw->mac.type == ixgbe_mac_82598EB) {
1521 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1522 ctrl &= ~IXGBE_VLNCTRL_VME;
1523 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1526 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1527 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1528 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1529 ctrl &= ~IXGBE_RXDCTL_VME;
1530 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1532 /* record those setting for HW strip per queue */
1533 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1539 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1541 struct ixgbe_hw *hw =
1542 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1546 PMD_INIT_FUNC_TRACE();
1548 if (hw->mac.type == ixgbe_mac_82598EB) {
1549 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1550 ctrl |= IXGBE_VLNCTRL_VME;
1551 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1554 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1555 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1556 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1557 ctrl |= IXGBE_RXDCTL_VME;
1558 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1560 /* record those setting for HW strip per queue */
1561 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1567 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1569 struct ixgbe_hw *hw =
1570 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1573 PMD_INIT_FUNC_TRACE();
1575 /* DMATXCTRL: Geric Double VLAN Disable */
1576 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1577 ctrl &= ~IXGBE_DMATXCTL_GDV;
1578 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1580 /* CTRL_EXT: Global Double VLAN Disable */
1581 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1582 ctrl &= ~IXGBE_EXTENDED_VLAN;
1583 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1588 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1590 struct ixgbe_hw *hw =
1591 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1594 PMD_INIT_FUNC_TRACE();
1596 /* DMATXCTRL: Geric Double VLAN Enable */
1597 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1598 ctrl |= IXGBE_DMATXCTL_GDV;
1599 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1601 /* CTRL_EXT: Global Double VLAN Enable */
1602 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1603 ctrl |= IXGBE_EXTENDED_VLAN;
1604 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1607 * VET EXT field in the EXVET register = 0x8100 by default
1608 * So no need to change. Same to VT field of DMATXCTL register
1613 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1615 if(mask & ETH_VLAN_STRIP_MASK){
1616 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1617 ixgbe_vlan_hw_strip_enable_all(dev);
1619 ixgbe_vlan_hw_strip_disable_all(dev);
1622 if(mask & ETH_VLAN_FILTER_MASK){
1623 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1624 ixgbe_vlan_hw_filter_enable(dev);
1626 ixgbe_vlan_hw_filter_disable(dev);
1629 if(mask & ETH_VLAN_EXTEND_MASK){
1630 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1631 ixgbe_vlan_hw_extend_enable(dev);
1633 ixgbe_vlan_hw_extend_disable(dev);
1638 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1640 struct ixgbe_hw *hw =
1641 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1643 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1644 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1645 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1649 ixgbe_dev_configure(struct rte_eth_dev *dev)
1651 struct ixgbe_interrupt *intr =
1652 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1653 struct ixgbe_adapter *adapter =
1654 (struct ixgbe_adapter *)dev->data->dev_private;
1656 PMD_INIT_FUNC_TRACE();
1658 /* set flag to update link status after init */
1659 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1662 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1663 * allocation or vector Rx preconditions we will reset it.
1665 adapter->rx_bulk_alloc_allowed = true;
1666 adapter->rx_vec_allowed = true;
1672 * Configure device link speed and setup link.
1673 * It returns 0 on success.
1676 ixgbe_dev_start(struct rte_eth_dev *dev)
1678 struct ixgbe_hw *hw =
1679 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680 struct ixgbe_vf_info *vfinfo =
1681 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1682 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1684 uint32_t intr_vector = 0;
1686 int err, link_up = 0, negotiate = 0;
1692 PMD_INIT_FUNC_TRACE();
1694 /* IXGBE devices don't support half duplex */
1695 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1696 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1697 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1698 dev->data->dev_conf.link_duplex,
1699 dev->data->port_id);
1704 hw->adapter_stopped = 0;
1705 ixgbe_stop_adapter(hw);
1707 /* reinitialize adapter
1708 * this calls reset and start */
1709 status = ixgbe_pf_reset_hw(hw);
1712 hw->mac.ops.start_hw(hw);
1713 hw->mac.get_link_status = true;
1715 /* configure PF module if SRIOV enabled */
1716 ixgbe_pf_host_configure(dev);
1719 /* check and configure queue intr-vector mapping */
1720 if (dev->data->dev_conf.intr_conf.rxq != 0)
1721 intr_vector = dev->data->nb_rx_queues;
1723 if (rte_intr_efd_enable(intr_handle, intr_vector))
1726 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1727 intr_handle->intr_vec =
1728 rte_zmalloc("intr_vec",
1729 dev->data->nb_rx_queues * sizeof(int),
1731 if (intr_handle->intr_vec == NULL) {
1732 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1733 " intr_vec\n", dev->data->nb_rx_queues);
1739 /* confiugre msix for sleep until rx interrupt */
1740 ixgbe_configure_msix(dev);
1742 /* initialize transmission unit */
1743 ixgbe_dev_tx_init(dev);
1745 /* This can fail when allocating mbufs for descriptor rings */
1746 err = ixgbe_dev_rx_init(dev);
1748 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1752 err = ixgbe_dev_rxtx_start(dev);
1754 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1758 /* Skip link setup if loopback mode is enabled for 82599. */
1759 if (hw->mac.type == ixgbe_mac_82599EB &&
1760 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1761 goto skip_link_setup;
1763 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1764 err = hw->mac.ops.setup_sfp(hw);
1769 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1770 /* Turn on the copper */
1771 ixgbe_set_phy_power(hw, true);
1773 /* Turn on the laser */
1774 ixgbe_enable_tx_laser(hw);
1777 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1780 dev->data->dev_link.link_status = link_up;
1782 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1786 switch(dev->data->dev_conf.link_speed) {
1787 case ETH_LINK_SPEED_AUTONEG:
1788 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1789 IXGBE_LINK_SPEED_82599_AUTONEG :
1790 IXGBE_LINK_SPEED_82598_AUTONEG;
1792 case ETH_LINK_SPEED_100:
1794 * Invalid for 82598 but error will be detected by
1795 * ixgbe_setup_link()
1797 speed = IXGBE_LINK_SPEED_100_FULL;
1799 case ETH_LINK_SPEED_1000:
1800 speed = IXGBE_LINK_SPEED_1GB_FULL;
1802 case ETH_LINK_SPEED_10000:
1803 speed = IXGBE_LINK_SPEED_10GB_FULL;
1806 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1807 dev->data->dev_conf.link_speed,
1808 dev->data->port_id);
1812 err = ixgbe_setup_link(hw, speed, link_up);
1818 /* check if lsc interrupt is enabled */
1819 if (dev->data->dev_conf.intr_conf.lsc != 0) {
1820 if (rte_intr_allow_others(intr_handle)) {
1821 rte_intr_callback_register(intr_handle,
1822 ixgbe_dev_interrupt_handler,
1824 ixgbe_dev_lsc_interrupt_setup(dev);
1826 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1827 " no intr multiplex\n");
1831 /* check if rxq interrupt is enabled */
1832 if (dev->data->dev_conf.intr_conf.rxq != 0)
1833 ixgbe_dev_rxq_interrupt_setup(dev);
1836 /* enable uio/vfio intr/eventfd mapping */
1837 rte_intr_enable(intr_handle);
1839 /* resume enabled intr since hw reset */
1840 ixgbe_enable_intr(dev);
1842 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1843 ETH_VLAN_EXTEND_MASK;
1844 ixgbe_vlan_offload_set(dev, mask);
1846 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1847 /* Enable vlan filtering for VMDq */
1848 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1851 /* Configure DCB hw */
1852 ixgbe_configure_dcb(dev);
1854 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1855 err = ixgbe_fdir_configure(dev);
1860 /* Restore vf rate limit */
1861 if (vfinfo != NULL) {
1862 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1863 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1864 if (vfinfo[vf].tx_rate[idx] != 0)
1865 ixgbe_set_vf_rate_limit(dev, vf,
1866 vfinfo[vf].tx_rate[idx],
1870 ixgbe_restore_statistics_mapping(dev);
1875 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1876 ixgbe_dev_clear_queues(dev);
1881 * Stop device: disable rx and tx functions to allow for reconfiguring.
1884 ixgbe_dev_stop(struct rte_eth_dev *dev)
1886 struct rte_eth_link link;
1887 struct ixgbe_hw *hw =
1888 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1889 struct ixgbe_vf_info *vfinfo =
1890 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1891 struct ixgbe_filter_info *filter_info =
1892 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1893 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1894 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1897 PMD_INIT_FUNC_TRACE();
1899 /* disable interrupts */
1900 ixgbe_disable_intr(hw);
1902 /* disable intr eventfd mapping */
1903 rte_intr_disable(intr_handle);
1906 ixgbe_pf_reset_hw(hw);
1907 hw->adapter_stopped = 0;
1910 ixgbe_stop_adapter(hw);
1912 for (vf = 0; vfinfo != NULL &&
1913 vf < dev->pci_dev->max_vfs; vf++)
1914 vfinfo[vf].clear_to_send = false;
1916 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1917 /* Turn off the copper */
1918 ixgbe_set_phy_power(hw, false);
1920 /* Turn off the laser */
1921 ixgbe_disable_tx_laser(hw);
1924 ixgbe_dev_clear_queues(dev);
1926 /* Clear stored conf */
1927 dev->data->scattered_rx = 0;
1930 /* Clear recorded link status */
1931 memset(&link, 0, sizeof(link));
1932 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1934 /* Remove all ntuple filters of the device */
1935 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1936 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1937 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1938 TAILQ_REMOVE(&filter_info->fivetuple_list,
1942 memset(filter_info->fivetuple_mask, 0,
1943 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1946 /* Clean datapath event and queue/vec mapping */
1947 rte_intr_efd_disable(intr_handle);
1948 if (intr_handle->intr_vec != NULL) {
1949 rte_free(intr_handle->intr_vec);
1950 intr_handle->intr_vec = NULL;
1956 * Set device link up: enable tx.
1959 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1961 struct ixgbe_hw *hw =
1962 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1963 if (hw->mac.type == ixgbe_mac_82599EB) {
1964 #ifdef RTE_NIC_BYPASS
1965 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1966 /* Not suported in bypass mode */
1967 PMD_INIT_LOG(ERR, "Set link up is not supported "
1968 "by device id 0x%x", hw->device_id);
1974 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1975 /* Turn on the copper */
1976 ixgbe_set_phy_power(hw, true);
1978 /* Turn on the laser */
1979 ixgbe_enable_tx_laser(hw);
1986 * Set device link down: disable tx.
1989 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1991 struct ixgbe_hw *hw =
1992 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993 if (hw->mac.type == ixgbe_mac_82599EB) {
1994 #ifdef RTE_NIC_BYPASS
1995 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1996 /* Not suported in bypass mode */
1997 PMD_INIT_LOG(ERR, "Set link down is not supported "
1998 "by device id 0x%x", hw->device_id);
2004 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2005 /* Turn off the copper */
2006 ixgbe_set_phy_power(hw, false);
2008 /* Turn off the laser */
2009 ixgbe_disable_tx_laser(hw);
2016 * Reest and stop device.
2019 ixgbe_dev_close(struct rte_eth_dev *dev)
2021 struct ixgbe_hw *hw =
2022 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024 PMD_INIT_FUNC_TRACE();
2026 ixgbe_pf_reset_hw(hw);
2028 ixgbe_dev_stop(dev);
2029 hw->adapter_stopped = 1;
2031 ixgbe_dev_free_queues(dev);
2033 ixgbe_disable_pcie_master(hw);
2035 /* reprogram the RAR[0] in case user changed it. */
2036 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2040 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2041 *hw_stats, uint64_t *total_missed_rx,
2042 uint64_t *total_qbrc, uint64_t *total_qprc,
2043 uint64_t *total_qprdc)
2045 uint32_t bprc, lxon, lxoff, total;
2048 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2049 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2050 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2051 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2053 for (i = 0; i < 8; i++) {
2055 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2056 /* global total per queue */
2057 hw_stats->mpc[i] += mp;
2058 /* Running comprehensive total for stats display */
2059 *total_missed_rx += hw_stats->mpc[i];
2060 if (hw->mac.type == ixgbe_mac_82598EB)
2061 hw_stats->rnbc[i] +=
2062 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2063 hw_stats->pxontxc[i] +=
2064 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2065 hw_stats->pxonrxc[i] +=
2066 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2067 hw_stats->pxofftxc[i] +=
2068 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2069 hw_stats->pxoffrxc[i] +=
2070 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2071 hw_stats->pxon2offc[i] +=
2072 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2074 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2075 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2076 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2077 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2078 hw_stats->qbrc[i] +=
2079 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2080 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2081 hw_stats->qbtc[i] +=
2082 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2083 *total_qprdc += hw_stats->qprdc[i] +=
2084 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2086 *total_qprc += hw_stats->qprc[i];
2087 *total_qbrc += hw_stats->qbrc[i];
2089 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2090 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2091 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2093 /* Note that gprc counts missed packets */
2094 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2096 if (hw->mac.type != ixgbe_mac_82598EB) {
2097 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2098 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2099 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2100 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2101 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2102 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2103 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2104 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2106 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2107 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2108 /* 82598 only has a counter in the high register */
2109 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2110 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2111 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2115 * Workaround: mprc hardware is incorrectly counting
2116 * broadcasts, so for now we subtract those.
2118 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2119 hw_stats->bprc += bprc;
2120 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2121 if (hw->mac.type == ixgbe_mac_82598EB)
2122 hw_stats->mprc -= bprc;
2124 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2125 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2126 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2127 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2128 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2129 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2131 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2132 hw_stats->lxontxc += lxon;
2133 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2134 hw_stats->lxofftxc += lxoff;
2135 total = lxon + lxoff;
2137 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2138 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2139 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2140 hw_stats->gptc -= total;
2141 hw_stats->mptc -= total;
2142 hw_stats->ptc64 -= total;
2143 hw_stats->gotc -= total * ETHER_MIN_LEN;
2145 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2146 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2147 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2148 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2149 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2150 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2151 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2152 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2153 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2154 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2155 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2156 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2157 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2158 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2159 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2160 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2161 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2162 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2163 /* Only read FCOE on 82599 */
2164 if (hw->mac.type != ixgbe_mac_82598EB) {
2165 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2166 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2167 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2168 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2169 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2172 /* Flow Director Stats registers */
2173 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2174 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2178 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2181 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2183 struct ixgbe_hw *hw =
2184 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185 struct ixgbe_hw_stats *hw_stats =
2186 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2187 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2190 total_missed_rx = 0;
2195 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2196 &total_qprc, &total_qprdc);
2201 /* Fill out the rte_eth_stats statistics structure */
2202 stats->ipackets = total_qprc;
2203 stats->ibytes = total_qbrc;
2204 stats->opackets = hw_stats->gptc;
2205 stats->obytes = hw_stats->gotc;
2207 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2208 stats->q_ipackets[i] = hw_stats->qprc[i];
2209 stats->q_opackets[i] = hw_stats->qptc[i];
2210 stats->q_ibytes[i] = hw_stats->qbrc[i];
2211 stats->q_obytes[i] = hw_stats->qbtc[i];
2212 stats->q_errors[i] = hw_stats->qprdc[i];
2216 stats->ierrors = hw_stats->crcerrs +
2236 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2238 struct ixgbe_hw_stats *stats =
2239 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2241 /* HW registers are cleared on read */
2242 ixgbe_dev_stats_get(dev, NULL);
2244 /* Reset software totals */
2245 memset(stats, 0, sizeof(*stats));
2249 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2252 struct ixgbe_hw *hw =
2253 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2254 struct ixgbe_hw_stats *hw_stats =
2255 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2256 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2257 unsigned i, count = IXGBE_NB_XSTATS;
2262 total_missed_rx = 0;
2267 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2268 &total_qprc, &total_qprdc);
2270 /* If this is a reset xstats is NULL, and we have cleared the
2271 * registers by reading them.
2276 /* Extended stats */
2277 for (i = 0; i < IXGBE_NB_XSTATS; i++) {
2278 snprintf(xstats[i].name, sizeof(xstats[i].name),
2279 "%s", rte_ixgbe_stats_strings[i].name);
2280 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2281 rte_ixgbe_stats_strings[i].offset);
2288 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2290 struct ixgbe_hw_stats *stats =
2291 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2293 /* HW registers are cleared on read */
2294 ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2296 /* Reset software totals */
2297 memset(stats, 0, sizeof(*stats));
2301 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2303 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2305 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2307 /* Good Rx packet, include VF loopback */
2308 UPDATE_VF_STAT(IXGBE_VFGPRC,
2309 hw_stats->last_vfgprc, hw_stats->vfgprc);
2311 /* Good Rx octets, include VF loopback */
2312 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2313 hw_stats->last_vfgorc, hw_stats->vfgorc);
2315 /* Good Tx packet, include VF loopback */
2316 UPDATE_VF_STAT(IXGBE_VFGPTC,
2317 hw_stats->last_vfgptc, hw_stats->vfgptc);
2319 /* Good Tx octets, include VF loopback */
2320 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2321 hw_stats->last_vfgotc, hw_stats->vfgotc);
2323 /* Rx Multicst Packet */
2324 UPDATE_VF_STAT(IXGBE_VFMPRC,
2325 hw_stats->last_vfmprc, hw_stats->vfmprc);
2330 stats->ipackets = hw_stats->vfgprc;
2331 stats->ibytes = hw_stats->vfgorc;
2332 stats->opackets = hw_stats->vfgptc;
2333 stats->obytes = hw_stats->vfgotc;
2334 stats->imcasts = hw_stats->vfmprc;
2335 /* stats->imcasts should be removed as imcasts is deprecated */
2339 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2341 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2342 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2344 /* Sync HW register to the last stats */
2345 ixgbevf_dev_stats_get(dev, NULL);
2347 /* reset HW current stats*/
2348 hw_stats->vfgprc = 0;
2349 hw_stats->vfgorc = 0;
2350 hw_stats->vfgptc = 0;
2351 hw_stats->vfgotc = 0;
2352 hw_stats->vfmprc = 0;
2357 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2359 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2361 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2362 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2363 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2364 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2365 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2366 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2367 dev_info->max_vfs = dev->pci_dev->max_vfs;
2368 if (hw->mac.type == ixgbe_mac_82598EB)
2369 dev_info->max_vmdq_pools = ETH_16_POOLS;
2371 dev_info->max_vmdq_pools = ETH_64_POOLS;
2372 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2373 dev_info->rx_offload_capa =
2374 DEV_RX_OFFLOAD_VLAN_STRIP |
2375 DEV_RX_OFFLOAD_IPV4_CKSUM |
2376 DEV_RX_OFFLOAD_UDP_CKSUM |
2377 DEV_RX_OFFLOAD_TCP_CKSUM;
2380 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2383 if ((hw->mac.type == ixgbe_mac_82599EB ||
2384 hw->mac.type == ixgbe_mac_X540) &&
2385 !RTE_ETH_DEV_SRIOV(dev).active)
2386 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2388 dev_info->tx_offload_capa =
2389 DEV_TX_OFFLOAD_VLAN_INSERT |
2390 DEV_TX_OFFLOAD_IPV4_CKSUM |
2391 DEV_TX_OFFLOAD_UDP_CKSUM |
2392 DEV_TX_OFFLOAD_TCP_CKSUM |
2393 DEV_TX_OFFLOAD_SCTP_CKSUM |
2394 DEV_TX_OFFLOAD_TCP_TSO;
2396 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2398 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2399 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2400 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2402 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2406 dev_info->default_txconf = (struct rte_eth_txconf) {
2408 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2409 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2410 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2412 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2413 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2414 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2415 ETH_TXQ_FLAGS_NOOFFLOADS,
2417 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2418 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2419 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2423 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2424 struct rte_eth_dev_info *dev_info)
2426 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2428 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2429 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2430 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2431 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2432 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2433 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2434 dev_info->max_vfs = dev->pci_dev->max_vfs;
2435 if (hw->mac.type == ixgbe_mac_82598EB)
2436 dev_info->max_vmdq_pools = ETH_16_POOLS;
2438 dev_info->max_vmdq_pools = ETH_64_POOLS;
2439 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2440 DEV_RX_OFFLOAD_IPV4_CKSUM |
2441 DEV_RX_OFFLOAD_UDP_CKSUM |
2442 DEV_RX_OFFLOAD_TCP_CKSUM;
2443 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2444 DEV_TX_OFFLOAD_IPV4_CKSUM |
2445 DEV_TX_OFFLOAD_UDP_CKSUM |
2446 DEV_TX_OFFLOAD_TCP_CKSUM |
2447 DEV_TX_OFFLOAD_SCTP_CKSUM;
2449 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2451 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2452 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2453 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2455 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2459 dev_info->default_txconf = (struct rte_eth_txconf) {
2461 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2462 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2463 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2465 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2466 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2467 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2468 ETH_TXQ_FLAGS_NOOFFLOADS,
2472 /* return 0 means link status changed, -1 means not changed */
2474 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2476 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477 struct rte_eth_link link, old;
2478 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2482 link.link_status = 0;
2483 link.link_speed = 0;
2484 link.link_duplex = 0;
2485 memset(&old, 0, sizeof(old));
2486 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2488 hw->mac.get_link_status = true;
2490 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2491 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2492 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2494 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2497 link.link_speed = ETH_LINK_SPEED_100;
2498 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2499 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2500 if (link.link_status == old.link_status)
2506 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2507 if (link.link_status == old.link_status)
2511 link.link_status = 1;
2512 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2514 switch (link_speed) {
2516 case IXGBE_LINK_SPEED_UNKNOWN:
2517 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2518 link.link_speed = ETH_LINK_SPEED_100;
2521 case IXGBE_LINK_SPEED_100_FULL:
2522 link.link_speed = ETH_LINK_SPEED_100;
2525 case IXGBE_LINK_SPEED_1GB_FULL:
2526 link.link_speed = ETH_LINK_SPEED_1000;
2529 case IXGBE_LINK_SPEED_10GB_FULL:
2530 link.link_speed = ETH_LINK_SPEED_10000;
2533 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2535 if (link.link_status == old.link_status)
2542 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2544 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2547 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2548 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2549 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2553 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2555 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2558 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2559 fctrl &= (~IXGBE_FCTRL_UPE);
2560 if (dev->data->all_multicast == 1)
2561 fctrl |= IXGBE_FCTRL_MPE;
2563 fctrl &= (~IXGBE_FCTRL_MPE);
2564 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2568 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2570 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2574 fctrl |= IXGBE_FCTRL_MPE;
2575 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2579 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2581 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584 if (dev->data->promiscuous == 1)
2585 return; /* must remain in all_multicast mode */
2587 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2588 fctrl &= (~IXGBE_FCTRL_MPE);
2589 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2593 * It clears the interrupt causes and enables the interrupt.
2594 * It will be called once only during nic initialized.
2597 * Pointer to struct rte_eth_dev.
2600 * - On success, zero.
2601 * - On failure, a negative value.
2604 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2606 struct ixgbe_interrupt *intr =
2607 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2609 ixgbe_dev_link_status_print(dev);
2610 intr->mask |= IXGBE_EICR_LSC;
2616 * It clears the interrupt causes and enables the interrupt.
2617 * It will be called once only during nic initialized.
2620 * Pointer to struct rte_eth_dev.
2623 * - On success, zero.
2624 * - On failure, a negative value.
2628 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2630 struct ixgbe_interrupt *intr =
2631 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2633 intr->mask |= IXGBE_EICR_RTX_QUEUE;
2640 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2643 * Pointer to struct rte_eth_dev.
2646 * - On success, zero.
2647 * - On failure, a negative value.
2650 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2653 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654 struct ixgbe_interrupt *intr =
2655 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2657 /* clear all cause mask */
2658 ixgbe_disable_intr(hw);
2660 /* read-on-clear nic registers here */
2661 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2662 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2666 /* set flag for async link update */
2667 if (eicr & IXGBE_EICR_LSC)
2668 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2670 if (eicr & IXGBE_EICR_MAILBOX)
2671 intr->flags |= IXGBE_FLAG_MAILBOX;
2677 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
2680 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681 struct ixgbe_interrupt *intr =
2682 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2684 /* clear all cause mask */
2685 ixgbevf_intr_disable(hw);
2687 /* read-on-clear nic registers here */
2688 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
2689 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2693 /* set flag for async link update */
2694 if (eicr & IXGBE_EICR_LSC)
2695 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2701 * It gets and then prints the link status.
2704 * Pointer to struct rte_eth_dev.
2707 * - On success, zero.
2708 * - On failure, a negative value.
2711 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2713 struct rte_eth_link link;
2715 memset(&link, 0, sizeof(link));
2716 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2717 if (link.link_status) {
2718 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2719 (int)(dev->data->port_id),
2720 (unsigned)link.link_speed,
2721 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2722 "full-duplex" : "half-duplex");
2724 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2725 (int)(dev->data->port_id));
2727 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2728 dev->pci_dev->addr.domain,
2729 dev->pci_dev->addr.bus,
2730 dev->pci_dev->addr.devid,
2731 dev->pci_dev->addr.function);
2735 * It executes link_update after knowing an interrupt occurred.
2738 * Pointer to struct rte_eth_dev.
2741 * - On success, zero.
2742 * - On failure, a negative value.
2745 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2747 struct ixgbe_interrupt *intr =
2748 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2750 struct rte_eth_link link;
2751 int intr_enable_delay = false;
2753 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2755 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2756 ixgbe_pf_mbx_process(dev);
2757 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2760 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2761 /* get the link status before link update, for predicting later */
2762 memset(&link, 0, sizeof(link));
2763 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2765 ixgbe_dev_link_update(dev, 0);
2768 if (!link.link_status)
2769 /* handle it 1 sec later, wait it being stable */
2770 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2771 /* likely to down */
2773 /* handle it 4 sec later, wait it being stable */
2774 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2776 ixgbe_dev_link_status_print(dev);
2778 intr_enable_delay = true;
2781 if (intr_enable_delay) {
2782 if (rte_eal_alarm_set(timeout * 1000,
2783 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2784 PMD_DRV_LOG(ERR, "Error setting alarm");
2786 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2787 ixgbe_enable_intr(dev);
2788 rte_intr_enable(&(dev->pci_dev->intr_handle));
2796 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
2798 struct ixgbe_hw *hw =
2799 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2802 ixgbevf_intr_enable(hw);
2803 rte_intr_enable(&dev->pci_dev->intr_handle);
2808 * Interrupt handler which shall be registered for alarm callback for delayed
2809 * handling specific interrupt to wait for the stable nic state. As the
2810 * NIC interrupt state is not stable for ixgbe after link is just down,
2811 * it needs to wait 4 seconds to get the stable status.
2814 * Pointer to interrupt handle.
2816 * The address of parameter (struct rte_eth_dev *) regsitered before.
2822 ixgbe_dev_interrupt_delayed_handler(void *param)
2824 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2825 struct ixgbe_interrupt *intr =
2826 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2827 struct ixgbe_hw *hw =
2828 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2831 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2832 if (eicr & IXGBE_EICR_MAILBOX)
2833 ixgbe_pf_mbx_process(dev);
2835 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2836 ixgbe_dev_link_update(dev, 0);
2837 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2838 ixgbe_dev_link_status_print(dev);
2839 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2842 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2843 ixgbe_enable_intr(dev);
2844 rte_intr_enable(&(dev->pci_dev->intr_handle));
2848 * Interrupt handler triggered by NIC for handling
2849 * specific interrupt.
2852 * Pointer to interrupt handle.
2854 * The address of parameter (struct rte_eth_dev *) regsitered before.
2860 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2863 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2865 ixgbe_dev_interrupt_get_status(dev);
2866 ixgbe_dev_interrupt_action(dev);
2870 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2873 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2875 ixgbevf_dev_interrupt_get_status(dev);
2876 ixgbevf_dev_interrupt_action(dev);
2880 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2882 struct ixgbe_hw *hw;
2884 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2885 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2889 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2891 struct ixgbe_hw *hw;
2893 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2894 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2898 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2900 struct ixgbe_hw *hw;
2906 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2908 fc_conf->pause_time = hw->fc.pause_time;
2909 fc_conf->high_water = hw->fc.high_water[0];
2910 fc_conf->low_water = hw->fc.low_water[0];
2911 fc_conf->send_xon = hw->fc.send_xon;
2912 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2915 * Return rx_pause status according to actual setting of
2918 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2919 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2925 * Return tx_pause status according to actual setting of
2928 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2929 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2934 if (rx_pause && tx_pause)
2935 fc_conf->mode = RTE_FC_FULL;
2937 fc_conf->mode = RTE_FC_RX_PAUSE;
2939 fc_conf->mode = RTE_FC_TX_PAUSE;
2941 fc_conf->mode = RTE_FC_NONE;
2947 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2949 struct ixgbe_hw *hw;
2951 uint32_t rx_buf_size;
2952 uint32_t max_high_water;
2954 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2961 PMD_INIT_FUNC_TRACE();
2963 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2965 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2968 * At least reserve one Ethernet frame for watermark
2969 * high_water/low_water in kilo bytes for ixgbe
2971 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2972 if ((fc_conf->high_water > max_high_water) ||
2973 (fc_conf->high_water < fc_conf->low_water)) {
2974 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2975 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2979 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2980 hw->fc.pause_time = fc_conf->pause_time;
2981 hw->fc.high_water[0] = fc_conf->high_water;
2982 hw->fc.low_water[0] = fc_conf->low_water;
2983 hw->fc.send_xon = fc_conf->send_xon;
2984 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2986 err = ixgbe_fc_enable(hw);
2988 /* Not negotiated is not an error case */
2989 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2991 /* check if we want to forward MAC frames - driver doesn't have native
2992 * capability to do that, so we'll write the registers ourselves */
2994 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2996 /* set or clear MFLCN.PMCF bit depending on configuration */
2997 if (fc_conf->mac_ctrl_frame_fwd != 0)
2998 mflcn |= IXGBE_MFLCN_PMCF;
3000 mflcn &= ~IXGBE_MFLCN_PMCF;
3002 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3003 IXGBE_WRITE_FLUSH(hw);
3008 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3013 * ixgbe_pfc_enable_generic - Enable flow control
3014 * @hw: pointer to hardware structure
3015 * @tc_num: traffic class number
3016 * Enable flow control according to the current settings.
3019 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3022 uint32_t mflcn_reg, fccfg_reg;
3024 uint32_t fcrtl, fcrth;
3028 /* Validate the water mark configuration */
3029 if (!hw->fc.pause_time) {
3030 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3034 /* Low water mark of zero causes XOFF floods */
3035 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3036 /* High/Low water can not be 0 */
3037 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3038 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3039 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3043 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3044 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3045 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3049 /* Negotiate the fc mode to use */
3050 ixgbe_fc_autoneg(hw);
3052 /* Disable any previous flow control settings */
3053 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3054 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3056 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3057 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3059 switch (hw->fc.current_mode) {
3062 * If the count of enabled RX Priority Flow control >1,
3063 * and the TX pause can not be disabled
3066 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3067 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3068 if (reg & IXGBE_FCRTH_FCEN)
3072 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3074 case ixgbe_fc_rx_pause:
3076 * Rx Flow control is enabled and Tx Flow control is
3077 * disabled by software override. Since there really
3078 * isn't a way to advertise that we are capable of RX
3079 * Pause ONLY, we will advertise that we support both
3080 * symmetric and asymmetric Rx PAUSE. Later, we will
3081 * disable the adapter's ability to send PAUSE frames.
3083 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3085 * If the count of enabled RX Priority Flow control >1,
3086 * and the TX pause can not be disabled
3089 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3090 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3091 if (reg & IXGBE_FCRTH_FCEN)
3095 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3097 case ixgbe_fc_tx_pause:
3099 * Tx Flow control is enabled, and Rx Flow control is
3100 * disabled by software override.
3102 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3105 /* Flow control (both Rx and Tx) is enabled by SW override. */
3106 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3107 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3110 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3111 ret_val = IXGBE_ERR_CONFIG;
3116 /* Set 802.3x based flow control settings. */
3117 mflcn_reg |= IXGBE_MFLCN_DPF;
3118 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3119 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3121 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3122 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3123 hw->fc.high_water[tc_num]) {
3124 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3125 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3126 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3128 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3130 * In order to prevent Tx hangs when the internal Tx
3131 * switch is enabled we must set the high water mark
3132 * to the maximum FCRTH value. This allows the Tx
3133 * switch to function even under heavy Rx workloads.
3135 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3137 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3139 /* Configure pause time (2 TCs per register) */
3140 reg = hw->fc.pause_time * 0x00010001;
3141 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3142 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3144 /* Configure flow control refresh threshold value */
3145 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3152 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3154 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3155 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3157 if(hw->mac.type != ixgbe_mac_82598EB) {
3158 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3164 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3167 uint32_t rx_buf_size;
3168 uint32_t max_high_water;
3170 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3171 struct ixgbe_hw *hw =
3172 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3173 struct ixgbe_dcb_config *dcb_config =
3174 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3176 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3183 PMD_INIT_FUNC_TRACE();
3185 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3186 tc_num = map[pfc_conf->priority];
3187 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3188 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3190 * At least reserve one Ethernet frame for watermark
3191 * high_water/low_water in kilo bytes for ixgbe
3193 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3194 if ((pfc_conf->fc.high_water > max_high_water) ||
3195 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3196 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3197 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3201 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3202 hw->fc.pause_time = pfc_conf->fc.pause_time;
3203 hw->fc.send_xon = pfc_conf->fc.send_xon;
3204 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3205 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3207 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3209 /* Not negotiated is not an error case */
3210 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3213 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3218 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3219 struct rte_eth_rss_reta_entry64 *reta_conf,
3224 uint16_t idx, shift;
3225 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3227 PMD_INIT_FUNC_TRACE();
3228 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3229 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3230 "(%d) doesn't match the number hardware can supported "
3231 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3235 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3236 idx = i / RTE_RETA_GROUP_SIZE;
3237 shift = i % RTE_RETA_GROUP_SIZE;
3238 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3242 if (mask == IXGBE_4_BIT_MASK)
3245 r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
3246 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3247 if (mask & (0x1 << j))
3248 reta |= reta_conf[idx].reta[shift + j] <<
3251 reta |= r & (IXGBE_8_BIT_MASK <<
3254 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3261 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3262 struct rte_eth_rss_reta_entry64 *reta_conf,
3267 uint16_t idx, shift;
3268 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3270 PMD_INIT_FUNC_TRACE();
3271 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3272 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3273 "(%d) doesn't match the number hardware can supported "
3274 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3278 for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
3279 idx = i / RTE_RETA_GROUP_SIZE;
3280 shift = i % RTE_RETA_GROUP_SIZE;
3281 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3286 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
3287 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3288 if (mask & (0x1 << j))
3289 reta_conf[idx].reta[shift + j] =
3290 ((reta >> (CHAR_BIT * j)) &
3299 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3300 uint32_t index, uint32_t pool)
3302 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3303 uint32_t enable_addr = 1;
3305 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3309 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3311 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313 ixgbe_clear_rar(hw, index);
3317 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3319 ixgbe_remove_rar(dev, 0);
3321 ixgbe_add_rar(dev, addr, 0, 0);
3325 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3329 struct ixgbe_hw *hw;
3330 struct rte_eth_dev_info dev_info;
3331 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3333 ixgbe_dev_info_get(dev, &dev_info);
3335 /* check that mtu is within the allowed range */
3336 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3339 /* refuse mtu that requires the support of scattered packets when this
3340 * feature has not been enabled before. */
3341 if (!dev->data->scattered_rx &&
3342 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3343 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3346 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3347 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3349 /* switch to jumbo mode if needed */
3350 if (frame_size > ETHER_MAX_LEN) {
3351 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3352 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3354 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3355 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3357 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3359 /* update max frame size */
3360 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3362 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3363 maxfrs &= 0x0000FFFF;
3364 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3365 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3371 * Virtual Function operations
3374 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3376 PMD_INIT_FUNC_TRACE();
3378 /* Clear interrupt mask to stop from interrupts being generated */
3379 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3381 IXGBE_WRITE_FLUSH(hw);
3385 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3387 PMD_INIT_FUNC_TRACE();
3389 /* VF enable interrupt autoclean */
3390 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3391 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3392 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3394 IXGBE_WRITE_FLUSH(hw);
3398 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3400 struct rte_eth_conf* conf = &dev->data->dev_conf;
3401 struct ixgbe_adapter *adapter =
3402 (struct ixgbe_adapter *)dev->data->dev_private;
3404 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3405 dev->data->port_id);
3408 * VF has no ability to enable/disable HW CRC
3409 * Keep the persistent behavior the same as Host PF
3411 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3412 if (!conf->rxmode.hw_strip_crc) {
3413 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
3414 conf->rxmode.hw_strip_crc = 1;
3417 if (conf->rxmode.hw_strip_crc) {
3418 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
3419 conf->rxmode.hw_strip_crc = 0;
3424 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3425 * allocation or vector Rx preconditions we will reset it.
3427 adapter->rx_bulk_alloc_allowed = true;
3428 adapter->rx_vec_allowed = true;
3434 ixgbevf_dev_start(struct rte_eth_dev *dev)
3436 struct ixgbe_hw *hw =
3437 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439 uint32_t intr_vector = 0;
3441 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3445 PMD_INIT_FUNC_TRACE();
3447 hw->mac.ops.reset_hw(hw);
3448 hw->mac.get_link_status = true;
3450 /* negotiate mailbox API version to use with the PF. */
3451 ixgbevf_negotiate_api(hw);
3453 ixgbevf_dev_tx_init(dev);
3455 /* This can fail when allocating mbufs for descriptor rings */
3456 err = ixgbevf_dev_rx_init(dev);
3458 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3459 ixgbe_dev_clear_queues(dev);
3464 ixgbevf_set_vfta_all(dev,1);
3467 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3468 ETH_VLAN_EXTEND_MASK;
3469 ixgbevf_vlan_offload_set(dev, mask);
3471 ixgbevf_dev_rxtx_start(dev);
3474 /* check and configure queue intr-vector mapping */
3475 if (dev->data->dev_conf.intr_conf.rxq != 0)
3476 intr_vector = dev->data->nb_rx_queues;
3478 if (rte_intr_efd_enable(intr_handle, intr_vector))
3481 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3482 intr_handle->intr_vec =
3483 rte_zmalloc("intr_vec",
3484 dev->data->nb_rx_queues * sizeof(int), 0);
3485 if (intr_handle->intr_vec == NULL) {
3486 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3487 " intr_vec\n", dev->data->nb_rx_queues);
3492 ixgbevf_configure_msix(dev);
3494 if (dev->data->dev_conf.intr_conf.lsc != 0) {
3495 if (rte_intr_allow_others(intr_handle))
3496 rte_intr_callback_register(intr_handle,
3497 ixgbevf_dev_interrupt_handler,
3500 PMD_INIT_LOG(INFO, "lsc won't enable because of"
3501 " no intr multiplex\n");
3504 rte_intr_enable(intr_handle);
3506 /* Re-enable interrupt for VF */
3507 ixgbevf_intr_enable(hw);
3513 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3515 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3516 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3518 PMD_INIT_FUNC_TRACE();
3520 hw->adapter_stopped = 1;
3521 ixgbe_stop_adapter(hw);
3524 * Clear what we set, but we still keep shadow_vfta to
3525 * restore after device starts
3527 ixgbevf_set_vfta_all(dev,0);
3529 /* Clear stored conf */
3530 dev->data->scattered_rx = 0;
3532 ixgbe_dev_clear_queues(dev);
3534 /* disable intr eventfd mapping */
3535 rte_intr_disable(intr_handle);
3538 /* Clean datapath event and queue/vec mapping */
3539 rte_intr_efd_disable(intr_handle);
3540 if (intr_handle->intr_vec != NULL) {
3541 rte_free(intr_handle->intr_vec);
3542 intr_handle->intr_vec = NULL;
3548 ixgbevf_dev_close(struct rte_eth_dev *dev)
3550 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3552 struct rte_pci_device *pci_dev;
3555 PMD_INIT_FUNC_TRACE();
3559 ixgbevf_dev_stop(dev);
3561 ixgbe_dev_free_queues(dev);
3563 /* reprogram the RAR[0] in case user changed it. */
3564 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3567 pci_dev = dev->pci_dev;
3568 if (pci_dev->intr_handle.intr_vec) {
3569 rte_free(pci_dev->intr_handle.intr_vec);
3570 pci_dev->intr_handle.intr_vec = NULL;
3575 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3577 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578 struct ixgbe_vfta * shadow_vfta =
3579 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3580 int i = 0, j = 0, vfta = 0, mask = 1;
3582 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3583 vfta = shadow_vfta->vfta[i];
3586 for (j = 0; j < 32; j++){
3588 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3597 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3599 struct ixgbe_hw *hw =
3600 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601 struct ixgbe_vfta * shadow_vfta =
3602 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3603 uint32_t vid_idx = 0;
3604 uint32_t vid_bit = 0;
3607 PMD_INIT_FUNC_TRACE();
3609 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3610 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3612 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3615 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3616 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3618 /* Save what we set and retore it after device reset */
3620 shadow_vfta->vfta[vid_idx] |= vid_bit;
3622 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3628 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3630 struct ixgbe_hw *hw =
3631 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3634 PMD_INIT_FUNC_TRACE();
3636 if(queue >= hw->mac.max_rx_queues)
3639 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3641 ctrl |= IXGBE_RXDCTL_VME;
3643 ctrl &= ~IXGBE_RXDCTL_VME;
3644 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3646 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3650 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3652 struct ixgbe_hw *hw =
3653 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3657 /* VF function only support hw strip feature, others are not support */
3658 if(mask & ETH_VLAN_STRIP_MASK){
3659 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3661 for(i=0; i < hw->mac.max_rx_queues; i++)
3662 ixgbevf_vlan_strip_queue_set(dev,i,on);
3667 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3671 /* we only need to do this if VMDq is enabled */
3672 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3673 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3674 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3682 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3684 uint32_t vector = 0;
3685 switch (hw->mac.mc_filter_type) {
3686 case 0: /* use bits [47:36] of the address */
3687 vector = ((uc_addr->addr_bytes[4] >> 4) |
3688 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3690 case 1: /* use bits [46:35] of the address */
3691 vector = ((uc_addr->addr_bytes[4] >> 3) |
3692 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3694 case 2: /* use bits [45:34] of the address */
3695 vector = ((uc_addr->addr_bytes[4] >> 2) |
3696 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3698 case 3: /* use bits [43:32] of the address */
3699 vector = ((uc_addr->addr_bytes[4]) |
3700 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3702 default: /* Invalid mc_filter_type */
3706 /* vector can only be 12-bits or boundary will be exceeded */
3712 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3720 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3721 const uint32_t ixgbe_uta_bit_shift = 5;
3722 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3723 const uint32_t bit1 = 0x1;
3725 struct ixgbe_hw *hw =
3726 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3727 struct ixgbe_uta_info *uta_info =
3728 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3730 /* The UTA table only exists on 82599 hardware and newer */
3731 if (hw->mac.type < ixgbe_mac_82599EB)
3734 vector = ixgbe_uta_vector(hw,mac_addr);
3735 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3736 uta_shift = vector & ixgbe_uta_bit_mask;
3738 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3742 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3744 uta_info->uta_in_use++;
3745 reg_val |= (bit1 << uta_shift);
3746 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3748 uta_info->uta_in_use--;
3749 reg_val &= ~(bit1 << uta_shift);
3750 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3753 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3755 if (uta_info->uta_in_use > 0)
3756 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3757 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3759 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3765 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3768 struct ixgbe_hw *hw =
3769 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3770 struct ixgbe_uta_info *uta_info =
3771 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3773 /* The UTA table only exists on 82599 hardware and newer */
3774 if (hw->mac.type < ixgbe_mac_82599EB)
3778 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3779 uta_info->uta_shadow[i] = ~0;
3780 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3783 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3784 uta_info->uta_shadow[i] = 0;
3785 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3793 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3795 uint32_t new_val = orig_val;
3797 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3798 new_val |= IXGBE_VMOLR_AUPE;
3799 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3800 new_val |= IXGBE_VMOLR_ROMPE;
3801 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3802 new_val |= IXGBE_VMOLR_ROPE;
3803 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3804 new_val |= IXGBE_VMOLR_BAM;
3805 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3806 new_val |= IXGBE_VMOLR_MPE;
3812 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3813 uint16_t rx_mask, uint8_t on)
3817 struct ixgbe_hw *hw =
3818 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3819 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3821 if (hw->mac.type == ixgbe_mac_82598EB) {
3822 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3823 " on 82599 hardware and newer");
3826 if (ixgbe_vmdq_mode_check(hw) < 0)
3829 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3836 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3842 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3846 const uint8_t bit1 = 0x1;
3848 struct ixgbe_hw *hw =
3849 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3851 if (ixgbe_vmdq_mode_check(hw) < 0)
3854 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3855 reg = IXGBE_READ_REG(hw, addr);
3863 IXGBE_WRITE_REG(hw, addr,reg);
3869 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3873 const uint8_t bit1 = 0x1;
3875 struct ixgbe_hw *hw =
3876 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3878 if (ixgbe_vmdq_mode_check(hw) < 0)
3881 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3882 reg = IXGBE_READ_REG(hw, addr);
3890 IXGBE_WRITE_REG(hw, addr,reg);
3896 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3897 uint64_t pool_mask, uint8_t vlan_on)
3901 struct ixgbe_hw *hw =
3902 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3904 if (ixgbe_vmdq_mode_check(hw) < 0)
3906 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3907 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3908 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3916 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
3917 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
3918 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
3919 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
3920 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
3921 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
3922 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
3925 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3926 struct rte_eth_mirror_conf *mirror_conf,
3927 uint8_t rule_id, uint8_t on)
3929 uint32_t mr_ctl,vlvf;
3930 uint32_t mp_lsb = 0;
3931 uint32_t mv_msb = 0;
3932 uint32_t mv_lsb = 0;
3933 uint32_t mp_msb = 0;
3936 uint64_t vlan_mask = 0;
3938 const uint8_t pool_mask_offset = 32;
3939 const uint8_t vlan_mask_offset = 32;
3940 const uint8_t dst_pool_offset = 8;
3941 const uint8_t rule_mr_offset = 4;
3942 const uint8_t mirror_rule_mask= 0x0F;
3944 struct ixgbe_mirror_info *mr_info =
3945 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3946 struct ixgbe_hw *hw =
3947 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3948 uint8_t mirror_type = 0;
3950 if (ixgbe_vmdq_mode_check(hw) < 0)
3953 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3956 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
3957 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
3958 mirror_conf->rule_type);
3962 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
3963 mirror_type |= IXGBE_MRCTL_VLME;
3964 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3965 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3966 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3967 /* search vlan id related pool vlan filter index */
3968 reg_index = ixgbe_find_vlvf_slot(hw,
3969 mirror_conf->vlan.vlan_id[i]);
3972 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3973 if ((vlvf & IXGBE_VLVF_VIEN) &&
3974 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
3975 mirror_conf->vlan.vlan_id[i]))
3976 vlan_mask |= (1ULL << reg_index);
3983 mv_lsb = vlan_mask & 0xFFFFFFFF;
3984 mv_msb = vlan_mask >> vlan_mask_offset;
3986 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3987 mirror_conf->vlan.vlan_mask;
3988 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3989 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3990 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3991 mirror_conf->vlan.vlan_id[i];
3996 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3997 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3998 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4003 * if enable pool mirror, write related pool mask register,if disable
4004 * pool mirror, clear PFMRVM register
4006 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4007 mirror_type |= IXGBE_MRCTL_VPME;
4009 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4010 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4011 mr_info->mr_conf[rule_id].pool_mask =
4012 mirror_conf->pool_mask;
4017 mr_info->mr_conf[rule_id].pool_mask = 0;
4020 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4021 mirror_type |= IXGBE_MRCTL_UPME;
4022 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4023 mirror_type |= IXGBE_MRCTL_DPME;
4025 /* read mirror control register and recalculate it */
4026 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4029 mr_ctl |= mirror_type;
4030 mr_ctl &= mirror_rule_mask;
4031 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4033 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4035 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4036 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4038 /* write mirrror control register */
4039 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4041 /* write pool mirrror control register */
4042 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4043 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4044 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4047 /* write VLAN mirrror control register */
4048 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4049 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4050 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4058 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4061 uint32_t lsb_val = 0;
4062 uint32_t msb_val = 0;
4063 const uint8_t rule_mr_offset = 4;
4065 struct ixgbe_hw *hw =
4066 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4067 struct ixgbe_mirror_info *mr_info =
4068 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4070 if (ixgbe_vmdq_mode_check(hw) < 0)
4073 memset(&mr_info->mr_conf[rule_id], 0,
4074 sizeof(struct rte_eth_mirror_conf));
4076 /* clear PFVMCTL register */
4077 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4079 /* clear pool mask register */
4080 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4081 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4083 /* clear vlan mask register */
4084 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4085 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4092 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4095 struct ixgbe_hw *hw =
4096 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4098 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4099 mask |= (1 << queue_id);
4100 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4102 rte_intr_enable(&dev->pci_dev->intr_handle);
4108 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4111 struct ixgbe_hw *hw =
4112 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4114 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4115 mask &= ~(1 << queue_id);
4116 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4122 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4125 struct ixgbe_hw *hw =
4126 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127 struct ixgbe_interrupt *intr =
4128 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4130 if (queue_id < 16) {
4131 ixgbe_disable_intr(hw);
4132 intr->mask |= (1 << queue_id);
4133 ixgbe_enable_intr(dev);
4134 } else if (queue_id < 32) {
4135 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4136 mask &= (1 << queue_id);
4137 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4138 } else if (queue_id < 64) {
4139 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4140 mask &= (1 << (queue_id - 32));
4141 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4143 rte_intr_enable(&dev->pci_dev->intr_handle);
4149 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4152 struct ixgbe_hw *hw =
4153 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4154 struct ixgbe_interrupt *intr =
4155 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4157 if (queue_id < 16) {
4158 ixgbe_disable_intr(hw);
4159 intr->mask &= ~(1 << queue_id);
4160 ixgbe_enable_intr(dev);
4161 } else if (queue_id < 32) {
4162 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4163 mask &= ~(1 << queue_id);
4164 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4165 } else if (queue_id < 64) {
4166 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4167 mask &= ~(1 << (queue_id - 32));
4168 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4175 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4176 uint8_t queue, uint8_t msix_vector)
4180 if (direction == -1) {
4182 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4183 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4186 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4188 /* rx or tx cause */
4189 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4190 idx = ((16 * (queue & 1)) + (8 * direction));
4191 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4192 tmp &= ~(0xFF << idx);
4193 tmp |= (msix_vector << idx);
4194 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4199 * set the IVAR registers, mapping interrupt causes to vectors
4201 * pointer to ixgbe_hw struct
4203 * 0 for Rx, 1 for Tx, -1 for other causes
4205 * queue to map the corresponding interrupt to
4207 * the vector to map to the corresponding queue
4210 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4211 uint8_t queue, uint8_t msix_vector)
4215 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4216 if (hw->mac.type == ixgbe_mac_82598EB) {
4217 if (direction == -1)
4219 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4220 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4221 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4222 tmp |= (msix_vector << (8 * (queue & 0x3)));
4223 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4224 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4225 (hw->mac.type == ixgbe_mac_X540)) {
4226 if (direction == -1) {
4228 idx = ((queue & 1) * 8);
4229 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4230 tmp &= ~(0xFF << idx);
4231 tmp |= (msix_vector << idx);
4232 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4234 /* rx or tx causes */
4235 idx = ((16 * (queue & 1)) + (8 * direction));
4236 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4237 tmp &= ~(0xFF << idx);
4238 tmp |= (msix_vector << idx);
4239 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4246 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4248 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4250 struct ixgbe_hw *hw =
4251 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4253 uint32_t vector_idx = 0;
4256 /* won't configure msix register if no mapping is done
4257 * between intr vector and event fd.
4259 if (!rte_intr_dp_is_en(intr_handle))
4263 /* Configure all RX queues of VF */
4264 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4265 /* Force all queue use vector 0,
4266 * as IXGBE_VF_MAXMSIVECOTR = 1
4268 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4269 intr_handle->intr_vec[q_idx] = vector_idx;
4272 /* Configure VF Rx queue ivar */
4273 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4278 * Sets up the hardware to properly generate MSI-X interrupts
4280 * board private structure
4283 ixgbe_configure_msix(struct rte_eth_dev *dev)
4285 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4287 struct ixgbe_hw *hw =
4288 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4289 uint32_t queue_id, vec = 0;
4294 /* won't configure msix register if no mapping is done
4295 * between intr vector and event fd
4297 if (!rte_intr_dp_is_en(intr_handle))
4301 /* setup GPIE for MSI-x mode */
4302 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4303 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4304 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4305 /* auto clearing and auto setting corresponding bits in EIMS
4306 * when MSI-X interrupt is triggered
4308 if (hw->mac.type == ixgbe_mac_82598EB) {
4309 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4311 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4312 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4314 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4316 /* Populate the IVAR table and set the ITR values to the
4317 * corresponding register.
4319 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4321 /* by default, 1:1 mapping */
4322 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4323 intr_handle->intr_vec[queue_id] = vec;
4324 if (vec < intr_handle->nb_efd - 1)
4328 switch (hw->mac.type) {
4329 case ixgbe_mac_82598EB:
4330 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4331 intr_handle->max_intr - 1);
4333 case ixgbe_mac_82599EB:
4334 case ixgbe_mac_X540:
4335 ixgbe_set_ivar_map(hw, -1, 1, intr_handle->max_intr - 1);
4340 IXGBE_WRITE_REG(hw, IXGBE_EITR(queue_id),
4341 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4343 /* set up to autoclear timer, and the vectors */
4344 mask = IXGBE_EIMS_ENABLE_MASK;
4345 mask &= ~(IXGBE_EIMS_OTHER |
4346 IXGBE_EIMS_MAILBOX |
4349 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4353 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4354 uint16_t queue_idx, uint16_t tx_rate)
4356 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4357 uint32_t rf_dec, rf_int;
4359 uint16_t link_speed = dev->data->dev_link.link_speed;
4361 if (queue_idx >= hw->mac.max_tx_queues)
4365 /* Calculate the rate factor values to set */
4366 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4367 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4368 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4370 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4371 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4372 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4373 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4379 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4380 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4383 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4384 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4385 IXGBE_MAX_JUMBO_FRAME_SIZE))
4386 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4387 IXGBE_MMW_SIZE_JUMBO_FRAME);
4389 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4390 IXGBE_MMW_SIZE_DEFAULT);
4392 /* Set RTTBCNRC of queue X */
4393 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4394 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4395 IXGBE_WRITE_FLUSH(hw);
4400 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4401 uint16_t tx_rate, uint64_t q_msk)
4403 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4404 struct ixgbe_vf_info *vfinfo =
4405 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4406 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4407 uint32_t queue_stride =
4408 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4409 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4410 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4411 uint16_t total_rate = 0;
4413 if (queue_end >= hw->mac.max_tx_queues)
4416 if (vfinfo != NULL) {
4417 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4420 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4422 total_rate += vfinfo[vf_idx].tx_rate[idx];
4427 /* Store tx_rate for this vf. */
4428 for (idx = 0; idx < nb_q_per_pool; idx++) {
4429 if (((uint64_t)0x1 << idx) & q_msk) {
4430 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4431 vfinfo[vf].tx_rate[idx] = tx_rate;
4432 total_rate += tx_rate;
4436 if (total_rate > dev->data->dev_link.link_speed) {
4438 * Reset stored TX rate of the VF if it causes exceed
4441 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4445 /* Set RTTBCNRC of each queue/pool for vf X */
4446 for (; queue_idx <= queue_end; queue_idx++) {
4448 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4456 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4457 __attribute__((unused)) uint32_t index,
4458 __attribute__((unused)) uint32_t pool)
4460 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4464 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4465 * operation. Trap this case to avoid exhausting the [very limited]
4466 * set of PF resources used to store VF MAC addresses.
4468 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4470 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4473 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4477 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4479 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4480 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4481 struct ether_addr *mac_addr;
4486 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4487 * not support the deletion of a given MAC address.
4488 * Instead, it imposes to delete all MAC addresses, then to add again
4489 * all MAC addresses with the exception of the one to be deleted.
4491 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4494 * Add again all MAC addresses, with the exception of the deleted one
4495 * and of the permanent MAC address.
4497 for (i = 0, mac_addr = dev->data->mac_addrs;
4498 i < hw->mac.num_rar_entries; i++, mac_addr++) {
4499 /* Skip the deleted MAC address */
4502 /* Skip NULL MAC addresses */
4503 if (is_zero_ether_addr(mac_addr))
4505 /* Skip the permanent MAC address */
4506 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4508 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4511 "Adding again MAC address "
4512 "%02x:%02x:%02x:%02x:%02x:%02x failed "
4514 mac_addr->addr_bytes[0],
4515 mac_addr->addr_bytes[1],
4516 mac_addr->addr_bytes[2],
4517 mac_addr->addr_bytes[3],
4518 mac_addr->addr_bytes[4],
4519 mac_addr->addr_bytes[5],
4525 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4527 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4529 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4532 #define MAC_TYPE_FILTER_SUP(type) do {\
4533 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4534 (type) != ixgbe_mac_X550)\
4539 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4540 struct rte_eth_syn_filter *filter,
4543 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4546 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4549 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4552 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4554 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4555 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4557 if (filter->hig_pri)
4558 synqf |= IXGBE_SYN_FILTER_SYNQFP;
4560 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4562 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4564 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4566 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4567 IXGBE_WRITE_FLUSH(hw);
4572 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4573 struct rte_eth_syn_filter *filter)
4575 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4576 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4578 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4579 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4580 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4587 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4588 enum rte_filter_op filter_op,
4591 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4594 MAC_TYPE_FILTER_SUP(hw->mac.type);
4596 if (filter_op == RTE_ETH_FILTER_NOP)
4600 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4605 switch (filter_op) {
4606 case RTE_ETH_FILTER_ADD:
4607 ret = ixgbe_syn_filter_set(dev,
4608 (struct rte_eth_syn_filter *)arg,
4611 case RTE_ETH_FILTER_DELETE:
4612 ret = ixgbe_syn_filter_set(dev,
4613 (struct rte_eth_syn_filter *)arg,
4616 case RTE_ETH_FILTER_GET:
4617 ret = ixgbe_syn_filter_get(dev,
4618 (struct rte_eth_syn_filter *)arg);
4621 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4630 static inline enum ixgbe_5tuple_protocol
4631 convert_protocol_type(uint8_t protocol_value)
4633 if (protocol_value == IPPROTO_TCP)
4634 return IXGBE_FILTER_PROTOCOL_TCP;
4635 else if (protocol_value == IPPROTO_UDP)
4636 return IXGBE_FILTER_PROTOCOL_UDP;
4637 else if (protocol_value == IPPROTO_SCTP)
4638 return IXGBE_FILTER_PROTOCOL_SCTP;
4640 return IXGBE_FILTER_PROTOCOL_NONE;
4644 * add a 5tuple filter
4647 * dev: Pointer to struct rte_eth_dev.
4648 * index: the index the filter allocates.
4649 * filter: ponter to the filter that will be added.
4650 * rx_queue: the queue id the filter assigned to.
4653 * - On success, zero.
4654 * - On failure, a negative value.
4657 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4658 struct ixgbe_5tuple_filter *filter)
4660 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4661 struct ixgbe_filter_info *filter_info =
4662 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4664 uint32_t ftqf, sdpqf;
4665 uint32_t l34timir = 0;
4666 uint8_t mask = 0xff;
4669 * look for an unused 5tuple filter index,
4670 * and insert the filter to list.
4672 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
4673 idx = i / (sizeof(uint32_t) * NBBY);
4674 shift = i % (sizeof(uint32_t) * NBBY);
4675 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
4676 filter_info->fivetuple_mask[idx] |= 1 << shift;
4678 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4684 if (i >= IXGBE_MAX_FTQF_FILTERS) {
4685 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4689 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
4690 IXGBE_SDPQF_DSTPORT_SHIFT);
4691 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
4693 ftqf = (uint32_t)(filter->filter_info.proto &
4694 IXGBE_FTQF_PROTOCOL_MASK);
4695 ftqf |= (uint32_t)((filter->filter_info.priority &
4696 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
4697 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
4698 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
4699 if (filter->filter_info.dst_ip_mask == 0)
4700 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
4701 if (filter->filter_info.src_port_mask == 0)
4702 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
4703 if (filter->filter_info.dst_port_mask == 0)
4704 mask &= IXGBE_FTQF_DEST_PORT_MASK;
4705 if (filter->filter_info.proto_mask == 0)
4706 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
4707 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
4708 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
4709 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
4711 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
4712 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
4713 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
4714 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
4716 l34timir |= IXGBE_L34T_IMIR_RESERVE;
4717 l34timir |= (uint32_t)(filter->queue <<
4718 IXGBE_L34T_IMIR_QUEUE_SHIFT);
4719 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
4724 * remove a 5tuple filter
4727 * dev: Pointer to struct rte_eth_dev.
4728 * filter: the pointer of the filter will be removed.
4731 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
4732 struct ixgbe_5tuple_filter *filter)
4734 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4735 struct ixgbe_filter_info *filter_info =
4736 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4737 uint16_t index = filter->index;
4739 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
4740 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
4741 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4744 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4745 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4746 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4747 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4748 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4752 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4754 struct ixgbe_hw *hw;
4755 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4757 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4759 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4762 /* refuse mtu that requires the support of scattered packets when this
4763 * feature has not been enabled before. */
4764 if (!dev->data->scattered_rx &&
4765 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4766 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4770 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4771 * request of the version 2.0 of the mailbox API.
4772 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4773 * of the mailbox API.
4774 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4775 * prior to 3.11.33 which contains the following change:
4776 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4778 ixgbevf_rlpml_set_vf(hw, max_frame);
4780 /* update max frame size */
4781 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4785 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
4786 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4790 static inline struct ixgbe_5tuple_filter *
4791 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4792 struct ixgbe_5tuple_filter_info *key)
4794 struct ixgbe_5tuple_filter *it;
4796 TAILQ_FOREACH(it, filter_list, entries) {
4797 if (memcmp(key, &it->filter_info,
4798 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4805 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4807 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4808 struct ixgbe_5tuple_filter_info *filter_info)
4810 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4811 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4812 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4815 switch (filter->dst_ip_mask) {
4817 filter_info->dst_ip_mask = 0;
4818 filter_info->dst_ip = filter->dst_ip;
4821 filter_info->dst_ip_mask = 1;
4824 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4828 switch (filter->src_ip_mask) {
4830 filter_info->src_ip_mask = 0;
4831 filter_info->src_ip = filter->src_ip;
4834 filter_info->src_ip_mask = 1;
4837 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4841 switch (filter->dst_port_mask) {
4843 filter_info->dst_port_mask = 0;
4844 filter_info->dst_port = filter->dst_port;
4847 filter_info->dst_port_mask = 1;
4850 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4854 switch (filter->src_port_mask) {
4856 filter_info->src_port_mask = 0;
4857 filter_info->src_port = filter->src_port;
4860 filter_info->src_port_mask = 1;
4863 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4867 switch (filter->proto_mask) {
4869 filter_info->proto_mask = 0;
4870 filter_info->proto =
4871 convert_protocol_type(filter->proto);
4874 filter_info->proto_mask = 1;
4877 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4881 filter_info->priority = (uint8_t)filter->priority;
4886 * add or delete a ntuple filter
4889 * dev: Pointer to struct rte_eth_dev.
4890 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4891 * add: if true, add filter, if false, remove filter
4894 * - On success, zero.
4895 * - On failure, a negative value.
4898 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4899 struct rte_eth_ntuple_filter *ntuple_filter,
4902 struct ixgbe_filter_info *filter_info =
4903 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4904 struct ixgbe_5tuple_filter_info filter_5tuple;
4905 struct ixgbe_5tuple_filter *filter;
4908 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4909 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4913 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4914 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4918 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4920 if (filter != NULL && add) {
4921 PMD_DRV_LOG(ERR, "filter exists.");
4924 if (filter == NULL && !add) {
4925 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4930 filter = rte_zmalloc("ixgbe_5tuple_filter",
4931 sizeof(struct ixgbe_5tuple_filter), 0);
4934 (void)rte_memcpy(&filter->filter_info,
4936 sizeof(struct ixgbe_5tuple_filter_info));
4937 filter->queue = ntuple_filter->queue;
4938 ret = ixgbe_add_5tuple_filter(dev, filter);
4944 ixgbe_remove_5tuple_filter(dev, filter);
4950 * get a ntuple filter
4953 * dev: Pointer to struct rte_eth_dev.
4954 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4957 * - On success, zero.
4958 * - On failure, a negative value.
4961 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4962 struct rte_eth_ntuple_filter *ntuple_filter)
4964 struct ixgbe_filter_info *filter_info =
4965 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4966 struct ixgbe_5tuple_filter_info filter_5tuple;
4967 struct ixgbe_5tuple_filter *filter;
4970 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4971 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4975 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4976 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4980 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4982 if (filter == NULL) {
4983 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4986 ntuple_filter->queue = filter->queue;
4991 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4992 * @dev: pointer to rte_eth_dev structure
4993 * @filter_op:operation will be taken.
4994 * @arg: a pointer to specific structure corresponding to the filter_op
4997 * - On success, zero.
4998 * - On failure, a negative value.
5001 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5002 enum rte_filter_op filter_op,
5005 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5008 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5010 if (filter_op == RTE_ETH_FILTER_NOP)
5014 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5019 switch (filter_op) {
5020 case RTE_ETH_FILTER_ADD:
5021 ret = ixgbe_add_del_ntuple_filter(dev,
5022 (struct rte_eth_ntuple_filter *)arg,
5025 case RTE_ETH_FILTER_DELETE:
5026 ret = ixgbe_add_del_ntuple_filter(dev,
5027 (struct rte_eth_ntuple_filter *)arg,
5030 case RTE_ETH_FILTER_GET:
5031 ret = ixgbe_get_ntuple_filter(dev,
5032 (struct rte_eth_ntuple_filter *)arg);
5035 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5043 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5048 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5049 if (filter_info->ethertype_filters[i] == ethertype &&
5050 (filter_info->ethertype_mask & (1 << i)))
5057 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5062 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5063 if (!(filter_info->ethertype_mask & (1 << i))) {
5064 filter_info->ethertype_mask |= 1 << i;
5065 filter_info->ethertype_filters[i] = ethertype;
5073 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5076 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5078 filter_info->ethertype_mask &= ~(1 << idx);
5079 filter_info->ethertype_filters[idx] = 0;
5084 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5085 struct rte_eth_ethertype_filter *filter,
5088 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5089 struct ixgbe_filter_info *filter_info =
5090 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5095 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5098 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5099 filter->ether_type == ETHER_TYPE_IPv6) {
5100 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5101 " ethertype filter.", filter->ether_type);
5105 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5106 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5109 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5110 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5114 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5115 if (ret >= 0 && add) {
5116 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5117 filter->ether_type);
5120 if (ret < 0 && !add) {
5121 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5122 filter->ether_type);
5127 ret = ixgbe_ethertype_filter_insert(filter_info,
5128 filter->ether_type);
5130 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5133 etqf = IXGBE_ETQF_FILTER_EN;
5134 etqf |= (uint32_t)filter->ether_type;
5135 etqs |= (uint32_t)((filter->queue <<
5136 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5137 IXGBE_ETQS_RX_QUEUE);
5138 etqs |= IXGBE_ETQS_QUEUE_EN;
5140 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5144 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5145 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5146 IXGBE_WRITE_FLUSH(hw);
5152 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5153 struct rte_eth_ethertype_filter *filter)
5155 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5156 struct ixgbe_filter_info *filter_info =
5157 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5158 uint32_t etqf, etqs;
5161 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5163 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5164 filter->ether_type);
5168 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5169 if (etqf & IXGBE_ETQF_FILTER_EN) {
5170 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5171 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5173 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5174 IXGBE_ETQS_RX_QUEUE_SHIFT;
5181 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5182 * @dev: pointer to rte_eth_dev structure
5183 * @filter_op:operation will be taken.
5184 * @arg: a pointer to specific structure corresponding to the filter_op
5187 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5188 enum rte_filter_op filter_op,
5191 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5194 MAC_TYPE_FILTER_SUP(hw->mac.type);
5196 if (filter_op == RTE_ETH_FILTER_NOP)
5200 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5205 switch (filter_op) {
5206 case RTE_ETH_FILTER_ADD:
5207 ret = ixgbe_add_del_ethertype_filter(dev,
5208 (struct rte_eth_ethertype_filter *)arg,
5211 case RTE_ETH_FILTER_DELETE:
5212 ret = ixgbe_add_del_ethertype_filter(dev,
5213 (struct rte_eth_ethertype_filter *)arg,
5216 case RTE_ETH_FILTER_GET:
5217 ret = ixgbe_get_ethertype_filter(dev,
5218 (struct rte_eth_ethertype_filter *)arg);
5221 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5229 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5230 enum rte_filter_type filter_type,
5231 enum rte_filter_op filter_op,
5236 switch (filter_type) {
5237 case RTE_ETH_FILTER_NTUPLE:
5238 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5240 case RTE_ETH_FILTER_ETHERTYPE:
5241 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5243 case RTE_ETH_FILTER_SYN:
5244 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5246 case RTE_ETH_FILTER_FDIR:
5247 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5250 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5259 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5260 u8 **mc_addr_ptr, u32 *vmdq)
5265 mc_addr = *mc_addr_ptr;
5266 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5271 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5272 struct ether_addr *mc_addr_set,
5273 uint32_t nb_mc_addr)
5275 struct ixgbe_hw *hw;
5278 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5279 mc_addr_list = (u8 *)mc_addr_set;
5280 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5281 ixgbe_dev_addr_list_itr, TRUE);
5285 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5287 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5291 /* Enable system time for platforms where it isn't on by default. */
5292 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5293 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5294 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5296 /* Start incrementing the register used to timestamp PTP packets. */
5297 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5299 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5300 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5302 IXGBE_ETQF_FILTER_EN |
5305 /* Enable timestamping of received PTP packets. */
5306 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5307 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5308 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5310 /* Enable timestamping of transmitted PTP packets. */
5311 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5312 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5313 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5319 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5321 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5324 /* Disable timestamping of transmitted PTP packets. */
5325 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5326 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5327 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5329 /* Disable timestamping of received PTP packets. */
5330 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5331 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5332 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5334 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5335 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5337 /* Stop incrementating the System Time registers. */
5338 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5344 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5345 struct timespec *timestamp,
5346 uint32_t flags __rte_unused)
5348 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5349 uint32_t tsync_rxctl;
5353 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5354 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5357 rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5358 rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5360 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5361 timestamp->tv_nsec = 0;
5367 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5368 struct timespec *timestamp)
5370 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5371 uint32_t tsync_txctl;
5375 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5376 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5379 tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5380 tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5382 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5383 timestamp->tv_nsec = 0;
5389 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5391 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5394 const struct reg_info *reg_group;
5395 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5396 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5398 while ((reg_group = reg_set[g_ind++]))
5399 count += ixgbe_regs_group_count(reg_group);
5405 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5409 const struct reg_info *reg_group;
5411 while ((reg_group = ixgbevf_regs[g_ind++]))
5412 count += ixgbe_regs_group_count(reg_group);
5418 ixgbe_get_regs(struct rte_eth_dev *dev,
5419 struct rte_dev_reg_info *regs)
5421 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5422 uint32_t *data = regs->data;
5425 const struct reg_info *reg_group;
5426 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5427 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5429 /* Support only full register dump */
5430 if ((regs->length == 0) ||
5431 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5432 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5434 while ((reg_group = reg_set[g_ind++]))
5435 count += ixgbe_read_regs_group(dev, &data[count],
5444 ixgbevf_get_regs(struct rte_eth_dev *dev,
5445 struct rte_dev_reg_info *regs)
5447 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5448 uint32_t *data = regs->data;
5451 const struct reg_info *reg_group;
5453 /* Support only full register dump */
5454 if ((regs->length == 0) ||
5455 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5456 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5458 while ((reg_group = ixgbevf_regs[g_ind++]))
5459 count += ixgbe_read_regs_group(dev, &data[count],
5468 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5470 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5472 /* Return unit is byte count */
5473 return hw->eeprom.word_size * 2;
5477 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5478 struct rte_dev_eeprom_info *in_eeprom)
5480 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5481 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5482 uint16_t *data = in_eeprom->data;
5485 first = in_eeprom->offset >> 1;
5486 length = in_eeprom->length >> 1;
5487 if ((first >= hw->eeprom.word_size) ||
5488 ((first + length) >= hw->eeprom.word_size))
5491 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5493 return eeprom->ops.read_buffer(hw, first, length, data);
5497 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5498 struct rte_dev_eeprom_info *in_eeprom)
5500 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5501 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5502 uint16_t *data = in_eeprom->data;
5505 first = in_eeprom->offset >> 1;
5506 length = in_eeprom->length >> 1;
5507 if ((first >= hw->eeprom.word_size) ||
5508 ((first + length) >= hw->eeprom.word_size))
5511 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5513 return eeprom->ops.write_buffer(hw, first, length, data);
5516 static struct rte_driver rte_ixgbe_driver = {
5518 .init = rte_ixgbe_pmd_init,
5521 static struct rte_driver rte_ixgbevf_driver = {
5523 .init = rte_ixgbevf_pmd_init,
5526 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5527 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);