4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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14 * notice, this list of conditions and the following disclaimer in
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define NSEC_PER_SEC 1000000000L
130 #define IXGBE_INCVAL_10GB 0x66666666
131 #define IXGBE_INCVAL_1GB 0x40000000
132 #define IXGBE_INCVAL_100 0x50000000
133 #define IXGBE_INCVAL_SHIFT_10GB 28
134 #define IXGBE_INCVAL_SHIFT_1GB 24
135 #define IXGBE_INCVAL_SHIFT_100 21
136 #define IXGBE_INCVAL_SHIFT_82599 7
137 #define IXGBE_INCPER_SHIFT_82599 24
139 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
141 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
143 #define DEFAULT_ETAG_ETYPE 0x893f
144 #define IXGBE_ETAG_ETYPE 0x00005084
145 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
146 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
147 #define IXGBE_RAH_ADTYPE 0x40000000
148 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
149 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
152 #define IXGBE_QDE_STRIP_TAG 0x00000004
153 #define IXGBE_VTEICR_MASK 0x07
155 enum ixgbevf_xcast_modes {
156 IXGBEVF_XCAST_MODE_NONE = 0,
157 IXGBEVF_XCAST_MODE_MULTI,
158 IXGBEVF_XCAST_MODE_ALLMULTI,
161 #define IXGBE_EXVET_VET_EXT_SHIFT 16
162 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
164 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
165 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
167 static int ixgbe_dev_start(struct rte_eth_dev *dev);
168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
169 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
172 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
173 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
174 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
176 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
177 int wait_to_complete);
178 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
179 struct rte_eth_stats *stats);
180 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
181 struct rte_eth_xstat *xstats, unsigned n);
182 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
183 struct rte_eth_xstat *xstats, unsigned n);
184 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
185 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
186 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
187 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
188 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
189 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
190 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
194 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
195 struct rte_eth_dev_info *dev_info);
196 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
197 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
198 struct rte_eth_dev_info *dev_info);
199 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
201 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
202 uint16_t vlan_id, int on);
203 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
204 enum rte_vlan_type vlan_type,
206 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
207 uint16_t queue, bool on);
208 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
210 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
211 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
212 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
213 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
214 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
216 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
217 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
218 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
219 struct rte_eth_fc_conf *fc_conf);
220 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
221 struct rte_eth_fc_conf *fc_conf);
222 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
223 struct rte_eth_pfc_conf *pfc_conf);
224 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
225 struct rte_eth_rss_reta_entry64 *reta_conf,
227 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
228 struct rte_eth_rss_reta_entry64 *reta_conf,
230 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
231 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
232 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
233 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
234 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
235 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
237 static void ixgbe_dev_interrupt_delayed_handler(void *param);
238 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
239 uint32_t index, uint32_t pool);
240 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
241 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
242 struct ether_addr *mac_addr);
243 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
245 /* For Virtual Function support */
246 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
247 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
248 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
249 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
250 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
251 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
252 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
253 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
254 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
255 struct rte_eth_stats *stats);
256 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
257 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
258 uint16_t vlan_id, int on);
259 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
260 uint16_t queue, int on);
261 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
262 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
263 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
265 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
267 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
268 uint8_t queue, uint8_t msix_vector);
269 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
270 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
271 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
273 /* For Eth VMDQ APIs support */
274 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
275 ether_addr * mac_addr, uint8_t on);
276 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
277 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
278 uint16_t rx_mask, uint8_t on);
279 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
280 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
281 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
282 uint64_t pool_mask, uint8_t vlan_on);
283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
284 struct rte_eth_mirror_conf *mirror_conf,
285 uint8_t rule_id, uint8_t on);
286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
293 uint8_t queue, uint8_t msix_vector);
294 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
296 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
297 uint16_t queue_idx, uint16_t tx_rate);
298 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
299 uint16_t tx_rate, uint64_t q_msk);
301 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
302 struct ether_addr *mac_addr,
303 uint32_t index, uint32_t pool);
304 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
305 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
306 struct ether_addr *mac_addr);
307 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
308 struct rte_eth_syn_filter *filter,
310 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
311 struct rte_eth_syn_filter *filter);
312 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
313 enum rte_filter_op filter_op,
315 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
316 struct ixgbe_5tuple_filter *filter);
317 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
318 struct ixgbe_5tuple_filter *filter);
319 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
320 struct rte_eth_ntuple_filter *filter,
322 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
323 enum rte_filter_op filter_op,
325 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
326 struct rte_eth_ntuple_filter *filter);
327 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
328 struct rte_eth_ethertype_filter *filter,
330 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
331 enum rte_filter_op filter_op,
333 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
334 struct rte_eth_ethertype_filter *filter);
335 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
336 enum rte_filter_type filter_type,
337 enum rte_filter_op filter_op,
339 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
341 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
342 struct ether_addr *mc_addr_set,
343 uint32_t nb_mc_addr);
344 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
345 struct rte_eth_dcb_info *dcb_info);
347 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
348 static int ixgbe_get_regs(struct rte_eth_dev *dev,
349 struct rte_dev_reg_info *regs);
350 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
351 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
352 struct rte_dev_eeprom_info *eeprom);
353 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
354 struct rte_dev_eeprom_info *eeprom);
356 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
357 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
358 struct rte_dev_reg_info *regs);
360 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
361 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
362 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
363 struct timespec *timestamp,
365 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
366 struct timespec *timestamp);
367 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
368 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
369 struct timespec *timestamp);
370 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
371 const struct timespec *timestamp);
372 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
375 static int ixgbe_dev_l2_tunnel_eth_type_conf
376 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
377 static int ixgbe_dev_l2_tunnel_offload_set
378 (struct rte_eth_dev *dev,
379 struct rte_eth_l2_tunnel_conf *l2_tunnel,
382 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
383 enum rte_filter_op filter_op,
386 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
387 struct rte_eth_udp_tunnel *udp_tunnel);
388 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
389 struct rte_eth_udp_tunnel *udp_tunnel);
392 * Define VF Stats MACRO for Non "cleared on read" register
394 #define UPDATE_VF_STAT(reg, last, cur) \
396 uint32_t latest = IXGBE_READ_REG(hw, reg); \
397 cur += (latest - last) & UINT_MAX; \
401 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
403 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
404 u64 new_msb = IXGBE_READ_REG(hw, msb); \
405 u64 latest = ((new_msb << 32) | new_lsb); \
406 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
410 #define IXGBE_SET_HWSTRIP(h, q) do {\
411 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
412 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
413 (h)->bitmap[idx] |= 1 << bit;\
416 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
417 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
418 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
419 (h)->bitmap[idx] &= ~(1 << bit);\
422 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
423 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
424 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
425 (r) = (h)->bitmap[idx] >> bit & 1;\
429 * The set of PCI devices this driver supports
431 static const struct rte_pci_id pci_id_ixgbe_map[] = {
433 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
434 #include "rte_pci_dev_ids.h"
436 { .vendor_id = 0, /* sentinel */ },
441 * The set of PCI devices this driver supports (for 82599 VF)
443 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
445 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
446 #include "rte_pci_dev_ids.h"
447 { .vendor_id = 0, /* sentinel */ },
451 static const struct rte_eth_desc_lim rx_desc_lim = {
452 .nb_max = IXGBE_MAX_RING_DESC,
453 .nb_min = IXGBE_MIN_RING_DESC,
454 .nb_align = IXGBE_RXD_ALIGN,
457 static const struct rte_eth_desc_lim tx_desc_lim = {
458 .nb_max = IXGBE_MAX_RING_DESC,
459 .nb_min = IXGBE_MIN_RING_DESC,
460 .nb_align = IXGBE_TXD_ALIGN,
463 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
464 .dev_configure = ixgbe_dev_configure,
465 .dev_start = ixgbe_dev_start,
466 .dev_stop = ixgbe_dev_stop,
467 .dev_set_link_up = ixgbe_dev_set_link_up,
468 .dev_set_link_down = ixgbe_dev_set_link_down,
469 .dev_close = ixgbe_dev_close,
470 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
471 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
472 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
473 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
474 .link_update = ixgbe_dev_link_update,
475 .stats_get = ixgbe_dev_stats_get,
476 .xstats_get = ixgbe_dev_xstats_get,
477 .stats_reset = ixgbe_dev_stats_reset,
478 .xstats_reset = ixgbe_dev_xstats_reset,
479 .xstats_get_names = ixgbe_dev_xstats_get_names,
480 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
481 .dev_infos_get = ixgbe_dev_info_get,
482 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
483 .mtu_set = ixgbe_dev_mtu_set,
484 .vlan_filter_set = ixgbe_vlan_filter_set,
485 .vlan_tpid_set = ixgbe_vlan_tpid_set,
486 .vlan_offload_set = ixgbe_vlan_offload_set,
487 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
488 .rx_queue_start = ixgbe_dev_rx_queue_start,
489 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
490 .tx_queue_start = ixgbe_dev_tx_queue_start,
491 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
492 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
493 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
494 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
495 .rx_queue_release = ixgbe_dev_rx_queue_release,
496 .rx_queue_count = ixgbe_dev_rx_queue_count,
497 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
498 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
499 .tx_queue_release = ixgbe_dev_tx_queue_release,
500 .dev_led_on = ixgbe_dev_led_on,
501 .dev_led_off = ixgbe_dev_led_off,
502 .flow_ctrl_get = ixgbe_flow_ctrl_get,
503 .flow_ctrl_set = ixgbe_flow_ctrl_set,
504 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
505 .mac_addr_add = ixgbe_add_rar,
506 .mac_addr_remove = ixgbe_remove_rar,
507 .mac_addr_set = ixgbe_set_default_mac_addr,
508 .uc_hash_table_set = ixgbe_uc_hash_table_set,
509 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
510 .mirror_rule_set = ixgbe_mirror_rule_set,
511 .mirror_rule_reset = ixgbe_mirror_rule_reset,
512 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
513 .set_vf_rx = ixgbe_set_pool_rx,
514 .set_vf_tx = ixgbe_set_pool_tx,
515 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
516 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
517 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
518 .reta_update = ixgbe_dev_rss_reta_update,
519 .reta_query = ixgbe_dev_rss_reta_query,
520 #ifdef RTE_NIC_BYPASS
521 .bypass_init = ixgbe_bypass_init,
522 .bypass_state_set = ixgbe_bypass_state_store,
523 .bypass_state_show = ixgbe_bypass_state_show,
524 .bypass_event_set = ixgbe_bypass_event_store,
525 .bypass_event_show = ixgbe_bypass_event_show,
526 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
527 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
528 .bypass_ver_show = ixgbe_bypass_ver_show,
529 .bypass_wd_reset = ixgbe_bypass_wd_reset,
530 #endif /* RTE_NIC_BYPASS */
531 .rss_hash_update = ixgbe_dev_rss_hash_update,
532 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
533 .filter_ctrl = ixgbe_dev_filter_ctrl,
534 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
535 .rxq_info_get = ixgbe_rxq_info_get,
536 .txq_info_get = ixgbe_txq_info_get,
537 .timesync_enable = ixgbe_timesync_enable,
538 .timesync_disable = ixgbe_timesync_disable,
539 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
540 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
541 .get_reg_length = ixgbe_get_reg_length,
542 .get_reg = ixgbe_get_regs,
543 .get_eeprom_length = ixgbe_get_eeprom_length,
544 .get_eeprom = ixgbe_get_eeprom,
545 .set_eeprom = ixgbe_set_eeprom,
546 .get_dcb_info = ixgbe_dev_get_dcb_info,
547 .timesync_adjust_time = ixgbe_timesync_adjust_time,
548 .timesync_read_time = ixgbe_timesync_read_time,
549 .timesync_write_time = ixgbe_timesync_write_time,
550 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
551 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
552 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
553 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
557 * dev_ops for virtual function, bare necessities for basic vf
558 * operation have been implemented
560 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
561 .dev_configure = ixgbevf_dev_configure,
562 .dev_start = ixgbevf_dev_start,
563 .dev_stop = ixgbevf_dev_stop,
564 .link_update = ixgbe_dev_link_update,
565 .stats_get = ixgbevf_dev_stats_get,
566 .xstats_get = ixgbevf_dev_xstats_get,
567 .stats_reset = ixgbevf_dev_stats_reset,
568 .xstats_reset = ixgbevf_dev_stats_reset,
569 .xstats_get_names = ixgbevf_dev_xstats_get_names,
570 .dev_close = ixgbevf_dev_close,
571 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
572 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
573 .dev_infos_get = ixgbevf_dev_info_get,
574 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
575 .mtu_set = ixgbevf_dev_set_mtu,
576 .vlan_filter_set = ixgbevf_vlan_filter_set,
577 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
578 .vlan_offload_set = ixgbevf_vlan_offload_set,
579 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
580 .rx_queue_release = ixgbe_dev_rx_queue_release,
581 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
582 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
583 .tx_queue_release = ixgbe_dev_tx_queue_release,
584 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
585 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
586 .mac_addr_add = ixgbevf_add_mac_addr,
587 .mac_addr_remove = ixgbevf_remove_mac_addr,
588 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
589 .rxq_info_get = ixgbe_rxq_info_get,
590 .txq_info_get = ixgbe_txq_info_get,
591 .mac_addr_set = ixgbevf_set_default_mac_addr,
592 .get_reg_length = ixgbevf_get_reg_length,
593 .get_reg = ixgbevf_get_regs,
594 .reta_update = ixgbe_dev_rss_reta_update,
595 .reta_query = ixgbe_dev_rss_reta_query,
596 .rss_hash_update = ixgbe_dev_rss_hash_update,
597 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
600 /* store statistics names and its offset in stats structure */
601 struct rte_ixgbe_xstats_name_off {
602 char name[RTE_ETH_XSTATS_NAME_SIZE];
606 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
607 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
608 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
609 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
610 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
611 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
612 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
613 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
614 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
615 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
616 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
617 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
618 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
619 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
620 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
621 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
623 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
625 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
626 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
627 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
628 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
629 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
630 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
631 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
632 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
633 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
634 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
635 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
636 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
637 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
638 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
639 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
640 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
641 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
643 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
645 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
646 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
647 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
648 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
650 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
652 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
654 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
656 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
658 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
660 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
663 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
664 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
665 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
667 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
668 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
669 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
670 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
671 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
673 {"rx_fcoe_no_direct_data_placement_ext_buff",
674 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
676 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
678 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
680 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
682 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
684 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
687 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
688 sizeof(rte_ixgbe_stats_strings[0]))
690 /* Per-queue statistics */
691 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
692 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
693 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
694 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
695 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
698 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
699 sizeof(rte_ixgbe_rxq_strings[0]))
700 #define IXGBE_NB_RXQ_PRIO_VALUES 8
702 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
703 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
704 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
705 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
709 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
710 sizeof(rte_ixgbe_txq_strings[0]))
711 #define IXGBE_NB_TXQ_PRIO_VALUES 8
713 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
714 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
717 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
718 sizeof(rte_ixgbevf_stats_strings[0]))
721 * Atomically reads the link status information from global
722 * structure rte_eth_dev.
725 * - Pointer to the structure rte_eth_dev to read from.
726 * - Pointer to the buffer to be saved with the link status.
729 * - On success, zero.
730 * - On failure, negative value.
733 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
734 struct rte_eth_link *link)
736 struct rte_eth_link *dst = link;
737 struct rte_eth_link *src = &(dev->data->dev_link);
739 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
740 *(uint64_t *)src) == 0)
747 * Atomically writes the link status information into global
748 * structure rte_eth_dev.
751 * - Pointer to the structure rte_eth_dev to read from.
752 * - Pointer to the buffer to be saved with the link status.
755 * - On success, zero.
756 * - On failure, negative value.
759 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
760 struct rte_eth_link *link)
762 struct rte_eth_link *dst = &(dev->data->dev_link);
763 struct rte_eth_link *src = link;
765 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
766 *(uint64_t *)src) == 0)
773 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
776 ixgbe_is_sfp(struct ixgbe_hw *hw)
778 switch (hw->phy.type) {
779 case ixgbe_phy_sfp_avago:
780 case ixgbe_phy_sfp_ftl:
781 case ixgbe_phy_sfp_intel:
782 case ixgbe_phy_sfp_unknown:
783 case ixgbe_phy_sfp_passive_tyco:
784 case ixgbe_phy_sfp_passive_unknown:
791 static inline int32_t
792 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
797 status = ixgbe_reset_hw(hw);
799 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
800 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
801 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
802 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
803 IXGBE_WRITE_FLUSH(hw);
809 ixgbe_enable_intr(struct rte_eth_dev *dev)
811 struct ixgbe_interrupt *intr =
812 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
813 struct ixgbe_hw *hw =
814 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
816 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
817 IXGBE_WRITE_FLUSH(hw);
821 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
824 ixgbe_disable_intr(struct ixgbe_hw *hw)
826 PMD_INIT_FUNC_TRACE();
828 if (hw->mac.type == ixgbe_mac_82598EB) {
829 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
831 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
832 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
833 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
835 IXGBE_WRITE_FLUSH(hw);
839 * This function resets queue statistics mapping registers.
840 * From Niantic datasheet, Initialization of Statistics section:
841 * "...if software requires the queue counters, the RQSMR and TQSM registers
842 * must be re-programmed following a device reset.
845 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
849 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
850 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
851 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
857 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
862 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
863 #define NB_QMAP_FIELDS_PER_QSM_REG 4
864 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
866 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
867 struct ixgbe_stat_mapping_registers *stat_mappings =
868 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
869 uint32_t qsmr_mask = 0;
870 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
874 if ((hw->mac.type != ixgbe_mac_82599EB) &&
875 (hw->mac.type != ixgbe_mac_X540) &&
876 (hw->mac.type != ixgbe_mac_X550) &&
877 (hw->mac.type != ixgbe_mac_X550EM_x) &&
878 (hw->mac.type != ixgbe_mac_X550EM_a))
881 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
882 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
885 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
886 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
887 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
890 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
892 /* Now clear any previous stat_idx set */
893 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
895 stat_mappings->tqsm[n] &= ~clearing_mask;
897 stat_mappings->rqsmr[n] &= ~clearing_mask;
899 q_map = (uint32_t)stat_idx;
900 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
901 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
903 stat_mappings->tqsm[n] |= qsmr_mask;
905 stat_mappings->rqsmr[n] |= qsmr_mask;
907 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
908 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
910 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
911 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
913 /* Now write the mapping in the appropriate register */
915 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
916 stat_mappings->rqsmr[n], n);
917 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
919 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
920 stat_mappings->tqsm[n], n);
921 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
927 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
929 struct ixgbe_stat_mapping_registers *stat_mappings =
930 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
931 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
934 /* write whatever was in stat mapping table to the NIC */
935 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
937 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
940 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
945 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
948 struct ixgbe_dcb_tc_config *tc;
949 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
951 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
952 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
953 for (i = 0; i < dcb_max_tc; i++) {
954 tc = &dcb_config->tc_config[i];
955 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
956 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
957 (uint8_t)(100/dcb_max_tc + (i & 1));
958 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
959 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
960 (uint8_t)(100/dcb_max_tc + (i & 1));
961 tc->pfc = ixgbe_dcb_pfc_disabled;
964 /* Initialize default user to priority mapping, UPx->TC0 */
965 tc = &dcb_config->tc_config[0];
966 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
967 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
968 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
969 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
970 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
972 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
973 dcb_config->pfc_mode_enable = false;
974 dcb_config->vt_mode = true;
975 dcb_config->round_robin_enable = false;
976 /* support all DCB capabilities in 82599 */
977 dcb_config->support.capabilities = 0xFF;
979 /*we only support 4 Tcs for X540, X550 */
980 if (hw->mac.type == ixgbe_mac_X540 ||
981 hw->mac.type == ixgbe_mac_X550 ||
982 hw->mac.type == ixgbe_mac_X550EM_x ||
983 hw->mac.type == ixgbe_mac_X550EM_a) {
984 dcb_config->num_tcs.pg_tcs = 4;
985 dcb_config->num_tcs.pfc_tcs = 4;
990 * Ensure that all locks are released before first NVM or PHY access
993 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
998 * Phy lock should not fail in this early stage. If this is the case,
999 * it is due to an improper exit of the application.
1000 * So force the release of the faulty lock. Release of common lock
1001 * is done automatically by swfw_sync function.
1003 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1004 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1005 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1007 ixgbe_release_swfw_semaphore(hw, mask);
1010 * These ones are more tricky since they are common to all ports; but
1011 * swfw_sync retries last long enough (1s) to be almost sure that if
1012 * lock can not be taken it is due to an improper lock of the
1015 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1016 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1017 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1019 ixgbe_release_swfw_semaphore(hw, mask);
1023 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1024 * It returns 0 on success.
1027 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1029 struct rte_pci_device *pci_dev;
1030 struct ixgbe_hw *hw =
1031 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1032 struct ixgbe_vfta *shadow_vfta =
1033 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1034 struct ixgbe_hwstrip *hwstrip =
1035 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1036 struct ixgbe_dcb_config *dcb_config =
1037 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1038 struct ixgbe_filter_info *filter_info =
1039 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1044 PMD_INIT_FUNC_TRACE();
1046 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1047 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1048 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1051 * For secondary processes, we don't initialise any further as primary
1052 * has already done this work. Only check we don't need a different
1053 * RX and TX function.
1055 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1056 struct ixgbe_tx_queue *txq;
1057 /* TX queue function in primary, set by last queue initialized
1058 * Tx queue may not initialized by primary process
1060 if (eth_dev->data->tx_queues) {
1061 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1062 ixgbe_set_tx_function(eth_dev, txq);
1064 /* Use default TX function if we get here */
1065 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1066 "Using default TX function.");
1069 ixgbe_set_rx_function(eth_dev);
1073 pci_dev = eth_dev->pci_dev;
1075 rte_eth_copy_pci_info(eth_dev, pci_dev);
1077 /* Vendor and Device ID need to be set before init of shared code */
1078 hw->device_id = pci_dev->id.device_id;
1079 hw->vendor_id = pci_dev->id.vendor_id;
1080 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1081 hw->allow_unsupported_sfp = 1;
1083 /* Initialize the shared code (base driver) */
1084 #ifdef RTE_NIC_BYPASS
1085 diag = ixgbe_bypass_init_shared_code(hw);
1087 diag = ixgbe_init_shared_code(hw);
1088 #endif /* RTE_NIC_BYPASS */
1090 if (diag != IXGBE_SUCCESS) {
1091 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1095 /* pick up the PCI bus settings for reporting later */
1096 ixgbe_get_bus_info(hw);
1098 /* Unlock any pending hardware semaphore */
1099 ixgbe_swfw_lock_reset(hw);
1101 /* Initialize DCB configuration*/
1102 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1103 ixgbe_dcb_init(hw, dcb_config);
1104 /* Get Hardware Flow Control setting */
1105 hw->fc.requested_mode = ixgbe_fc_full;
1106 hw->fc.current_mode = ixgbe_fc_full;
1107 hw->fc.pause_time = IXGBE_FC_PAUSE;
1108 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1109 hw->fc.low_water[i] = IXGBE_FC_LO;
1110 hw->fc.high_water[i] = IXGBE_FC_HI;
1112 hw->fc.send_xon = 1;
1114 /* Make sure we have a good EEPROM before we read from it */
1115 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1116 if (diag != IXGBE_SUCCESS) {
1117 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1121 #ifdef RTE_NIC_BYPASS
1122 diag = ixgbe_bypass_init_hw(hw);
1124 diag = ixgbe_init_hw(hw);
1125 #endif /* RTE_NIC_BYPASS */
1128 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1129 * is called too soon after the kernel driver unbinding/binding occurs.
1130 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1131 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1132 * also called. See ixgbe_identify_phy_82599(). The reason for the
1133 * failure is not known, and only occuts when virtualisation features
1134 * are disabled in the bios. A delay of 100ms was found to be enough by
1135 * trial-and-error, and is doubled to be safe.
1137 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1139 diag = ixgbe_init_hw(hw);
1142 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1143 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1144 "LOM. Please be aware there may be issues associated "
1145 "with your hardware.");
1146 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1147 "please contact your Intel or hardware representative "
1148 "who provided you with this hardware.");
1149 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1150 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1152 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1156 /* Reset the hw statistics */
1157 ixgbe_dev_stats_reset(eth_dev);
1159 /* disable interrupt */
1160 ixgbe_disable_intr(hw);
1162 /* reset mappings for queue statistics hw counters*/
1163 ixgbe_reset_qstat_mappings(hw);
1165 /* Allocate memory for storing MAC addresses */
1166 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167 hw->mac.num_rar_entries, 0);
1168 if (eth_dev->data->mac_addrs == NULL) {
1170 "Failed to allocate %u bytes needed to store "
1172 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1175 /* Copy the permanent MAC address */
1176 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1177 ð_dev->data->mac_addrs[0]);
1179 /* Allocate memory for storing hash filter MAC addresses */
1180 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1181 IXGBE_VMDQ_NUM_UC_MAC, 0);
1182 if (eth_dev->data->hash_mac_addrs == NULL) {
1184 "Failed to allocate %d bytes needed to store MAC addresses",
1185 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1189 /* initialize the vfta */
1190 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1192 /* initialize the hw strip bitmap*/
1193 memset(hwstrip, 0, sizeof(*hwstrip));
1195 /* initialize PF if max_vfs not zero */
1196 ixgbe_pf_host_init(eth_dev);
1198 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1199 /* let hardware know driver is loaded */
1200 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1201 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1202 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1203 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1204 IXGBE_WRITE_FLUSH(hw);
1206 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1207 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1208 (int) hw->mac.type, (int) hw->phy.type,
1209 (int) hw->phy.sfp_type);
1211 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1212 (int) hw->mac.type, (int) hw->phy.type);
1214 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1215 eth_dev->data->port_id, pci_dev->id.vendor_id,
1216 pci_dev->id.device_id);
1218 rte_intr_callback_register(&pci_dev->intr_handle,
1219 ixgbe_dev_interrupt_handler,
1222 /* enable uio/vfio intr/eventfd mapping */
1223 rte_intr_enable(&pci_dev->intr_handle);
1225 /* enable support intr */
1226 ixgbe_enable_intr(eth_dev);
1228 /* initialize 5tuple filter list */
1229 TAILQ_INIT(&filter_info->fivetuple_list);
1230 memset(filter_info->fivetuple_mask, 0,
1231 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1237 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1239 struct rte_pci_device *pci_dev;
1240 struct ixgbe_hw *hw;
1242 PMD_INIT_FUNC_TRACE();
1244 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1247 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1248 pci_dev = eth_dev->pci_dev;
1250 if (hw->adapter_stopped == 0)
1251 ixgbe_dev_close(eth_dev);
1253 eth_dev->dev_ops = NULL;
1254 eth_dev->rx_pkt_burst = NULL;
1255 eth_dev->tx_pkt_burst = NULL;
1257 /* Unlock any pending hardware semaphore */
1258 ixgbe_swfw_lock_reset(hw);
1260 /* disable uio intr before callback unregister */
1261 rte_intr_disable(&(pci_dev->intr_handle));
1262 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1263 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1265 /* uninitialize PF if max_vfs not zero */
1266 ixgbe_pf_host_uninit(eth_dev);
1268 rte_free(eth_dev->data->mac_addrs);
1269 eth_dev->data->mac_addrs = NULL;
1271 rte_free(eth_dev->data->hash_mac_addrs);
1272 eth_dev->data->hash_mac_addrs = NULL;
1278 * Negotiate mailbox API version with the PF.
1279 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1280 * Then we try to negotiate starting with the most recent one.
1281 * If all negotiation attempts fail, then we will proceed with
1282 * the default one (ixgbe_mbox_api_10).
1285 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1289 /* start with highest supported, proceed down */
1290 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1297 i != RTE_DIM(sup_ver) &&
1298 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1304 generate_random_mac_addr(struct ether_addr *mac_addr)
1308 /* Set Organizationally Unique Identifier (OUI) prefix. */
1309 mac_addr->addr_bytes[0] = 0x00;
1310 mac_addr->addr_bytes[1] = 0x09;
1311 mac_addr->addr_bytes[2] = 0xC0;
1312 /* Force indication of locally assigned MAC address. */
1313 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1314 /* Generate the last 3 bytes of the MAC address with a random number. */
1315 random = rte_rand();
1316 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1320 * Virtual Function device init
1323 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1327 struct rte_pci_device *pci_dev;
1328 struct ixgbe_hw *hw =
1329 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1330 struct ixgbe_vfta *shadow_vfta =
1331 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1332 struct ixgbe_hwstrip *hwstrip =
1333 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1334 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1336 PMD_INIT_FUNC_TRACE();
1338 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1339 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1340 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1342 /* for secondary processes, we don't initialise any further as primary
1343 * has already done this work. Only check we don't need a different
1346 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1347 struct ixgbe_tx_queue *txq;
1348 /* TX queue function in primary, set by last queue initialized
1349 * Tx queue may not initialized by primary process
1351 if (eth_dev->data->tx_queues) {
1352 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1353 ixgbe_set_tx_function(eth_dev, txq);
1355 /* Use default TX function if we get here */
1356 PMD_INIT_LOG(NOTICE,
1357 "No TX queues configured yet. Using default TX function.");
1360 ixgbe_set_rx_function(eth_dev);
1365 pci_dev = eth_dev->pci_dev;
1367 rte_eth_copy_pci_info(eth_dev, pci_dev);
1369 hw->device_id = pci_dev->id.device_id;
1370 hw->vendor_id = pci_dev->id.vendor_id;
1371 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1373 /* initialize the vfta */
1374 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1376 /* initialize the hw strip bitmap*/
1377 memset(hwstrip, 0, sizeof(*hwstrip));
1379 /* Initialize the shared code (base driver) */
1380 diag = ixgbe_init_shared_code(hw);
1381 if (diag != IXGBE_SUCCESS) {
1382 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1386 /* init_mailbox_params */
1387 hw->mbx.ops.init_params(hw);
1389 /* Reset the hw statistics */
1390 ixgbevf_dev_stats_reset(eth_dev);
1392 /* Disable the interrupts for VF */
1393 ixgbevf_intr_disable(hw);
1395 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1396 diag = hw->mac.ops.reset_hw(hw);
1399 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1400 * the underlying PF driver has not assigned a MAC address to the VF.
1401 * In this case, assign a random MAC address.
1403 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1404 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1408 /* negotiate mailbox API version to use with the PF. */
1409 ixgbevf_negotiate_api(hw);
1411 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1412 ixgbevf_get_queues(hw, &tcs, &tc);
1414 /* Allocate memory for storing MAC addresses */
1415 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1416 hw->mac.num_rar_entries, 0);
1417 if (eth_dev->data->mac_addrs == NULL) {
1419 "Failed to allocate %u bytes needed to store "
1421 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1425 /* Generate a random MAC address, if none was assigned by PF. */
1426 if (is_zero_ether_addr(perm_addr)) {
1427 generate_random_mac_addr(perm_addr);
1428 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1430 rte_free(eth_dev->data->mac_addrs);
1431 eth_dev->data->mac_addrs = NULL;
1434 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1435 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1436 "%02x:%02x:%02x:%02x:%02x:%02x",
1437 perm_addr->addr_bytes[0],
1438 perm_addr->addr_bytes[1],
1439 perm_addr->addr_bytes[2],
1440 perm_addr->addr_bytes[3],
1441 perm_addr->addr_bytes[4],
1442 perm_addr->addr_bytes[5]);
1445 /* Copy the permanent MAC address */
1446 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1448 /* reset the hardware with the new settings */
1449 diag = hw->mac.ops.start_hw(hw);
1455 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1459 rte_intr_callback_register(&pci_dev->intr_handle,
1460 ixgbevf_dev_interrupt_handler,
1462 rte_intr_enable(&pci_dev->intr_handle);
1463 ixgbevf_intr_enable(hw);
1465 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1466 eth_dev->data->port_id, pci_dev->id.vendor_id,
1467 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1472 /* Virtual Function device uninit */
1475 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1477 struct ixgbe_hw *hw;
1478 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1480 PMD_INIT_FUNC_TRACE();
1482 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1485 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1487 if (hw->adapter_stopped == 0)
1488 ixgbevf_dev_close(eth_dev);
1490 eth_dev->dev_ops = NULL;
1491 eth_dev->rx_pkt_burst = NULL;
1492 eth_dev->tx_pkt_burst = NULL;
1494 /* Disable the interrupts for VF */
1495 ixgbevf_intr_disable(hw);
1497 rte_free(eth_dev->data->mac_addrs);
1498 eth_dev->data->mac_addrs = NULL;
1500 rte_intr_disable(&pci_dev->intr_handle);
1501 rte_intr_callback_unregister(&pci_dev->intr_handle,
1502 ixgbevf_dev_interrupt_handler,
1508 static struct eth_driver rte_ixgbe_pmd = {
1510 .name = "rte_ixgbe_pmd",
1511 .id_table = pci_id_ixgbe_map,
1512 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1513 RTE_PCI_DRV_DETACHABLE,
1515 .eth_dev_init = eth_ixgbe_dev_init,
1516 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1517 .dev_private_size = sizeof(struct ixgbe_adapter),
1521 * virtual function driver struct
1523 static struct eth_driver rte_ixgbevf_pmd = {
1525 .name = "rte_ixgbevf_pmd",
1526 .id_table = pci_id_ixgbevf_map,
1527 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1529 .eth_dev_init = eth_ixgbevf_dev_init,
1530 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1531 .dev_private_size = sizeof(struct ixgbe_adapter),
1535 * Driver initialization routine.
1536 * Invoked once at EAL init time.
1537 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1540 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1542 PMD_INIT_FUNC_TRACE();
1544 rte_eth_driver_register(&rte_ixgbe_pmd);
1549 * VF Driver initialization routine.
1550 * Invoked one at EAL init time.
1551 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1554 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1556 PMD_INIT_FUNC_TRACE();
1558 rte_eth_driver_register(&rte_ixgbevf_pmd);
1563 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1565 struct ixgbe_hw *hw =
1566 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567 struct ixgbe_vfta *shadow_vfta =
1568 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1573 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1574 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1575 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1580 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1582 /* update local VFTA copy */
1583 shadow_vfta->vfta[vid_idx] = vfta;
1589 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1592 ixgbe_vlan_hw_strip_enable(dev, queue);
1594 ixgbe_vlan_hw_strip_disable(dev, queue);
1598 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1599 enum rte_vlan_type vlan_type,
1602 struct ixgbe_hw *hw =
1603 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1609 qinq &= IXGBE_DMATXCTL_GDV;
1611 switch (vlan_type) {
1612 case ETH_VLAN_TYPE_INNER:
1614 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1615 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1616 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1617 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1618 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1619 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1620 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1623 PMD_DRV_LOG(ERR, "Inner type is not supported"
1627 case ETH_VLAN_TYPE_OUTER:
1629 /* Only the high 16-bits is valid */
1630 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1631 IXGBE_EXVET_VET_EXT_SHIFT);
1633 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1634 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1635 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1636 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1637 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1638 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1639 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1645 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1653 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1655 struct ixgbe_hw *hw =
1656 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659 PMD_INIT_FUNC_TRACE();
1661 /* Filter Table Disable */
1662 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1663 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1665 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1669 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1671 struct ixgbe_hw *hw =
1672 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673 struct ixgbe_vfta *shadow_vfta =
1674 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1678 PMD_INIT_FUNC_TRACE();
1680 /* Filter Table Enable */
1681 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1682 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1683 vlnctrl |= IXGBE_VLNCTRL_VFE;
1685 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1687 /* write whatever is in local vfta copy */
1688 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1689 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1693 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1695 struct ixgbe_hwstrip *hwstrip =
1696 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1697 struct ixgbe_rx_queue *rxq;
1699 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1703 IXGBE_SET_HWSTRIP(hwstrip, queue);
1705 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1707 if (queue >= dev->data->nb_rx_queues)
1710 rxq = dev->data->rx_queues[queue];
1713 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1715 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1719 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1721 struct ixgbe_hw *hw =
1722 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1725 PMD_INIT_FUNC_TRACE();
1727 if (hw->mac.type == ixgbe_mac_82598EB) {
1728 /* No queue level support */
1729 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1733 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1734 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1735 ctrl &= ~IXGBE_RXDCTL_VME;
1736 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1738 /* record those setting for HW strip per queue */
1739 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1743 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1745 struct ixgbe_hw *hw =
1746 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1749 PMD_INIT_FUNC_TRACE();
1751 if (hw->mac.type == ixgbe_mac_82598EB) {
1752 /* No queue level supported */
1753 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1757 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1758 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1759 ctrl |= IXGBE_RXDCTL_VME;
1760 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1762 /* record those setting for HW strip per queue */
1763 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1767 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1769 struct ixgbe_hw *hw =
1770 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1774 PMD_INIT_FUNC_TRACE();
1776 if (hw->mac.type == ixgbe_mac_82598EB) {
1777 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1778 ctrl &= ~IXGBE_VLNCTRL_VME;
1779 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1781 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1782 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1783 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1784 ctrl &= ~IXGBE_RXDCTL_VME;
1785 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1787 /* record those setting for HW strip per queue */
1788 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1794 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1796 struct ixgbe_hw *hw =
1797 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1801 PMD_INIT_FUNC_TRACE();
1803 if (hw->mac.type == ixgbe_mac_82598EB) {
1804 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1805 ctrl |= IXGBE_VLNCTRL_VME;
1806 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1808 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1809 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1810 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1811 ctrl |= IXGBE_RXDCTL_VME;
1812 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1814 /* record those setting for HW strip per queue */
1815 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1821 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1823 struct ixgbe_hw *hw =
1824 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827 PMD_INIT_FUNC_TRACE();
1829 /* DMATXCTRL: Geric Double VLAN Disable */
1830 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1831 ctrl &= ~IXGBE_DMATXCTL_GDV;
1832 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1834 /* CTRL_EXT: Global Double VLAN Disable */
1835 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1836 ctrl &= ~IXGBE_EXTENDED_VLAN;
1837 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1842 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1844 struct ixgbe_hw *hw =
1845 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848 PMD_INIT_FUNC_TRACE();
1850 /* DMATXCTRL: Geric Double VLAN Enable */
1851 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1852 ctrl |= IXGBE_DMATXCTL_GDV;
1853 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1855 /* CTRL_EXT: Global Double VLAN Enable */
1856 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1857 ctrl |= IXGBE_EXTENDED_VLAN;
1858 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1860 /* Clear pooling mode of PFVTCTL. It's required by X550. */
1861 if (hw->mac.type == ixgbe_mac_X550 ||
1862 hw->mac.type == ixgbe_mac_X550EM_x ||
1863 hw->mac.type == ixgbe_mac_X550EM_a) {
1864 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1865 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1866 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1870 * VET EXT field in the EXVET register = 0x8100 by default
1871 * So no need to change. Same to VT field of DMATXCTL register
1876 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1878 if (mask & ETH_VLAN_STRIP_MASK) {
1879 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1880 ixgbe_vlan_hw_strip_enable_all(dev);
1882 ixgbe_vlan_hw_strip_disable_all(dev);
1885 if (mask & ETH_VLAN_FILTER_MASK) {
1886 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1887 ixgbe_vlan_hw_filter_enable(dev);
1889 ixgbe_vlan_hw_filter_disable(dev);
1892 if (mask & ETH_VLAN_EXTEND_MASK) {
1893 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1894 ixgbe_vlan_hw_extend_enable(dev);
1896 ixgbe_vlan_hw_extend_disable(dev);
1901 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1903 struct ixgbe_hw *hw =
1904 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1905 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1906 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1908 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1909 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1913 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1918 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1921 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1927 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1928 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1934 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1936 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1937 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1939 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1941 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1942 /* check multi-queue mode */
1943 switch (dev_conf->rxmode.mq_mode) {
1944 case ETH_MQ_RX_VMDQ_DCB:
1945 case ETH_MQ_RX_VMDQ_DCB_RSS:
1946 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1947 PMD_INIT_LOG(ERR, "SRIOV active,"
1948 " unsupported mq_mode rx %d.",
1949 dev_conf->rxmode.mq_mode);
1952 case ETH_MQ_RX_VMDQ_RSS:
1953 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1954 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1955 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1956 PMD_INIT_LOG(ERR, "SRIOV is active,"
1957 " invalid queue number"
1958 " for VMDQ RSS, allowed"
1959 " value are 1, 2 or 4.");
1963 case ETH_MQ_RX_VMDQ_ONLY:
1964 case ETH_MQ_RX_NONE:
1965 /* if nothing mq mode configure, use default scheme */
1966 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1967 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1968 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1970 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1971 /* SRIOV only works in VMDq enable mode */
1972 PMD_INIT_LOG(ERR, "SRIOV is active,"
1973 " wrong mq_mode rx %d.",
1974 dev_conf->rxmode.mq_mode);
1978 switch (dev_conf->txmode.mq_mode) {
1979 case ETH_MQ_TX_VMDQ_DCB:
1980 /* DCB VMDQ in SRIOV mode, not implement yet */
1981 PMD_INIT_LOG(ERR, "SRIOV is active,"
1982 " unsupported VMDQ mq_mode tx %d.",
1983 dev_conf->txmode.mq_mode);
1985 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1986 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1990 /* check valid queue number */
1991 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1992 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1993 PMD_INIT_LOG(ERR, "SRIOV is active,"
1994 " nb_rx_q=%d nb_tx_q=%d queue number"
1995 " must be less than or equal to %d.",
1997 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2001 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2002 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2006 /* check configuration for vmdb+dcb mode */
2007 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2008 const struct rte_eth_vmdq_dcb_conf *conf;
2010 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2011 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2012 IXGBE_VMDQ_DCB_NB_QUEUES);
2015 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2016 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2017 conf->nb_queue_pools == ETH_32_POOLS)) {
2018 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2019 " nb_queue_pools must be %d or %d.",
2020 ETH_16_POOLS, ETH_32_POOLS);
2024 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2025 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2027 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2028 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2029 IXGBE_VMDQ_DCB_NB_QUEUES);
2032 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2033 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2034 conf->nb_queue_pools == ETH_32_POOLS)) {
2035 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2036 " nb_queue_pools != %d and"
2037 " nb_queue_pools != %d.",
2038 ETH_16_POOLS, ETH_32_POOLS);
2043 /* For DCB mode check our configuration before we go further */
2044 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2045 const struct rte_eth_dcb_rx_conf *conf;
2047 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2048 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2049 IXGBE_DCB_NB_QUEUES);
2052 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2053 if (!(conf->nb_tcs == ETH_4_TCS ||
2054 conf->nb_tcs == ETH_8_TCS)) {
2055 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2056 " and nb_tcs != %d.",
2057 ETH_4_TCS, ETH_8_TCS);
2062 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2063 const struct rte_eth_dcb_tx_conf *conf;
2065 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2066 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2067 IXGBE_DCB_NB_QUEUES);
2070 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2071 if (!(conf->nb_tcs == ETH_4_TCS ||
2072 conf->nb_tcs == ETH_8_TCS)) {
2073 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2074 " and nb_tcs != %d.",
2075 ETH_4_TCS, ETH_8_TCS);
2081 * When DCB/VT is off, maximum number of queues changes,
2082 * except for 82598EB, which remains constant.
2084 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2085 hw->mac.type != ixgbe_mac_82598EB) {
2086 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2088 "Neither VT nor DCB are enabled, "
2090 IXGBE_NONE_MODE_TX_NB_QUEUES);
2099 ixgbe_dev_configure(struct rte_eth_dev *dev)
2101 struct ixgbe_interrupt *intr =
2102 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2103 struct ixgbe_adapter *adapter =
2104 (struct ixgbe_adapter *)dev->data->dev_private;
2107 PMD_INIT_FUNC_TRACE();
2108 /* multipe queue mode checking */
2109 ret = ixgbe_check_mq_mode(dev);
2111 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2116 /* set flag to update link status after init */
2117 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2120 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2121 * allocation or vector Rx preconditions we will reset it.
2123 adapter->rx_bulk_alloc_allowed = true;
2124 adapter->rx_vec_allowed = true;
2130 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2132 struct ixgbe_hw *hw =
2133 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134 struct ixgbe_interrupt *intr =
2135 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2138 /* only set up it on X550EM_X */
2139 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2140 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2141 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2142 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2143 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2144 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2149 * Configure device link speed and setup link.
2150 * It returns 0 on success.
2153 ixgbe_dev_start(struct rte_eth_dev *dev)
2155 struct ixgbe_hw *hw =
2156 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2157 struct ixgbe_vf_info *vfinfo =
2158 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2159 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2160 uint32_t intr_vector = 0;
2161 int err, link_up = 0, negotiate = 0;
2166 uint32_t *link_speeds;
2168 PMD_INIT_FUNC_TRACE();
2170 /* IXGBE devices don't support:
2171 * - half duplex (checked afterwards for valid speeds)
2172 * - fixed speed: TODO implement
2174 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2175 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2176 dev->data->port_id);
2180 /* disable uio/vfio intr/eventfd mapping */
2181 rte_intr_disable(intr_handle);
2184 hw->adapter_stopped = 0;
2185 ixgbe_stop_adapter(hw);
2187 /* reinitialize adapter
2188 * this calls reset and start
2190 status = ixgbe_pf_reset_hw(hw);
2193 hw->mac.ops.start_hw(hw);
2194 hw->mac.get_link_status = true;
2196 /* configure PF module if SRIOV enabled */
2197 ixgbe_pf_host_configure(dev);
2199 ixgbe_dev_phy_intr_setup(dev);
2201 /* check and configure queue intr-vector mapping */
2202 if ((rte_intr_cap_multiple(intr_handle) ||
2203 !RTE_ETH_DEV_SRIOV(dev).active) &&
2204 dev->data->dev_conf.intr_conf.rxq != 0) {
2205 intr_vector = dev->data->nb_rx_queues;
2206 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2207 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2208 IXGBE_MAX_INTR_QUEUE_NUM);
2211 if (rte_intr_efd_enable(intr_handle, intr_vector))
2215 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2216 intr_handle->intr_vec =
2217 rte_zmalloc("intr_vec",
2218 dev->data->nb_rx_queues * sizeof(int), 0);
2219 if (intr_handle->intr_vec == NULL) {
2220 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2221 " intr_vec\n", dev->data->nb_rx_queues);
2226 /* confiugre msix for sleep until rx interrupt */
2227 ixgbe_configure_msix(dev);
2229 /* initialize transmission unit */
2230 ixgbe_dev_tx_init(dev);
2232 /* This can fail when allocating mbufs for descriptor rings */
2233 err = ixgbe_dev_rx_init(dev);
2235 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2239 err = ixgbe_dev_rxtx_start(dev);
2241 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2245 /* Skip link setup if loopback mode is enabled for 82599. */
2246 if (hw->mac.type == ixgbe_mac_82599EB &&
2247 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2248 goto skip_link_setup;
2250 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2251 err = hw->mac.ops.setup_sfp(hw);
2256 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2257 /* Turn on the copper */
2258 ixgbe_set_phy_power(hw, true);
2260 /* Turn on the laser */
2261 ixgbe_enable_tx_laser(hw);
2264 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2267 dev->data->dev_link.link_status = link_up;
2269 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2273 link_speeds = &dev->data->dev_conf.link_speeds;
2274 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2275 ETH_LINK_SPEED_10G)) {
2276 PMD_INIT_LOG(ERR, "Invalid link setting");
2281 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2282 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2283 IXGBE_LINK_SPEED_82599_AUTONEG :
2284 IXGBE_LINK_SPEED_82598_AUTONEG;
2286 if (*link_speeds & ETH_LINK_SPEED_10G)
2287 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2288 if (*link_speeds & ETH_LINK_SPEED_1G)
2289 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2290 if (*link_speeds & ETH_LINK_SPEED_100M)
2291 speed |= IXGBE_LINK_SPEED_100_FULL;
2294 err = ixgbe_setup_link(hw, speed, link_up);
2300 if (rte_intr_allow_others(intr_handle)) {
2301 /* check if lsc interrupt is enabled */
2302 if (dev->data->dev_conf.intr_conf.lsc != 0)
2303 ixgbe_dev_lsc_interrupt_setup(dev);
2305 rte_intr_callback_unregister(intr_handle,
2306 ixgbe_dev_interrupt_handler,
2308 if (dev->data->dev_conf.intr_conf.lsc != 0)
2309 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2310 " no intr multiplex\n");
2313 /* check if rxq interrupt is enabled */
2314 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2315 rte_intr_dp_is_en(intr_handle))
2316 ixgbe_dev_rxq_interrupt_setup(dev);
2318 /* enable uio/vfio intr/eventfd mapping */
2319 rte_intr_enable(intr_handle);
2321 /* resume enabled intr since hw reset */
2322 ixgbe_enable_intr(dev);
2324 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2325 ETH_VLAN_EXTEND_MASK;
2326 ixgbe_vlan_offload_set(dev, mask);
2328 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2329 /* Enable vlan filtering for VMDq */
2330 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2333 /* Configure DCB hw */
2334 ixgbe_configure_dcb(dev);
2336 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2337 err = ixgbe_fdir_configure(dev);
2342 /* Restore vf rate limit */
2343 if (vfinfo != NULL) {
2344 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2345 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2346 if (vfinfo[vf].tx_rate[idx] != 0)
2347 ixgbe_set_vf_rate_limit(dev, vf,
2348 vfinfo[vf].tx_rate[idx],
2352 ixgbe_restore_statistics_mapping(dev);
2357 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2358 ixgbe_dev_clear_queues(dev);
2363 * Stop device: disable rx and tx functions to allow for reconfiguring.
2366 ixgbe_dev_stop(struct rte_eth_dev *dev)
2368 struct rte_eth_link link;
2369 struct ixgbe_hw *hw =
2370 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2371 struct ixgbe_vf_info *vfinfo =
2372 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2373 struct ixgbe_filter_info *filter_info =
2374 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2375 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2376 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2379 PMD_INIT_FUNC_TRACE();
2381 /* disable interrupts */
2382 ixgbe_disable_intr(hw);
2385 ixgbe_pf_reset_hw(hw);
2386 hw->adapter_stopped = 0;
2389 ixgbe_stop_adapter(hw);
2391 for (vf = 0; vfinfo != NULL &&
2392 vf < dev->pci_dev->max_vfs; vf++)
2393 vfinfo[vf].clear_to_send = false;
2395 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2396 /* Turn off the copper */
2397 ixgbe_set_phy_power(hw, false);
2399 /* Turn off the laser */
2400 ixgbe_disable_tx_laser(hw);
2403 ixgbe_dev_clear_queues(dev);
2405 /* Clear stored conf */
2406 dev->data->scattered_rx = 0;
2409 /* Clear recorded link status */
2410 memset(&link, 0, sizeof(link));
2411 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2413 /* Remove all ntuple filters of the device */
2414 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2415 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2416 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2417 TAILQ_REMOVE(&filter_info->fivetuple_list,
2421 memset(filter_info->fivetuple_mask, 0,
2422 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2424 if (!rte_intr_allow_others(intr_handle))
2425 /* resume to the default handler */
2426 rte_intr_callback_register(intr_handle,
2427 ixgbe_dev_interrupt_handler,
2430 /* Clean datapath event and queue/vec mapping */
2431 rte_intr_efd_disable(intr_handle);
2432 if (intr_handle->intr_vec != NULL) {
2433 rte_free(intr_handle->intr_vec);
2434 intr_handle->intr_vec = NULL;
2439 * Set device link up: enable tx.
2442 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2444 struct ixgbe_hw *hw =
2445 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2446 if (hw->mac.type == ixgbe_mac_82599EB) {
2447 #ifdef RTE_NIC_BYPASS
2448 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2449 /* Not suported in bypass mode */
2450 PMD_INIT_LOG(ERR, "Set link up is not supported "
2451 "by device id 0x%x", hw->device_id);
2457 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2458 /* Turn on the copper */
2459 ixgbe_set_phy_power(hw, true);
2461 /* Turn on the laser */
2462 ixgbe_enable_tx_laser(hw);
2469 * Set device link down: disable tx.
2472 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2474 struct ixgbe_hw *hw =
2475 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476 if (hw->mac.type == ixgbe_mac_82599EB) {
2477 #ifdef RTE_NIC_BYPASS
2478 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2479 /* Not suported in bypass mode */
2480 PMD_INIT_LOG(ERR, "Set link down is not supported "
2481 "by device id 0x%x", hw->device_id);
2487 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2488 /* Turn off the copper */
2489 ixgbe_set_phy_power(hw, false);
2491 /* Turn off the laser */
2492 ixgbe_disable_tx_laser(hw);
2499 * Reest and stop device.
2502 ixgbe_dev_close(struct rte_eth_dev *dev)
2504 struct ixgbe_hw *hw =
2505 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2507 PMD_INIT_FUNC_TRACE();
2509 ixgbe_pf_reset_hw(hw);
2511 ixgbe_dev_stop(dev);
2512 hw->adapter_stopped = 1;
2514 ixgbe_dev_free_queues(dev);
2516 ixgbe_disable_pcie_master(hw);
2518 /* reprogram the RAR[0] in case user changed it. */
2519 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2523 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2524 struct ixgbe_hw_stats *hw_stats,
2525 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2526 uint64_t *total_qprc, uint64_t *total_qprdc)
2528 uint32_t bprc, lxon, lxoff, total;
2529 uint32_t delta_gprc = 0;
2531 /* Workaround for RX byte count not including CRC bytes when CRC
2532 + * strip is enabled. CRC bytes are removed from counters when crc_strip
2535 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2536 IXGBE_HLREG0_RXCRCSTRP);
2538 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2539 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2540 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2541 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2543 for (i = 0; i < 8; i++) {
2544 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2546 /* global total per queue */
2547 hw_stats->mpc[i] += mp;
2548 /* Running comprehensive total for stats display */
2549 *total_missed_rx += hw_stats->mpc[i];
2550 if (hw->mac.type == ixgbe_mac_82598EB) {
2551 hw_stats->rnbc[i] +=
2552 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2553 hw_stats->pxonrxc[i] +=
2554 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2555 hw_stats->pxoffrxc[i] +=
2556 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2558 hw_stats->pxonrxc[i] +=
2559 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2560 hw_stats->pxoffrxc[i] +=
2561 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2562 hw_stats->pxon2offc[i] +=
2563 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2565 hw_stats->pxontxc[i] +=
2566 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2567 hw_stats->pxofftxc[i] +=
2568 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2570 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2571 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2572 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2573 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2575 delta_gprc += delta_qprc;
2577 hw_stats->qprc[i] += delta_qprc;
2578 hw_stats->qptc[i] += delta_qptc;
2580 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2581 hw_stats->qbrc[i] +=
2582 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2584 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2586 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2587 hw_stats->qbtc[i] +=
2588 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2590 hw_stats->qprdc[i] += delta_qprdc;
2591 *total_qprdc += hw_stats->qprdc[i];
2593 *total_qprc += hw_stats->qprc[i];
2594 *total_qbrc += hw_stats->qbrc[i];
2596 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2597 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2598 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2601 * An errata states that gprc actually counts good + missed packets:
2602 * Workaround to set gprc to summated queue packet receives
2604 hw_stats->gprc = *total_qprc;
2606 if (hw->mac.type != ixgbe_mac_82598EB) {
2607 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2608 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2609 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2610 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2611 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2612 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2613 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2614 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2616 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2617 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2618 /* 82598 only has a counter in the high register */
2619 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2620 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2621 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2623 uint64_t old_tpr = hw_stats->tpr;
2625 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2626 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2629 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2631 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2632 hw_stats->gptc += delta_gptc;
2633 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2634 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2637 * Workaround: mprc hardware is incorrectly counting
2638 * broadcasts, so for now we subtract those.
2640 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2641 hw_stats->bprc += bprc;
2642 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2643 if (hw->mac.type == ixgbe_mac_82598EB)
2644 hw_stats->mprc -= bprc;
2646 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2647 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2648 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2649 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2650 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2651 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2653 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2654 hw_stats->lxontxc += lxon;
2655 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2656 hw_stats->lxofftxc += lxoff;
2657 total = lxon + lxoff;
2659 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2660 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2661 hw_stats->gptc -= total;
2662 hw_stats->mptc -= total;
2663 hw_stats->ptc64 -= total;
2664 hw_stats->gotc -= total * ETHER_MIN_LEN;
2666 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2667 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2668 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2669 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2670 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2671 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2672 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2673 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2674 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2675 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2676 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2677 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2678 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2679 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2680 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2681 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2682 /* Only read FCOE on 82599 */
2683 if (hw->mac.type != ixgbe_mac_82598EB) {
2684 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2685 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2686 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2687 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2688 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2691 /* Flow Director Stats registers */
2692 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2693 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2697 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2700 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2702 struct ixgbe_hw *hw =
2703 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704 struct ixgbe_hw_stats *hw_stats =
2705 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2706 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2709 total_missed_rx = 0;
2714 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2715 &total_qprc, &total_qprdc);
2720 /* Fill out the rte_eth_stats statistics structure */
2721 stats->ipackets = total_qprc;
2722 stats->ibytes = total_qbrc;
2723 stats->opackets = hw_stats->gptc;
2724 stats->obytes = hw_stats->gotc;
2726 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2727 stats->q_ipackets[i] = hw_stats->qprc[i];
2728 stats->q_opackets[i] = hw_stats->qptc[i];
2729 stats->q_ibytes[i] = hw_stats->qbrc[i];
2730 stats->q_obytes[i] = hw_stats->qbtc[i];
2731 stats->q_errors[i] = hw_stats->qprdc[i];
2735 stats->imissed = total_missed_rx;
2736 stats->ierrors = hw_stats->crcerrs +
2752 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2754 struct ixgbe_hw_stats *stats =
2755 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2757 /* HW registers are cleared on read */
2758 ixgbe_dev_stats_get(dev, NULL);
2760 /* Reset software totals */
2761 memset(stats, 0, sizeof(*stats));
2764 /* This function calculates the number of xstats based on the current config */
2766 ixgbe_xstats_calc_num(void) {
2767 return IXGBE_NB_HW_STATS +
2768 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2769 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2772 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2773 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2775 const unsigned cnt_stats = ixgbe_xstats_calc_num();
2776 unsigned stat, i, count;
2778 if (xstats_names != NULL) {
2781 /* Note: limit >= cnt_stats checked upstream
2782 * in rte_eth_xstats_names()
2785 /* Extended stats from ixgbe_hw_stats */
2786 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2787 xstats_names[count].id = count;
2788 snprintf(xstats_names[count].name,
2789 sizeof(xstats_names[count].name),
2791 rte_ixgbe_stats_strings[i].name);
2795 /* RX Priority Stats */
2796 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2797 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2798 xstats_names[count].id = count;
2799 snprintf(xstats_names[count].name,
2800 sizeof(xstats_names[count].name),
2801 "rx_priority%u_%s", i,
2802 rte_ixgbe_rxq_strings[stat].name);
2807 /* TX Priority Stats */
2808 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2809 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2810 xstats_names[count].id = count;
2811 snprintf(xstats_names[count].name,
2812 sizeof(xstats_names[count].name),
2813 "tx_priority%u_%s", i,
2814 rte_ixgbe_txq_strings[stat].name);
2822 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2823 struct rte_eth_xstat_name *xstats_names, unsigned limit)
2827 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2830 if (xstats_names != NULL)
2831 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2832 snprintf(xstats_names[i].name,
2833 sizeof(xstats_names[i].name),
2834 "%s", rte_ixgbevf_stats_strings[i].name);
2835 return IXGBEVF_NB_XSTATS;
2839 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2842 struct ixgbe_hw *hw =
2843 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844 struct ixgbe_hw_stats *hw_stats =
2845 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2846 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2847 unsigned i, stat, count = 0;
2849 count = ixgbe_xstats_calc_num();
2854 total_missed_rx = 0;
2859 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2860 &total_qprc, &total_qprdc);
2862 /* If this is a reset xstats is NULL, and we have cleared the
2863 * registers by reading them.
2868 /* Extended stats from ixgbe_hw_stats */
2870 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2871 xstats[count].id = count;
2872 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2873 rte_ixgbe_stats_strings[i].offset);
2877 /* RX Priority Stats */
2878 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2879 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2880 xstats[count].id = count;
2881 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2882 rte_ixgbe_rxq_strings[stat].offset +
2883 (sizeof(uint64_t) * i));
2888 /* TX Priority Stats */
2889 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2890 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2891 xstats[count].id = count;
2892 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2893 rte_ixgbe_txq_strings[stat].offset +
2894 (sizeof(uint64_t) * i));
2902 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2904 struct ixgbe_hw_stats *stats =
2905 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2907 unsigned count = ixgbe_xstats_calc_num();
2909 /* HW registers are cleared on read */
2910 ixgbe_dev_xstats_get(dev, NULL, count);
2912 /* Reset software totals */
2913 memset(stats, 0, sizeof(*stats));
2917 ixgbevf_update_stats(struct rte_eth_dev *dev)
2919 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2921 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2923 /* Good Rx packet, include VF loopback */
2924 UPDATE_VF_STAT(IXGBE_VFGPRC,
2925 hw_stats->last_vfgprc, hw_stats->vfgprc);
2927 /* Good Rx octets, include VF loopback */
2928 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2929 hw_stats->last_vfgorc, hw_stats->vfgorc);
2931 /* Good Tx packet, include VF loopback */
2932 UPDATE_VF_STAT(IXGBE_VFGPTC,
2933 hw_stats->last_vfgptc, hw_stats->vfgptc);
2935 /* Good Tx octets, include VF loopback */
2936 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2937 hw_stats->last_vfgotc, hw_stats->vfgotc);
2939 /* Rx Multicst Packet */
2940 UPDATE_VF_STAT(IXGBE_VFMPRC,
2941 hw_stats->last_vfmprc, hw_stats->vfmprc);
2945 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2948 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2949 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2952 if (n < IXGBEVF_NB_XSTATS)
2953 return IXGBEVF_NB_XSTATS;
2955 ixgbevf_update_stats(dev);
2960 /* Extended stats */
2961 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2963 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2964 rte_ixgbevf_stats_strings[i].offset);
2967 return IXGBEVF_NB_XSTATS;
2971 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2973 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2974 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2976 ixgbevf_update_stats(dev);
2981 stats->ipackets = hw_stats->vfgprc;
2982 stats->ibytes = hw_stats->vfgorc;
2983 stats->opackets = hw_stats->vfgptc;
2984 stats->obytes = hw_stats->vfgotc;
2988 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2990 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2991 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2993 /* Sync HW register to the last stats */
2994 ixgbevf_dev_stats_get(dev, NULL);
2996 /* reset HW current stats*/
2997 hw_stats->vfgprc = 0;
2998 hw_stats->vfgorc = 0;
2999 hw_stats->vfgptc = 0;
3000 hw_stats->vfgotc = 0;
3004 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3006 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3007 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3009 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3010 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3011 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3013 * When DCB/VT is off, maximum number of queues changes,
3014 * except for 82598EB, which remains constant.
3016 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3017 hw->mac.type != ixgbe_mac_82598EB)
3018 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3020 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3021 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3022 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3023 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3024 dev_info->max_vfs = dev->pci_dev->max_vfs;
3025 if (hw->mac.type == ixgbe_mac_82598EB)
3026 dev_info->max_vmdq_pools = ETH_16_POOLS;
3028 dev_info->max_vmdq_pools = ETH_64_POOLS;
3029 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3030 dev_info->rx_offload_capa =
3031 DEV_RX_OFFLOAD_VLAN_STRIP |
3032 DEV_RX_OFFLOAD_IPV4_CKSUM |
3033 DEV_RX_OFFLOAD_UDP_CKSUM |
3034 DEV_RX_OFFLOAD_TCP_CKSUM;
3037 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3040 if ((hw->mac.type == ixgbe_mac_82599EB ||
3041 hw->mac.type == ixgbe_mac_X540) &&
3042 !RTE_ETH_DEV_SRIOV(dev).active)
3043 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3045 if (hw->mac.type == ixgbe_mac_X550 ||
3046 hw->mac.type == ixgbe_mac_X550EM_x ||
3047 hw->mac.type == ixgbe_mac_X550EM_a)
3048 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3050 dev_info->tx_offload_capa =
3051 DEV_TX_OFFLOAD_VLAN_INSERT |
3052 DEV_TX_OFFLOAD_IPV4_CKSUM |
3053 DEV_TX_OFFLOAD_UDP_CKSUM |
3054 DEV_TX_OFFLOAD_TCP_CKSUM |
3055 DEV_TX_OFFLOAD_SCTP_CKSUM |
3056 DEV_TX_OFFLOAD_TCP_TSO;
3058 if (hw->mac.type == ixgbe_mac_X550 ||
3059 hw->mac.type == ixgbe_mac_X550EM_x ||
3060 hw->mac.type == ixgbe_mac_X550EM_a)
3061 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3063 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3065 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3066 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3067 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3069 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3073 dev_info->default_txconf = (struct rte_eth_txconf) {
3075 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3076 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3077 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3079 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3080 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3081 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3082 ETH_TXQ_FLAGS_NOOFFLOADS,
3085 dev_info->rx_desc_lim = rx_desc_lim;
3086 dev_info->tx_desc_lim = tx_desc_lim;
3088 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3089 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3090 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3092 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3093 if (hw->mac.type == ixgbe_mac_X540 ||
3094 hw->mac.type == ixgbe_mac_X540_vf ||
3095 hw->mac.type == ixgbe_mac_X550 ||
3096 hw->mac.type == ixgbe_mac_X550_vf) {
3097 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3101 static const uint32_t *
3102 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3104 static const uint32_t ptypes[] = {
3105 /* For non-vec functions,
3106 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3107 * for vec functions,
3108 * refers to _recv_raw_pkts_vec().
3112 RTE_PTYPE_L3_IPV4_EXT,
3114 RTE_PTYPE_L3_IPV6_EXT,
3118 RTE_PTYPE_TUNNEL_IP,
3119 RTE_PTYPE_INNER_L3_IPV6,
3120 RTE_PTYPE_INNER_L3_IPV6_EXT,
3121 RTE_PTYPE_INNER_L4_TCP,
3122 RTE_PTYPE_INNER_L4_UDP,
3126 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3127 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3128 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3129 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3135 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3136 struct rte_eth_dev_info *dev_info)
3138 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3140 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3141 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3142 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3143 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3144 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3145 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3146 dev_info->max_vfs = dev->pci_dev->max_vfs;
3147 if (hw->mac.type == ixgbe_mac_82598EB)
3148 dev_info->max_vmdq_pools = ETH_16_POOLS;
3150 dev_info->max_vmdq_pools = ETH_64_POOLS;
3151 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3152 DEV_RX_OFFLOAD_IPV4_CKSUM |
3153 DEV_RX_OFFLOAD_UDP_CKSUM |
3154 DEV_RX_OFFLOAD_TCP_CKSUM;
3155 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3156 DEV_TX_OFFLOAD_IPV4_CKSUM |
3157 DEV_TX_OFFLOAD_UDP_CKSUM |
3158 DEV_TX_OFFLOAD_TCP_CKSUM |
3159 DEV_TX_OFFLOAD_SCTP_CKSUM |
3160 DEV_TX_OFFLOAD_TCP_TSO;
3162 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3164 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3165 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3166 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3168 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3172 dev_info->default_txconf = (struct rte_eth_txconf) {
3174 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3175 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3176 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3178 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3179 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3180 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3181 ETH_TXQ_FLAGS_NOOFFLOADS,
3184 dev_info->rx_desc_lim = rx_desc_lim;
3185 dev_info->tx_desc_lim = tx_desc_lim;
3188 /* return 0 means link status changed, -1 means not changed */
3190 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3192 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3193 struct rte_eth_link link, old;
3194 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3198 link.link_status = ETH_LINK_DOWN;
3199 link.link_speed = 0;
3200 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3201 memset(&old, 0, sizeof(old));
3202 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3204 hw->mac.get_link_status = true;
3206 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3207 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3208 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3210 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3213 link.link_speed = ETH_SPEED_NUM_100M;
3214 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3215 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3216 if (link.link_status == old.link_status)
3222 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3223 if (link.link_status == old.link_status)
3227 link.link_status = ETH_LINK_UP;
3228 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3230 switch (link_speed) {
3232 case IXGBE_LINK_SPEED_UNKNOWN:
3233 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3234 link.link_speed = ETH_SPEED_NUM_100M;
3237 case IXGBE_LINK_SPEED_100_FULL:
3238 link.link_speed = ETH_SPEED_NUM_100M;
3241 case IXGBE_LINK_SPEED_1GB_FULL:
3242 link.link_speed = ETH_SPEED_NUM_1G;
3245 case IXGBE_LINK_SPEED_10GB_FULL:
3246 link.link_speed = ETH_SPEED_NUM_10G;
3249 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3251 if (link.link_status == old.link_status)
3258 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3260 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3263 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3264 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3265 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3269 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3271 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3274 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3275 fctrl &= (~IXGBE_FCTRL_UPE);
3276 if (dev->data->all_multicast == 1)
3277 fctrl |= IXGBE_FCTRL_MPE;
3279 fctrl &= (~IXGBE_FCTRL_MPE);
3280 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3284 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3286 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3289 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3290 fctrl |= IXGBE_FCTRL_MPE;
3291 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3295 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3297 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300 if (dev->data->promiscuous == 1)
3301 return; /* must remain in all_multicast mode */
3303 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3304 fctrl &= (~IXGBE_FCTRL_MPE);
3305 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3309 * It clears the interrupt causes and enables the interrupt.
3310 * It will be called once only during nic initialized.
3313 * Pointer to struct rte_eth_dev.
3316 * - On success, zero.
3317 * - On failure, a negative value.
3320 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3322 struct ixgbe_interrupt *intr =
3323 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3325 ixgbe_dev_link_status_print(dev);
3326 intr->mask |= IXGBE_EICR_LSC;
3332 * It clears the interrupt causes and enables the interrupt.
3333 * It will be called once only during nic initialized.
3336 * Pointer to struct rte_eth_dev.
3339 * - On success, zero.
3340 * - On failure, a negative value.
3343 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3345 struct ixgbe_interrupt *intr =
3346 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3348 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3354 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3357 * Pointer to struct rte_eth_dev.
3360 * - On success, zero.
3361 * - On failure, a negative value.
3364 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3367 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3368 struct ixgbe_interrupt *intr =
3369 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3371 /* clear all cause mask */
3372 ixgbe_disable_intr(hw);
3374 /* read-on-clear nic registers here */
3375 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3376 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3380 /* set flag for async link update */
3381 if (eicr & IXGBE_EICR_LSC)
3382 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3384 if (eicr & IXGBE_EICR_MAILBOX)
3385 intr->flags |= IXGBE_FLAG_MAILBOX;
3387 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3388 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3389 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3390 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3396 * It gets and then prints the link status.
3399 * Pointer to struct rte_eth_dev.
3402 * - On success, zero.
3403 * - On failure, a negative value.
3406 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3408 struct rte_eth_link link;
3410 memset(&link, 0, sizeof(link));
3411 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3412 if (link.link_status) {
3413 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3414 (int)(dev->data->port_id),
3415 (unsigned)link.link_speed,
3416 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3417 "full-duplex" : "half-duplex");
3419 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3420 (int)(dev->data->port_id));
3422 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3423 dev->pci_dev->addr.domain,
3424 dev->pci_dev->addr.bus,
3425 dev->pci_dev->addr.devid,
3426 dev->pci_dev->addr.function);
3430 * It executes link_update after knowing an interrupt occurred.
3433 * Pointer to struct rte_eth_dev.
3436 * - On success, zero.
3437 * - On failure, a negative value.
3440 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3442 struct ixgbe_interrupt *intr =
3443 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3445 struct rte_eth_link link;
3446 int intr_enable_delay = false;
3447 struct ixgbe_hw *hw =
3448 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3450 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3452 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3453 ixgbe_pf_mbx_process(dev);
3454 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3457 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3458 ixgbe_handle_lasi(hw);
3459 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3462 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3463 /* get the link status before link update, for predicting later */
3464 memset(&link, 0, sizeof(link));
3465 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3467 ixgbe_dev_link_update(dev, 0);
3470 if (!link.link_status)
3471 /* handle it 1 sec later, wait it being stable */
3472 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3473 /* likely to down */
3475 /* handle it 4 sec later, wait it being stable */
3476 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3478 ixgbe_dev_link_status_print(dev);
3480 intr_enable_delay = true;
3483 if (intr_enable_delay) {
3484 if (rte_eal_alarm_set(timeout * 1000,
3485 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3486 PMD_DRV_LOG(ERR, "Error setting alarm");
3488 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3489 ixgbe_enable_intr(dev);
3490 rte_intr_enable(&(dev->pci_dev->intr_handle));
3498 * Interrupt handler which shall be registered for alarm callback for delayed
3499 * handling specific interrupt to wait for the stable nic state. As the
3500 * NIC interrupt state is not stable for ixgbe after link is just down,
3501 * it needs to wait 4 seconds to get the stable status.
3504 * Pointer to interrupt handle.
3506 * The address of parameter (struct rte_eth_dev *) regsitered before.
3512 ixgbe_dev_interrupt_delayed_handler(void *param)
3514 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3515 struct ixgbe_interrupt *intr =
3516 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3517 struct ixgbe_hw *hw =
3518 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3521 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3522 if (eicr & IXGBE_EICR_MAILBOX)
3523 ixgbe_pf_mbx_process(dev);
3525 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3526 ixgbe_handle_lasi(hw);
3527 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3530 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3531 ixgbe_dev_link_update(dev, 0);
3532 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3533 ixgbe_dev_link_status_print(dev);
3534 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3537 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3538 ixgbe_enable_intr(dev);
3539 rte_intr_enable(&(dev->pci_dev->intr_handle));
3543 * Interrupt handler triggered by NIC for handling
3544 * specific interrupt.
3547 * Pointer to interrupt handle.
3549 * The address of parameter (struct rte_eth_dev *) regsitered before.
3555 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3558 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3560 ixgbe_dev_interrupt_get_status(dev);
3561 ixgbe_dev_interrupt_action(dev);
3565 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3567 struct ixgbe_hw *hw;
3569 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3570 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3574 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3576 struct ixgbe_hw *hw;
3578 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3579 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3583 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3585 struct ixgbe_hw *hw;
3591 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3593 fc_conf->pause_time = hw->fc.pause_time;
3594 fc_conf->high_water = hw->fc.high_water[0];
3595 fc_conf->low_water = hw->fc.low_water[0];
3596 fc_conf->send_xon = hw->fc.send_xon;
3597 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3600 * Return rx_pause status according to actual setting of
3603 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3604 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3610 * Return tx_pause status according to actual setting of
3613 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3614 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3619 if (rx_pause && tx_pause)
3620 fc_conf->mode = RTE_FC_FULL;
3622 fc_conf->mode = RTE_FC_RX_PAUSE;
3624 fc_conf->mode = RTE_FC_TX_PAUSE;
3626 fc_conf->mode = RTE_FC_NONE;
3632 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3634 struct ixgbe_hw *hw;
3636 uint32_t rx_buf_size;
3637 uint32_t max_high_water;
3639 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3646 PMD_INIT_FUNC_TRACE();
3648 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3649 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3650 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3653 * At least reserve one Ethernet frame for watermark
3654 * high_water/low_water in kilo bytes for ixgbe
3656 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3657 if ((fc_conf->high_water > max_high_water) ||
3658 (fc_conf->high_water < fc_conf->low_water)) {
3659 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3660 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3664 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3665 hw->fc.pause_time = fc_conf->pause_time;
3666 hw->fc.high_water[0] = fc_conf->high_water;
3667 hw->fc.low_water[0] = fc_conf->low_water;
3668 hw->fc.send_xon = fc_conf->send_xon;
3669 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3671 err = ixgbe_fc_enable(hw);
3673 /* Not negotiated is not an error case */
3674 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3676 /* check if we want to forward MAC frames - driver doesn't have native
3677 * capability to do that, so we'll write the registers ourselves */
3679 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3681 /* set or clear MFLCN.PMCF bit depending on configuration */
3682 if (fc_conf->mac_ctrl_frame_fwd != 0)
3683 mflcn |= IXGBE_MFLCN_PMCF;
3685 mflcn &= ~IXGBE_MFLCN_PMCF;
3687 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3688 IXGBE_WRITE_FLUSH(hw);
3693 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3698 * ixgbe_pfc_enable_generic - Enable flow control
3699 * @hw: pointer to hardware structure
3700 * @tc_num: traffic class number
3701 * Enable flow control according to the current settings.
3704 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3707 uint32_t mflcn_reg, fccfg_reg;
3709 uint32_t fcrtl, fcrth;
3713 /* Validate the water mark configuration */
3714 if (!hw->fc.pause_time) {
3715 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3719 /* Low water mark of zero causes XOFF floods */
3720 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3721 /* High/Low water can not be 0 */
3722 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3723 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3724 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3728 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3729 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3730 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3734 /* Negotiate the fc mode to use */
3735 ixgbe_fc_autoneg(hw);
3737 /* Disable any previous flow control settings */
3738 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3739 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3741 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3742 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3744 switch (hw->fc.current_mode) {
3747 * If the count of enabled RX Priority Flow control >1,
3748 * and the TX pause can not be disabled
3751 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3752 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3753 if (reg & IXGBE_FCRTH_FCEN)
3757 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3759 case ixgbe_fc_rx_pause:
3761 * Rx Flow control is enabled and Tx Flow control is
3762 * disabled by software override. Since there really
3763 * isn't a way to advertise that we are capable of RX
3764 * Pause ONLY, we will advertise that we support both
3765 * symmetric and asymmetric Rx PAUSE. Later, we will
3766 * disable the adapter's ability to send PAUSE frames.
3768 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3770 * If the count of enabled RX Priority Flow control >1,
3771 * and the TX pause can not be disabled
3774 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3775 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3776 if (reg & IXGBE_FCRTH_FCEN)
3780 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3782 case ixgbe_fc_tx_pause:
3784 * Tx Flow control is enabled, and Rx Flow control is
3785 * disabled by software override.
3787 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3790 /* Flow control (both Rx and Tx) is enabled by SW override. */
3791 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3792 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3795 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3796 ret_val = IXGBE_ERR_CONFIG;
3800 /* Set 802.3x based flow control settings. */
3801 mflcn_reg |= IXGBE_MFLCN_DPF;
3802 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3803 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3805 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3806 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3807 hw->fc.high_water[tc_num]) {
3808 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3809 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3810 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3812 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3814 * In order to prevent Tx hangs when the internal Tx
3815 * switch is enabled we must set the high water mark
3816 * to the maximum FCRTH value. This allows the Tx
3817 * switch to function even under heavy Rx workloads.
3819 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3821 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3823 /* Configure pause time (2 TCs per register) */
3824 reg = hw->fc.pause_time * 0x00010001;
3825 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3826 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3828 /* Configure flow control refresh threshold value */
3829 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3836 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3838 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3839 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3841 if (hw->mac.type != ixgbe_mac_82598EB) {
3842 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3848 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3851 uint32_t rx_buf_size;
3852 uint32_t max_high_water;
3854 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3855 struct ixgbe_hw *hw =
3856 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3857 struct ixgbe_dcb_config *dcb_config =
3858 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3860 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3867 PMD_INIT_FUNC_TRACE();
3869 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3870 tc_num = map[pfc_conf->priority];
3871 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3872 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3874 * At least reserve one Ethernet frame for watermark
3875 * high_water/low_water in kilo bytes for ixgbe
3877 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3878 if ((pfc_conf->fc.high_water > max_high_water) ||
3879 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3880 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3881 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3885 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3886 hw->fc.pause_time = pfc_conf->fc.pause_time;
3887 hw->fc.send_xon = pfc_conf->fc.send_xon;
3888 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3889 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3891 err = ixgbe_dcb_pfc_enable(dev, tc_num);
3893 /* Not negotiated is not an error case */
3894 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3897 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3902 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3903 struct rte_eth_rss_reta_entry64 *reta_conf,
3906 uint16_t i, sp_reta_size;
3909 uint16_t idx, shift;
3910 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3913 PMD_INIT_FUNC_TRACE();
3915 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3916 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3921 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3922 if (reta_size != sp_reta_size) {
3923 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3924 "(%d) doesn't match the number hardware can supported "
3925 "(%d)\n", reta_size, sp_reta_size);
3929 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3930 idx = i / RTE_RETA_GROUP_SIZE;
3931 shift = i % RTE_RETA_GROUP_SIZE;
3932 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3936 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3937 if (mask == IXGBE_4_BIT_MASK)
3940 r = IXGBE_READ_REG(hw, reta_reg);
3941 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3942 if (mask & (0x1 << j))
3943 reta |= reta_conf[idx].reta[shift + j] <<
3946 reta |= r & (IXGBE_8_BIT_MASK <<
3949 IXGBE_WRITE_REG(hw, reta_reg, reta);
3956 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3957 struct rte_eth_rss_reta_entry64 *reta_conf,
3960 uint16_t i, sp_reta_size;
3963 uint16_t idx, shift;
3964 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3967 PMD_INIT_FUNC_TRACE();
3968 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3969 if (reta_size != sp_reta_size) {
3970 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3971 "(%d) doesn't match the number hardware can supported "
3972 "(%d)\n", reta_size, sp_reta_size);
3976 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3977 idx = i / RTE_RETA_GROUP_SIZE;
3978 shift = i % RTE_RETA_GROUP_SIZE;
3979 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3984 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3985 reta = IXGBE_READ_REG(hw, reta_reg);
3986 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3987 if (mask & (0x1 << j))
3988 reta_conf[idx].reta[shift + j] =
3989 ((reta >> (CHAR_BIT * j)) &
3998 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3999 uint32_t index, uint32_t pool)
4001 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4002 uint32_t enable_addr = 1;
4004 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4008 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4010 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4012 ixgbe_clear_rar(hw, index);
4016 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4018 ixgbe_remove_rar(dev, 0);
4020 ixgbe_add_rar(dev, addr, 0, 0);
4024 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4028 struct ixgbe_hw *hw;
4029 struct rte_eth_dev_info dev_info;
4030 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4032 ixgbe_dev_info_get(dev, &dev_info);
4034 /* check that mtu is within the allowed range */
4035 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4038 /* refuse mtu that requires the support of scattered packets when this
4039 * feature has not been enabled before.
4041 if (!dev->data->scattered_rx &&
4042 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4043 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4046 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4047 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4049 /* switch to jumbo mode if needed */
4050 if (frame_size > ETHER_MAX_LEN) {
4051 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4052 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4054 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4055 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4057 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4059 /* update max frame size */
4060 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4062 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4063 maxfrs &= 0x0000FFFF;
4064 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4065 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4071 * Virtual Function operations
4074 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4076 PMD_INIT_FUNC_TRACE();
4078 /* Clear interrupt mask to stop from interrupts being generated */
4079 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4081 IXGBE_WRITE_FLUSH(hw);
4085 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4087 PMD_INIT_FUNC_TRACE();
4089 /* VF enable interrupt autoclean */
4090 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4091 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4092 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4094 IXGBE_WRITE_FLUSH(hw);
4098 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4100 struct rte_eth_conf *conf = &dev->data->dev_conf;
4101 struct ixgbe_adapter *adapter =
4102 (struct ixgbe_adapter *)dev->data->dev_private;
4104 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4105 dev->data->port_id);
4108 * VF has no ability to enable/disable HW CRC
4109 * Keep the persistent behavior the same as Host PF
4111 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4112 if (!conf->rxmode.hw_strip_crc) {
4113 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4114 conf->rxmode.hw_strip_crc = 1;
4117 if (conf->rxmode.hw_strip_crc) {
4118 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4119 conf->rxmode.hw_strip_crc = 0;
4124 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4125 * allocation or vector Rx preconditions we will reset it.
4127 adapter->rx_bulk_alloc_allowed = true;
4128 adapter->rx_vec_allowed = true;
4134 ixgbevf_dev_start(struct rte_eth_dev *dev)
4136 struct ixgbe_hw *hw =
4137 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4138 uint32_t intr_vector = 0;
4139 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4143 PMD_INIT_FUNC_TRACE();
4145 hw->mac.ops.reset_hw(hw);
4146 hw->mac.get_link_status = true;
4148 /* negotiate mailbox API version to use with the PF. */
4149 ixgbevf_negotiate_api(hw);
4151 ixgbevf_dev_tx_init(dev);
4153 /* This can fail when allocating mbufs for descriptor rings */
4154 err = ixgbevf_dev_rx_init(dev);
4156 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4157 ixgbe_dev_clear_queues(dev);
4162 ixgbevf_set_vfta_all(dev, 1);
4165 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4166 ETH_VLAN_EXTEND_MASK;
4167 ixgbevf_vlan_offload_set(dev, mask);
4169 ixgbevf_dev_rxtx_start(dev);
4171 /* check and configure queue intr-vector mapping */
4172 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4173 intr_vector = dev->data->nb_rx_queues;
4174 if (rte_intr_efd_enable(intr_handle, intr_vector))
4178 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4179 intr_handle->intr_vec =
4180 rte_zmalloc("intr_vec",
4181 dev->data->nb_rx_queues * sizeof(int), 0);
4182 if (intr_handle->intr_vec == NULL) {
4183 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4184 " intr_vec\n", dev->data->nb_rx_queues);
4188 ixgbevf_configure_msix(dev);
4190 rte_intr_enable(intr_handle);
4192 /* Re-enable interrupt for VF */
4193 ixgbevf_intr_enable(hw);
4199 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4201 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4204 PMD_INIT_FUNC_TRACE();
4206 ixgbevf_intr_disable(hw);
4208 hw->adapter_stopped = 1;
4209 ixgbe_stop_adapter(hw);
4212 * Clear what we set, but we still keep shadow_vfta to
4213 * restore after device starts
4215 ixgbevf_set_vfta_all(dev, 0);
4217 /* Clear stored conf */
4218 dev->data->scattered_rx = 0;
4220 ixgbe_dev_clear_queues(dev);
4222 /* Clean datapath event and queue/vec mapping */
4223 rte_intr_efd_disable(intr_handle);
4224 if (intr_handle->intr_vec != NULL) {
4225 rte_free(intr_handle->intr_vec);
4226 intr_handle->intr_vec = NULL;
4231 ixgbevf_dev_close(struct rte_eth_dev *dev)
4233 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235 PMD_INIT_FUNC_TRACE();
4239 ixgbevf_dev_stop(dev);
4241 ixgbe_dev_free_queues(dev);
4244 * Remove the VF MAC address ro ensure
4245 * that the VF traffic goes to the PF
4246 * after stop, close and detach of the VF
4248 ixgbevf_remove_mac_addr(dev, 0);
4251 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4253 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4254 struct ixgbe_vfta *shadow_vfta =
4255 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4256 int i = 0, j = 0, vfta = 0, mask = 1;
4258 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4259 vfta = shadow_vfta->vfta[i];
4262 for (j = 0; j < 32; j++) {
4264 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4274 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4276 struct ixgbe_hw *hw =
4277 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4278 struct ixgbe_vfta *shadow_vfta =
4279 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4280 uint32_t vid_idx = 0;
4281 uint32_t vid_bit = 0;
4284 PMD_INIT_FUNC_TRACE();
4286 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4287 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4289 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4292 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4293 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4295 /* Save what we set and retore it after device reset */
4297 shadow_vfta->vfta[vid_idx] |= vid_bit;
4299 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4305 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4307 struct ixgbe_hw *hw =
4308 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4311 PMD_INIT_FUNC_TRACE();
4313 if (queue >= hw->mac.max_rx_queues)
4316 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4318 ctrl |= IXGBE_RXDCTL_VME;
4320 ctrl &= ~IXGBE_RXDCTL_VME;
4321 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4323 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4327 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4329 struct ixgbe_hw *hw =
4330 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4334 /* VF function only support hw strip feature, others are not support */
4335 if (mask & ETH_VLAN_STRIP_MASK) {
4336 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4338 for (i = 0; i < hw->mac.max_rx_queues; i++)
4339 ixgbevf_vlan_strip_queue_set(dev, i, on);
4344 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4348 /* we only need to do this if VMDq is enabled */
4349 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4350 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4351 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4359 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4361 uint32_t vector = 0;
4363 switch (hw->mac.mc_filter_type) {
4364 case 0: /* use bits [47:36] of the address */
4365 vector = ((uc_addr->addr_bytes[4] >> 4) |
4366 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4368 case 1: /* use bits [46:35] of the address */
4369 vector = ((uc_addr->addr_bytes[4] >> 3) |
4370 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4372 case 2: /* use bits [45:34] of the address */
4373 vector = ((uc_addr->addr_bytes[4] >> 2) |
4374 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4376 case 3: /* use bits [43:32] of the address */
4377 vector = ((uc_addr->addr_bytes[4]) |
4378 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4380 default: /* Invalid mc_filter_type */
4384 /* vector can only be 12-bits or boundary will be exceeded */
4390 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4398 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4399 const uint32_t ixgbe_uta_bit_shift = 5;
4400 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4401 const uint32_t bit1 = 0x1;
4403 struct ixgbe_hw *hw =
4404 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4405 struct ixgbe_uta_info *uta_info =
4406 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4408 /* The UTA table only exists on 82599 hardware and newer */
4409 if (hw->mac.type < ixgbe_mac_82599EB)
4412 vector = ixgbe_uta_vector(hw, mac_addr);
4413 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4414 uta_shift = vector & ixgbe_uta_bit_mask;
4416 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4420 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4422 uta_info->uta_in_use++;
4423 reg_val |= (bit1 << uta_shift);
4424 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4426 uta_info->uta_in_use--;
4427 reg_val &= ~(bit1 << uta_shift);
4428 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4431 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4433 if (uta_info->uta_in_use > 0)
4434 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4435 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4437 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4443 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4446 struct ixgbe_hw *hw =
4447 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4448 struct ixgbe_uta_info *uta_info =
4449 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4451 /* The UTA table only exists on 82599 hardware and newer */
4452 if (hw->mac.type < ixgbe_mac_82599EB)
4456 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4457 uta_info->uta_shadow[i] = ~0;
4458 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4461 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4462 uta_info->uta_shadow[i] = 0;
4463 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4471 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4473 uint32_t new_val = orig_val;
4475 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4476 new_val |= IXGBE_VMOLR_AUPE;
4477 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4478 new_val |= IXGBE_VMOLR_ROMPE;
4479 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4480 new_val |= IXGBE_VMOLR_ROPE;
4481 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4482 new_val |= IXGBE_VMOLR_BAM;
4483 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4484 new_val |= IXGBE_VMOLR_MPE;
4490 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4491 uint16_t rx_mask, uint8_t on)
4495 struct ixgbe_hw *hw =
4496 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4497 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4499 if (hw->mac.type == ixgbe_mac_82598EB) {
4500 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4501 " on 82599 hardware and newer");
4504 if (ixgbe_vmdq_mode_check(hw) < 0)
4507 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4514 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4520 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4524 const uint8_t bit1 = 0x1;
4526 struct ixgbe_hw *hw =
4527 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4529 if (ixgbe_vmdq_mode_check(hw) < 0)
4532 if (pool >= ETH_64_POOLS)
4535 /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4537 addr = IXGBE_VFRE(1);
4538 val = bit1 << (pool - 32);
4540 addr = IXGBE_VFRE(0);
4544 reg = IXGBE_READ_REG(hw, addr);
4551 IXGBE_WRITE_REG(hw, addr, reg);
4557 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4561 const uint8_t bit1 = 0x1;
4563 struct ixgbe_hw *hw =
4564 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4566 if (ixgbe_vmdq_mode_check(hw) < 0)
4569 if (pool >= ETH_64_POOLS)
4572 /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4574 addr = IXGBE_VFTE(1);
4575 val = bit1 << (pool - 32);
4577 addr = IXGBE_VFTE(0);
4581 reg = IXGBE_READ_REG(hw, addr);
4588 IXGBE_WRITE_REG(hw, addr, reg);
4594 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4595 uint64_t pool_mask, uint8_t vlan_on)
4599 struct ixgbe_hw *hw =
4600 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4602 if (ixgbe_vmdq_mode_check(hw) < 0)
4604 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4605 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4606 ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4616 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4617 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4618 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4619 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4620 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4621 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4622 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4625 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4626 struct rte_eth_mirror_conf *mirror_conf,
4627 uint8_t rule_id, uint8_t on)
4629 uint32_t mr_ctl, vlvf;
4630 uint32_t mp_lsb = 0;
4631 uint32_t mv_msb = 0;
4632 uint32_t mv_lsb = 0;
4633 uint32_t mp_msb = 0;
4636 uint64_t vlan_mask = 0;
4638 const uint8_t pool_mask_offset = 32;
4639 const uint8_t vlan_mask_offset = 32;
4640 const uint8_t dst_pool_offset = 8;
4641 const uint8_t rule_mr_offset = 4;
4642 const uint8_t mirror_rule_mask = 0x0F;
4644 struct ixgbe_mirror_info *mr_info =
4645 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4646 struct ixgbe_hw *hw =
4647 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4648 uint8_t mirror_type = 0;
4650 if (ixgbe_vmdq_mode_check(hw) < 0)
4653 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4656 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4657 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4658 mirror_conf->rule_type);
4662 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4663 mirror_type |= IXGBE_MRCTL_VLME;
4664 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4665 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4666 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4667 /* search vlan id related pool vlan filter index */
4668 reg_index = ixgbe_find_vlvf_slot(hw,
4669 mirror_conf->vlan.vlan_id[i],
4673 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4674 if ((vlvf & IXGBE_VLVF_VIEN) &&
4675 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4676 mirror_conf->vlan.vlan_id[i]))
4677 vlan_mask |= (1ULL << reg_index);
4684 mv_lsb = vlan_mask & 0xFFFFFFFF;
4685 mv_msb = vlan_mask >> vlan_mask_offset;
4687 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4688 mirror_conf->vlan.vlan_mask;
4689 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4690 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4691 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4692 mirror_conf->vlan.vlan_id[i];
4697 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4698 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4699 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4704 * if enable pool mirror, write related pool mask register,if disable
4705 * pool mirror, clear PFMRVM register
4707 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4708 mirror_type |= IXGBE_MRCTL_VPME;
4710 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4711 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4712 mr_info->mr_conf[rule_id].pool_mask =
4713 mirror_conf->pool_mask;
4718 mr_info->mr_conf[rule_id].pool_mask = 0;
4721 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4722 mirror_type |= IXGBE_MRCTL_UPME;
4723 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4724 mirror_type |= IXGBE_MRCTL_DPME;
4726 /* read mirror control register and recalculate it */
4727 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4730 mr_ctl |= mirror_type;
4731 mr_ctl &= mirror_rule_mask;
4732 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4734 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4736 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4737 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4739 /* write mirrror control register */
4740 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4742 /* write pool mirrror control register */
4743 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4744 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4745 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4748 /* write VLAN mirrror control register */
4749 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4750 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4751 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4759 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4762 uint32_t lsb_val = 0;
4763 uint32_t msb_val = 0;
4764 const uint8_t rule_mr_offset = 4;
4766 struct ixgbe_hw *hw =
4767 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4768 struct ixgbe_mirror_info *mr_info =
4769 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4771 if (ixgbe_vmdq_mode_check(hw) < 0)
4774 memset(&mr_info->mr_conf[rule_id], 0,
4775 sizeof(struct rte_eth_mirror_conf));
4777 /* clear PFVMCTL register */
4778 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4780 /* clear pool mask register */
4781 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4782 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4784 /* clear vlan mask register */
4785 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4786 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4792 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4795 struct ixgbe_hw *hw =
4796 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4798 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4799 mask |= (1 << IXGBE_MISC_VEC_ID);
4800 RTE_SET_USED(queue_id);
4801 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4803 rte_intr_enable(&dev->pci_dev->intr_handle);
4809 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4812 struct ixgbe_hw *hw =
4813 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4815 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4816 mask &= ~(1 << IXGBE_MISC_VEC_ID);
4817 RTE_SET_USED(queue_id);
4818 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4824 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4827 struct ixgbe_hw *hw =
4828 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829 struct ixgbe_interrupt *intr =
4830 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4832 if (queue_id < 16) {
4833 ixgbe_disable_intr(hw);
4834 intr->mask |= (1 << queue_id);
4835 ixgbe_enable_intr(dev);
4836 } else if (queue_id < 32) {
4837 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4838 mask &= (1 << queue_id);
4839 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4840 } else if (queue_id < 64) {
4841 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4842 mask &= (1 << (queue_id - 32));
4843 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4845 rte_intr_enable(&dev->pci_dev->intr_handle);
4851 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4854 struct ixgbe_hw *hw =
4855 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4856 struct ixgbe_interrupt *intr =
4857 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4859 if (queue_id < 16) {
4860 ixgbe_disable_intr(hw);
4861 intr->mask &= ~(1 << queue_id);
4862 ixgbe_enable_intr(dev);
4863 } else if (queue_id < 32) {
4864 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4865 mask &= ~(1 << queue_id);
4866 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4867 } else if (queue_id < 64) {
4868 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4869 mask &= ~(1 << (queue_id - 32));
4870 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4877 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4878 uint8_t queue, uint8_t msix_vector)
4882 if (direction == -1) {
4884 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4885 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4888 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4890 /* rx or tx cause */
4891 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4892 idx = ((16 * (queue & 1)) + (8 * direction));
4893 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4894 tmp &= ~(0xFF << idx);
4895 tmp |= (msix_vector << idx);
4896 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4901 * set the IVAR registers, mapping interrupt causes to vectors
4903 * pointer to ixgbe_hw struct
4905 * 0 for Rx, 1 for Tx, -1 for other causes
4907 * queue to map the corresponding interrupt to
4909 * the vector to map to the corresponding queue
4912 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4913 uint8_t queue, uint8_t msix_vector)
4917 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4918 if (hw->mac.type == ixgbe_mac_82598EB) {
4919 if (direction == -1)
4921 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4922 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4923 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4924 tmp |= (msix_vector << (8 * (queue & 0x3)));
4925 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4926 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4927 (hw->mac.type == ixgbe_mac_X540)) {
4928 if (direction == -1) {
4930 idx = ((queue & 1) * 8);
4931 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4932 tmp &= ~(0xFF << idx);
4933 tmp |= (msix_vector << idx);
4934 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4936 /* rx or tx causes */
4937 idx = ((16 * (queue & 1)) + (8 * direction));
4938 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4939 tmp &= ~(0xFF << idx);
4940 tmp |= (msix_vector << idx);
4941 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4947 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4949 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4950 struct ixgbe_hw *hw =
4951 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4953 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4955 /* Configure VF other cause ivar */
4956 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4958 /* won't configure msix register if no mapping is done
4959 * between intr vector and event fd.
4961 if (!rte_intr_dp_is_en(intr_handle))
4964 /* Configure all RX queues of VF */
4965 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4966 /* Force all queue use vector 0,
4967 * as IXGBE_VF_MAXMSIVECOTR = 1
4969 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4970 intr_handle->intr_vec[q_idx] = vector_idx;
4975 * Sets up the hardware to properly generate MSI-X interrupts
4977 * board private structure
4980 ixgbe_configure_msix(struct rte_eth_dev *dev)
4982 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4983 struct ixgbe_hw *hw =
4984 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4985 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4986 uint32_t vec = IXGBE_MISC_VEC_ID;
4990 /* won't configure msix register if no mapping is done
4991 * between intr vector and event fd
4993 if (!rte_intr_dp_is_en(intr_handle))
4996 if (rte_intr_allow_others(intr_handle))
4997 vec = base = IXGBE_RX_VEC_START;
4999 /* setup GPIE for MSI-x mode */
5000 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5001 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5002 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5003 /* auto clearing and auto setting corresponding bits in EIMS
5004 * when MSI-X interrupt is triggered
5006 if (hw->mac.type == ixgbe_mac_82598EB) {
5007 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5009 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5010 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5012 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5014 /* Populate the IVAR table and set the ITR values to the
5015 * corresponding register.
5017 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5019 /* by default, 1:1 mapping */
5020 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5021 intr_handle->intr_vec[queue_id] = vec;
5022 if (vec < base + intr_handle->nb_efd - 1)
5026 switch (hw->mac.type) {
5027 case ixgbe_mac_82598EB:
5028 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5031 case ixgbe_mac_82599EB:
5032 case ixgbe_mac_X540:
5033 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5038 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5039 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5041 /* set up to autoclear timer, and the vectors */
5042 mask = IXGBE_EIMS_ENABLE_MASK;
5043 mask &= ~(IXGBE_EIMS_OTHER |
5044 IXGBE_EIMS_MAILBOX |
5047 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5050 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5051 uint16_t queue_idx, uint16_t tx_rate)
5053 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5054 uint32_t rf_dec, rf_int;
5056 uint16_t link_speed = dev->data->dev_link.link_speed;
5058 if (queue_idx >= hw->mac.max_tx_queues)
5062 /* Calculate the rate factor values to set */
5063 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5064 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5065 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5067 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5068 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5069 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5070 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5076 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5077 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5080 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5081 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5082 IXGBE_MAX_JUMBO_FRAME_SIZE))
5083 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5084 IXGBE_MMW_SIZE_JUMBO_FRAME);
5086 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5087 IXGBE_MMW_SIZE_DEFAULT);
5089 /* Set RTTBCNRC of queue X */
5090 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5091 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5092 IXGBE_WRITE_FLUSH(hw);
5097 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5098 uint16_t tx_rate, uint64_t q_msk)
5100 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5101 struct ixgbe_vf_info *vfinfo =
5102 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5103 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5104 uint32_t queue_stride =
5105 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5106 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5107 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5108 uint16_t total_rate = 0;
5110 if (queue_end >= hw->mac.max_tx_queues)
5113 if (vfinfo != NULL) {
5114 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5117 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5119 total_rate += vfinfo[vf_idx].tx_rate[idx];
5124 /* Store tx_rate for this vf. */
5125 for (idx = 0; idx < nb_q_per_pool; idx++) {
5126 if (((uint64_t)0x1 << idx) & q_msk) {
5127 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5128 vfinfo[vf].tx_rate[idx] = tx_rate;
5129 total_rate += tx_rate;
5133 if (total_rate > dev->data->dev_link.link_speed) {
5135 * Reset stored TX rate of the VF if it causes exceed
5138 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5142 /* Set RTTBCNRC of each queue/pool for vf X */
5143 for (; queue_idx <= queue_end; queue_idx++) {
5145 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5153 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5154 __attribute__((unused)) uint32_t index,
5155 __attribute__((unused)) uint32_t pool)
5157 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5161 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5162 * operation. Trap this case to avoid exhausting the [very limited]
5163 * set of PF resources used to store VF MAC addresses.
5165 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5167 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5170 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5174 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5176 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5177 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5178 struct ether_addr *mac_addr;
5183 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5184 * not support the deletion of a given MAC address.
5185 * Instead, it imposes to delete all MAC addresses, then to add again
5186 * all MAC addresses with the exception of the one to be deleted.
5188 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5191 * Add again all MAC addresses, with the exception of the deleted one
5192 * and of the permanent MAC address.
5194 for (i = 0, mac_addr = dev->data->mac_addrs;
5195 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5196 /* Skip the deleted MAC address */
5199 /* Skip NULL MAC addresses */
5200 if (is_zero_ether_addr(mac_addr))
5202 /* Skip the permanent MAC address */
5203 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5205 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5208 "Adding again MAC address "
5209 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5211 mac_addr->addr_bytes[0],
5212 mac_addr->addr_bytes[1],
5213 mac_addr->addr_bytes[2],
5214 mac_addr->addr_bytes[3],
5215 mac_addr->addr_bytes[4],
5216 mac_addr->addr_bytes[5],
5222 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5224 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5226 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5229 #define MAC_TYPE_FILTER_SUP(type) do {\
5230 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5231 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5232 (type) != ixgbe_mac_X550EM_a)\
5237 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5238 struct rte_eth_syn_filter *filter,
5241 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5244 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5247 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5250 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5252 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5253 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5255 if (filter->hig_pri)
5256 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5258 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5260 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5262 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5264 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5265 IXGBE_WRITE_FLUSH(hw);
5270 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5271 struct rte_eth_syn_filter *filter)
5273 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5274 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5276 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5277 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5278 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5285 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5286 enum rte_filter_op filter_op,
5289 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5292 MAC_TYPE_FILTER_SUP(hw->mac.type);
5294 if (filter_op == RTE_ETH_FILTER_NOP)
5298 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5303 switch (filter_op) {
5304 case RTE_ETH_FILTER_ADD:
5305 ret = ixgbe_syn_filter_set(dev,
5306 (struct rte_eth_syn_filter *)arg,
5309 case RTE_ETH_FILTER_DELETE:
5310 ret = ixgbe_syn_filter_set(dev,
5311 (struct rte_eth_syn_filter *)arg,
5314 case RTE_ETH_FILTER_GET:
5315 ret = ixgbe_syn_filter_get(dev,
5316 (struct rte_eth_syn_filter *)arg);
5319 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5328 static inline enum ixgbe_5tuple_protocol
5329 convert_protocol_type(uint8_t protocol_value)
5331 if (protocol_value == IPPROTO_TCP)
5332 return IXGBE_FILTER_PROTOCOL_TCP;
5333 else if (protocol_value == IPPROTO_UDP)
5334 return IXGBE_FILTER_PROTOCOL_UDP;
5335 else if (protocol_value == IPPROTO_SCTP)
5336 return IXGBE_FILTER_PROTOCOL_SCTP;
5338 return IXGBE_FILTER_PROTOCOL_NONE;
5342 * add a 5tuple filter
5345 * dev: Pointer to struct rte_eth_dev.
5346 * index: the index the filter allocates.
5347 * filter: ponter to the filter that will be added.
5348 * rx_queue: the queue id the filter assigned to.
5351 * - On success, zero.
5352 * - On failure, a negative value.
5355 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5356 struct ixgbe_5tuple_filter *filter)
5358 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5359 struct ixgbe_filter_info *filter_info =
5360 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5362 uint32_t ftqf, sdpqf;
5363 uint32_t l34timir = 0;
5364 uint8_t mask = 0xff;
5367 * look for an unused 5tuple filter index,
5368 * and insert the filter to list.
5370 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5371 idx = i / (sizeof(uint32_t) * NBBY);
5372 shift = i % (sizeof(uint32_t) * NBBY);
5373 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5374 filter_info->fivetuple_mask[idx] |= 1 << shift;
5376 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5382 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5383 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5387 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5388 IXGBE_SDPQF_DSTPORT_SHIFT);
5389 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5391 ftqf = (uint32_t)(filter->filter_info.proto &
5392 IXGBE_FTQF_PROTOCOL_MASK);
5393 ftqf |= (uint32_t)((filter->filter_info.priority &
5394 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5395 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5396 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5397 if (filter->filter_info.dst_ip_mask == 0)
5398 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5399 if (filter->filter_info.src_port_mask == 0)
5400 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5401 if (filter->filter_info.dst_port_mask == 0)
5402 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5403 if (filter->filter_info.proto_mask == 0)
5404 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5405 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5406 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5407 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5409 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5410 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5411 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5412 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5414 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5415 l34timir |= (uint32_t)(filter->queue <<
5416 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5417 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5422 * remove a 5tuple filter
5425 * dev: Pointer to struct rte_eth_dev.
5426 * filter: the pointer of the filter will be removed.
5429 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5430 struct ixgbe_5tuple_filter *filter)
5432 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5433 struct ixgbe_filter_info *filter_info =
5434 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5435 uint16_t index = filter->index;
5437 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5438 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5439 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5442 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5443 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5444 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5445 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5446 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5450 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5452 struct ixgbe_hw *hw;
5453 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5455 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5457 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5460 /* refuse mtu that requires the support of scattered packets when this
5461 * feature has not been enabled before.
5463 if (!dev->data->scattered_rx &&
5464 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5465 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5469 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5470 * request of the version 2.0 of the mailbox API.
5471 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5472 * of the mailbox API.
5473 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5474 * prior to 3.11.33 which contains the following change:
5475 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5477 ixgbevf_rlpml_set_vf(hw, max_frame);
5479 /* update max frame size */
5480 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5484 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5485 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5489 static inline struct ixgbe_5tuple_filter *
5490 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5491 struct ixgbe_5tuple_filter_info *key)
5493 struct ixgbe_5tuple_filter *it;
5495 TAILQ_FOREACH(it, filter_list, entries) {
5496 if (memcmp(key, &it->filter_info,
5497 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5504 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5506 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5507 struct ixgbe_5tuple_filter_info *filter_info)
5509 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5510 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5511 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5514 switch (filter->dst_ip_mask) {
5516 filter_info->dst_ip_mask = 0;
5517 filter_info->dst_ip = filter->dst_ip;
5520 filter_info->dst_ip_mask = 1;
5523 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5527 switch (filter->src_ip_mask) {
5529 filter_info->src_ip_mask = 0;
5530 filter_info->src_ip = filter->src_ip;
5533 filter_info->src_ip_mask = 1;
5536 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5540 switch (filter->dst_port_mask) {
5542 filter_info->dst_port_mask = 0;
5543 filter_info->dst_port = filter->dst_port;
5546 filter_info->dst_port_mask = 1;
5549 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5553 switch (filter->src_port_mask) {
5555 filter_info->src_port_mask = 0;
5556 filter_info->src_port = filter->src_port;
5559 filter_info->src_port_mask = 1;
5562 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5566 switch (filter->proto_mask) {
5568 filter_info->proto_mask = 0;
5569 filter_info->proto =
5570 convert_protocol_type(filter->proto);
5573 filter_info->proto_mask = 1;
5576 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5580 filter_info->priority = (uint8_t)filter->priority;
5585 * add or delete a ntuple filter
5588 * dev: Pointer to struct rte_eth_dev.
5589 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5590 * add: if true, add filter, if false, remove filter
5593 * - On success, zero.
5594 * - On failure, a negative value.
5597 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5598 struct rte_eth_ntuple_filter *ntuple_filter,
5601 struct ixgbe_filter_info *filter_info =
5602 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5603 struct ixgbe_5tuple_filter_info filter_5tuple;
5604 struct ixgbe_5tuple_filter *filter;
5607 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5608 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5612 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5613 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5617 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5619 if (filter != NULL && add) {
5620 PMD_DRV_LOG(ERR, "filter exists.");
5623 if (filter == NULL && !add) {
5624 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5629 filter = rte_zmalloc("ixgbe_5tuple_filter",
5630 sizeof(struct ixgbe_5tuple_filter), 0);
5633 (void)rte_memcpy(&filter->filter_info,
5635 sizeof(struct ixgbe_5tuple_filter_info));
5636 filter->queue = ntuple_filter->queue;
5637 ret = ixgbe_add_5tuple_filter(dev, filter);
5643 ixgbe_remove_5tuple_filter(dev, filter);
5649 * get a ntuple filter
5652 * dev: Pointer to struct rte_eth_dev.
5653 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5656 * - On success, zero.
5657 * - On failure, a negative value.
5660 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5661 struct rte_eth_ntuple_filter *ntuple_filter)
5663 struct ixgbe_filter_info *filter_info =
5664 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5665 struct ixgbe_5tuple_filter_info filter_5tuple;
5666 struct ixgbe_5tuple_filter *filter;
5669 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5670 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5674 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5675 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5679 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5681 if (filter == NULL) {
5682 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5685 ntuple_filter->queue = filter->queue;
5690 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5691 * @dev: pointer to rte_eth_dev structure
5692 * @filter_op:operation will be taken.
5693 * @arg: a pointer to specific structure corresponding to the filter_op
5696 * - On success, zero.
5697 * - On failure, a negative value.
5700 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5701 enum rte_filter_op filter_op,
5704 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5707 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5709 if (filter_op == RTE_ETH_FILTER_NOP)
5713 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5718 switch (filter_op) {
5719 case RTE_ETH_FILTER_ADD:
5720 ret = ixgbe_add_del_ntuple_filter(dev,
5721 (struct rte_eth_ntuple_filter *)arg,
5724 case RTE_ETH_FILTER_DELETE:
5725 ret = ixgbe_add_del_ntuple_filter(dev,
5726 (struct rte_eth_ntuple_filter *)arg,
5729 case RTE_ETH_FILTER_GET:
5730 ret = ixgbe_get_ntuple_filter(dev,
5731 (struct rte_eth_ntuple_filter *)arg);
5734 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5742 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5747 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5748 if (filter_info->ethertype_filters[i] == ethertype &&
5749 (filter_info->ethertype_mask & (1 << i)))
5756 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5761 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5762 if (!(filter_info->ethertype_mask & (1 << i))) {
5763 filter_info->ethertype_mask |= 1 << i;
5764 filter_info->ethertype_filters[i] = ethertype;
5772 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5775 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5777 filter_info->ethertype_mask &= ~(1 << idx);
5778 filter_info->ethertype_filters[idx] = 0;
5783 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5784 struct rte_eth_ethertype_filter *filter,
5787 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5788 struct ixgbe_filter_info *filter_info =
5789 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5794 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5797 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5798 filter->ether_type == ETHER_TYPE_IPv6) {
5799 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5800 " ethertype filter.", filter->ether_type);
5804 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5805 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5808 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5809 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5813 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5814 if (ret >= 0 && add) {
5815 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5816 filter->ether_type);
5819 if (ret < 0 && !add) {
5820 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5821 filter->ether_type);
5826 ret = ixgbe_ethertype_filter_insert(filter_info,
5827 filter->ether_type);
5829 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5832 etqf = IXGBE_ETQF_FILTER_EN;
5833 etqf |= (uint32_t)filter->ether_type;
5834 etqs |= (uint32_t)((filter->queue <<
5835 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5836 IXGBE_ETQS_RX_QUEUE);
5837 etqs |= IXGBE_ETQS_QUEUE_EN;
5839 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5843 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5844 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5845 IXGBE_WRITE_FLUSH(hw);
5851 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5852 struct rte_eth_ethertype_filter *filter)
5854 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5855 struct ixgbe_filter_info *filter_info =
5856 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5857 uint32_t etqf, etqs;
5860 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5862 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5863 filter->ether_type);
5867 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5868 if (etqf & IXGBE_ETQF_FILTER_EN) {
5869 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5870 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5872 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5873 IXGBE_ETQS_RX_QUEUE_SHIFT;
5880 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5881 * @dev: pointer to rte_eth_dev structure
5882 * @filter_op:operation will be taken.
5883 * @arg: a pointer to specific structure corresponding to the filter_op
5886 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5887 enum rte_filter_op filter_op,
5890 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5893 MAC_TYPE_FILTER_SUP(hw->mac.type);
5895 if (filter_op == RTE_ETH_FILTER_NOP)
5899 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5904 switch (filter_op) {
5905 case RTE_ETH_FILTER_ADD:
5906 ret = ixgbe_add_del_ethertype_filter(dev,
5907 (struct rte_eth_ethertype_filter *)arg,
5910 case RTE_ETH_FILTER_DELETE:
5911 ret = ixgbe_add_del_ethertype_filter(dev,
5912 (struct rte_eth_ethertype_filter *)arg,
5915 case RTE_ETH_FILTER_GET:
5916 ret = ixgbe_get_ethertype_filter(dev,
5917 (struct rte_eth_ethertype_filter *)arg);
5920 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5928 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5929 enum rte_filter_type filter_type,
5930 enum rte_filter_op filter_op,
5935 switch (filter_type) {
5936 case RTE_ETH_FILTER_NTUPLE:
5937 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5939 case RTE_ETH_FILTER_ETHERTYPE:
5940 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5942 case RTE_ETH_FILTER_SYN:
5943 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5945 case RTE_ETH_FILTER_FDIR:
5946 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5948 case RTE_ETH_FILTER_L2_TUNNEL:
5949 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5952 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5961 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5962 u8 **mc_addr_ptr, u32 *vmdq)
5967 mc_addr = *mc_addr_ptr;
5968 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5973 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5974 struct ether_addr *mc_addr_set,
5975 uint32_t nb_mc_addr)
5977 struct ixgbe_hw *hw;
5980 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5981 mc_addr_list = (u8 *)mc_addr_set;
5982 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5983 ixgbe_dev_addr_list_itr, TRUE);
5987 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5989 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5990 uint64_t systime_cycles;
5992 switch (hw->mac.type) {
5993 case ixgbe_mac_X550:
5994 case ixgbe_mac_X550EM_x:
5995 case ixgbe_mac_X550EM_a:
5996 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5997 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5998 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6002 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6003 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6007 return systime_cycles;
6011 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6013 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6014 uint64_t rx_tstamp_cycles;
6016 switch (hw->mac.type) {
6017 case ixgbe_mac_X550:
6018 case ixgbe_mac_X550EM_x:
6019 case ixgbe_mac_X550EM_a:
6020 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6021 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6022 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6026 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6027 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6028 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6032 return rx_tstamp_cycles;
6036 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6038 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6039 uint64_t tx_tstamp_cycles;
6041 switch (hw->mac.type) {
6042 case ixgbe_mac_X550:
6043 case ixgbe_mac_X550EM_x:
6044 case ixgbe_mac_X550EM_a:
6045 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6046 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6047 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6051 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6052 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6053 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6057 return tx_tstamp_cycles;
6061 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6063 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6064 struct ixgbe_adapter *adapter =
6065 (struct ixgbe_adapter *)dev->data->dev_private;
6066 struct rte_eth_link link;
6067 uint32_t incval = 0;
6070 /* Get current link speed. */
6071 memset(&link, 0, sizeof(link));
6072 ixgbe_dev_link_update(dev, 1);
6073 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6075 switch (link.link_speed) {
6076 case ETH_SPEED_NUM_100M:
6077 incval = IXGBE_INCVAL_100;
6078 shift = IXGBE_INCVAL_SHIFT_100;
6080 case ETH_SPEED_NUM_1G:
6081 incval = IXGBE_INCVAL_1GB;
6082 shift = IXGBE_INCVAL_SHIFT_1GB;
6084 case ETH_SPEED_NUM_10G:
6086 incval = IXGBE_INCVAL_10GB;
6087 shift = IXGBE_INCVAL_SHIFT_10GB;
6091 switch (hw->mac.type) {
6092 case ixgbe_mac_X550:
6093 case ixgbe_mac_X550EM_x:
6094 case ixgbe_mac_X550EM_a:
6095 /* Independent of link speed. */
6097 /* Cycles read will be interpreted as ns. */
6100 case ixgbe_mac_X540:
6101 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6103 case ixgbe_mac_82599EB:
6104 incval >>= IXGBE_INCVAL_SHIFT_82599;
6105 shift -= IXGBE_INCVAL_SHIFT_82599;
6106 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6107 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6110 /* Not supported. */
6114 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6115 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6116 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6118 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6119 adapter->systime_tc.cc_shift = shift;
6120 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6122 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6123 adapter->rx_tstamp_tc.cc_shift = shift;
6124 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6126 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6127 adapter->tx_tstamp_tc.cc_shift = shift;
6128 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6132 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6134 struct ixgbe_adapter *adapter =
6135 (struct ixgbe_adapter *)dev->data->dev_private;
6137 adapter->systime_tc.nsec += delta;
6138 adapter->rx_tstamp_tc.nsec += delta;
6139 adapter->tx_tstamp_tc.nsec += delta;
6145 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6148 struct ixgbe_adapter *adapter =
6149 (struct ixgbe_adapter *)dev->data->dev_private;
6151 ns = rte_timespec_to_ns(ts);
6152 /* Set the timecounters to a new value. */
6153 adapter->systime_tc.nsec = ns;
6154 adapter->rx_tstamp_tc.nsec = ns;
6155 adapter->tx_tstamp_tc.nsec = ns;
6161 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6163 uint64_t ns, systime_cycles;
6164 struct ixgbe_adapter *adapter =
6165 (struct ixgbe_adapter *)dev->data->dev_private;
6167 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6168 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6169 *ts = rte_ns_to_timespec(ns);
6175 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6177 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6181 /* Stop the timesync system time. */
6182 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6183 /* Reset the timesync system time value. */
6184 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6185 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6187 /* Enable system time for platforms where it isn't on by default. */
6188 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6189 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6190 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6192 ixgbe_start_timecounters(dev);
6194 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6195 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6197 IXGBE_ETQF_FILTER_EN |
6200 /* Enable timestamping of received PTP packets. */
6201 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6202 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6203 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6205 /* Enable timestamping of transmitted PTP packets. */
6206 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6207 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6208 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6210 IXGBE_WRITE_FLUSH(hw);
6216 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6218 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6221 /* Disable timestamping of transmitted PTP packets. */
6222 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6223 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6224 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6226 /* Disable timestamping of received PTP packets. */
6227 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6228 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6229 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6231 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6232 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6234 /* Stop incrementating the System Time registers. */
6235 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6241 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6242 struct timespec *timestamp,
6243 uint32_t flags __rte_unused)
6245 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6246 struct ixgbe_adapter *adapter =
6247 (struct ixgbe_adapter *)dev->data->dev_private;
6248 uint32_t tsync_rxctl;
6249 uint64_t rx_tstamp_cycles;
6252 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6253 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6256 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6257 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6258 *timestamp = rte_ns_to_timespec(ns);
6264 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6265 struct timespec *timestamp)
6267 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6268 struct ixgbe_adapter *adapter =
6269 (struct ixgbe_adapter *)dev->data->dev_private;
6270 uint32_t tsync_txctl;
6271 uint64_t tx_tstamp_cycles;
6274 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6275 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6278 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6279 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6280 *timestamp = rte_ns_to_timespec(ns);
6286 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6288 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6291 const struct reg_info *reg_group;
6292 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6293 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6295 while ((reg_group = reg_set[g_ind++]))
6296 count += ixgbe_regs_group_count(reg_group);
6302 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6306 const struct reg_info *reg_group;
6308 while ((reg_group = ixgbevf_regs[g_ind++]))
6309 count += ixgbe_regs_group_count(reg_group);
6315 ixgbe_get_regs(struct rte_eth_dev *dev,
6316 struct rte_dev_reg_info *regs)
6318 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6319 uint32_t *data = regs->data;
6322 const struct reg_info *reg_group;
6323 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6324 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6326 /* Support only full register dump */
6327 if ((regs->length == 0) ||
6328 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6329 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6331 while ((reg_group = reg_set[g_ind++]))
6332 count += ixgbe_read_regs_group(dev, &data[count],
6341 ixgbevf_get_regs(struct rte_eth_dev *dev,
6342 struct rte_dev_reg_info *regs)
6344 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6345 uint32_t *data = regs->data;
6348 const struct reg_info *reg_group;
6350 /* Support only full register dump */
6351 if ((regs->length == 0) ||
6352 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6353 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6355 while ((reg_group = ixgbevf_regs[g_ind++]))
6356 count += ixgbe_read_regs_group(dev, &data[count],
6365 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6367 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6369 /* Return unit is byte count */
6370 return hw->eeprom.word_size * 2;
6374 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6375 struct rte_dev_eeprom_info *in_eeprom)
6377 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6378 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6379 uint16_t *data = in_eeprom->data;
6382 first = in_eeprom->offset >> 1;
6383 length = in_eeprom->length >> 1;
6384 if ((first > hw->eeprom.word_size) ||
6385 ((first + length) > hw->eeprom.word_size))
6388 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6390 return eeprom->ops.read_buffer(hw, first, length, data);
6394 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6395 struct rte_dev_eeprom_info *in_eeprom)
6397 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6398 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6399 uint16_t *data = in_eeprom->data;
6402 first = in_eeprom->offset >> 1;
6403 length = in_eeprom->length >> 1;
6404 if ((first > hw->eeprom.word_size) ||
6405 ((first + length) > hw->eeprom.word_size))
6408 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6410 return eeprom->ops.write_buffer(hw, first, length, data);
6414 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6416 case ixgbe_mac_X550:
6417 case ixgbe_mac_X550EM_x:
6418 case ixgbe_mac_X550EM_a:
6419 return ETH_RSS_RETA_SIZE_512;
6420 case ixgbe_mac_X550_vf:
6421 case ixgbe_mac_X550EM_x_vf:
6422 case ixgbe_mac_X550EM_a_vf:
6423 return ETH_RSS_RETA_SIZE_64;
6425 return ETH_RSS_RETA_SIZE_128;
6430 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6432 case ixgbe_mac_X550:
6433 case ixgbe_mac_X550EM_x:
6434 case ixgbe_mac_X550EM_a:
6435 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6436 return IXGBE_RETA(reta_idx >> 2);
6438 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6439 case ixgbe_mac_X550_vf:
6440 case ixgbe_mac_X550EM_x_vf:
6441 case ixgbe_mac_X550EM_a_vf:
6442 return IXGBE_VFRETA(reta_idx >> 2);
6444 return IXGBE_RETA(reta_idx >> 2);
6449 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6451 case ixgbe_mac_X550_vf:
6452 case ixgbe_mac_X550EM_x_vf:
6453 case ixgbe_mac_X550EM_a_vf:
6454 return IXGBE_VFMRQC;
6461 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6463 case ixgbe_mac_X550_vf:
6464 case ixgbe_mac_X550EM_x_vf:
6465 case ixgbe_mac_X550EM_a_vf:
6466 return IXGBE_VFRSSRK(i);
6468 return IXGBE_RSSRK(i);
6473 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6475 case ixgbe_mac_82599_vf:
6476 case ixgbe_mac_X540_vf:
6484 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6485 struct rte_eth_dcb_info *dcb_info)
6487 struct ixgbe_dcb_config *dcb_config =
6488 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6489 struct ixgbe_dcb_tc_config *tc;
6492 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6493 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6495 dcb_info->nb_tcs = 1;
6497 if (dcb_config->vt_mode) { /* vt is enabled*/
6498 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6499 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6500 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6501 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6502 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6503 for (j = 0; j < dcb_info->nb_tcs; j++) {
6504 dcb_info->tc_queue.tc_rxq[i][j].base =
6505 i * dcb_info->nb_tcs + j;
6506 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6507 dcb_info->tc_queue.tc_txq[i][j].base =
6508 i * dcb_info->nb_tcs + j;
6509 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6512 } else { /* vt is disabled*/
6513 struct rte_eth_dcb_rx_conf *rx_conf =
6514 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6515 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6516 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6517 if (dcb_info->nb_tcs == ETH_4_TCS) {
6518 for (i = 0; i < dcb_info->nb_tcs; i++) {
6519 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6520 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6522 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6523 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6524 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6525 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6526 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6527 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6528 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6529 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6530 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6531 for (i = 0; i < dcb_info->nb_tcs; i++) {
6532 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6533 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6535 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6536 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6537 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6538 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6539 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6540 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6541 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6542 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6543 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6544 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6545 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6546 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6547 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6548 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6549 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6550 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6553 for (i = 0; i < dcb_info->nb_tcs; i++) {
6554 tc = &dcb_config->tc_config[i];
6555 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6560 /* Update e-tag ether type */
6562 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6563 uint16_t ether_type)
6565 uint32_t etag_etype;
6567 if (hw->mac.type != ixgbe_mac_X550 &&
6568 hw->mac.type != ixgbe_mac_X550EM_x &&
6569 hw->mac.type != ixgbe_mac_X550EM_a) {
6573 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6574 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6575 etag_etype |= ether_type;
6576 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6577 IXGBE_WRITE_FLUSH(hw);
6582 /* Config l2 tunnel ether type */
6584 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6585 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6588 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6590 if (l2_tunnel == NULL)
6593 switch (l2_tunnel->l2_tunnel_type) {
6594 case RTE_L2_TUNNEL_TYPE_E_TAG:
6595 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6598 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6606 /* Enable e-tag tunnel */
6608 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6610 uint32_t etag_etype;
6612 if (hw->mac.type != ixgbe_mac_X550 &&
6613 hw->mac.type != ixgbe_mac_X550EM_x &&
6614 hw->mac.type != ixgbe_mac_X550EM_a) {
6618 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6619 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6620 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6621 IXGBE_WRITE_FLUSH(hw);
6626 /* Enable l2 tunnel */
6628 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6629 enum rte_eth_tunnel_type l2_tunnel_type)
6632 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6634 switch (l2_tunnel_type) {
6635 case RTE_L2_TUNNEL_TYPE_E_TAG:
6636 ret = ixgbe_e_tag_enable(hw);
6639 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6647 /* Disable e-tag tunnel */
6649 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6651 uint32_t etag_etype;
6653 if (hw->mac.type != ixgbe_mac_X550 &&
6654 hw->mac.type != ixgbe_mac_X550EM_x &&
6655 hw->mac.type != ixgbe_mac_X550EM_a) {
6659 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6660 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6661 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6662 IXGBE_WRITE_FLUSH(hw);
6667 /* Disable l2 tunnel */
6669 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6670 enum rte_eth_tunnel_type l2_tunnel_type)
6673 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6675 switch (l2_tunnel_type) {
6676 case RTE_L2_TUNNEL_TYPE_E_TAG:
6677 ret = ixgbe_e_tag_disable(hw);
6680 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6689 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6690 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6693 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6694 uint32_t i, rar_entries;
6695 uint32_t rar_low, rar_high;
6697 if (hw->mac.type != ixgbe_mac_X550 &&
6698 hw->mac.type != ixgbe_mac_X550EM_x &&
6699 hw->mac.type != ixgbe_mac_X550EM_a) {
6703 rar_entries = ixgbe_get_num_rx_addrs(hw);
6705 for (i = 1; i < rar_entries; i++) {
6706 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6707 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6708 if ((rar_high & IXGBE_RAH_AV) &&
6709 (rar_high & IXGBE_RAH_ADTYPE) &&
6710 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6711 l2_tunnel->tunnel_id)) {
6712 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6713 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6715 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6725 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6726 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6729 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6730 uint32_t i, rar_entries;
6731 uint32_t rar_low, rar_high;
6733 if (hw->mac.type != ixgbe_mac_X550 &&
6734 hw->mac.type != ixgbe_mac_X550EM_x &&
6735 hw->mac.type != ixgbe_mac_X550EM_a) {
6739 /* One entry for one tunnel. Try to remove potential existing entry. */
6740 ixgbe_e_tag_filter_del(dev, l2_tunnel);
6742 rar_entries = ixgbe_get_num_rx_addrs(hw);
6744 for (i = 1; i < rar_entries; i++) {
6745 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6746 if (rar_high & IXGBE_RAH_AV) {
6749 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6750 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6751 rar_low = l2_tunnel->tunnel_id;
6753 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6754 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6760 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6761 " Please remove a rule before adding a new one.");
6765 /* Add l2 tunnel filter */
6767 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6768 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6772 switch (l2_tunnel->l2_tunnel_type) {
6773 case RTE_L2_TUNNEL_TYPE_E_TAG:
6774 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6777 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6785 /* Delete l2 tunnel filter */
6787 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6788 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6792 switch (l2_tunnel->l2_tunnel_type) {
6793 case RTE_L2_TUNNEL_TYPE_E_TAG:
6794 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6797 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6806 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6807 * @dev: pointer to rte_eth_dev structure
6808 * @filter_op:operation will be taken.
6809 * @arg: a pointer to specific structure corresponding to the filter_op
6812 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6813 enum rte_filter_op filter_op,
6818 if (filter_op == RTE_ETH_FILTER_NOP)
6822 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6827 switch (filter_op) {
6828 case RTE_ETH_FILTER_ADD:
6829 ret = ixgbe_dev_l2_tunnel_filter_add
6831 (struct rte_eth_l2_tunnel_conf *)arg);
6833 case RTE_ETH_FILTER_DELETE:
6834 ret = ixgbe_dev_l2_tunnel_filter_del
6836 (struct rte_eth_l2_tunnel_conf *)arg);
6839 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6847 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6851 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6853 if (hw->mac.type != ixgbe_mac_X550 &&
6854 hw->mac.type != ixgbe_mac_X550EM_x &&
6855 hw->mac.type != ixgbe_mac_X550EM_a) {
6859 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6860 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6862 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6863 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6868 /* Enable l2 tunnel forwarding */
6870 ixgbe_dev_l2_tunnel_forwarding_enable
6871 (struct rte_eth_dev *dev,
6872 enum rte_eth_tunnel_type l2_tunnel_type)
6876 switch (l2_tunnel_type) {
6877 case RTE_L2_TUNNEL_TYPE_E_TAG:
6878 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6881 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6889 /* Disable l2 tunnel forwarding */
6891 ixgbe_dev_l2_tunnel_forwarding_disable
6892 (struct rte_eth_dev *dev,
6893 enum rte_eth_tunnel_type l2_tunnel_type)
6897 switch (l2_tunnel_type) {
6898 case RTE_L2_TUNNEL_TYPE_E_TAG:
6899 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6902 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6911 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6912 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6916 uint32_t vmtir, vmvir;
6917 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6919 if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6921 "VF id %u should be less than %u",
6923 dev->pci_dev->max_vfs);
6927 if (hw->mac.type != ixgbe_mac_X550 &&
6928 hw->mac.type != ixgbe_mac_X550EM_x &&
6929 hw->mac.type != ixgbe_mac_X550EM_a) {
6934 vmtir = l2_tunnel->tunnel_id;
6938 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6940 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6941 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6943 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6944 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6949 /* Enable l2 tunnel tag insertion */
6951 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6952 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6956 switch (l2_tunnel->l2_tunnel_type) {
6957 case RTE_L2_TUNNEL_TYPE_E_TAG:
6958 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6961 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6969 /* Disable l2 tunnel tag insertion */
6971 ixgbe_dev_l2_tunnel_insertion_disable
6972 (struct rte_eth_dev *dev,
6973 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6977 switch (l2_tunnel->l2_tunnel_type) {
6978 case RTE_L2_TUNNEL_TYPE_E_TAG:
6979 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6982 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6991 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6996 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6998 if (hw->mac.type != ixgbe_mac_X550 &&
6999 hw->mac.type != ixgbe_mac_X550EM_x &&
7000 hw->mac.type != ixgbe_mac_X550EM_a) {
7004 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7006 qde |= IXGBE_QDE_STRIP_TAG;
7008 qde &= ~IXGBE_QDE_STRIP_TAG;
7009 qde &= ~IXGBE_QDE_READ;
7010 qde |= IXGBE_QDE_WRITE;
7011 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7016 /* Enable l2 tunnel tag stripping */
7018 ixgbe_dev_l2_tunnel_stripping_enable
7019 (struct rte_eth_dev *dev,
7020 enum rte_eth_tunnel_type l2_tunnel_type)
7024 switch (l2_tunnel_type) {
7025 case RTE_L2_TUNNEL_TYPE_E_TAG:
7026 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7029 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7037 /* Disable l2 tunnel tag stripping */
7039 ixgbe_dev_l2_tunnel_stripping_disable
7040 (struct rte_eth_dev *dev,
7041 enum rte_eth_tunnel_type l2_tunnel_type)
7045 switch (l2_tunnel_type) {
7046 case RTE_L2_TUNNEL_TYPE_E_TAG:
7047 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7050 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7058 /* Enable/disable l2 tunnel offload functions */
7060 ixgbe_dev_l2_tunnel_offload_set
7061 (struct rte_eth_dev *dev,
7062 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7068 if (l2_tunnel == NULL)
7072 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7074 ret = ixgbe_dev_l2_tunnel_enable(
7076 l2_tunnel->l2_tunnel_type);
7078 ret = ixgbe_dev_l2_tunnel_disable(
7080 l2_tunnel->l2_tunnel_type);
7083 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7085 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7089 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7094 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7096 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7098 l2_tunnel->l2_tunnel_type);
7100 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7102 l2_tunnel->l2_tunnel_type);
7105 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7107 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7109 l2_tunnel->l2_tunnel_type);
7111 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7113 l2_tunnel->l2_tunnel_type);
7120 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7123 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7124 IXGBE_WRITE_FLUSH(hw);
7129 /* There's only one register for VxLAN UDP port.
7130 * So, we cannot add several ports. Will update it.
7133 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7137 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7141 return ixgbe_update_vxlan_port(hw, port);
7144 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7145 * UDP port, it must have a value.
7146 * So, will reset it to the original value 0.
7149 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7154 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7156 if (cur_port != port) {
7157 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7161 return ixgbe_update_vxlan_port(hw, 0);
7164 /* Add UDP tunneling port */
7166 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7167 struct rte_eth_udp_tunnel *udp_tunnel)
7170 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7172 if (hw->mac.type != ixgbe_mac_X550 &&
7173 hw->mac.type != ixgbe_mac_X550EM_x &&
7174 hw->mac.type != ixgbe_mac_X550EM_a) {
7178 if (udp_tunnel == NULL)
7181 switch (udp_tunnel->prot_type) {
7182 case RTE_TUNNEL_TYPE_VXLAN:
7183 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7186 case RTE_TUNNEL_TYPE_GENEVE:
7187 case RTE_TUNNEL_TYPE_TEREDO:
7188 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7193 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7201 /* Remove UDP tunneling port */
7203 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7204 struct rte_eth_udp_tunnel *udp_tunnel)
7207 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7209 if (hw->mac.type != ixgbe_mac_X550 &&
7210 hw->mac.type != ixgbe_mac_X550EM_x &&
7211 hw->mac.type != ixgbe_mac_X550EM_a) {
7215 if (udp_tunnel == NULL)
7218 switch (udp_tunnel->prot_type) {
7219 case RTE_TUNNEL_TYPE_VXLAN:
7220 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7222 case RTE_TUNNEL_TYPE_GENEVE:
7223 case RTE_TUNNEL_TYPE_TEREDO:
7224 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7228 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7236 /* ixgbevf_update_xcast_mode - Update Multicast mode
7237 * @hw: pointer to the HW structure
7238 * @netdev: pointer to net device structure
7239 * @xcast_mode: new multicast mode
7241 * Updates the Multicast Mode of VF.
7243 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7246 struct ixgbe_mbx_info *mbx = &hw->mbx;
7250 switch (hw->api_version) {
7251 case ixgbe_mbox_api_12:
7257 msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7258 msgbuf[1] = xcast_mode;
7260 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7264 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7268 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7269 if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7276 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7278 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7280 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7284 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7286 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7288 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7291 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7293 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7296 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7299 /* PF reset VF event */
7300 if (in_msg == IXGBE_PF_CONTROL_MSG)
7301 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
7305 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7308 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7309 struct ixgbe_interrupt *intr =
7310 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7311 ixgbevf_intr_disable(hw);
7313 /* read-on-clear nic registers here */
7314 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7317 /* only one misc vector supported - mailbox */
7318 eicr &= IXGBE_VTEICR_MASK;
7319 if (eicr == IXGBE_MISC_VEC_ID)
7320 intr->flags |= IXGBE_FLAG_MAILBOX;
7326 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7328 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7329 struct ixgbe_interrupt *intr =
7330 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7332 if (intr->flags & IXGBE_FLAG_MAILBOX) {
7333 ixgbevf_mbx_process(dev);
7334 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7337 ixgbevf_intr_enable(hw);
7343 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7346 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7348 ixgbevf_dev_interrupt_get_status(dev);
7349 ixgbevf_dev_interrupt_action(dev);
7352 static struct rte_driver rte_ixgbe_driver = {
7354 .init = rte_ixgbe_pmd_init,
7357 static struct rte_driver rte_ixgbevf_driver = {
7359 .init = rte_ixgbevf_pmd_init,
7362 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7363 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);