1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_kvargs.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_hash_crc.h>
36 #ifdef RTE_LIB_SECURITY
37 #include <rte_security_driver.h>
40 #include "ixgbe_logs.h"
41 #include "base/ixgbe_api.h"
42 #include "base/ixgbe_vf.h"
43 #include "base/ixgbe_common.h"
44 #include "ixgbe_ethdev.h"
45 #include "ixgbe_bypass.h"
46 #include "ixgbe_rxtx.h"
47 #include "base/ixgbe_type.h"
48 #include "base/ixgbe_phy.h"
49 #include "ixgbe_regs.h"
52 * High threshold controlling when to start sending XOFF frames. Must be at
53 * least 8 bytes less than receive packet buffer size. This value is in units
56 #define IXGBE_FC_HI 0x80
59 * Low threshold controlling when to start sending XON frames. This value is
60 * in units of 1024 bytes.
62 #define IXGBE_FC_LO 0x40
64 /* Timer value included in XOFF frames. */
65 #define IXGBE_FC_PAUSE 0x680
67 /*Default value of Max Rx Queue*/
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
74 #define IXGBE_MMW_SIZE_DEFAULT 0x4
75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
79 * Default values for RX/TX configuration
81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
82 #define IXGBE_DEFAULT_RX_PTHRESH 8
83 #define IXGBE_DEFAULT_RX_HTHRESH 8
84 #define IXGBE_DEFAULT_RX_WTHRESH 0
86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
87 #define IXGBE_DEFAULT_TX_PTHRESH 32
88 #define IXGBE_DEFAULT_TX_HTHRESH 0
89 #define IXGBE_DEFAULT_TX_WTHRESH 0
90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
95 #define IXGBE_8_BIT_WIDTH CHAR_BIT
96 #define IXGBE_8_BIT_MASK UINT8_MAX
98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
102 /* Additional timesync values. */
103 #define NSEC_PER_SEC 1000000000L
104 #define IXGBE_INCVAL_10GB 0x66666666
105 #define IXGBE_INCVAL_1GB 0x40000000
106 #define IXGBE_INCVAL_100 0x50000000
107 #define IXGBE_INCVAL_SHIFT_10GB 28
108 #define IXGBE_INCVAL_SHIFT_1GB 24
109 #define IXGBE_INCVAL_SHIFT_100 21
110 #define IXGBE_INCVAL_SHIFT_82599 7
111 #define IXGBE_INCPER_SHIFT_82599 24
113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
117 #define IXGBE_ETAG_ETYPE 0x00005084
118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
120 #define IXGBE_RAH_ADTYPE 0x40000000
121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
125 #define IXGBE_QDE_STRIP_TAG 0x00000004
126 #define IXGBE_VTEICR_MASK 0x07
128 #define IXGBE_EXVET_VET_EXT_SHIFT 16
129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk"
133 static const char * const ixgbevf_valid_arguments[] = {
134 IXGBEVF_DEVARG_PFLINK_FULLCHK,
138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
157 int wait_to_complete);
158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
166 uint64_t *values, unsigned int n);
167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names, unsigned limit);
174 static int ixgbe_dev_xstats_get_names_by_id(
175 struct rte_eth_dev *dev,
176 struct rte_eth_xstat_name *xstats_names,
179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_fc_conf *fc_conf);
216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
217 struct rte_eth_pfc_conf *pfc_conf);
218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
222 struct rte_eth_rss_reta_entry64 *reta_conf,
224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
230 static void ixgbe_dev_interrupt_handler(void *param);
231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
234 uint32_t timeout_ms);
236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
237 struct rte_ether_addr *mac_addr,
238 uint32_t index, uint32_t pool);
239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
241 struct rte_ether_addr *mac_addr);
242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
243 static bool is_device_supported(struct rte_eth_dev *dev,
244 struct rte_pci_driver *drv);
246 /* For Virtual Function support */
247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
250 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
252 int wait_to_complete);
253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
255 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
262 uint16_t vlan_id, int on);
263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
264 uint16_t queue, int on);
265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
273 uint8_t queue, uint8_t msix_vector);
274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
280 /* For Eth VMDQ APIs support */
281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
282 rte_ether_addr * mac_addr, uint8_t on);
283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
285 struct rte_eth_mirror_conf *mirror_conf,
286 uint8_t rule_id, uint8_t on);
287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
294 uint8_t queue, uint8_t msix_vector);
295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
298 struct rte_ether_addr *mac_addr,
299 uint32_t index, uint32_t pool);
300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
302 struct rte_ether_addr *mac_addr);
303 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
304 struct ixgbe_5tuple_filter *filter);
305 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
306 struct ixgbe_5tuple_filter *filter);
307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
308 enum rte_filter_type filter_type,
309 enum rte_filter_op filter_op,
311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
314 struct rte_ether_addr *mc_addr_set,
315 uint32_t nb_mc_addr);
316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
317 struct rte_eth_dcb_info *dcb_info);
319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
320 static int ixgbe_get_regs(struct rte_eth_dev *dev,
321 struct rte_dev_reg_info *regs);
322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
324 struct rte_dev_eeprom_info *eeprom);
325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
326 struct rte_dev_eeprom_info *eeprom);
328 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
329 struct rte_eth_dev_module_info *modinfo);
330 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
331 struct rte_dev_eeprom_info *info);
333 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
334 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
335 struct rte_dev_reg_info *regs);
337 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
338 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
339 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
340 struct timespec *timestamp,
342 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
343 struct timespec *timestamp);
344 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
345 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
346 struct timespec *timestamp);
347 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
348 const struct timespec *timestamp);
349 static void ixgbevf_dev_interrupt_handler(void *param);
351 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
352 struct rte_eth_udp_tunnel *udp_tunnel);
353 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
354 struct rte_eth_udp_tunnel *udp_tunnel);
355 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
356 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
357 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
360 * Define VF Stats MACRO for Non "cleared on read" register
362 #define UPDATE_VF_STAT(reg, last, cur) \
364 uint32_t latest = IXGBE_READ_REG(hw, reg); \
365 cur += (latest - last) & UINT_MAX; \
369 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
371 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
372 u64 new_msb = IXGBE_READ_REG(hw, msb); \
373 u64 latest = ((new_msb << 32) | new_lsb); \
374 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
378 #define IXGBE_SET_HWSTRIP(h, q) do {\
379 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
380 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
381 (h)->bitmap[idx] |= 1 << bit;\
384 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
385 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
386 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
387 (h)->bitmap[idx] &= ~(1 << bit);\
390 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
391 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
392 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
393 (r) = (h)->bitmap[idx] >> bit & 1;\
397 * The set of PCI devices this driver supports
399 static const struct rte_pci_id pci_id_ixgbe_map[] = {
400 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
401 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
402 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
403 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
404 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
405 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
406 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
407 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
408 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
409 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
410 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
411 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
412 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
448 #ifdef RTE_LIBRTE_IXGBE_BYPASS
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
451 { .vendor_id = 0, /* sentinel */ },
455 * The set of PCI devices this driver supports (for 82599 VF)
457 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
468 { .vendor_id = 0, /* sentinel */ },
471 static const struct rte_eth_desc_lim rx_desc_lim = {
472 .nb_max = IXGBE_MAX_RING_DESC,
473 .nb_min = IXGBE_MIN_RING_DESC,
474 .nb_align = IXGBE_RXD_ALIGN,
477 static const struct rte_eth_desc_lim tx_desc_lim = {
478 .nb_max = IXGBE_MAX_RING_DESC,
479 .nb_min = IXGBE_MIN_RING_DESC,
480 .nb_align = IXGBE_TXD_ALIGN,
481 .nb_seg_max = IXGBE_TX_MAX_SEG,
482 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
485 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
486 .dev_configure = ixgbe_dev_configure,
487 .dev_start = ixgbe_dev_start,
488 .dev_stop = ixgbe_dev_stop,
489 .dev_set_link_up = ixgbe_dev_set_link_up,
490 .dev_set_link_down = ixgbe_dev_set_link_down,
491 .dev_close = ixgbe_dev_close,
492 .dev_reset = ixgbe_dev_reset,
493 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
494 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
495 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
496 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
497 .link_update = ixgbe_dev_link_update,
498 .stats_get = ixgbe_dev_stats_get,
499 .xstats_get = ixgbe_dev_xstats_get,
500 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
501 .stats_reset = ixgbe_dev_stats_reset,
502 .xstats_reset = ixgbe_dev_xstats_reset,
503 .xstats_get_names = ixgbe_dev_xstats_get_names,
504 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
505 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
506 .fw_version_get = ixgbe_fw_version_get,
507 .dev_infos_get = ixgbe_dev_info_get,
508 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
509 .mtu_set = ixgbe_dev_mtu_set,
510 .vlan_filter_set = ixgbe_vlan_filter_set,
511 .vlan_tpid_set = ixgbe_vlan_tpid_set,
512 .vlan_offload_set = ixgbe_vlan_offload_set,
513 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
514 .rx_queue_start = ixgbe_dev_rx_queue_start,
515 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
516 .tx_queue_start = ixgbe_dev_tx_queue_start,
517 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
518 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
519 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
520 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
521 .rx_queue_release = ixgbe_dev_rx_queue_release,
522 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
523 .tx_queue_release = ixgbe_dev_tx_queue_release,
524 .dev_led_on = ixgbe_dev_led_on,
525 .dev_led_off = ixgbe_dev_led_off,
526 .flow_ctrl_get = ixgbe_flow_ctrl_get,
527 .flow_ctrl_set = ixgbe_flow_ctrl_set,
528 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
529 .mac_addr_add = ixgbe_add_rar,
530 .mac_addr_remove = ixgbe_remove_rar,
531 .mac_addr_set = ixgbe_set_default_mac_addr,
532 .uc_hash_table_set = ixgbe_uc_hash_table_set,
533 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
534 .mirror_rule_set = ixgbe_mirror_rule_set,
535 .mirror_rule_reset = ixgbe_mirror_rule_reset,
536 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
537 .reta_update = ixgbe_dev_rss_reta_update,
538 .reta_query = ixgbe_dev_rss_reta_query,
539 .rss_hash_update = ixgbe_dev_rss_hash_update,
540 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
541 .filter_ctrl = ixgbe_dev_filter_ctrl,
542 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
543 .rxq_info_get = ixgbe_rxq_info_get,
544 .txq_info_get = ixgbe_txq_info_get,
545 .timesync_enable = ixgbe_timesync_enable,
546 .timesync_disable = ixgbe_timesync_disable,
547 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
548 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
549 .get_reg = ixgbe_get_regs,
550 .get_eeprom_length = ixgbe_get_eeprom_length,
551 .get_eeprom = ixgbe_get_eeprom,
552 .set_eeprom = ixgbe_set_eeprom,
553 .get_module_info = ixgbe_get_module_info,
554 .get_module_eeprom = ixgbe_get_module_eeprom,
555 .get_dcb_info = ixgbe_dev_get_dcb_info,
556 .timesync_adjust_time = ixgbe_timesync_adjust_time,
557 .timesync_read_time = ixgbe_timesync_read_time,
558 .timesync_write_time = ixgbe_timesync_write_time,
559 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
560 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
561 .tm_ops_get = ixgbe_tm_ops_get,
562 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
566 * dev_ops for virtual function, bare necessities for basic vf
567 * operation have been implemented
569 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
570 .dev_configure = ixgbevf_dev_configure,
571 .dev_start = ixgbevf_dev_start,
572 .dev_stop = ixgbevf_dev_stop,
573 .link_update = ixgbevf_dev_link_update,
574 .stats_get = ixgbevf_dev_stats_get,
575 .xstats_get = ixgbevf_dev_xstats_get,
576 .stats_reset = ixgbevf_dev_stats_reset,
577 .xstats_reset = ixgbevf_dev_stats_reset,
578 .xstats_get_names = ixgbevf_dev_xstats_get_names,
579 .dev_close = ixgbevf_dev_close,
580 .dev_reset = ixgbevf_dev_reset,
581 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
582 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
583 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
584 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
585 .dev_infos_get = ixgbevf_dev_info_get,
586 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
587 .mtu_set = ixgbevf_dev_set_mtu,
588 .vlan_filter_set = ixgbevf_vlan_filter_set,
589 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
590 .vlan_offload_set = ixgbevf_vlan_offload_set,
591 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
592 .rx_queue_release = ixgbe_dev_rx_queue_release,
593 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
594 .tx_queue_release = ixgbe_dev_tx_queue_release,
595 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
596 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
597 .mac_addr_add = ixgbevf_add_mac_addr,
598 .mac_addr_remove = ixgbevf_remove_mac_addr,
599 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
600 .rxq_info_get = ixgbe_rxq_info_get,
601 .txq_info_get = ixgbe_txq_info_get,
602 .mac_addr_set = ixgbevf_set_default_mac_addr,
603 .get_reg = ixgbevf_get_regs,
604 .reta_update = ixgbe_dev_rss_reta_update,
605 .reta_query = ixgbe_dev_rss_reta_query,
606 .rss_hash_update = ixgbe_dev_rss_hash_update,
607 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
608 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
611 /* store statistics names and its offset in stats structure */
612 struct rte_ixgbe_xstats_name_off {
613 char name[RTE_ETH_XSTATS_NAME_SIZE];
617 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
618 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
619 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
620 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
621 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
622 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
623 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
624 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
625 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
626 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
627 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
628 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
629 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
630 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
631 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
632 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
634 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
636 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
637 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
638 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
639 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
640 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
641 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
642 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
643 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
644 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
645 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
646 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
647 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
648 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
649 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
650 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
651 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
652 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
654 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
656 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
657 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
658 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
659 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
661 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
663 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
665 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
667 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
669 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
671 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
674 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
675 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
676 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
678 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
679 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
680 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
681 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
682 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
684 {"rx_fcoe_no_direct_data_placement_ext_buff",
685 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
687 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
689 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
691 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
693 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
695 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
698 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
699 sizeof(rte_ixgbe_stats_strings[0]))
701 /* MACsec statistics */
702 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
703 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
705 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
706 out_pkts_encrypted)},
707 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
708 out_pkts_protected)},
709 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
710 out_octets_encrypted)},
711 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
712 out_octets_protected)},
713 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
715 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
717 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
719 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
720 in_pkts_unknownsci)},
721 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
722 in_octets_decrypted)},
723 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
724 in_octets_validated)},
725 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
727 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
729 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
731 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
733 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
735 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
737 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
739 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
740 in_pkts_notusingsa)},
743 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
744 sizeof(rte_ixgbe_macsec_strings[0]))
746 /* Per-queue statistics */
747 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
748 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
749 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
750 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
751 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
754 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
755 sizeof(rte_ixgbe_rxq_strings[0]))
756 #define IXGBE_NB_RXQ_PRIO_VALUES 8
758 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
759 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
760 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
761 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
765 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
766 sizeof(rte_ixgbe_txq_strings[0]))
767 #define IXGBE_NB_TXQ_PRIO_VALUES 8
769 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
770 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
773 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
774 sizeof(rte_ixgbevf_stats_strings[0]))
777 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
780 ixgbe_is_sfp(struct ixgbe_hw *hw)
782 switch (hw->phy.type) {
783 case ixgbe_phy_sfp_avago:
784 case ixgbe_phy_sfp_ftl:
785 case ixgbe_phy_sfp_intel:
786 case ixgbe_phy_sfp_unknown:
787 case ixgbe_phy_sfp_passive_tyco:
788 case ixgbe_phy_sfp_passive_unknown:
795 static inline int32_t
796 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
801 status = ixgbe_reset_hw(hw);
803 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
804 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
805 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
806 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
807 IXGBE_WRITE_FLUSH(hw);
809 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
810 status = IXGBE_SUCCESS;
815 ixgbe_enable_intr(struct rte_eth_dev *dev)
817 struct ixgbe_interrupt *intr =
818 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
819 struct ixgbe_hw *hw =
820 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
822 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
823 IXGBE_WRITE_FLUSH(hw);
827 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
830 ixgbe_disable_intr(struct ixgbe_hw *hw)
832 PMD_INIT_FUNC_TRACE();
834 if (hw->mac.type == ixgbe_mac_82598EB) {
835 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
837 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
838 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
839 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
841 IXGBE_WRITE_FLUSH(hw);
845 * This function resets queue statistics mapping registers.
846 * From Niantic datasheet, Initialization of Statistics section:
847 * "...if software requires the queue counters, the RQSMR and TQSM registers
848 * must be re-programmed following a device reset.
851 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
855 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
856 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
857 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
863 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
868 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
869 #define NB_QMAP_FIELDS_PER_QSM_REG 4
870 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
872 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
873 struct ixgbe_stat_mapping_registers *stat_mappings =
874 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
875 uint32_t qsmr_mask = 0;
876 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
880 if ((hw->mac.type != ixgbe_mac_82599EB) &&
881 (hw->mac.type != ixgbe_mac_X540) &&
882 (hw->mac.type != ixgbe_mac_X550) &&
883 (hw->mac.type != ixgbe_mac_X550EM_x) &&
884 (hw->mac.type != ixgbe_mac_X550EM_a))
887 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
888 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
891 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
892 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
893 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
896 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
898 /* Now clear any previous stat_idx set */
899 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
901 stat_mappings->tqsm[n] &= ~clearing_mask;
903 stat_mappings->rqsmr[n] &= ~clearing_mask;
905 q_map = (uint32_t)stat_idx;
906 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
907 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
909 stat_mappings->tqsm[n] |= qsmr_mask;
911 stat_mappings->rqsmr[n] |= qsmr_mask;
913 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
914 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
916 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
917 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
919 /* Now write the mapping in the appropriate register */
921 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
922 stat_mappings->rqsmr[n], n);
923 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
925 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
926 stat_mappings->tqsm[n], n);
927 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
933 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
935 struct ixgbe_stat_mapping_registers *stat_mappings =
936 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
937 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
940 /* write whatever was in stat mapping table to the NIC */
941 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
943 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
946 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
951 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
954 struct ixgbe_dcb_tc_config *tc;
955 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
957 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
958 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
959 for (i = 0; i < dcb_max_tc; i++) {
960 tc = &dcb_config->tc_config[i];
961 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
962 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
963 (uint8_t)(100/dcb_max_tc + (i & 1));
964 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
965 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
966 (uint8_t)(100/dcb_max_tc + (i & 1));
967 tc->pfc = ixgbe_dcb_pfc_disabled;
970 /* Initialize default user to priority mapping, UPx->TC0 */
971 tc = &dcb_config->tc_config[0];
972 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
973 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
974 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
975 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
976 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
978 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
979 dcb_config->pfc_mode_enable = false;
980 dcb_config->vt_mode = true;
981 dcb_config->round_robin_enable = false;
982 /* support all DCB capabilities in 82599 */
983 dcb_config->support.capabilities = 0xFF;
985 /*we only support 4 Tcs for X540, X550 */
986 if (hw->mac.type == ixgbe_mac_X540 ||
987 hw->mac.type == ixgbe_mac_X550 ||
988 hw->mac.type == ixgbe_mac_X550EM_x ||
989 hw->mac.type == ixgbe_mac_X550EM_a) {
990 dcb_config->num_tcs.pg_tcs = 4;
991 dcb_config->num_tcs.pfc_tcs = 4;
996 * Ensure that all locks are released before first NVM or PHY access
999 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1004 * Phy lock should not fail in this early stage. If this is the case,
1005 * it is due to an improper exit of the application.
1006 * So force the release of the faulty lock. Release of common lock
1007 * is done automatically by swfw_sync function.
1009 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1010 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1011 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1013 ixgbe_release_swfw_semaphore(hw, mask);
1016 * These ones are more tricky since they are common to all ports; but
1017 * swfw_sync retries last long enough (1s) to be almost sure that if
1018 * lock can not be taken it is due to an improper lock of the
1021 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1022 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1023 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1025 ixgbe_release_swfw_semaphore(hw, mask);
1029 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1030 * It returns 0 on success.
1033 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1035 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1036 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1037 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1038 struct ixgbe_hw *hw =
1039 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1040 struct ixgbe_vfta *shadow_vfta =
1041 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1042 struct ixgbe_hwstrip *hwstrip =
1043 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1044 struct ixgbe_dcb_config *dcb_config =
1045 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1046 struct ixgbe_filter_info *filter_info =
1047 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1048 struct ixgbe_bw_conf *bw_conf =
1049 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1054 PMD_INIT_FUNC_TRACE();
1056 ixgbe_dev_macsec_setting_reset(eth_dev);
1058 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1059 eth_dev->rx_queue_count = ixgbe_dev_rx_queue_count;
1060 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done;
1061 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1062 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1063 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1064 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1065 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1068 * For secondary processes, we don't initialise any further as primary
1069 * has already done this work. Only check we don't need a different
1070 * RX and TX function.
1072 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1073 struct ixgbe_tx_queue *txq;
1074 /* TX queue function in primary, set by last queue initialized
1075 * Tx queue may not initialized by primary process
1077 if (eth_dev->data->tx_queues) {
1078 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1079 ixgbe_set_tx_function(eth_dev, txq);
1081 /* Use default TX function if we get here */
1082 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1083 "Using default TX function.");
1086 ixgbe_set_rx_function(eth_dev);
1091 rte_atomic32_clear(&ad->link_thread_running);
1092 rte_eth_copy_pci_info(eth_dev, pci_dev);
1093 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1095 /* Vendor and Device ID need to be set before init of shared code */
1096 hw->device_id = pci_dev->id.device_id;
1097 hw->vendor_id = pci_dev->id.vendor_id;
1098 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1099 hw->allow_unsupported_sfp = 1;
1101 /* Initialize the shared code (base driver) */
1102 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1103 diag = ixgbe_bypass_init_shared_code(hw);
1105 diag = ixgbe_init_shared_code(hw);
1106 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1108 if (diag != IXGBE_SUCCESS) {
1109 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1113 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1114 PMD_INIT_LOG(ERR, "\nERROR: "
1115 "Firmware recovery mode detected. Limiting functionality.\n"
1116 "Refer to the Intel(R) Ethernet Adapters and Devices "
1117 "User Guide for details on firmware recovery mode.");
1121 /* pick up the PCI bus settings for reporting later */
1122 ixgbe_get_bus_info(hw);
1124 /* Unlock any pending hardware semaphore */
1125 ixgbe_swfw_lock_reset(hw);
1127 #ifdef RTE_LIB_SECURITY
1128 /* Initialize security_ctx only for primary process*/
1129 if (ixgbe_ipsec_ctx_create(eth_dev))
1133 /* Initialize DCB configuration*/
1134 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1135 ixgbe_dcb_init(hw, dcb_config);
1136 /* Get Hardware Flow Control setting */
1137 hw->fc.requested_mode = ixgbe_fc_none;
1138 hw->fc.current_mode = ixgbe_fc_none;
1139 hw->fc.pause_time = IXGBE_FC_PAUSE;
1140 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1141 hw->fc.low_water[i] = IXGBE_FC_LO;
1142 hw->fc.high_water[i] = IXGBE_FC_HI;
1144 hw->fc.send_xon = 1;
1146 /* Make sure we have a good EEPROM before we read from it */
1147 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1148 if (diag != IXGBE_SUCCESS) {
1149 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1153 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1154 diag = ixgbe_bypass_init_hw(hw);
1156 diag = ixgbe_init_hw(hw);
1157 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1160 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1161 * is called too soon after the kernel driver unbinding/binding occurs.
1162 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1163 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1164 * also called. See ixgbe_identify_phy_82599(). The reason for the
1165 * failure is not known, and only occuts when virtualisation features
1166 * are disabled in the bios. A delay of 100ms was found to be enough by
1167 * trial-and-error, and is doubled to be safe.
1169 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1171 diag = ixgbe_init_hw(hw);
1174 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1175 diag = IXGBE_SUCCESS;
1177 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1178 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1179 "LOM. Please be aware there may be issues associated "
1180 "with your hardware.");
1181 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1182 "please contact your Intel or hardware representative "
1183 "who provided you with this hardware.");
1184 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1185 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1187 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1191 /* Reset the hw statistics */
1192 ixgbe_dev_stats_reset(eth_dev);
1194 /* disable interrupt */
1195 ixgbe_disable_intr(hw);
1197 /* reset mappings for queue statistics hw counters*/
1198 ixgbe_reset_qstat_mappings(hw);
1200 /* Allocate memory for storing MAC addresses */
1201 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1202 hw->mac.num_rar_entries, 0);
1203 if (eth_dev->data->mac_addrs == NULL) {
1205 "Failed to allocate %u bytes needed to store "
1207 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1210 /* Copy the permanent MAC address */
1211 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1212 ð_dev->data->mac_addrs[0]);
1214 /* Allocate memory for storing hash filter MAC addresses */
1215 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1216 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1217 if (eth_dev->data->hash_mac_addrs == NULL) {
1219 "Failed to allocate %d bytes needed to store MAC addresses",
1220 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1224 /* initialize the vfta */
1225 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1227 /* initialize the hw strip bitmap*/
1228 memset(hwstrip, 0, sizeof(*hwstrip));
1230 /* initialize PF if max_vfs not zero */
1231 ret = ixgbe_pf_host_init(eth_dev);
1233 rte_free(eth_dev->data->mac_addrs);
1234 eth_dev->data->mac_addrs = NULL;
1235 rte_free(eth_dev->data->hash_mac_addrs);
1236 eth_dev->data->hash_mac_addrs = NULL;
1240 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1241 /* let hardware know driver is loaded */
1242 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1243 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1244 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1245 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1246 IXGBE_WRITE_FLUSH(hw);
1248 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1249 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1250 (int) hw->mac.type, (int) hw->phy.type,
1251 (int) hw->phy.sfp_type);
1253 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1254 (int) hw->mac.type, (int) hw->phy.type);
1256 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1257 eth_dev->data->port_id, pci_dev->id.vendor_id,
1258 pci_dev->id.device_id);
1260 rte_intr_callback_register(intr_handle,
1261 ixgbe_dev_interrupt_handler, eth_dev);
1263 /* enable uio/vfio intr/eventfd mapping */
1264 rte_intr_enable(intr_handle);
1266 /* enable support intr */
1267 ixgbe_enable_intr(eth_dev);
1269 /* initialize filter info */
1270 memset(filter_info, 0,
1271 sizeof(struct ixgbe_filter_info));
1273 /* initialize 5tuple filter list */
1274 TAILQ_INIT(&filter_info->fivetuple_list);
1276 /* initialize flow director filter list & hash */
1277 ixgbe_fdir_filter_init(eth_dev);
1279 /* initialize l2 tunnel filter list & hash */
1280 ixgbe_l2_tn_filter_init(eth_dev);
1282 /* initialize flow filter lists */
1283 ixgbe_filterlist_init();
1285 /* initialize bandwidth configuration info */
1286 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1288 /* initialize Traffic Manager configuration */
1289 ixgbe_tm_conf_init(eth_dev);
1295 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1297 PMD_INIT_FUNC_TRACE();
1299 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1302 ixgbe_dev_close(eth_dev);
1307 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1309 struct ixgbe_filter_info *filter_info =
1310 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1311 struct ixgbe_5tuple_filter *p_5tuple;
1313 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1314 TAILQ_REMOVE(&filter_info->fivetuple_list,
1319 memset(filter_info->fivetuple_mask, 0,
1320 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1325 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1327 struct ixgbe_hw_fdir_info *fdir_info =
1328 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1329 struct ixgbe_fdir_filter *fdir_filter;
1331 if (fdir_info->hash_map)
1332 rte_free(fdir_info->hash_map);
1333 if (fdir_info->hash_handle)
1334 rte_hash_free(fdir_info->hash_handle);
1336 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1337 TAILQ_REMOVE(&fdir_info->fdir_list,
1340 rte_free(fdir_filter);
1346 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1348 struct ixgbe_l2_tn_info *l2_tn_info =
1349 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1350 struct ixgbe_l2_tn_filter *l2_tn_filter;
1352 if (l2_tn_info->hash_map)
1353 rte_free(l2_tn_info->hash_map);
1354 if (l2_tn_info->hash_handle)
1355 rte_hash_free(l2_tn_info->hash_handle);
1357 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1358 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1361 rte_free(l2_tn_filter);
1367 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1369 struct ixgbe_hw_fdir_info *fdir_info =
1370 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1371 char fdir_hash_name[RTE_HASH_NAMESIZE];
1372 struct rte_hash_parameters fdir_hash_params = {
1373 .name = fdir_hash_name,
1374 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1375 .key_len = sizeof(union ixgbe_atr_input),
1376 .hash_func = rte_hash_crc,
1377 .hash_func_init_val = 0,
1378 .socket_id = rte_socket_id(),
1381 TAILQ_INIT(&fdir_info->fdir_list);
1382 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1383 "fdir_%s", eth_dev->device->name);
1384 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1385 if (!fdir_info->hash_handle) {
1386 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1389 fdir_info->hash_map = rte_zmalloc("ixgbe",
1390 sizeof(struct ixgbe_fdir_filter *) *
1391 IXGBE_MAX_FDIR_FILTER_NUM,
1393 if (!fdir_info->hash_map) {
1395 "Failed to allocate memory for fdir hash map!");
1398 fdir_info->mask_added = FALSE;
1403 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1405 struct ixgbe_l2_tn_info *l2_tn_info =
1406 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1407 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1408 struct rte_hash_parameters l2_tn_hash_params = {
1409 .name = l2_tn_hash_name,
1410 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1411 .key_len = sizeof(struct ixgbe_l2_tn_key),
1412 .hash_func = rte_hash_crc,
1413 .hash_func_init_val = 0,
1414 .socket_id = rte_socket_id(),
1417 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1418 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1419 "l2_tn_%s", eth_dev->device->name);
1420 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1421 if (!l2_tn_info->hash_handle) {
1422 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1425 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1426 sizeof(struct ixgbe_l2_tn_filter *) *
1427 IXGBE_MAX_L2_TN_FILTER_NUM,
1429 if (!l2_tn_info->hash_map) {
1431 "Failed to allocate memory for L2 TN hash map!");
1434 l2_tn_info->e_tag_en = FALSE;
1435 l2_tn_info->e_tag_fwd_en = FALSE;
1436 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1441 * Negotiate mailbox API version with the PF.
1442 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1443 * Then we try to negotiate starting with the most recent one.
1444 * If all negotiation attempts fail, then we will proceed with
1445 * the default one (ixgbe_mbox_api_10).
1448 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1452 /* start with highest supported, proceed down */
1453 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1461 i != RTE_DIM(sup_ver) &&
1462 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1468 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1472 /* Set Organizationally Unique Identifier (OUI) prefix. */
1473 mac_addr->addr_bytes[0] = 0x00;
1474 mac_addr->addr_bytes[1] = 0x09;
1475 mac_addr->addr_bytes[2] = 0xC0;
1476 /* Force indication of locally assigned MAC address. */
1477 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1478 /* Generate the last 3 bytes of the MAC address with a random number. */
1479 random = rte_rand();
1480 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1484 devarg_handle_int(__rte_unused const char *key, const char *value,
1487 uint16_t *n = extra_args;
1489 if (value == NULL || extra_args == NULL)
1492 *n = (uint16_t)strtoul(value, NULL, 0);
1493 if (*n == USHRT_MAX && errno == ERANGE)
1500 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1501 struct rte_devargs *devargs)
1503 struct rte_kvargs *kvlist;
1504 uint16_t pflink_fullchk;
1506 if (devargs == NULL)
1509 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1513 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1514 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1515 devarg_handle_int, &pflink_fullchk) == 0 &&
1516 pflink_fullchk == 1)
1517 adapter->pflink_fullchk = 1;
1519 rte_kvargs_free(kvlist);
1523 * Virtual Function device init
1526 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1530 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1531 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1532 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1533 struct ixgbe_hw *hw =
1534 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1535 struct ixgbe_vfta *shadow_vfta =
1536 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1537 struct ixgbe_hwstrip *hwstrip =
1538 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1539 struct rte_ether_addr *perm_addr =
1540 (struct rte_ether_addr *)hw->mac.perm_addr;
1542 PMD_INIT_FUNC_TRACE();
1544 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1545 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done;
1546 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1547 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1548 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1549 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1551 /* for secondary processes, we don't initialise any further as primary
1552 * has already done this work. Only check we don't need a different
1555 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1556 struct ixgbe_tx_queue *txq;
1557 /* TX queue function in primary, set by last queue initialized
1558 * Tx queue may not initialized by primary process
1560 if (eth_dev->data->tx_queues) {
1561 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1562 ixgbe_set_tx_function(eth_dev, txq);
1564 /* Use default TX function if we get here */
1565 PMD_INIT_LOG(NOTICE,
1566 "No TX queues configured yet. Using default TX function.");
1569 ixgbe_set_rx_function(eth_dev);
1574 rte_atomic32_clear(&ad->link_thread_running);
1575 ixgbevf_parse_devargs(eth_dev->data->dev_private,
1576 pci_dev->device.devargs);
1578 rte_eth_copy_pci_info(eth_dev, pci_dev);
1579 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1581 hw->device_id = pci_dev->id.device_id;
1582 hw->vendor_id = pci_dev->id.vendor_id;
1583 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1585 /* initialize the vfta */
1586 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1588 /* initialize the hw strip bitmap*/
1589 memset(hwstrip, 0, sizeof(*hwstrip));
1591 /* Initialize the shared code (base driver) */
1592 diag = ixgbe_init_shared_code(hw);
1593 if (diag != IXGBE_SUCCESS) {
1594 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1598 /* init_mailbox_params */
1599 hw->mbx.ops.init_params(hw);
1601 /* Reset the hw statistics */
1602 ixgbevf_dev_stats_reset(eth_dev);
1604 /* Disable the interrupts for VF */
1605 ixgbevf_intr_disable(eth_dev);
1607 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1608 diag = hw->mac.ops.reset_hw(hw);
1611 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1612 * the underlying PF driver has not assigned a MAC address to the VF.
1613 * In this case, assign a random MAC address.
1615 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1616 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1618 * This error code will be propagated to the app by
1619 * rte_eth_dev_reset, so use a public error code rather than
1620 * the internal-only IXGBE_ERR_RESET_FAILED
1625 /* negotiate mailbox API version to use with the PF. */
1626 ixgbevf_negotiate_api(hw);
1628 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1629 ixgbevf_get_queues(hw, &tcs, &tc);
1631 /* Allocate memory for storing MAC addresses */
1632 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1633 hw->mac.num_rar_entries, 0);
1634 if (eth_dev->data->mac_addrs == NULL) {
1636 "Failed to allocate %u bytes needed to store "
1638 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1642 /* Generate a random MAC address, if none was assigned by PF. */
1643 if (rte_is_zero_ether_addr(perm_addr)) {
1644 generate_random_mac_addr(perm_addr);
1645 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1647 rte_free(eth_dev->data->mac_addrs);
1648 eth_dev->data->mac_addrs = NULL;
1651 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1652 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1653 "%02x:%02x:%02x:%02x:%02x:%02x",
1654 perm_addr->addr_bytes[0],
1655 perm_addr->addr_bytes[1],
1656 perm_addr->addr_bytes[2],
1657 perm_addr->addr_bytes[3],
1658 perm_addr->addr_bytes[4],
1659 perm_addr->addr_bytes[5]);
1662 /* Copy the permanent MAC address */
1663 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1665 /* reset the hardware with the new settings */
1666 diag = hw->mac.ops.start_hw(hw);
1672 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1676 rte_intr_callback_register(intr_handle,
1677 ixgbevf_dev_interrupt_handler, eth_dev);
1678 rte_intr_enable(intr_handle);
1679 ixgbevf_intr_enable(eth_dev);
1681 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1682 eth_dev->data->port_id, pci_dev->id.vendor_id,
1683 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1688 /* Virtual Function device uninit */
1691 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1693 PMD_INIT_FUNC_TRACE();
1695 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1698 ixgbevf_dev_close(eth_dev);
1704 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1705 struct rte_pci_device *pci_dev)
1707 char name[RTE_ETH_NAME_MAX_LEN];
1708 struct rte_eth_dev *pf_ethdev;
1709 struct rte_eth_devargs eth_da;
1712 if (pci_dev->device.devargs) {
1713 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1718 memset(ð_da, 0, sizeof(eth_da));
1720 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1721 sizeof(struct ixgbe_adapter),
1722 eth_dev_pci_specific_init, pci_dev,
1723 eth_ixgbe_dev_init, NULL);
1725 if (retval || eth_da.nb_representor_ports < 1)
1728 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1729 if (pf_ethdev == NULL)
1732 /* probe VF representor ports */
1733 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1734 struct ixgbe_vf_info *vfinfo;
1735 struct ixgbe_vf_representor representor;
1737 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1738 pf_ethdev->data->dev_private);
1739 if (vfinfo == NULL) {
1741 "no virtual functions supported by PF");
1745 representor.vf_id = eth_da.representor_ports[i];
1746 representor.switch_domain_id = vfinfo->switch_domain_id;
1747 representor.pf_ethdev = pf_ethdev;
1749 /* representor port net_bdf_port */
1750 snprintf(name, sizeof(name), "net_%s_representor_%d",
1751 pci_dev->device.name,
1752 eth_da.representor_ports[i]);
1754 retval = rte_eth_dev_create(&pci_dev->device, name,
1755 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1756 ixgbe_vf_representor_init, &representor);
1759 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1760 "representor %s.", name);
1766 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1768 struct rte_eth_dev *ethdev;
1770 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1774 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1775 return rte_eth_dev_pci_generic_remove(pci_dev,
1776 ixgbe_vf_representor_uninit);
1778 return rte_eth_dev_pci_generic_remove(pci_dev,
1779 eth_ixgbe_dev_uninit);
1782 static struct rte_pci_driver rte_ixgbe_pmd = {
1783 .id_table = pci_id_ixgbe_map,
1784 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1785 .probe = eth_ixgbe_pci_probe,
1786 .remove = eth_ixgbe_pci_remove,
1789 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1790 struct rte_pci_device *pci_dev)
1792 return rte_eth_dev_pci_generic_probe(pci_dev,
1793 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1796 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1798 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1802 * virtual function driver struct
1804 static struct rte_pci_driver rte_ixgbevf_pmd = {
1805 .id_table = pci_id_ixgbevf_map,
1806 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1807 .probe = eth_ixgbevf_pci_probe,
1808 .remove = eth_ixgbevf_pci_remove,
1812 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1814 struct ixgbe_hw *hw =
1815 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816 struct ixgbe_vfta *shadow_vfta =
1817 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1822 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1823 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1824 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1829 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1831 /* update local VFTA copy */
1832 shadow_vfta->vfta[vid_idx] = vfta;
1838 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1841 ixgbe_vlan_hw_strip_enable(dev, queue);
1843 ixgbe_vlan_hw_strip_disable(dev, queue);
1847 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1848 enum rte_vlan_type vlan_type,
1851 struct ixgbe_hw *hw =
1852 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1858 qinq &= IXGBE_DMATXCTL_GDV;
1860 switch (vlan_type) {
1861 case ETH_VLAN_TYPE_INNER:
1863 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1864 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1865 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1866 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1868 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1869 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1872 PMD_DRV_LOG(ERR, "Inner type is not supported"
1876 case ETH_VLAN_TYPE_OUTER:
1878 /* Only the high 16-bits is valid */
1879 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1880 IXGBE_EXVET_VET_EXT_SHIFT);
1882 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1894 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1902 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1904 struct ixgbe_hw *hw =
1905 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1908 PMD_INIT_FUNC_TRACE();
1910 /* Filter Table Disable */
1911 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1914 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1918 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1920 struct ixgbe_hw *hw =
1921 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922 struct ixgbe_vfta *shadow_vfta =
1923 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1927 PMD_INIT_FUNC_TRACE();
1929 /* Filter Table Enable */
1930 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1932 vlnctrl |= IXGBE_VLNCTRL_VFE;
1934 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1936 /* write whatever is in local vfta copy */
1937 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1938 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1942 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1944 struct ixgbe_hwstrip *hwstrip =
1945 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1946 struct ixgbe_rx_queue *rxq;
1948 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1952 IXGBE_SET_HWSTRIP(hwstrip, queue);
1954 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1956 if (queue >= dev->data->nb_rx_queues)
1959 rxq = dev->data->rx_queues[queue];
1962 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1963 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1965 rxq->vlan_flags = PKT_RX_VLAN;
1966 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1971 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1973 struct ixgbe_hw *hw =
1974 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1977 PMD_INIT_FUNC_TRACE();
1979 if (hw->mac.type == ixgbe_mac_82598EB) {
1980 /* No queue level support */
1981 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1985 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1986 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1987 ctrl &= ~IXGBE_RXDCTL_VME;
1988 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1990 /* record those setting for HW strip per queue */
1991 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1995 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1997 struct ixgbe_hw *hw =
1998 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001 PMD_INIT_FUNC_TRACE();
2003 if (hw->mac.type == ixgbe_mac_82598EB) {
2004 /* No queue level supported */
2005 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2009 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2010 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2011 ctrl |= IXGBE_RXDCTL_VME;
2012 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2014 /* record those setting for HW strip per queue */
2015 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2019 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2021 struct ixgbe_hw *hw =
2022 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025 PMD_INIT_FUNC_TRACE();
2027 /* DMATXCTRL: Geric Double VLAN Disable */
2028 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2029 ctrl &= ~IXGBE_DMATXCTL_GDV;
2030 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2032 /* CTRL_EXT: Global Double VLAN Disable */
2033 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2034 ctrl &= ~IXGBE_EXTENDED_VLAN;
2035 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2040 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2042 struct ixgbe_hw *hw =
2043 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2046 PMD_INIT_FUNC_TRACE();
2048 /* DMATXCTRL: Geric Double VLAN Enable */
2049 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2050 ctrl |= IXGBE_DMATXCTL_GDV;
2051 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2053 /* CTRL_EXT: Global Double VLAN Enable */
2054 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2055 ctrl |= IXGBE_EXTENDED_VLAN;
2056 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2058 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2059 if (hw->mac.type == ixgbe_mac_X550 ||
2060 hw->mac.type == ixgbe_mac_X550EM_x ||
2061 hw->mac.type == ixgbe_mac_X550EM_a) {
2062 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2063 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2064 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2068 * VET EXT field in the EXVET register = 0x8100 by default
2069 * So no need to change. Same to VT field of DMATXCTL register
2074 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2076 struct ixgbe_hw *hw =
2077 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2081 struct ixgbe_rx_queue *rxq;
2084 PMD_INIT_FUNC_TRACE();
2086 if (hw->mac.type == ixgbe_mac_82598EB) {
2087 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2088 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2089 ctrl |= IXGBE_VLNCTRL_VME;
2090 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2092 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2093 ctrl &= ~IXGBE_VLNCTRL_VME;
2094 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2098 * Other 10G NIC, the VLAN strip can be setup
2099 * per queue in RXDCTL
2101 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2102 rxq = dev->data->rx_queues[i];
2103 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2104 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2105 ctrl |= IXGBE_RXDCTL_VME;
2108 ctrl &= ~IXGBE_RXDCTL_VME;
2111 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2113 /* record those setting for HW strip per queue */
2114 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2120 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2123 struct rte_eth_rxmode *rxmode;
2124 struct ixgbe_rx_queue *rxq;
2126 if (mask & ETH_VLAN_STRIP_MASK) {
2127 rxmode = &dev->data->dev_conf.rxmode;
2128 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2129 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2130 rxq = dev->data->rx_queues[i];
2131 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2134 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2135 rxq = dev->data->rx_queues[i];
2136 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2142 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2144 struct rte_eth_rxmode *rxmode;
2145 rxmode = &dev->data->dev_conf.rxmode;
2147 if (mask & ETH_VLAN_STRIP_MASK) {
2148 ixgbe_vlan_hw_strip_config(dev);
2151 if (mask & ETH_VLAN_FILTER_MASK) {
2152 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2153 ixgbe_vlan_hw_filter_enable(dev);
2155 ixgbe_vlan_hw_filter_disable(dev);
2158 if (mask & ETH_VLAN_EXTEND_MASK) {
2159 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2160 ixgbe_vlan_hw_extend_enable(dev);
2162 ixgbe_vlan_hw_extend_disable(dev);
2169 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2171 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2173 ixgbe_vlan_offload_config(dev, mask);
2179 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2181 struct ixgbe_hw *hw =
2182 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2184 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2186 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2187 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2191 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2193 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2198 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2201 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2207 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2208 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2209 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2210 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2215 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2217 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2218 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2220 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2222 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2223 /* check multi-queue mode */
2224 switch (dev_conf->rxmode.mq_mode) {
2225 case ETH_MQ_RX_VMDQ_DCB:
2226 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2228 case ETH_MQ_RX_VMDQ_DCB_RSS:
2229 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2230 PMD_INIT_LOG(ERR, "SRIOV active,"
2231 " unsupported mq_mode rx %d.",
2232 dev_conf->rxmode.mq_mode);
2235 case ETH_MQ_RX_VMDQ_RSS:
2236 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2237 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2238 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2239 PMD_INIT_LOG(ERR, "SRIOV is active,"
2240 " invalid queue number"
2241 " for VMDQ RSS, allowed"
2242 " value are 1, 2 or 4.");
2246 case ETH_MQ_RX_VMDQ_ONLY:
2247 case ETH_MQ_RX_NONE:
2248 /* if nothing mq mode configure, use default scheme */
2249 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2251 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2252 /* SRIOV only works in VMDq enable mode */
2253 PMD_INIT_LOG(ERR, "SRIOV is active,"
2254 " wrong mq_mode rx %d.",
2255 dev_conf->rxmode.mq_mode);
2259 switch (dev_conf->txmode.mq_mode) {
2260 case ETH_MQ_TX_VMDQ_DCB:
2261 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2262 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2264 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2265 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2269 /* check valid queue number */
2270 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2271 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2272 PMD_INIT_LOG(ERR, "SRIOV is active,"
2273 " nb_rx_q=%d nb_tx_q=%d queue number"
2274 " must be less than or equal to %d.",
2276 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2280 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2281 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2285 /* check configuration for vmdb+dcb mode */
2286 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2287 const struct rte_eth_vmdq_dcb_conf *conf;
2289 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2290 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2291 IXGBE_VMDQ_DCB_NB_QUEUES);
2294 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2295 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2296 conf->nb_queue_pools == ETH_32_POOLS)) {
2297 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2298 " nb_queue_pools must be %d or %d.",
2299 ETH_16_POOLS, ETH_32_POOLS);
2303 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2304 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2306 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2307 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2308 IXGBE_VMDQ_DCB_NB_QUEUES);
2311 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2312 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2313 conf->nb_queue_pools == ETH_32_POOLS)) {
2314 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2315 " nb_queue_pools != %d and"
2316 " nb_queue_pools != %d.",
2317 ETH_16_POOLS, ETH_32_POOLS);
2322 /* For DCB mode check our configuration before we go further */
2323 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2324 const struct rte_eth_dcb_rx_conf *conf;
2326 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2327 if (!(conf->nb_tcs == ETH_4_TCS ||
2328 conf->nb_tcs == ETH_8_TCS)) {
2329 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2330 " and nb_tcs != %d.",
2331 ETH_4_TCS, ETH_8_TCS);
2336 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2337 const struct rte_eth_dcb_tx_conf *conf;
2339 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2340 if (!(conf->nb_tcs == ETH_4_TCS ||
2341 conf->nb_tcs == ETH_8_TCS)) {
2342 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2343 " and nb_tcs != %d.",
2344 ETH_4_TCS, ETH_8_TCS);
2350 * When DCB/VT is off, maximum number of queues changes,
2351 * except for 82598EB, which remains constant.
2353 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2354 hw->mac.type != ixgbe_mac_82598EB) {
2355 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2357 "Neither VT nor DCB are enabled, "
2359 IXGBE_NONE_MODE_TX_NB_QUEUES);
2368 ixgbe_dev_configure(struct rte_eth_dev *dev)
2370 struct ixgbe_interrupt *intr =
2371 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2372 struct ixgbe_adapter *adapter = dev->data->dev_private;
2375 PMD_INIT_FUNC_TRACE();
2377 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2378 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2380 /* multipe queue mode checking */
2381 ret = ixgbe_check_mq_mode(dev);
2383 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2388 /* set flag to update link status after init */
2389 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2392 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2393 * allocation or vector Rx preconditions we will reset it.
2395 adapter->rx_bulk_alloc_allowed = true;
2396 adapter->rx_vec_allowed = true;
2402 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2404 struct ixgbe_hw *hw =
2405 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406 struct ixgbe_interrupt *intr =
2407 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2410 /* only set up it on X550EM_X */
2411 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2412 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2413 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2414 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2415 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2416 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2421 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2422 uint16_t tx_rate, uint64_t q_msk)
2424 struct ixgbe_hw *hw;
2425 struct ixgbe_vf_info *vfinfo;
2426 struct rte_eth_link link;
2427 uint8_t nb_q_per_pool;
2428 uint32_t queue_stride;
2429 uint32_t queue_idx, idx = 0, vf_idx;
2431 uint16_t total_rate = 0;
2432 struct rte_pci_device *pci_dev;
2435 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2436 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2440 if (vf >= pci_dev->max_vfs)
2443 if (tx_rate > link.link_speed)
2449 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2450 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2451 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2452 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2453 queue_idx = vf * queue_stride;
2454 queue_end = queue_idx + nb_q_per_pool - 1;
2455 if (queue_end >= hw->mac.max_tx_queues)
2459 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2462 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2464 total_rate += vfinfo[vf_idx].tx_rate[idx];
2470 /* Store tx_rate for this vf. */
2471 for (idx = 0; idx < nb_q_per_pool; idx++) {
2472 if (((uint64_t)0x1 << idx) & q_msk) {
2473 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2474 vfinfo[vf].tx_rate[idx] = tx_rate;
2475 total_rate += tx_rate;
2479 if (total_rate > dev->data->dev_link.link_speed) {
2480 /* Reset stored TX rate of the VF if it causes exceed
2483 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2487 /* Set RTTBCNRC of each queue/pool for vf X */
2488 for (; queue_idx <= queue_end; queue_idx++) {
2490 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2498 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2500 struct ixgbe_adapter *adapter = dev->data->dev_private;
2506 err = ixgbe_fc_enable(hw);
2508 /* Not negotiated is not an error case */
2509 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2511 *check if we want to forward MAC frames - driver doesn't
2512 *have native capability to do that,
2513 *so we'll write the registers ourselves
2516 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2518 /* set or clear MFLCN.PMCF bit depending on configuration */
2519 if (adapter->mac_ctrl_frame_fwd != 0)
2520 mflcn |= IXGBE_MFLCN_PMCF;
2522 mflcn &= ~IXGBE_MFLCN_PMCF;
2524 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2525 IXGBE_WRITE_FLUSH(hw);
2533 * Configure device link speed and setup link.
2534 * It returns 0 on success.
2537 ixgbe_dev_start(struct rte_eth_dev *dev)
2539 struct ixgbe_hw *hw =
2540 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541 struct ixgbe_vf_info *vfinfo =
2542 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2543 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2544 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2545 uint32_t intr_vector = 0;
2547 bool link_up = false, negotiate = 0;
2549 uint32_t allowed_speeds = 0;
2553 uint32_t *link_speeds;
2554 struct ixgbe_tm_conf *tm_conf =
2555 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2556 struct ixgbe_macsec_setting *macsec_setting =
2557 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2559 PMD_INIT_FUNC_TRACE();
2561 /* Stop the link setup handler before resetting the HW. */
2562 ixgbe_dev_wait_setup_link_complete(dev, 0);
2564 /* disable uio/vfio intr/eventfd mapping */
2565 rte_intr_disable(intr_handle);
2568 hw->adapter_stopped = 0;
2569 ixgbe_stop_adapter(hw);
2571 /* reinitialize adapter
2572 * this calls reset and start
2574 status = ixgbe_pf_reset_hw(hw);
2577 hw->mac.ops.start_hw(hw);
2578 hw->mac.get_link_status = true;
2580 /* configure PF module if SRIOV enabled */
2581 ixgbe_pf_host_configure(dev);
2583 ixgbe_dev_phy_intr_setup(dev);
2585 /* check and configure queue intr-vector mapping */
2586 if ((rte_intr_cap_multiple(intr_handle) ||
2587 !RTE_ETH_DEV_SRIOV(dev).active) &&
2588 dev->data->dev_conf.intr_conf.rxq != 0) {
2589 intr_vector = dev->data->nb_rx_queues;
2590 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2591 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2592 IXGBE_MAX_INTR_QUEUE_NUM);
2595 if (rte_intr_efd_enable(intr_handle, intr_vector))
2599 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2600 intr_handle->intr_vec =
2601 rte_zmalloc("intr_vec",
2602 dev->data->nb_rx_queues * sizeof(int), 0);
2603 if (intr_handle->intr_vec == NULL) {
2604 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2605 " intr_vec", dev->data->nb_rx_queues);
2610 /* confiugre msix for sleep until rx interrupt */
2611 ixgbe_configure_msix(dev);
2613 /* initialize transmission unit */
2614 ixgbe_dev_tx_init(dev);
2616 /* This can fail when allocating mbufs for descriptor rings */
2617 err = ixgbe_dev_rx_init(dev);
2619 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2623 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2624 ETH_VLAN_EXTEND_MASK;
2625 err = ixgbe_vlan_offload_config(dev, mask);
2627 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2631 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2632 /* Enable vlan filtering for VMDq */
2633 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2636 /* Configure DCB hw */
2637 ixgbe_configure_dcb(dev);
2639 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2640 err = ixgbe_fdir_configure(dev);
2645 /* Restore vf rate limit */
2646 if (vfinfo != NULL) {
2647 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2648 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2649 if (vfinfo[vf].tx_rate[idx] != 0)
2650 ixgbe_set_vf_rate_limit(
2652 vfinfo[vf].tx_rate[idx],
2656 ixgbe_restore_statistics_mapping(dev);
2658 err = ixgbe_flow_ctrl_enable(dev, hw);
2660 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2664 err = ixgbe_dev_rxtx_start(dev);
2666 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2670 /* Skip link setup if loopback mode is enabled. */
2671 if (dev->data->dev_conf.lpbk_mode != 0) {
2672 err = ixgbe_check_supported_loopback_mode(dev);
2674 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2677 goto skip_link_setup;
2681 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2682 err = hw->mac.ops.setup_sfp(hw);
2687 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2688 /* Turn on the copper */
2689 ixgbe_set_phy_power(hw, true);
2691 /* Turn on the laser */
2692 ixgbe_enable_tx_laser(hw);
2695 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2698 dev->data->dev_link.link_status = link_up;
2700 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2704 switch (hw->mac.type) {
2705 case ixgbe_mac_X550:
2706 case ixgbe_mac_X550EM_x:
2707 case ixgbe_mac_X550EM_a:
2708 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2709 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2711 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2712 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2713 allowed_speeds = ETH_LINK_SPEED_10M |
2714 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2717 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2721 link_speeds = &dev->data->dev_conf.link_speeds;
2723 /* Ignore autoneg flag bit and check the validity ofÂ
2726 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2727 PMD_INIT_LOG(ERR, "Invalid link setting");
2732 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2733 switch (hw->mac.type) {
2734 case ixgbe_mac_82598EB:
2735 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2737 case ixgbe_mac_82599EB:
2738 case ixgbe_mac_X540:
2739 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2741 case ixgbe_mac_X550:
2742 case ixgbe_mac_X550EM_x:
2743 case ixgbe_mac_X550EM_a:
2744 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2747 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2750 if (*link_speeds & ETH_LINK_SPEED_10G)
2751 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2752 if (*link_speeds & ETH_LINK_SPEED_5G)
2753 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2754 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2755 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2756 if (*link_speeds & ETH_LINK_SPEED_1G)
2757 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2758 if (*link_speeds & ETH_LINK_SPEED_100M)
2759 speed |= IXGBE_LINK_SPEED_100_FULL;
2760 if (*link_speeds & ETH_LINK_SPEED_10M)
2761 speed |= IXGBE_LINK_SPEED_10_FULL;
2764 err = ixgbe_setup_link(hw, speed, link_up);
2770 if (rte_intr_allow_others(intr_handle)) {
2771 /* check if lsc interrupt is enabled */
2772 if (dev->data->dev_conf.intr_conf.lsc != 0)
2773 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2775 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2776 ixgbe_dev_macsec_interrupt_setup(dev);
2778 rte_intr_callback_unregister(intr_handle,
2779 ixgbe_dev_interrupt_handler, dev);
2780 if (dev->data->dev_conf.intr_conf.lsc != 0)
2781 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2782 " no intr multiplex");
2785 /* check if rxq interrupt is enabled */
2786 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2787 rte_intr_dp_is_en(intr_handle))
2788 ixgbe_dev_rxq_interrupt_setup(dev);
2790 /* enable uio/vfio intr/eventfd mapping */
2791 rte_intr_enable(intr_handle);
2793 /* resume enabled intr since hw reset */
2794 ixgbe_enable_intr(dev);
2795 ixgbe_l2_tunnel_conf(dev);
2796 ixgbe_filter_restore(dev);
2798 if (tm_conf->root && !tm_conf->committed)
2799 PMD_DRV_LOG(WARNING,
2800 "please call hierarchy_commit() "
2801 "before starting the port");
2803 /* wait for the controller to acquire link */
2804 err = ixgbe_wait_for_link_up(hw);
2809 * Update link status right before return, because it may
2810 * start link configuration process in a separate thread.
2812 ixgbe_dev_link_update(dev, 0);
2814 /* setup the macsec setting register */
2815 if (macsec_setting->offload_en)
2816 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2821 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2822 ixgbe_dev_clear_queues(dev);
2827 * Stop device: disable rx and tx functions to allow for reconfiguring.
2830 ixgbe_dev_stop(struct rte_eth_dev *dev)
2832 struct rte_eth_link link;
2833 struct ixgbe_adapter *adapter = dev->data->dev_private;
2834 struct ixgbe_hw *hw =
2835 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836 struct ixgbe_vf_info *vfinfo =
2837 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2838 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2839 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2841 struct ixgbe_tm_conf *tm_conf =
2842 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2844 if (hw->adapter_stopped)
2847 PMD_INIT_FUNC_TRACE();
2849 ixgbe_dev_wait_setup_link_complete(dev, 0);
2851 /* disable interrupts */
2852 ixgbe_disable_intr(hw);
2855 ixgbe_pf_reset_hw(hw);
2856 hw->adapter_stopped = 0;
2859 ixgbe_stop_adapter(hw);
2861 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2862 vfinfo[vf].clear_to_send = false;
2864 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2865 /* Turn off the copper */
2866 ixgbe_set_phy_power(hw, false);
2868 /* Turn off the laser */
2869 ixgbe_disable_tx_laser(hw);
2872 ixgbe_dev_clear_queues(dev);
2874 /* Clear stored conf */
2875 dev->data->scattered_rx = 0;
2878 /* Clear recorded link status */
2879 memset(&link, 0, sizeof(link));
2880 rte_eth_linkstatus_set(dev, &link);
2882 if (!rte_intr_allow_others(intr_handle))
2883 /* resume to the default handler */
2884 rte_intr_callback_register(intr_handle,
2885 ixgbe_dev_interrupt_handler,
2888 /* Clean datapath event and queue/vec mapping */
2889 rte_intr_efd_disable(intr_handle);
2890 if (intr_handle->intr_vec != NULL) {
2891 rte_free(intr_handle->intr_vec);
2892 intr_handle->intr_vec = NULL;
2895 /* reset hierarchy commit */
2896 tm_conf->committed = false;
2898 adapter->rss_reta_updated = 0;
2900 hw->adapter_stopped = true;
2901 dev->data->dev_started = 0;
2907 * Set device link up: enable tx.
2910 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2912 struct ixgbe_hw *hw =
2913 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2914 if (hw->mac.type == ixgbe_mac_82599EB) {
2915 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2916 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2917 /* Not suported in bypass mode */
2918 PMD_INIT_LOG(ERR, "Set link up is not supported "
2919 "by device id 0x%x", hw->device_id);
2925 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2926 /* Turn on the copper */
2927 ixgbe_set_phy_power(hw, true);
2929 /* Turn on the laser */
2930 ixgbe_enable_tx_laser(hw);
2931 ixgbe_dev_link_update(dev, 0);
2938 * Set device link down: disable tx.
2941 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2943 struct ixgbe_hw *hw =
2944 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2945 if (hw->mac.type == ixgbe_mac_82599EB) {
2946 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2947 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2948 /* Not suported in bypass mode */
2949 PMD_INIT_LOG(ERR, "Set link down is not supported "
2950 "by device id 0x%x", hw->device_id);
2956 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2957 /* Turn off the copper */
2958 ixgbe_set_phy_power(hw, false);
2960 /* Turn off the laser */
2961 ixgbe_disable_tx_laser(hw);
2962 ixgbe_dev_link_update(dev, 0);
2969 * Reset and stop device.
2972 ixgbe_dev_close(struct rte_eth_dev *dev)
2974 struct ixgbe_hw *hw =
2975 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2976 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2977 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2981 PMD_INIT_FUNC_TRACE();
2982 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2985 ixgbe_pf_reset_hw(hw);
2987 ret = ixgbe_dev_stop(dev);
2989 ixgbe_dev_free_queues(dev);
2991 ixgbe_disable_pcie_master(hw);
2993 /* reprogram the RAR[0] in case user changed it. */
2994 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2996 /* Unlock any pending hardware semaphore */
2997 ixgbe_swfw_lock_reset(hw);
2999 /* disable uio intr before callback unregister */
3000 rte_intr_disable(intr_handle);
3003 ret = rte_intr_callback_unregister(intr_handle,
3004 ixgbe_dev_interrupt_handler, dev);
3005 if (ret >= 0 || ret == -ENOENT) {
3007 } else if (ret != -EAGAIN) {
3009 "intr callback unregister failed: %d",
3013 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3015 /* cancel the delay handler before remove dev */
3016 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3018 /* uninitialize PF if max_vfs not zero */
3019 ixgbe_pf_host_uninit(dev);
3021 /* remove all the fdir filters & hash */
3022 ixgbe_fdir_filter_uninit(dev);
3024 /* remove all the L2 tunnel filters & hash */
3025 ixgbe_l2_tn_filter_uninit(dev);
3027 /* Remove all ntuple filters of the device */
3028 ixgbe_ntuple_filter_uninit(dev);
3030 /* clear all the filters list */
3031 ixgbe_filterlist_flush();
3033 /* Remove all Traffic Manager configuration */
3034 ixgbe_tm_conf_uninit(dev);
3036 #ifdef RTE_LIB_SECURITY
3037 rte_free(dev->security_ctx);
3047 ixgbe_dev_reset(struct rte_eth_dev *dev)
3051 /* When a DPDK PMD PF begin to reset PF port, it should notify all
3052 * its VF to make them align with it. The detailed notification
3053 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3054 * To avoid unexpected behavior in VF, currently reset of PF with
3055 * SR-IOV activation is not supported. It might be supported later.
3057 if (dev->data->sriov.active)
3060 ret = eth_ixgbe_dev_uninit(dev);
3064 ret = eth_ixgbe_dev_init(dev, NULL);
3070 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3071 struct ixgbe_hw_stats *hw_stats,
3072 struct ixgbe_macsec_stats *macsec_stats,
3073 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3074 uint64_t *total_qprc, uint64_t *total_qprdc)
3076 uint32_t bprc, lxon, lxoff, total;
3077 uint32_t delta_gprc = 0;
3079 /* Workaround for RX byte count not including CRC bytes when CRC
3080 * strip is enabled. CRC bytes are removed from counters when crc_strip
3083 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3084 IXGBE_HLREG0_RXCRCSTRP);
3086 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3087 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3088 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3089 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3091 for (i = 0; i < 8; i++) {
3092 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3094 /* global total per queue */
3095 hw_stats->mpc[i] += mp;
3096 /* Running comprehensive total for stats display */
3097 *total_missed_rx += hw_stats->mpc[i];
3098 if (hw->mac.type == ixgbe_mac_82598EB) {
3099 hw_stats->rnbc[i] +=
3100 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3101 hw_stats->pxonrxc[i] +=
3102 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3103 hw_stats->pxoffrxc[i] +=
3104 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3106 hw_stats->pxonrxc[i] +=
3107 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3108 hw_stats->pxoffrxc[i] +=
3109 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3110 hw_stats->pxon2offc[i] +=
3111 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3113 hw_stats->pxontxc[i] +=
3114 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3115 hw_stats->pxofftxc[i] +=
3116 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3118 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3119 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3120 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3121 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3123 delta_gprc += delta_qprc;
3125 hw_stats->qprc[i] += delta_qprc;
3126 hw_stats->qptc[i] += delta_qptc;
3128 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3129 hw_stats->qbrc[i] +=
3130 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3132 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3134 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3135 hw_stats->qbtc[i] +=
3136 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3138 hw_stats->qprdc[i] += delta_qprdc;
3139 *total_qprdc += hw_stats->qprdc[i];
3141 *total_qprc += hw_stats->qprc[i];
3142 *total_qbrc += hw_stats->qbrc[i];
3144 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3145 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3146 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3149 * An errata states that gprc actually counts good + missed packets:
3150 * Workaround to set gprc to summated queue packet receives
3152 hw_stats->gprc = *total_qprc;
3154 if (hw->mac.type != ixgbe_mac_82598EB) {
3155 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3156 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3157 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3158 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3159 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3160 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3161 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3162 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3164 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3165 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3166 /* 82598 only has a counter in the high register */
3167 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3168 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3169 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3171 uint64_t old_tpr = hw_stats->tpr;
3173 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3174 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3177 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3179 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3180 hw_stats->gptc += delta_gptc;
3181 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3182 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3185 * Workaround: mprc hardware is incorrectly counting
3186 * broadcasts, so for now we subtract those.
3188 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3189 hw_stats->bprc += bprc;
3190 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3191 if (hw->mac.type == ixgbe_mac_82598EB)
3192 hw_stats->mprc -= bprc;
3194 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3195 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3196 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3197 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3198 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3199 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3201 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3202 hw_stats->lxontxc += lxon;
3203 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3204 hw_stats->lxofftxc += lxoff;
3205 total = lxon + lxoff;
3207 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3208 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3209 hw_stats->gptc -= total;
3210 hw_stats->mptc -= total;
3211 hw_stats->ptc64 -= total;
3212 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3214 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3215 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3216 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3217 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3218 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3219 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3220 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3221 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3222 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3223 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3224 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3225 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3226 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3227 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3228 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3229 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3230 /* Only read FCOE on 82599 */
3231 if (hw->mac.type != ixgbe_mac_82598EB) {
3232 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3233 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3234 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3235 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3236 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3239 /* Flow Director Stats registers */
3240 if (hw->mac.type != ixgbe_mac_82598EB) {
3241 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3242 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3243 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3244 IXGBE_FDIRUSTAT) & 0xFFFF;
3245 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3246 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3247 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3248 IXGBE_FDIRFSTAT) & 0xFFFF;
3249 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3250 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3252 /* MACsec Stats registers */
3253 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3254 macsec_stats->out_pkts_encrypted +=
3255 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3256 macsec_stats->out_pkts_protected +=
3257 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3258 macsec_stats->out_octets_encrypted +=
3259 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3260 macsec_stats->out_octets_protected +=
3261 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3262 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3263 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3264 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3265 macsec_stats->in_pkts_unknownsci +=
3266 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3267 macsec_stats->in_octets_decrypted +=
3268 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3269 macsec_stats->in_octets_validated +=
3270 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3271 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3272 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3273 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3274 for (i = 0; i < 2; i++) {
3275 macsec_stats->in_pkts_ok +=
3276 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3277 macsec_stats->in_pkts_invalid +=
3278 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3279 macsec_stats->in_pkts_notvalid +=
3280 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3282 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3283 macsec_stats->in_pkts_notusingsa +=
3284 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3288 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3291 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3293 struct ixgbe_hw *hw =
3294 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295 struct ixgbe_hw_stats *hw_stats =
3296 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3297 struct ixgbe_macsec_stats *macsec_stats =
3298 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3299 dev->data->dev_private);
3300 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3303 total_missed_rx = 0;
3308 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3309 &total_qbrc, &total_qprc, &total_qprdc);
3314 /* Fill out the rte_eth_stats statistics structure */
3315 stats->ipackets = total_qprc;
3316 stats->ibytes = total_qbrc;
3317 stats->opackets = hw_stats->gptc;
3318 stats->obytes = hw_stats->gotc;
3320 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3321 stats->q_ipackets[i] = hw_stats->qprc[i];
3322 stats->q_opackets[i] = hw_stats->qptc[i];
3323 stats->q_ibytes[i] = hw_stats->qbrc[i];
3324 stats->q_obytes[i] = hw_stats->qbtc[i];
3325 stats->q_errors[i] = hw_stats->qprdc[i];
3329 stats->imissed = total_missed_rx;
3330 stats->ierrors = hw_stats->crcerrs +
3347 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3349 struct ixgbe_hw_stats *stats =
3350 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3352 /* HW registers are cleared on read */
3353 ixgbe_dev_stats_get(dev, NULL);
3355 /* Reset software totals */
3356 memset(stats, 0, sizeof(*stats));
3361 /* This function calculates the number of xstats based on the current config */
3363 ixgbe_xstats_calc_num(void) {
3364 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3365 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3366 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3369 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3370 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3372 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3373 unsigned stat, i, count;
3375 if (xstats_names != NULL) {
3378 /* Note: limit >= cnt_stats checked upstream
3379 * in rte_eth_xstats_names()
3382 /* Extended stats from ixgbe_hw_stats */
3383 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3384 strlcpy(xstats_names[count].name,
3385 rte_ixgbe_stats_strings[i].name,
3386 sizeof(xstats_names[count].name));
3391 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3392 strlcpy(xstats_names[count].name,
3393 rte_ixgbe_macsec_strings[i].name,
3394 sizeof(xstats_names[count].name));
3398 /* RX Priority Stats */
3399 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3400 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3401 snprintf(xstats_names[count].name,
3402 sizeof(xstats_names[count].name),
3403 "rx_priority%u_%s", i,
3404 rte_ixgbe_rxq_strings[stat].name);
3409 /* TX Priority Stats */
3410 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3411 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3412 snprintf(xstats_names[count].name,
3413 sizeof(xstats_names[count].name),
3414 "tx_priority%u_%s", i,
3415 rte_ixgbe_txq_strings[stat].name);
3423 static int ixgbe_dev_xstats_get_names_by_id(
3424 struct rte_eth_dev *dev,
3425 struct rte_eth_xstat_name *xstats_names,
3426 const uint64_t *ids,
3430 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3431 unsigned int stat, i, count;
3433 if (xstats_names != NULL) {
3436 /* Note: limit >= cnt_stats checked upstream
3437 * in rte_eth_xstats_names()
3440 /* Extended stats from ixgbe_hw_stats */
3441 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3442 strlcpy(xstats_names[count].name,
3443 rte_ixgbe_stats_strings[i].name,
3444 sizeof(xstats_names[count].name));
3449 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3450 strlcpy(xstats_names[count].name,
3451 rte_ixgbe_macsec_strings[i].name,
3452 sizeof(xstats_names[count].name));
3456 /* RX Priority Stats */
3457 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3458 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3459 snprintf(xstats_names[count].name,
3460 sizeof(xstats_names[count].name),
3461 "rx_priority%u_%s", i,
3462 rte_ixgbe_rxq_strings[stat].name);
3467 /* TX Priority Stats */
3468 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3469 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3470 snprintf(xstats_names[count].name,
3471 sizeof(xstats_names[count].name),
3472 "tx_priority%u_%s", i,
3473 rte_ixgbe_txq_strings[stat].name);
3482 uint16_t size = ixgbe_xstats_calc_num();
3483 struct rte_eth_xstat_name xstats_names_copy[size];
3485 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3488 for (i = 0; i < limit; i++) {
3489 if (ids[i] >= size) {
3490 PMD_INIT_LOG(ERR, "id value isn't valid");
3493 strcpy(xstats_names[i].name,
3494 xstats_names_copy[ids[i]].name);
3499 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3500 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3504 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3507 if (xstats_names != NULL)
3508 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3509 strlcpy(xstats_names[i].name,
3510 rte_ixgbevf_stats_strings[i].name,
3511 sizeof(xstats_names[i].name));
3512 return IXGBEVF_NB_XSTATS;
3516 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3519 struct ixgbe_hw *hw =
3520 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3521 struct ixgbe_hw_stats *hw_stats =
3522 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3523 struct ixgbe_macsec_stats *macsec_stats =
3524 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3525 dev->data->dev_private);
3526 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3527 unsigned i, stat, count = 0;
3529 count = ixgbe_xstats_calc_num();
3534 total_missed_rx = 0;
3539 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3540 &total_qbrc, &total_qprc, &total_qprdc);
3542 /* If this is a reset xstats is NULL, and we have cleared the
3543 * registers by reading them.
3548 /* Extended stats from ixgbe_hw_stats */
3550 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3551 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3552 rte_ixgbe_stats_strings[i].offset);
3553 xstats[count].id = count;
3558 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3559 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3560 rte_ixgbe_macsec_strings[i].offset);
3561 xstats[count].id = count;
3565 /* RX Priority Stats */
3566 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3567 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3568 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3569 rte_ixgbe_rxq_strings[stat].offset +
3570 (sizeof(uint64_t) * i));
3571 xstats[count].id = count;
3576 /* TX Priority Stats */
3577 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3578 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3579 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3580 rte_ixgbe_txq_strings[stat].offset +
3581 (sizeof(uint64_t) * i));
3582 xstats[count].id = count;
3590 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3591 uint64_t *values, unsigned int n)
3594 struct ixgbe_hw *hw =
3595 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3596 struct ixgbe_hw_stats *hw_stats =
3597 IXGBE_DEV_PRIVATE_TO_STATS(
3598 dev->data->dev_private);
3599 struct ixgbe_macsec_stats *macsec_stats =
3600 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3601 dev->data->dev_private);
3602 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3603 unsigned int i, stat, count = 0;
3605 count = ixgbe_xstats_calc_num();
3607 if (!ids && n < count)
3610 total_missed_rx = 0;
3615 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3616 &total_missed_rx, &total_qbrc, &total_qprc,
3619 /* If this is a reset xstats is NULL, and we have cleared the
3620 * registers by reading them.
3622 if (!ids && !values)
3625 /* Extended stats from ixgbe_hw_stats */
3627 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3628 values[count] = *(uint64_t *)(((char *)hw_stats) +
3629 rte_ixgbe_stats_strings[i].offset);
3634 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3635 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3636 rte_ixgbe_macsec_strings[i].offset);
3640 /* RX Priority Stats */
3641 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3642 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3644 *(uint64_t *)(((char *)hw_stats) +
3645 rte_ixgbe_rxq_strings[stat].offset +
3646 (sizeof(uint64_t) * i));
3651 /* TX Priority Stats */
3652 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3653 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3655 *(uint64_t *)(((char *)hw_stats) +
3656 rte_ixgbe_txq_strings[stat].offset +
3657 (sizeof(uint64_t) * i));
3665 uint16_t size = ixgbe_xstats_calc_num();
3666 uint64_t values_copy[size];
3668 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3670 for (i = 0; i < n; i++) {
3671 if (ids[i] >= size) {
3672 PMD_INIT_LOG(ERR, "id value isn't valid");
3675 values[i] = values_copy[ids[i]];
3681 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3683 struct ixgbe_hw_stats *stats =
3684 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3685 struct ixgbe_macsec_stats *macsec_stats =
3686 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3687 dev->data->dev_private);
3689 unsigned count = ixgbe_xstats_calc_num();
3691 /* HW registers are cleared on read */
3692 ixgbe_dev_xstats_get(dev, NULL, count);
3694 /* Reset software totals */
3695 memset(stats, 0, sizeof(*stats));
3696 memset(macsec_stats, 0, sizeof(*macsec_stats));
3702 ixgbevf_update_stats(struct rte_eth_dev *dev)
3704 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3705 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3706 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3708 /* Good Rx packet, include VF loopback */
3709 UPDATE_VF_STAT(IXGBE_VFGPRC,
3710 hw_stats->last_vfgprc, hw_stats->vfgprc);
3712 /* Good Rx octets, include VF loopback */
3713 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3714 hw_stats->last_vfgorc, hw_stats->vfgorc);
3716 /* Good Tx packet, include VF loopback */
3717 UPDATE_VF_STAT(IXGBE_VFGPTC,
3718 hw_stats->last_vfgptc, hw_stats->vfgptc);
3720 /* Good Tx octets, include VF loopback */
3721 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3722 hw_stats->last_vfgotc, hw_stats->vfgotc);
3724 /* Rx Multicst Packet */
3725 UPDATE_VF_STAT(IXGBE_VFMPRC,
3726 hw_stats->last_vfmprc, hw_stats->vfmprc);
3730 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3733 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3734 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3737 if (n < IXGBEVF_NB_XSTATS)
3738 return IXGBEVF_NB_XSTATS;
3740 ixgbevf_update_stats(dev);
3745 /* Extended stats */
3746 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3748 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3749 rte_ixgbevf_stats_strings[i].offset);
3752 return IXGBEVF_NB_XSTATS;
3756 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3758 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3759 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3761 ixgbevf_update_stats(dev);
3766 stats->ipackets = hw_stats->vfgprc;
3767 stats->ibytes = hw_stats->vfgorc;
3768 stats->opackets = hw_stats->vfgptc;
3769 stats->obytes = hw_stats->vfgotc;
3774 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3776 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3777 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3779 /* Sync HW register to the last stats */
3780 ixgbevf_dev_stats_get(dev, NULL);
3782 /* reset HW current stats*/
3783 hw_stats->vfgprc = 0;
3784 hw_stats->vfgorc = 0;
3785 hw_stats->vfgptc = 0;
3786 hw_stats->vfgotc = 0;
3792 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3794 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3795 u16 eeprom_verh, eeprom_verl;
3799 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3800 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3802 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3803 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3805 ret += 1; /* add the size of '\0' */
3806 if (fw_size < (u32)ret)
3813 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3815 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3816 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3817 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3819 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3820 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3821 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3823 * When DCB/VT is off, maximum number of queues changes,
3824 * except for 82598EB, which remains constant.
3826 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3827 hw->mac.type != ixgbe_mac_82598EB)
3828 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3830 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3831 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3832 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3833 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3834 dev_info->max_vfs = pci_dev->max_vfs;
3835 if (hw->mac.type == ixgbe_mac_82598EB)
3836 dev_info->max_vmdq_pools = ETH_16_POOLS;
3838 dev_info->max_vmdq_pools = ETH_64_POOLS;
3839 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3840 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3841 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3842 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3843 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3844 dev_info->rx_queue_offload_capa);
3845 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3846 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3848 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3850 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3851 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3852 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3854 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3859 dev_info->default_txconf = (struct rte_eth_txconf) {
3861 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3862 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3863 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3865 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3866 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3870 dev_info->rx_desc_lim = rx_desc_lim;
3871 dev_info->tx_desc_lim = tx_desc_lim;
3873 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3874 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3875 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3877 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3878 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3879 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3880 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3881 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3883 if (hw->mac.type == ixgbe_mac_X540 ||
3884 hw->mac.type == ixgbe_mac_X540_vf ||
3885 hw->mac.type == ixgbe_mac_X550 ||
3886 hw->mac.type == ixgbe_mac_X550_vf) {
3887 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3889 if (hw->mac.type == ixgbe_mac_X550) {
3890 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3891 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3894 /* Driver-preferred Rx/Tx parameters */
3895 dev_info->default_rxportconf.burst_size = 32;
3896 dev_info->default_txportconf.burst_size = 32;
3897 dev_info->default_rxportconf.nb_queues = 1;
3898 dev_info->default_txportconf.nb_queues = 1;
3899 dev_info->default_rxportconf.ring_size = 256;
3900 dev_info->default_txportconf.ring_size = 256;
3905 static const uint32_t *
3906 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3908 static const uint32_t ptypes[] = {
3909 /* For non-vec functions,
3910 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3911 * for vec functions,
3912 * refers to _recv_raw_pkts_vec().
3916 RTE_PTYPE_L3_IPV4_EXT,
3918 RTE_PTYPE_L3_IPV6_EXT,
3922 RTE_PTYPE_TUNNEL_IP,
3923 RTE_PTYPE_INNER_L3_IPV6,
3924 RTE_PTYPE_INNER_L3_IPV6_EXT,
3925 RTE_PTYPE_INNER_L4_TCP,
3926 RTE_PTYPE_INNER_L4_UDP,
3930 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3931 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3932 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3933 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3936 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3937 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3938 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3945 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3946 struct rte_eth_dev_info *dev_info)
3948 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3949 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3951 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3952 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3953 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3954 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3955 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3956 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3957 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3958 dev_info->max_vfs = pci_dev->max_vfs;
3959 if (hw->mac.type == ixgbe_mac_82598EB)
3960 dev_info->max_vmdq_pools = ETH_16_POOLS;
3962 dev_info->max_vmdq_pools = ETH_64_POOLS;
3963 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3964 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3965 dev_info->rx_queue_offload_capa);
3966 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3967 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3968 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3969 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3970 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3972 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3974 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3975 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3976 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3978 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3983 dev_info->default_txconf = (struct rte_eth_txconf) {
3985 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3986 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3987 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3989 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3990 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3994 dev_info->rx_desc_lim = rx_desc_lim;
3995 dev_info->tx_desc_lim = tx_desc_lim;
4001 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4002 bool *link_up, int wait_to_complete)
4004 struct ixgbe_adapter *adapter = container_of(hw,
4005 struct ixgbe_adapter, hw);
4006 struct ixgbe_mbx_info *mbx = &hw->mbx;
4007 struct ixgbe_mac_info *mac = &hw->mac;
4008 uint32_t links_reg, in_msg;
4011 /* If we were hit with a reset drop the link */
4012 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4013 mac->get_link_status = true;
4015 if (!mac->get_link_status)
4018 /* if link status is down no point in checking to see if pf is up */
4019 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4020 if (!(links_reg & IXGBE_LINKS_UP))
4023 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4024 * before the link status is correct
4026 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4029 for (i = 0; i < 5; i++) {
4031 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4033 if (!(links_reg & IXGBE_LINKS_UP))
4038 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4039 case IXGBE_LINKS_SPEED_10G_82599:
4040 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4041 if (hw->mac.type >= ixgbe_mac_X550) {
4042 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4043 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4046 case IXGBE_LINKS_SPEED_1G_82599:
4047 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4049 case IXGBE_LINKS_SPEED_100_82599:
4050 *speed = IXGBE_LINK_SPEED_100_FULL;
4051 if (hw->mac.type == ixgbe_mac_X550) {
4052 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4053 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4056 case IXGBE_LINKS_SPEED_10_X550EM_A:
4057 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4058 /* Since Reserved in older MAC's */
4059 if (hw->mac.type >= ixgbe_mac_X550)
4060 *speed = IXGBE_LINK_SPEED_10_FULL;
4063 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4066 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4067 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4068 mac->get_link_status = true;
4070 mac->get_link_status = false;
4075 /* if the read failed it could just be a mailbox collision, best wait
4076 * until we are called again and don't report an error
4078 if (mbx->ops.read(hw, &in_msg, 1, 0))
4081 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4082 /* msg is not CTS and is NACK we must have lost CTS status */
4083 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4084 mac->get_link_status = false;
4088 /* the pf is talking, if we timed out in the past we reinit */
4089 if (!mbx->timeout) {
4094 /* if we passed all the tests above then the link is up and we no
4095 * longer need to check for link
4097 mac->get_link_status = false;
4100 *link_up = !mac->get_link_status;
4105 * If @timeout_ms was 0, it means that it will not return until link complete.
4106 * It returns 1 on complete, return 0 on timeout.
4109 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4111 #define WARNING_TIMEOUT 9000 /* 9s in total */
4112 struct ixgbe_adapter *ad = dev->data->dev_private;
4113 uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4115 while (rte_atomic32_read(&ad->link_thread_running)) {
4122 } else if (!timeout) {
4123 /* It will not return until link complete */
4124 timeout = WARNING_TIMEOUT;
4125 PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4133 ixgbe_dev_setup_link_thread_handler(void *param)
4135 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4136 struct ixgbe_adapter *ad = dev->data->dev_private;
4137 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4138 struct ixgbe_interrupt *intr =
4139 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4141 bool autoneg = false;
4143 pthread_detach(pthread_self());
4144 speed = hw->phy.autoneg_advertised;
4146 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4148 ixgbe_setup_link(hw, speed, true);
4150 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4151 rte_atomic32_clear(&ad->link_thread_running);
4156 * In freebsd environment, nic_uio drivers do not support interrupts,
4157 * rte_intr_callback_register() will fail to register interrupts.
4158 * We can not make link status to change from down to up by interrupt
4159 * callback. So we need to wait for the controller to acquire link
4161 * It returns 0 on link up.
4164 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4166 #ifdef RTE_EXEC_ENV_FREEBSD
4168 bool link_up = false;
4170 const int nb_iter = 25;
4172 for (i = 0; i < nb_iter; i++) {
4173 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4188 /* return 0 means link status changed, -1 means not changed */
4190 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4191 int wait_to_complete, int vf)
4193 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4194 struct ixgbe_adapter *ad = dev->data->dev_private;
4195 struct rte_eth_link link;
4196 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4197 struct ixgbe_interrupt *intr =
4198 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4204 memset(&link, 0, sizeof(link));
4205 link.link_status = ETH_LINK_DOWN;
4206 link.link_speed = ETH_SPEED_NUM_NONE;
4207 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4208 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4209 ETH_LINK_SPEED_FIXED);
4211 hw->mac.get_link_status = true;
4213 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4214 return rte_eth_linkstatus_set(dev, &link);
4216 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4217 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4220 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4221 #ifdef RTE_EXEC_ENV_FREEBSD
4226 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4228 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4231 link.link_speed = ETH_SPEED_NUM_100M;
4232 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4233 return rte_eth_linkstatus_set(dev, &link);
4236 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4237 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4238 if ((esdp_reg & IXGBE_ESDP_SDP3))
4243 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4244 ixgbe_dev_wait_setup_link_complete(dev, 0);
4245 if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4246 /* To avoid race condition between threads, set
4247 * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4248 * when there is no link thread running.
4250 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4251 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4252 "ixgbe-link-handler",
4254 ixgbe_dev_setup_link_thread_handler,
4257 "Create link thread failed!");
4258 rte_atomic32_clear(&ad->link_thread_running);
4262 "Other link thread is running now!");
4265 return rte_eth_linkstatus_set(dev, &link);
4268 link.link_status = ETH_LINK_UP;
4269 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4271 switch (link_speed) {
4273 case IXGBE_LINK_SPEED_UNKNOWN:
4274 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4277 case IXGBE_LINK_SPEED_10_FULL:
4278 link.link_speed = ETH_SPEED_NUM_10M;
4281 case IXGBE_LINK_SPEED_100_FULL:
4282 link.link_speed = ETH_SPEED_NUM_100M;
4285 case IXGBE_LINK_SPEED_1GB_FULL:
4286 link.link_speed = ETH_SPEED_NUM_1G;
4289 case IXGBE_LINK_SPEED_2_5GB_FULL:
4290 link.link_speed = ETH_SPEED_NUM_2_5G;
4293 case IXGBE_LINK_SPEED_5GB_FULL:
4294 link.link_speed = ETH_SPEED_NUM_5G;
4297 case IXGBE_LINK_SPEED_10GB_FULL:
4298 link.link_speed = ETH_SPEED_NUM_10G;
4302 return rte_eth_linkstatus_set(dev, &link);
4306 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4308 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4312 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4314 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4318 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4320 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4323 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4324 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4325 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4331 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4333 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4336 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4337 fctrl &= (~IXGBE_FCTRL_UPE);
4338 if (dev->data->all_multicast == 1)
4339 fctrl |= IXGBE_FCTRL_MPE;
4341 fctrl &= (~IXGBE_FCTRL_MPE);
4342 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4348 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4350 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4353 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4354 fctrl |= IXGBE_FCTRL_MPE;
4355 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4361 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4363 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4366 if (dev->data->promiscuous == 1)
4367 return 0; /* must remain in all_multicast mode */
4369 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4370 fctrl &= (~IXGBE_FCTRL_MPE);
4371 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4377 * It clears the interrupt causes and enables the interrupt.
4378 * It will be called once only during nic initialized.
4381 * Pointer to struct rte_eth_dev.
4383 * Enable or Disable.
4386 * - On success, zero.
4387 * - On failure, a negative value.
4390 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4392 struct ixgbe_interrupt *intr =
4393 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4395 ixgbe_dev_link_status_print(dev);
4397 intr->mask |= IXGBE_EICR_LSC;
4399 intr->mask &= ~IXGBE_EICR_LSC;
4405 * It clears the interrupt causes and enables the interrupt.
4406 * It will be called once only during nic initialized.
4409 * Pointer to struct rte_eth_dev.
4412 * - On success, zero.
4413 * - On failure, a negative value.
4416 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4418 struct ixgbe_interrupt *intr =
4419 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4421 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4427 * It clears the interrupt causes and enables the interrupt.
4428 * It will be called once only during nic initialized.
4431 * Pointer to struct rte_eth_dev.
4434 * - On success, zero.
4435 * - On failure, a negative value.
4438 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4440 struct ixgbe_interrupt *intr =
4441 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4443 intr->mask |= IXGBE_EICR_LINKSEC;
4449 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4452 * Pointer to struct rte_eth_dev.
4455 * - On success, zero.
4456 * - On failure, a negative value.
4459 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4462 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4463 struct ixgbe_interrupt *intr =
4464 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4466 /* clear all cause mask */
4467 ixgbe_disable_intr(hw);
4469 /* read-on-clear nic registers here */
4470 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4471 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4475 /* set flag for async link update */
4476 if (eicr & IXGBE_EICR_LSC)
4477 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4479 if (eicr & IXGBE_EICR_MAILBOX)
4480 intr->flags |= IXGBE_FLAG_MAILBOX;
4482 if (eicr & IXGBE_EICR_LINKSEC)
4483 intr->flags |= IXGBE_FLAG_MACSEC;
4485 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4486 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4487 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4488 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4494 * It gets and then prints the link status.
4497 * Pointer to struct rte_eth_dev.
4500 * - On success, zero.
4501 * - On failure, a negative value.
4504 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4506 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4507 struct rte_eth_link link;
4509 rte_eth_linkstatus_get(dev, &link);
4511 if (link.link_status) {
4512 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4513 (int)(dev->data->port_id),
4514 (unsigned)link.link_speed,
4515 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4516 "full-duplex" : "half-duplex");
4518 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4519 (int)(dev->data->port_id));
4521 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4522 pci_dev->addr.domain,
4524 pci_dev->addr.devid,
4525 pci_dev->addr.function);
4529 * It executes link_update after knowing an interrupt occurred.
4532 * Pointer to struct rte_eth_dev.
4535 * - On success, zero.
4536 * - On failure, a negative value.
4539 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4541 struct ixgbe_interrupt *intr =
4542 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4544 struct ixgbe_hw *hw =
4545 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4547 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4549 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4550 ixgbe_pf_mbx_process(dev);
4551 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4554 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4555 ixgbe_handle_lasi(hw);
4556 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4559 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4560 struct rte_eth_link link;
4562 /* get the link status before link update, for predicting later */
4563 rte_eth_linkstatus_get(dev, &link);
4565 ixgbe_dev_link_update(dev, 0);
4568 if (!link.link_status)
4569 /* handle it 1 sec later, wait it being stable */
4570 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4571 /* likely to down */
4573 /* handle it 4 sec later, wait it being stable */
4574 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4576 ixgbe_dev_link_status_print(dev);
4577 if (rte_eal_alarm_set(timeout * 1000,
4578 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4579 PMD_DRV_LOG(ERR, "Error setting alarm");
4581 /* remember original mask */
4582 intr->mask_original = intr->mask;
4583 /* only disable lsc interrupt */
4584 intr->mask &= ~IXGBE_EIMS_LSC;
4588 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4589 ixgbe_enable_intr(dev);
4595 * Interrupt handler which shall be registered for alarm callback for delayed
4596 * handling specific interrupt to wait for the stable nic state. As the
4597 * NIC interrupt state is not stable for ixgbe after link is just down,
4598 * it needs to wait 4 seconds to get the stable status.
4601 * Pointer to interrupt handle.
4603 * The address of parameter (struct rte_eth_dev *) regsitered before.
4609 ixgbe_dev_interrupt_delayed_handler(void *param)
4611 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4612 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4613 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4614 struct ixgbe_interrupt *intr =
4615 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4616 struct ixgbe_hw *hw =
4617 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4620 ixgbe_disable_intr(hw);
4622 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4623 if (eicr & IXGBE_EICR_MAILBOX)
4624 ixgbe_pf_mbx_process(dev);
4626 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4627 ixgbe_handle_lasi(hw);
4628 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4631 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4632 ixgbe_dev_link_update(dev, 0);
4633 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4634 ixgbe_dev_link_status_print(dev);
4635 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4638 if (intr->flags & IXGBE_FLAG_MACSEC) {
4639 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4640 intr->flags &= ~IXGBE_FLAG_MACSEC;
4643 /* restore original mask */
4644 intr->mask = intr->mask_original;
4645 intr->mask_original = 0;
4647 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4648 ixgbe_enable_intr(dev);
4649 rte_intr_ack(intr_handle);
4653 * Interrupt handler triggered by NIC for handling
4654 * specific interrupt.
4657 * Pointer to interrupt handle.
4659 * The address of parameter (struct rte_eth_dev *) regsitered before.
4665 ixgbe_dev_interrupt_handler(void *param)
4667 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4669 ixgbe_dev_interrupt_get_status(dev);
4670 ixgbe_dev_interrupt_action(dev);
4674 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4676 struct ixgbe_hw *hw;
4678 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4679 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4683 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4685 struct ixgbe_hw *hw;
4687 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4688 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4692 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4694 struct ixgbe_hw *hw;
4700 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702 fc_conf->pause_time = hw->fc.pause_time;
4703 fc_conf->high_water = hw->fc.high_water[0];
4704 fc_conf->low_water = hw->fc.low_water[0];
4705 fc_conf->send_xon = hw->fc.send_xon;
4706 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4709 * Return rx_pause status according to actual setting of
4712 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4713 if (mflcn_reg & IXGBE_MFLCN_PMCF)
4714 fc_conf->mac_ctrl_frame_fwd = 1;
4716 fc_conf->mac_ctrl_frame_fwd = 0;
4718 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4724 * Return tx_pause status according to actual setting of
4727 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4728 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4733 if (rx_pause && tx_pause)
4734 fc_conf->mode = RTE_FC_FULL;
4736 fc_conf->mode = RTE_FC_RX_PAUSE;
4738 fc_conf->mode = RTE_FC_TX_PAUSE;
4740 fc_conf->mode = RTE_FC_NONE;
4746 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4748 struct ixgbe_hw *hw;
4749 struct ixgbe_adapter *adapter = dev->data->dev_private;
4751 uint32_t rx_buf_size;
4752 uint32_t max_high_water;
4753 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4760 PMD_INIT_FUNC_TRACE();
4762 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4763 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4764 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4767 * At least reserve one Ethernet frame for watermark
4768 * high_water/low_water in kilo bytes for ixgbe
4770 max_high_water = (rx_buf_size -
4771 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4772 if ((fc_conf->high_water > max_high_water) ||
4773 (fc_conf->high_water < fc_conf->low_water)) {
4774 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4775 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4779 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4780 hw->fc.pause_time = fc_conf->pause_time;
4781 hw->fc.high_water[0] = fc_conf->high_water;
4782 hw->fc.low_water[0] = fc_conf->low_water;
4783 hw->fc.send_xon = fc_conf->send_xon;
4784 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4785 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4787 err = ixgbe_flow_ctrl_enable(dev, hw);
4789 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4796 * ixgbe_pfc_enable_generic - Enable flow control
4797 * @hw: pointer to hardware structure
4798 * @tc_num: traffic class number
4799 * Enable flow control according to the current settings.
4802 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4805 uint32_t mflcn_reg, fccfg_reg;
4807 uint32_t fcrtl, fcrth;
4811 /* Validate the water mark configuration */
4812 if (!hw->fc.pause_time) {
4813 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4817 /* Low water mark of zero causes XOFF floods */
4818 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4819 /* High/Low water can not be 0 */
4820 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4821 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4822 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4826 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4827 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4828 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4832 /* Negotiate the fc mode to use */
4833 ixgbe_fc_autoneg(hw);
4835 /* Disable any previous flow control settings */
4836 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4837 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4839 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4840 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4842 switch (hw->fc.current_mode) {
4845 * If the count of enabled RX Priority Flow control >1,
4846 * and the TX pause can not be disabled
4849 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4850 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4851 if (reg & IXGBE_FCRTH_FCEN)
4855 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4857 case ixgbe_fc_rx_pause:
4859 * Rx Flow control is enabled and Tx Flow control is
4860 * disabled by software override. Since there really
4861 * isn't a way to advertise that we are capable of RX
4862 * Pause ONLY, we will advertise that we support both
4863 * symmetric and asymmetric Rx PAUSE. Later, we will
4864 * disable the adapter's ability to send PAUSE frames.
4866 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4868 * If the count of enabled RX Priority Flow control >1,
4869 * and the TX pause can not be disabled
4872 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4873 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4874 if (reg & IXGBE_FCRTH_FCEN)
4878 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4880 case ixgbe_fc_tx_pause:
4882 * Tx Flow control is enabled, and Rx Flow control is
4883 * disabled by software override.
4885 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4888 /* Flow control (both Rx and Tx) is enabled by SW override. */
4889 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4890 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4893 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4894 ret_val = IXGBE_ERR_CONFIG;
4898 /* Set 802.3x based flow control settings. */
4899 mflcn_reg |= IXGBE_MFLCN_DPF;
4900 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4901 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4903 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4904 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4905 hw->fc.high_water[tc_num]) {
4906 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4907 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4908 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4910 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4912 * In order to prevent Tx hangs when the internal Tx
4913 * switch is enabled we must set the high water mark
4914 * to the maximum FCRTH value. This allows the Tx
4915 * switch to function even under heavy Rx workloads.
4917 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4919 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4921 /* Configure pause time (2 TCs per register) */
4922 reg = hw->fc.pause_time * 0x00010001;
4923 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4924 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4926 /* Configure flow control refresh threshold value */
4927 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4934 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4936 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4937 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4939 if (hw->mac.type != ixgbe_mac_82598EB) {
4940 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4946 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4949 uint32_t rx_buf_size;
4950 uint32_t max_high_water;
4952 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4953 struct ixgbe_hw *hw =
4954 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955 struct ixgbe_dcb_config *dcb_config =
4956 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4958 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4965 PMD_INIT_FUNC_TRACE();
4967 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4968 tc_num = map[pfc_conf->priority];
4969 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4970 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4972 * At least reserve one Ethernet frame for watermark
4973 * high_water/low_water in kilo bytes for ixgbe
4975 max_high_water = (rx_buf_size -
4976 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4977 if ((pfc_conf->fc.high_water > max_high_water) ||
4978 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4979 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4980 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4984 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4985 hw->fc.pause_time = pfc_conf->fc.pause_time;
4986 hw->fc.send_xon = pfc_conf->fc.send_xon;
4987 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4988 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4990 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4992 /* Not negotiated is not an error case */
4993 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4996 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5001 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5002 struct rte_eth_rss_reta_entry64 *reta_conf,
5005 uint16_t i, sp_reta_size;
5008 uint16_t idx, shift;
5009 struct ixgbe_adapter *adapter = dev->data->dev_private;
5010 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5013 PMD_INIT_FUNC_TRACE();
5015 if (!ixgbe_rss_update_sp(hw->mac.type)) {
5016 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5021 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5022 if (reta_size != sp_reta_size) {
5023 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5024 "(%d) doesn't match the number hardware can supported "
5025 "(%d)", reta_size, sp_reta_size);
5029 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5030 idx = i / RTE_RETA_GROUP_SIZE;
5031 shift = i % RTE_RETA_GROUP_SIZE;
5032 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5036 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5037 if (mask == IXGBE_4_BIT_MASK)
5040 r = IXGBE_READ_REG(hw, reta_reg);
5041 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5042 if (mask & (0x1 << j))
5043 reta |= reta_conf[idx].reta[shift + j] <<
5046 reta |= r & (IXGBE_8_BIT_MASK <<
5049 IXGBE_WRITE_REG(hw, reta_reg, reta);
5051 adapter->rss_reta_updated = 1;
5057 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5058 struct rte_eth_rss_reta_entry64 *reta_conf,
5061 uint16_t i, sp_reta_size;
5064 uint16_t idx, shift;
5065 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5068 PMD_INIT_FUNC_TRACE();
5069 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5070 if (reta_size != sp_reta_size) {
5071 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5072 "(%d) doesn't match the number hardware can supported "
5073 "(%d)", reta_size, sp_reta_size);
5077 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5078 idx = i / RTE_RETA_GROUP_SIZE;
5079 shift = i % RTE_RETA_GROUP_SIZE;
5080 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5085 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5086 reta = IXGBE_READ_REG(hw, reta_reg);
5087 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5088 if (mask & (0x1 << j))
5089 reta_conf[idx].reta[shift + j] =
5090 ((reta >> (CHAR_BIT * j)) &
5099 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5100 uint32_t index, uint32_t pool)
5102 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5103 uint32_t enable_addr = 1;
5105 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5110 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5112 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5114 ixgbe_clear_rar(hw, index);
5118 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5120 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5122 ixgbe_remove_rar(dev, 0);
5123 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5129 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5131 if (strcmp(dev->device->driver->name, drv->driver.name))
5138 is_ixgbe_supported(struct rte_eth_dev *dev)
5140 return is_device_supported(dev, &rte_ixgbe_pmd);
5144 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5148 struct ixgbe_hw *hw;
5149 struct rte_eth_dev_info dev_info;
5150 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5151 struct rte_eth_dev_data *dev_data = dev->data;
5154 ret = ixgbe_dev_info_get(dev, &dev_info);
5158 /* check that mtu is within the allowed range */
5159 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5162 /* If device is started, refuse mtu that requires the support of
5163 * scattered packets when this feature has not been enabled before.
5165 if (dev_data->dev_started && !dev_data->scattered_rx &&
5166 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5167 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5168 PMD_INIT_LOG(ERR, "Stop port first.");
5172 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5173 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5175 /* switch to jumbo mode if needed */
5176 if (frame_size > RTE_ETHER_MAX_LEN) {
5177 dev->data->dev_conf.rxmode.offloads |=
5178 DEV_RX_OFFLOAD_JUMBO_FRAME;
5179 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5181 dev->data->dev_conf.rxmode.offloads &=
5182 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5183 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5185 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5187 /* update max frame size */
5188 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5190 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5191 maxfrs &= 0x0000FFFF;
5192 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5193 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5199 * Virtual Function operations
5202 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5204 struct ixgbe_interrupt *intr =
5205 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5206 struct ixgbe_hw *hw =
5207 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5209 PMD_INIT_FUNC_TRACE();
5211 /* Clear interrupt mask to stop from interrupts being generated */
5212 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5214 IXGBE_WRITE_FLUSH(hw);
5216 /* Clear mask value. */
5221 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5223 struct ixgbe_interrupt *intr =
5224 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5225 struct ixgbe_hw *hw =
5226 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5228 PMD_INIT_FUNC_TRACE();
5230 /* VF enable interrupt autoclean */
5231 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5232 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5233 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5235 IXGBE_WRITE_FLUSH(hw);
5237 /* Save IXGBE_VTEIMS value to mask. */
5238 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5242 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5244 struct rte_eth_conf *conf = &dev->data->dev_conf;
5245 struct ixgbe_adapter *adapter = dev->data->dev_private;
5247 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5248 dev->data->port_id);
5250 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5251 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5254 * VF has no ability to enable/disable HW CRC
5255 * Keep the persistent behavior the same as Host PF
5257 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5258 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5259 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5260 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5263 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5264 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5265 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5270 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5271 * allocation or vector Rx preconditions we will reset it.
5273 adapter->rx_bulk_alloc_allowed = true;
5274 adapter->rx_vec_allowed = true;
5280 ixgbevf_dev_start(struct rte_eth_dev *dev)
5282 struct ixgbe_hw *hw =
5283 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5284 uint32_t intr_vector = 0;
5285 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5286 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5290 PMD_INIT_FUNC_TRACE();
5292 /* Stop the link setup handler before resetting the HW. */
5293 ixgbe_dev_wait_setup_link_complete(dev, 0);
5295 err = hw->mac.ops.reset_hw(hw);
5298 * In this case, reuses the MAC address assigned by VF
5301 if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5302 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5306 hw->mac.get_link_status = true;
5308 /* negotiate mailbox API version to use with the PF. */
5309 ixgbevf_negotiate_api(hw);
5311 ixgbevf_dev_tx_init(dev);
5313 /* This can fail when allocating mbufs for descriptor rings */
5314 err = ixgbevf_dev_rx_init(dev);
5316 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5317 ixgbe_dev_clear_queues(dev);
5322 ixgbevf_set_vfta_all(dev, 1);
5325 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5326 ETH_VLAN_EXTEND_MASK;
5327 err = ixgbevf_vlan_offload_config(dev, mask);
5329 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5330 ixgbe_dev_clear_queues(dev);
5334 ixgbevf_dev_rxtx_start(dev);
5336 /* check and configure queue intr-vector mapping */
5337 if (rte_intr_cap_multiple(intr_handle) &&
5338 dev->data->dev_conf.intr_conf.rxq) {
5339 /* According to datasheet, only vector 0/1/2 can be used,
5340 * now only one vector is used for Rx queue
5343 if (rte_intr_efd_enable(intr_handle, intr_vector))
5347 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5348 intr_handle->intr_vec =
5349 rte_zmalloc("intr_vec",
5350 dev->data->nb_rx_queues * sizeof(int), 0);
5351 if (intr_handle->intr_vec == NULL) {
5352 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5353 " intr_vec", dev->data->nb_rx_queues);
5357 ixgbevf_configure_msix(dev);
5359 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5360 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5361 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5362 * is not cleared, it will fail when following rte_intr_enable( ) tries
5363 * to map Rx queue interrupt to other VFIO vectors.
5364 * So clear uio/vfio intr/evevnfd first to avoid failure.
5366 rte_intr_disable(intr_handle);
5368 rte_intr_enable(intr_handle);
5370 /* Re-enable interrupt for VF */
5371 ixgbevf_intr_enable(dev);
5374 * Update link status right before return, because it may
5375 * start link configuration process in a separate thread.
5377 ixgbevf_dev_link_update(dev, 0);
5379 hw->adapter_stopped = false;
5385 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5387 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5388 struct ixgbe_adapter *adapter = dev->data->dev_private;
5389 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5390 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5392 if (hw->adapter_stopped)
5395 PMD_INIT_FUNC_TRACE();
5397 ixgbe_dev_wait_setup_link_complete(dev, 0);
5399 ixgbevf_intr_disable(dev);
5401 dev->data->dev_started = 0;
5402 hw->adapter_stopped = 1;
5403 ixgbe_stop_adapter(hw);
5406 * Clear what we set, but we still keep shadow_vfta to
5407 * restore after device starts
5409 ixgbevf_set_vfta_all(dev, 0);
5411 /* Clear stored conf */
5412 dev->data->scattered_rx = 0;
5414 ixgbe_dev_clear_queues(dev);
5416 /* Clean datapath event and queue/vec mapping */
5417 rte_intr_efd_disable(intr_handle);
5418 if (intr_handle->intr_vec != NULL) {
5419 rte_free(intr_handle->intr_vec);
5420 intr_handle->intr_vec = NULL;
5423 adapter->rss_reta_updated = 0;
5429 ixgbevf_dev_close(struct rte_eth_dev *dev)
5431 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5432 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5433 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5436 PMD_INIT_FUNC_TRACE();
5437 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5442 ret = ixgbevf_dev_stop(dev);
5444 ixgbe_dev_free_queues(dev);
5447 * Remove the VF MAC address ro ensure
5448 * that the VF traffic goes to the PF
5449 * after stop, close and detach of the VF
5451 ixgbevf_remove_mac_addr(dev, 0);
5453 rte_intr_disable(intr_handle);
5454 rte_intr_callback_unregister(intr_handle,
5455 ixgbevf_dev_interrupt_handler, dev);
5464 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5468 ret = eth_ixgbevf_dev_uninit(dev);
5472 ret = eth_ixgbevf_dev_init(dev);
5477 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5479 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5480 struct ixgbe_vfta *shadow_vfta =
5481 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5482 int i = 0, j = 0, vfta = 0, mask = 1;
5484 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5485 vfta = shadow_vfta->vfta[i];
5488 for (j = 0; j < 32; j++) {
5490 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5500 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5502 struct ixgbe_hw *hw =
5503 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5504 struct ixgbe_vfta *shadow_vfta =
5505 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5506 uint32_t vid_idx = 0;
5507 uint32_t vid_bit = 0;
5510 PMD_INIT_FUNC_TRACE();
5512 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5513 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5515 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5518 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5519 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5521 /* Save what we set and retore it after device reset */
5523 shadow_vfta->vfta[vid_idx] |= vid_bit;
5525 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5531 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5533 struct ixgbe_hw *hw =
5534 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5537 PMD_INIT_FUNC_TRACE();
5539 if (queue >= hw->mac.max_rx_queues)
5542 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5544 ctrl |= IXGBE_RXDCTL_VME;
5546 ctrl &= ~IXGBE_RXDCTL_VME;
5547 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5549 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5553 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5555 struct ixgbe_rx_queue *rxq;
5559 /* VF function only support hw strip feature, others are not support */
5560 if (mask & ETH_VLAN_STRIP_MASK) {
5561 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5562 rxq = dev->data->rx_queues[i];
5563 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5564 ixgbevf_vlan_strip_queue_set(dev, i, on);
5572 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5574 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5576 ixgbevf_vlan_offload_config(dev, mask);
5582 ixgbe_vt_check(struct ixgbe_hw *hw)
5586 /* if Virtualization Technology is enabled */
5587 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5588 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5589 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5597 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5599 uint32_t vector = 0;
5601 switch (hw->mac.mc_filter_type) {
5602 case 0: /* use bits [47:36] of the address */
5603 vector = ((uc_addr->addr_bytes[4] >> 4) |
5604 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5606 case 1: /* use bits [46:35] of the address */
5607 vector = ((uc_addr->addr_bytes[4] >> 3) |
5608 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5610 case 2: /* use bits [45:34] of the address */
5611 vector = ((uc_addr->addr_bytes[4] >> 2) |
5612 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5614 case 3: /* use bits [43:32] of the address */
5615 vector = ((uc_addr->addr_bytes[4]) |
5616 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5618 default: /* Invalid mc_filter_type */
5622 /* vector can only be 12-bits or boundary will be exceeded */
5628 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5629 struct rte_ether_addr *mac_addr, uint8_t on)
5636 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5637 const uint32_t ixgbe_uta_bit_shift = 5;
5638 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5639 const uint32_t bit1 = 0x1;
5641 struct ixgbe_hw *hw =
5642 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5643 struct ixgbe_uta_info *uta_info =
5644 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5646 /* The UTA table only exists on 82599 hardware and newer */
5647 if (hw->mac.type < ixgbe_mac_82599EB)
5650 vector = ixgbe_uta_vector(hw, mac_addr);
5651 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5652 uta_shift = vector & ixgbe_uta_bit_mask;
5654 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5658 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5660 uta_info->uta_in_use++;
5661 reg_val |= (bit1 << uta_shift);
5662 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5664 uta_info->uta_in_use--;
5665 reg_val &= ~(bit1 << uta_shift);
5666 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5669 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5671 if (uta_info->uta_in_use > 0)
5672 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5673 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5675 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5681 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5684 struct ixgbe_hw *hw =
5685 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5686 struct ixgbe_uta_info *uta_info =
5687 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5689 /* The UTA table only exists on 82599 hardware and newer */
5690 if (hw->mac.type < ixgbe_mac_82599EB)
5694 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5695 uta_info->uta_shadow[i] = ~0;
5696 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5699 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5700 uta_info->uta_shadow[i] = 0;
5701 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5709 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5711 uint32_t new_val = orig_val;
5713 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5714 new_val |= IXGBE_VMOLR_AUPE;
5715 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5716 new_val |= IXGBE_VMOLR_ROMPE;
5717 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5718 new_val |= IXGBE_VMOLR_ROPE;
5719 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5720 new_val |= IXGBE_VMOLR_BAM;
5721 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5722 new_val |= IXGBE_VMOLR_MPE;
5727 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5728 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5729 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5730 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5731 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5732 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5733 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5736 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5737 struct rte_eth_mirror_conf *mirror_conf,
5738 uint8_t rule_id, uint8_t on)
5740 uint32_t mr_ctl, vlvf;
5741 uint32_t mp_lsb = 0;
5742 uint32_t mv_msb = 0;
5743 uint32_t mv_lsb = 0;
5744 uint32_t mp_msb = 0;
5747 uint64_t vlan_mask = 0;
5749 const uint8_t pool_mask_offset = 32;
5750 const uint8_t vlan_mask_offset = 32;
5751 const uint8_t dst_pool_offset = 8;
5752 const uint8_t rule_mr_offset = 4;
5753 const uint8_t mirror_rule_mask = 0x0F;
5755 struct ixgbe_mirror_info *mr_info =
5756 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5757 struct ixgbe_hw *hw =
5758 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5759 uint8_t mirror_type = 0;
5761 if (ixgbe_vt_check(hw) < 0)
5764 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5767 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5768 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5769 mirror_conf->rule_type);
5773 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5774 mirror_type |= IXGBE_MRCTL_VLME;
5775 /* Check if vlan id is valid and find conresponding VLAN ID
5778 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5779 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5780 /* search vlan id related pool vlan filter
5783 reg_index = ixgbe_find_vlvf_slot(
5785 mirror_conf->vlan.vlan_id[i],
5789 vlvf = IXGBE_READ_REG(hw,
5790 IXGBE_VLVF(reg_index));
5791 if ((vlvf & IXGBE_VLVF_VIEN) &&
5792 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5793 mirror_conf->vlan.vlan_id[i]))
5794 vlan_mask |= (1ULL << reg_index);
5801 mv_lsb = vlan_mask & 0xFFFFFFFF;
5802 mv_msb = vlan_mask >> vlan_mask_offset;
5804 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5805 mirror_conf->vlan.vlan_mask;
5806 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5807 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5808 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5809 mirror_conf->vlan.vlan_id[i];
5814 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5815 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5816 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5821 * if enable pool mirror, write related pool mask register,if disable
5822 * pool mirror, clear PFMRVM register
5824 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5825 mirror_type |= IXGBE_MRCTL_VPME;
5827 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5828 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5829 mr_info->mr_conf[rule_id].pool_mask =
5830 mirror_conf->pool_mask;
5835 mr_info->mr_conf[rule_id].pool_mask = 0;
5838 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5839 mirror_type |= IXGBE_MRCTL_UPME;
5840 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5841 mirror_type |= IXGBE_MRCTL_DPME;
5843 /* read mirror control register and recalculate it */
5844 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5847 mr_ctl |= mirror_type;
5848 mr_ctl &= mirror_rule_mask;
5849 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5851 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5854 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5855 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5857 /* write mirrror control register */
5858 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5860 /* write pool mirrror control register */
5861 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5862 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5863 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5866 /* write VLAN mirrror control register */
5867 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5868 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5869 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5877 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5880 uint32_t lsb_val = 0;
5881 uint32_t msb_val = 0;
5882 const uint8_t rule_mr_offset = 4;
5884 struct ixgbe_hw *hw =
5885 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5886 struct ixgbe_mirror_info *mr_info =
5887 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5889 if (ixgbe_vt_check(hw) < 0)
5892 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5895 memset(&mr_info->mr_conf[rule_id], 0,
5896 sizeof(struct rte_eth_mirror_conf));
5898 /* clear PFVMCTL register */
5899 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5901 /* clear pool mask register */
5902 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5903 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5905 /* clear vlan mask register */
5906 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5907 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5913 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5915 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5916 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5917 struct ixgbe_interrupt *intr =
5918 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5919 struct ixgbe_hw *hw =
5920 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5921 uint32_t vec = IXGBE_MISC_VEC_ID;
5923 if (rte_intr_allow_others(intr_handle))
5924 vec = IXGBE_RX_VEC_START;
5925 intr->mask |= (1 << vec);
5926 RTE_SET_USED(queue_id);
5927 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5929 rte_intr_ack(intr_handle);
5935 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5937 struct ixgbe_interrupt *intr =
5938 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5939 struct ixgbe_hw *hw =
5940 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5941 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5942 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5943 uint32_t vec = IXGBE_MISC_VEC_ID;
5945 if (rte_intr_allow_others(intr_handle))
5946 vec = IXGBE_RX_VEC_START;
5947 intr->mask &= ~(1 << vec);
5948 RTE_SET_USED(queue_id);
5949 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5955 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5957 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5958 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5960 struct ixgbe_hw *hw =
5961 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5962 struct ixgbe_interrupt *intr =
5963 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5965 if (queue_id < 16) {
5966 ixgbe_disable_intr(hw);
5967 intr->mask |= (1 << queue_id);
5968 ixgbe_enable_intr(dev);
5969 } else if (queue_id < 32) {
5970 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5971 mask &= (1 << queue_id);
5972 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5973 } else if (queue_id < 64) {
5974 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5975 mask &= (1 << (queue_id - 32));
5976 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5978 rte_intr_ack(intr_handle);
5984 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5987 struct ixgbe_hw *hw =
5988 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5989 struct ixgbe_interrupt *intr =
5990 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5992 if (queue_id < 16) {
5993 ixgbe_disable_intr(hw);
5994 intr->mask &= ~(1 << queue_id);
5995 ixgbe_enable_intr(dev);
5996 } else if (queue_id < 32) {
5997 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5998 mask &= ~(1 << queue_id);
5999 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6000 } else if (queue_id < 64) {
6001 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6002 mask &= ~(1 << (queue_id - 32));
6003 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6010 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6011 uint8_t queue, uint8_t msix_vector)
6015 if (direction == -1) {
6017 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6018 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6021 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6023 /* rx or tx cause */
6024 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6025 idx = ((16 * (queue & 1)) + (8 * direction));
6026 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6027 tmp &= ~(0xFF << idx);
6028 tmp |= (msix_vector << idx);
6029 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6034 * set the IVAR registers, mapping interrupt causes to vectors
6036 * pointer to ixgbe_hw struct
6038 * 0 for Rx, 1 for Tx, -1 for other causes
6040 * queue to map the corresponding interrupt to
6042 * the vector to map to the corresponding queue
6045 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6046 uint8_t queue, uint8_t msix_vector)
6050 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6051 if (hw->mac.type == ixgbe_mac_82598EB) {
6052 if (direction == -1)
6054 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6055 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6056 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6057 tmp |= (msix_vector << (8 * (queue & 0x3)));
6058 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6059 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6060 (hw->mac.type == ixgbe_mac_X540) ||
6061 (hw->mac.type == ixgbe_mac_X550) ||
6062 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6063 if (direction == -1) {
6065 idx = ((queue & 1) * 8);
6066 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6067 tmp &= ~(0xFF << idx);
6068 tmp |= (msix_vector << idx);
6069 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6071 /* rx or tx causes */
6072 idx = ((16 * (queue & 1)) + (8 * direction));
6073 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6074 tmp &= ~(0xFF << idx);
6075 tmp |= (msix_vector << idx);
6076 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6082 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6084 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6085 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6086 struct ixgbe_hw *hw =
6087 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6089 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6090 uint32_t base = IXGBE_MISC_VEC_ID;
6092 /* Configure VF other cause ivar */
6093 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6095 /* won't configure msix register if no mapping is done
6096 * between intr vector and event fd.
6098 if (!rte_intr_dp_is_en(intr_handle))
6101 if (rte_intr_allow_others(intr_handle)) {
6102 base = IXGBE_RX_VEC_START;
6103 vector_idx = IXGBE_RX_VEC_START;
6106 /* Configure all RX queues of VF */
6107 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6108 /* Force all queue use vector 0,
6109 * as IXGBE_VF_MAXMSIVECOTR = 1
6111 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6112 intr_handle->intr_vec[q_idx] = vector_idx;
6113 if (vector_idx < base + intr_handle->nb_efd - 1)
6117 /* As RX queue setting above show, all queues use the vector 0.
6118 * Set only the ITR value of IXGBE_MISC_VEC_ID.
6120 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6121 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6122 | IXGBE_EITR_CNT_WDIS);
6126 * Sets up the hardware to properly generate MSI-X interrupts
6128 * board private structure
6131 ixgbe_configure_msix(struct rte_eth_dev *dev)
6133 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6134 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6135 struct ixgbe_hw *hw =
6136 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6137 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6138 uint32_t vec = IXGBE_MISC_VEC_ID;
6142 /* won't configure msix register if no mapping is done
6143 * between intr vector and event fd
6144 * but if misx has been enabled already, need to configure
6145 * auto clean, auto mask and throttling.
6147 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6148 if (!rte_intr_dp_is_en(intr_handle) &&
6149 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6152 if (rte_intr_allow_others(intr_handle))
6153 vec = base = IXGBE_RX_VEC_START;
6155 /* setup GPIE for MSI-x mode */
6156 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6157 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6158 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6159 /* auto clearing and auto setting corresponding bits in EIMS
6160 * when MSI-X interrupt is triggered
6162 if (hw->mac.type == ixgbe_mac_82598EB) {
6163 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6165 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6166 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6168 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6170 /* Populate the IVAR table and set the ITR values to the
6171 * corresponding register.
6173 if (rte_intr_dp_is_en(intr_handle)) {
6174 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6176 /* by default, 1:1 mapping */
6177 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6178 intr_handle->intr_vec[queue_id] = vec;
6179 if (vec < base + intr_handle->nb_efd - 1)
6183 switch (hw->mac.type) {
6184 case ixgbe_mac_82598EB:
6185 ixgbe_set_ivar_map(hw, -1,
6186 IXGBE_IVAR_OTHER_CAUSES_INDEX,
6189 case ixgbe_mac_82599EB:
6190 case ixgbe_mac_X540:
6191 case ixgbe_mac_X550:
6192 case ixgbe_mac_X550EM_x:
6193 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6199 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6200 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6201 | IXGBE_EITR_CNT_WDIS);
6203 /* set up to autoclear timer, and the vectors */
6204 mask = IXGBE_EIMS_ENABLE_MASK;
6205 mask &= ~(IXGBE_EIMS_OTHER |
6206 IXGBE_EIMS_MAILBOX |
6209 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6213 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6214 uint16_t queue_idx, uint16_t tx_rate)
6216 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6217 struct rte_eth_rxmode *rxmode;
6218 uint32_t rf_dec, rf_int;
6220 uint16_t link_speed = dev->data->dev_link.link_speed;
6222 if (queue_idx >= hw->mac.max_tx_queues)
6226 /* Calculate the rate factor values to set */
6227 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6228 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6229 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6231 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6232 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6233 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6234 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6239 rxmode = &dev->data->dev_conf.rxmode;
6241 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6242 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6245 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6246 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6247 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6248 IXGBE_MMW_SIZE_JUMBO_FRAME);
6250 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6251 IXGBE_MMW_SIZE_DEFAULT);
6253 /* Set RTTBCNRC of queue X */
6254 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6255 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6256 IXGBE_WRITE_FLUSH(hw);
6262 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6263 __rte_unused uint32_t index,
6264 __rte_unused uint32_t pool)
6266 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6270 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6271 * operation. Trap this case to avoid exhausting the [very limited]
6272 * set of PF resources used to store VF MAC addresses.
6274 if (memcmp(hw->mac.perm_addr, mac_addr,
6275 sizeof(struct rte_ether_addr)) == 0)
6277 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6279 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6280 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6281 mac_addr->addr_bytes[0],
6282 mac_addr->addr_bytes[1],
6283 mac_addr->addr_bytes[2],
6284 mac_addr->addr_bytes[3],
6285 mac_addr->addr_bytes[4],
6286 mac_addr->addr_bytes[5],
6292 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6294 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6295 struct rte_ether_addr *perm_addr =
6296 (struct rte_ether_addr *)hw->mac.perm_addr;
6297 struct rte_ether_addr *mac_addr;
6302 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6303 * not support the deletion of a given MAC address.
6304 * Instead, it imposes to delete all MAC addresses, then to add again
6305 * all MAC addresses with the exception of the one to be deleted.
6307 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6310 * Add again all MAC addresses, with the exception of the deleted one
6311 * and of the permanent MAC address.
6313 for (i = 0, mac_addr = dev->data->mac_addrs;
6314 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6315 /* Skip the deleted MAC address */
6318 /* Skip NULL MAC addresses */
6319 if (rte_is_zero_ether_addr(mac_addr))
6321 /* Skip the permanent MAC address */
6322 if (memcmp(perm_addr, mac_addr,
6323 sizeof(struct rte_ether_addr)) == 0)
6325 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6328 "Adding again MAC address "
6329 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6331 mac_addr->addr_bytes[0],
6332 mac_addr->addr_bytes[1],
6333 mac_addr->addr_bytes[2],
6334 mac_addr->addr_bytes[3],
6335 mac_addr->addr_bytes[4],
6336 mac_addr->addr_bytes[5],
6342 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6343 struct rte_ether_addr *addr)
6345 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6347 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6353 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6354 struct rte_eth_syn_filter *filter,
6357 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6358 struct ixgbe_filter_info *filter_info =
6359 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6363 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6366 syn_info = filter_info->syn_info;
6369 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6371 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6372 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6374 if (filter->hig_pri)
6375 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6377 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6379 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6380 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6382 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6385 filter_info->syn_info = synqf;
6386 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6387 IXGBE_WRITE_FLUSH(hw);
6392 static inline enum ixgbe_5tuple_protocol
6393 convert_protocol_type(uint8_t protocol_value)
6395 if (protocol_value == IPPROTO_TCP)
6396 return IXGBE_FILTER_PROTOCOL_TCP;
6397 else if (protocol_value == IPPROTO_UDP)
6398 return IXGBE_FILTER_PROTOCOL_UDP;
6399 else if (protocol_value == IPPROTO_SCTP)
6400 return IXGBE_FILTER_PROTOCOL_SCTP;
6402 return IXGBE_FILTER_PROTOCOL_NONE;
6405 /* inject a 5-tuple filter to HW */
6407 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6408 struct ixgbe_5tuple_filter *filter)
6410 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6412 uint32_t ftqf, sdpqf;
6413 uint32_t l34timir = 0;
6414 uint8_t mask = 0xff;
6418 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6419 IXGBE_SDPQF_DSTPORT_SHIFT);
6420 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6422 ftqf = (uint32_t)(filter->filter_info.proto &
6423 IXGBE_FTQF_PROTOCOL_MASK);
6424 ftqf |= (uint32_t)((filter->filter_info.priority &
6425 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6426 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6427 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6428 if (filter->filter_info.dst_ip_mask == 0)
6429 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6430 if (filter->filter_info.src_port_mask == 0)
6431 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6432 if (filter->filter_info.dst_port_mask == 0)
6433 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6434 if (filter->filter_info.proto_mask == 0)
6435 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6436 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6437 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6438 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6440 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6441 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6442 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6443 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6445 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6446 l34timir |= (uint32_t)(filter->queue <<
6447 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6448 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6452 * add a 5tuple filter
6455 * dev: Pointer to struct rte_eth_dev.
6456 * index: the index the filter allocates.
6457 * filter: ponter to the filter that will be added.
6458 * rx_queue: the queue id the filter assigned to.
6461 * - On success, zero.
6462 * - On failure, a negative value.
6465 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6466 struct ixgbe_5tuple_filter *filter)
6468 struct ixgbe_filter_info *filter_info =
6469 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6473 * look for an unused 5tuple filter index,
6474 * and insert the filter to list.
6476 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6477 idx = i / (sizeof(uint32_t) * NBBY);
6478 shift = i % (sizeof(uint32_t) * NBBY);
6479 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6480 filter_info->fivetuple_mask[idx] |= 1 << shift;
6482 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6488 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6489 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6493 ixgbe_inject_5tuple_filter(dev, filter);
6499 * remove a 5tuple filter
6502 * dev: Pointer to struct rte_eth_dev.
6503 * filter: the pointer of the filter will be removed.
6506 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6507 struct ixgbe_5tuple_filter *filter)
6509 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6510 struct ixgbe_filter_info *filter_info =
6511 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6512 uint16_t index = filter->index;
6514 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6515 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6516 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6519 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6520 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6521 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6522 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6523 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6527 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6529 struct ixgbe_hw *hw;
6530 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6531 struct rte_eth_dev_data *dev_data = dev->data;
6533 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6535 if (mtu < RTE_ETHER_MIN_MTU ||
6536 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6539 /* If device is started, refuse mtu that requires the support of
6540 * scattered packets when this feature has not been enabled before.
6542 if (dev_data->dev_started && !dev_data->scattered_rx &&
6543 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6544 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6545 PMD_INIT_LOG(ERR, "Stop port first.");
6550 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6551 * request of the version 2.0 of the mailbox API.
6552 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6553 * of the mailbox API.
6554 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6555 * prior to 3.11.33 which contains the following change:
6556 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6558 if (ixgbevf_rlpml_set_vf(hw, max_frame))
6561 /* update max frame size */
6562 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6566 static inline struct ixgbe_5tuple_filter *
6567 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6568 struct ixgbe_5tuple_filter_info *key)
6570 struct ixgbe_5tuple_filter *it;
6572 TAILQ_FOREACH(it, filter_list, entries) {
6573 if (memcmp(key, &it->filter_info,
6574 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6581 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6583 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6584 struct ixgbe_5tuple_filter_info *filter_info)
6586 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6587 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6588 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6591 switch (filter->dst_ip_mask) {
6593 filter_info->dst_ip_mask = 0;
6594 filter_info->dst_ip = filter->dst_ip;
6597 filter_info->dst_ip_mask = 1;
6600 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6604 switch (filter->src_ip_mask) {
6606 filter_info->src_ip_mask = 0;
6607 filter_info->src_ip = filter->src_ip;
6610 filter_info->src_ip_mask = 1;
6613 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6617 switch (filter->dst_port_mask) {
6619 filter_info->dst_port_mask = 0;
6620 filter_info->dst_port = filter->dst_port;
6623 filter_info->dst_port_mask = 1;
6626 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6630 switch (filter->src_port_mask) {
6632 filter_info->src_port_mask = 0;
6633 filter_info->src_port = filter->src_port;
6636 filter_info->src_port_mask = 1;
6639 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6643 switch (filter->proto_mask) {
6645 filter_info->proto_mask = 0;
6646 filter_info->proto =
6647 convert_protocol_type(filter->proto);
6650 filter_info->proto_mask = 1;
6653 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6657 filter_info->priority = (uint8_t)filter->priority;
6662 * add or delete a ntuple filter
6665 * dev: Pointer to struct rte_eth_dev.
6666 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6667 * add: if true, add filter, if false, remove filter
6670 * - On success, zero.
6671 * - On failure, a negative value.
6674 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6675 struct rte_eth_ntuple_filter *ntuple_filter,
6678 struct ixgbe_filter_info *filter_info =
6679 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6680 struct ixgbe_5tuple_filter_info filter_5tuple;
6681 struct ixgbe_5tuple_filter *filter;
6684 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6685 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6689 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6690 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6694 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6696 if (filter != NULL && add) {
6697 PMD_DRV_LOG(ERR, "filter exists.");
6700 if (filter == NULL && !add) {
6701 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6706 filter = rte_zmalloc("ixgbe_5tuple_filter",
6707 sizeof(struct ixgbe_5tuple_filter), 0);
6710 rte_memcpy(&filter->filter_info,
6712 sizeof(struct ixgbe_5tuple_filter_info));
6713 filter->queue = ntuple_filter->queue;
6714 ret = ixgbe_add_5tuple_filter(dev, filter);
6720 ixgbe_remove_5tuple_filter(dev, filter);
6726 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6727 struct rte_eth_ethertype_filter *filter,
6730 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6731 struct ixgbe_filter_info *filter_info =
6732 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6736 struct ixgbe_ethertype_filter ethertype_filter;
6738 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6741 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6742 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6743 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6744 " ethertype filter.", filter->ether_type);
6748 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6749 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6752 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6753 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6757 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6758 if (ret >= 0 && add) {
6759 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6760 filter->ether_type);
6763 if (ret < 0 && !add) {
6764 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6765 filter->ether_type);
6770 etqf = IXGBE_ETQF_FILTER_EN;
6771 etqf |= (uint32_t)filter->ether_type;
6772 etqs |= (uint32_t)((filter->queue <<
6773 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6774 IXGBE_ETQS_RX_QUEUE);
6775 etqs |= IXGBE_ETQS_QUEUE_EN;
6777 ethertype_filter.ethertype = filter->ether_type;
6778 ethertype_filter.etqf = etqf;
6779 ethertype_filter.etqs = etqs;
6780 ethertype_filter.conf = FALSE;
6781 ret = ixgbe_ethertype_filter_insert(filter_info,
6784 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6788 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6792 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6793 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6794 IXGBE_WRITE_FLUSH(hw);
6800 ixgbe_dev_filter_ctrl(__rte_unused struct rte_eth_dev *dev,
6801 enum rte_filter_type filter_type,
6802 enum rte_filter_op filter_op,
6807 switch (filter_type) {
6808 case RTE_ETH_FILTER_GENERIC:
6809 if (filter_op != RTE_ETH_FILTER_GET)
6811 *(const void **)arg = &ixgbe_flow_ops;
6814 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6824 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6825 u8 **mc_addr_ptr, u32 *vmdq)
6830 mc_addr = *mc_addr_ptr;
6831 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6836 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6837 struct rte_ether_addr *mc_addr_set,
6838 uint32_t nb_mc_addr)
6840 struct ixgbe_hw *hw;
6843 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6844 mc_addr_list = (u8 *)mc_addr_set;
6845 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6846 ixgbe_dev_addr_list_itr, TRUE);
6850 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6852 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6853 uint64_t systime_cycles;
6855 switch (hw->mac.type) {
6856 case ixgbe_mac_X550:
6857 case ixgbe_mac_X550EM_x:
6858 case ixgbe_mac_X550EM_a:
6859 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6860 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6861 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6865 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6866 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6870 return systime_cycles;
6874 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6876 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6877 uint64_t rx_tstamp_cycles;
6879 switch (hw->mac.type) {
6880 case ixgbe_mac_X550:
6881 case ixgbe_mac_X550EM_x:
6882 case ixgbe_mac_X550EM_a:
6883 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6884 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6885 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6889 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6890 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6891 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6895 return rx_tstamp_cycles;
6899 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6901 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6902 uint64_t tx_tstamp_cycles;
6904 switch (hw->mac.type) {
6905 case ixgbe_mac_X550:
6906 case ixgbe_mac_X550EM_x:
6907 case ixgbe_mac_X550EM_a:
6908 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6909 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6910 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6914 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6915 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6916 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6920 return tx_tstamp_cycles;
6924 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6926 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6927 struct ixgbe_adapter *adapter = dev->data->dev_private;
6928 struct rte_eth_link link;
6929 uint32_t incval = 0;
6932 /* Get current link speed. */
6933 ixgbe_dev_link_update(dev, 1);
6934 rte_eth_linkstatus_get(dev, &link);
6936 switch (link.link_speed) {
6937 case ETH_SPEED_NUM_100M:
6938 incval = IXGBE_INCVAL_100;
6939 shift = IXGBE_INCVAL_SHIFT_100;
6941 case ETH_SPEED_NUM_1G:
6942 incval = IXGBE_INCVAL_1GB;
6943 shift = IXGBE_INCVAL_SHIFT_1GB;
6945 case ETH_SPEED_NUM_10G:
6947 incval = IXGBE_INCVAL_10GB;
6948 shift = IXGBE_INCVAL_SHIFT_10GB;
6952 switch (hw->mac.type) {
6953 case ixgbe_mac_X550:
6954 case ixgbe_mac_X550EM_x:
6955 case ixgbe_mac_X550EM_a:
6956 /* Independent of link speed. */
6958 /* Cycles read will be interpreted as ns. */
6961 case ixgbe_mac_X540:
6962 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6964 case ixgbe_mac_82599EB:
6965 incval >>= IXGBE_INCVAL_SHIFT_82599;
6966 shift -= IXGBE_INCVAL_SHIFT_82599;
6967 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6968 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6971 /* Not supported. */
6975 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6976 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6977 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6979 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6980 adapter->systime_tc.cc_shift = shift;
6981 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6983 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6984 adapter->rx_tstamp_tc.cc_shift = shift;
6985 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6987 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6988 adapter->tx_tstamp_tc.cc_shift = shift;
6989 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6993 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6995 struct ixgbe_adapter *adapter = dev->data->dev_private;
6997 adapter->systime_tc.nsec += delta;
6998 adapter->rx_tstamp_tc.nsec += delta;
6999 adapter->tx_tstamp_tc.nsec += delta;
7005 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7008 struct ixgbe_adapter *adapter = dev->data->dev_private;
7010 ns = rte_timespec_to_ns(ts);
7011 /* Set the timecounters to a new value. */
7012 adapter->systime_tc.nsec = ns;
7013 adapter->rx_tstamp_tc.nsec = ns;
7014 adapter->tx_tstamp_tc.nsec = ns;
7020 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7022 uint64_t ns, systime_cycles;
7023 struct ixgbe_adapter *adapter = dev->data->dev_private;
7025 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7026 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7027 *ts = rte_ns_to_timespec(ns);
7033 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7035 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7039 /* Stop the timesync system time. */
7040 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7041 /* Reset the timesync system time value. */
7042 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7043 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7045 /* Enable system time for platforms where it isn't on by default. */
7046 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7047 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7048 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7050 ixgbe_start_timecounters(dev);
7052 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7053 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7054 (RTE_ETHER_TYPE_1588 |
7055 IXGBE_ETQF_FILTER_EN |
7058 /* Enable timestamping of received PTP packets. */
7059 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7060 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7061 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7063 /* Enable timestamping of transmitted PTP packets. */
7064 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7065 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7066 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7068 IXGBE_WRITE_FLUSH(hw);
7074 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7076 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7079 /* Disable timestamping of transmitted PTP packets. */
7080 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7081 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7082 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7084 /* Disable timestamping of received PTP packets. */
7085 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7086 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7087 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7089 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7090 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7092 /* Stop incrementating the System Time registers. */
7093 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7099 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7100 struct timespec *timestamp,
7101 uint32_t flags __rte_unused)
7103 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7104 struct ixgbe_adapter *adapter = dev->data->dev_private;
7105 uint32_t tsync_rxctl;
7106 uint64_t rx_tstamp_cycles;
7109 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7110 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7113 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7114 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7115 *timestamp = rte_ns_to_timespec(ns);
7121 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7122 struct timespec *timestamp)
7124 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7125 struct ixgbe_adapter *adapter = dev->data->dev_private;
7126 uint32_t tsync_txctl;
7127 uint64_t tx_tstamp_cycles;
7130 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7131 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7134 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7135 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7136 *timestamp = rte_ns_to_timespec(ns);
7142 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7144 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7147 const struct reg_info *reg_group;
7148 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7149 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7151 while ((reg_group = reg_set[g_ind++]))
7152 count += ixgbe_regs_group_count(reg_group);
7158 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7162 const struct reg_info *reg_group;
7164 while ((reg_group = ixgbevf_regs[g_ind++]))
7165 count += ixgbe_regs_group_count(reg_group);
7171 ixgbe_get_regs(struct rte_eth_dev *dev,
7172 struct rte_dev_reg_info *regs)
7174 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7175 uint32_t *data = regs->data;
7178 const struct reg_info *reg_group;
7179 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7180 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7183 regs->length = ixgbe_get_reg_length(dev);
7184 regs->width = sizeof(uint32_t);
7188 /* Support only full register dump */
7189 if ((regs->length == 0) ||
7190 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7191 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7193 while ((reg_group = reg_set[g_ind++]))
7194 count += ixgbe_read_regs_group(dev, &data[count],
7203 ixgbevf_get_regs(struct rte_eth_dev *dev,
7204 struct rte_dev_reg_info *regs)
7206 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7207 uint32_t *data = regs->data;
7210 const struct reg_info *reg_group;
7213 regs->length = ixgbevf_get_reg_length(dev);
7214 regs->width = sizeof(uint32_t);
7218 /* Support only full register dump */
7219 if ((regs->length == 0) ||
7220 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7221 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7223 while ((reg_group = ixgbevf_regs[g_ind++]))
7224 count += ixgbe_read_regs_group(dev, &data[count],
7233 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7235 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7237 /* Return unit is byte count */
7238 return hw->eeprom.word_size * 2;
7242 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7243 struct rte_dev_eeprom_info *in_eeprom)
7245 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7246 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7247 uint16_t *data = in_eeprom->data;
7250 first = in_eeprom->offset >> 1;
7251 length = in_eeprom->length >> 1;
7252 if ((first > hw->eeprom.word_size) ||
7253 ((first + length) > hw->eeprom.word_size))
7256 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7258 return eeprom->ops.read_buffer(hw, first, length, data);
7262 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7263 struct rte_dev_eeprom_info *in_eeprom)
7265 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7266 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7267 uint16_t *data = in_eeprom->data;
7270 first = in_eeprom->offset >> 1;
7271 length = in_eeprom->length >> 1;
7272 if ((first > hw->eeprom.word_size) ||
7273 ((first + length) > hw->eeprom.word_size))
7276 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7278 return eeprom->ops.write_buffer(hw, first, length, data);
7282 ixgbe_get_module_info(struct rte_eth_dev *dev,
7283 struct rte_eth_dev_module_info *modinfo)
7285 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7287 uint8_t sff8472_rev, addr_mode;
7288 bool page_swap = false;
7290 /* Check whether we support SFF-8472 or not */
7291 status = hw->phy.ops.read_i2c_eeprom(hw,
7292 IXGBE_SFF_SFF_8472_COMP,
7297 /* addressing mode is not supported */
7298 status = hw->phy.ops.read_i2c_eeprom(hw,
7299 IXGBE_SFF_SFF_8472_SWAP,
7304 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7306 "Address change required to access page 0xA2, "
7307 "but not supported. Please report the module "
7308 "type to the driver maintainers.");
7312 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7313 /* We have a SFP, but it does not support SFF-8472 */
7314 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7315 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7317 /* We have a SFP which supports a revision of SFF-8472. */
7318 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7319 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7326 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7327 struct rte_dev_eeprom_info *info)
7329 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7330 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7331 uint8_t databyte = 0xFF;
7332 uint8_t *data = info->data;
7335 if (info->length == 0)
7338 for (i = info->offset; i < info->offset + info->length; i++) {
7339 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7340 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7342 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7347 data[i - info->offset] = databyte;
7354 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7356 case ixgbe_mac_X550:
7357 case ixgbe_mac_X550EM_x:
7358 case ixgbe_mac_X550EM_a:
7359 return ETH_RSS_RETA_SIZE_512;
7360 case ixgbe_mac_X550_vf:
7361 case ixgbe_mac_X550EM_x_vf:
7362 case ixgbe_mac_X550EM_a_vf:
7363 return ETH_RSS_RETA_SIZE_64;
7364 case ixgbe_mac_X540_vf:
7365 case ixgbe_mac_82599_vf:
7368 return ETH_RSS_RETA_SIZE_128;
7373 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7375 case ixgbe_mac_X550:
7376 case ixgbe_mac_X550EM_x:
7377 case ixgbe_mac_X550EM_a:
7378 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7379 return IXGBE_RETA(reta_idx >> 2);
7381 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7382 case ixgbe_mac_X550_vf:
7383 case ixgbe_mac_X550EM_x_vf:
7384 case ixgbe_mac_X550EM_a_vf:
7385 return IXGBE_VFRETA(reta_idx >> 2);
7387 return IXGBE_RETA(reta_idx >> 2);
7392 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7394 case ixgbe_mac_X550_vf:
7395 case ixgbe_mac_X550EM_x_vf:
7396 case ixgbe_mac_X550EM_a_vf:
7397 return IXGBE_VFMRQC;
7404 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7406 case ixgbe_mac_X550_vf:
7407 case ixgbe_mac_X550EM_x_vf:
7408 case ixgbe_mac_X550EM_a_vf:
7409 return IXGBE_VFRSSRK(i);
7411 return IXGBE_RSSRK(i);
7416 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7418 case ixgbe_mac_82599_vf:
7419 case ixgbe_mac_X540_vf:
7427 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7428 struct rte_eth_dcb_info *dcb_info)
7430 struct ixgbe_dcb_config *dcb_config =
7431 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7432 struct ixgbe_dcb_tc_config *tc;
7433 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7437 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7438 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7440 dcb_info->nb_tcs = 1;
7442 tc_queue = &dcb_info->tc_queue;
7443 nb_tcs = dcb_info->nb_tcs;
7445 if (dcb_config->vt_mode) { /* vt is enabled*/
7446 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7447 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7448 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7449 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7450 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7451 for (j = 0; j < nb_tcs; j++) {
7452 tc_queue->tc_rxq[0][j].base = j;
7453 tc_queue->tc_rxq[0][j].nb_queue = 1;
7454 tc_queue->tc_txq[0][j].base = j;
7455 tc_queue->tc_txq[0][j].nb_queue = 1;
7458 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7459 for (j = 0; j < nb_tcs; j++) {
7460 tc_queue->tc_rxq[i][j].base =
7462 tc_queue->tc_rxq[i][j].nb_queue = 1;
7463 tc_queue->tc_txq[i][j].base =
7465 tc_queue->tc_txq[i][j].nb_queue = 1;
7469 } else { /* vt is disabled*/
7470 struct rte_eth_dcb_rx_conf *rx_conf =
7471 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7472 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7473 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7474 if (dcb_info->nb_tcs == ETH_4_TCS) {
7475 for (i = 0; i < dcb_info->nb_tcs; i++) {
7476 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7477 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7479 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7480 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7481 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7482 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7483 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7484 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7485 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7486 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7487 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7488 for (i = 0; i < dcb_info->nb_tcs; i++) {
7489 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7490 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7492 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7493 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7494 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7495 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7496 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7497 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7498 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7499 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7500 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7501 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7502 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7503 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7504 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7505 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7506 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7507 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7510 for (i = 0; i < dcb_info->nb_tcs; i++) {
7511 tc = &dcb_config->tc_config[i];
7512 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7517 /* Update e-tag ether type */
7519 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7520 uint16_t ether_type)
7522 uint32_t etag_etype;
7524 if (hw->mac.type != ixgbe_mac_X550 &&
7525 hw->mac.type != ixgbe_mac_X550EM_x &&
7526 hw->mac.type != ixgbe_mac_X550EM_a) {
7530 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7531 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7532 etag_etype |= ether_type;
7533 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7534 IXGBE_WRITE_FLUSH(hw);
7539 /* Enable e-tag tunnel */
7541 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7543 uint32_t etag_etype;
7545 if (hw->mac.type != ixgbe_mac_X550 &&
7546 hw->mac.type != ixgbe_mac_X550EM_x &&
7547 hw->mac.type != ixgbe_mac_X550EM_a) {
7551 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7552 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7553 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7554 IXGBE_WRITE_FLUSH(hw);
7560 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7561 struct ixgbe_l2_tunnel_conf *l2_tunnel)
7564 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7565 uint32_t i, rar_entries;
7566 uint32_t rar_low, rar_high;
7568 if (hw->mac.type != ixgbe_mac_X550 &&
7569 hw->mac.type != ixgbe_mac_X550EM_x &&
7570 hw->mac.type != ixgbe_mac_X550EM_a) {
7574 rar_entries = ixgbe_get_num_rx_addrs(hw);
7576 for (i = 1; i < rar_entries; i++) {
7577 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7578 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7579 if ((rar_high & IXGBE_RAH_AV) &&
7580 (rar_high & IXGBE_RAH_ADTYPE) &&
7581 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7582 l2_tunnel->tunnel_id)) {
7583 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7584 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7586 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7596 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7597 struct ixgbe_l2_tunnel_conf *l2_tunnel)
7600 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7601 uint32_t i, rar_entries;
7602 uint32_t rar_low, rar_high;
7604 if (hw->mac.type != ixgbe_mac_X550 &&
7605 hw->mac.type != ixgbe_mac_X550EM_x &&
7606 hw->mac.type != ixgbe_mac_X550EM_a) {
7610 /* One entry for one tunnel. Try to remove potential existing entry. */
7611 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7613 rar_entries = ixgbe_get_num_rx_addrs(hw);
7615 for (i = 1; i < rar_entries; i++) {
7616 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7617 if (rar_high & IXGBE_RAH_AV) {
7620 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7621 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7622 rar_low = l2_tunnel->tunnel_id;
7624 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7625 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7631 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7632 " Please remove a rule before adding a new one.");
7636 static inline struct ixgbe_l2_tn_filter *
7637 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7638 struct ixgbe_l2_tn_key *key)
7642 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7646 return l2_tn_info->hash_map[ret];
7650 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7651 struct ixgbe_l2_tn_filter *l2_tn_filter)
7655 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7656 &l2_tn_filter->key);
7660 "Failed to insert L2 tunnel filter"
7661 " to hash table %d!",
7666 l2_tn_info->hash_map[ret] = l2_tn_filter;
7668 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7674 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7675 struct ixgbe_l2_tn_key *key)
7678 struct ixgbe_l2_tn_filter *l2_tn_filter;
7680 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7684 "No such L2 tunnel filter to delete %d!",
7689 l2_tn_filter = l2_tn_info->hash_map[ret];
7690 l2_tn_info->hash_map[ret] = NULL;
7692 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7693 rte_free(l2_tn_filter);
7698 /* Add l2 tunnel filter */
7700 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7701 struct ixgbe_l2_tunnel_conf *l2_tunnel,
7705 struct ixgbe_l2_tn_info *l2_tn_info =
7706 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7707 struct ixgbe_l2_tn_key key;
7708 struct ixgbe_l2_tn_filter *node;
7711 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7712 key.tn_id = l2_tunnel->tunnel_id;
7714 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7718 "The L2 tunnel filter already exists!");
7722 node = rte_zmalloc("ixgbe_l2_tn",
7723 sizeof(struct ixgbe_l2_tn_filter),
7728 rte_memcpy(&node->key,
7730 sizeof(struct ixgbe_l2_tn_key));
7731 node->pool = l2_tunnel->pool;
7732 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7739 switch (l2_tunnel->l2_tunnel_type) {
7740 case RTE_L2_TUNNEL_TYPE_E_TAG:
7741 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7744 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7749 if ((!restore) && (ret < 0))
7750 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7755 /* Delete l2 tunnel filter */
7757 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7758 struct ixgbe_l2_tunnel_conf *l2_tunnel)
7761 struct ixgbe_l2_tn_info *l2_tn_info =
7762 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7763 struct ixgbe_l2_tn_key key;
7765 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7766 key.tn_id = l2_tunnel->tunnel_id;
7767 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7771 switch (l2_tunnel->l2_tunnel_type) {
7772 case RTE_L2_TUNNEL_TYPE_E_TAG:
7773 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7776 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7785 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7789 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7791 if (hw->mac.type != ixgbe_mac_X550 &&
7792 hw->mac.type != ixgbe_mac_X550EM_x &&
7793 hw->mac.type != ixgbe_mac_X550EM_a) {
7797 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7798 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7800 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7801 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7807 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7810 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7811 IXGBE_WRITE_FLUSH(hw);
7816 /* There's only one register for VxLAN UDP port.
7817 * So, we cannot add several ports. Will update it.
7820 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7824 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7828 return ixgbe_update_vxlan_port(hw, port);
7831 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7832 * UDP port, it must have a value.
7833 * So, will reset it to the original value 0.
7836 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7841 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7843 if (cur_port != port) {
7844 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7848 return ixgbe_update_vxlan_port(hw, 0);
7851 /* Add UDP tunneling port */
7853 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7854 struct rte_eth_udp_tunnel *udp_tunnel)
7857 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7859 if (hw->mac.type != ixgbe_mac_X550 &&
7860 hw->mac.type != ixgbe_mac_X550EM_x &&
7861 hw->mac.type != ixgbe_mac_X550EM_a) {
7865 if (udp_tunnel == NULL)
7868 switch (udp_tunnel->prot_type) {
7869 case RTE_TUNNEL_TYPE_VXLAN:
7870 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7873 case RTE_TUNNEL_TYPE_GENEVE:
7874 case RTE_TUNNEL_TYPE_TEREDO:
7875 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7880 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7888 /* Remove UDP tunneling port */
7890 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7891 struct rte_eth_udp_tunnel *udp_tunnel)
7894 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7896 if (hw->mac.type != ixgbe_mac_X550 &&
7897 hw->mac.type != ixgbe_mac_X550EM_x &&
7898 hw->mac.type != ixgbe_mac_X550EM_a) {
7902 if (udp_tunnel == NULL)
7905 switch (udp_tunnel->prot_type) {
7906 case RTE_TUNNEL_TYPE_VXLAN:
7907 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7909 case RTE_TUNNEL_TYPE_GENEVE:
7910 case RTE_TUNNEL_TYPE_TEREDO:
7911 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7915 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7924 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
7926 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7929 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
7933 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7945 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
7947 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7950 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
7954 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7966 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7968 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7970 int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
7972 switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
7976 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7988 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7990 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7993 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
7997 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8008 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8010 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8013 /* peek the message first */
8014 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8016 /* PF reset VF event */
8017 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8018 /* dummy mbx read to ack pf */
8019 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8021 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8027 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8030 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8031 struct ixgbe_interrupt *intr =
8032 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8033 ixgbevf_intr_disable(dev);
8035 /* read-on-clear nic registers here */
8036 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8039 /* only one misc vector supported - mailbox */
8040 eicr &= IXGBE_VTEICR_MASK;
8041 if (eicr == IXGBE_MISC_VEC_ID)
8042 intr->flags |= IXGBE_FLAG_MAILBOX;
8048 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8050 struct ixgbe_interrupt *intr =
8051 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8053 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8054 ixgbevf_mbx_process(dev);
8055 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8058 ixgbevf_intr_enable(dev);
8064 ixgbevf_dev_interrupt_handler(void *param)
8066 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8068 ixgbevf_dev_interrupt_get_status(dev);
8069 ixgbevf_dev_interrupt_action(dev);
8073 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8074 * @hw: pointer to hardware structure
8076 * Stops the transmit data path and waits for the HW to internally empty
8077 * the Tx security block
8079 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8081 #define IXGBE_MAX_SECTX_POLL 40
8086 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8087 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8088 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8089 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8090 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8091 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8093 /* Use interrupt-safe sleep just in case */
8097 /* For informational purposes only */
8098 if (i >= IXGBE_MAX_SECTX_POLL)
8099 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8100 "path fully disabled. Continuing with init.");
8102 return IXGBE_SUCCESS;
8106 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8107 * @hw: pointer to hardware structure
8109 * Enables the transmit data path.
8111 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8115 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8116 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8117 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8118 IXGBE_WRITE_FLUSH(hw);
8120 return IXGBE_SUCCESS;
8123 /* restore n-tuple filter */
8125 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8127 struct ixgbe_filter_info *filter_info =
8128 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8129 struct ixgbe_5tuple_filter *node;
8131 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8132 ixgbe_inject_5tuple_filter(dev, node);
8136 /* restore ethernet type filter */
8138 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8140 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8141 struct ixgbe_filter_info *filter_info =
8142 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8145 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8146 if (filter_info->ethertype_mask & (1 << i)) {
8147 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8148 filter_info->ethertype_filters[i].etqf);
8149 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8150 filter_info->ethertype_filters[i].etqs);
8151 IXGBE_WRITE_FLUSH(hw);
8156 /* restore SYN filter */
8158 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8160 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8161 struct ixgbe_filter_info *filter_info =
8162 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8165 synqf = filter_info->syn_info;
8167 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8168 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8169 IXGBE_WRITE_FLUSH(hw);
8173 /* restore L2 tunnel filter */
8175 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8177 struct ixgbe_l2_tn_info *l2_tn_info =
8178 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8179 struct ixgbe_l2_tn_filter *node;
8180 struct ixgbe_l2_tunnel_conf l2_tn_conf;
8182 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8183 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8184 l2_tn_conf.tunnel_id = node->key.tn_id;
8185 l2_tn_conf.pool = node->pool;
8186 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8190 /* restore rss filter */
8192 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8194 struct ixgbe_filter_info *filter_info =
8195 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8197 if (filter_info->rss_info.conf.queue_num)
8198 ixgbe_config_rss_filter(dev,
8199 &filter_info->rss_info, TRUE);
8203 ixgbe_filter_restore(struct rte_eth_dev *dev)
8205 ixgbe_ntuple_filter_restore(dev);
8206 ixgbe_ethertype_filter_restore(dev);
8207 ixgbe_syn_filter_restore(dev);
8208 ixgbe_fdir_filter_restore(dev);
8209 ixgbe_l2_tn_filter_restore(dev);
8210 ixgbe_rss_filter_restore(dev);
8216 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8218 struct ixgbe_l2_tn_info *l2_tn_info =
8219 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8220 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8222 if (l2_tn_info->e_tag_en)
8223 (void)ixgbe_e_tag_enable(hw);
8225 if (l2_tn_info->e_tag_fwd_en)
8226 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8228 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8231 /* remove all the n-tuple filters */
8233 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8235 struct ixgbe_filter_info *filter_info =
8236 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8237 struct ixgbe_5tuple_filter *p_5tuple;
8239 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8240 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8243 /* remove all the ether type filters */
8245 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8247 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8248 struct ixgbe_filter_info *filter_info =
8249 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8252 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8253 if (filter_info->ethertype_mask & (1 << i) &&
8254 !filter_info->ethertype_filters[i].conf) {
8255 (void)ixgbe_ethertype_filter_remove(filter_info,
8257 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8258 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8259 IXGBE_WRITE_FLUSH(hw);
8264 /* remove the SYN filter */
8266 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8268 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8269 struct ixgbe_filter_info *filter_info =
8270 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8272 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8273 filter_info->syn_info = 0;
8275 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8276 IXGBE_WRITE_FLUSH(hw);
8280 /* remove all the L2 tunnel filters */
8282 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8284 struct ixgbe_l2_tn_info *l2_tn_info =
8285 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8286 struct ixgbe_l2_tn_filter *l2_tn_filter;
8287 struct ixgbe_l2_tunnel_conf l2_tn_conf;
8290 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8291 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8292 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8293 l2_tn_conf.pool = l2_tn_filter->pool;
8294 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8303 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8304 struct ixgbe_macsec_setting *macsec_setting)
8306 struct ixgbe_macsec_setting *macsec =
8307 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8309 macsec->offload_en = macsec_setting->offload_en;
8310 macsec->encrypt_en = macsec_setting->encrypt_en;
8311 macsec->replayprotect_en = macsec_setting->replayprotect_en;
8315 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8317 struct ixgbe_macsec_setting *macsec =
8318 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8320 macsec->offload_en = 0;
8321 macsec->encrypt_en = 0;
8322 macsec->replayprotect_en = 0;
8326 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8327 struct ixgbe_macsec_setting *macsec_setting)
8329 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8331 uint8_t en = macsec_setting->encrypt_en;
8332 uint8_t rp = macsec_setting->replayprotect_en;
8336 * As no ixgbe_disable_sec_rx_path equivalent is
8337 * implemented for tx in the base code, and we are
8338 * not allowed to modify the base code in DPDK, so
8339 * just call the hand-written one directly for now.
8340 * The hardware support has been checked by
8341 * ixgbe_disable_sec_rx_path().
8343 ixgbe_disable_sec_tx_path_generic(hw);
8345 /* Enable Ethernet CRC (required by MACsec offload) */
8346 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8347 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8348 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8350 /* Enable the TX and RX crypto engines */
8351 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8352 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8353 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8355 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8356 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8357 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8359 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8360 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8362 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8364 /* Enable SA lookup */
8365 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8366 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8367 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8368 IXGBE_LSECTXCTRL_AUTH;
8369 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8370 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8371 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8372 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8374 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8375 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8376 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8377 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8379 ctrl |= IXGBE_LSECRXCTRL_RP;
8381 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8382 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8384 /* Start the data paths */
8385 ixgbe_enable_sec_rx_path(hw);
8388 * As no ixgbe_enable_sec_rx_path equivalent is
8389 * implemented for tx in the base code, and we are
8390 * not allowed to modify the base code in DPDK, so
8391 * just call the hand-written one directly for now.
8393 ixgbe_enable_sec_tx_path_generic(hw);
8397 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8399 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8404 * As no ixgbe_disable_sec_rx_path equivalent is
8405 * implemented for tx in the base code, and we are
8406 * not allowed to modify the base code in DPDK, so
8407 * just call the hand-written one directly for now.
8408 * The hardware support has been checked by
8409 * ixgbe_disable_sec_rx_path().
8411 ixgbe_disable_sec_tx_path_generic(hw);
8413 /* Disable the TX and RX crypto engines */
8414 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8415 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8416 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8418 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8419 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8420 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8422 /* Disable SA lookup */
8423 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8424 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8425 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8426 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8428 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8429 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8430 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8431 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8433 /* Start the data paths */
8434 ixgbe_enable_sec_rx_path(hw);
8437 * As no ixgbe_enable_sec_rx_path equivalent is
8438 * implemented for tx in the base code, and we are
8439 * not allowed to modify the base code in DPDK, so
8440 * just call the hand-written one directly for now.
8442 ixgbe_enable_sec_tx_path_generic(hw);
8445 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8446 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8447 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8448 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8449 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8450 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8451 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8452 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8454 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
8455 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
8457 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
8458 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
8460 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
8461 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
8463 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
8464 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);