4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define IXGBE_TIMINCA_16NS_SHIFT 24
130 #define IXGBE_TIMINCA_INCVALUE 16000000
131 #define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
132 | IXGBE_TIMINCA_INCVALUE)
134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
147 int wait_to_complete);
148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
149 struct rte_eth_stats *stats);
150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
151 struct rte_eth_xstats *xstats, unsigned n);
152 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
153 struct rte_eth_xstats *xstats, unsigned n);
154 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
155 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
156 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
160 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
161 struct rte_eth_dev_info *dev_info);
162 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
163 struct rte_eth_dev_info *dev_info);
164 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
166 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
167 uint16_t vlan_id, int on);
168 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
169 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
170 uint16_t queue, bool on);
171 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
173 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
174 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
175 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
176 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
177 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
179 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
180 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
181 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
182 struct rte_eth_fc_conf *fc_conf);
183 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
184 struct rte_eth_fc_conf *fc_conf);
185 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
186 struct rte_eth_pfc_conf *pfc_conf);
187 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
188 struct rte_eth_rss_reta_entry64 *reta_conf,
190 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
191 struct rte_eth_rss_reta_entry64 *reta_conf,
193 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
194 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
195 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
196 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
197 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
198 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
200 static void ixgbe_dev_interrupt_delayed_handler(void *param);
201 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
202 uint32_t index, uint32_t pool);
203 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
204 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
205 struct ether_addr *mac_addr);
206 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
208 /* For Virtual Function support */
209 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
210 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
211 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
212 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
213 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
214 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
215 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
216 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
217 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
218 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
219 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
220 struct rte_eth_stats *stats);
221 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
222 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
223 uint16_t vlan_id, int on);
224 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
225 uint16_t queue, int on);
226 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
227 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
228 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
230 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
232 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
234 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
235 uint8_t queue, uint8_t msix_vector);
236 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
238 /* For Eth VMDQ APIs support */
239 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
240 ether_addr* mac_addr,uint8_t on);
241 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
242 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
243 uint16_t rx_mask, uint8_t on);
244 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
245 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
246 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
247 uint64_t pool_mask,uint8_t vlan_on);
248 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
249 struct rte_eth_mirror_conf *mirror_conf,
250 uint8_t rule_id, uint8_t on);
251 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
253 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
255 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
257 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
258 uint8_t queue, uint8_t msix_vector);
259 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
261 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
262 uint16_t queue_idx, uint16_t tx_rate);
263 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
264 uint16_t tx_rate, uint64_t q_msk);
266 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
267 struct ether_addr *mac_addr,
268 uint32_t index, uint32_t pool);
269 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
270 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
271 struct ether_addr *mac_addr);
272 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
273 struct rte_eth_syn_filter *filter,
275 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
276 struct rte_eth_syn_filter *filter);
277 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
278 enum rte_filter_op filter_op,
280 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
281 struct ixgbe_5tuple_filter *filter);
282 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
283 struct ixgbe_5tuple_filter *filter);
284 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
285 struct rte_eth_ntuple_filter *filter,
287 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
288 enum rte_filter_op filter_op,
290 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
291 struct rte_eth_ntuple_filter *filter);
292 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
293 struct rte_eth_ethertype_filter *filter,
295 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
296 enum rte_filter_op filter_op,
298 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
299 struct rte_eth_ethertype_filter *filter);
300 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
301 enum rte_filter_type filter_type,
302 enum rte_filter_op filter_op,
304 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
306 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
307 struct ether_addr *mc_addr_set,
308 uint32_t nb_mc_addr);
309 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
310 struct rte_eth_dcb_info *dcb_info);
312 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
313 static int ixgbe_get_regs(struct rte_eth_dev *dev,
314 struct rte_dev_reg_info *regs);
315 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
316 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
317 struct rte_dev_eeprom_info *eeprom);
318 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
319 struct rte_dev_eeprom_info *eeprom);
321 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
322 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
323 struct rte_dev_reg_info *regs);
325 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
326 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
327 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
328 struct timespec *timestamp,
330 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
331 struct timespec *timestamp);
334 * Define VF Stats MACRO for Non "cleared on read" register
336 #define UPDATE_VF_STAT(reg, last, cur) \
338 uint32_t latest = IXGBE_READ_REG(hw, reg); \
339 cur += (latest - last) & UINT_MAX; \
343 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
345 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
346 u64 new_msb = IXGBE_READ_REG(hw, msb); \
347 u64 latest = ((new_msb << 32) | new_lsb); \
348 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
352 #define IXGBE_SET_HWSTRIP(h, q) do{\
353 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
354 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
355 (h)->bitmap[idx] |= 1 << bit;\
358 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
359 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
360 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
361 (h)->bitmap[idx] &= ~(1 << bit);\
364 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
365 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
366 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
367 (r) = (h)->bitmap[idx] >> bit & 1;\
371 * The set of PCI devices this driver supports
373 static const struct rte_pci_id pci_id_ixgbe_map[] = {
375 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
376 #include "rte_pci_dev_ids.h"
378 { .vendor_id = 0, /* sentinel */ },
383 * The set of PCI devices this driver supports (for 82599 VF)
385 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
387 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
388 #include "rte_pci_dev_ids.h"
389 { .vendor_id = 0, /* sentinel */ },
393 static const struct rte_eth_desc_lim rx_desc_lim = {
394 .nb_max = IXGBE_MAX_RING_DESC,
395 .nb_min = IXGBE_MIN_RING_DESC,
396 .nb_align = IXGBE_RXD_ALIGN,
399 static const struct rte_eth_desc_lim tx_desc_lim = {
400 .nb_max = IXGBE_MAX_RING_DESC,
401 .nb_min = IXGBE_MIN_RING_DESC,
402 .nb_align = IXGBE_TXD_ALIGN,
405 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
406 .dev_configure = ixgbe_dev_configure,
407 .dev_start = ixgbe_dev_start,
408 .dev_stop = ixgbe_dev_stop,
409 .dev_set_link_up = ixgbe_dev_set_link_up,
410 .dev_set_link_down = ixgbe_dev_set_link_down,
411 .dev_close = ixgbe_dev_close,
412 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
413 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
414 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
415 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
416 .link_update = ixgbe_dev_link_update,
417 .stats_get = ixgbe_dev_stats_get,
418 .xstats_get = ixgbe_dev_xstats_get,
419 .stats_reset = ixgbe_dev_stats_reset,
420 .xstats_reset = ixgbe_dev_xstats_reset,
421 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
422 .dev_infos_get = ixgbe_dev_info_get,
423 .mtu_set = ixgbe_dev_mtu_set,
424 .vlan_filter_set = ixgbe_vlan_filter_set,
425 .vlan_tpid_set = ixgbe_vlan_tpid_set,
426 .vlan_offload_set = ixgbe_vlan_offload_set,
427 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
428 .rx_queue_start = ixgbe_dev_rx_queue_start,
429 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
430 .tx_queue_start = ixgbe_dev_tx_queue_start,
431 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
432 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
433 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
434 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
435 .rx_queue_release = ixgbe_dev_rx_queue_release,
436 .rx_queue_count = ixgbe_dev_rx_queue_count,
437 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
438 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
439 .tx_queue_release = ixgbe_dev_tx_queue_release,
440 .dev_led_on = ixgbe_dev_led_on,
441 .dev_led_off = ixgbe_dev_led_off,
442 .flow_ctrl_get = ixgbe_flow_ctrl_get,
443 .flow_ctrl_set = ixgbe_flow_ctrl_set,
444 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
445 .mac_addr_add = ixgbe_add_rar,
446 .mac_addr_remove = ixgbe_remove_rar,
447 .mac_addr_set = ixgbe_set_default_mac_addr,
448 .uc_hash_table_set = ixgbe_uc_hash_table_set,
449 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
450 .mirror_rule_set = ixgbe_mirror_rule_set,
451 .mirror_rule_reset = ixgbe_mirror_rule_reset,
452 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
453 .set_vf_rx = ixgbe_set_pool_rx,
454 .set_vf_tx = ixgbe_set_pool_tx,
455 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
456 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
457 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
458 .reta_update = ixgbe_dev_rss_reta_update,
459 .reta_query = ixgbe_dev_rss_reta_query,
460 #ifdef RTE_NIC_BYPASS
461 .bypass_init = ixgbe_bypass_init,
462 .bypass_state_set = ixgbe_bypass_state_store,
463 .bypass_state_show = ixgbe_bypass_state_show,
464 .bypass_event_set = ixgbe_bypass_event_store,
465 .bypass_event_show = ixgbe_bypass_event_show,
466 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
467 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
468 .bypass_ver_show = ixgbe_bypass_ver_show,
469 .bypass_wd_reset = ixgbe_bypass_wd_reset,
470 #endif /* RTE_NIC_BYPASS */
471 .rss_hash_update = ixgbe_dev_rss_hash_update,
472 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
473 .filter_ctrl = ixgbe_dev_filter_ctrl,
474 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
475 .rxq_info_get = ixgbe_rxq_info_get,
476 .txq_info_get = ixgbe_txq_info_get,
477 .timesync_enable = ixgbe_timesync_enable,
478 .timesync_disable = ixgbe_timesync_disable,
479 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
480 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
481 .get_reg_length = ixgbe_get_reg_length,
482 .get_reg = ixgbe_get_regs,
483 .get_eeprom_length = ixgbe_get_eeprom_length,
484 .get_eeprom = ixgbe_get_eeprom,
485 .set_eeprom = ixgbe_set_eeprom,
486 .get_dcb_info = ixgbe_dev_get_dcb_info,
490 * dev_ops for virtual function, bare necessities for basic vf
491 * operation have been implemented
493 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
494 .dev_configure = ixgbevf_dev_configure,
495 .dev_start = ixgbevf_dev_start,
496 .dev_stop = ixgbevf_dev_stop,
497 .link_update = ixgbe_dev_link_update,
498 .stats_get = ixgbevf_dev_stats_get,
499 .xstats_get = ixgbevf_dev_xstats_get,
500 .stats_reset = ixgbevf_dev_stats_reset,
501 .xstats_reset = ixgbevf_dev_stats_reset,
502 .dev_close = ixgbevf_dev_close,
503 .dev_infos_get = ixgbevf_dev_info_get,
504 .mtu_set = ixgbevf_dev_set_mtu,
505 .vlan_filter_set = ixgbevf_vlan_filter_set,
506 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
507 .vlan_offload_set = ixgbevf_vlan_offload_set,
508 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
509 .rx_queue_release = ixgbe_dev_rx_queue_release,
510 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
511 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
512 .tx_queue_release = ixgbe_dev_tx_queue_release,
513 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
514 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
515 .mac_addr_add = ixgbevf_add_mac_addr,
516 .mac_addr_remove = ixgbevf_remove_mac_addr,
517 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
518 .rxq_info_get = ixgbe_rxq_info_get,
519 .txq_info_get = ixgbe_txq_info_get,
520 .mac_addr_set = ixgbevf_set_default_mac_addr,
521 .get_reg_length = ixgbevf_get_reg_length,
522 .get_reg = ixgbevf_get_regs,
523 .reta_update = ixgbe_dev_rss_reta_update,
524 .reta_query = ixgbe_dev_rss_reta_query,
525 .rss_hash_update = ixgbe_dev_rss_hash_update,
526 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
529 /* store statistics names and its offset in stats structure */
530 struct rte_ixgbe_xstats_name_off {
531 char name[RTE_ETH_XSTATS_NAME_SIZE];
535 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
536 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
537 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
538 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
539 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
540 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
541 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
542 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
543 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
544 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
545 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
546 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
547 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
548 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
549 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
550 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
552 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
554 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
555 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
556 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
557 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
558 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
559 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
560 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
561 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
562 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
563 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
564 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
565 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
566 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
567 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
568 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
569 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
570 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
572 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
574 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
575 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
576 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
577 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
579 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
581 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
583 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
585 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
587 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
589 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
592 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
593 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
594 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
596 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
597 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
598 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
599 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
600 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
602 {"rx_fcoe_no_direct_data_placement_ext_buff",
603 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
605 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
607 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
609 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
611 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
613 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
616 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
617 sizeof(rte_ixgbe_stats_strings[0]))
619 /* Per-queue statistics */
620 #define IXBGE_NB_8_PER_Q_STATS (8 * 7)
621 #define IXBGE_NB_16_PER_Q_STATS (16 * 5)
622 #define IXGBE_NB_Q_STATS (IXBGE_NB_8_PER_Q_STATS + IXBGE_NB_16_PER_Q_STATS)
624 #define IXGBE_NB_XSTATS (IXGBE_NB_HW_STATS + IXGBE_NB_Q_STATS)
626 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
627 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
630 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
631 sizeof(rte_ixgbevf_stats_strings[0]))
634 * Atomically reads the link status information from global
635 * structure rte_eth_dev.
638 * - Pointer to the structure rte_eth_dev to read from.
639 * - Pointer to the buffer to be saved with the link status.
642 * - On success, zero.
643 * - On failure, negative value.
646 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
647 struct rte_eth_link *link)
649 struct rte_eth_link *dst = link;
650 struct rte_eth_link *src = &(dev->data->dev_link);
652 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
653 *(uint64_t *)src) == 0)
660 * Atomically writes the link status information into global
661 * structure rte_eth_dev.
664 * - Pointer to the structure rte_eth_dev to read from.
665 * - Pointer to the buffer to be saved with the link status.
668 * - On success, zero.
669 * - On failure, negative value.
672 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
673 struct rte_eth_link *link)
675 struct rte_eth_link *dst = &(dev->data->dev_link);
676 struct rte_eth_link *src = link;
678 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
679 *(uint64_t *)src) == 0)
686 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
689 ixgbe_is_sfp(struct ixgbe_hw *hw)
691 switch (hw->phy.type) {
692 case ixgbe_phy_sfp_avago:
693 case ixgbe_phy_sfp_ftl:
694 case ixgbe_phy_sfp_intel:
695 case ixgbe_phy_sfp_unknown:
696 case ixgbe_phy_sfp_passive_tyco:
697 case ixgbe_phy_sfp_passive_unknown:
704 static inline int32_t
705 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
710 status = ixgbe_reset_hw(hw);
712 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
713 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
714 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
715 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
716 IXGBE_WRITE_FLUSH(hw);
722 ixgbe_enable_intr(struct rte_eth_dev *dev)
724 struct ixgbe_interrupt *intr =
725 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
726 struct ixgbe_hw *hw =
727 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
729 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
730 IXGBE_WRITE_FLUSH(hw);
734 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
737 ixgbe_disable_intr(struct ixgbe_hw *hw)
739 PMD_INIT_FUNC_TRACE();
741 if (hw->mac.type == ixgbe_mac_82598EB) {
742 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
744 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
745 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
746 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
748 IXGBE_WRITE_FLUSH(hw);
752 * This function resets queue statistics mapping registers.
753 * From Niantic datasheet, Initialization of Statistics section:
754 * "...if software requires the queue counters, the RQSMR and TQSM registers
755 * must be re-programmed following a device reset.
758 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
762 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
763 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
764 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
770 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
775 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
776 #define NB_QMAP_FIELDS_PER_QSM_REG 4
777 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
779 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
780 struct ixgbe_stat_mapping_registers *stat_mappings =
781 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
782 uint32_t qsmr_mask = 0;
783 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
787 if ((hw->mac.type != ixgbe_mac_82599EB) &&
788 (hw->mac.type != ixgbe_mac_X540) &&
789 (hw->mac.type != ixgbe_mac_X550) &&
790 (hw->mac.type != ixgbe_mac_X550EM_x))
793 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
794 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
797 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
798 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
799 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
802 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
804 /* Now clear any previous stat_idx set */
805 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
807 stat_mappings->tqsm[n] &= ~clearing_mask;
809 stat_mappings->rqsmr[n] &= ~clearing_mask;
811 q_map = (uint32_t)stat_idx;
812 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
813 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
815 stat_mappings->tqsm[n] |= qsmr_mask;
817 stat_mappings->rqsmr[n] |= qsmr_mask;
819 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
820 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
822 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
823 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
825 /* Now write the mapping in the appropriate register */
827 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
828 stat_mappings->rqsmr[n], n);
829 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
832 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
833 stat_mappings->tqsm[n], n);
834 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
840 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
842 struct ixgbe_stat_mapping_registers *stat_mappings =
843 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
844 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
847 /* write whatever was in stat mapping table to the NIC */
848 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
850 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
853 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
858 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
861 struct ixgbe_dcb_tc_config *tc;
862 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
864 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
865 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
866 for (i = 0; i < dcb_max_tc; i++) {
867 tc = &dcb_config->tc_config[i];
868 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
869 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
870 (uint8_t)(100/dcb_max_tc + (i & 1));
871 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
872 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
873 (uint8_t)(100/dcb_max_tc + (i & 1));
874 tc->pfc = ixgbe_dcb_pfc_disabled;
877 /* Initialize default user to priority mapping, UPx->TC0 */
878 tc = &dcb_config->tc_config[0];
879 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
880 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
881 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
882 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
883 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
885 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
886 dcb_config->pfc_mode_enable = false;
887 dcb_config->vt_mode = true;
888 dcb_config->round_robin_enable = false;
889 /* support all DCB capabilities in 82599 */
890 dcb_config->support.capabilities = 0xFF;
892 /*we only support 4 Tcs for X540, X550 */
893 if (hw->mac.type == ixgbe_mac_X540 ||
894 hw->mac.type == ixgbe_mac_X550 ||
895 hw->mac.type == ixgbe_mac_X550EM_x) {
896 dcb_config->num_tcs.pg_tcs = 4;
897 dcb_config->num_tcs.pfc_tcs = 4;
902 * Ensure that all locks are released before first NVM or PHY access
905 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
910 * Phy lock should not fail in this early stage. If this is the case,
911 * it is due to an improper exit of the application.
912 * So force the release of the faulty lock. Release of common lock
913 * is done automatically by swfw_sync function.
915 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
916 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
917 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
919 ixgbe_release_swfw_semaphore(hw, mask);
922 * These ones are more tricky since they are common to all ports; but
923 * swfw_sync retries last long enough (1s) to be almost sure that if
924 * lock can not be taken it is due to an improper lock of the
927 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
928 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
929 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
931 ixgbe_release_swfw_semaphore(hw, mask);
935 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
936 * It returns 0 on success.
939 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
941 struct rte_pci_device *pci_dev;
942 struct ixgbe_hw *hw =
943 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
944 struct ixgbe_vfta * shadow_vfta =
945 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
946 struct ixgbe_hwstrip *hwstrip =
947 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
948 struct ixgbe_dcb_config *dcb_config =
949 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
950 struct ixgbe_filter_info *filter_info =
951 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
956 PMD_INIT_FUNC_TRACE();
958 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
959 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
960 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
963 * For secondary processes, we don't initialise any further as primary
964 * has already done this work. Only check we don't need a different
965 * RX and TX function.
967 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
968 struct ixgbe_tx_queue *txq;
969 /* TX queue function in primary, set by last queue initialized
970 * Tx queue may not initialized by primary process */
971 if (eth_dev->data->tx_queues) {
972 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
973 ixgbe_set_tx_function(eth_dev, txq);
975 /* Use default TX function if we get here */
976 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
977 "Using default TX function.");
980 ixgbe_set_rx_function(eth_dev);
984 pci_dev = eth_dev->pci_dev;
986 /* Vendor and Device ID need to be set before init of shared code */
987 hw->device_id = pci_dev->id.device_id;
988 hw->vendor_id = pci_dev->id.vendor_id;
989 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
990 hw->allow_unsupported_sfp = 1;
992 /* Initialize the shared code (base driver) */
993 #ifdef RTE_NIC_BYPASS
994 diag = ixgbe_bypass_init_shared_code(hw);
996 diag = ixgbe_init_shared_code(hw);
997 #endif /* RTE_NIC_BYPASS */
999 if (diag != IXGBE_SUCCESS) {
1000 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1004 /* pick up the PCI bus settings for reporting later */
1005 ixgbe_get_bus_info(hw);
1007 /* Unlock any pending hardware semaphore */
1008 ixgbe_swfw_lock_reset(hw);
1010 /* Initialize DCB configuration*/
1011 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1012 ixgbe_dcb_init(hw,dcb_config);
1013 /* Get Hardware Flow Control setting */
1014 hw->fc.requested_mode = ixgbe_fc_full;
1015 hw->fc.current_mode = ixgbe_fc_full;
1016 hw->fc.pause_time = IXGBE_FC_PAUSE;
1017 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1018 hw->fc.low_water[i] = IXGBE_FC_LO;
1019 hw->fc.high_water[i] = IXGBE_FC_HI;
1021 hw->fc.send_xon = 1;
1023 /* Make sure we have a good EEPROM before we read from it */
1024 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1025 if (diag != IXGBE_SUCCESS) {
1026 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1030 #ifdef RTE_NIC_BYPASS
1031 diag = ixgbe_bypass_init_hw(hw);
1033 diag = ixgbe_init_hw(hw);
1034 #endif /* RTE_NIC_BYPASS */
1037 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1038 * is called too soon after the kernel driver unbinding/binding occurs.
1039 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1040 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1041 * also called. See ixgbe_identify_phy_82599(). The reason for the
1042 * failure is not known, and only occuts when virtualisation features
1043 * are disabled in the bios. A delay of 100ms was found to be enough by
1044 * trial-and-error, and is doubled to be safe.
1046 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1048 diag = ixgbe_init_hw(hw);
1051 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1052 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1053 "LOM. Please be aware there may be issues associated "
1054 "with your hardware.");
1055 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1056 "please contact your Intel or hardware representative "
1057 "who provided you with this hardware.");
1058 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1059 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1061 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1065 /* Reset the hw statistics */
1066 ixgbe_dev_stats_reset(eth_dev);
1068 /* disable interrupt */
1069 ixgbe_disable_intr(hw);
1071 /* reset mappings for queue statistics hw counters*/
1072 ixgbe_reset_qstat_mappings(hw);
1074 /* Allocate memory for storing MAC addresses */
1075 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1076 hw->mac.num_rar_entries, 0);
1077 if (eth_dev->data->mac_addrs == NULL) {
1079 "Failed to allocate %u bytes needed to store "
1081 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1084 /* Copy the permanent MAC address */
1085 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1086 ð_dev->data->mac_addrs[0]);
1088 /* Allocate memory for storing hash filter MAC addresses */
1089 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1090 IXGBE_VMDQ_NUM_UC_MAC, 0);
1091 if (eth_dev->data->hash_mac_addrs == NULL) {
1093 "Failed to allocate %d bytes needed to store MAC addresses",
1094 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1098 /* initialize the vfta */
1099 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1101 /* initialize the hw strip bitmap*/
1102 memset(hwstrip, 0, sizeof(*hwstrip));
1104 /* initialize PF if max_vfs not zero */
1105 ixgbe_pf_host_init(eth_dev);
1107 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1108 /* let hardware know driver is loaded */
1109 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1110 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1111 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1112 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1113 IXGBE_WRITE_FLUSH(hw);
1115 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1116 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1117 (int) hw->mac.type, (int) hw->phy.type,
1118 (int) hw->phy.sfp_type);
1120 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1121 (int) hw->mac.type, (int) hw->phy.type);
1123 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1124 eth_dev->data->port_id, pci_dev->id.vendor_id,
1125 pci_dev->id.device_id);
1127 /* enable support intr */
1128 ixgbe_enable_intr(eth_dev);
1130 /* initialize 5tuple filter list */
1131 TAILQ_INIT(&filter_info->fivetuple_list);
1132 memset(filter_info->fivetuple_mask, 0,
1133 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1139 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1141 struct rte_pci_device *pci_dev;
1142 struct ixgbe_hw *hw;
1144 PMD_INIT_FUNC_TRACE();
1146 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1149 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1150 pci_dev = eth_dev->pci_dev;
1152 if (hw->adapter_stopped == 0)
1153 ixgbe_dev_close(eth_dev);
1155 eth_dev->dev_ops = NULL;
1156 eth_dev->rx_pkt_burst = NULL;
1157 eth_dev->tx_pkt_burst = NULL;
1159 /* Unlock any pending hardware semaphore */
1160 ixgbe_swfw_lock_reset(hw);
1162 /* disable uio intr before callback unregister */
1163 rte_intr_disable(&(pci_dev->intr_handle));
1164 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1165 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1167 /* uninitialize PF if max_vfs not zero */
1168 ixgbe_pf_host_uninit(eth_dev);
1170 rte_free(eth_dev->data->mac_addrs);
1171 eth_dev->data->mac_addrs = NULL;
1173 rte_free(eth_dev->data->hash_mac_addrs);
1174 eth_dev->data->hash_mac_addrs = NULL;
1180 * Negotiate mailbox API version with the PF.
1181 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1182 * Then we try to negotiate starting with the most recent one.
1183 * If all negotiation attempts fail, then we will proceed with
1184 * the default one (ixgbe_mbox_api_10).
1187 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1191 /* start with highest supported, proceed down */
1192 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1198 i != RTE_DIM(sup_ver) &&
1199 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1205 generate_random_mac_addr(struct ether_addr *mac_addr)
1209 /* Set Organizationally Unique Identifier (OUI) prefix. */
1210 mac_addr->addr_bytes[0] = 0x00;
1211 mac_addr->addr_bytes[1] = 0x09;
1212 mac_addr->addr_bytes[2] = 0xC0;
1213 /* Force indication of locally assigned MAC address. */
1214 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1215 /* Generate the last 3 bytes of the MAC address with a random number. */
1216 random = rte_rand();
1217 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1221 * Virtual Function device init
1224 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1228 struct rte_pci_device *pci_dev;
1229 struct ixgbe_hw *hw =
1230 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1231 struct ixgbe_vfta * shadow_vfta =
1232 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1233 struct ixgbe_hwstrip *hwstrip =
1234 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1235 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1237 PMD_INIT_FUNC_TRACE();
1239 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1240 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1241 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1243 /* for secondary processes, we don't initialise any further as primary
1244 * has already done this work. Only check we don't need a different
1246 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1247 if (eth_dev->data->scattered_rx)
1248 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1252 pci_dev = eth_dev->pci_dev;
1254 hw->device_id = pci_dev->id.device_id;
1255 hw->vendor_id = pci_dev->id.vendor_id;
1256 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1258 /* initialize the vfta */
1259 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1261 /* initialize the hw strip bitmap*/
1262 memset(hwstrip, 0, sizeof(*hwstrip));
1264 /* Initialize the shared code (base driver) */
1265 diag = ixgbe_init_shared_code(hw);
1266 if (diag != IXGBE_SUCCESS) {
1267 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1271 /* init_mailbox_params */
1272 hw->mbx.ops.init_params(hw);
1274 /* Reset the hw statistics */
1275 ixgbevf_dev_stats_reset(eth_dev);
1277 /* Disable the interrupts for VF */
1278 ixgbevf_intr_disable(hw);
1280 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1281 diag = hw->mac.ops.reset_hw(hw);
1284 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1285 * the underlying PF driver has not assigned a MAC address to the VF.
1286 * In this case, assign a random MAC address.
1288 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1289 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1293 /* negotiate mailbox API version to use with the PF. */
1294 ixgbevf_negotiate_api(hw);
1296 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1297 ixgbevf_get_queues(hw, &tcs, &tc);
1299 /* Allocate memory for storing MAC addresses */
1300 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1301 hw->mac.num_rar_entries, 0);
1302 if (eth_dev->data->mac_addrs == NULL) {
1304 "Failed to allocate %u bytes needed to store "
1306 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1310 /* Generate a random MAC address, if none was assigned by PF. */
1311 if (is_zero_ether_addr(perm_addr)) {
1312 generate_random_mac_addr(perm_addr);
1313 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1315 rte_free(eth_dev->data->mac_addrs);
1316 eth_dev->data->mac_addrs = NULL;
1319 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1320 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1321 "%02x:%02x:%02x:%02x:%02x:%02x",
1322 perm_addr->addr_bytes[0],
1323 perm_addr->addr_bytes[1],
1324 perm_addr->addr_bytes[2],
1325 perm_addr->addr_bytes[3],
1326 perm_addr->addr_bytes[4],
1327 perm_addr->addr_bytes[5]);
1330 /* Copy the permanent MAC address */
1331 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1333 /* reset the hardware with the new settings */
1334 diag = hw->mac.ops.start_hw(hw);
1340 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1344 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1345 eth_dev->data->port_id, pci_dev->id.vendor_id,
1346 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1351 /* Virtual Function device uninit */
1354 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1356 struct ixgbe_hw *hw;
1359 PMD_INIT_FUNC_TRACE();
1361 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1364 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1366 if (hw->adapter_stopped == 0)
1367 ixgbevf_dev_close(eth_dev);
1369 eth_dev->dev_ops = NULL;
1370 eth_dev->rx_pkt_burst = NULL;
1371 eth_dev->tx_pkt_burst = NULL;
1373 /* Disable the interrupts for VF */
1374 ixgbevf_intr_disable(hw);
1376 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1377 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1378 eth_dev->data->rx_queues[i] = NULL;
1380 eth_dev->data->nb_rx_queues = 0;
1382 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1383 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1384 eth_dev->data->tx_queues[i] = NULL;
1386 eth_dev->data->nb_tx_queues = 0;
1388 rte_free(eth_dev->data->mac_addrs);
1389 eth_dev->data->mac_addrs = NULL;
1394 static struct eth_driver rte_ixgbe_pmd = {
1396 .name = "rte_ixgbe_pmd",
1397 .id_table = pci_id_ixgbe_map,
1398 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1399 RTE_PCI_DRV_DETACHABLE,
1401 .eth_dev_init = eth_ixgbe_dev_init,
1402 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1403 .dev_private_size = sizeof(struct ixgbe_adapter),
1407 * virtual function driver struct
1409 static struct eth_driver rte_ixgbevf_pmd = {
1411 .name = "rte_ixgbevf_pmd",
1412 .id_table = pci_id_ixgbevf_map,
1413 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1415 .eth_dev_init = eth_ixgbevf_dev_init,
1416 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1417 .dev_private_size = sizeof(struct ixgbe_adapter),
1421 * Driver initialization routine.
1422 * Invoked once at EAL init time.
1423 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1426 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1428 PMD_INIT_FUNC_TRACE();
1430 rte_eth_driver_register(&rte_ixgbe_pmd);
1435 * VF Driver initialization routine.
1436 * Invoked one at EAL init time.
1437 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1440 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1442 PMD_INIT_FUNC_TRACE();
1444 rte_eth_driver_register(&rte_ixgbevf_pmd);
1449 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1451 struct ixgbe_hw *hw =
1452 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1453 struct ixgbe_vfta * shadow_vfta =
1454 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1459 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1460 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1461 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1466 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1468 /* update local VFTA copy */
1469 shadow_vfta->vfta[vid_idx] = vfta;
1475 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1478 ixgbe_vlan_hw_strip_enable(dev, queue);
1480 ixgbe_vlan_hw_strip_disable(dev, queue);
1484 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1486 struct ixgbe_hw *hw =
1487 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489 /* Only the high 16-bits is valid */
1490 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1494 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1496 struct ixgbe_hw *hw =
1497 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1500 PMD_INIT_FUNC_TRACE();
1502 /* Filter Table Disable */
1503 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1504 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1506 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1510 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1512 struct ixgbe_hw *hw =
1513 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1514 struct ixgbe_vfta * shadow_vfta =
1515 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1519 PMD_INIT_FUNC_TRACE();
1521 /* Filter Table Enable */
1522 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1523 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1524 vlnctrl |= IXGBE_VLNCTRL_VFE;
1526 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1528 /* write whatever is in local vfta copy */
1529 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1530 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1534 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1536 struct ixgbe_hwstrip *hwstrip =
1537 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1539 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1543 IXGBE_SET_HWSTRIP(hwstrip, queue);
1545 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1549 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1551 struct ixgbe_hw *hw =
1552 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555 PMD_INIT_FUNC_TRACE();
1557 if (hw->mac.type == ixgbe_mac_82598EB) {
1558 /* No queue level support */
1559 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1563 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1564 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1565 ctrl &= ~IXGBE_RXDCTL_VME;
1566 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1568 /* record those setting for HW strip per queue */
1569 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1573 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1575 struct ixgbe_hw *hw =
1576 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579 PMD_INIT_FUNC_TRACE();
1581 if (hw->mac.type == ixgbe_mac_82598EB) {
1582 /* No queue level supported */
1583 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1587 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1588 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1589 ctrl |= IXGBE_RXDCTL_VME;
1590 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1592 /* record those setting for HW strip per queue */
1593 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1597 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1599 struct ixgbe_hw *hw =
1600 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604 PMD_INIT_FUNC_TRACE();
1606 if (hw->mac.type == ixgbe_mac_82598EB) {
1607 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1608 ctrl &= ~IXGBE_VLNCTRL_VME;
1609 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1612 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1613 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1614 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1615 ctrl &= ~IXGBE_RXDCTL_VME;
1616 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1618 /* record those setting for HW strip per queue */
1619 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1625 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1627 struct ixgbe_hw *hw =
1628 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1632 PMD_INIT_FUNC_TRACE();
1634 if (hw->mac.type == ixgbe_mac_82598EB) {
1635 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1636 ctrl |= IXGBE_VLNCTRL_VME;
1637 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1640 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1641 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1642 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1643 ctrl |= IXGBE_RXDCTL_VME;
1644 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1646 /* record those setting for HW strip per queue */
1647 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1653 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1655 struct ixgbe_hw *hw =
1656 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659 PMD_INIT_FUNC_TRACE();
1661 /* DMATXCTRL: Geric Double VLAN Disable */
1662 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1663 ctrl &= ~IXGBE_DMATXCTL_GDV;
1664 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1666 /* CTRL_EXT: Global Double VLAN Disable */
1667 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1668 ctrl &= ~IXGBE_EXTENDED_VLAN;
1669 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1674 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1676 struct ixgbe_hw *hw =
1677 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680 PMD_INIT_FUNC_TRACE();
1682 /* DMATXCTRL: Geric Double VLAN Enable */
1683 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1684 ctrl |= IXGBE_DMATXCTL_GDV;
1685 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1687 /* CTRL_EXT: Global Double VLAN Enable */
1688 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1689 ctrl |= IXGBE_EXTENDED_VLAN;
1690 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1693 * VET EXT field in the EXVET register = 0x8100 by default
1694 * So no need to change. Same to VT field of DMATXCTL register
1699 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1701 if(mask & ETH_VLAN_STRIP_MASK){
1702 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1703 ixgbe_vlan_hw_strip_enable_all(dev);
1705 ixgbe_vlan_hw_strip_disable_all(dev);
1708 if(mask & ETH_VLAN_FILTER_MASK){
1709 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1710 ixgbe_vlan_hw_filter_enable(dev);
1712 ixgbe_vlan_hw_filter_disable(dev);
1715 if(mask & ETH_VLAN_EXTEND_MASK){
1716 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1717 ixgbe_vlan_hw_extend_enable(dev);
1719 ixgbe_vlan_hw_extend_disable(dev);
1724 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1726 struct ixgbe_hw *hw =
1727 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1728 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1729 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1730 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1731 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1735 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1740 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1743 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1749 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1750 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1756 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1758 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1759 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1760 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1762 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1763 /* check multi-queue mode */
1764 switch (dev_conf->rxmode.mq_mode) {
1765 case ETH_MQ_RX_VMDQ_DCB:
1766 case ETH_MQ_RX_VMDQ_DCB_RSS:
1767 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1768 PMD_INIT_LOG(ERR, "SRIOV active,"
1769 " unsupported mq_mode rx %d.",
1770 dev_conf->rxmode.mq_mode);
1773 case ETH_MQ_RX_VMDQ_RSS:
1774 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1775 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1776 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1777 PMD_INIT_LOG(ERR, "SRIOV is active,"
1778 " invalid queue number"
1779 " for VMDQ RSS, allowed"
1780 " value are 1, 2 or 4.");
1784 case ETH_MQ_RX_VMDQ_ONLY:
1785 case ETH_MQ_RX_NONE:
1786 /* if nothing mq mode configure, use default scheme */
1787 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1788 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1789 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1791 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1792 /* SRIOV only works in VMDq enable mode */
1793 PMD_INIT_LOG(ERR, "SRIOV is active,"
1794 " wrong mq_mode rx %d.",
1795 dev_conf->rxmode.mq_mode);
1799 switch (dev_conf->txmode.mq_mode) {
1800 case ETH_MQ_TX_VMDQ_DCB:
1801 /* DCB VMDQ in SRIOV mode, not implement yet */
1802 PMD_INIT_LOG(ERR, "SRIOV is active,"
1803 " unsupported VMDQ mq_mode tx %d.",
1804 dev_conf->txmode.mq_mode);
1806 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1807 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1811 /* check valid queue number */
1812 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1813 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1814 PMD_INIT_LOG(ERR, "SRIOV is active,"
1815 " queue number must less equal to %d.",
1816 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1820 /* check configuration for vmdb+dcb mode */
1821 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1822 const struct rte_eth_vmdq_dcb_conf *conf;
1824 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1825 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1826 IXGBE_VMDQ_DCB_NB_QUEUES);
1829 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1830 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1831 conf->nb_queue_pools == ETH_32_POOLS)) {
1832 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1833 " nb_queue_pools must be %d or %d.",
1834 ETH_16_POOLS, ETH_32_POOLS);
1838 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1839 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1841 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1842 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1843 IXGBE_VMDQ_DCB_NB_QUEUES);
1846 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1847 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1848 conf->nb_queue_pools == ETH_32_POOLS)) {
1849 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1850 " nb_queue_pools != %d and"
1851 " nb_queue_pools != %d.",
1852 ETH_16_POOLS, ETH_32_POOLS);
1857 /* For DCB mode check our configuration before we go further */
1858 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1859 const struct rte_eth_dcb_rx_conf *conf;
1861 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1862 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1863 IXGBE_DCB_NB_QUEUES);
1866 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1867 if (!(conf->nb_tcs == ETH_4_TCS ||
1868 conf->nb_tcs == ETH_8_TCS)) {
1869 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1870 " and nb_tcs != %d.",
1871 ETH_4_TCS, ETH_8_TCS);
1876 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1877 const struct rte_eth_dcb_tx_conf *conf;
1879 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1880 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1881 IXGBE_DCB_NB_QUEUES);
1884 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1885 if (!(conf->nb_tcs == ETH_4_TCS ||
1886 conf->nb_tcs == ETH_8_TCS)) {
1887 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1888 " and nb_tcs != %d.",
1889 ETH_4_TCS, ETH_8_TCS);
1898 ixgbe_dev_configure(struct rte_eth_dev *dev)
1900 struct ixgbe_interrupt *intr =
1901 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1902 struct ixgbe_adapter *adapter =
1903 (struct ixgbe_adapter *)dev->data->dev_private;
1906 PMD_INIT_FUNC_TRACE();
1907 /* multipe queue mode checking */
1908 ret = ixgbe_check_mq_mode(dev);
1910 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1915 /* set flag to update link status after init */
1916 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1919 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1920 * allocation or vector Rx preconditions we will reset it.
1922 adapter->rx_bulk_alloc_allowed = true;
1923 adapter->rx_vec_allowed = true;
1929 * Configure device link speed and setup link.
1930 * It returns 0 on success.
1933 ixgbe_dev_start(struct rte_eth_dev *dev)
1935 struct ixgbe_hw *hw =
1936 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1937 struct ixgbe_vf_info *vfinfo =
1938 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1939 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1940 uint32_t intr_vector = 0;
1941 int err, link_up = 0, negotiate = 0;
1947 PMD_INIT_FUNC_TRACE();
1949 /* IXGBE devices don't support half duplex */
1950 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1951 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1952 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1953 dev->data->dev_conf.link_duplex,
1954 dev->data->port_id);
1959 hw->adapter_stopped = 0;
1960 ixgbe_stop_adapter(hw);
1962 /* reinitialize adapter
1963 * this calls reset and start */
1964 status = ixgbe_pf_reset_hw(hw);
1967 hw->mac.ops.start_hw(hw);
1968 hw->mac.get_link_status = true;
1970 /* configure PF module if SRIOV enabled */
1971 ixgbe_pf_host_configure(dev);
1973 /* check and configure queue intr-vector mapping */
1974 if (dev->data->dev_conf.intr_conf.rxq != 0)
1975 intr_vector = dev->data->nb_rx_queues;
1977 if (rte_intr_efd_enable(intr_handle, intr_vector))
1980 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1981 intr_handle->intr_vec =
1982 rte_zmalloc("intr_vec",
1983 dev->data->nb_rx_queues * sizeof(int),
1985 if (intr_handle->intr_vec == NULL) {
1986 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1987 " intr_vec\n", dev->data->nb_rx_queues);
1992 /* confiugre msix for sleep until rx interrupt */
1993 ixgbe_configure_msix(dev);
1995 /* initialize transmission unit */
1996 ixgbe_dev_tx_init(dev);
1998 /* This can fail when allocating mbufs for descriptor rings */
1999 err = ixgbe_dev_rx_init(dev);
2001 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2005 err = ixgbe_dev_rxtx_start(dev);
2007 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2011 /* Skip link setup if loopback mode is enabled for 82599. */
2012 if (hw->mac.type == ixgbe_mac_82599EB &&
2013 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2014 goto skip_link_setup;
2016 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2017 err = hw->mac.ops.setup_sfp(hw);
2022 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2023 /* Turn on the copper */
2024 ixgbe_set_phy_power(hw, true);
2026 /* Turn on the laser */
2027 ixgbe_enable_tx_laser(hw);
2030 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2033 dev->data->dev_link.link_status = link_up;
2035 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2039 switch(dev->data->dev_conf.link_speed) {
2040 case ETH_LINK_SPEED_AUTONEG:
2041 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2042 IXGBE_LINK_SPEED_82599_AUTONEG :
2043 IXGBE_LINK_SPEED_82598_AUTONEG;
2045 case ETH_LINK_SPEED_100:
2047 * Invalid for 82598 but error will be detected by
2048 * ixgbe_setup_link()
2050 speed = IXGBE_LINK_SPEED_100_FULL;
2052 case ETH_LINK_SPEED_1000:
2053 speed = IXGBE_LINK_SPEED_1GB_FULL;
2055 case ETH_LINK_SPEED_10000:
2056 speed = IXGBE_LINK_SPEED_10GB_FULL;
2059 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2060 dev->data->dev_conf.link_speed,
2061 dev->data->port_id);
2065 err = ixgbe_setup_link(hw, speed, link_up);
2071 /* check if lsc interrupt is enabled */
2072 if (dev->data->dev_conf.intr_conf.lsc != 0) {
2073 if (rte_intr_allow_others(intr_handle)) {
2074 rte_intr_callback_register(intr_handle,
2075 ixgbe_dev_interrupt_handler,
2077 ixgbe_dev_lsc_interrupt_setup(dev);
2079 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2080 " no intr multiplex\n");
2083 /* check if rxq interrupt is enabled */
2084 if (dev->data->dev_conf.intr_conf.rxq != 0)
2085 ixgbe_dev_rxq_interrupt_setup(dev);
2087 /* enable uio/vfio intr/eventfd mapping */
2088 rte_intr_enable(intr_handle);
2090 /* resume enabled intr since hw reset */
2091 ixgbe_enable_intr(dev);
2093 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2094 ETH_VLAN_EXTEND_MASK;
2095 ixgbe_vlan_offload_set(dev, mask);
2097 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2098 /* Enable vlan filtering for VMDq */
2099 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2102 /* Configure DCB hw */
2103 ixgbe_configure_dcb(dev);
2105 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2106 err = ixgbe_fdir_configure(dev);
2111 /* Restore vf rate limit */
2112 if (vfinfo != NULL) {
2113 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2114 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2115 if (vfinfo[vf].tx_rate[idx] != 0)
2116 ixgbe_set_vf_rate_limit(dev, vf,
2117 vfinfo[vf].tx_rate[idx],
2121 ixgbe_restore_statistics_mapping(dev);
2126 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2127 ixgbe_dev_clear_queues(dev);
2132 * Stop device: disable rx and tx functions to allow for reconfiguring.
2135 ixgbe_dev_stop(struct rte_eth_dev *dev)
2137 struct rte_eth_link link;
2138 struct ixgbe_hw *hw =
2139 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2140 struct ixgbe_vf_info *vfinfo =
2141 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2142 struct ixgbe_filter_info *filter_info =
2143 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2144 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2145 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2148 PMD_INIT_FUNC_TRACE();
2150 /* disable interrupts */
2151 ixgbe_disable_intr(hw);
2153 /* disable intr eventfd mapping */
2154 rte_intr_disable(intr_handle);
2157 ixgbe_pf_reset_hw(hw);
2158 hw->adapter_stopped = 0;
2161 ixgbe_stop_adapter(hw);
2163 for (vf = 0; vfinfo != NULL &&
2164 vf < dev->pci_dev->max_vfs; vf++)
2165 vfinfo[vf].clear_to_send = false;
2167 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2168 /* Turn off the copper */
2169 ixgbe_set_phy_power(hw, false);
2171 /* Turn off the laser */
2172 ixgbe_disable_tx_laser(hw);
2175 ixgbe_dev_clear_queues(dev);
2177 /* Clear stored conf */
2178 dev->data->scattered_rx = 0;
2181 /* Clear recorded link status */
2182 memset(&link, 0, sizeof(link));
2183 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2185 /* Remove all ntuple filters of the device */
2186 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2187 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2188 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2189 TAILQ_REMOVE(&filter_info->fivetuple_list,
2193 memset(filter_info->fivetuple_mask, 0,
2194 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2196 /* Clean datapath event and queue/vec mapping */
2197 rte_intr_efd_disable(intr_handle);
2198 if (intr_handle->intr_vec != NULL) {
2199 rte_free(intr_handle->intr_vec);
2200 intr_handle->intr_vec = NULL;
2205 * Set device link up: enable tx.
2208 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2210 struct ixgbe_hw *hw =
2211 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212 if (hw->mac.type == ixgbe_mac_82599EB) {
2213 #ifdef RTE_NIC_BYPASS
2214 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2215 /* Not suported in bypass mode */
2216 PMD_INIT_LOG(ERR, "Set link up is not supported "
2217 "by device id 0x%x", hw->device_id);
2223 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2224 /* Turn on the copper */
2225 ixgbe_set_phy_power(hw, true);
2227 /* Turn on the laser */
2228 ixgbe_enable_tx_laser(hw);
2235 * Set device link down: disable tx.
2238 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2240 struct ixgbe_hw *hw =
2241 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242 if (hw->mac.type == ixgbe_mac_82599EB) {
2243 #ifdef RTE_NIC_BYPASS
2244 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2245 /* Not suported in bypass mode */
2246 PMD_INIT_LOG(ERR, "Set link down is not supported "
2247 "by device id 0x%x", hw->device_id);
2253 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2254 /* Turn off the copper */
2255 ixgbe_set_phy_power(hw, false);
2257 /* Turn off the laser */
2258 ixgbe_disable_tx_laser(hw);
2265 * Reest and stop device.
2268 ixgbe_dev_close(struct rte_eth_dev *dev)
2270 struct ixgbe_hw *hw =
2271 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2273 PMD_INIT_FUNC_TRACE();
2275 ixgbe_pf_reset_hw(hw);
2277 ixgbe_dev_stop(dev);
2278 hw->adapter_stopped = 1;
2280 ixgbe_dev_free_queues(dev);
2282 ixgbe_disable_pcie_master(hw);
2284 /* reprogram the RAR[0] in case user changed it. */
2285 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2289 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2290 *hw_stats, uint64_t *total_missed_rx,
2291 uint64_t *total_qbrc, uint64_t *total_qprc,
2292 uint64_t *total_qprdc)
2294 uint32_t bprc, lxon, lxoff, total;
2297 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2298 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2299 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2300 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2302 for (i = 0; i < 8; i++) {
2304 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2305 /* global total per queue */
2306 hw_stats->mpc[i] += mp;
2307 /* Running comprehensive total for stats display */
2308 *total_missed_rx += hw_stats->mpc[i];
2309 if (hw->mac.type == ixgbe_mac_82598EB) {
2310 hw_stats->rnbc[i] +=
2311 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2312 hw_stats->pxonrxc[i] +=
2313 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2314 hw_stats->pxoffrxc[i] +=
2315 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2317 hw_stats->pxonrxc[i] +=
2318 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2319 hw_stats->pxoffrxc[i] +=
2320 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2321 hw_stats->pxon2offc[i] +=
2322 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2324 hw_stats->pxontxc[i] +=
2325 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2326 hw_stats->pxofftxc[i] +=
2327 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2329 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2330 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2331 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2332 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2333 hw_stats->qbrc[i] +=
2334 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2335 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2336 hw_stats->qbtc[i] +=
2337 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2338 *total_qprdc += hw_stats->qprdc[i] +=
2339 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2341 *total_qprc += hw_stats->qprc[i];
2342 *total_qbrc += hw_stats->qbrc[i];
2344 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2345 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2346 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2348 /* Note that gprc counts missed packets */
2349 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2351 if (hw->mac.type != ixgbe_mac_82598EB) {
2352 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2353 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2354 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2355 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2356 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2357 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2358 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2359 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2361 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2362 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2363 /* 82598 only has a counter in the high register */
2364 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2365 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2366 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2370 * Workaround: mprc hardware is incorrectly counting
2371 * broadcasts, so for now we subtract those.
2373 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2374 hw_stats->bprc += bprc;
2375 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2376 if (hw->mac.type == ixgbe_mac_82598EB)
2377 hw_stats->mprc -= bprc;
2379 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2380 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2381 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2382 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2383 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2384 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2386 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2387 hw_stats->lxontxc += lxon;
2388 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2389 hw_stats->lxofftxc += lxoff;
2390 total = lxon + lxoff;
2392 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2393 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2394 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2395 hw_stats->gptc -= total;
2396 hw_stats->mptc -= total;
2397 hw_stats->ptc64 -= total;
2398 hw_stats->gotc -= total * ETHER_MIN_LEN;
2400 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2401 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2402 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2403 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2404 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2405 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2406 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2407 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2408 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2409 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2410 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2411 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2412 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2413 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2414 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2415 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2416 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2417 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2418 /* Only read FCOE on 82599 */
2419 if (hw->mac.type != ixgbe_mac_82598EB) {
2420 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2421 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2422 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2423 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2424 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2427 /* Flow Director Stats registers */
2428 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2429 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2433 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2436 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2438 struct ixgbe_hw *hw =
2439 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2440 struct ixgbe_hw_stats *hw_stats =
2441 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2442 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2445 total_missed_rx = 0;
2450 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2451 &total_qprc, &total_qprdc);
2456 /* Fill out the rte_eth_stats statistics structure */
2457 stats->ipackets = total_qprc;
2458 stats->ibytes = total_qbrc;
2459 stats->opackets = hw_stats->gptc;
2460 stats->obytes = hw_stats->gotc;
2462 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2463 stats->q_ipackets[i] = hw_stats->qprc[i];
2464 stats->q_opackets[i] = hw_stats->qptc[i];
2465 stats->q_ibytes[i] = hw_stats->qbrc[i];
2466 stats->q_obytes[i] = hw_stats->qbtc[i];
2467 stats->q_errors[i] = hw_stats->qprdc[i];
2471 stats->ierrors = hw_stats->crcerrs +
2491 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2493 struct ixgbe_hw_stats *stats =
2494 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2496 /* HW registers are cleared on read */
2497 ixgbe_dev_stats_get(dev, NULL);
2499 /* Reset software totals */
2500 memset(stats, 0, sizeof(*stats));
2504 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2507 struct ixgbe_hw *hw =
2508 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2509 struct ixgbe_hw_stats *hw_stats =
2510 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2511 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2512 unsigned i, count = IXGBE_NB_XSTATS;
2517 total_missed_rx = 0;
2522 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2523 &total_qprc, &total_qprdc);
2525 /* If this is a reset xstats is NULL, and we have cleared the
2526 * registers by reading them.
2531 /* Extended stats from ixgbe_hw_stats */
2533 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2534 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2535 rte_ixgbe_stats_strings[i].name);
2536 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2537 rte_ixgbe_stats_strings[i].offset);
2541 /* Per-Q stats, with 8 queues available */
2542 for (i = 0; i < 8; i++) {
2543 snprintf(xstats[count].name, sizeof(xstats[count].name),
2544 "rx_q%u_mbuf_allocation_errors", i);
2545 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2546 offsetof(struct ixgbe_hw_stats, rnbc[i]));
2549 snprintf(xstats[count].name, sizeof(xstats[count].name),
2550 "rx_q%u_missed_packets", i);
2551 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2552 offsetof(struct ixgbe_hw_stats, mpc[i]));
2555 snprintf(xstats[count].name, sizeof(xstats[count].name),
2556 "rx_q%u_xon_priority_packets", i);
2557 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2558 offsetof(struct ixgbe_hw_stats, pxonrxc[i]));
2561 snprintf(xstats[count].name, sizeof(xstats[count].name),
2562 "tx_q%u_xon_priority_packets", i);
2563 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2564 offsetof(struct ixgbe_hw_stats, pxontxc[i]));
2567 snprintf(xstats[count].name, sizeof(xstats[count].name),
2568 "rx_q%u_xoff_priority_packets", i);
2569 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2570 offsetof(struct ixgbe_hw_stats, pxoffrxc[i]));
2573 snprintf(xstats[count].name, sizeof(xstats[count].name),
2574 "tx_q%u_xoff_priority_packets", i);
2575 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2576 offsetof(struct ixgbe_hw_stats, pxofftxc[i]));
2579 snprintf(xstats[count].name, sizeof(xstats[count].name),
2580 "xx_q%u_xon_to_xoff_priority_packets", i);
2581 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2582 offsetof(struct ixgbe_hw_stats, pxon2offc[i]));
2586 for (i = 0; i < 16; i++) {
2587 snprintf(xstats[count].name, sizeof(xstats[count].name),
2588 "rx_q%u_packets", i);
2589 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2590 offsetof(struct ixgbe_hw_stats, qprc[i]));
2593 snprintf(xstats[count].name, sizeof(xstats[count].name),
2595 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2596 offsetof(struct ixgbe_hw_stats, qbrc[i]));
2599 snprintf(xstats[count].name, sizeof(xstats[count].name),
2600 "tx_q%u_packets", i);
2601 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2602 offsetof(struct ixgbe_hw_stats, qptc[i]));
2605 snprintf(xstats[count].name, sizeof(xstats[count].name),
2607 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2608 offsetof(struct ixgbe_hw_stats, qbtc[i]));
2611 snprintf(xstats[count].name, sizeof(xstats[count].name),
2612 "rx_q%u_dropped", i);
2613 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2614 offsetof(struct ixgbe_hw_stats, qprdc[i]));
2622 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2624 struct ixgbe_hw_stats *stats =
2625 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2627 /* HW registers are cleared on read */
2628 ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2630 /* Reset software totals */
2631 memset(stats, 0, sizeof(*stats));
2635 ixgbevf_update_stats(struct rte_eth_dev *dev)
2637 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2638 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2639 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2641 /* Good Rx packet, include VF loopback */
2642 UPDATE_VF_STAT(IXGBE_VFGPRC,
2643 hw_stats->last_vfgprc, hw_stats->vfgprc);
2645 /* Good Rx octets, include VF loopback */
2646 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2647 hw_stats->last_vfgorc, hw_stats->vfgorc);
2649 /* Good Tx packet, include VF loopback */
2650 UPDATE_VF_STAT(IXGBE_VFGPTC,
2651 hw_stats->last_vfgptc, hw_stats->vfgptc);
2653 /* Good Tx octets, include VF loopback */
2654 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2655 hw_stats->last_vfgotc, hw_stats->vfgotc);
2657 /* Rx Multicst Packet */
2658 UPDATE_VF_STAT(IXGBE_VFMPRC,
2659 hw_stats->last_vfmprc, hw_stats->vfmprc);
2663 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2666 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2667 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2670 if (n < IXGBEVF_NB_XSTATS)
2671 return IXGBEVF_NB_XSTATS;
2673 ixgbevf_update_stats(dev);
2678 /* Extended stats */
2679 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2680 snprintf(xstats[i].name, sizeof(xstats[i].name),
2681 "%s", rte_ixgbevf_stats_strings[i].name);
2682 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2683 rte_ixgbevf_stats_strings[i].offset);
2686 return IXGBEVF_NB_XSTATS;
2690 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2692 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2693 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2695 ixgbevf_update_stats(dev);
2700 stats->ipackets = hw_stats->vfgprc;
2701 stats->ibytes = hw_stats->vfgorc;
2702 stats->opackets = hw_stats->vfgptc;
2703 stats->obytes = hw_stats->vfgotc;
2704 stats->imcasts = hw_stats->vfmprc;
2705 /* stats->imcasts should be removed as imcasts is deprecated */
2709 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2711 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2712 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2714 /* Sync HW register to the last stats */
2715 ixgbevf_dev_stats_get(dev, NULL);
2717 /* reset HW current stats*/
2718 hw_stats->vfgprc = 0;
2719 hw_stats->vfgorc = 0;
2720 hw_stats->vfgptc = 0;
2721 hw_stats->vfgotc = 0;
2722 hw_stats->vfmprc = 0;
2727 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2729 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2731 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2732 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2733 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2734 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2735 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2736 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2737 dev_info->max_vfs = dev->pci_dev->max_vfs;
2738 if (hw->mac.type == ixgbe_mac_82598EB)
2739 dev_info->max_vmdq_pools = ETH_16_POOLS;
2741 dev_info->max_vmdq_pools = ETH_64_POOLS;
2742 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2743 dev_info->rx_offload_capa =
2744 DEV_RX_OFFLOAD_VLAN_STRIP |
2745 DEV_RX_OFFLOAD_IPV4_CKSUM |
2746 DEV_RX_OFFLOAD_UDP_CKSUM |
2747 DEV_RX_OFFLOAD_TCP_CKSUM;
2750 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2753 if ((hw->mac.type == ixgbe_mac_82599EB ||
2754 hw->mac.type == ixgbe_mac_X540) &&
2755 !RTE_ETH_DEV_SRIOV(dev).active)
2756 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2758 dev_info->tx_offload_capa =
2759 DEV_TX_OFFLOAD_VLAN_INSERT |
2760 DEV_TX_OFFLOAD_IPV4_CKSUM |
2761 DEV_TX_OFFLOAD_UDP_CKSUM |
2762 DEV_TX_OFFLOAD_TCP_CKSUM |
2763 DEV_TX_OFFLOAD_SCTP_CKSUM |
2764 DEV_TX_OFFLOAD_TCP_TSO;
2766 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2768 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2769 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2770 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2772 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2776 dev_info->default_txconf = (struct rte_eth_txconf) {
2778 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2779 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2780 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2782 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2783 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2784 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2785 ETH_TXQ_FLAGS_NOOFFLOADS,
2788 dev_info->rx_desc_lim = rx_desc_lim;
2789 dev_info->tx_desc_lim = tx_desc_lim;
2791 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2792 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2793 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2797 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2798 struct rte_eth_dev_info *dev_info)
2800 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2802 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2803 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2804 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2805 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2806 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2807 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2808 dev_info->max_vfs = dev->pci_dev->max_vfs;
2809 if (hw->mac.type == ixgbe_mac_82598EB)
2810 dev_info->max_vmdq_pools = ETH_16_POOLS;
2812 dev_info->max_vmdq_pools = ETH_64_POOLS;
2813 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2814 DEV_RX_OFFLOAD_IPV4_CKSUM |
2815 DEV_RX_OFFLOAD_UDP_CKSUM |
2816 DEV_RX_OFFLOAD_TCP_CKSUM;
2817 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2818 DEV_TX_OFFLOAD_IPV4_CKSUM |
2819 DEV_TX_OFFLOAD_UDP_CKSUM |
2820 DEV_TX_OFFLOAD_TCP_CKSUM |
2821 DEV_TX_OFFLOAD_SCTP_CKSUM |
2822 DEV_TX_OFFLOAD_TCP_TSO;
2824 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2826 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2827 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2828 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2830 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2834 dev_info->default_txconf = (struct rte_eth_txconf) {
2836 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2837 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2838 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2840 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2841 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2842 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2843 ETH_TXQ_FLAGS_NOOFFLOADS,
2846 dev_info->rx_desc_lim = rx_desc_lim;
2847 dev_info->tx_desc_lim = tx_desc_lim;
2850 /* return 0 means link status changed, -1 means not changed */
2852 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2854 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855 struct rte_eth_link link, old;
2856 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2860 link.link_status = 0;
2861 link.link_speed = 0;
2862 link.link_duplex = 0;
2863 memset(&old, 0, sizeof(old));
2864 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2866 hw->mac.get_link_status = true;
2868 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2869 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2870 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2872 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2875 link.link_speed = ETH_LINK_SPEED_100;
2876 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2877 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2878 if (link.link_status == old.link_status)
2884 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2885 if (link.link_status == old.link_status)
2889 link.link_status = 1;
2890 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2892 switch (link_speed) {
2894 case IXGBE_LINK_SPEED_UNKNOWN:
2895 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2896 link.link_speed = ETH_LINK_SPEED_100;
2899 case IXGBE_LINK_SPEED_100_FULL:
2900 link.link_speed = ETH_LINK_SPEED_100;
2903 case IXGBE_LINK_SPEED_1GB_FULL:
2904 link.link_speed = ETH_LINK_SPEED_1000;
2907 case IXGBE_LINK_SPEED_10GB_FULL:
2908 link.link_speed = ETH_LINK_SPEED_10000;
2911 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2913 if (link.link_status == old.link_status)
2920 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2922 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2925 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2926 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2927 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2931 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2933 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2937 fctrl &= (~IXGBE_FCTRL_UPE);
2938 if (dev->data->all_multicast == 1)
2939 fctrl |= IXGBE_FCTRL_MPE;
2941 fctrl &= (~IXGBE_FCTRL_MPE);
2942 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2946 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2948 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2951 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2952 fctrl |= IXGBE_FCTRL_MPE;
2953 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2957 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2959 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962 if (dev->data->promiscuous == 1)
2963 return; /* must remain in all_multicast mode */
2965 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2966 fctrl &= (~IXGBE_FCTRL_MPE);
2967 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2971 * It clears the interrupt causes and enables the interrupt.
2972 * It will be called once only during nic initialized.
2975 * Pointer to struct rte_eth_dev.
2978 * - On success, zero.
2979 * - On failure, a negative value.
2982 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2984 struct ixgbe_interrupt *intr =
2985 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2987 ixgbe_dev_link_status_print(dev);
2988 intr->mask |= IXGBE_EICR_LSC;
2994 * It clears the interrupt causes and enables the interrupt.
2995 * It will be called once only during nic initialized.
2998 * Pointer to struct rte_eth_dev.
3001 * - On success, zero.
3002 * - On failure, a negative value.
3005 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3007 struct ixgbe_interrupt *intr =
3008 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3010 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3016 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3019 * Pointer to struct rte_eth_dev.
3022 * - On success, zero.
3023 * - On failure, a negative value.
3026 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3029 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030 struct ixgbe_interrupt *intr =
3031 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3033 /* clear all cause mask */
3034 ixgbe_disable_intr(hw);
3036 /* read-on-clear nic registers here */
3037 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3038 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3042 /* set flag for async link update */
3043 if (eicr & IXGBE_EICR_LSC)
3044 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3046 if (eicr & IXGBE_EICR_MAILBOX)
3047 intr->flags |= IXGBE_FLAG_MAILBOX;
3053 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
3056 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3057 struct ixgbe_interrupt *intr =
3058 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3060 /* clear all cause mask */
3061 ixgbevf_intr_disable(hw);
3063 /* read-on-clear nic registers here */
3064 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
3065 PMD_DRV_LOG(INFO, "eicr %x", eicr);
3069 /* set flag for async link update */
3070 if (eicr & IXGBE_EICR_LSC)
3071 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3077 * It gets and then prints the link status.
3080 * Pointer to struct rte_eth_dev.
3083 * - On success, zero.
3084 * - On failure, a negative value.
3087 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3089 struct rte_eth_link link;
3091 memset(&link, 0, sizeof(link));
3092 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3093 if (link.link_status) {
3094 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3095 (int)(dev->data->port_id),
3096 (unsigned)link.link_speed,
3097 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3098 "full-duplex" : "half-duplex");
3100 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3101 (int)(dev->data->port_id));
3103 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3104 dev->pci_dev->addr.domain,
3105 dev->pci_dev->addr.bus,
3106 dev->pci_dev->addr.devid,
3107 dev->pci_dev->addr.function);
3111 * It executes link_update after knowing an interrupt occurred.
3114 * Pointer to struct rte_eth_dev.
3117 * - On success, zero.
3118 * - On failure, a negative value.
3121 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3123 struct ixgbe_interrupt *intr =
3124 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3126 struct rte_eth_link link;
3127 int intr_enable_delay = false;
3129 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3131 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3132 ixgbe_pf_mbx_process(dev);
3133 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3136 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3137 /* get the link status before link update, for predicting later */
3138 memset(&link, 0, sizeof(link));
3139 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3141 ixgbe_dev_link_update(dev, 0);
3144 if (!link.link_status)
3145 /* handle it 1 sec later, wait it being stable */
3146 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3147 /* likely to down */
3149 /* handle it 4 sec later, wait it being stable */
3150 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3152 ixgbe_dev_link_status_print(dev);
3154 intr_enable_delay = true;
3157 if (intr_enable_delay) {
3158 if (rte_eal_alarm_set(timeout * 1000,
3159 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3160 PMD_DRV_LOG(ERR, "Error setting alarm");
3162 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3163 ixgbe_enable_intr(dev);
3164 rte_intr_enable(&(dev->pci_dev->intr_handle));
3172 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
3174 struct ixgbe_hw *hw =
3175 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3177 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3178 ixgbevf_intr_enable(hw);
3179 rte_intr_enable(&dev->pci_dev->intr_handle);
3184 * Interrupt handler which shall be registered for alarm callback for delayed
3185 * handling specific interrupt to wait for the stable nic state. As the
3186 * NIC interrupt state is not stable for ixgbe after link is just down,
3187 * it needs to wait 4 seconds to get the stable status.
3190 * Pointer to interrupt handle.
3192 * The address of parameter (struct rte_eth_dev *) regsitered before.
3198 ixgbe_dev_interrupt_delayed_handler(void *param)
3200 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3201 struct ixgbe_interrupt *intr =
3202 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3203 struct ixgbe_hw *hw =
3204 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3207 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3208 if (eicr & IXGBE_EICR_MAILBOX)
3209 ixgbe_pf_mbx_process(dev);
3211 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3212 ixgbe_dev_link_update(dev, 0);
3213 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3214 ixgbe_dev_link_status_print(dev);
3215 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3218 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3219 ixgbe_enable_intr(dev);
3220 rte_intr_enable(&(dev->pci_dev->intr_handle));
3224 * Interrupt handler triggered by NIC for handling
3225 * specific interrupt.
3228 * Pointer to interrupt handle.
3230 * The address of parameter (struct rte_eth_dev *) regsitered before.
3236 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3239 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3241 ixgbe_dev_interrupt_get_status(dev);
3242 ixgbe_dev_interrupt_action(dev);
3246 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3249 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3251 ixgbevf_dev_interrupt_get_status(dev);
3252 ixgbevf_dev_interrupt_action(dev);
3256 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3258 struct ixgbe_hw *hw;
3260 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3261 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3265 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3267 struct ixgbe_hw *hw;
3269 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3270 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3274 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3276 struct ixgbe_hw *hw;
3282 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3284 fc_conf->pause_time = hw->fc.pause_time;
3285 fc_conf->high_water = hw->fc.high_water[0];
3286 fc_conf->low_water = hw->fc.low_water[0];
3287 fc_conf->send_xon = hw->fc.send_xon;
3288 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3291 * Return rx_pause status according to actual setting of
3294 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3295 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3301 * Return tx_pause status according to actual setting of
3304 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3305 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3310 if (rx_pause && tx_pause)
3311 fc_conf->mode = RTE_FC_FULL;
3313 fc_conf->mode = RTE_FC_RX_PAUSE;
3315 fc_conf->mode = RTE_FC_TX_PAUSE;
3317 fc_conf->mode = RTE_FC_NONE;
3323 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3325 struct ixgbe_hw *hw;
3327 uint32_t rx_buf_size;
3328 uint32_t max_high_water;
3330 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3337 PMD_INIT_FUNC_TRACE();
3339 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3341 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3344 * At least reserve one Ethernet frame for watermark
3345 * high_water/low_water in kilo bytes for ixgbe
3347 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3348 if ((fc_conf->high_water > max_high_water) ||
3349 (fc_conf->high_water < fc_conf->low_water)) {
3350 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3351 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3355 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3356 hw->fc.pause_time = fc_conf->pause_time;
3357 hw->fc.high_water[0] = fc_conf->high_water;
3358 hw->fc.low_water[0] = fc_conf->low_water;
3359 hw->fc.send_xon = fc_conf->send_xon;
3360 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3362 err = ixgbe_fc_enable(hw);
3364 /* Not negotiated is not an error case */
3365 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3367 /* check if we want to forward MAC frames - driver doesn't have native
3368 * capability to do that, so we'll write the registers ourselves */
3370 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3372 /* set or clear MFLCN.PMCF bit depending on configuration */
3373 if (fc_conf->mac_ctrl_frame_fwd != 0)
3374 mflcn |= IXGBE_MFLCN_PMCF;
3376 mflcn &= ~IXGBE_MFLCN_PMCF;
3378 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3379 IXGBE_WRITE_FLUSH(hw);
3384 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3389 * ixgbe_pfc_enable_generic - Enable flow control
3390 * @hw: pointer to hardware structure
3391 * @tc_num: traffic class number
3392 * Enable flow control according to the current settings.
3395 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3398 uint32_t mflcn_reg, fccfg_reg;
3400 uint32_t fcrtl, fcrth;
3404 /* Validate the water mark configuration */
3405 if (!hw->fc.pause_time) {
3406 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3410 /* Low water mark of zero causes XOFF floods */
3411 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3412 /* High/Low water can not be 0 */
3413 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3414 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3415 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3419 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3420 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3421 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3425 /* Negotiate the fc mode to use */
3426 ixgbe_fc_autoneg(hw);
3428 /* Disable any previous flow control settings */
3429 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3430 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3432 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3433 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3435 switch (hw->fc.current_mode) {
3438 * If the count of enabled RX Priority Flow control >1,
3439 * and the TX pause can not be disabled
3442 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3443 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3444 if (reg & IXGBE_FCRTH_FCEN)
3448 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3450 case ixgbe_fc_rx_pause:
3452 * Rx Flow control is enabled and Tx Flow control is
3453 * disabled by software override. Since there really
3454 * isn't a way to advertise that we are capable of RX
3455 * Pause ONLY, we will advertise that we support both
3456 * symmetric and asymmetric Rx PAUSE. Later, we will
3457 * disable the adapter's ability to send PAUSE frames.
3459 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3461 * If the count of enabled RX Priority Flow control >1,
3462 * and the TX pause can not be disabled
3465 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3466 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3467 if (reg & IXGBE_FCRTH_FCEN)
3471 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3473 case ixgbe_fc_tx_pause:
3475 * Tx Flow control is enabled, and Rx Flow control is
3476 * disabled by software override.
3478 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3481 /* Flow control (both Rx and Tx) is enabled by SW override. */
3482 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3483 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3486 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3487 ret_val = IXGBE_ERR_CONFIG;
3492 /* Set 802.3x based flow control settings. */
3493 mflcn_reg |= IXGBE_MFLCN_DPF;
3494 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3495 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3497 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3498 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3499 hw->fc.high_water[tc_num]) {
3500 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3501 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3502 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3504 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3506 * In order to prevent Tx hangs when the internal Tx
3507 * switch is enabled we must set the high water mark
3508 * to the maximum FCRTH value. This allows the Tx
3509 * switch to function even under heavy Rx workloads.
3511 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3513 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3515 /* Configure pause time (2 TCs per register) */
3516 reg = hw->fc.pause_time * 0x00010001;
3517 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3518 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3520 /* Configure flow control refresh threshold value */
3521 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3528 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3530 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3531 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3533 if(hw->mac.type != ixgbe_mac_82598EB) {
3534 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3540 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3543 uint32_t rx_buf_size;
3544 uint32_t max_high_water;
3546 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3547 struct ixgbe_hw *hw =
3548 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3549 struct ixgbe_dcb_config *dcb_config =
3550 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3552 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3559 PMD_INIT_FUNC_TRACE();
3561 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3562 tc_num = map[pfc_conf->priority];
3563 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3564 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3566 * At least reserve one Ethernet frame for watermark
3567 * high_water/low_water in kilo bytes for ixgbe
3569 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3570 if ((pfc_conf->fc.high_water > max_high_water) ||
3571 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3572 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3573 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3577 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3578 hw->fc.pause_time = pfc_conf->fc.pause_time;
3579 hw->fc.send_xon = pfc_conf->fc.send_xon;
3580 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3581 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3583 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3585 /* Not negotiated is not an error case */
3586 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3589 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3594 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3595 struct rte_eth_rss_reta_entry64 *reta_conf,
3600 uint16_t idx, shift;
3601 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3602 uint16_t sp_reta_size;
3605 PMD_INIT_FUNC_TRACE();
3607 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3608 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3613 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3614 if (reta_size != sp_reta_size) {
3615 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3616 "(%d) doesn't match the number hardware can supported "
3617 "(%d)\n", reta_size, sp_reta_size);
3621 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3622 idx = i / RTE_RETA_GROUP_SIZE;
3623 shift = i % RTE_RETA_GROUP_SIZE;
3624 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3628 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3629 if (mask == IXGBE_4_BIT_MASK)
3632 r = IXGBE_READ_REG(hw, reta_reg);
3633 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3634 if (mask & (0x1 << j))
3635 reta |= reta_conf[idx].reta[shift + j] <<
3638 reta |= r & (IXGBE_8_BIT_MASK <<
3641 IXGBE_WRITE_REG(hw, reta_reg, reta);
3648 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3649 struct rte_eth_rss_reta_entry64 *reta_conf,
3654 uint16_t idx, shift;
3655 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3656 uint16_t sp_reta_size;
3659 PMD_INIT_FUNC_TRACE();
3660 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3661 if (reta_size != sp_reta_size) {
3662 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3663 "(%d) doesn't match the number hardware can supported "
3664 "(%d)\n", reta_size, sp_reta_size);
3668 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3669 idx = i / RTE_RETA_GROUP_SIZE;
3670 shift = i % RTE_RETA_GROUP_SIZE;
3671 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3676 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3677 reta = IXGBE_READ_REG(hw, reta_reg);
3678 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3679 if (mask & (0x1 << j))
3680 reta_conf[idx].reta[shift + j] =
3681 ((reta >> (CHAR_BIT * j)) &
3690 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3691 uint32_t index, uint32_t pool)
3693 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3694 uint32_t enable_addr = 1;
3696 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3700 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3702 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3704 ixgbe_clear_rar(hw, index);
3708 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3710 ixgbe_remove_rar(dev, 0);
3712 ixgbe_add_rar(dev, addr, 0, 0);
3716 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3720 struct ixgbe_hw *hw;
3721 struct rte_eth_dev_info dev_info;
3722 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3724 ixgbe_dev_info_get(dev, &dev_info);
3726 /* check that mtu is within the allowed range */
3727 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3730 /* refuse mtu that requires the support of scattered packets when this
3731 * feature has not been enabled before. */
3732 if (!dev->data->scattered_rx &&
3733 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3734 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3737 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3738 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3740 /* switch to jumbo mode if needed */
3741 if (frame_size > ETHER_MAX_LEN) {
3742 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3743 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3745 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3746 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3748 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3750 /* update max frame size */
3751 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3753 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3754 maxfrs &= 0x0000FFFF;
3755 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3756 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3762 * Virtual Function operations
3765 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3767 PMD_INIT_FUNC_TRACE();
3769 /* Clear interrupt mask to stop from interrupts being generated */
3770 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3772 IXGBE_WRITE_FLUSH(hw);
3776 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3778 PMD_INIT_FUNC_TRACE();
3780 /* VF enable interrupt autoclean */
3781 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3782 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3783 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3785 IXGBE_WRITE_FLUSH(hw);
3789 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3791 struct rte_eth_conf* conf = &dev->data->dev_conf;
3792 struct ixgbe_adapter *adapter =
3793 (struct ixgbe_adapter *)dev->data->dev_private;
3795 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3796 dev->data->port_id);
3799 * VF has no ability to enable/disable HW CRC
3800 * Keep the persistent behavior the same as Host PF
3802 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3803 if (!conf->rxmode.hw_strip_crc) {
3804 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3805 conf->rxmode.hw_strip_crc = 1;
3808 if (conf->rxmode.hw_strip_crc) {
3809 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3810 conf->rxmode.hw_strip_crc = 0;
3815 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3816 * allocation or vector Rx preconditions we will reset it.
3818 adapter->rx_bulk_alloc_allowed = true;
3819 adapter->rx_vec_allowed = true;
3825 ixgbevf_dev_start(struct rte_eth_dev *dev)
3827 struct ixgbe_hw *hw =
3828 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3829 uint32_t intr_vector = 0;
3830 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3834 PMD_INIT_FUNC_TRACE();
3836 hw->mac.ops.reset_hw(hw);
3837 hw->mac.get_link_status = true;
3839 /* negotiate mailbox API version to use with the PF. */
3840 ixgbevf_negotiate_api(hw);
3842 ixgbevf_dev_tx_init(dev);
3844 /* This can fail when allocating mbufs for descriptor rings */
3845 err = ixgbevf_dev_rx_init(dev);
3847 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3848 ixgbe_dev_clear_queues(dev);
3853 ixgbevf_set_vfta_all(dev,1);
3856 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3857 ETH_VLAN_EXTEND_MASK;
3858 ixgbevf_vlan_offload_set(dev, mask);
3860 ixgbevf_dev_rxtx_start(dev);
3862 /* check and configure queue intr-vector mapping */
3863 if (dev->data->dev_conf.intr_conf.rxq != 0)
3864 intr_vector = dev->data->nb_rx_queues;
3866 if (rte_intr_efd_enable(intr_handle, intr_vector))
3869 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3870 intr_handle->intr_vec =
3871 rte_zmalloc("intr_vec",
3872 dev->data->nb_rx_queues * sizeof(int), 0);
3873 if (intr_handle->intr_vec == NULL) {
3874 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3875 " intr_vec\n", dev->data->nb_rx_queues);
3879 ixgbevf_configure_msix(dev);
3881 if (dev->data->dev_conf.intr_conf.lsc != 0) {
3882 if (rte_intr_allow_others(intr_handle))
3883 rte_intr_callback_register(intr_handle,
3884 ixgbevf_dev_interrupt_handler,
3887 PMD_INIT_LOG(INFO, "lsc won't enable because of"
3888 " no intr multiplex\n");
3891 rte_intr_enable(intr_handle);
3893 /* Re-enable interrupt for VF */
3894 ixgbevf_intr_enable(hw);
3900 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3902 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3903 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3905 PMD_INIT_FUNC_TRACE();
3907 hw->adapter_stopped = 1;
3908 ixgbe_stop_adapter(hw);
3911 * Clear what we set, but we still keep shadow_vfta to
3912 * restore after device starts
3914 ixgbevf_set_vfta_all(dev,0);
3916 /* Clear stored conf */
3917 dev->data->scattered_rx = 0;
3919 ixgbe_dev_clear_queues(dev);
3921 /* disable intr eventfd mapping */
3922 rte_intr_disable(intr_handle);
3924 /* Clean datapath event and queue/vec mapping */
3925 rte_intr_efd_disable(intr_handle);
3926 if (intr_handle->intr_vec != NULL) {
3927 rte_free(intr_handle->intr_vec);
3928 intr_handle->intr_vec = NULL;
3933 ixgbevf_dev_close(struct rte_eth_dev *dev)
3935 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3936 struct rte_pci_device *pci_dev;
3938 PMD_INIT_FUNC_TRACE();
3942 ixgbevf_dev_stop(dev);
3944 ixgbe_dev_free_queues(dev);
3946 /* reprogram the RAR[0] in case user changed it. */
3947 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3949 pci_dev = dev->pci_dev;
3950 if (pci_dev->intr_handle.intr_vec) {
3951 rte_free(pci_dev->intr_handle.intr_vec);
3952 pci_dev->intr_handle.intr_vec = NULL;
3956 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3958 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3959 struct ixgbe_vfta * shadow_vfta =
3960 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3961 int i = 0, j = 0, vfta = 0, mask = 1;
3963 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3964 vfta = shadow_vfta->vfta[i];
3967 for (j = 0; j < 32; j++){
3969 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3978 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3980 struct ixgbe_hw *hw =
3981 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3982 struct ixgbe_vfta * shadow_vfta =
3983 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3984 uint32_t vid_idx = 0;
3985 uint32_t vid_bit = 0;
3988 PMD_INIT_FUNC_TRACE();
3990 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3991 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3993 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3996 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3997 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3999 /* Save what we set and retore it after device reset */
4001 shadow_vfta->vfta[vid_idx] |= vid_bit;
4003 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4009 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4011 struct ixgbe_hw *hw =
4012 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4015 PMD_INIT_FUNC_TRACE();
4017 if(queue >= hw->mac.max_rx_queues)
4020 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4022 ctrl |= IXGBE_RXDCTL_VME;
4024 ctrl &= ~IXGBE_RXDCTL_VME;
4025 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4027 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4031 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4033 struct ixgbe_hw *hw =
4034 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4038 /* VF function only support hw strip feature, others are not support */
4039 if(mask & ETH_VLAN_STRIP_MASK){
4040 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4042 for(i=0; i < hw->mac.max_rx_queues; i++)
4043 ixgbevf_vlan_strip_queue_set(dev,i,on);
4048 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4052 /* we only need to do this if VMDq is enabled */
4053 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4054 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4055 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4063 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4065 uint32_t vector = 0;
4066 switch (hw->mac.mc_filter_type) {
4067 case 0: /* use bits [47:36] of the address */
4068 vector = ((uc_addr->addr_bytes[4] >> 4) |
4069 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4071 case 1: /* use bits [46:35] of the address */
4072 vector = ((uc_addr->addr_bytes[4] >> 3) |
4073 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4075 case 2: /* use bits [45:34] of the address */
4076 vector = ((uc_addr->addr_bytes[4] >> 2) |
4077 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4079 case 3: /* use bits [43:32] of the address */
4080 vector = ((uc_addr->addr_bytes[4]) |
4081 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4083 default: /* Invalid mc_filter_type */
4087 /* vector can only be 12-bits or boundary will be exceeded */
4093 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4101 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4102 const uint32_t ixgbe_uta_bit_shift = 5;
4103 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4104 const uint32_t bit1 = 0x1;
4106 struct ixgbe_hw *hw =
4107 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4108 struct ixgbe_uta_info *uta_info =
4109 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4111 /* The UTA table only exists on 82599 hardware and newer */
4112 if (hw->mac.type < ixgbe_mac_82599EB)
4115 vector = ixgbe_uta_vector(hw,mac_addr);
4116 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4117 uta_shift = vector & ixgbe_uta_bit_mask;
4119 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4123 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4125 uta_info->uta_in_use++;
4126 reg_val |= (bit1 << uta_shift);
4127 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4129 uta_info->uta_in_use--;
4130 reg_val &= ~(bit1 << uta_shift);
4131 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4134 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4136 if (uta_info->uta_in_use > 0)
4137 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4138 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4140 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4146 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4149 struct ixgbe_hw *hw =
4150 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4151 struct ixgbe_uta_info *uta_info =
4152 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4154 /* The UTA table only exists on 82599 hardware and newer */
4155 if (hw->mac.type < ixgbe_mac_82599EB)
4159 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4160 uta_info->uta_shadow[i] = ~0;
4161 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4164 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4165 uta_info->uta_shadow[i] = 0;
4166 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4174 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4176 uint32_t new_val = orig_val;
4178 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4179 new_val |= IXGBE_VMOLR_AUPE;
4180 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4181 new_val |= IXGBE_VMOLR_ROMPE;
4182 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4183 new_val |= IXGBE_VMOLR_ROPE;
4184 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4185 new_val |= IXGBE_VMOLR_BAM;
4186 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4187 new_val |= IXGBE_VMOLR_MPE;
4193 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4194 uint16_t rx_mask, uint8_t on)
4198 struct ixgbe_hw *hw =
4199 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4200 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4202 if (hw->mac.type == ixgbe_mac_82598EB) {
4203 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4204 " on 82599 hardware and newer");
4207 if (ixgbe_vmdq_mode_check(hw) < 0)
4210 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4217 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4223 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4227 const uint8_t bit1 = 0x1;
4229 struct ixgbe_hw *hw =
4230 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4232 if (ixgbe_vmdq_mode_check(hw) < 0)
4235 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4236 reg = IXGBE_READ_REG(hw, addr);
4244 IXGBE_WRITE_REG(hw, addr,reg);
4250 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4254 const uint8_t bit1 = 0x1;
4256 struct ixgbe_hw *hw =
4257 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4259 if (ixgbe_vmdq_mode_check(hw) < 0)
4262 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4263 reg = IXGBE_READ_REG(hw, addr);
4271 IXGBE_WRITE_REG(hw, addr,reg);
4277 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4278 uint64_t pool_mask, uint8_t vlan_on)
4282 struct ixgbe_hw *hw =
4283 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4285 if (ixgbe_vmdq_mode_check(hw) < 0)
4287 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4288 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4289 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4297 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4298 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4299 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4300 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4301 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4302 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4303 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4306 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4307 struct rte_eth_mirror_conf *mirror_conf,
4308 uint8_t rule_id, uint8_t on)
4310 uint32_t mr_ctl,vlvf;
4311 uint32_t mp_lsb = 0;
4312 uint32_t mv_msb = 0;
4313 uint32_t mv_lsb = 0;
4314 uint32_t mp_msb = 0;
4317 uint64_t vlan_mask = 0;
4319 const uint8_t pool_mask_offset = 32;
4320 const uint8_t vlan_mask_offset = 32;
4321 const uint8_t dst_pool_offset = 8;
4322 const uint8_t rule_mr_offset = 4;
4323 const uint8_t mirror_rule_mask= 0x0F;
4325 struct ixgbe_mirror_info *mr_info =
4326 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4327 struct ixgbe_hw *hw =
4328 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4329 uint8_t mirror_type = 0;
4331 if (ixgbe_vmdq_mode_check(hw) < 0)
4334 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4337 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4338 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4339 mirror_conf->rule_type);
4343 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4344 mirror_type |= IXGBE_MRCTL_VLME;
4345 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4346 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4347 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4348 /* search vlan id related pool vlan filter index */
4349 reg_index = ixgbe_find_vlvf_slot(hw,
4350 mirror_conf->vlan.vlan_id[i]);
4353 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4354 if ((vlvf & IXGBE_VLVF_VIEN) &&
4355 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4356 mirror_conf->vlan.vlan_id[i]))
4357 vlan_mask |= (1ULL << reg_index);
4364 mv_lsb = vlan_mask & 0xFFFFFFFF;
4365 mv_msb = vlan_mask >> vlan_mask_offset;
4367 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4368 mirror_conf->vlan.vlan_mask;
4369 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4370 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4371 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4372 mirror_conf->vlan.vlan_id[i];
4377 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4378 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4379 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4384 * if enable pool mirror, write related pool mask register,if disable
4385 * pool mirror, clear PFMRVM register
4387 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4388 mirror_type |= IXGBE_MRCTL_VPME;
4390 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4391 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4392 mr_info->mr_conf[rule_id].pool_mask =
4393 mirror_conf->pool_mask;
4398 mr_info->mr_conf[rule_id].pool_mask = 0;
4401 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4402 mirror_type |= IXGBE_MRCTL_UPME;
4403 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4404 mirror_type |= IXGBE_MRCTL_DPME;
4406 /* read mirror control register and recalculate it */
4407 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4410 mr_ctl |= mirror_type;
4411 mr_ctl &= mirror_rule_mask;
4412 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4414 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4416 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4417 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4419 /* write mirrror control register */
4420 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4422 /* write pool mirrror control register */
4423 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4424 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4425 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4428 /* write VLAN mirrror control register */
4429 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4430 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4431 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4439 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4442 uint32_t lsb_val = 0;
4443 uint32_t msb_val = 0;
4444 const uint8_t rule_mr_offset = 4;
4446 struct ixgbe_hw *hw =
4447 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4448 struct ixgbe_mirror_info *mr_info =
4449 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4451 if (ixgbe_vmdq_mode_check(hw) < 0)
4454 memset(&mr_info->mr_conf[rule_id], 0,
4455 sizeof(struct rte_eth_mirror_conf));
4457 /* clear PFVMCTL register */
4458 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4460 /* clear pool mask register */
4461 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4462 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4464 /* clear vlan mask register */
4465 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4466 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4472 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4475 struct ixgbe_hw *hw =
4476 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4478 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4479 mask |= (1 << queue_id);
4480 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4482 rte_intr_enable(&dev->pci_dev->intr_handle);
4488 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4491 struct ixgbe_hw *hw =
4492 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4494 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4495 mask &= ~(1 << queue_id);
4496 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4502 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4505 struct ixgbe_hw *hw =
4506 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4507 struct ixgbe_interrupt *intr =
4508 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4510 if (queue_id < 16) {
4511 ixgbe_disable_intr(hw);
4512 intr->mask |= (1 << queue_id);
4513 ixgbe_enable_intr(dev);
4514 } else if (queue_id < 32) {
4515 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4516 mask &= (1 << queue_id);
4517 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4518 } else if (queue_id < 64) {
4519 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4520 mask &= (1 << (queue_id - 32));
4521 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4523 rte_intr_enable(&dev->pci_dev->intr_handle);
4529 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4532 struct ixgbe_hw *hw =
4533 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4534 struct ixgbe_interrupt *intr =
4535 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4537 if (queue_id < 16) {
4538 ixgbe_disable_intr(hw);
4539 intr->mask &= ~(1 << queue_id);
4540 ixgbe_enable_intr(dev);
4541 } else if (queue_id < 32) {
4542 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4543 mask &= ~(1 << queue_id);
4544 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4545 } else if (queue_id < 64) {
4546 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4547 mask &= ~(1 << (queue_id - 32));
4548 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4555 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4556 uint8_t queue, uint8_t msix_vector)
4560 if (direction == -1) {
4562 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4563 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4566 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4568 /* rx or tx cause */
4569 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4570 idx = ((16 * (queue & 1)) + (8 * direction));
4571 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4572 tmp &= ~(0xFF << idx);
4573 tmp |= (msix_vector << idx);
4574 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4579 * set the IVAR registers, mapping interrupt causes to vectors
4581 * pointer to ixgbe_hw struct
4583 * 0 for Rx, 1 for Tx, -1 for other causes
4585 * queue to map the corresponding interrupt to
4587 * the vector to map to the corresponding queue
4590 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4591 uint8_t queue, uint8_t msix_vector)
4595 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4596 if (hw->mac.type == ixgbe_mac_82598EB) {
4597 if (direction == -1)
4599 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4600 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4601 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4602 tmp |= (msix_vector << (8 * (queue & 0x3)));
4603 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4604 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4605 (hw->mac.type == ixgbe_mac_X540)) {
4606 if (direction == -1) {
4608 idx = ((queue & 1) * 8);
4609 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4610 tmp &= ~(0xFF << idx);
4611 tmp |= (msix_vector << idx);
4612 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4614 /* rx or tx causes */
4615 idx = ((16 * (queue & 1)) + (8 * direction));
4616 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4617 tmp &= ~(0xFF << idx);
4618 tmp |= (msix_vector << idx);
4619 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4625 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4627 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4628 struct ixgbe_hw *hw =
4629 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4631 uint32_t vector_idx = 0;
4633 /* won't configure msix register if no mapping is done
4634 * between intr vector and event fd.
4636 if (!rte_intr_dp_is_en(intr_handle))
4639 /* Configure all RX queues of VF */
4640 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4641 /* Force all queue use vector 0,
4642 * as IXGBE_VF_MAXMSIVECOTR = 1
4644 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4645 intr_handle->intr_vec[q_idx] = vector_idx;
4648 /* Configure VF Rx queue ivar */
4649 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4653 * Sets up the hardware to properly generate MSI-X interrupts
4655 * board private structure
4658 ixgbe_configure_msix(struct rte_eth_dev *dev)
4660 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4661 struct ixgbe_hw *hw =
4662 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663 uint32_t queue_id, vec = 0;
4667 /* won't configure msix register if no mapping is done
4668 * between intr vector and event fd
4670 if (!rte_intr_dp_is_en(intr_handle))
4673 /* setup GPIE for MSI-x mode */
4674 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4675 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4676 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4677 /* auto clearing and auto setting corresponding bits in EIMS
4678 * when MSI-X interrupt is triggered
4680 if (hw->mac.type == ixgbe_mac_82598EB) {
4681 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4683 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4684 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4686 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4688 /* Populate the IVAR table and set the ITR values to the
4689 * corresponding register.
4691 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4693 /* by default, 1:1 mapping */
4694 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4695 intr_handle->intr_vec[queue_id] = vec;
4696 if (vec < intr_handle->nb_efd - 1)
4700 switch (hw->mac.type) {
4701 case ixgbe_mac_82598EB:
4702 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4703 intr_handle->max_intr - 1);
4705 case ixgbe_mac_82599EB:
4706 case ixgbe_mac_X540:
4707 ixgbe_set_ivar_map(hw, -1, 1, intr_handle->max_intr - 1);
4712 IXGBE_WRITE_REG(hw, IXGBE_EITR(queue_id),
4713 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4715 /* set up to autoclear timer, and the vectors */
4716 mask = IXGBE_EIMS_ENABLE_MASK;
4717 mask &= ~(IXGBE_EIMS_OTHER |
4718 IXGBE_EIMS_MAILBOX |
4721 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4724 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4725 uint16_t queue_idx, uint16_t tx_rate)
4727 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4728 uint32_t rf_dec, rf_int;
4730 uint16_t link_speed = dev->data->dev_link.link_speed;
4732 if (queue_idx >= hw->mac.max_tx_queues)
4736 /* Calculate the rate factor values to set */
4737 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4738 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4739 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4741 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4742 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4743 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4744 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4750 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4751 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4754 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4755 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4756 IXGBE_MAX_JUMBO_FRAME_SIZE))
4757 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4758 IXGBE_MMW_SIZE_JUMBO_FRAME);
4760 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4761 IXGBE_MMW_SIZE_DEFAULT);
4763 /* Set RTTBCNRC of queue X */
4764 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4765 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4766 IXGBE_WRITE_FLUSH(hw);
4771 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4772 uint16_t tx_rate, uint64_t q_msk)
4774 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4775 struct ixgbe_vf_info *vfinfo =
4776 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4777 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4778 uint32_t queue_stride =
4779 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4780 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4781 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4782 uint16_t total_rate = 0;
4784 if (queue_end >= hw->mac.max_tx_queues)
4787 if (vfinfo != NULL) {
4788 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4791 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4793 total_rate += vfinfo[vf_idx].tx_rate[idx];
4798 /* Store tx_rate for this vf. */
4799 for (idx = 0; idx < nb_q_per_pool; idx++) {
4800 if (((uint64_t)0x1 << idx) & q_msk) {
4801 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4802 vfinfo[vf].tx_rate[idx] = tx_rate;
4803 total_rate += tx_rate;
4807 if (total_rate > dev->data->dev_link.link_speed) {
4809 * Reset stored TX rate of the VF if it causes exceed
4812 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4816 /* Set RTTBCNRC of each queue/pool for vf X */
4817 for (; queue_idx <= queue_end; queue_idx++) {
4819 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4827 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4828 __attribute__((unused)) uint32_t index,
4829 __attribute__((unused)) uint32_t pool)
4831 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4835 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4836 * operation. Trap this case to avoid exhausting the [very limited]
4837 * set of PF resources used to store VF MAC addresses.
4839 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4841 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4844 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4848 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4850 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4851 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4852 struct ether_addr *mac_addr;
4857 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4858 * not support the deletion of a given MAC address.
4859 * Instead, it imposes to delete all MAC addresses, then to add again
4860 * all MAC addresses with the exception of the one to be deleted.
4862 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4865 * Add again all MAC addresses, with the exception of the deleted one
4866 * and of the permanent MAC address.
4868 for (i = 0, mac_addr = dev->data->mac_addrs;
4869 i < hw->mac.num_rar_entries; i++, mac_addr++) {
4870 /* Skip the deleted MAC address */
4873 /* Skip NULL MAC addresses */
4874 if (is_zero_ether_addr(mac_addr))
4876 /* Skip the permanent MAC address */
4877 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4879 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4882 "Adding again MAC address "
4883 "%02x:%02x:%02x:%02x:%02x:%02x failed "
4885 mac_addr->addr_bytes[0],
4886 mac_addr->addr_bytes[1],
4887 mac_addr->addr_bytes[2],
4888 mac_addr->addr_bytes[3],
4889 mac_addr->addr_bytes[4],
4890 mac_addr->addr_bytes[5],
4896 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4898 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4900 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4903 #define MAC_TYPE_FILTER_SUP(type) do {\
4904 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4905 (type) != ixgbe_mac_X550)\
4910 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4911 struct rte_eth_syn_filter *filter,
4914 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4917 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4920 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4923 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4925 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4926 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4928 if (filter->hig_pri)
4929 synqf |= IXGBE_SYN_FILTER_SYNQFP;
4931 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4933 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4935 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4937 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4938 IXGBE_WRITE_FLUSH(hw);
4943 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4944 struct rte_eth_syn_filter *filter)
4946 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4947 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4949 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4950 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4951 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4958 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4959 enum rte_filter_op filter_op,
4962 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4965 MAC_TYPE_FILTER_SUP(hw->mac.type);
4967 if (filter_op == RTE_ETH_FILTER_NOP)
4971 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4976 switch (filter_op) {
4977 case RTE_ETH_FILTER_ADD:
4978 ret = ixgbe_syn_filter_set(dev,
4979 (struct rte_eth_syn_filter *)arg,
4982 case RTE_ETH_FILTER_DELETE:
4983 ret = ixgbe_syn_filter_set(dev,
4984 (struct rte_eth_syn_filter *)arg,
4987 case RTE_ETH_FILTER_GET:
4988 ret = ixgbe_syn_filter_get(dev,
4989 (struct rte_eth_syn_filter *)arg);
4992 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5001 static inline enum ixgbe_5tuple_protocol
5002 convert_protocol_type(uint8_t protocol_value)
5004 if (protocol_value == IPPROTO_TCP)
5005 return IXGBE_FILTER_PROTOCOL_TCP;
5006 else if (protocol_value == IPPROTO_UDP)
5007 return IXGBE_FILTER_PROTOCOL_UDP;
5008 else if (protocol_value == IPPROTO_SCTP)
5009 return IXGBE_FILTER_PROTOCOL_SCTP;
5011 return IXGBE_FILTER_PROTOCOL_NONE;
5015 * add a 5tuple filter
5018 * dev: Pointer to struct rte_eth_dev.
5019 * index: the index the filter allocates.
5020 * filter: ponter to the filter that will be added.
5021 * rx_queue: the queue id the filter assigned to.
5024 * - On success, zero.
5025 * - On failure, a negative value.
5028 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5029 struct ixgbe_5tuple_filter *filter)
5031 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5032 struct ixgbe_filter_info *filter_info =
5033 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5035 uint32_t ftqf, sdpqf;
5036 uint32_t l34timir = 0;
5037 uint8_t mask = 0xff;
5040 * look for an unused 5tuple filter index,
5041 * and insert the filter to list.
5043 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5044 idx = i / (sizeof(uint32_t) * NBBY);
5045 shift = i % (sizeof(uint32_t) * NBBY);
5046 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5047 filter_info->fivetuple_mask[idx] |= 1 << shift;
5049 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5055 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5056 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5060 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5061 IXGBE_SDPQF_DSTPORT_SHIFT);
5062 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5064 ftqf = (uint32_t)(filter->filter_info.proto &
5065 IXGBE_FTQF_PROTOCOL_MASK);
5066 ftqf |= (uint32_t)((filter->filter_info.priority &
5067 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5068 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5069 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5070 if (filter->filter_info.dst_ip_mask == 0)
5071 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5072 if (filter->filter_info.src_port_mask == 0)
5073 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5074 if (filter->filter_info.dst_port_mask == 0)
5075 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5076 if (filter->filter_info.proto_mask == 0)
5077 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5078 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5079 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5080 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5082 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5083 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5084 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5085 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5087 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5088 l34timir |= (uint32_t)(filter->queue <<
5089 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5090 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5095 * remove a 5tuple filter
5098 * dev: Pointer to struct rte_eth_dev.
5099 * filter: the pointer of the filter will be removed.
5102 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5103 struct ixgbe_5tuple_filter *filter)
5105 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5106 struct ixgbe_filter_info *filter_info =
5107 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5108 uint16_t index = filter->index;
5110 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5111 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5112 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5115 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5116 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5117 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5118 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5119 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5123 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5125 struct ixgbe_hw *hw;
5126 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5128 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5130 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5133 /* refuse mtu that requires the support of scattered packets when this
5134 * feature has not been enabled before. */
5135 if (!dev->data->scattered_rx &&
5136 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5137 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5141 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5142 * request of the version 2.0 of the mailbox API.
5143 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5144 * of the mailbox API.
5145 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5146 * prior to 3.11.33 which contains the following change:
5147 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5149 ixgbevf_rlpml_set_vf(hw, max_frame);
5151 /* update max frame size */
5152 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5156 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5157 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5161 static inline struct ixgbe_5tuple_filter *
5162 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5163 struct ixgbe_5tuple_filter_info *key)
5165 struct ixgbe_5tuple_filter *it;
5167 TAILQ_FOREACH(it, filter_list, entries) {
5168 if (memcmp(key, &it->filter_info,
5169 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5176 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5178 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5179 struct ixgbe_5tuple_filter_info *filter_info)
5181 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5182 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5183 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5186 switch (filter->dst_ip_mask) {
5188 filter_info->dst_ip_mask = 0;
5189 filter_info->dst_ip = filter->dst_ip;
5192 filter_info->dst_ip_mask = 1;
5195 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5199 switch (filter->src_ip_mask) {
5201 filter_info->src_ip_mask = 0;
5202 filter_info->src_ip = filter->src_ip;
5205 filter_info->src_ip_mask = 1;
5208 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5212 switch (filter->dst_port_mask) {
5214 filter_info->dst_port_mask = 0;
5215 filter_info->dst_port = filter->dst_port;
5218 filter_info->dst_port_mask = 1;
5221 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5225 switch (filter->src_port_mask) {
5227 filter_info->src_port_mask = 0;
5228 filter_info->src_port = filter->src_port;
5231 filter_info->src_port_mask = 1;
5234 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5238 switch (filter->proto_mask) {
5240 filter_info->proto_mask = 0;
5241 filter_info->proto =
5242 convert_protocol_type(filter->proto);
5245 filter_info->proto_mask = 1;
5248 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5252 filter_info->priority = (uint8_t)filter->priority;
5257 * add or delete a ntuple filter
5260 * dev: Pointer to struct rte_eth_dev.
5261 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5262 * add: if true, add filter, if false, remove filter
5265 * - On success, zero.
5266 * - On failure, a negative value.
5269 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5270 struct rte_eth_ntuple_filter *ntuple_filter,
5273 struct ixgbe_filter_info *filter_info =
5274 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5275 struct ixgbe_5tuple_filter_info filter_5tuple;
5276 struct ixgbe_5tuple_filter *filter;
5279 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5280 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5284 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5285 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5289 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5291 if (filter != NULL && add) {
5292 PMD_DRV_LOG(ERR, "filter exists.");
5295 if (filter == NULL && !add) {
5296 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5301 filter = rte_zmalloc("ixgbe_5tuple_filter",
5302 sizeof(struct ixgbe_5tuple_filter), 0);
5305 (void)rte_memcpy(&filter->filter_info,
5307 sizeof(struct ixgbe_5tuple_filter_info));
5308 filter->queue = ntuple_filter->queue;
5309 ret = ixgbe_add_5tuple_filter(dev, filter);
5315 ixgbe_remove_5tuple_filter(dev, filter);
5321 * get a ntuple filter
5324 * dev: Pointer to struct rte_eth_dev.
5325 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5328 * - On success, zero.
5329 * - On failure, a negative value.
5332 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5333 struct rte_eth_ntuple_filter *ntuple_filter)
5335 struct ixgbe_filter_info *filter_info =
5336 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5337 struct ixgbe_5tuple_filter_info filter_5tuple;
5338 struct ixgbe_5tuple_filter *filter;
5341 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5342 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5346 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5347 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5351 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5353 if (filter == NULL) {
5354 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5357 ntuple_filter->queue = filter->queue;
5362 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5363 * @dev: pointer to rte_eth_dev structure
5364 * @filter_op:operation will be taken.
5365 * @arg: a pointer to specific structure corresponding to the filter_op
5368 * - On success, zero.
5369 * - On failure, a negative value.
5372 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5373 enum rte_filter_op filter_op,
5376 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5379 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5381 if (filter_op == RTE_ETH_FILTER_NOP)
5385 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5390 switch (filter_op) {
5391 case RTE_ETH_FILTER_ADD:
5392 ret = ixgbe_add_del_ntuple_filter(dev,
5393 (struct rte_eth_ntuple_filter *)arg,
5396 case RTE_ETH_FILTER_DELETE:
5397 ret = ixgbe_add_del_ntuple_filter(dev,
5398 (struct rte_eth_ntuple_filter *)arg,
5401 case RTE_ETH_FILTER_GET:
5402 ret = ixgbe_get_ntuple_filter(dev,
5403 (struct rte_eth_ntuple_filter *)arg);
5406 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5414 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5419 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5420 if (filter_info->ethertype_filters[i] == ethertype &&
5421 (filter_info->ethertype_mask & (1 << i)))
5428 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5433 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5434 if (!(filter_info->ethertype_mask & (1 << i))) {
5435 filter_info->ethertype_mask |= 1 << i;
5436 filter_info->ethertype_filters[i] = ethertype;
5444 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5447 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5449 filter_info->ethertype_mask &= ~(1 << idx);
5450 filter_info->ethertype_filters[idx] = 0;
5455 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5456 struct rte_eth_ethertype_filter *filter,
5459 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5460 struct ixgbe_filter_info *filter_info =
5461 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5466 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5469 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5470 filter->ether_type == ETHER_TYPE_IPv6) {
5471 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5472 " ethertype filter.", filter->ether_type);
5476 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5477 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5480 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5481 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5485 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5486 if (ret >= 0 && add) {
5487 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5488 filter->ether_type);
5491 if (ret < 0 && !add) {
5492 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5493 filter->ether_type);
5498 ret = ixgbe_ethertype_filter_insert(filter_info,
5499 filter->ether_type);
5501 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5504 etqf = IXGBE_ETQF_FILTER_EN;
5505 etqf |= (uint32_t)filter->ether_type;
5506 etqs |= (uint32_t)((filter->queue <<
5507 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5508 IXGBE_ETQS_RX_QUEUE);
5509 etqs |= IXGBE_ETQS_QUEUE_EN;
5511 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5515 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5516 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5517 IXGBE_WRITE_FLUSH(hw);
5523 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5524 struct rte_eth_ethertype_filter *filter)
5526 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5527 struct ixgbe_filter_info *filter_info =
5528 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5529 uint32_t etqf, etqs;
5532 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5534 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5535 filter->ether_type);
5539 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5540 if (etqf & IXGBE_ETQF_FILTER_EN) {
5541 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5542 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5544 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5545 IXGBE_ETQS_RX_QUEUE_SHIFT;
5552 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5553 * @dev: pointer to rte_eth_dev structure
5554 * @filter_op:operation will be taken.
5555 * @arg: a pointer to specific structure corresponding to the filter_op
5558 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5559 enum rte_filter_op filter_op,
5562 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5565 MAC_TYPE_FILTER_SUP(hw->mac.type);
5567 if (filter_op == RTE_ETH_FILTER_NOP)
5571 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5576 switch (filter_op) {
5577 case RTE_ETH_FILTER_ADD:
5578 ret = ixgbe_add_del_ethertype_filter(dev,
5579 (struct rte_eth_ethertype_filter *)arg,
5582 case RTE_ETH_FILTER_DELETE:
5583 ret = ixgbe_add_del_ethertype_filter(dev,
5584 (struct rte_eth_ethertype_filter *)arg,
5587 case RTE_ETH_FILTER_GET:
5588 ret = ixgbe_get_ethertype_filter(dev,
5589 (struct rte_eth_ethertype_filter *)arg);
5592 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5600 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5601 enum rte_filter_type filter_type,
5602 enum rte_filter_op filter_op,
5607 switch (filter_type) {
5608 case RTE_ETH_FILTER_NTUPLE:
5609 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5611 case RTE_ETH_FILTER_ETHERTYPE:
5612 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5614 case RTE_ETH_FILTER_SYN:
5615 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5617 case RTE_ETH_FILTER_FDIR:
5618 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5621 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5630 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5631 u8 **mc_addr_ptr, u32 *vmdq)
5636 mc_addr = *mc_addr_ptr;
5637 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5642 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5643 struct ether_addr *mc_addr_set,
5644 uint32_t nb_mc_addr)
5646 struct ixgbe_hw *hw;
5649 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5650 mc_addr_list = (u8 *)mc_addr_set;
5651 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5652 ixgbe_dev_addr_list_itr, TRUE);
5656 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5658 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5662 /* Enable system time for platforms where it isn't on by default. */
5663 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5664 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5665 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5667 /* Start incrementing the register used to timestamp PTP packets. */
5668 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5670 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5671 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5673 IXGBE_ETQF_FILTER_EN |
5676 /* Enable timestamping of received PTP packets. */
5677 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5678 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5679 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5681 /* Enable timestamping of transmitted PTP packets. */
5682 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5683 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5684 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5690 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5692 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5695 /* Disable timestamping of transmitted PTP packets. */
5696 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5697 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5698 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5700 /* Disable timestamping of received PTP packets. */
5701 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5702 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5703 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5705 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5706 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5708 /* Stop incrementating the System Time registers. */
5709 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5715 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5716 struct timespec *timestamp,
5717 uint32_t flags __rte_unused)
5719 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5720 uint32_t tsync_rxctl;
5724 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5725 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5728 rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5729 rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5731 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5732 timestamp->tv_nsec = 0;
5738 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5739 struct timespec *timestamp)
5741 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5742 uint32_t tsync_txctl;
5746 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5747 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5750 tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5751 tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5753 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5754 timestamp->tv_nsec = 0;
5760 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5762 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5765 const struct reg_info *reg_group;
5766 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5767 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5769 while ((reg_group = reg_set[g_ind++]))
5770 count += ixgbe_regs_group_count(reg_group);
5776 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5780 const struct reg_info *reg_group;
5782 while ((reg_group = ixgbevf_regs[g_ind++]))
5783 count += ixgbe_regs_group_count(reg_group);
5789 ixgbe_get_regs(struct rte_eth_dev *dev,
5790 struct rte_dev_reg_info *regs)
5792 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5793 uint32_t *data = regs->data;
5796 const struct reg_info *reg_group;
5797 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5798 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5800 /* Support only full register dump */
5801 if ((regs->length == 0) ||
5802 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5803 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5805 while ((reg_group = reg_set[g_ind++]))
5806 count += ixgbe_read_regs_group(dev, &data[count],
5815 ixgbevf_get_regs(struct rte_eth_dev *dev,
5816 struct rte_dev_reg_info *regs)
5818 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5819 uint32_t *data = regs->data;
5822 const struct reg_info *reg_group;
5824 /* Support only full register dump */
5825 if ((regs->length == 0) ||
5826 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5827 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5829 while ((reg_group = ixgbevf_regs[g_ind++]))
5830 count += ixgbe_read_regs_group(dev, &data[count],
5839 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5841 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5843 /* Return unit is byte count */
5844 return hw->eeprom.word_size * 2;
5848 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5849 struct rte_dev_eeprom_info *in_eeprom)
5851 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5852 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5853 uint16_t *data = in_eeprom->data;
5856 first = in_eeprom->offset >> 1;
5857 length = in_eeprom->length >> 1;
5858 if ((first > hw->eeprom.word_size) ||
5859 ((first + length) > hw->eeprom.word_size))
5862 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5864 return eeprom->ops.read_buffer(hw, first, length, data);
5868 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5869 struct rte_dev_eeprom_info *in_eeprom)
5871 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5872 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5873 uint16_t *data = in_eeprom->data;
5876 first = in_eeprom->offset >> 1;
5877 length = in_eeprom->length >> 1;
5878 if ((first > hw->eeprom.word_size) ||
5879 ((first + length) > hw->eeprom.word_size))
5882 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5884 return eeprom->ops.write_buffer(hw, first, length, data);
5888 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5890 case ixgbe_mac_X550:
5891 case ixgbe_mac_X550EM_x:
5892 return ETH_RSS_RETA_SIZE_512;
5893 case ixgbe_mac_X550_vf:
5894 case ixgbe_mac_X550EM_x_vf:
5895 return ETH_RSS_RETA_SIZE_64;
5897 return ETH_RSS_RETA_SIZE_128;
5902 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5904 case ixgbe_mac_X550:
5905 case ixgbe_mac_X550EM_x:
5906 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5907 return IXGBE_RETA(reta_idx >> 2);
5909 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5910 case ixgbe_mac_X550_vf:
5911 case ixgbe_mac_X550EM_x_vf:
5912 return IXGBE_VFRETA(reta_idx >> 2);
5914 return IXGBE_RETA(reta_idx >> 2);
5919 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5921 case ixgbe_mac_X550_vf:
5922 case ixgbe_mac_X550EM_x_vf:
5923 return IXGBE_VFMRQC;
5930 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5932 case ixgbe_mac_X550_vf:
5933 case ixgbe_mac_X550EM_x_vf:
5934 return IXGBE_VFRSSRK(i);
5936 return IXGBE_RSSRK(i);
5941 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5943 case ixgbe_mac_82599_vf:
5944 case ixgbe_mac_X540_vf:
5952 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
5953 struct rte_eth_dcb_info *dcb_info)
5955 struct ixgbe_dcb_config *dcb_config =
5956 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
5957 struct ixgbe_dcb_tc_config *tc;
5960 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
5961 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
5963 dcb_info->nb_tcs = 1;
5965 if (dcb_config->vt_mode) { /* vt is enabled*/
5966 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
5967 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
5968 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5969 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
5970 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
5971 for (j = 0; j < dcb_info->nb_tcs; j++) {
5972 dcb_info->tc_queue.tc_rxq[i][j].base =
5973 i * dcb_info->nb_tcs + j;
5974 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
5975 dcb_info->tc_queue.tc_txq[i][j].base =
5976 i * dcb_info->nb_tcs + j;
5977 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
5980 } else { /* vt is disabled*/
5981 struct rte_eth_dcb_rx_conf *rx_conf =
5982 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
5983 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5984 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
5985 if (dcb_info->nb_tcs == ETH_4_TCS) {
5986 for (i = 0; i < dcb_info->nb_tcs; i++) {
5987 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
5988 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5990 dcb_info->tc_queue.tc_txq[0][0].base = 0;
5991 dcb_info->tc_queue.tc_txq[0][1].base = 64;
5992 dcb_info->tc_queue.tc_txq[0][2].base = 96;
5993 dcb_info->tc_queue.tc_txq[0][3].base = 112;
5994 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
5995 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
5996 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
5997 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
5998 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
5999 for (i = 0; i < dcb_info->nb_tcs; i++) {
6000 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6001 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6003 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6004 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6005 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6006 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6007 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6008 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6009 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6010 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6011 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6012 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6013 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6014 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6015 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6016 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6017 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6018 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6021 for (i = 0; i < dcb_info->nb_tcs; i++) {
6022 tc = &dcb_config->tc_config[i];
6023 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6028 static struct rte_driver rte_ixgbe_driver = {
6030 .init = rte_ixgbe_pmd_init,
6033 static struct rte_driver rte_ixgbevf_driver = {
6035 .init = rte_ixgbevf_pmd_init,
6038 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6039 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);