drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstat *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstat *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 183         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 184 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 185         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 186 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 187                                              uint16_t queue_id,
 188                                              uint8_t stat_idx,
 189                                              uint8_t is_rx);
 190 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 191                                struct rte_eth_dev_info *dev_info);
 192 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 193 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 194                                  struct rte_eth_dev_info *dev_info);
 195 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 196
 197 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 198                 uint16_t vlan_id, int on);
 199 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 200                                enum rte_vlan_type vlan_type,
 201                                uint16_t tpid_id);
 202 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 203                 uint16_t queue, bool on);
 204 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 205                 int on);
 206 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 207 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 208 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 209 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 210 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 211
 212 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 213 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 214 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 217                                struct rte_eth_fc_conf *fc_conf);
 218 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 219                 struct rte_eth_pfc_conf *pfc_conf);
 220 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 221                         struct rte_eth_rss_reta_entry64 *reta_conf,
 222                         uint16_t reta_size);
 223 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 224                         struct rte_eth_rss_reta_entry64 *reta_conf,
 225                         uint16_t reta_size);
 226 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 230 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 231 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 232                 void *param);
 233 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 234 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 235                 uint32_t index, uint32_t pool);
 236 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 237 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 238                                            struct ether_addr *mac_addr);
 239 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 240
 241 /* For Virtual Function support */
 242 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 243 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 244 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 245 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 246 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 247 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 248 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 249 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 250 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 251                 struct rte_eth_stats *stats);
 252 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 253 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 254                 uint16_t vlan_id, int on);
 255 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 256                 uint16_t queue, int on);
 257 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 258 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 259 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 260                                             uint16_t queue_id);
 261 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 262                                              uint16_t queue_id);
 263 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 264                                  uint8_t queue, uint8_t msix_vector);
 265 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 267 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 268
 269 /* For Eth VMDQ APIs support */
 270 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 271                 ether_addr * mac_addr, uint8_t on);
 272 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 273 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 274                 uint16_t rx_mask, uint8_t on);
 275 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 276 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 277 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 278                 uint64_t pool_mask, uint8_t vlan_on);
 279 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 280                 struct rte_eth_mirror_conf *mirror_conf,
 281                 uint8_t rule_id, uint8_t on);
 282 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 283                 uint8_t rule_id);
 284 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 285                                           uint16_t queue_id);
 286 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 287                                            uint16_t queue_id);
 288 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 289                                uint8_t queue, uint8_t msix_vector);
 290 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 291
 292 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 293                 uint16_t queue_idx, uint16_t tx_rate);
 294 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 295                 uint16_t tx_rate, uint64_t q_msk);
 296
 297 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                  struct ether_addr *mac_addr,
 299                                  uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter,
 305                         bool add);
 306 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 307                         struct rte_eth_syn_filter *filter);
 308 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 309                         enum rte_filter_op filter_op,
 310                         void *arg);
 311 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 312                         struct ixgbe_5tuple_filter *filter);
 313 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 314                         struct ixgbe_5tuple_filter *filter);
 315 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter,
 317                         bool add);
 318 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 319                                 enum rte_filter_op filter_op,
 320                                 void *arg);
 321 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 322                         struct rte_eth_ntuple_filter *filter);
 323 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 324                         struct rte_eth_ethertype_filter *filter,
 325                         bool add);
 326 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 327                                 enum rte_filter_op filter_op,
 328                                 void *arg);
 329 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 330                         struct rte_eth_ethertype_filter *filter);
 331 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 332                      enum rte_filter_type filter_type,
 333                      enum rte_filter_op filter_op,
 334                      void *arg);
 335 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 336
 337 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 338                                       struct ether_addr *mc_addr_set,
 339                                       uint32_t nb_mc_addr);
 340 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 341                                    struct rte_eth_dcb_info *dcb_info);
 342
 343 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 344 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 345                             struct rte_dev_reg_info *regs);
 346 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 347 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 348                                 struct rte_dev_eeprom_info *eeprom);
 349 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351
 352 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 353 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 354                                 struct rte_dev_reg_info *regs);
 355
 356 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 357 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 358 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 359                                             struct timespec *timestamp,
 360                                             uint32_t flags);
 361 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 362                                             struct timespec *timestamp);
 363 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 364 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 365                                    struct timespec *timestamp);
 366 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 367                                    const struct timespec *timestamp);
 368
 369 static int ixgbe_dev_l2_tunnel_eth_type_conf
 370         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 371 static int ixgbe_dev_l2_tunnel_offload_set
 372         (struct rte_eth_dev *dev,
 373          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 374          uint32_t mask,
 375          uint8_t en);
 376 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 377                                              enum rte_filter_op filter_op,
 378                                              void *arg);
 379
 380 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 381                                          struct rte_eth_udp_tunnel *udp_tunnel);
 382 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 383                                          struct rte_eth_udp_tunnel *udp_tunnel);
 384
 385 /*
 386  * Define VF Stats MACRO for Non "cleared on read" register
 387  */
 388 #define UPDATE_VF_STAT(reg, last, cur)                          \
 389 {                                                               \
 390         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 391         cur += (latest - last) & UINT_MAX;                      \
 392         last = latest;                                          \
 393 }
 394
 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 396 {                                                                \
 397         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 398         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 399         u64 latest = ((new_msb << 32) | new_lsb);                \
 400         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 401         last = latest;                                           \
 402 }
 403
 404 #define IXGBE_SET_HWSTRIP(h, q) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (h)->bitmap[idx] |= 1 << bit;\
 408         } while (0)
 409
 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] &= ~(1 << bit);\
 414         } while (0)
 415
 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (r) = (h)->bitmap[idx] >> bit & 1;\
 420         } while (0)
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426
 427 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 428 #include "rte_pci_dev_ids.h"
 429
 430 { .vendor_id = 0, /* sentinel */ },
 431 };
 432
 433
 434 /*
 435  * The set of PCI devices this driver supports (for 82599 VF)
 436  */
 437 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 438
 439 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 440 #include "rte_pci_dev_ids.h"
 441 { .vendor_id = 0, /* sentinel */ },
 442
 443 };
 444
 445 static const struct rte_eth_desc_lim rx_desc_lim = {
 446         .nb_max = IXGBE_MAX_RING_DESC,
 447         .nb_min = IXGBE_MIN_RING_DESC,
 448         .nb_align = IXGBE_RXD_ALIGN,
 449 };
 450
 451 static const struct rte_eth_desc_lim tx_desc_lim = {
 452         .nb_max = IXGBE_MAX_RING_DESC,
 453         .nb_min = IXGBE_MIN_RING_DESC,
 454         .nb_align = IXGBE_TXD_ALIGN,
 455 };
 456
 457 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 458         .dev_configure        = ixgbe_dev_configure,
 459         .dev_start            = ixgbe_dev_start,
 460         .dev_stop             = ixgbe_dev_stop,
 461         .dev_set_link_up    = ixgbe_dev_set_link_up,
 462         .dev_set_link_down  = ixgbe_dev_set_link_down,
 463         .dev_close            = ixgbe_dev_close,
 464         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 465         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 466         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 467         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 468         .link_update          = ixgbe_dev_link_update,
 469         .stats_get            = ixgbe_dev_stats_get,
 470         .xstats_get           = ixgbe_dev_xstats_get,
 471         .stats_reset          = ixgbe_dev_stats_reset,
 472         .xstats_reset         = ixgbe_dev_xstats_reset,
 473         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 474         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 475         .dev_infos_get        = ixgbe_dev_info_get,
 476         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 477         .mtu_set              = ixgbe_dev_mtu_set,
 478         .vlan_filter_set      = ixgbe_vlan_filter_set,
 479         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 480         .vlan_offload_set     = ixgbe_vlan_offload_set,
 481         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 482         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 483         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 484         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 485         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 486         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 487         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 488         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 489         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 490         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 491         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 492         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 493         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 494         .dev_led_on           = ixgbe_dev_led_on,
 495         .dev_led_off          = ixgbe_dev_led_off,
 496         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 497         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 498         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 499         .mac_addr_add         = ixgbe_add_rar,
 500         .mac_addr_remove      = ixgbe_remove_rar,
 501         .mac_addr_set         = ixgbe_set_default_mac_addr,
 502         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 503         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 504         .mirror_rule_set      = ixgbe_mirror_rule_set,
 505         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 506         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 507         .set_vf_rx            = ixgbe_set_pool_rx,
 508         .set_vf_tx            = ixgbe_set_pool_tx,
 509         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 510         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 511         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 512         .reta_update          = ixgbe_dev_rss_reta_update,
 513         .reta_query           = ixgbe_dev_rss_reta_query,
 514 #ifdef RTE_NIC_BYPASS
 515         .bypass_init          = ixgbe_bypass_init,
 516         .bypass_state_set     = ixgbe_bypass_state_store,
 517         .bypass_state_show    = ixgbe_bypass_state_show,
 518         .bypass_event_set     = ixgbe_bypass_event_store,
 519         .bypass_event_show    = ixgbe_bypass_event_show,
 520         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 521         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 522         .bypass_ver_show      = ixgbe_bypass_ver_show,
 523         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 524 #endif /* RTE_NIC_BYPASS */
 525         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 526         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 527         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 528         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 529         .rxq_info_get         = ixgbe_rxq_info_get,
 530         .txq_info_get         = ixgbe_txq_info_get,
 531         .timesync_enable      = ixgbe_timesync_enable,
 532         .timesync_disable     = ixgbe_timesync_disable,
 533         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 534         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 535         .get_reg_length       = ixgbe_get_reg_length,
 536         .get_reg              = ixgbe_get_regs,
 537         .get_eeprom_length    = ixgbe_get_eeprom_length,
 538         .get_eeprom           = ixgbe_get_eeprom,
 539         .set_eeprom           = ixgbe_set_eeprom,
 540         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 541         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 542         .timesync_read_time   = ixgbe_timesync_read_time,
 543         .timesync_write_time  = ixgbe_timesync_write_time,
 544         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 545         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 546         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 547         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 548 };
 549
 550 /*
 551  * dev_ops for virtual function, bare necessities for basic vf
 552  * operation have been implemented
 553  */
 554 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 555         .dev_configure        = ixgbevf_dev_configure,
 556         .dev_start            = ixgbevf_dev_start,
 557         .dev_stop             = ixgbevf_dev_stop,
 558         .link_update          = ixgbe_dev_link_update,
 559         .stats_get            = ixgbevf_dev_stats_get,
 560         .xstats_get           = ixgbevf_dev_xstats_get,
 561         .stats_reset          = ixgbevf_dev_stats_reset,
 562         .xstats_reset         = ixgbevf_dev_stats_reset,
 563         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 564         .dev_close            = ixgbevf_dev_close,
 565         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 566         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 567         .dev_infos_get        = ixgbevf_dev_info_get,
 568         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 569         .mtu_set              = ixgbevf_dev_set_mtu,
 570         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 571         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 572         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 573         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 574         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 575         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 576         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 577         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 578         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 579         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 580         .mac_addr_add         = ixgbevf_add_mac_addr,
 581         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 582         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 583         .rxq_info_get         = ixgbe_rxq_info_get,
 584         .txq_info_get         = ixgbe_txq_info_get,
 585         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 586         .get_reg_length       = ixgbevf_get_reg_length,
 587         .get_reg              = ixgbevf_get_regs,
 588         .reta_update          = ixgbe_dev_rss_reta_update,
 589         .reta_query           = ixgbe_dev_rss_reta_query,
 590         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 591         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 592 };
 593
 594 /* store statistics names and its offset in stats structure */
 595 struct rte_ixgbe_xstats_name_off {
 596         char name[RTE_ETH_XSTATS_NAME_SIZE];
 597         unsigned offset;
 598 };
 599
 600 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 601         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 602         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 603         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 604         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 605         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 606         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 607         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 608         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 609         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 610         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 611         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 612         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 613         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 614         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 615         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 616                 prc1023)},
 617         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 618                 prc1522)},
 619         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 620         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 621         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 622         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 623         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 624         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 625         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 626         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 627         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 628         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 629         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 630         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 631         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 632         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 633         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 634         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 635         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 636                 ptc1023)},
 637         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 638                 ptc1522)},
 639         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 640         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 641         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 642         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 643
 644         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 645                 fdirustat_add)},
 646         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 647                 fdirustat_remove)},
 648         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 649                 fdirfstat_fadd)},
 650         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 651                 fdirfstat_fremove)},
 652         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 653                 fdirmatch)},
 654         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 655                 fdirmiss)},
 656
 657         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 658         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 659         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 660                 fclast)},
 661         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 662         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 663         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 664         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 665         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 666                 fcoe_noddp)},
 667         {"rx_fcoe_no_direct_data_placement_ext_buff",
 668                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 669
 670         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 671                 lxontxc)},
 672         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 673                 lxonrxc)},
 674         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 675                 lxofftxc)},
 676         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 677                 lxoffrxc)},
 678         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 679 };
 680
 681 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 682                            sizeof(rte_ixgbe_stats_strings[0]))
 683
 684 /* Per-queue statistics */
 685 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 686         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 687         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 688         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 689         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 690 };
 691
 692 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 693                            sizeof(rte_ixgbe_rxq_strings[0]))
 694 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 695
 696 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 697         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 698         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 699         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 700                 pxon2offc)},
 701 };
 702
 703 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 704                            sizeof(rte_ixgbe_txq_strings[0]))
 705 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 706
 707 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 708         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 709 };
 710
 711 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 712                 sizeof(rte_ixgbevf_stats_strings[0]))
 713
 714 /**
 715  * Atomically reads the link status information from global
 716  * structure rte_eth_dev.
 717  *
 718  * @param dev
 719  *   - Pointer to the structure rte_eth_dev to read from.
 720  *   - Pointer to the buffer to be saved with the link status.
 721  *
 722  * @return
 723  *   - On success, zero.
 724  *   - On failure, negative value.
 725  */
 726 static inline int
 727 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 728                                 struct rte_eth_link *link)
 729 {
 730         struct rte_eth_link *dst = link;
 731         struct rte_eth_link *src = &(dev->data->dev_link);
 732
 733         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 734                                         *(uint64_t *)src) == 0)
 735                 return -1;
 736
 737         return 0;
 738 }
 739
 740 /**
 741  * Atomically writes the link status information into global
 742  * structure rte_eth_dev.
 743  *
 744  * @param dev
 745  *   - Pointer to the structure rte_eth_dev to read from.
 746  *   - Pointer to the buffer to be saved with the link status.
 747  *
 748  * @return
 749  *   - On success, zero.
 750  *   - On failure, negative value.
 751  */
 752 static inline int
 753 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 754                                 struct rte_eth_link *link)
 755 {
 756         struct rte_eth_link *dst = &(dev->data->dev_link);
 757         struct rte_eth_link *src = link;
 758
 759         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 760                                         *(uint64_t *)src) == 0)
 761                 return -1;
 762
 763         return 0;
 764 }
 765
 766 /*
 767  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 768  */
 769 static inline int
 770 ixgbe_is_sfp(struct ixgbe_hw *hw)
 771 {
 772         switch (hw->phy.type) {
 773         case ixgbe_phy_sfp_avago:
 774         case ixgbe_phy_sfp_ftl:
 775         case ixgbe_phy_sfp_intel:
 776         case ixgbe_phy_sfp_unknown:
 777         case ixgbe_phy_sfp_passive_tyco:
 778         case ixgbe_phy_sfp_passive_unknown:
 779                 return 1;
 780         default:
 781                 return 0;
 782         }
 783 }
 784
 785 static inline int32_t
 786 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 787 {
 788         uint32_t ctrl_ext;
 789         int32_t status;
 790
 791         status = ixgbe_reset_hw(hw);
 792
 793         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 794         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 795         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 796         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 797         IXGBE_WRITE_FLUSH(hw);
 798
 799         return status;
 800 }
 801
 802 static inline void
 803 ixgbe_enable_intr(struct rte_eth_dev *dev)
 804 {
 805         struct ixgbe_interrupt *intr =
 806                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 807         struct ixgbe_hw *hw =
 808                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 809
 810         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 811         IXGBE_WRITE_FLUSH(hw);
 812 }
 813
 814 /*
 815  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 816  */
 817 static void
 818 ixgbe_disable_intr(struct ixgbe_hw *hw)
 819 {
 820         PMD_INIT_FUNC_TRACE();
 821
 822         if (hw->mac.type == ixgbe_mac_82598EB) {
 823                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 824         } else {
 825                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 826                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 827                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 828         }
 829         IXGBE_WRITE_FLUSH(hw);
 830 }
 831
 832 /*
 833  * This function resets queue statistics mapping registers.
 834  * From Niantic datasheet, Initialization of Statistics section:
 835  * "...if software requires the queue counters, the RQSMR and TQSM registers
 836  * must be re-programmed following a device reset.
 837  */
 838 static void
 839 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 840 {
 841         uint32_t i;
 842
 843         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 844                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 845                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 846         }
 847 }
 848
 849
 850 static int
 851 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 852                                   uint16_t queue_id,
 853                                   uint8_t stat_idx,
 854                                   uint8_t is_rx)
 855 {
 856 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 857 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 858 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 859
 860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 861         struct ixgbe_stat_mapping_registers *stat_mappings =
 862                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 863         uint32_t qsmr_mask = 0;
 864         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 865         uint32_t q_map;
 866         uint8_t n, offset;
 867
 868         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 869                 (hw->mac.type != ixgbe_mac_X540) &&
 870                 (hw->mac.type != ixgbe_mac_X550) &&
 871                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 872                 (hw->mac.type != ixgbe_mac_X550EM_a))
 873                 return -ENOSYS;
 874
 875         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 876                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 877                      queue_id, stat_idx);
 878
 879         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 880         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 881                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 882                 return -EIO;
 883         }
 884         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 885
 886         /* Now clear any previous stat_idx set */
 887         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 888         if (!is_rx)
 889                 stat_mappings->tqsm[n] &= ~clearing_mask;
 890         else
 891                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 892
 893         q_map = (uint32_t)stat_idx;
 894         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 895         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 896         if (!is_rx)
 897                 stat_mappings->tqsm[n] |= qsmr_mask;
 898         else
 899                 stat_mappings->rqsmr[n] |= qsmr_mask;
 900
 901         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 902                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 903                      queue_id, stat_idx);
 904         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 905                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 906
 907         /* Now write the mapping in the appropriate register */
 908         if (is_rx) {
 909                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 910                              stat_mappings->rqsmr[n], n);
 911                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 912         } else {
 913                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 914                              stat_mappings->tqsm[n], n);
 915                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 916         }
 917         return 0;
 918 }
 919
 920 static void
 921 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 922 {
 923         struct ixgbe_stat_mapping_registers *stat_mappings =
 924                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 926         int i;
 927
 928         /* write whatever was in stat mapping table to the NIC */
 929         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 930                 /* rx */
 931                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 932
 933                 /* tx */
 934                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 935         }
 936 }
 937
 938 static void
 939 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 940 {
 941         uint8_t i;
 942         struct ixgbe_dcb_tc_config *tc;
 943         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 944
 945         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 946         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 947         for (i = 0; i < dcb_max_tc; i++) {
 948                 tc = &dcb_config->tc_config[i];
 949                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 950                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 951                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 952                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 953                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 954                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 955                 tc->pfc = ixgbe_dcb_pfc_disabled;
 956         }
 957
 958         /* Initialize default user to priority mapping, UPx->TC0 */
 959         tc = &dcb_config->tc_config[0];
 960         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 961         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 962         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 963                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 964                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 965         }
 966         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 967         dcb_config->pfc_mode_enable = false;
 968         dcb_config->vt_mode = true;
 969         dcb_config->round_robin_enable = false;
 970         /* support all DCB capabilities in 82599 */
 971         dcb_config->support.capabilities = 0xFF;
 972
 973         /*we only support 4 Tcs for X540, X550 */
 974         if (hw->mac.type == ixgbe_mac_X540 ||
 975                 hw->mac.type == ixgbe_mac_X550 ||
 976                 hw->mac.type == ixgbe_mac_X550EM_x ||
 977                 hw->mac.type == ixgbe_mac_X550EM_a) {
 978                 dcb_config->num_tcs.pg_tcs = 4;
 979                 dcb_config->num_tcs.pfc_tcs = 4;
 980         }
 981 }
 982
 983 /*
 984  * Ensure that all locks are released before first NVM or PHY access
 985  */
 986 static void
 987 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 988 {
 989         uint16_t mask;
 990
 991         /*
 992          * Phy lock should not fail in this early stage. If this is the case,
 993          * it is due to an improper exit of the application.
 994          * So force the release of the faulty lock. Release of common lock
 995          * is done automatically by swfw_sync function.
 996          */
 997         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 998         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 999                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1000         }
1001         ixgbe_release_swfw_semaphore(hw, mask);
1002
1003         /*
1004          * These ones are more tricky since they are common to all ports; but
1005          * swfw_sync retries last long enough (1s) to be almost sure that if
1006          * lock can not be taken it is due to an improper lock of the
1007          * semaphore.
1008          */
1009         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1010         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1011                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1012         }
1013         ixgbe_release_swfw_semaphore(hw, mask);
1014 }
1015
1016 /*
1017  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1018  * It returns 0 on success.
1019  */
1020 static int
1021 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1022 {
1023         struct rte_pci_device *pci_dev;
1024         struct ixgbe_hw *hw =
1025                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1026         struct ixgbe_vfta *shadow_vfta =
1027                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1028         struct ixgbe_hwstrip *hwstrip =
1029                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1030         struct ixgbe_dcb_config *dcb_config =
1031                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1032         struct ixgbe_filter_info *filter_info =
1033                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1034         uint32_t ctrl_ext;
1035         uint16_t csum;
1036         int diag, i;
1037
1038         PMD_INIT_FUNC_TRACE();
1039
1040         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1041         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1042         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1043
1044         /*
1045          * For secondary processes, we don't initialise any further as primary
1046          * has already done this work. Only check we don't need a different
1047          * RX and TX function.
1048          */
1049         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1050                 struct ixgbe_tx_queue *txq;
1051                 /* TX queue function in primary, set by last queue initialized
1052                  * Tx queue may not initialized by primary process
1053                  */
1054                 if (eth_dev->data->tx_queues) {
1055                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1056                         ixgbe_set_tx_function(eth_dev, txq);
1057                 } else {
1058                         /* Use default TX function if we get here */
1059                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1060                                      "Using default TX function.");
1061                 }
1062
1063                 ixgbe_set_rx_function(eth_dev);
1064
1065                 return 0;
1066         }
1067         pci_dev = eth_dev->pci_dev;
1068
1069         rte_eth_copy_pci_info(eth_dev, pci_dev);
1070
1071         /* Vendor and Device ID need to be set before init of shared code */
1072         hw->device_id = pci_dev->id.device_id;
1073         hw->vendor_id = pci_dev->id.vendor_id;
1074         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1075         hw->allow_unsupported_sfp = 1;
1076
1077         /* Initialize the shared code (base driver) */
1078 #ifdef RTE_NIC_BYPASS
1079         diag = ixgbe_bypass_init_shared_code(hw);
1080 #else
1081         diag = ixgbe_init_shared_code(hw);
1082 #endif /* RTE_NIC_BYPASS */
1083
1084         if (diag != IXGBE_SUCCESS) {
1085                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1086                 return -EIO;
1087         }
1088
1089         /* pick up the PCI bus settings for reporting later */
1090         ixgbe_get_bus_info(hw);
1091
1092         /* Unlock any pending hardware semaphore */
1093         ixgbe_swfw_lock_reset(hw);
1094
1095         /* Initialize DCB configuration*/
1096         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1097         ixgbe_dcb_init(hw, dcb_config);
1098         /* Get Hardware Flow Control setting */
1099         hw->fc.requested_mode = ixgbe_fc_full;
1100         hw->fc.current_mode = ixgbe_fc_full;
1101         hw->fc.pause_time = IXGBE_FC_PAUSE;
1102         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1103                 hw->fc.low_water[i] = IXGBE_FC_LO;
1104                 hw->fc.high_water[i] = IXGBE_FC_HI;
1105         }
1106         hw->fc.send_xon = 1;
1107
1108         /* Make sure we have a good EEPROM before we read from it */
1109         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1110         if (diag != IXGBE_SUCCESS) {
1111                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1112                 return -EIO;
1113         }
1114
1115 #ifdef RTE_NIC_BYPASS
1116         diag = ixgbe_bypass_init_hw(hw);
1117 #else
1118         diag = ixgbe_init_hw(hw);
1119 #endif /* RTE_NIC_BYPASS */
1120
1121         /*
1122          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1123          * is called too soon after the kernel driver unbinding/binding occurs.
1124          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1125          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1126          * also called. See ixgbe_identify_phy_82599(). The reason for the
1127          * failure is not known, and only occuts when virtualisation features
1128          * are disabled in the bios. A delay of 100ms  was found to be enough by
1129          * trial-and-error, and is doubled to be safe.
1130          */
1131         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1132                 rte_delay_ms(200);
1133                 diag = ixgbe_init_hw(hw);
1134         }
1135
1136         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1137                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1138                              "LOM.  Please be aware there may be issues associated "
1139                              "with your hardware.");
1140                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1141                              "please contact your Intel or hardware representative "
1142                              "who provided you with this hardware.");
1143         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1144                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1145         if (diag) {
1146                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1147                 return -EIO;
1148         }
1149
1150         /* Reset the hw statistics */
1151         ixgbe_dev_stats_reset(eth_dev);
1152
1153         /* disable interrupt */
1154         ixgbe_disable_intr(hw);
1155
1156         /* reset mappings for queue statistics hw counters*/
1157         ixgbe_reset_qstat_mappings(hw);
1158
1159         /* Allocate memory for storing MAC addresses */
1160         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1161                                                hw->mac.num_rar_entries, 0);
1162         if (eth_dev->data->mac_addrs == NULL) {
1163                 PMD_INIT_LOG(ERR,
1164                              "Failed to allocate %u bytes needed to store "
1165                              "MAC addresses",
1166                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1167                 return -ENOMEM;
1168         }
1169         /* Copy the permanent MAC address */
1170         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1171                         &eth_dev->data->mac_addrs[0]);
1172
1173         /* Allocate memory for storing hash filter MAC addresses */
1174         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1175                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1176         if (eth_dev->data->hash_mac_addrs == NULL) {
1177                 PMD_INIT_LOG(ERR,
1178                              "Failed to allocate %d bytes needed to store MAC addresses",
1179                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1180                 return -ENOMEM;
1181         }
1182
1183         /* initialize the vfta */
1184         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1185
1186         /* initialize the hw strip bitmap*/
1187         memset(hwstrip, 0, sizeof(*hwstrip));
1188
1189         /* initialize PF if max_vfs not zero */
1190         ixgbe_pf_host_init(eth_dev);
1191
1192         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1193         /* let hardware know driver is loaded */
1194         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1195         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1196         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1197         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1198         IXGBE_WRITE_FLUSH(hw);
1199
1200         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1201                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1202                              (int) hw->mac.type, (int) hw->phy.type,
1203                              (int) hw->phy.sfp_type);
1204         else
1205                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1206                              (int) hw->mac.type, (int) hw->phy.type);
1207
1208         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1209                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1210                      pci_dev->id.device_id);
1211
1212         rte_intr_callback_register(&pci_dev->intr_handle,
1213                                    ixgbe_dev_interrupt_handler,
1214                                    (void *)eth_dev);
1215
1216         /* enable uio/vfio intr/eventfd mapping */
1217         rte_intr_enable(&pci_dev->intr_handle);
1218
1219         /* enable support intr */
1220         ixgbe_enable_intr(eth_dev);
1221
1222         /* initialize 5tuple filter list */
1223         TAILQ_INIT(&filter_info->fivetuple_list);
1224         memset(filter_info->fivetuple_mask, 0,
1225                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1226
1227         return 0;
1228 }
1229
1230 static int
1231 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1232 {
1233         struct rte_pci_device *pci_dev;
1234         struct ixgbe_hw *hw;
1235
1236         PMD_INIT_FUNC_TRACE();
1237
1238         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1239                 return -EPERM;
1240
1241         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1242         pci_dev = eth_dev->pci_dev;
1243
1244         if (hw->adapter_stopped == 0)
1245                 ixgbe_dev_close(eth_dev);
1246
1247         eth_dev->dev_ops = NULL;
1248         eth_dev->rx_pkt_burst = NULL;
1249         eth_dev->tx_pkt_burst = NULL;
1250
1251         /* Unlock any pending hardware semaphore */
1252         ixgbe_swfw_lock_reset(hw);
1253
1254         /* disable uio intr before callback unregister */
1255         rte_intr_disable(&(pci_dev->intr_handle));
1256         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1257                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1258
1259         /* uninitialize PF if max_vfs not zero */
1260         ixgbe_pf_host_uninit(eth_dev);
1261
1262         rte_free(eth_dev->data->mac_addrs);
1263         eth_dev->data->mac_addrs = NULL;
1264
1265         rte_free(eth_dev->data->hash_mac_addrs);
1266         eth_dev->data->hash_mac_addrs = NULL;
1267
1268         return 0;
1269 }
1270
1271 /*
1272  * Negotiate mailbox API version with the PF.
1273  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1274  * Then we try to negotiate starting with the most recent one.
1275  * If all negotiation attempts fail, then we will proceed with
1276  * the default one (ixgbe_mbox_api_10).
1277  */
1278 static void
1279 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1280 {
1281         int32_t i;
1282
1283         /* start with highest supported, proceed down */
1284         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1285                 ixgbe_mbox_api_12,
1286                 ixgbe_mbox_api_11,
1287                 ixgbe_mbox_api_10,
1288         };
1289
1290         for (i = 0;
1291                         i != RTE_DIM(sup_ver) &&
1292                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1293                         i++)
1294                 ;
1295 }
1296
1297 static void
1298 generate_random_mac_addr(struct ether_addr *mac_addr)
1299 {
1300         uint64_t random;
1301
1302         /* Set Organizationally Unique Identifier (OUI) prefix. */
1303         mac_addr->addr_bytes[0] = 0x00;
1304         mac_addr->addr_bytes[1] = 0x09;
1305         mac_addr->addr_bytes[2] = 0xC0;
1306         /* Force indication of locally assigned MAC address. */
1307         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1308         /* Generate the last 3 bytes of the MAC address with a random number. */
1309         random = rte_rand();
1310         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1311 }
1312
1313 /*
1314  * Virtual Function device init
1315  */
1316 static int
1317 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1318 {
1319         int diag;
1320         uint32_t tc, tcs;
1321         struct rte_pci_device *pci_dev;
1322         struct ixgbe_hw *hw =
1323                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1324         struct ixgbe_vfta *shadow_vfta =
1325                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1326         struct ixgbe_hwstrip *hwstrip =
1327                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1328         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1329
1330         PMD_INIT_FUNC_TRACE();
1331
1332         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1333         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1334         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1335
1336         /* for secondary processes, we don't initialise any further as primary
1337          * has already done this work. Only check we don't need a different
1338          * RX function
1339          */
1340         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1341                 struct ixgbe_tx_queue *txq;
1342                 /* TX queue function in primary, set by last queue initialized
1343                  * Tx queue may not initialized by primary process
1344                  */
1345                 if (eth_dev->data->tx_queues) {
1346                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1347                         ixgbe_set_tx_function(eth_dev, txq);
1348                 } else {
1349                         /* Use default TX function if we get here */
1350                         PMD_INIT_LOG(NOTICE,
1351                                      "No TX queues configured yet. Using default TX function.");
1352                 }
1353
1354                 ixgbe_set_rx_function(eth_dev);
1355
1356                 return 0;
1357         }
1358
1359         pci_dev = eth_dev->pci_dev;
1360
1361         rte_eth_copy_pci_info(eth_dev, pci_dev);
1362
1363         hw->device_id = pci_dev->id.device_id;
1364         hw->vendor_id = pci_dev->id.vendor_id;
1365         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1366
1367         /* initialize the vfta */
1368         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1369
1370         /* initialize the hw strip bitmap*/
1371         memset(hwstrip, 0, sizeof(*hwstrip));
1372
1373         /* Initialize the shared code (base driver) */
1374         diag = ixgbe_init_shared_code(hw);
1375         if (diag != IXGBE_SUCCESS) {
1376                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1377                 return -EIO;
1378         }
1379
1380         /* init_mailbox_params */
1381         hw->mbx.ops.init_params(hw);
1382
1383         /* Reset the hw statistics */
1384         ixgbevf_dev_stats_reset(eth_dev);
1385
1386         /* Disable the interrupts for VF */
1387         ixgbevf_intr_disable(hw);
1388
1389         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1390         diag = hw->mac.ops.reset_hw(hw);
1391
1392         /*
1393          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1394          * the underlying PF driver has not assigned a MAC address to the VF.
1395          * In this case, assign a random MAC address.
1396          */
1397         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1398                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1399                 return diag;
1400         }
1401
1402         /* negotiate mailbox API version to use with the PF. */
1403         ixgbevf_negotiate_api(hw);
1404
1405         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1406         ixgbevf_get_queues(hw, &tcs, &tc);
1407
1408         /* Allocate memory for storing MAC addresses */
1409         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1410                                                hw->mac.num_rar_entries, 0);
1411         if (eth_dev->data->mac_addrs == NULL) {
1412                 PMD_INIT_LOG(ERR,
1413                              "Failed to allocate %u bytes needed to store "
1414                              "MAC addresses",
1415                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1416                 return -ENOMEM;
1417         }
1418
1419         /* Generate a random MAC address, if none was assigned by PF. */
1420         if (is_zero_ether_addr(perm_addr)) {
1421                 generate_random_mac_addr(perm_addr);
1422                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1423                 if (diag) {
1424                         rte_free(eth_dev->data->mac_addrs);
1425                         eth_dev->data->mac_addrs = NULL;
1426                         return diag;
1427                 }
1428                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1429                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1430                              "%02x:%02x:%02x:%02x:%02x:%02x",
1431                              perm_addr->addr_bytes[0],
1432                              perm_addr->addr_bytes[1],
1433                              perm_addr->addr_bytes[2],
1434                              perm_addr->addr_bytes[3],
1435                              perm_addr->addr_bytes[4],
1436                              perm_addr->addr_bytes[5]);
1437         }
1438
1439         /* Copy the permanent MAC address */
1440         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1441
1442         /* reset the hardware with the new settings */
1443         diag = hw->mac.ops.start_hw(hw);
1444         switch (diag) {
1445         case  0:
1446                 break;
1447
1448         default:
1449                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1450                 return -EIO;
1451         }
1452
1453         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1454                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1455                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1456
1457         return 0;
1458 }
1459
1460 /* Virtual Function device uninit */
1461
1462 static int
1463 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1464 {
1465         struct ixgbe_hw *hw;
1466
1467         PMD_INIT_FUNC_TRACE();
1468
1469         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1470                 return -EPERM;
1471
1472         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1473
1474         if (hw->adapter_stopped == 0)
1475                 ixgbevf_dev_close(eth_dev);
1476
1477         eth_dev->dev_ops = NULL;
1478         eth_dev->rx_pkt_burst = NULL;
1479         eth_dev->tx_pkt_burst = NULL;
1480
1481         /* Disable the interrupts for VF */
1482         ixgbevf_intr_disable(hw);
1483
1484         rte_free(eth_dev->data->mac_addrs);
1485         eth_dev->data->mac_addrs = NULL;
1486
1487         return 0;
1488 }
1489
1490 static struct eth_driver rte_ixgbe_pmd = {
1491         .pci_drv = {
1492                 .name = "rte_ixgbe_pmd",
1493                 .id_table = pci_id_ixgbe_map,
1494                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1495                         RTE_PCI_DRV_DETACHABLE,
1496         },
1497         .eth_dev_init = eth_ixgbe_dev_init,
1498         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1499         .dev_private_size = sizeof(struct ixgbe_adapter),
1500 };
1501
1502 /*
1503  * virtual function driver struct
1504  */
1505 static struct eth_driver rte_ixgbevf_pmd = {
1506         .pci_drv = {
1507                 .name = "rte_ixgbevf_pmd",
1508                 .id_table = pci_id_ixgbevf_map,
1509                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1510         },
1511         .eth_dev_init = eth_ixgbevf_dev_init,
1512         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1513         .dev_private_size = sizeof(struct ixgbe_adapter),
1514 };
1515
1516 /*
1517  * Driver initialization routine.
1518  * Invoked once at EAL init time.
1519  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1520  */
1521 static int
1522 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1523 {
1524         PMD_INIT_FUNC_TRACE();
1525
1526         rte_eth_driver_register(&rte_ixgbe_pmd);
1527         return 0;
1528 }
1529
1530 /*
1531  * VF Driver initialization routine.
1532  * Invoked one at EAL init time.
1533  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1534  */
1535 static int
1536 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1537 {
1538         PMD_INIT_FUNC_TRACE();
1539
1540         rte_eth_driver_register(&rte_ixgbevf_pmd);
1541         return 0;
1542 }
1543
1544 static int
1545 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1546 {
1547         struct ixgbe_hw *hw =
1548                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1549         struct ixgbe_vfta *shadow_vfta =
1550                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1551         uint32_t vfta;
1552         uint32_t vid_idx;
1553         uint32_t vid_bit;
1554
1555         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1556         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1557         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1558         if (on)
1559                 vfta |= vid_bit;
1560         else
1561                 vfta &= ~vid_bit;
1562         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1563
1564         /* update local VFTA copy */
1565         shadow_vfta->vfta[vid_idx] = vfta;
1566
1567         return 0;
1568 }
1569
1570 static void
1571 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1572 {
1573         if (on)
1574                 ixgbe_vlan_hw_strip_enable(dev, queue);
1575         else
1576                 ixgbe_vlan_hw_strip_disable(dev, queue);
1577 }
1578
1579 static int
1580 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1581                     enum rte_vlan_type vlan_type,
1582                     uint16_t tpid)
1583 {
1584         struct ixgbe_hw *hw =
1585                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586         int ret = 0;
1587
1588         switch (vlan_type) {
1589         case ETH_VLAN_TYPE_INNER:
1590                 /* Only the high 16-bits is valid */
1591                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1592                 break;
1593         default:
1594                 ret = -EINVAL;
1595                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1596                 break;
1597         }
1598
1599         return ret;
1600 }
1601
1602 void
1603 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1604 {
1605         struct ixgbe_hw *hw =
1606                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1607         uint32_t vlnctrl;
1608
1609         PMD_INIT_FUNC_TRACE();
1610
1611         /* Filter Table Disable */
1612         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1613         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1614
1615         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1616 }
1617
1618 void
1619 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1620 {
1621         struct ixgbe_hw *hw =
1622                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623         struct ixgbe_vfta *shadow_vfta =
1624                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1625         uint32_t vlnctrl;
1626         uint16_t i;
1627
1628         PMD_INIT_FUNC_TRACE();
1629
1630         /* Filter Table Enable */
1631         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1632         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1633         vlnctrl |= IXGBE_VLNCTRL_VFE;
1634
1635         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1636
1637         /* write whatever is in local vfta copy */
1638         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1639                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1640 }
1641
1642 static void
1643 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1644 {
1645         struct ixgbe_hwstrip *hwstrip =
1646                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1647         struct ixgbe_rx_queue *rxq;
1648
1649         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1650                 return;
1651
1652         if (on)
1653                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1654         else
1655                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1656
1657         if (queue >= dev->data->nb_rx_queues)
1658                 return;
1659
1660         rxq = dev->data->rx_queues[queue];
1661
1662         if (on)
1663                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1664         else
1665                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1666 }
1667
1668 static void
1669 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1670 {
1671         struct ixgbe_hw *hw =
1672                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673         uint32_t ctrl;
1674
1675         PMD_INIT_FUNC_TRACE();
1676
1677         if (hw->mac.type == ixgbe_mac_82598EB) {
1678                 /* No queue level support */
1679                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1680                 return;
1681         }
1682
1683         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1684         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1685         ctrl &= ~IXGBE_RXDCTL_VME;
1686         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1687
1688         /* record those setting for HW strip per queue */
1689         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1690 }
1691
1692 static void
1693 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1694 {
1695         struct ixgbe_hw *hw =
1696                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1697         uint32_t ctrl;
1698
1699         PMD_INIT_FUNC_TRACE();
1700
1701         if (hw->mac.type == ixgbe_mac_82598EB) {
1702                 /* No queue level supported */
1703                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1704                 return;
1705         }
1706
1707         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1708         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1709         ctrl |= IXGBE_RXDCTL_VME;
1710         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1711
1712         /* record those setting for HW strip per queue */
1713         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1714 }
1715
1716 void
1717 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1718 {
1719         struct ixgbe_hw *hw =
1720                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1721         uint32_t ctrl;
1722         uint16_t i;
1723
1724         PMD_INIT_FUNC_TRACE();
1725
1726         if (hw->mac.type == ixgbe_mac_82598EB) {
1727                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1728                 ctrl &= ~IXGBE_VLNCTRL_VME;
1729                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1730         } else {
1731                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1732                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1733                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1734                         ctrl &= ~IXGBE_RXDCTL_VME;
1735                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1736
1737                         /* record those setting for HW strip per queue */
1738                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1739                 }
1740         }
1741 }
1742
1743 void
1744 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1745 {
1746         struct ixgbe_hw *hw =
1747                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1748         uint32_t ctrl;
1749         uint16_t i;
1750
1751         PMD_INIT_FUNC_TRACE();
1752
1753         if (hw->mac.type == ixgbe_mac_82598EB) {
1754                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1755                 ctrl |= IXGBE_VLNCTRL_VME;
1756                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1757         } else {
1758                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1759                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1760                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1761                         ctrl |= IXGBE_RXDCTL_VME;
1762                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1763
1764                         /* record those setting for HW strip per queue */
1765                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1766                 }
1767         }
1768 }
1769
1770 static void
1771 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1772 {
1773         struct ixgbe_hw *hw =
1774                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775         uint32_t ctrl;
1776
1777         PMD_INIT_FUNC_TRACE();
1778
1779         /* DMATXCTRL: Geric Double VLAN Disable */
1780         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1781         ctrl &= ~IXGBE_DMATXCTL_GDV;
1782         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1783
1784         /* CTRL_EXT: Global Double VLAN Disable */
1785         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1786         ctrl &= ~IXGBE_EXTENDED_VLAN;
1787         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1788
1789 }
1790
1791 static void
1792 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1793 {
1794         struct ixgbe_hw *hw =
1795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796         uint32_t ctrl;
1797
1798         PMD_INIT_FUNC_TRACE();
1799
1800         /* DMATXCTRL: Geric Double VLAN Enable */
1801         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1802         ctrl |= IXGBE_DMATXCTL_GDV;
1803         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1804
1805         /* CTRL_EXT: Global Double VLAN Enable */
1806         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1807         ctrl |= IXGBE_EXTENDED_VLAN;
1808         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1809
1810         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1811         if (hw->mac.type == ixgbe_mac_X550 ||
1812             hw->mac.type == ixgbe_mac_X550EM_x ||
1813             hw->mac.type == ixgbe_mac_X550EM_a) {
1814                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1815                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1816                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1817         }
1818
1819         /*
1820          * VET EXT field in the EXVET register = 0x8100 by default
1821          * So no need to change. Same to VT field of DMATXCTL register
1822          */
1823 }
1824
1825 static void
1826 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1827 {
1828         if (mask & ETH_VLAN_STRIP_MASK) {
1829                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1830                         ixgbe_vlan_hw_strip_enable_all(dev);
1831                 else
1832                         ixgbe_vlan_hw_strip_disable_all(dev);
1833         }
1834
1835         if (mask & ETH_VLAN_FILTER_MASK) {
1836                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1837                         ixgbe_vlan_hw_filter_enable(dev);
1838                 else
1839                         ixgbe_vlan_hw_filter_disable(dev);
1840         }
1841
1842         if (mask & ETH_VLAN_EXTEND_MASK) {
1843                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1844                         ixgbe_vlan_hw_extend_enable(dev);
1845                 else
1846                         ixgbe_vlan_hw_extend_disable(dev);
1847         }
1848 }
1849
1850 static void
1851 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1852 {
1853         struct ixgbe_hw *hw =
1854                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1856         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1857
1858         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1859         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1860 }
1861
1862 static int
1863 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1864 {
1865         switch (nb_rx_q) {
1866         case 1:
1867         case 2:
1868                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1869                 break;
1870         case 4:
1871                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1872                 break;
1873         default:
1874                 return -EINVAL;
1875         }
1876
1877         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1878         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1879
1880         return 0;
1881 }
1882
1883 static int
1884 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1885 {
1886         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1888         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1889         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1890
1891         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1892                 /* check multi-queue mode */
1893                 switch (dev_conf->rxmode.mq_mode) {
1894                 case ETH_MQ_RX_VMDQ_DCB:
1895                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1896                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1897                         PMD_INIT_LOG(ERR, "SRIOV active,"
1898                                         " unsupported mq_mode rx %d.",
1899                                         dev_conf->rxmode.mq_mode);
1900                         return -EINVAL;
1901                 case ETH_MQ_RX_RSS:
1902                 case ETH_MQ_RX_VMDQ_RSS:
1903                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1904                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1905                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1906                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1907                                                 " invalid queue number"
1908                                                 " for VMDQ RSS, allowed"
1909                                                 " value are 1, 2 or 4.");
1910                                         return -EINVAL;
1911                                 }
1912                         break;
1913                 case ETH_MQ_RX_VMDQ_ONLY:
1914                 case ETH_MQ_RX_NONE:
1915                         /* if nothing mq mode configure, use default scheme */
1916                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1917                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1918                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1919                         break;
1920                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1921                         /* SRIOV only works in VMDq enable mode */
1922                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1923                                         " wrong mq_mode rx %d.",
1924                                         dev_conf->rxmode.mq_mode);
1925                         return -EINVAL;
1926                 }
1927
1928                 switch (dev_conf->txmode.mq_mode) {
1929                 case ETH_MQ_TX_VMDQ_DCB:
1930                         /* DCB VMDQ in SRIOV mode, not implement yet */
1931                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1932                                         " unsupported VMDQ mq_mode tx %d.",
1933                                         dev_conf->txmode.mq_mode);
1934                         return -EINVAL;
1935                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1936                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1937                         break;
1938                 }
1939
1940                 /* check valid queue number */
1941                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1942                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1943                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1944                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1945                                         " must be less than or equal to %d.",
1946                                         nb_rx_q, nb_tx_q,
1947                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1948                         return -EINVAL;
1949                 }
1950         } else {
1951                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1952                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1953                                           " not supported.");
1954                         return -EINVAL;
1955                 }
1956                 /* check configuration for vmdb+dcb mode */
1957                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1958                         const struct rte_eth_vmdq_dcb_conf *conf;
1959
1960                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1961                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1962                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1963                                 return -EINVAL;
1964                         }
1965                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1966                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1967                                conf->nb_queue_pools == ETH_32_POOLS)) {
1968                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1969                                                 " nb_queue_pools must be %d or %d.",
1970                                                 ETH_16_POOLS, ETH_32_POOLS);
1971                                 return -EINVAL;
1972                         }
1973                 }
1974                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1975                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1976
1977                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1978                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1979                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1980                                 return -EINVAL;
1981                         }
1982                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1983                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1984                                conf->nb_queue_pools == ETH_32_POOLS)) {
1985                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1986                                                 " nb_queue_pools != %d and"
1987                                                 " nb_queue_pools != %d.",
1988                                                 ETH_16_POOLS, ETH_32_POOLS);
1989                                 return -EINVAL;
1990                         }
1991                 }
1992
1993                 /* For DCB mode check our configuration before we go further */
1994                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1995                         const struct rte_eth_dcb_rx_conf *conf;
1996
1997                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1998                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1999                                                  IXGBE_DCB_NB_QUEUES);
2000                                 return -EINVAL;
2001                         }
2002                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2003                         if (!(conf->nb_tcs == ETH_4_TCS ||
2004                                conf->nb_tcs == ETH_8_TCS)) {
2005                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2006                                                 " and nb_tcs != %d.",
2007                                                 ETH_4_TCS, ETH_8_TCS);
2008                                 return -EINVAL;
2009                         }
2010                 }
2011
2012                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2013                         const struct rte_eth_dcb_tx_conf *conf;
2014
2015                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2016                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2017                                                  IXGBE_DCB_NB_QUEUES);
2018                                 return -EINVAL;
2019                         }
2020                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2021                         if (!(conf->nb_tcs == ETH_4_TCS ||
2022                                conf->nb_tcs == ETH_8_TCS)) {
2023                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2024                                                 " and nb_tcs != %d.",
2025                                                 ETH_4_TCS, ETH_8_TCS);
2026                                 return -EINVAL;
2027                         }
2028                 }
2029
2030                 /*
2031                  * When DCB/VT is off, maximum number of queues changes,
2032                  * except for 82598EB, which remains constant.
2033                  */
2034                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2035                                 hw->mac.type != ixgbe_mac_82598EB) {
2036                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2037                                 PMD_INIT_LOG(ERR,
2038                                              "Neither VT nor DCB are enabled, "
2039                                              "nb_tx_q > %d.",
2040                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2041                                 return -EINVAL;
2042                         }
2043                 }
2044         }
2045         return 0;
2046 }
2047
2048 static int
2049 ixgbe_dev_configure(struct rte_eth_dev *dev)
2050 {
2051         struct ixgbe_interrupt *intr =
2052                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2053         struct ixgbe_adapter *adapter =
2054                 (struct ixgbe_adapter *)dev->data->dev_private;
2055         int ret;
2056
2057         PMD_INIT_FUNC_TRACE();
2058         /* multipe queue mode checking */
2059         ret  = ixgbe_check_mq_mode(dev);
2060         if (ret != 0) {
2061                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2062                             ret);
2063                 return ret;
2064         }
2065
2066         /* set flag to update link status after init */
2067         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2068
2069         /*
2070          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2071          * allocation or vector Rx preconditions we will reset it.
2072          */
2073         adapter->rx_bulk_alloc_allowed = true;
2074         adapter->rx_vec_allowed = true;
2075
2076         return 0;
2077 }
2078
2079 static void
2080 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2081 {
2082         struct ixgbe_hw *hw =
2083                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084         struct ixgbe_interrupt *intr =
2085                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2086         uint32_t gpie;
2087
2088         /* only set up it on X550EM_X */
2089         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2090                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2091                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2092                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2093                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2094                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2095         }
2096 }
2097
2098 /*
2099  * Configure device link speed and setup link.
2100  * It returns 0 on success.
2101  */
2102 static int
2103 ixgbe_dev_start(struct rte_eth_dev *dev)
2104 {
2105         struct ixgbe_hw *hw =
2106                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct ixgbe_vf_info *vfinfo =
2108                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2109         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2110         uint32_t intr_vector = 0;
2111         int err, link_up = 0, negotiate = 0;
2112         uint32_t speed = 0;
2113         int mask = 0;
2114         int status;
2115         uint16_t vf, idx;
2116         uint32_t *link_speeds;
2117
2118         PMD_INIT_FUNC_TRACE();
2119
2120         /* IXGBE devices don't support:
2121         *    - half duplex (checked afterwards for valid speeds)
2122         *    - fixed speed: TODO implement
2123         */
2124         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2125                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2126                              dev->data->port_id);
2127                 return -EINVAL;
2128         }
2129
2130         /* disable uio/vfio intr/eventfd mapping */
2131         rte_intr_disable(intr_handle);
2132
2133         /* stop adapter */
2134         hw->adapter_stopped = 0;
2135         ixgbe_stop_adapter(hw);
2136
2137         /* reinitialize adapter
2138          * this calls reset and start
2139          */
2140         status = ixgbe_pf_reset_hw(hw);
2141         if (status != 0)
2142                 return -1;
2143         hw->mac.ops.start_hw(hw);
2144         hw->mac.get_link_status = true;
2145
2146         /* configure PF module if SRIOV enabled */
2147         ixgbe_pf_host_configure(dev);
2148
2149         ixgbe_dev_phy_intr_setup(dev);
2150
2151         /* check and configure queue intr-vector mapping */
2152         if ((rte_intr_cap_multiple(intr_handle) ||
2153              !RTE_ETH_DEV_SRIOV(dev).active) &&
2154             dev->data->dev_conf.intr_conf.rxq != 0) {
2155                 intr_vector = dev->data->nb_rx_queues;
2156                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2157                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2158                                         IXGBE_MAX_INTR_QUEUE_NUM);
2159                         return -ENOTSUP;
2160                 }
2161                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2162                         return -1;
2163         }
2164
2165         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2166                 intr_handle->intr_vec =
2167                         rte_zmalloc("intr_vec",
2168                                     dev->data->nb_rx_queues * sizeof(int), 0);
2169                 if (intr_handle->intr_vec == NULL) {
2170                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2171                                      " intr_vec\n", dev->data->nb_rx_queues);
2172                         return -ENOMEM;
2173                 }
2174         }
2175
2176         /* confiugre msix for sleep until rx interrupt */
2177         ixgbe_configure_msix(dev);
2178
2179         /* initialize transmission unit */
2180         ixgbe_dev_tx_init(dev);
2181
2182         /* This can fail when allocating mbufs for descriptor rings */
2183         err = ixgbe_dev_rx_init(dev);
2184         if (err) {
2185                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2186                 goto error;
2187         }
2188
2189         err = ixgbe_dev_rxtx_start(dev);
2190         if (err < 0) {
2191                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2192                 goto error;
2193         }
2194
2195         /* Skip link setup if loopback mode is enabled for 82599. */
2196         if (hw->mac.type == ixgbe_mac_82599EB &&
2197                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2198                 goto skip_link_setup;
2199
2200         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2201                 err = hw->mac.ops.setup_sfp(hw);
2202                 if (err)
2203                         goto error;
2204         }
2205
2206         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2207                 /* Turn on the copper */
2208                 ixgbe_set_phy_power(hw, true);
2209         } else {
2210                 /* Turn on the laser */
2211                 ixgbe_enable_tx_laser(hw);
2212         }
2213
2214         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2215         if (err)
2216                 goto error;
2217         dev->data->dev_link.link_status = link_up;
2218
2219         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2220         if (err)
2221                 goto error;
2222
2223         link_speeds = &dev->data->dev_conf.link_speeds;
2224         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2225                         ETH_LINK_SPEED_10G)) {
2226                 PMD_INIT_LOG(ERR, "Invalid link setting");
2227                 goto error;
2228         }
2229
2230         speed = 0x0;
2231         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2232                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2233                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2234                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2235         } else {
2236                 if (*link_speeds & ETH_LINK_SPEED_10G)
2237                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2238                 if (*link_speeds & ETH_LINK_SPEED_1G)
2239                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2240                 if (*link_speeds & ETH_LINK_SPEED_100M)
2241                         speed |= IXGBE_LINK_SPEED_100_FULL;
2242         }
2243
2244         err = ixgbe_setup_link(hw, speed, link_up);
2245         if (err)
2246                 goto error;
2247
2248 skip_link_setup:
2249
2250         if (rte_intr_allow_others(intr_handle)) {
2251                 /* check if lsc interrupt is enabled */
2252                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2253                         ixgbe_dev_lsc_interrupt_setup(dev);
2254         } else {
2255                 rte_intr_callback_unregister(intr_handle,
2256                                              ixgbe_dev_interrupt_handler,
2257                                              (void *)dev);
2258                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2259                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2260                                      " no intr multiplex\n");
2261         }
2262
2263         /* check if rxq interrupt is enabled */
2264         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2265             rte_intr_dp_is_en(intr_handle))
2266                 ixgbe_dev_rxq_interrupt_setup(dev);
2267
2268         /* enable uio/vfio intr/eventfd mapping */
2269         rte_intr_enable(intr_handle);
2270
2271         /* resume enabled intr since hw reset */
2272         ixgbe_enable_intr(dev);
2273
2274         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2275                 ETH_VLAN_EXTEND_MASK;
2276         ixgbe_vlan_offload_set(dev, mask);
2277
2278         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2279                 /* Enable vlan filtering for VMDq */
2280                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2281         }
2282
2283         /* Configure DCB hw */
2284         ixgbe_configure_dcb(dev);
2285
2286         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2287                 err = ixgbe_fdir_configure(dev);
2288                 if (err)
2289                         goto error;
2290         }
2291
2292         /* Restore vf rate limit */
2293         if (vfinfo != NULL) {
2294                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2295                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2296                                 if (vfinfo[vf].tx_rate[idx] != 0)
2297                                         ixgbe_set_vf_rate_limit(dev, vf,
2298                                                 vfinfo[vf].tx_rate[idx],
2299                                                 1 << idx);
2300         }
2301
2302         ixgbe_restore_statistics_mapping(dev);
2303
2304         return 0;
2305
2306 error:
2307         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2308         ixgbe_dev_clear_queues(dev);
2309         return -EIO;
2310 }
2311
2312 /*
2313  * Stop device: disable rx and tx functions to allow for reconfiguring.
2314  */
2315 static void
2316 ixgbe_dev_stop(struct rte_eth_dev *dev)
2317 {
2318         struct rte_eth_link link;
2319         struct ixgbe_hw *hw =
2320                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2321         struct ixgbe_vf_info *vfinfo =
2322                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2323         struct ixgbe_filter_info *filter_info =
2324                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2325         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2326         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2327         int vf;
2328
2329         PMD_INIT_FUNC_TRACE();
2330
2331         /* disable interrupts */
2332         ixgbe_disable_intr(hw);
2333
2334         /* reset the NIC */
2335         ixgbe_pf_reset_hw(hw);
2336         hw->adapter_stopped = 0;
2337
2338         /* stop adapter */
2339         ixgbe_stop_adapter(hw);
2340
2341         for (vf = 0; vfinfo != NULL &&
2342                      vf < dev->pci_dev->max_vfs; vf++)
2343                 vfinfo[vf].clear_to_send = false;
2344
2345         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2346                 /* Turn off the copper */
2347                 ixgbe_set_phy_power(hw, false);
2348         } else {
2349                 /* Turn off the laser */
2350                 ixgbe_disable_tx_laser(hw);
2351         }
2352
2353         ixgbe_dev_clear_queues(dev);
2354
2355         /* Clear stored conf */
2356         dev->data->scattered_rx = 0;
2357         dev->data->lro = 0;
2358
2359         /* Clear recorded link status */
2360         memset(&link, 0, sizeof(link));
2361         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2362
2363         /* Remove all ntuple filters of the device */
2364         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2365              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2366                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2367                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2368                              p_5tuple, entries);
2369                 rte_free(p_5tuple);
2370         }
2371         memset(filter_info->fivetuple_mask, 0,
2372                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2373
2374         if (!rte_intr_allow_others(intr_handle))
2375                 /* resume to the default handler */
2376                 rte_intr_callback_register(intr_handle,
2377                                            ixgbe_dev_interrupt_handler,
2378                                            (void *)dev);
2379
2380         /* Clean datapath event and queue/vec mapping */
2381         rte_intr_efd_disable(intr_handle);
2382         if (intr_handle->intr_vec != NULL) {
2383                 rte_free(intr_handle->intr_vec);
2384                 intr_handle->intr_vec = NULL;
2385         }
2386 }
2387
2388 /*
2389  * Set device link up: enable tx.
2390  */
2391 static int
2392 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2393 {
2394         struct ixgbe_hw *hw =
2395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396         if (hw->mac.type == ixgbe_mac_82599EB) {
2397 #ifdef RTE_NIC_BYPASS
2398                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2399                         /* Not suported in bypass mode */
2400                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2401                                      "by device id 0x%x", hw->device_id);
2402                         return -ENOTSUP;
2403                 }
2404 #endif
2405         }
2406
2407         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2408                 /* Turn on the copper */
2409                 ixgbe_set_phy_power(hw, true);
2410         } else {
2411                 /* Turn on the laser */
2412                 ixgbe_enable_tx_laser(hw);
2413         }
2414
2415         return 0;
2416 }
2417
2418 /*
2419  * Set device link down: disable tx.
2420  */
2421 static int
2422 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2423 {
2424         struct ixgbe_hw *hw =
2425                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2426         if (hw->mac.type == ixgbe_mac_82599EB) {
2427 #ifdef RTE_NIC_BYPASS
2428                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2429                         /* Not suported in bypass mode */
2430                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2431                                      "by device id 0x%x", hw->device_id);
2432                         return -ENOTSUP;
2433                 }
2434 #endif
2435         }
2436
2437         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2438                 /* Turn off the copper */
2439                 ixgbe_set_phy_power(hw, false);
2440         } else {
2441                 /* Turn off the laser */
2442                 ixgbe_disable_tx_laser(hw);
2443         }
2444
2445         return 0;
2446 }
2447
2448 /*
2449  * Reest and stop device.
2450  */
2451 static void
2452 ixgbe_dev_close(struct rte_eth_dev *dev)
2453 {
2454         struct ixgbe_hw *hw =
2455                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456
2457         PMD_INIT_FUNC_TRACE();
2458
2459         ixgbe_pf_reset_hw(hw);
2460
2461         ixgbe_dev_stop(dev);
2462         hw->adapter_stopped = 1;
2463
2464         ixgbe_dev_free_queues(dev);
2465
2466         ixgbe_disable_pcie_master(hw);
2467
2468         /* reprogram the RAR[0] in case user changed it. */
2469         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2470 }
2471
2472 static void
2473 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2474                            struct ixgbe_hw_stats *hw_stats,
2475                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2476                            uint64_t *total_qprc, uint64_t *total_qprdc)
2477 {
2478         uint32_t bprc, lxon, lxoff, total;
2479         uint32_t delta_gprc = 0;
2480         unsigned i;
2481         /* Workaround for RX byte count not including CRC bytes when CRC
2482 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2483          * is disabled.
2484 +        */
2485         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2486                         IXGBE_HLREG0_RXCRCSTRP);
2487
2488         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2489         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2490         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2491         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2492
2493         for (i = 0; i < 8; i++) {
2494                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2495
2496                 /* global total per queue */
2497                 hw_stats->mpc[i] += mp;
2498                 /* Running comprehensive total for stats display */
2499                 *total_missed_rx += hw_stats->mpc[i];
2500                 if (hw->mac.type == ixgbe_mac_82598EB) {
2501                         hw_stats->rnbc[i] +=
2502                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2503                         hw_stats->pxonrxc[i] +=
2504                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2505                         hw_stats->pxoffrxc[i] +=
2506                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2507                 } else {
2508                         hw_stats->pxonrxc[i] +=
2509                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2510                         hw_stats->pxoffrxc[i] +=
2511                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2512                         hw_stats->pxon2offc[i] +=
2513                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2514                 }
2515                 hw_stats->pxontxc[i] +=
2516                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2517                 hw_stats->pxofftxc[i] +=
2518                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2519         }
2520         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2521                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2522                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2523                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2524
2525                 delta_gprc += delta_qprc;
2526
2527                 hw_stats->qprc[i] += delta_qprc;
2528                 hw_stats->qptc[i] += delta_qptc;
2529
2530                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2531                 hw_stats->qbrc[i] +=
2532                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2533                 if (crc_strip == 0)
2534                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2535
2536                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2537                 hw_stats->qbtc[i] +=
2538                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2539
2540                 hw_stats->qprdc[i] += delta_qprdc;
2541                 *total_qprdc += hw_stats->qprdc[i];
2542
2543                 *total_qprc += hw_stats->qprc[i];
2544                 *total_qbrc += hw_stats->qbrc[i];
2545         }
2546         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2547         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2548         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2549
2550         /*
2551          * An errata states that gprc actually counts good + missed packets:
2552          * Workaround to set gprc to summated queue packet receives
2553          */
2554         hw_stats->gprc = *total_qprc;
2555
2556         if (hw->mac.type != ixgbe_mac_82598EB) {
2557                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2558                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2559                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2560                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2561                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2562                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2563                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2564                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2565         } else {
2566                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2567                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2568                 /* 82598 only has a counter in the high register */
2569                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2570                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2571                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2572         }
2573         uint64_t old_tpr = hw_stats->tpr;
2574
2575         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2576         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2577
2578         if (crc_strip == 0)
2579                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2580
2581         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2582         hw_stats->gptc += delta_gptc;
2583         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2584         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2585
2586         /*
2587          * Workaround: mprc hardware is incorrectly counting
2588          * broadcasts, so for now we subtract those.
2589          */
2590         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2591         hw_stats->bprc += bprc;
2592         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2593         if (hw->mac.type == ixgbe_mac_82598EB)
2594                 hw_stats->mprc -= bprc;
2595
2596         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2597         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2598         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2599         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2600         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2601         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2602
2603         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2604         hw_stats->lxontxc += lxon;
2605         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2606         hw_stats->lxofftxc += lxoff;
2607         total = lxon + lxoff;
2608
2609         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2610         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2611         hw_stats->gptc -= total;
2612         hw_stats->mptc -= total;
2613         hw_stats->ptc64 -= total;
2614         hw_stats->gotc -= total * ETHER_MIN_LEN;
2615
2616         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2617         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2618         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2619         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2620         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2621         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2622         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2623         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2624         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2625         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2626         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2627         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2628         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2629         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2630         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2631         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2632         /* Only read FCOE on 82599 */
2633         if (hw->mac.type != ixgbe_mac_82598EB) {
2634                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2635                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2636                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2637                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2638                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2639         }
2640
2641         /* Flow Director Stats registers */
2642         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2643         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2644 }
2645
2646 /*
2647  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2648  */
2649 static void
2650 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2651 {
2652         struct ixgbe_hw *hw =
2653                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654         struct ixgbe_hw_stats *hw_stats =
2655                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2656         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2657         unsigned i;
2658
2659         total_missed_rx = 0;
2660         total_qbrc = 0;
2661         total_qprc = 0;
2662         total_qprdc = 0;
2663
2664         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2665                         &total_qprc, &total_qprdc);
2666
2667         if (stats == NULL)
2668                 return;
2669
2670         /* Fill out the rte_eth_stats statistics structure */
2671         stats->ipackets = total_qprc;
2672         stats->ibytes = total_qbrc;
2673         stats->opackets = hw_stats->gptc;
2674         stats->obytes = hw_stats->gotc;
2675
2676         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2677                 stats->q_ipackets[i] = hw_stats->qprc[i];
2678                 stats->q_opackets[i] = hw_stats->qptc[i];
2679                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2680                 stats->q_obytes[i] = hw_stats->qbtc[i];
2681                 stats->q_errors[i] = hw_stats->qprdc[i];
2682         }
2683
2684         /* Rx Errors */
2685         stats->imissed  = total_missed_rx;
2686         stats->ierrors  = hw_stats->crcerrs +
2687                           hw_stats->mspdc +
2688                           hw_stats->rlec +
2689                           hw_stats->ruc +
2690                           hw_stats->roc +
2691                           hw_stats->illerrc +
2692                           hw_stats->errbc +
2693                           hw_stats->rfc +
2694                           hw_stats->fccrc +
2695                           hw_stats->fclast;
2696
2697         /* Tx Errors */
2698         stats->oerrors  = 0;
2699 }
2700
2701 static void
2702 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2703 {
2704         struct ixgbe_hw_stats *stats =
2705                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2706
2707         /* HW registers are cleared on read */
2708         ixgbe_dev_stats_get(dev, NULL);
2709
2710         /* Reset software totals */
2711         memset(stats, 0, sizeof(*stats));
2712 }
2713
2714 /* This function calculates the number of xstats based on the current config */
2715 static unsigned
2716 ixgbe_xstats_calc_num(void) {
2717         return IXGBE_NB_HW_STATS +
2718                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2719                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2720 }
2721
2722 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2723         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2724 {
2725         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2726         unsigned stat, i, count;
2727
2728         if (xstats_names != NULL) {
2729                 count = 0;
2730
2731                 /* Note: limit >= cnt_stats checked upstream
2732                  * in rte_eth_xstats_names()
2733                  */
2734
2735                 /* Extended stats from ixgbe_hw_stats */
2736                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2737                         xstats_names[count].id = count;
2738                         snprintf(xstats_names[count].name,
2739                                 sizeof(xstats_names[count].name),
2740                                 "%s",
2741                                 rte_ixgbe_stats_strings[i].name);
2742                         count++;
2743                 }
2744
2745                 /* RX Priority Stats */
2746                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2747                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2748                                 xstats_names[count].id = count;
2749                                 snprintf(xstats_names[count].name,
2750                                         sizeof(xstats_names[count].name),
2751                                         "rx_priority%u_%s", i,
2752                                         rte_ixgbe_rxq_strings[stat].name);
2753                                 count++;
2754                         }
2755                 }
2756
2757                 /* TX Priority Stats */
2758                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2759                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2760                                 xstats_names[count].id = count;
2761                                 snprintf(xstats_names[count].name,
2762                                         sizeof(xstats_names[count].name),
2763                                         "tx_priority%u_%s", i,
2764                                         rte_ixgbe_txq_strings[stat].name);
2765                                 count++;
2766                         }
2767                 }
2768         }
2769         return cnt_stats;
2770 }
2771
2772 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2773         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2774 {
2775         unsigned i;
2776
2777         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2778                 return -ENOMEM;
2779
2780         if (xstats_names != NULL)
2781                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2782                         snprintf(xstats_names[i].name,
2783                                 sizeof(xstats_names[i].name),
2784                                 "%s", rte_ixgbevf_stats_strings[i].name);
2785         return IXGBEVF_NB_XSTATS;
2786 }
2787
2788 static int
2789 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2790                                          unsigned n)
2791 {
2792         struct ixgbe_hw *hw =
2793                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794         struct ixgbe_hw_stats *hw_stats =
2795                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2796         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2797         unsigned i, stat, count = 0;
2798
2799         count = ixgbe_xstats_calc_num();
2800
2801         if (n < count)
2802                 return count;
2803
2804         total_missed_rx = 0;
2805         total_qbrc = 0;
2806         total_qprc = 0;
2807         total_qprdc = 0;
2808
2809         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2810                                    &total_qprc, &total_qprdc);
2811
2812         /* If this is a reset xstats is NULL, and we have cleared the
2813          * registers by reading them.
2814          */
2815         if (!xstats)
2816                 return 0;
2817
2818         /* Extended stats from ixgbe_hw_stats */
2819         count = 0;
2820         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2821                 xstats[count].id = count;
2822                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2823                                 rte_ixgbe_stats_strings[i].offset);
2824                 count++;
2825         }
2826
2827         /* RX Priority Stats */
2828         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2829                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2830                         xstats[count].id = count;
2831                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2832                                         rte_ixgbe_rxq_strings[stat].offset +
2833                                         (sizeof(uint64_t) * i));
2834                         count++;
2835                 }
2836         }
2837
2838         /* TX Priority Stats */
2839         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2840                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2841                         xstats[count].id = count;
2842                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2843                                         rte_ixgbe_txq_strings[stat].offset +
2844                                         (sizeof(uint64_t) * i));
2845                         count++;
2846                 }
2847         }
2848         return count;
2849 }
2850
2851 static void
2852 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2853 {
2854         struct ixgbe_hw_stats *stats =
2855                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2856
2857         unsigned count = ixgbe_xstats_calc_num();
2858
2859         /* HW registers are cleared on read */
2860         ixgbe_dev_xstats_get(dev, NULL, count);
2861
2862         /* Reset software totals */
2863         memset(stats, 0, sizeof(*stats));
2864 }
2865
2866 static void
2867 ixgbevf_update_stats(struct rte_eth_dev *dev)
2868 {
2869         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2870         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2871                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2872
2873         /* Good Rx packet, include VF loopback */
2874         UPDATE_VF_STAT(IXGBE_VFGPRC,
2875             hw_stats->last_vfgprc, hw_stats->vfgprc);
2876
2877         /* Good Rx octets, include VF loopback */
2878         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2879             hw_stats->last_vfgorc, hw_stats->vfgorc);
2880
2881         /* Good Tx packet, include VF loopback */
2882         UPDATE_VF_STAT(IXGBE_VFGPTC,
2883             hw_stats->last_vfgptc, hw_stats->vfgptc);
2884
2885         /* Good Tx octets, include VF loopback */
2886         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2887             hw_stats->last_vfgotc, hw_stats->vfgotc);
2888
2889         /* Rx Multicst Packet */
2890         UPDATE_VF_STAT(IXGBE_VFMPRC,
2891             hw_stats->last_vfmprc, hw_stats->vfmprc);
2892 }
2893
2894 static int
2895 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2896                        unsigned n)
2897 {
2898         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2899                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2900         unsigned i;
2901
2902         if (n < IXGBEVF_NB_XSTATS)
2903                 return IXGBEVF_NB_XSTATS;
2904
2905         ixgbevf_update_stats(dev);
2906
2907         if (!xstats)
2908                 return 0;
2909
2910         /* Extended stats */
2911         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2912                 xstats[i].id = i;
2913                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2914                         rte_ixgbevf_stats_strings[i].offset);
2915         }
2916
2917         return IXGBEVF_NB_XSTATS;
2918 }
2919
2920 static void
2921 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2922 {
2923         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2924                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2925
2926         ixgbevf_update_stats(dev);
2927
2928         if (stats == NULL)
2929                 return;
2930
2931         stats->ipackets = hw_stats->vfgprc;
2932         stats->ibytes = hw_stats->vfgorc;
2933         stats->opackets = hw_stats->vfgptc;
2934         stats->obytes = hw_stats->vfgotc;
2935 }
2936
2937 static void
2938 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2939 {
2940         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2941                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2942
2943         /* Sync HW register to the last stats */
2944         ixgbevf_dev_stats_get(dev, NULL);
2945
2946         /* reset HW current stats*/
2947         hw_stats->vfgprc = 0;
2948         hw_stats->vfgorc = 0;
2949         hw_stats->vfgptc = 0;
2950         hw_stats->vfgotc = 0;
2951 }
2952
2953 static void
2954 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2955 {
2956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2957         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2958
2959         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2960         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2961         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
2962                 /*
2963                  * When DCB/VT is off, maximum number of queues changes,
2964                  * except for 82598EB, which remains constant.
2965                  */
2966                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2967                                 hw->mac.type != ixgbe_mac_82598EB)
2968                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
2969         }
2970         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2971         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2972         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2973         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2974         dev_info->max_vfs = dev->pci_dev->max_vfs;
2975         if (hw->mac.type == ixgbe_mac_82598EB)
2976                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2977         else
2978                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2979         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2980         dev_info->rx_offload_capa =
2981                 DEV_RX_OFFLOAD_VLAN_STRIP |
2982                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2983                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2984                 DEV_RX_OFFLOAD_TCP_CKSUM;
2985
2986         /*
2987          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2988          * mode.
2989          */
2990         if ((hw->mac.type == ixgbe_mac_82599EB ||
2991              hw->mac.type == ixgbe_mac_X540) &&
2992             !RTE_ETH_DEV_SRIOV(dev).active)
2993                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2994
2995         if (hw->mac.type == ixgbe_mac_X550 ||
2996             hw->mac.type == ixgbe_mac_X550EM_x ||
2997             hw->mac.type == ixgbe_mac_X550EM_a)
2998                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2999
3000         dev_info->tx_offload_capa =
3001                 DEV_TX_OFFLOAD_VLAN_INSERT |
3002                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3003                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3004                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3005                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3006                 DEV_TX_OFFLOAD_TCP_TSO;
3007
3008         if (hw->mac.type == ixgbe_mac_X550 ||
3009             hw->mac.type == ixgbe_mac_X550EM_x ||
3010             hw->mac.type == ixgbe_mac_X550EM_a)
3011                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3012
3013         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3014                 .rx_thresh = {
3015                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3016                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3017                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3018                 },
3019                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3020                 .rx_drop_en = 0,
3021         };
3022
3023         dev_info->default_txconf = (struct rte_eth_txconf) {
3024                 .tx_thresh = {
3025                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3026                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3027                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3028                 },
3029                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3030                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3031                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3032                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3033         };
3034
3035         dev_info->rx_desc_lim = rx_desc_lim;
3036         dev_info->tx_desc_lim = tx_desc_lim;
3037
3038         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3039         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3040         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3041
3042         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3043         if (hw->mac.type == ixgbe_mac_X540 ||
3044             hw->mac.type == ixgbe_mac_X540_vf ||
3045             hw->mac.type == ixgbe_mac_X550 ||
3046             hw->mac.type == ixgbe_mac_X550_vf) {
3047                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3048         }
3049 }
3050
3051 static const uint32_t *
3052 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3053 {
3054         static const uint32_t ptypes[] = {
3055                 /* For non-vec functions,
3056                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3057                  * for vec functions,
3058                  * refers to _recv_raw_pkts_vec().
3059                  */
3060                 RTE_PTYPE_L2_ETHER,
3061                 RTE_PTYPE_L3_IPV4,
3062                 RTE_PTYPE_L3_IPV4_EXT,
3063                 RTE_PTYPE_L3_IPV6,
3064                 RTE_PTYPE_L3_IPV6_EXT,
3065                 RTE_PTYPE_L4_SCTP,
3066                 RTE_PTYPE_L4_TCP,
3067                 RTE_PTYPE_L4_UDP,
3068                 RTE_PTYPE_TUNNEL_IP,
3069                 RTE_PTYPE_INNER_L3_IPV6,
3070                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3071                 RTE_PTYPE_INNER_L4_TCP,
3072                 RTE_PTYPE_INNER_L4_UDP,
3073                 RTE_PTYPE_UNKNOWN
3074         };
3075
3076         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3077             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3078             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3079             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3080                 return ptypes;
3081         return NULL;
3082 }
3083
3084 static void
3085 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3086                      struct rte_eth_dev_info *dev_info)
3087 {
3088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3089
3090         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3091         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3092         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3093         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3094         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3095         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3096         dev_info->max_vfs = dev->pci_dev->max_vfs;
3097         if (hw->mac.type == ixgbe_mac_82598EB)
3098                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3099         else
3100                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3101         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3102                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3103                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3104                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3105         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3106                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3107                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3108                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3109                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3110                                 DEV_TX_OFFLOAD_TCP_TSO;
3111
3112         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3113                 .rx_thresh = {
3114                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3115                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3116                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3117                 },
3118                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3119                 .rx_drop_en = 0,
3120         };
3121
3122         dev_info->default_txconf = (struct rte_eth_txconf) {
3123                 .tx_thresh = {
3124                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3125                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3126                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3127                 },
3128                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3129                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3130                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3131                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3132         };
3133
3134         dev_info->rx_desc_lim = rx_desc_lim;
3135         dev_info->tx_desc_lim = tx_desc_lim;
3136 }
3137
3138 /* return 0 means link status changed, -1 means not changed */
3139 static int
3140 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3141 {
3142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3143         struct rte_eth_link link, old;
3144         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3145         int link_up;
3146         int diag;
3147
3148         link.link_status = ETH_LINK_DOWN;
3149         link.link_speed = 0;
3150         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3151         memset(&old, 0, sizeof(old));
3152         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3153
3154         hw->mac.get_link_status = true;
3155
3156         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3157         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3158                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3159         else
3160                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3161
3162         if (diag != 0) {
3163                 link.link_speed = ETH_SPEED_NUM_100M;
3164                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3165                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3166                 if (link.link_status == old.link_status)
3167                         return -1;
3168                 return 0;
3169         }
3170
3171         if (link_up == 0) {
3172                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3173                 if (link.link_status == old.link_status)
3174                         return -1;
3175                 return 0;
3176         }
3177         link.link_status = ETH_LINK_UP;
3178         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3179
3180         switch (link_speed) {
3181         default:
3182         case IXGBE_LINK_SPEED_UNKNOWN:
3183                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3184                 link.link_speed = ETH_SPEED_NUM_100M;
3185                 break;
3186
3187         case IXGBE_LINK_SPEED_100_FULL:
3188                 link.link_speed = ETH_SPEED_NUM_100M;
3189                 break;
3190
3191         case IXGBE_LINK_SPEED_1GB_FULL:
3192                 link.link_speed = ETH_SPEED_NUM_1G;
3193                 break;
3194
3195         case IXGBE_LINK_SPEED_10GB_FULL:
3196                 link.link_speed = ETH_SPEED_NUM_10G;
3197                 break;
3198         }
3199         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3200
3201         if (link.link_status == old.link_status)
3202                 return -1;
3203
3204         return 0;
3205 }
3206
3207 static void
3208 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3209 {
3210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3211         uint32_t fctrl;
3212
3213         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3214         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3215         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3216 }
3217
3218 static void
3219 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3220 {
3221         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3222         uint32_t fctrl;
3223
3224         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3225         fctrl &= (~IXGBE_FCTRL_UPE);
3226         if (dev->data->all_multicast == 1)
3227                 fctrl |= IXGBE_FCTRL_MPE;
3228         else
3229                 fctrl &= (~IXGBE_FCTRL_MPE);
3230         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3231 }
3232
3233 static void
3234 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3235 {
3236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3237         uint32_t fctrl;
3238
3239         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3240         fctrl |= IXGBE_FCTRL_MPE;
3241         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3242 }
3243
3244 static void
3245 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3246 {
3247         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3248         uint32_t fctrl;
3249
3250         if (dev->data->promiscuous == 1)
3251                 return; /* must remain in all_multicast mode */
3252
3253         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3254         fctrl &= (~IXGBE_FCTRL_MPE);
3255         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3256 }
3257
3258 /**
3259  * It clears the interrupt causes and enables the interrupt.
3260  * It will be called once only during nic initialized.
3261  *
3262  * @param dev
3263  *  Pointer to struct rte_eth_dev.
3264  *
3265  * @return
3266  *  - On success, zero.
3267  *  - On failure, a negative value.
3268  */
3269 static int
3270 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3271 {
3272         struct ixgbe_interrupt *intr =
3273                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3274
3275         ixgbe_dev_link_status_print(dev);
3276         intr->mask |= IXGBE_EICR_LSC;
3277
3278         return 0;
3279 }
3280
3281 /**
3282  * It clears the interrupt causes and enables the interrupt.
3283  * It will be called once only during nic initialized.
3284  *
3285  * @param dev
3286  *  Pointer to struct rte_eth_dev.
3287  *
3288  * @return
3289  *  - On success, zero.
3290  *  - On failure, a negative value.
3291  */
3292 static int
3293 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3294 {
3295         struct ixgbe_interrupt *intr =
3296                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3297
3298         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3299
3300         return 0;
3301 }
3302
3303 /*
3304  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3305  *
3306  * @param dev
3307  *  Pointer to struct rte_eth_dev.
3308  *
3309  * @return
3310  *  - On success, zero.
3311  *  - On failure, a negative value.
3312  */
3313 static int
3314 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3315 {
3316         uint32_t eicr;
3317         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3318         struct ixgbe_interrupt *intr =
3319                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3320
3321         /* clear all cause mask */
3322         ixgbe_disable_intr(hw);
3323
3324         /* read-on-clear nic registers here */
3325         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3326         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3327
3328         intr->flags = 0;
3329
3330         /* set flag for async link update */
3331         if (eicr & IXGBE_EICR_LSC)
3332                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3333
3334         if (eicr & IXGBE_EICR_MAILBOX)
3335                 intr->flags |= IXGBE_FLAG_MAILBOX;
3336
3337         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3338             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3339             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3340                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3341
3342         return 0;
3343 }
3344
3345 /**
3346  * It gets and then prints the link status.
3347  *
3348  * @param dev
3349  *  Pointer to struct rte_eth_dev.
3350  *
3351  * @return
3352  *  - On success, zero.
3353  *  - On failure, a negative value.
3354  */
3355 static void
3356 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3357 {
3358         struct rte_eth_link link;
3359
3360         memset(&link, 0, sizeof(link));
3361         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3362         if (link.link_status) {
3363                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3364                                         (int)(dev->data->port_id),
3365                                         (unsigned)link.link_speed,
3366                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3367                                         "full-duplex" : "half-duplex");
3368         } else {
3369                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3370                                 (int)(dev->data->port_id));
3371         }
3372         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3373                                 dev->pci_dev->addr.domain,
3374                                 dev->pci_dev->addr.bus,
3375                                 dev->pci_dev->addr.devid,
3376                                 dev->pci_dev->addr.function);
3377 }
3378
3379 /*
3380  * It executes link_update after knowing an interrupt occurred.
3381  *
3382  * @param dev
3383  *  Pointer to struct rte_eth_dev.
3384  *
3385  * @return
3386  *  - On success, zero.
3387  *  - On failure, a negative value.
3388  */
3389 static int
3390 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3391 {
3392         struct ixgbe_interrupt *intr =
3393                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3394         int64_t timeout;
3395         struct rte_eth_link link;
3396         int intr_enable_delay = false;
3397         struct ixgbe_hw *hw =
3398                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399
3400         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3401
3402         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3403                 ixgbe_pf_mbx_process(dev);
3404                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3405         }
3406
3407         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3408                 ixgbe_handle_lasi(hw);
3409                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3410         }
3411
3412         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3413                 /* get the link status before link update, for predicting later */
3414                 memset(&link, 0, sizeof(link));
3415                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3416
3417                 ixgbe_dev_link_update(dev, 0);
3418
3419                 /* likely to up */
3420                 if (!link.link_status)
3421                         /* handle it 1 sec later, wait it being stable */
3422                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3423                 /* likely to down */
3424                 else
3425                         /* handle it 4 sec later, wait it being stable */
3426                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3427
3428                 ixgbe_dev_link_status_print(dev);
3429
3430                 intr_enable_delay = true;
3431         }
3432
3433         if (intr_enable_delay) {
3434                 if (rte_eal_alarm_set(timeout * 1000,
3435                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3436                         PMD_DRV_LOG(ERR, "Error setting alarm");
3437         } else {
3438                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3439                 ixgbe_enable_intr(dev);
3440                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3441         }
3442
3443
3444         return 0;
3445 }
3446
3447 /**
3448  * Interrupt handler which shall be registered for alarm callback for delayed
3449  * handling specific interrupt to wait for the stable nic state. As the
3450  * NIC interrupt state is not stable for ixgbe after link is just down,
3451  * it needs to wait 4 seconds to get the stable status.
3452  *
3453  * @param handle
3454  *  Pointer to interrupt handle.
3455  * @param param
3456  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3457  *
3458  * @return
3459  *  void
3460  */
3461 static void
3462 ixgbe_dev_interrupt_delayed_handler(void *param)
3463 {
3464         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3465         struct ixgbe_interrupt *intr =
3466                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3467         struct ixgbe_hw *hw =
3468                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469         uint32_t eicr;
3470
3471         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3472         if (eicr & IXGBE_EICR_MAILBOX)
3473                 ixgbe_pf_mbx_process(dev);
3474
3475         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3476                 ixgbe_handle_lasi(hw);
3477                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3478         }
3479
3480         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3481                 ixgbe_dev_link_update(dev, 0);
3482                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3483                 ixgbe_dev_link_status_print(dev);
3484                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3485         }
3486
3487         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3488         ixgbe_enable_intr(dev);
3489         rte_intr_enable(&(dev->pci_dev->intr_handle));
3490 }
3491
3492 /**
3493  * Interrupt handler triggered by NIC  for handling
3494  * specific interrupt.
3495  *
3496  * @param handle
3497  *  Pointer to interrupt handle.
3498  * @param param
3499  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3500  *
3501  * @return
3502  *  void
3503  */
3504 static void
3505 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3506                             void *param)
3507 {
3508         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3509
3510         ixgbe_dev_interrupt_get_status(dev);
3511         ixgbe_dev_interrupt_action(dev);
3512 }
3513
3514 static int
3515 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3516 {
3517         struct ixgbe_hw *hw;
3518
3519         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3520         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3521 }
3522
3523 static int
3524 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3525 {
3526         struct ixgbe_hw *hw;
3527
3528         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3529         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3530 }
3531
3532 static int
3533 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3534 {
3535         struct ixgbe_hw *hw;
3536         uint32_t mflcn_reg;
3537         uint32_t fccfg_reg;
3538         int rx_pause;
3539         int tx_pause;
3540
3541         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3542
3543         fc_conf->pause_time = hw->fc.pause_time;
3544         fc_conf->high_water = hw->fc.high_water[0];
3545         fc_conf->low_water = hw->fc.low_water[0];
3546         fc_conf->send_xon = hw->fc.send_xon;
3547         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3548
3549         /*
3550          * Return rx_pause status according to actual setting of
3551          * MFLCN register.
3552          */
3553         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3554         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3555                 rx_pause = 1;
3556         else
3557                 rx_pause = 0;
3558
3559         /*
3560          * Return tx_pause status according to actual setting of
3561          * FCCFG register.
3562          */
3563         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3564         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3565                 tx_pause = 1;
3566         else
3567                 tx_pause = 0;
3568
3569         if (rx_pause && tx_pause)
3570                 fc_conf->mode = RTE_FC_FULL;
3571         else if (rx_pause)
3572                 fc_conf->mode = RTE_FC_RX_PAUSE;
3573         else if (tx_pause)
3574                 fc_conf->mode = RTE_FC_TX_PAUSE;
3575         else
3576                 fc_conf->mode = RTE_FC_NONE;
3577
3578         return 0;
3579 }
3580
3581 static int
3582 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3583 {
3584         struct ixgbe_hw *hw;
3585         int err;
3586         uint32_t rx_buf_size;
3587         uint32_t max_high_water;
3588         uint32_t mflcn;
3589         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3590                 ixgbe_fc_none,
3591                 ixgbe_fc_rx_pause,
3592                 ixgbe_fc_tx_pause,
3593                 ixgbe_fc_full
3594         };
3595
3596         PMD_INIT_FUNC_TRACE();
3597
3598         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3599         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3600         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3601
3602         /*
3603          * At least reserve one Ethernet frame for watermark
3604          * high_water/low_water in kilo bytes for ixgbe
3605          */
3606         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3607         if ((fc_conf->high_water > max_high_water) ||
3608                 (fc_conf->high_water < fc_conf->low_water)) {
3609                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3610                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3611                 return -EINVAL;
3612         }
3613
3614         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3615         hw->fc.pause_time     = fc_conf->pause_time;
3616         hw->fc.high_water[0]  = fc_conf->high_water;
3617         hw->fc.low_water[0]   = fc_conf->low_water;
3618         hw->fc.send_xon       = fc_conf->send_xon;
3619         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3620
3621         err = ixgbe_fc_enable(hw);
3622
3623         /* Not negotiated is not an error case */
3624         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3625
3626                 /* check if we want to forward MAC frames - driver doesn't have native
3627                  * capability to do that, so we'll write the registers ourselves */
3628
3629                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3630
3631                 /* set or clear MFLCN.PMCF bit depending on configuration */
3632                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3633                         mflcn |= IXGBE_MFLCN_PMCF;
3634                 else
3635                         mflcn &= ~IXGBE_MFLCN_PMCF;
3636
3637                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3638                 IXGBE_WRITE_FLUSH(hw);
3639
3640                 return 0;
3641         }
3642
3643         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3644         return -EIO;
3645 }
3646
3647 /**
3648  *  ixgbe_pfc_enable_generic - Enable flow control
3649  *  @hw: pointer to hardware structure
3650  *  @tc_num: traffic class number
3651  *  Enable flow control according to the current settings.
3652  */
3653 static int
3654 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3655 {
3656         int ret_val = 0;
3657         uint32_t mflcn_reg, fccfg_reg;
3658         uint32_t reg;
3659         uint32_t fcrtl, fcrth;
3660         uint8_t i;
3661         uint8_t nb_rx_en;
3662
3663         /* Validate the water mark configuration */
3664         if (!hw->fc.pause_time) {
3665                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3666                 goto out;
3667         }
3668
3669         /* Low water mark of zero causes XOFF floods */
3670         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3671                  /* High/Low water can not be 0 */
3672                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3673                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3674                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3675                         goto out;
3676                 }
3677
3678                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3679                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3680                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3681                         goto out;
3682                 }
3683         }
3684         /* Negotiate the fc mode to use */
3685         ixgbe_fc_autoneg(hw);
3686
3687         /* Disable any previous flow control settings */
3688         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3689         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3690
3691         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3692         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3693
3694         switch (hw->fc.current_mode) {
3695         case ixgbe_fc_none:
3696                 /*
3697                  * If the count of enabled RX Priority Flow control >1,
3698                  * and the TX pause can not be disabled
3699                  */
3700                 nb_rx_en = 0;
3701                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3702                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3703                         if (reg & IXGBE_FCRTH_FCEN)
3704                                 nb_rx_en++;
3705                 }
3706                 if (nb_rx_en > 1)
3707                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3708                 break;
3709         case ixgbe_fc_rx_pause:
3710                 /*
3711                  * Rx Flow control is enabled and Tx Flow control is
3712                  * disabled by software override. Since there really
3713                  * isn't a way to advertise that we are capable of RX
3714                  * Pause ONLY, we will advertise that we support both
3715                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3716                  * disable the adapter's ability to send PAUSE frames.
3717                  */
3718                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3719                 /*
3720                  * If the count of enabled RX Priority Flow control >1,
3721                  * and the TX pause can not be disabled
3722                  */
3723                 nb_rx_en = 0;
3724                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3725                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3726                         if (reg & IXGBE_FCRTH_FCEN)
3727                                 nb_rx_en++;
3728                 }
3729                 if (nb_rx_en > 1)
3730                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3731                 break;
3732         case ixgbe_fc_tx_pause:
3733                 /*
3734                  * Tx Flow control is enabled, and Rx Flow control is
3735                  * disabled by software override.
3736                  */
3737                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3738                 break;
3739         case ixgbe_fc_full:
3740                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3741                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3742                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3743                 break;
3744         default:
3745                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3746                 ret_val = IXGBE_ERR_CONFIG;
3747                 goto out;
3748         }
3749
3750         /* Set 802.3x based flow control settings. */
3751         mflcn_reg |= IXGBE_MFLCN_DPF;
3752         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3753         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3754
3755         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3756         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3757                 hw->fc.high_water[tc_num]) {
3758                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3759                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3760                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3761         } else {
3762                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3763                 /*
3764                  * In order to prevent Tx hangs when the internal Tx
3765                  * switch is enabled we must set the high water mark
3766                  * to the maximum FCRTH value.  This allows the Tx
3767                  * switch to function even under heavy Rx workloads.
3768                  */
3769                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3770         }
3771         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3772
3773         /* Configure pause time (2 TCs per register) */
3774         reg = hw->fc.pause_time * 0x00010001;
3775         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3776                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3777
3778         /* Configure flow control refresh threshold value */
3779         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3780
3781 out:
3782         return ret_val;
3783 }
3784
3785 static int
3786 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3787 {
3788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3789         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3790
3791         if (hw->mac.type != ixgbe_mac_82598EB) {
3792                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3793         }
3794         return ret_val;
3795 }
3796
3797 static int
3798 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3799 {
3800         int err;
3801         uint32_t rx_buf_size;
3802         uint32_t max_high_water;
3803         uint8_t tc_num;
3804         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3805         struct ixgbe_hw *hw =
3806                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807         struct ixgbe_dcb_config *dcb_config =
3808                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3809
3810         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3811                 ixgbe_fc_none,
3812                 ixgbe_fc_rx_pause,
3813                 ixgbe_fc_tx_pause,
3814                 ixgbe_fc_full
3815         };
3816
3817         PMD_INIT_FUNC_TRACE();
3818
3819         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3820         tc_num = map[pfc_conf->priority];
3821         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3822         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3823         /*
3824          * At least reserve one Ethernet frame for watermark
3825          * high_water/low_water in kilo bytes for ixgbe
3826          */
3827         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3828         if ((pfc_conf->fc.high_water > max_high_water) ||
3829             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3830                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3831                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3832                 return -EINVAL;
3833         }
3834
3835         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3836         hw->fc.pause_time = pfc_conf->fc.pause_time;
3837         hw->fc.send_xon = pfc_conf->fc.send_xon;
3838         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3839         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3840
3841         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3842
3843         /* Not negotiated is not an error case */
3844         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3845                 return 0;
3846
3847         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3848         return -EIO;
3849 }
3850
3851 static int
3852 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3853                           struct rte_eth_rss_reta_entry64 *reta_conf,
3854                           uint16_t reta_size)
3855 {
3856         uint16_t i, sp_reta_size;
3857         uint8_t j, mask;
3858         uint32_t reta, r;
3859         uint16_t idx, shift;
3860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3861         uint32_t reta_reg;
3862
3863         PMD_INIT_FUNC_TRACE();
3864
3865         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3866                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3867                         "NIC.");
3868                 return -ENOTSUP;
3869         }
3870
3871         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3872         if (reta_size != sp_reta_size) {
3873                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3874                         "(%d) doesn't match the number hardware can supported "
3875                         "(%d)\n", reta_size, sp_reta_size);
3876                 return -EINVAL;
3877         }
3878
3879         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3880                 idx = i / RTE_RETA_GROUP_SIZE;
3881                 shift = i % RTE_RETA_GROUP_SIZE;
3882                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3883                                                 IXGBE_4_BIT_MASK);
3884                 if (!mask)
3885                         continue;
3886                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3887                 if (mask == IXGBE_4_BIT_MASK)
3888                         r = 0;
3889                 else
3890                         r = IXGBE_READ_REG(hw, reta_reg);
3891                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3892                         if (mask & (0x1 << j))
3893                                 reta |= reta_conf[idx].reta[shift + j] <<
3894                                                         (CHAR_BIT * j);
3895                         else
3896                                 reta |= r & (IXGBE_8_BIT_MASK <<
3897                                                 (CHAR_BIT * j));
3898                 }
3899                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3900         }
3901
3902         return 0;
3903 }
3904
3905 static int
3906 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3907                          struct rte_eth_rss_reta_entry64 *reta_conf,
3908                          uint16_t reta_size)
3909 {
3910         uint16_t i, sp_reta_size;
3911         uint8_t j, mask;
3912         uint32_t reta;
3913         uint16_t idx, shift;
3914         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3915         uint32_t reta_reg;
3916
3917         PMD_INIT_FUNC_TRACE();
3918         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3919         if (reta_size != sp_reta_size) {
3920                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3921                         "(%d) doesn't match the number hardware can supported "
3922                         "(%d)\n", reta_size, sp_reta_size);
3923                 return -EINVAL;
3924         }
3925
3926         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3927                 idx = i / RTE_RETA_GROUP_SIZE;
3928                 shift = i % RTE_RETA_GROUP_SIZE;
3929                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3930                                                 IXGBE_4_BIT_MASK);
3931                 if (!mask)
3932                         continue;
3933
3934                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3935                 reta = IXGBE_READ_REG(hw, reta_reg);
3936                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3937                         if (mask & (0x1 << j))
3938                                 reta_conf[idx].reta[shift + j] =
3939                                         ((reta >> (CHAR_BIT * j)) &
3940                                                 IXGBE_8_BIT_MASK);
3941                 }
3942         }
3943
3944         return 0;
3945 }
3946
3947 static void
3948 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3949                                 uint32_t index, uint32_t pool)
3950 {
3951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3952         uint32_t enable_addr = 1;
3953
3954         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3955 }
3956
3957 static void
3958 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3959 {
3960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3961
3962         ixgbe_clear_rar(hw, index);
3963 }
3964
3965 static void
3966 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3967 {
3968         ixgbe_remove_rar(dev, 0);
3969
3970         ixgbe_add_rar(dev, addr, 0, 0);
3971 }
3972
3973 static int
3974 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3975 {
3976         uint32_t hlreg0;
3977         uint32_t maxfrs;
3978         struct ixgbe_hw *hw;
3979         struct rte_eth_dev_info dev_info;
3980         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3981
3982         ixgbe_dev_info_get(dev, &dev_info);
3983
3984         /* check that mtu is within the allowed range */
3985         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3986                 return -EINVAL;
3987
3988         /* refuse mtu that requires the support of scattered packets when this
3989          * feature has not been enabled before.
3990          */
3991         if (!dev->data->scattered_rx &&
3992             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3993              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3994                 return -EINVAL;
3995
3996         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3997         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3998
3999         /* switch to jumbo mode if needed */
4000         if (frame_size > ETHER_MAX_LEN) {
4001                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4002                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4003         } else {
4004                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4005                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4006         }
4007         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4008
4009         /* update max frame size */
4010         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4011
4012         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4013         maxfrs &= 0x0000FFFF;
4014         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4015         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4016
4017         return 0;
4018 }
4019
4020 /*
4021  * Virtual Function operations
4022  */
4023 static void
4024 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4025 {
4026         PMD_INIT_FUNC_TRACE();
4027
4028         /* Clear interrupt mask to stop from interrupts being generated */
4029         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4030
4031         IXGBE_WRITE_FLUSH(hw);
4032 }
4033
4034 static void
4035 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4036 {
4037         PMD_INIT_FUNC_TRACE();
4038
4039         /* VF enable interrupt autoclean */
4040         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4041         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4042         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4043
4044         IXGBE_WRITE_FLUSH(hw);
4045 }
4046
4047 static int
4048 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4049 {
4050         struct rte_eth_conf *conf = &dev->data->dev_conf;
4051         struct ixgbe_adapter *adapter =
4052                         (struct ixgbe_adapter *)dev->data->dev_private;
4053
4054         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4055                      dev->data->port_id);
4056
4057         /*
4058          * VF has no ability to enable/disable HW CRC
4059          * Keep the persistent behavior the same as Host PF
4060          */
4061 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4062         if (!conf->rxmode.hw_strip_crc) {
4063                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4064                 conf->rxmode.hw_strip_crc = 1;
4065         }
4066 #else
4067         if (conf->rxmode.hw_strip_crc) {
4068                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4069                 conf->rxmode.hw_strip_crc = 0;
4070         }
4071 #endif
4072
4073         /*
4074          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4075          * allocation or vector Rx preconditions we will reset it.
4076          */
4077         adapter->rx_bulk_alloc_allowed = true;
4078         adapter->rx_vec_allowed = true;
4079
4080         return 0;
4081 }
4082
4083 static int
4084 ixgbevf_dev_start(struct rte_eth_dev *dev)
4085 {
4086         struct ixgbe_hw *hw =
4087                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4088         uint32_t intr_vector = 0;
4089         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4090
4091         int err, mask = 0;
4092
4093         PMD_INIT_FUNC_TRACE();
4094
4095         hw->mac.ops.reset_hw(hw);
4096         hw->mac.get_link_status = true;
4097
4098         /* negotiate mailbox API version to use with the PF. */
4099         ixgbevf_negotiate_api(hw);
4100
4101         ixgbevf_dev_tx_init(dev);
4102
4103         /* This can fail when allocating mbufs for descriptor rings */
4104         err = ixgbevf_dev_rx_init(dev);
4105         if (err) {
4106                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4107                 ixgbe_dev_clear_queues(dev);
4108                 return err;
4109         }
4110
4111         /* Set vfta */
4112         ixgbevf_set_vfta_all(dev, 1);
4113
4114         /* Set HW strip */
4115         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4116                 ETH_VLAN_EXTEND_MASK;
4117         ixgbevf_vlan_offload_set(dev, mask);
4118
4119         ixgbevf_dev_rxtx_start(dev);
4120
4121         /* check and configure queue intr-vector mapping */
4122         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4123                 intr_vector = dev->data->nb_rx_queues;
4124                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4125                         return -1;
4126         }
4127
4128         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4129                 intr_handle->intr_vec =
4130                         rte_zmalloc("intr_vec",
4131                                     dev->data->nb_rx_queues * sizeof(int), 0);
4132                 if (intr_handle->intr_vec == NULL) {
4133                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4134                                      " intr_vec\n", dev->data->nb_rx_queues);
4135                         return -ENOMEM;
4136                 }
4137         }
4138         ixgbevf_configure_msix(dev);
4139
4140         rte_intr_enable(intr_handle);
4141
4142         /* Re-enable interrupt for VF */
4143         ixgbevf_intr_enable(hw);
4144
4145         return 0;
4146 }
4147
4148 static void
4149 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4150 {
4151         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4152         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4153
4154         PMD_INIT_FUNC_TRACE();
4155
4156         hw->adapter_stopped = 1;
4157         ixgbe_stop_adapter(hw);
4158
4159         /*
4160           * Clear what we set, but we still keep shadow_vfta to
4161           * restore after device starts
4162           */
4163         ixgbevf_set_vfta_all(dev, 0);
4164
4165         /* Clear stored conf */
4166         dev->data->scattered_rx = 0;
4167
4168         ixgbe_dev_clear_queues(dev);
4169
4170         /* Clean datapath event and queue/vec mapping */
4171         rte_intr_efd_disable(intr_handle);
4172         if (intr_handle->intr_vec != NULL) {
4173                 rte_free(intr_handle->intr_vec);
4174                 intr_handle->intr_vec = NULL;
4175         }
4176 }
4177
4178 static void
4179 ixgbevf_dev_close(struct rte_eth_dev *dev)
4180 {
4181         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182
4183         PMD_INIT_FUNC_TRACE();
4184
4185         ixgbe_reset_hw(hw);
4186
4187         ixgbevf_dev_stop(dev);
4188
4189         ixgbe_dev_free_queues(dev);
4190
4191         /**
4192          * Remove the VF MAC address ro ensure
4193          * that the VF traffic goes to the PF
4194          * after stop, close and detach of the VF
4195          **/
4196         ixgbevf_remove_mac_addr(dev, 0);
4197 }
4198
4199 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4200 {
4201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202         struct ixgbe_vfta *shadow_vfta =
4203                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4204         int i = 0, j = 0, vfta = 0, mask = 1;
4205
4206         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4207                 vfta = shadow_vfta->vfta[i];
4208                 if (vfta) {
4209                         mask = 1;
4210                         for (j = 0; j < 32; j++) {
4211                                 if (vfta & mask)
4212                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4213                                 mask <<= 1;
4214                         }
4215                 }
4216         }
4217
4218 }
4219
4220 static int
4221 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4222 {
4223         struct ixgbe_hw *hw =
4224                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4225         struct ixgbe_vfta *shadow_vfta =
4226                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4227         uint32_t vid_idx = 0;
4228         uint32_t vid_bit = 0;
4229         int ret = 0;
4230
4231         PMD_INIT_FUNC_TRACE();
4232
4233         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4234         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4235         if (ret) {
4236                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4237                 return ret;
4238         }
4239         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4240         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4241
4242         /* Save what we set and retore it after device reset */
4243         if (on)
4244                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4245         else
4246                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4247
4248         return 0;
4249 }
4250
4251 static void
4252 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4253 {
4254         struct ixgbe_hw *hw =
4255                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4256         uint32_t ctrl;
4257
4258         PMD_INIT_FUNC_TRACE();
4259
4260         if (queue >= hw->mac.max_rx_queues)
4261                 return;
4262
4263         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4264         if (on)
4265                 ctrl |= IXGBE_RXDCTL_VME;
4266         else
4267                 ctrl &= ~IXGBE_RXDCTL_VME;
4268         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4269
4270         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4271 }
4272
4273 static void
4274 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4275 {
4276         struct ixgbe_hw *hw =
4277                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4278         uint16_t i;
4279         int on = 0;
4280
4281         /* VF function only support hw strip feature, others are not support */
4282         if (mask & ETH_VLAN_STRIP_MASK) {
4283                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4284
4285                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4286                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4287         }
4288 }
4289
4290 static int
4291 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4292 {
4293         uint32_t reg_val;
4294
4295         /* we only need to do this if VMDq is enabled */
4296         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4297         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4298                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4299                 return -1;
4300         }
4301
4302         return 0;
4303 }
4304
4305 static uint32_t
4306 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4307 {
4308         uint32_t vector = 0;
4309
4310         switch (hw->mac.mc_filter_type) {
4311         case 0:   /* use bits [47:36] of the address */
4312                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4313                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4314                 break;
4315         case 1:   /* use bits [46:35] of the address */
4316                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4317                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4318                 break;
4319         case 2:   /* use bits [45:34] of the address */
4320                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4321                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4322                 break;
4323         case 3:   /* use bits [43:32] of the address */
4324                 vector = ((uc_addr->addr_bytes[4]) |
4325                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4326                 break;
4327         default:  /* Invalid mc_filter_type */
4328                 break;
4329         }
4330
4331         /* vector can only be 12-bits or boundary will be exceeded */
4332         vector &= 0xFFF;
4333         return vector;
4334 }
4335
4336 static int
4337 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4338                         uint8_t on)
4339 {
4340         uint32_t vector;
4341         uint32_t uta_idx;
4342         uint32_t reg_val;
4343         uint32_t uta_shift;
4344         uint32_t rc;
4345         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4346         const uint32_t ixgbe_uta_bit_shift = 5;
4347         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4348         const uint32_t bit1 = 0x1;
4349
4350         struct ixgbe_hw *hw =
4351                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4352         struct ixgbe_uta_info *uta_info =
4353                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4354
4355         /* The UTA table only exists on 82599 hardware and newer */
4356         if (hw->mac.type < ixgbe_mac_82599EB)
4357                 return -ENOTSUP;
4358
4359         vector = ixgbe_uta_vector(hw, mac_addr);
4360         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4361         uta_shift = vector & ixgbe_uta_bit_mask;
4362
4363         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4364         if (rc == on)
4365                 return 0;
4366
4367         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4368         if (on) {
4369                 uta_info->uta_in_use++;
4370                 reg_val |= (bit1 << uta_shift);
4371                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4372         } else {
4373                 uta_info->uta_in_use--;
4374                 reg_val &= ~(bit1 << uta_shift);
4375                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4376         }
4377
4378         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4379
4380         if (uta_info->uta_in_use > 0)
4381                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4382                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4383         else
4384                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4385
4386         return 0;
4387 }
4388
4389 static int
4390 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4391 {
4392         int i;
4393         struct ixgbe_hw *hw =
4394                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4395         struct ixgbe_uta_info *uta_info =
4396                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4397
4398         /* The UTA table only exists on 82599 hardware and newer */
4399         if (hw->mac.type < ixgbe_mac_82599EB)
4400                 return -ENOTSUP;
4401
4402         if (on) {
4403                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4404                         uta_info->uta_shadow[i] = ~0;
4405                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4406                 }
4407         } else {
4408                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4409                         uta_info->uta_shadow[i] = 0;
4410                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4411                 }
4412         }
4413         return 0;
4414
4415 }
4416
4417 uint32_t
4418 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4419 {
4420         uint32_t new_val = orig_val;
4421
4422         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4423                 new_val |= IXGBE_VMOLR_AUPE;
4424         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4425                 new_val |= IXGBE_VMOLR_ROMPE;
4426         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4427                 new_val |= IXGBE_VMOLR_ROPE;
4428         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4429                 new_val |= IXGBE_VMOLR_BAM;
4430         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4431                 new_val |= IXGBE_VMOLR_MPE;
4432
4433         return new_val;
4434 }
4435
4436 static int
4437 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4438                                uint16_t rx_mask, uint8_t on)
4439 {
4440         int val = 0;
4441
4442         struct ixgbe_hw *hw =
4443                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4444         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4445
4446         if (hw->mac.type == ixgbe_mac_82598EB) {
4447                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4448                              " on 82599 hardware and newer");
4449                 return -ENOTSUP;
4450         }
4451         if (ixgbe_vmdq_mode_check(hw) < 0)
4452                 return -ENOTSUP;
4453
4454         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4455
4456         if (on)
4457                 vmolr |= val;
4458         else
4459                 vmolr &= ~val;
4460
4461         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4462
4463         return 0;
4464 }
4465
4466 static int
4467 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4468 {
4469         uint32_t reg, addr;
4470         uint32_t val;
4471         const uint8_t bit1 = 0x1;
4472
4473         struct ixgbe_hw *hw =
4474                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4475
4476         if (ixgbe_vmdq_mode_check(hw) < 0)
4477                 return -ENOTSUP;
4478
4479         if (pool >= ETH_64_POOLS)
4480                 return -EINVAL;
4481
4482         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4483         if (pool >= 32) {
4484                 addr = IXGBE_VFRE(1);
4485                 val = bit1 << (pool - 32);
4486         } else {
4487                 addr = IXGBE_VFRE(0);
4488                 val = bit1 << pool;
4489         }
4490
4491         reg = IXGBE_READ_REG(hw, addr);
4492
4493         if (on)
4494                 reg |= val;
4495         else
4496                 reg &= ~val;
4497
4498         IXGBE_WRITE_REG(hw, addr, reg);
4499
4500         return 0;
4501 }
4502
4503 static int
4504 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4505 {
4506         uint32_t reg, addr;
4507         uint32_t val;
4508         const uint8_t bit1 = 0x1;
4509
4510         struct ixgbe_hw *hw =
4511                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4512
4513         if (ixgbe_vmdq_mode_check(hw) < 0)
4514                 return -ENOTSUP;
4515
4516         if (pool >= ETH_64_POOLS)
4517                 return -EINVAL;
4518
4519         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4520         if (pool >= 32) {
4521                 addr = IXGBE_VFTE(1);
4522                 val = bit1 << (pool - 32);
4523         } else {
4524                 addr = IXGBE_VFTE(0);
4525                 val = bit1 << pool;
4526         }
4527
4528         reg = IXGBE_READ_REG(hw, addr);
4529
4530         if (on)
4531                 reg |= val;
4532         else
4533                 reg &= ~val;
4534
4535         IXGBE_WRITE_REG(hw, addr, reg);
4536
4537         return 0;
4538 }
4539
4540 static int
4541 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4542                         uint64_t pool_mask, uint8_t vlan_on)
4543 {
4544         int ret = 0;
4545         uint16_t pool_idx;
4546         struct ixgbe_hw *hw =
4547                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4548
4549         if (ixgbe_vmdq_mode_check(hw) < 0)
4550                 return -ENOTSUP;
4551         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4552                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4553                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx, vlan_on);
4554                         if (ret < 0)
4555                                 return ret;
4556                 }
4557         }
4558
4559         return ret;
4560 }
4561
4562 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4563 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4564 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4565 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4566 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4567         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4568         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4569
4570 static int
4571 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4572                         struct rte_eth_mirror_conf *mirror_conf,
4573                         uint8_t rule_id, uint8_t on)
4574 {
4575         uint32_t mr_ctl, vlvf;
4576         uint32_t mp_lsb = 0;
4577         uint32_t mv_msb = 0;
4578         uint32_t mv_lsb = 0;
4579         uint32_t mp_msb = 0;
4580         uint8_t i = 0;
4581         int reg_index = 0;
4582         uint64_t vlan_mask = 0;
4583
4584         const uint8_t pool_mask_offset = 32;
4585         const uint8_t vlan_mask_offset = 32;
4586         const uint8_t dst_pool_offset = 8;
4587         const uint8_t rule_mr_offset  = 4;
4588         const uint8_t mirror_rule_mask = 0x0F;
4589
4590         struct ixgbe_mirror_info *mr_info =
4591                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4592         struct ixgbe_hw *hw =
4593                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4594         uint8_t mirror_type = 0;
4595
4596         if (ixgbe_vmdq_mode_check(hw) < 0)
4597                 return -ENOTSUP;
4598
4599         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4600                 return -EINVAL;
4601
4602         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4603                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4604                         mirror_conf->rule_type);
4605                 return -EINVAL;
4606         }
4607
4608         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4609                 mirror_type |= IXGBE_MRCTL_VLME;
4610                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4611                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4612                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4613                                 /* search vlan id related pool vlan filter index */
4614                                 reg_index = ixgbe_find_vlvf_slot(hw,
4615                                                 mirror_conf->vlan.vlan_id[i]);
4616                                 if (reg_index < 0)
4617                                         return -EINVAL;
4618                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4619                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4620                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4621                                       mirror_conf->vlan.vlan_id[i]))
4622                                         vlan_mask |= (1ULL << reg_index);
4623                                 else
4624                                         return -EINVAL;
4625                         }
4626                 }
4627
4628                 if (on) {
4629                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4630                         mv_msb = vlan_mask >> vlan_mask_offset;
4631
4632                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4633                                                 mirror_conf->vlan.vlan_mask;
4634                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4635                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4636                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4637                                                 mirror_conf->vlan.vlan_id[i];
4638                         }
4639                 } else {
4640                         mv_lsb = 0;
4641                         mv_msb = 0;
4642                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4643                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4644                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4645                 }
4646         }
4647
4648         /*
4649          * if enable pool mirror, write related pool mask register,if disable
4650          * pool mirror, clear PFMRVM register
4651          */
4652         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4653                 mirror_type |= IXGBE_MRCTL_VPME;
4654                 if (on) {
4655                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4656                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4657                         mr_info->mr_conf[rule_id].pool_mask =
4658                                         mirror_conf->pool_mask;
4659
4660                 } else {
4661                         mp_lsb = 0;
4662                         mp_msb = 0;
4663                         mr_info->mr_conf[rule_id].pool_mask = 0;
4664                 }
4665         }
4666         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4667                 mirror_type |= IXGBE_MRCTL_UPME;
4668         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4669                 mirror_type |= IXGBE_MRCTL_DPME;
4670
4671         /* read  mirror control register and recalculate it */
4672         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4673
4674         if (on) {
4675                 mr_ctl |= mirror_type;
4676                 mr_ctl &= mirror_rule_mask;
4677                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4678         } else
4679                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4680
4681         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4682         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4683
4684         /* write mirrror control  register */
4685         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4686
4687         /* write pool mirrror control  register */
4688         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4689                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4690                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4691                                 mp_msb);
4692         }
4693         /* write VLAN mirrror control  register */
4694         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4695                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4696                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4697                                 mv_msb);
4698         }
4699
4700         return 0;
4701 }
4702
4703 static int
4704 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4705 {
4706         int mr_ctl = 0;
4707         uint32_t lsb_val = 0;
4708         uint32_t msb_val = 0;
4709         const uint8_t rule_mr_offset = 4;
4710
4711         struct ixgbe_hw *hw =
4712                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4713         struct ixgbe_mirror_info *mr_info =
4714                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4715
4716         if (ixgbe_vmdq_mode_check(hw) < 0)
4717                 return -ENOTSUP;
4718
4719         memset(&mr_info->mr_conf[rule_id], 0,
4720                 sizeof(struct rte_eth_mirror_conf));
4721
4722         /* clear PFVMCTL register */
4723         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4724
4725         /* clear pool mask register */
4726         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4727         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4728
4729         /* clear vlan mask register */
4730         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4731         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4732
4733         return 0;
4734 }
4735
4736 static int
4737 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4738 {
4739         uint32_t mask;
4740         struct ixgbe_hw *hw =
4741                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4742
4743         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4744         mask |= (1 << IXGBE_MISC_VEC_ID);
4745         RTE_SET_USED(queue_id);
4746         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4747
4748         rte_intr_enable(&dev->pci_dev->intr_handle);
4749
4750         return 0;
4751 }
4752
4753 static int
4754 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4755 {
4756         uint32_t mask;
4757         struct ixgbe_hw *hw =
4758                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4759
4760         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4761         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4762         RTE_SET_USED(queue_id);
4763         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4764
4765         return 0;
4766 }
4767
4768 static int
4769 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4770 {
4771         uint32_t mask;
4772         struct ixgbe_hw *hw =
4773                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4774         struct ixgbe_interrupt *intr =
4775                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4776
4777         if (queue_id < 16) {
4778                 ixgbe_disable_intr(hw);
4779                 intr->mask |= (1 << queue_id);
4780                 ixgbe_enable_intr(dev);
4781         } else if (queue_id < 32) {
4782                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4783                 mask &= (1 << queue_id);
4784                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4785         } else if (queue_id < 64) {
4786                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4787                 mask &= (1 << (queue_id - 32));
4788                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4789         }
4790         rte_intr_enable(&dev->pci_dev->intr_handle);
4791
4792         return 0;
4793 }
4794
4795 static int
4796 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4797 {
4798         uint32_t mask;
4799         struct ixgbe_hw *hw =
4800                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4801         struct ixgbe_interrupt *intr =
4802                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4803
4804         if (queue_id < 16) {
4805                 ixgbe_disable_intr(hw);
4806                 intr->mask &= ~(1 << queue_id);
4807                 ixgbe_enable_intr(dev);
4808         } else if (queue_id < 32) {
4809                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4810                 mask &= ~(1 << queue_id);
4811                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4812         } else if (queue_id < 64) {
4813                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4814                 mask &= ~(1 << (queue_id - 32));
4815                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4816         }
4817
4818         return 0;
4819 }
4820
4821 static void
4822 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4823                      uint8_t queue, uint8_t msix_vector)
4824 {
4825         uint32_t tmp, idx;
4826
4827         if (direction == -1) {
4828                 /* other causes */
4829                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4830                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4831                 tmp &= ~0xFF;
4832                 tmp |= msix_vector;
4833                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4834         } else {
4835                 /* rx or tx cause */
4836                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4837                 idx = ((16 * (queue & 1)) + (8 * direction));
4838                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4839                 tmp &= ~(0xFF << idx);
4840                 tmp |= (msix_vector << idx);
4841                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4842         }
4843 }
4844
4845 /**
4846  * set the IVAR registers, mapping interrupt causes to vectors
4847  * @param hw
4848  *  pointer to ixgbe_hw struct
4849  * @direction
4850  *  0 for Rx, 1 for Tx, -1 for other causes
4851  * @queue
4852  *  queue to map the corresponding interrupt to
4853  * @msix_vector
4854  *  the vector to map to the corresponding queue
4855  */
4856 static void
4857 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4858                    uint8_t queue, uint8_t msix_vector)
4859 {
4860         uint32_t tmp, idx;
4861
4862         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4863         if (hw->mac.type == ixgbe_mac_82598EB) {
4864                 if (direction == -1)
4865                         direction = 0;
4866                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4867                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4868                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4869                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4870                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4871         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4872                         (hw->mac.type == ixgbe_mac_X540)) {
4873                 if (direction == -1) {
4874                         /* other causes */
4875                         idx = ((queue & 1) * 8);
4876                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4877                         tmp &= ~(0xFF << idx);
4878                         tmp |= (msix_vector << idx);
4879                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4880                 } else {
4881                         /* rx or tx causes */
4882                         idx = ((16 * (queue & 1)) + (8 * direction));
4883                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4884                         tmp &= ~(0xFF << idx);
4885                         tmp |= (msix_vector << idx);
4886                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4887                 }
4888         }
4889 }
4890
4891 static void
4892 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4893 {
4894         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4895         struct ixgbe_hw *hw =
4896                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4897         uint32_t q_idx;
4898         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4899
4900         /* won't configure msix register if no mapping is done
4901          * between intr vector and event fd.
4902          */
4903         if (!rte_intr_dp_is_en(intr_handle))
4904                 return;
4905
4906         /* Configure all RX queues of VF */
4907         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4908                 /* Force all queue use vector 0,
4909                  * as IXGBE_VF_MAXMSIVECOTR = 1
4910                  */
4911                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4912                 intr_handle->intr_vec[q_idx] = vector_idx;
4913         }
4914
4915         /* Configure VF other cause ivar */
4916         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4917 }
4918
4919 /**
4920  * Sets up the hardware to properly generate MSI-X interrupts
4921  * @hw
4922  *  board private structure
4923  */
4924 static void
4925 ixgbe_configure_msix(struct rte_eth_dev *dev)
4926 {
4927         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4928         struct ixgbe_hw *hw =
4929                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4930         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4931         uint32_t vec = IXGBE_MISC_VEC_ID;
4932         uint32_t mask;
4933         uint32_t gpie;
4934
4935         /* won't configure msix register if no mapping is done
4936          * between intr vector and event fd
4937          */
4938         if (!rte_intr_dp_is_en(intr_handle))
4939                 return;
4940
4941         if (rte_intr_allow_others(intr_handle))
4942                 vec = base = IXGBE_RX_VEC_START;
4943
4944         /* setup GPIE for MSI-x mode */
4945         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4946         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4947                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4948         /* auto clearing and auto setting corresponding bits in EIMS
4949          * when MSI-X interrupt is triggered
4950          */
4951         if (hw->mac.type == ixgbe_mac_82598EB) {
4952                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4953         } else {
4954                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4955                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4956         }
4957         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4958
4959         /* Populate the IVAR table and set the ITR values to the
4960          * corresponding register.
4961          */
4962         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4963              queue_id++) {
4964                 /* by default, 1:1 mapping */
4965                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4966                 intr_handle->intr_vec[queue_id] = vec;
4967                 if (vec < base + intr_handle->nb_efd - 1)
4968                         vec++;
4969         }
4970
4971         switch (hw->mac.type) {
4972         case ixgbe_mac_82598EB:
4973                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4974                                    IXGBE_MISC_VEC_ID);
4975                 break;
4976         case ixgbe_mac_82599EB:
4977         case ixgbe_mac_X540:
4978                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4979                 break;
4980         default:
4981                 break;
4982         }
4983         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4984                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4985
4986         /* set up to autoclear timer, and the vectors */
4987         mask = IXGBE_EIMS_ENABLE_MASK;
4988         mask &= ~(IXGBE_EIMS_OTHER |
4989                   IXGBE_EIMS_MAILBOX |
4990                   IXGBE_EIMS_LSC);
4991
4992         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4993 }
4994
4995 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4996         uint16_t queue_idx, uint16_t tx_rate)
4997 {
4998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4999         uint32_t rf_dec, rf_int;
5000         uint32_t bcnrc_val;
5001         uint16_t link_speed = dev->data->dev_link.link_speed;
5002
5003         if (queue_idx >= hw->mac.max_tx_queues)
5004                 return -EINVAL;
5005
5006         if (tx_rate != 0) {
5007                 /* Calculate the rate factor values to set */
5008                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5009                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5010                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5011
5012                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5013                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5014                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5015                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5016         } else {
5017                 bcnrc_val = 0;
5018         }
5019
5020         /*
5021          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5022          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5023          * set as 0x4.
5024          */
5025         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5026                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5027                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5028                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5029                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5030         else
5031                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5032                         IXGBE_MMW_SIZE_DEFAULT);
5033
5034         /* Set RTTBCNRC of queue X */
5035         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5036         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5037         IXGBE_WRITE_FLUSH(hw);
5038
5039         return 0;
5040 }
5041
5042 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5043         uint16_t tx_rate, uint64_t q_msk)
5044 {
5045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5046         struct ixgbe_vf_info *vfinfo =
5047                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5048         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5049         uint32_t queue_stride =
5050                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5051         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5052         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5053         uint16_t total_rate = 0;
5054
5055         if (queue_end >= hw->mac.max_tx_queues)
5056                 return -EINVAL;
5057
5058         if (vfinfo != NULL) {
5059                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5060                         if (vf_idx == vf)
5061                                 continue;
5062                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5063                                 idx++)
5064                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5065                 }
5066         } else
5067                 return -EINVAL;
5068
5069         /* Store tx_rate for this vf. */
5070         for (idx = 0; idx < nb_q_per_pool; idx++) {
5071                 if (((uint64_t)0x1 << idx) & q_msk) {
5072                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5073                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5074                         total_rate += tx_rate;
5075                 }
5076         }
5077
5078         if (total_rate > dev->data->dev_link.link_speed) {
5079                 /*
5080                  * Reset stored TX rate of the VF if it causes exceed
5081                  * link speed.
5082                  */
5083                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5084                 return -EINVAL;
5085         }
5086
5087         /* Set RTTBCNRC of each queue/pool for vf X  */
5088         for (; queue_idx <= queue_end; queue_idx++) {
5089                 if (0x1 & q_msk)
5090                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5091                 q_msk = q_msk >> 1;
5092         }
5093
5094         return 0;
5095 }
5096
5097 static void
5098 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5099                      __attribute__((unused)) uint32_t index,
5100                      __attribute__((unused)) uint32_t pool)
5101 {
5102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5103         int diag;
5104
5105         /*
5106          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5107          * operation. Trap this case to avoid exhausting the [very limited]
5108          * set of PF resources used to store VF MAC addresses.
5109          */
5110         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5111                 return;
5112         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5113         if (diag == 0)
5114                 return;
5115         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5116 }
5117
5118 static void
5119 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5120 {
5121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5122         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5123         struct ether_addr *mac_addr;
5124         uint32_t i;
5125         int diag;
5126
5127         /*
5128          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5129          * not support the deletion of a given MAC address.
5130          * Instead, it imposes to delete all MAC addresses, then to add again
5131          * all MAC addresses with the exception of the one to be deleted.
5132          */
5133         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5134
5135         /*
5136          * Add again all MAC addresses, with the exception of the deleted one
5137          * and of the permanent MAC address.
5138          */
5139         for (i = 0, mac_addr = dev->data->mac_addrs;
5140              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5141                 /* Skip the deleted MAC address */
5142                 if (i == index)
5143                         continue;
5144                 /* Skip NULL MAC addresses */
5145                 if (is_zero_ether_addr(mac_addr))
5146                         continue;
5147                 /* Skip the permanent MAC address */
5148                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5149                         continue;
5150                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5151                 if (diag != 0)
5152                         PMD_DRV_LOG(ERR,
5153                                     "Adding again MAC address "
5154                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5155                                     "diag=%d",
5156                                     mac_addr->addr_bytes[0],
5157                                     mac_addr->addr_bytes[1],
5158                                     mac_addr->addr_bytes[2],
5159                                     mac_addr->addr_bytes[3],
5160                                     mac_addr->addr_bytes[4],
5161                                     mac_addr->addr_bytes[5],
5162                                     diag);
5163         }
5164 }
5165
5166 static void
5167 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5168 {
5169         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5170
5171         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5172 }
5173
5174 #define MAC_TYPE_FILTER_SUP(type)    do {\
5175         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5176                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5177                 (type) != ixgbe_mac_X550EM_a)\
5178                 return -ENOTSUP;\
5179 } while (0)
5180
5181 static int
5182 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5183                         struct rte_eth_syn_filter *filter,
5184                         bool add)
5185 {
5186         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5187         uint32_t synqf;
5188
5189         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5190                 return -EINVAL;
5191
5192         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5193
5194         if (add) {
5195                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5196                         return -EINVAL;
5197                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5198                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5199
5200                 if (filter->hig_pri)
5201                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5202                 else
5203                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5204         } else {
5205                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5206                         return -ENOENT;
5207                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5208         }
5209         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5210         IXGBE_WRITE_FLUSH(hw);
5211         return 0;
5212 }
5213
5214 static int
5215 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5216                         struct rte_eth_syn_filter *filter)
5217 {
5218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5219         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5220
5221         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5222                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5223                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5224                 return 0;
5225         }
5226         return -ENOENT;
5227 }
5228
5229 static int
5230 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5231                         enum rte_filter_op filter_op,
5232                         void *arg)
5233 {
5234         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5235         int ret;
5236
5237         MAC_TYPE_FILTER_SUP(hw->mac.type);
5238
5239         if (filter_op == RTE_ETH_FILTER_NOP)
5240                 return 0;
5241
5242         if (arg == NULL) {
5243                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5244                             filter_op);
5245                 return -EINVAL;
5246         }
5247
5248         switch (filter_op) {
5249         case RTE_ETH_FILTER_ADD:
5250                 ret = ixgbe_syn_filter_set(dev,
5251                                 (struct rte_eth_syn_filter *)arg,
5252                                 TRUE);
5253                 break;
5254         case RTE_ETH_FILTER_DELETE:
5255                 ret = ixgbe_syn_filter_set(dev,
5256                                 (struct rte_eth_syn_filter *)arg,
5257                                 FALSE);
5258                 break;
5259         case RTE_ETH_FILTER_GET:
5260                 ret = ixgbe_syn_filter_get(dev,
5261                                 (struct rte_eth_syn_filter *)arg);
5262                 break;
5263         default:
5264                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5265                 ret = -EINVAL;
5266                 break;
5267         }
5268
5269         return ret;
5270 }
5271
5272
5273 static inline enum ixgbe_5tuple_protocol
5274 convert_protocol_type(uint8_t protocol_value)
5275 {
5276         if (protocol_value == IPPROTO_TCP)
5277                 return IXGBE_FILTER_PROTOCOL_TCP;
5278         else if (protocol_value == IPPROTO_UDP)
5279                 return IXGBE_FILTER_PROTOCOL_UDP;
5280         else if (protocol_value == IPPROTO_SCTP)
5281                 return IXGBE_FILTER_PROTOCOL_SCTP;
5282         else
5283                 return IXGBE_FILTER_PROTOCOL_NONE;
5284 }
5285
5286 /*
5287  * add a 5tuple filter
5288  *
5289  * @param
5290  * dev: Pointer to struct rte_eth_dev.
5291  * index: the index the filter allocates.
5292  * filter: ponter to the filter that will be added.
5293  * rx_queue: the queue id the filter assigned to.
5294  *
5295  * @return
5296  *    - On success, zero.
5297  *    - On failure, a negative value.
5298  */
5299 static int
5300 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5301                         struct ixgbe_5tuple_filter *filter)
5302 {
5303         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5304         struct ixgbe_filter_info *filter_info =
5305                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5306         int i, idx, shift;
5307         uint32_t ftqf, sdpqf;
5308         uint32_t l34timir = 0;
5309         uint8_t mask = 0xff;
5310
5311         /*
5312          * look for an unused 5tuple filter index,
5313          * and insert the filter to list.
5314          */
5315         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5316                 idx = i / (sizeof(uint32_t) * NBBY);
5317                 shift = i % (sizeof(uint32_t) * NBBY);
5318                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5319                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5320                         filter->index = i;
5321                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5322                                           filter,
5323                                           entries);
5324                         break;
5325                 }
5326         }
5327         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5328                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5329                 return -ENOSYS;
5330         }
5331
5332         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5333                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5334         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5335
5336         ftqf = (uint32_t)(filter->filter_info.proto &
5337                 IXGBE_FTQF_PROTOCOL_MASK);
5338         ftqf |= (uint32_t)((filter->filter_info.priority &
5339                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5340         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5341                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5342         if (filter->filter_info.dst_ip_mask == 0)
5343                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5344         if (filter->filter_info.src_port_mask == 0)
5345                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5346         if (filter->filter_info.dst_port_mask == 0)
5347                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5348         if (filter->filter_info.proto_mask == 0)
5349                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5350         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5351         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5352         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5353
5354         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5355         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5356         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5357         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5358
5359         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5360         l34timir |= (uint32_t)(filter->queue <<
5361                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5362         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5363         return 0;
5364 }
5365
5366 /*
5367  * remove a 5tuple filter
5368  *
5369  * @param
5370  * dev: Pointer to struct rte_eth_dev.
5371  * filter: the pointer of the filter will be removed.
5372  */
5373 static void
5374 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5375                         struct ixgbe_5tuple_filter *filter)
5376 {
5377         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5378         struct ixgbe_filter_info *filter_info =
5379                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5380         uint16_t index = filter->index;
5381
5382         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5383                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5384         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5385         rte_free(filter);
5386
5387         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5388         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5389         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5390         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5391         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5392 }
5393
5394 static int
5395 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5396 {
5397         struct ixgbe_hw *hw;
5398         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5399
5400         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5401
5402         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5403                 return -EINVAL;
5404
5405         /* refuse mtu that requires the support of scattered packets when this
5406          * feature has not been enabled before.
5407          */
5408         if (!dev->data->scattered_rx &&
5409             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5410              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5411                 return -EINVAL;
5412
5413         /*
5414          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5415          * request of the version 2.0 of the mailbox API.
5416          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5417          * of the mailbox API.
5418          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5419          * prior to 3.11.33 which contains the following change:
5420          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5421          */
5422         ixgbevf_rlpml_set_vf(hw, max_frame);
5423
5424         /* update max frame size */
5425         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5426         return 0;
5427 }
5428
5429 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5430         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5431                 return -ENOTSUP;\
5432 } while (0)
5433
5434 static inline struct ixgbe_5tuple_filter *
5435 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5436                         struct ixgbe_5tuple_filter_info *key)
5437 {
5438         struct ixgbe_5tuple_filter *it;
5439
5440         TAILQ_FOREACH(it, filter_list, entries) {
5441                 if (memcmp(key, &it->filter_info,
5442                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5443                         return it;
5444                 }
5445         }
5446         return NULL;
5447 }
5448
5449 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5450 static inline int
5451 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5452                         struct ixgbe_5tuple_filter_info *filter_info)
5453 {
5454         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5455                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5456                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5457                 return -EINVAL;
5458
5459         switch (filter->dst_ip_mask) {
5460         case UINT32_MAX:
5461                 filter_info->dst_ip_mask = 0;
5462                 filter_info->dst_ip = filter->dst_ip;
5463                 break;
5464         case 0:
5465                 filter_info->dst_ip_mask = 1;
5466                 break;
5467         default:
5468                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5469                 return -EINVAL;
5470         }
5471
5472         switch (filter->src_ip_mask) {
5473         case UINT32_MAX:
5474                 filter_info->src_ip_mask = 0;
5475                 filter_info->src_ip = filter->src_ip;
5476                 break;
5477         case 0:
5478                 filter_info->src_ip_mask = 1;
5479                 break;
5480         default:
5481                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5482                 return -EINVAL;
5483         }
5484
5485         switch (filter->dst_port_mask) {
5486         case UINT16_MAX:
5487                 filter_info->dst_port_mask = 0;
5488                 filter_info->dst_port = filter->dst_port;
5489                 break;
5490         case 0:
5491                 filter_info->dst_port_mask = 1;
5492                 break;
5493         default:
5494                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5495                 return -EINVAL;
5496         }
5497
5498         switch (filter->src_port_mask) {
5499         case UINT16_MAX:
5500                 filter_info->src_port_mask = 0;
5501                 filter_info->src_port = filter->src_port;
5502                 break;
5503         case 0:
5504                 filter_info->src_port_mask = 1;
5505                 break;
5506         default:
5507                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5508                 return -EINVAL;
5509         }
5510
5511         switch (filter->proto_mask) {
5512         case UINT8_MAX:
5513                 filter_info->proto_mask = 0;
5514                 filter_info->proto =
5515                         convert_protocol_type(filter->proto);
5516                 break;
5517         case 0:
5518                 filter_info->proto_mask = 1;
5519                 break;
5520         default:
5521                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5522                 return -EINVAL;
5523         }
5524
5525         filter_info->priority = (uint8_t)filter->priority;
5526         return 0;
5527 }
5528
5529 /*
5530  * add or delete a ntuple filter
5531  *
5532  * @param
5533  * dev: Pointer to struct rte_eth_dev.
5534  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5535  * add: if true, add filter, if false, remove filter
5536  *
5537  * @return
5538  *    - On success, zero.
5539  *    - On failure, a negative value.
5540  */
5541 static int
5542 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5543                         struct rte_eth_ntuple_filter *ntuple_filter,
5544                         bool add)
5545 {
5546         struct ixgbe_filter_info *filter_info =
5547                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5548         struct ixgbe_5tuple_filter_info filter_5tuple;
5549         struct ixgbe_5tuple_filter *filter;
5550         int ret;
5551
5552         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5553                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5554                 return -EINVAL;
5555         }
5556
5557         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5558         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5559         if (ret < 0)
5560                 return ret;
5561
5562         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5563                                          &filter_5tuple);
5564         if (filter != NULL && add) {
5565                 PMD_DRV_LOG(ERR, "filter exists.");
5566                 return -EEXIST;
5567         }
5568         if (filter == NULL && !add) {
5569                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5570                 return -ENOENT;
5571         }
5572
5573         if (add) {
5574                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5575                                 sizeof(struct ixgbe_5tuple_filter), 0);
5576                 if (filter == NULL)
5577                         return -ENOMEM;
5578                 (void)rte_memcpy(&filter->filter_info,
5579                                  &filter_5tuple,
5580                                  sizeof(struct ixgbe_5tuple_filter_info));
5581                 filter->queue = ntuple_filter->queue;
5582                 ret = ixgbe_add_5tuple_filter(dev, filter);
5583                 if (ret < 0) {
5584                         rte_free(filter);
5585                         return ret;
5586                 }
5587         } else
5588                 ixgbe_remove_5tuple_filter(dev, filter);
5589
5590         return 0;
5591 }
5592
5593 /*
5594  * get a ntuple filter
5595  *
5596  * @param
5597  * dev: Pointer to struct rte_eth_dev.
5598  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5599  *
5600  * @return
5601  *    - On success, zero.
5602  *    - On failure, a negative value.
5603  */
5604 static int
5605 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5606                         struct rte_eth_ntuple_filter *ntuple_filter)
5607 {
5608         struct ixgbe_filter_info *filter_info =
5609                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5610         struct ixgbe_5tuple_filter_info filter_5tuple;
5611         struct ixgbe_5tuple_filter *filter;
5612         int ret;
5613
5614         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5615                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5616                 return -EINVAL;
5617         }
5618
5619         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5620         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5621         if (ret < 0)
5622                 return ret;
5623
5624         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5625                                          &filter_5tuple);
5626         if (filter == NULL) {
5627                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5628                 return -ENOENT;
5629         }
5630         ntuple_filter->queue = filter->queue;
5631         return 0;
5632 }
5633
5634 /*
5635  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5636  * @dev: pointer to rte_eth_dev structure
5637  * @filter_op:operation will be taken.
5638  * @arg: a pointer to specific structure corresponding to the filter_op
5639  *
5640  * @return
5641  *    - On success, zero.
5642  *    - On failure, a negative value.
5643  */
5644 static int
5645 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5646                                 enum rte_filter_op filter_op,
5647                                 void *arg)
5648 {
5649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5650         int ret;
5651
5652         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5653
5654         if (filter_op == RTE_ETH_FILTER_NOP)
5655                 return 0;
5656
5657         if (arg == NULL) {
5658                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5659                             filter_op);
5660                 return -EINVAL;
5661         }
5662
5663         switch (filter_op) {
5664         case RTE_ETH_FILTER_ADD:
5665                 ret = ixgbe_add_del_ntuple_filter(dev,
5666                         (struct rte_eth_ntuple_filter *)arg,
5667                         TRUE);
5668                 break;
5669         case RTE_ETH_FILTER_DELETE:
5670                 ret = ixgbe_add_del_ntuple_filter(dev,
5671                         (struct rte_eth_ntuple_filter *)arg,
5672                         FALSE);
5673                 break;
5674         case RTE_ETH_FILTER_GET:
5675                 ret = ixgbe_get_ntuple_filter(dev,
5676                         (struct rte_eth_ntuple_filter *)arg);
5677                 break;
5678         default:
5679                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5680                 ret = -EINVAL;
5681                 break;
5682         }
5683         return ret;
5684 }
5685
5686 static inline int
5687 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5688                         uint16_t ethertype)
5689 {
5690         int i;
5691
5692         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5693                 if (filter_info->ethertype_filters[i] == ethertype &&
5694                     (filter_info->ethertype_mask & (1 << i)))
5695                         return i;
5696         }
5697         return -1;
5698 }
5699
5700 static inline int
5701 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5702                         uint16_t ethertype)
5703 {
5704         int i;
5705
5706         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5707                 if (!(filter_info->ethertype_mask & (1 << i))) {
5708                         filter_info->ethertype_mask |= 1 << i;
5709                         filter_info->ethertype_filters[i] = ethertype;
5710                         return i;
5711                 }
5712         }
5713         return -1;
5714 }
5715
5716 static inline int
5717 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5718                         uint8_t idx)
5719 {
5720         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5721                 return -1;
5722         filter_info->ethertype_mask &= ~(1 << idx);
5723         filter_info->ethertype_filters[idx] = 0;
5724         return idx;
5725 }
5726
5727 static int
5728 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5729                         struct rte_eth_ethertype_filter *filter,
5730                         bool add)
5731 {
5732         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5733         struct ixgbe_filter_info *filter_info =
5734                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5735         uint32_t etqf = 0;
5736         uint32_t etqs = 0;
5737         int ret;
5738
5739         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5740                 return -EINVAL;
5741
5742         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5743                 filter->ether_type == ETHER_TYPE_IPv6) {
5744                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5745                         " ethertype filter.", filter->ether_type);
5746                 return -EINVAL;
5747         }
5748
5749         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5750                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5751                 return -EINVAL;
5752         }
5753         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5754                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5755                 return -EINVAL;
5756         }
5757
5758         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5759         if (ret >= 0 && add) {
5760                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5761                             filter->ether_type);
5762                 return -EEXIST;
5763         }
5764         if (ret < 0 && !add) {
5765                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5766                             filter->ether_type);
5767                 return -ENOENT;
5768         }
5769
5770         if (add) {
5771                 ret = ixgbe_ethertype_filter_insert(filter_info,
5772                         filter->ether_type);
5773                 if (ret < 0) {
5774                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5775                         return -ENOSYS;
5776                 }
5777                 etqf = IXGBE_ETQF_FILTER_EN;
5778                 etqf |= (uint32_t)filter->ether_type;
5779                 etqs |= (uint32_t)((filter->queue <<
5780                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5781                                     IXGBE_ETQS_RX_QUEUE);
5782                 etqs |= IXGBE_ETQS_QUEUE_EN;
5783         } else {
5784                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5785                 if (ret < 0)
5786                         return -ENOSYS;
5787         }
5788         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5789         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5790         IXGBE_WRITE_FLUSH(hw);
5791
5792         return 0;
5793 }
5794
5795 static int
5796 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5797                         struct rte_eth_ethertype_filter *filter)
5798 {
5799         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5800         struct ixgbe_filter_info *filter_info =
5801                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5802         uint32_t etqf, etqs;
5803         int ret;
5804
5805         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5806         if (ret < 0) {
5807                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5808                             filter->ether_type);
5809                 return -ENOENT;
5810         }
5811
5812         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5813         if (etqf & IXGBE_ETQF_FILTER_EN) {
5814                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5815                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5816                 filter->flags = 0;
5817                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5818                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5819                 return 0;
5820         }
5821         return -ENOENT;
5822 }
5823
5824 /*
5825  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5826  * @dev: pointer to rte_eth_dev structure
5827  * @filter_op:operation will be taken.
5828  * @arg: a pointer to specific structure corresponding to the filter_op
5829  */
5830 static int
5831 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5832                                 enum rte_filter_op filter_op,
5833                                 void *arg)
5834 {
5835         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5836         int ret;
5837
5838         MAC_TYPE_FILTER_SUP(hw->mac.type);
5839
5840         if (filter_op == RTE_ETH_FILTER_NOP)
5841                 return 0;
5842
5843         if (arg == NULL) {
5844                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5845                             filter_op);
5846                 return -EINVAL;
5847         }
5848
5849         switch (filter_op) {
5850         case RTE_ETH_FILTER_ADD:
5851                 ret = ixgbe_add_del_ethertype_filter(dev,
5852                         (struct rte_eth_ethertype_filter *)arg,
5853                         TRUE);
5854                 break;
5855         case RTE_ETH_FILTER_DELETE:
5856                 ret = ixgbe_add_del_ethertype_filter(dev,
5857                         (struct rte_eth_ethertype_filter *)arg,
5858                         FALSE);
5859                 break;
5860         case RTE_ETH_FILTER_GET:
5861                 ret = ixgbe_get_ethertype_filter(dev,
5862                         (struct rte_eth_ethertype_filter *)arg);
5863                 break;
5864         default:
5865                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5866                 ret = -EINVAL;
5867                 break;
5868         }
5869         return ret;
5870 }
5871
5872 static int
5873 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5874                      enum rte_filter_type filter_type,
5875                      enum rte_filter_op filter_op,
5876                      void *arg)
5877 {
5878         int ret = -EINVAL;
5879
5880         switch (filter_type) {
5881         case RTE_ETH_FILTER_NTUPLE:
5882                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5883                 break;
5884         case RTE_ETH_FILTER_ETHERTYPE:
5885                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5886                 break;
5887         case RTE_ETH_FILTER_SYN:
5888                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5889                 break;
5890         case RTE_ETH_FILTER_FDIR:
5891                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5892                 break;
5893         case RTE_ETH_FILTER_L2_TUNNEL:
5894                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5895                 break;
5896         default:
5897                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5898                                                         filter_type);
5899                 break;
5900         }
5901
5902         return ret;
5903 }
5904
5905 static u8 *
5906 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5907                         u8 **mc_addr_ptr, u32 *vmdq)
5908 {
5909         u8 *mc_addr;
5910
5911         *vmdq = 0;
5912         mc_addr = *mc_addr_ptr;
5913         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5914         return mc_addr;
5915 }
5916
5917 static int
5918 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5919                           struct ether_addr *mc_addr_set,
5920                           uint32_t nb_mc_addr)
5921 {
5922         struct ixgbe_hw *hw;
5923         u8 *mc_addr_list;
5924
5925         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5926         mc_addr_list = (u8 *)mc_addr_set;
5927         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5928                                          ixgbe_dev_addr_list_itr, TRUE);
5929 }
5930
5931 static uint64_t
5932 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5933 {
5934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5935         uint64_t systime_cycles;
5936
5937         switch (hw->mac.type) {
5938         case ixgbe_mac_X550:
5939         case ixgbe_mac_X550EM_x:
5940         case ixgbe_mac_X550EM_a:
5941                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5942                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5943                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5944                                 * NSEC_PER_SEC;
5945                 break;
5946         default:
5947                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5948                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5949                                 << 32;
5950         }
5951
5952         return systime_cycles;
5953 }
5954
5955 static uint64_t
5956 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5957 {
5958         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5959         uint64_t rx_tstamp_cycles;
5960
5961         switch (hw->mac.type) {
5962         case ixgbe_mac_X550:
5963         case ixgbe_mac_X550EM_x:
5964         case ixgbe_mac_X550EM_a:
5965                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5966                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5967                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5968                                 * NSEC_PER_SEC;
5969                 break;
5970         default:
5971                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5972                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5973                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5974                                 << 32;
5975         }
5976
5977         return rx_tstamp_cycles;
5978 }
5979
5980 static uint64_t
5981 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5982 {
5983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5984         uint64_t tx_tstamp_cycles;
5985
5986         switch (hw->mac.type) {
5987         case ixgbe_mac_X550:
5988         case ixgbe_mac_X550EM_x:
5989         case ixgbe_mac_X550EM_a:
5990                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5991                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5992                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5993                                 * NSEC_PER_SEC;
5994                 break;
5995         default:
5996                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5997                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5998                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5999                                 << 32;
6000         }
6001
6002         return tx_tstamp_cycles;
6003 }
6004
6005 static void
6006 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6007 {
6008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6009         struct ixgbe_adapter *adapter =
6010                 (struct ixgbe_adapter *)dev->data->dev_private;
6011         struct rte_eth_link link;
6012         uint32_t incval = 0;
6013         uint32_t shift = 0;
6014
6015         /* Get current link speed. */
6016         memset(&link, 0, sizeof(link));
6017         ixgbe_dev_link_update(dev, 1);
6018         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6019
6020         switch (link.link_speed) {
6021         case ETH_SPEED_NUM_100M:
6022                 incval = IXGBE_INCVAL_100;
6023                 shift = IXGBE_INCVAL_SHIFT_100;
6024                 break;
6025         case ETH_SPEED_NUM_1G:
6026                 incval = IXGBE_INCVAL_1GB;
6027                 shift = IXGBE_INCVAL_SHIFT_1GB;
6028                 break;
6029         case ETH_SPEED_NUM_10G:
6030         default:
6031                 incval = IXGBE_INCVAL_10GB;
6032                 shift = IXGBE_INCVAL_SHIFT_10GB;
6033                 break;
6034         }
6035
6036         switch (hw->mac.type) {
6037         case ixgbe_mac_X550:
6038         case ixgbe_mac_X550EM_x:
6039         case ixgbe_mac_X550EM_a:
6040                 /* Independent of link speed. */
6041                 incval = 1;
6042                 /* Cycles read will be interpreted as ns. */
6043                 shift = 0;
6044                 /* Fall-through */
6045         case ixgbe_mac_X540:
6046                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6047                 break;
6048         case ixgbe_mac_82599EB:
6049                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6050                 shift -= IXGBE_INCVAL_SHIFT_82599;
6051                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6052                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6053                 break;
6054         default:
6055                 /* Not supported. */
6056                 return;
6057         }
6058
6059         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6060         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6061         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6062
6063         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6064         adapter->systime_tc.cc_shift = shift;
6065         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6066
6067         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6068         adapter->rx_tstamp_tc.cc_shift = shift;
6069         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6070
6071         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6072         adapter->tx_tstamp_tc.cc_shift = shift;
6073         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6074 }
6075
6076 static int
6077 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6078 {
6079         struct ixgbe_adapter *adapter =
6080                         (struct ixgbe_adapter *)dev->data->dev_private;
6081
6082         adapter->systime_tc.nsec += delta;
6083         adapter->rx_tstamp_tc.nsec += delta;
6084         adapter->tx_tstamp_tc.nsec += delta;
6085
6086         return 0;
6087 }
6088
6089 static int
6090 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6091 {
6092         uint64_t ns;
6093         struct ixgbe_adapter *adapter =
6094                         (struct ixgbe_adapter *)dev->data->dev_private;
6095
6096         ns = rte_timespec_to_ns(ts);
6097         /* Set the timecounters to a new value. */
6098         adapter->systime_tc.nsec = ns;
6099         adapter->rx_tstamp_tc.nsec = ns;
6100         adapter->tx_tstamp_tc.nsec = ns;
6101
6102         return 0;
6103 }
6104
6105 static int
6106 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6107 {
6108         uint64_t ns, systime_cycles;
6109         struct ixgbe_adapter *adapter =
6110                         (struct ixgbe_adapter *)dev->data->dev_private;
6111
6112         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6113         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6114         *ts = rte_ns_to_timespec(ns);
6115
6116         return 0;
6117 }
6118
6119 static int
6120 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6121 {
6122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6123         uint32_t tsync_ctl;
6124         uint32_t tsauxc;
6125
6126         /* Stop the timesync system time. */
6127         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6128         /* Reset the timesync system time value. */
6129         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6130         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6131
6132         /* Enable system time for platforms where it isn't on by default. */
6133         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6134         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6135         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6136
6137         ixgbe_start_timecounters(dev);
6138
6139         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6140         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6141                         (ETHER_TYPE_1588 |
6142                          IXGBE_ETQF_FILTER_EN |
6143                          IXGBE_ETQF_1588));
6144
6145         /* Enable timestamping of received PTP packets. */
6146         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6147         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6148         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6149
6150         /* Enable timestamping of transmitted PTP packets. */
6151         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6152         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6153         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6154
6155         IXGBE_WRITE_FLUSH(hw);
6156
6157         return 0;
6158 }
6159
6160 static int
6161 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6162 {
6163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6164         uint32_t tsync_ctl;
6165
6166         /* Disable timestamping of transmitted PTP packets. */
6167         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6168         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6169         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6170
6171         /* Disable timestamping of received PTP packets. */
6172         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6173         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6174         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6175
6176         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6177         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6178
6179         /* Stop incrementating the System Time registers. */
6180         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6181
6182         return 0;
6183 }
6184
6185 static int
6186 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6187                                  struct timespec *timestamp,
6188                                  uint32_t flags __rte_unused)
6189 {
6190         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6191         struct ixgbe_adapter *adapter =
6192                 (struct ixgbe_adapter *)dev->data->dev_private;
6193         uint32_t tsync_rxctl;
6194         uint64_t rx_tstamp_cycles;
6195         uint64_t ns;
6196
6197         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6198         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6199                 return -EINVAL;
6200
6201         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6202         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6203         *timestamp = rte_ns_to_timespec(ns);
6204
6205         return  0;
6206 }
6207
6208 static int
6209 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6210                                  struct timespec *timestamp)
6211 {
6212         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6213         struct ixgbe_adapter *adapter =
6214                 (struct ixgbe_adapter *)dev->data->dev_private;
6215         uint32_t tsync_txctl;
6216         uint64_t tx_tstamp_cycles;
6217         uint64_t ns;
6218
6219         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6220         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6221                 return -EINVAL;
6222
6223         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6224         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6225         *timestamp = rte_ns_to_timespec(ns);
6226
6227         return 0;
6228 }
6229
6230 static int
6231 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6232 {
6233         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6234         int count = 0;
6235         int g_ind = 0;
6236         const struct reg_info *reg_group;
6237         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6238                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6239
6240         while ((reg_group = reg_set[g_ind++]))
6241                 count += ixgbe_regs_group_count(reg_group);
6242
6243         return count;
6244 }
6245
6246 static int
6247 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6248 {
6249         int count = 0;
6250         int g_ind = 0;
6251         const struct reg_info *reg_group;
6252
6253         while ((reg_group = ixgbevf_regs[g_ind++]))
6254                 count += ixgbe_regs_group_count(reg_group);
6255
6256         return count;
6257 }
6258
6259 static int
6260 ixgbe_get_regs(struct rte_eth_dev *dev,
6261               struct rte_dev_reg_info *regs)
6262 {
6263         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6264         uint32_t *data = regs->data;
6265         int g_ind = 0;
6266         int count = 0;
6267         const struct reg_info *reg_group;
6268         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6269                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6270
6271         /* Support only full register dump */
6272         if ((regs->length == 0) ||
6273             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6274                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6275                         hw->device_id;
6276                 while ((reg_group = reg_set[g_ind++]))
6277                         count += ixgbe_read_regs_group(dev, &data[count],
6278                                 reg_group);
6279                 return 0;
6280         }
6281
6282         return -ENOTSUP;
6283 }
6284
6285 static int
6286 ixgbevf_get_regs(struct rte_eth_dev *dev,
6287                 struct rte_dev_reg_info *regs)
6288 {
6289         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6290         uint32_t *data = regs->data;
6291         int g_ind = 0;
6292         int count = 0;
6293         const struct reg_info *reg_group;
6294
6295         /* Support only full register dump */
6296         if ((regs->length == 0) ||
6297             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6298                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6299                         hw->device_id;
6300                 while ((reg_group = ixgbevf_regs[g_ind++]))
6301                         count += ixgbe_read_regs_group(dev, &data[count],
6302                                                       reg_group);
6303                 return 0;
6304         }
6305
6306         return -ENOTSUP;
6307 }
6308
6309 static int
6310 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6311 {
6312         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6313
6314         /* Return unit is byte count */
6315         return hw->eeprom.word_size * 2;
6316 }
6317
6318 static int
6319 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6320                 struct rte_dev_eeprom_info *in_eeprom)
6321 {
6322         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6323         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6324         uint16_t *data = in_eeprom->data;
6325         int first, length;
6326
6327         first = in_eeprom->offset >> 1;
6328         length = in_eeprom->length >> 1;
6329         if ((first > hw->eeprom.word_size) ||
6330             ((first + length) > hw->eeprom.word_size))
6331                 return -EINVAL;
6332
6333         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6334
6335         return eeprom->ops.read_buffer(hw, first, length, data);
6336 }
6337
6338 static int
6339 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6340                 struct rte_dev_eeprom_info *in_eeprom)
6341 {
6342         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6343         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6344         uint16_t *data = in_eeprom->data;
6345         int first, length;
6346
6347         first = in_eeprom->offset >> 1;
6348         length = in_eeprom->length >> 1;
6349         if ((first > hw->eeprom.word_size) ||
6350             ((first + length) > hw->eeprom.word_size))
6351                 return -EINVAL;
6352
6353         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6354
6355         return eeprom->ops.write_buffer(hw,  first, length, data);
6356 }
6357
6358 uint16_t
6359 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6360         switch (mac_type) {
6361         case ixgbe_mac_X550:
6362         case ixgbe_mac_X550EM_x:
6363         case ixgbe_mac_X550EM_a:
6364                 return ETH_RSS_RETA_SIZE_512;
6365         case ixgbe_mac_X550_vf:
6366         case ixgbe_mac_X550EM_x_vf:
6367         case ixgbe_mac_X550EM_a_vf:
6368                 return ETH_RSS_RETA_SIZE_64;
6369         default:
6370                 return ETH_RSS_RETA_SIZE_128;
6371         }
6372 }
6373
6374 uint32_t
6375 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6376         switch (mac_type) {
6377         case ixgbe_mac_X550:
6378         case ixgbe_mac_X550EM_x:
6379         case ixgbe_mac_X550EM_a:
6380                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6381                         return IXGBE_RETA(reta_idx >> 2);
6382                 else
6383                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6384         case ixgbe_mac_X550_vf:
6385         case ixgbe_mac_X550EM_x_vf:
6386         case ixgbe_mac_X550EM_a_vf:
6387                 return IXGBE_VFRETA(reta_idx >> 2);
6388         default:
6389                 return IXGBE_RETA(reta_idx >> 2);
6390         }
6391 }
6392
6393 uint32_t
6394 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6395         switch (mac_type) {
6396         case ixgbe_mac_X550_vf:
6397         case ixgbe_mac_X550EM_x_vf:
6398         case ixgbe_mac_X550EM_a_vf:
6399                 return IXGBE_VFMRQC;
6400         default:
6401                 return IXGBE_MRQC;
6402         }
6403 }
6404
6405 uint32_t
6406 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6407         switch (mac_type) {
6408         case ixgbe_mac_X550_vf:
6409         case ixgbe_mac_X550EM_x_vf:
6410         case ixgbe_mac_X550EM_a_vf:
6411                 return IXGBE_VFRSSRK(i);
6412         default:
6413                 return IXGBE_RSSRK(i);
6414         }
6415 }
6416
6417 bool
6418 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6419         switch (mac_type) {
6420         case ixgbe_mac_82599_vf:
6421         case ixgbe_mac_X540_vf:
6422                 return 0;
6423         default:
6424                 return 1;
6425         }
6426 }
6427
6428 static int
6429 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6430                         struct rte_eth_dcb_info *dcb_info)
6431 {
6432         struct ixgbe_dcb_config *dcb_config =
6433                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6434         struct ixgbe_dcb_tc_config *tc;
6435         uint8_t i, j;
6436
6437         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6438                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6439         else
6440                 dcb_info->nb_tcs = 1;
6441
6442         if (dcb_config->vt_mode) { /* vt is enabled*/
6443                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6444                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6445                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6446                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6447                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6448                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6449                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6450                                                 i * dcb_info->nb_tcs + j;
6451                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6452                                 dcb_info->tc_queue.tc_txq[i][j].base =
6453                                                 i * dcb_info->nb_tcs + j;
6454                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6455                         }
6456                 }
6457         } else { /* vt is disabled*/
6458                 struct rte_eth_dcb_rx_conf *rx_conf =
6459                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6460                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6461                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6462                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6463                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6464                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6465                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6466                         }
6467                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6468                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6469                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6470                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6471                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6472                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6473                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6474                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6475                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6476                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6477                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6478                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6479                         }
6480                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6481                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6482                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6483                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6484                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6485                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6486                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6487                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6488                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6489                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6490                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6491                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6492                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6493                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6494                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6495                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6496                 }
6497         }
6498         for (i = 0; i < dcb_info->nb_tcs; i++) {
6499                 tc = &dcb_config->tc_config[i];
6500                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6501         }
6502         return 0;
6503 }
6504
6505 /* Update e-tag ether type */
6506 static int
6507 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6508                             uint16_t ether_type)
6509 {
6510         uint32_t etag_etype;
6511
6512         if (hw->mac.type != ixgbe_mac_X550 &&
6513             hw->mac.type != ixgbe_mac_X550EM_x &&
6514             hw->mac.type != ixgbe_mac_X550EM_a) {
6515                 return -ENOTSUP;
6516         }
6517
6518         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6519         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6520         etag_etype |= ether_type;
6521         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6522         IXGBE_WRITE_FLUSH(hw);
6523
6524         return 0;
6525 }
6526
6527 /* Config l2 tunnel ether type */
6528 static int
6529 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6530                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6531 {
6532         int ret = 0;
6533         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6534
6535         if (l2_tunnel == NULL)
6536                 return -EINVAL;
6537
6538         switch (l2_tunnel->l2_tunnel_type) {
6539         case RTE_L2_TUNNEL_TYPE_E_TAG:
6540                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6541                 break;
6542         default:
6543                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6544                 ret = -EINVAL;
6545                 break;
6546         }
6547
6548         return ret;
6549 }
6550
6551 /* Enable e-tag tunnel */
6552 static int
6553 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6554 {
6555         uint32_t etag_etype;
6556
6557         if (hw->mac.type != ixgbe_mac_X550 &&
6558             hw->mac.type != ixgbe_mac_X550EM_x &&
6559             hw->mac.type != ixgbe_mac_X550EM_a) {
6560                 return -ENOTSUP;
6561         }
6562
6563         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6564         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6565         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6566         IXGBE_WRITE_FLUSH(hw);
6567
6568         return 0;
6569 }
6570
6571 /* Enable l2 tunnel */
6572 static int
6573 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6574                            enum rte_eth_tunnel_type l2_tunnel_type)
6575 {
6576         int ret = 0;
6577         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6578
6579         switch (l2_tunnel_type) {
6580         case RTE_L2_TUNNEL_TYPE_E_TAG:
6581                 ret = ixgbe_e_tag_enable(hw);
6582                 break;
6583         default:
6584                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6585                 ret = -EINVAL;
6586                 break;
6587         }
6588
6589         return ret;
6590 }
6591
6592 /* Disable e-tag tunnel */
6593 static int
6594 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6595 {
6596         uint32_t etag_etype;
6597
6598         if (hw->mac.type != ixgbe_mac_X550 &&
6599             hw->mac.type != ixgbe_mac_X550EM_x &&
6600             hw->mac.type != ixgbe_mac_X550EM_a) {
6601                 return -ENOTSUP;
6602         }
6603
6604         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6605         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6606         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6607         IXGBE_WRITE_FLUSH(hw);
6608
6609         return 0;
6610 }
6611
6612 /* Disable l2 tunnel */
6613 static int
6614 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6615                             enum rte_eth_tunnel_type l2_tunnel_type)
6616 {
6617         int ret = 0;
6618         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6619
6620         switch (l2_tunnel_type) {
6621         case RTE_L2_TUNNEL_TYPE_E_TAG:
6622                 ret = ixgbe_e_tag_disable(hw);
6623                 break;
6624         default:
6625                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6626                 ret = -EINVAL;
6627                 break;
6628         }
6629
6630         return ret;
6631 }
6632
6633 static int
6634 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6635                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6636 {
6637         int ret = 0;
6638         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6639         uint32_t i, rar_entries;
6640         uint32_t rar_low, rar_high;
6641
6642         if (hw->mac.type != ixgbe_mac_X550 &&
6643             hw->mac.type != ixgbe_mac_X550EM_x &&
6644             hw->mac.type != ixgbe_mac_X550EM_a) {
6645                 return -ENOTSUP;
6646         }
6647
6648         rar_entries = ixgbe_get_num_rx_addrs(hw);
6649
6650         for (i = 1; i < rar_entries; i++) {
6651                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6652                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6653                 if ((rar_high & IXGBE_RAH_AV) &&
6654                     (rar_high & IXGBE_RAH_ADTYPE) &&
6655                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6656                      l2_tunnel->tunnel_id)) {
6657                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6658                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6659
6660                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6661
6662                         return ret;
6663                 }
6664         }
6665
6666         return ret;
6667 }
6668
6669 static int
6670 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6671                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6672 {
6673         int ret = 0;
6674         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6675         uint32_t i, rar_entries;
6676         uint32_t rar_low, rar_high;
6677
6678         if (hw->mac.type != ixgbe_mac_X550 &&
6679             hw->mac.type != ixgbe_mac_X550EM_x &&
6680             hw->mac.type != ixgbe_mac_X550EM_a) {
6681                 return -ENOTSUP;
6682         }
6683
6684         /* One entry for one tunnel. Try to remove potential existing entry. */
6685         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6686
6687         rar_entries = ixgbe_get_num_rx_addrs(hw);
6688
6689         for (i = 1; i < rar_entries; i++) {
6690                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6691                 if (rar_high & IXGBE_RAH_AV) {
6692                         continue;
6693                 } else {
6694                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6695                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6696                         rar_low = l2_tunnel->tunnel_id;
6697
6698                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6699                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6700
6701                         return ret;
6702                 }
6703         }
6704
6705         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6706                      " Please remove a rule before adding a new one.");
6707         return -EINVAL;
6708 }
6709
6710 /* Add l2 tunnel filter */
6711 static int
6712 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6713                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6714 {
6715         int ret = 0;
6716
6717         switch (l2_tunnel->l2_tunnel_type) {
6718         case RTE_L2_TUNNEL_TYPE_E_TAG:
6719                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6720                 break;
6721         default:
6722                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6723                 ret = -EINVAL;
6724                 break;
6725         }
6726
6727         return ret;
6728 }
6729
6730 /* Delete l2 tunnel filter */
6731 static int
6732 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6733                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6734 {
6735         int ret = 0;
6736
6737         switch (l2_tunnel->l2_tunnel_type) {
6738         case RTE_L2_TUNNEL_TYPE_E_TAG:
6739                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6740                 break;
6741         default:
6742                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6743                 ret = -EINVAL;
6744                 break;
6745         }
6746
6747         return ret;
6748 }
6749
6750 /**
6751  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6752  * @dev: pointer to rte_eth_dev structure
6753  * @filter_op:operation will be taken.
6754  * @arg: a pointer to specific structure corresponding to the filter_op
6755  */
6756 static int
6757 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6758                                   enum rte_filter_op filter_op,
6759                                   void *arg)
6760 {
6761         int ret = 0;
6762
6763         if (filter_op == RTE_ETH_FILTER_NOP)
6764                 return 0;
6765
6766         if (arg == NULL) {
6767                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6768                             filter_op);
6769                 return -EINVAL;
6770         }
6771
6772         switch (filter_op) {
6773         case RTE_ETH_FILTER_ADD:
6774                 ret = ixgbe_dev_l2_tunnel_filter_add
6775                         (dev,
6776                          (struct rte_eth_l2_tunnel_conf *)arg);
6777                 break;
6778         case RTE_ETH_FILTER_DELETE:
6779                 ret = ixgbe_dev_l2_tunnel_filter_del
6780                         (dev,
6781                          (struct rte_eth_l2_tunnel_conf *)arg);
6782                 break;
6783         default:
6784                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6785                 ret = -EINVAL;
6786                 break;
6787         }
6788         return ret;
6789 }
6790
6791 static int
6792 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6793 {
6794         int ret = 0;
6795         uint32_t ctrl;
6796         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6797
6798         if (hw->mac.type != ixgbe_mac_X550 &&
6799             hw->mac.type != ixgbe_mac_X550EM_x &&
6800             hw->mac.type != ixgbe_mac_X550EM_a) {
6801                 return -ENOTSUP;
6802         }
6803
6804         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6805         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6806         if (en)
6807                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6808         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6809
6810         return ret;
6811 }
6812
6813 /* Enable l2 tunnel forwarding */
6814 static int
6815 ixgbe_dev_l2_tunnel_forwarding_enable
6816         (struct rte_eth_dev *dev,
6817          enum rte_eth_tunnel_type l2_tunnel_type)
6818 {
6819         int ret = 0;
6820
6821         switch (l2_tunnel_type) {
6822         case RTE_L2_TUNNEL_TYPE_E_TAG:
6823                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6824                 break;
6825         default:
6826                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6827                 ret = -EINVAL;
6828                 break;
6829         }
6830
6831         return ret;
6832 }
6833
6834 /* Disable l2 tunnel forwarding */
6835 static int
6836 ixgbe_dev_l2_tunnel_forwarding_disable
6837         (struct rte_eth_dev *dev,
6838          enum rte_eth_tunnel_type l2_tunnel_type)
6839 {
6840         int ret = 0;
6841
6842         switch (l2_tunnel_type) {
6843         case RTE_L2_TUNNEL_TYPE_E_TAG:
6844                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6845                 break;
6846         default:
6847                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6848                 ret = -EINVAL;
6849                 break;
6850         }
6851
6852         return ret;
6853 }
6854
6855 static int
6856 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6857                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6858                              bool en)
6859 {
6860         int ret = 0;
6861         uint32_t vmtir, vmvir;
6862         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6863
6864         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6865                 PMD_DRV_LOG(ERR,
6866                             "VF id %u should be less than %u",
6867                             l2_tunnel->vf_id,
6868                             dev->pci_dev->max_vfs);
6869                 return -EINVAL;
6870         }
6871
6872         if (hw->mac.type != ixgbe_mac_X550 &&
6873             hw->mac.type != ixgbe_mac_X550EM_x &&
6874             hw->mac.type != ixgbe_mac_X550EM_a) {
6875                 return -ENOTSUP;
6876         }
6877
6878         if (en)
6879                 vmtir = l2_tunnel->tunnel_id;
6880         else
6881                 vmtir = 0;
6882
6883         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6884
6885         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6886         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6887         if (en)
6888                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6889         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6890
6891         return ret;
6892 }
6893
6894 /* Enable l2 tunnel tag insertion */
6895 static int
6896 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6897                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6898 {
6899         int ret = 0;
6900
6901         switch (l2_tunnel->l2_tunnel_type) {
6902         case RTE_L2_TUNNEL_TYPE_E_TAG:
6903                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6904                 break;
6905         default:
6906                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6907                 ret = -EINVAL;
6908                 break;
6909         }
6910
6911         return ret;
6912 }
6913
6914 /* Disable l2 tunnel tag insertion */
6915 static int
6916 ixgbe_dev_l2_tunnel_insertion_disable
6917         (struct rte_eth_dev *dev,
6918          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6919 {
6920         int ret = 0;
6921
6922         switch (l2_tunnel->l2_tunnel_type) {
6923         case RTE_L2_TUNNEL_TYPE_E_TAG:
6924                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6925                 break;
6926         default:
6927                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6928                 ret = -EINVAL;
6929                 break;
6930         }
6931
6932         return ret;
6933 }
6934
6935 static int
6936 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6937                              bool en)
6938 {
6939         int ret = 0;
6940         uint32_t qde;
6941         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6942
6943         if (hw->mac.type != ixgbe_mac_X550 &&
6944             hw->mac.type != ixgbe_mac_X550EM_x &&
6945             hw->mac.type != ixgbe_mac_X550EM_a) {
6946                 return -ENOTSUP;
6947         }
6948
6949         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6950         if (en)
6951                 qde |= IXGBE_QDE_STRIP_TAG;
6952         else
6953                 qde &= ~IXGBE_QDE_STRIP_TAG;
6954         qde &= ~IXGBE_QDE_READ;
6955         qde |= IXGBE_QDE_WRITE;
6956         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6957
6958         return ret;
6959 }
6960
6961 /* Enable l2 tunnel tag stripping */
6962 static int
6963 ixgbe_dev_l2_tunnel_stripping_enable
6964         (struct rte_eth_dev *dev,
6965          enum rte_eth_tunnel_type l2_tunnel_type)
6966 {
6967         int ret = 0;
6968
6969         switch (l2_tunnel_type) {
6970         case RTE_L2_TUNNEL_TYPE_E_TAG:
6971                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6972                 break;
6973         default:
6974                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6975                 ret = -EINVAL;
6976                 break;
6977         }
6978
6979         return ret;
6980 }
6981
6982 /* Disable l2 tunnel tag stripping */
6983 static int
6984 ixgbe_dev_l2_tunnel_stripping_disable
6985         (struct rte_eth_dev *dev,
6986          enum rte_eth_tunnel_type l2_tunnel_type)
6987 {
6988         int ret = 0;
6989
6990         switch (l2_tunnel_type) {
6991         case RTE_L2_TUNNEL_TYPE_E_TAG:
6992                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6993                 break;
6994         default:
6995                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6996                 ret = -EINVAL;
6997                 break;
6998         }
6999
7000         return ret;
7001 }
7002
7003 /* Enable/disable l2 tunnel offload functions */
7004 static int
7005 ixgbe_dev_l2_tunnel_offload_set
7006         (struct rte_eth_dev *dev,
7007          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7008          uint32_t mask,
7009          uint8_t en)
7010 {
7011         int ret = 0;
7012
7013         if (l2_tunnel == NULL)
7014                 return -EINVAL;
7015
7016         ret = -EINVAL;
7017         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7018                 if (en)
7019                         ret = ixgbe_dev_l2_tunnel_enable(
7020                                 dev,
7021                                 l2_tunnel->l2_tunnel_type);
7022                 else
7023                         ret = ixgbe_dev_l2_tunnel_disable(
7024                                 dev,
7025                                 l2_tunnel->l2_tunnel_type);
7026         }
7027
7028         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7029                 if (en)
7030                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7031                                 dev,
7032                                 l2_tunnel);
7033                 else
7034                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7035                                 dev,
7036                                 l2_tunnel);
7037         }
7038
7039         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7040                 if (en)
7041                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7042                                 dev,
7043                                 l2_tunnel->l2_tunnel_type);
7044                 else
7045                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7046                                 dev,
7047                                 l2_tunnel->l2_tunnel_type);
7048         }
7049
7050         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7051                 if (en)
7052                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7053                                 dev,
7054                                 l2_tunnel->l2_tunnel_type);
7055                 else
7056                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7057                                 dev,
7058                                 l2_tunnel->l2_tunnel_type);
7059         }
7060
7061         return ret;
7062 }
7063
7064 static int
7065 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7066                         uint16_t port)
7067 {
7068         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7069         IXGBE_WRITE_FLUSH(hw);
7070
7071         return 0;
7072 }
7073
7074 /* There's only one register for VxLAN UDP port.
7075  * So, we cannot add several ports. Will update it.
7076  */
7077 static int
7078 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7079                      uint16_t port)
7080 {
7081         if (port == 0) {
7082                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7083                 return -EINVAL;
7084         }
7085
7086         return ixgbe_update_vxlan_port(hw, port);
7087 }
7088
7089 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7090  * UDP port, it must have a value.
7091  * So, will reset it to the original value 0.
7092  */
7093 static int
7094 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7095                      uint16_t port)
7096 {
7097         uint16_t cur_port;
7098
7099         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7100
7101         if (cur_port != port) {
7102                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7103                 return -EINVAL;
7104         }
7105
7106         return ixgbe_update_vxlan_port(hw, 0);
7107 }
7108
7109 /* Add UDP tunneling port */
7110 static int
7111 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7112                               struct rte_eth_udp_tunnel *udp_tunnel)
7113 {
7114         int ret = 0;
7115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7116
7117         if (hw->mac.type != ixgbe_mac_X550 &&
7118             hw->mac.type != ixgbe_mac_X550EM_x &&
7119             hw->mac.type != ixgbe_mac_X550EM_a) {
7120                 return -ENOTSUP;
7121         }
7122
7123         if (udp_tunnel == NULL)
7124                 return -EINVAL;
7125
7126         switch (udp_tunnel->prot_type) {
7127         case RTE_TUNNEL_TYPE_VXLAN:
7128                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7129                 break;
7130
7131         case RTE_TUNNEL_TYPE_GENEVE:
7132         case RTE_TUNNEL_TYPE_TEREDO:
7133                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7134                 ret = -EINVAL;
7135                 break;
7136
7137         default:
7138                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7139                 ret = -EINVAL;
7140                 break;
7141         }
7142
7143         return ret;
7144 }
7145
7146 /* Remove UDP tunneling port */
7147 static int
7148 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7149                               struct rte_eth_udp_tunnel *udp_tunnel)
7150 {
7151         int ret = 0;
7152         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7153
7154         if (hw->mac.type != ixgbe_mac_X550 &&
7155             hw->mac.type != ixgbe_mac_X550EM_x &&
7156             hw->mac.type != ixgbe_mac_X550EM_a) {
7157                 return -ENOTSUP;
7158         }
7159
7160         if (udp_tunnel == NULL)
7161                 return -EINVAL;
7162
7163         switch (udp_tunnel->prot_type) {
7164         case RTE_TUNNEL_TYPE_VXLAN:
7165                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7166                 break;
7167         case RTE_TUNNEL_TYPE_GENEVE:
7168         case RTE_TUNNEL_TYPE_TEREDO:
7169                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7170                 ret = -EINVAL;
7171                 break;
7172         default:
7173                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7174                 ret = -EINVAL;
7175                 break;
7176         }
7177
7178         return ret;
7179 }
7180
7181 /* ixgbevf_update_xcast_mode - Update Multicast mode
7182  * @hw: pointer to the HW structure
7183  * @netdev: pointer to net device structure
7184  * @xcast_mode: new multicast mode
7185  *
7186  * Updates the Multicast Mode of VF.
7187  */
7188 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7189                                      int xcast_mode)
7190 {
7191         struct ixgbe_mbx_info *mbx = &hw->mbx;
7192         u32 msgbuf[2];
7193         s32 err;
7194
7195         switch (hw->api_version) {
7196         case ixgbe_mbox_api_12:
7197                 break;
7198         default:
7199                 return -EOPNOTSUPP;
7200         }
7201
7202         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7203         msgbuf[1] = xcast_mode;
7204
7205         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7206         if (err)
7207                 return err;
7208
7209         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7210         if (err)
7211                 return err;
7212
7213         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7214         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7215                 return -EPERM;
7216
7217         return 0;
7218 }
7219
7220 static void
7221 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7222 {
7223         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7224
7225         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7226 }
7227
7228 static void
7229 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7230 {
7231         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7232
7233         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7234 }
7235
7236 static struct rte_driver rte_ixgbe_driver = {
7237         .type = PMD_PDEV,
7238         .init = rte_ixgbe_pmd_init,
7239 };
7240
7241 static struct rte_driver rte_ixgbevf_driver = {
7242         .type = PMD_PDEV,
7243         .init = rte_ixgbevf_pmd_init,
7244 };
7245
7246 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7247 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);