drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Timer value included in XOFF frames. */
  89 #define IXGBE_FC_PAUSE 0x680
  90
  91 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  92 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  93 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  94
  95 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  96 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  97 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  98
  99 /*
 100  *  Default values for RX/TX configuration
 101  */
 102 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 103 #define IXGBE_DEFAULT_RX_PTHRESH      8
 104 #define IXGBE_DEFAULT_RX_HTHRESH      8
 105 #define IXGBE_DEFAULT_RX_WTHRESH      0
 106
 107 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_TX_PTHRESH      32
 109 #define IXGBE_DEFAULT_TX_HTHRESH      0
 110 #define IXGBE_DEFAULT_TX_WTHRESH      0
 111 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 112
 113 /* Bit shift and mask */
 114 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 115 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 116 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 117 #define IXGBE_8_BIT_MASK   UINT8_MAX
 118
 119 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 120
 121 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 122
 123 #define IXGBE_HKEY_MAX_INDEX 10
 124
 125 /* Additional timesync values. */
 126 #define IXGBE_TIMINCA_16NS_SHIFT 24
 127 #define IXGBE_TIMINCA_INCVALUE   16000000
 128 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 129                                   | IXGBE_TIMINCA_INCVALUE)
 130
 131 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 132 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 133 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 134 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 135 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 136 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 139 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 140 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 143 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 144                                 int wait_to_complete);
 145 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 146                                 struct rte_eth_stats *stats);
 147 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 148                                 struct rte_eth_xstats *xstats, unsigned n);
 149 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 152                                              uint16_t queue_id,
 153                                              uint8_t stat_idx,
 154                                              uint8_t is_rx);
 155 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 156                                struct rte_eth_dev_info *dev_info);
 157 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 158                                  struct rte_eth_dev_info *dev_info);
 159 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 160
 161 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 162                 uint16_t vlan_id, int on);
 163 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 164 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 165                 uint16_t queue, bool on);
 166 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 167                 int on);
 168 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 169 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 170 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 171 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 172 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 173
 174 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 176 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_fc_conf *fc_conf);
 178 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 179                                struct rte_eth_fc_conf *fc_conf);
 180 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 181                 struct rte_eth_pfc_conf *pfc_conf);
 182 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 183                         struct rte_eth_rss_reta_entry64 *reta_conf,
 184                         uint16_t reta_size);
 185 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 186                         struct rte_eth_rss_reta_entry64 *reta_conf,
 187                         uint16_t reta_size);
 188 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 189 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 191 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 192 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 193                 void *param);
 194 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 195 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 196                 uint32_t index, uint32_t pool);
 197 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 198 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 199                                            struct ether_addr *mac_addr);
 200 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 201
 202 /* For Virtual Function support */
 203 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 204 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 205 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 206 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 207 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 208 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 209 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 210 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 211                 struct rte_eth_stats *stats);
 212 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 213 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 214                 uint16_t vlan_id, int on);
 215 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 216                 uint16_t queue, int on);
 217 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 218 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 219
 220 /* For Eth VMDQ APIs support */
 221 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 222                 ether_addr* mac_addr,uint8_t on);
 223 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 224 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 225                 uint16_t rx_mask, uint8_t on);
 226 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 227 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 228 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 229                 uint64_t pool_mask,uint8_t vlan_on);
 230 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 231                 struct rte_eth_mirror_conf *mirror_conf,
 232                 uint8_t rule_id, uint8_t on);
 233 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 234                 uint8_t rule_id);
 235
 236 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 237                 uint16_t queue_idx, uint16_t tx_rate);
 238 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 239                 uint16_t tx_rate, uint64_t q_msk);
 240
 241 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 242                                  struct ether_addr *mac_addr,
 243                                  uint32_t index, uint32_t pool);
 244 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 245 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 246                                              struct ether_addr *mac_addr);
 247 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 248                         struct rte_eth_syn_filter *filter,
 249                         bool add);
 250 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 251                         struct rte_eth_syn_filter *filter);
 252 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 253                         enum rte_filter_op filter_op,
 254                         void *arg);
 255 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 256                         struct ixgbe_5tuple_filter *filter);
 257 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 258                         struct ixgbe_5tuple_filter *filter);
 259 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 260                         struct rte_eth_ntuple_filter *filter,
 261                         bool add);
 262 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 263                                 enum rte_filter_op filter_op,
 264                                 void *arg);
 265 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 266                         struct rte_eth_ntuple_filter *filter);
 267 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 268                         struct rte_eth_ethertype_filter *filter,
 269                         bool add);
 270 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 271                                 enum rte_filter_op filter_op,
 272                                 void *arg);
 273 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 274                         struct rte_eth_ethertype_filter *filter);
 275 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 276                      enum rte_filter_type filter_type,
 277                      enum rte_filter_op filter_op,
 278                      void *arg);
 279 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 280
 281 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 282                                       struct ether_addr *mc_addr_set,
 283                                       uint32_t nb_mc_addr);
 284
 285 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 286 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 287                             struct rte_dev_reg_info *regs);
 288 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 289 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 290                                 struct rte_dev_eeprom_info *eeprom);
 291 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 292                                 struct rte_dev_eeprom_info *eeprom);
 293
 294 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 295 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 296                                 struct rte_dev_reg_info *regs);
 297
 298 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 299 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 300 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 301                                             struct timespec *timestamp,
 302                                             uint32_t flags);
 303 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 304                                             struct timespec *timestamp);
 305
 306 /*
 307  * Define VF Stats MACRO for Non "cleared on read" register
 308  */
 309 #define UPDATE_VF_STAT(reg, last, cur)                          \
 310 {                                                               \
 311         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 312         cur += latest - last;                                   \
 313         last = latest;                                          \
 314 }
 315
 316 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 317 {                                                                \
 318         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 319         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 320         u64 latest = ((new_msb << 32) | new_lsb);                \
 321         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 322         last = latest;                                           \
 323 }
 324
 325 #define IXGBE_SET_HWSTRIP(h, q) do{\
 326                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 327                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 328                 (h)->bitmap[idx] |= 1 << bit;\
 329         }while(0)
 330
 331 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 332                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 333                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 334                 (h)->bitmap[idx] &= ~(1 << bit);\
 335         }while(0)
 336
 337 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 338                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 339                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 340                 (r) = (h)->bitmap[idx] >> bit & 1;\
 341         }while(0)
 342
 343 /*
 344  * The set of PCI devices this driver supports
 345  */
 346 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 347
 348 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 349 #include "rte_pci_dev_ids.h"
 350
 351 { .vendor_id = 0, /* sentinel */ },
 352 };
 353
 354
 355 /*
 356  * The set of PCI devices this driver supports (for 82599 VF)
 357  */
 358 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 359
 360 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 361 #include "rte_pci_dev_ids.h"
 362 { .vendor_id = 0, /* sentinel */ },
 363
 364 };
 365
 366 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 367         .dev_configure        = ixgbe_dev_configure,
 368         .dev_start            = ixgbe_dev_start,
 369         .dev_stop             = ixgbe_dev_stop,
 370         .dev_set_link_up    = ixgbe_dev_set_link_up,
 371         .dev_set_link_down  = ixgbe_dev_set_link_down,
 372         .dev_close            = ixgbe_dev_close,
 373         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 374         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 375         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 376         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 377         .link_update          = ixgbe_dev_link_update,
 378         .stats_get            = ixgbe_dev_stats_get,
 379         .xstats_get           = ixgbe_dev_xstats_get,
 380         .stats_reset          = ixgbe_dev_stats_reset,
 381         .xstats_reset         = ixgbe_dev_xstats_reset,
 382         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 383         .dev_infos_get        = ixgbe_dev_info_get,
 384         .mtu_set              = ixgbe_dev_mtu_set,
 385         .vlan_filter_set      = ixgbe_vlan_filter_set,
 386         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 387         .vlan_offload_set     = ixgbe_vlan_offload_set,
 388         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 389         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 390         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 391         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 392         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 393         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 394         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 395         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 396         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 397         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 398         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 399         .dev_led_on           = ixgbe_dev_led_on,
 400         .dev_led_off          = ixgbe_dev_led_off,
 401         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 402         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 403         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 404         .mac_addr_add         = ixgbe_add_rar,
 405         .mac_addr_remove      = ixgbe_remove_rar,
 406         .mac_addr_set         = ixgbe_set_default_mac_addr,
 407         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 408         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 409         .mirror_rule_set      = ixgbe_mirror_rule_set,
 410         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 411         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 412         .set_vf_rx            = ixgbe_set_pool_rx,
 413         .set_vf_tx            = ixgbe_set_pool_tx,
 414         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 415         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 416         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 417         .reta_update          = ixgbe_dev_rss_reta_update,
 418         .reta_query           = ixgbe_dev_rss_reta_query,
 419 #ifdef RTE_NIC_BYPASS
 420         .bypass_init          = ixgbe_bypass_init,
 421         .bypass_state_set     = ixgbe_bypass_state_store,
 422         .bypass_state_show    = ixgbe_bypass_state_show,
 423         .bypass_event_set     = ixgbe_bypass_event_store,
 424         .bypass_event_show    = ixgbe_bypass_event_show,
 425         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 426         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 427         .bypass_ver_show      = ixgbe_bypass_ver_show,
 428         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 429 #endif /* RTE_NIC_BYPASS */
 430         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 431         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 432         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 433         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 434         .timesync_enable      = ixgbe_timesync_enable,
 435         .timesync_disable     = ixgbe_timesync_disable,
 436         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 437         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 438         .get_reg_length       = ixgbe_get_reg_length,
 439         .get_reg              = ixgbe_get_regs,
 440         .get_eeprom_length    = ixgbe_get_eeprom_length,
 441         .get_eeprom           = ixgbe_get_eeprom,
 442         .set_eeprom           = ixgbe_set_eeprom,
 443 };
 444
 445 /*
 446  * dev_ops for virtual function, bare necessities for basic vf
 447  * operation have been implemented
 448  */
 449 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 450         .dev_configure        = ixgbevf_dev_configure,
 451         .dev_start            = ixgbevf_dev_start,
 452         .dev_stop             = ixgbevf_dev_stop,
 453         .link_update          = ixgbe_dev_link_update,
 454         .stats_get            = ixgbevf_dev_stats_get,
 455         .stats_reset          = ixgbevf_dev_stats_reset,
 456         .dev_close            = ixgbevf_dev_close,
 457         .dev_infos_get        = ixgbevf_dev_info_get,
 458         .mtu_set              = ixgbevf_dev_set_mtu,
 459         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 460         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 461         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 462         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 463         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 464         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 465         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 466         .mac_addr_add         = ixgbevf_add_mac_addr,
 467         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 468         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 469         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 470         .get_reg_length       = ixgbevf_get_reg_length,
 471         .get_reg              = ixgbevf_get_regs,
 472 };
 473
 474 /* store statistics names and its offset in stats structure */
 475 struct rte_ixgbe_xstats_name_off {
 476         char name[RTE_ETH_XSTATS_NAME_SIZE];
 477         unsigned offset;
 478 };
 479
 480 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 481         {"rx_illegal_byte_err", offsetof(struct ixgbe_hw_stats, errbc)},
 482         {"rx_len_err", offsetof(struct ixgbe_hw_stats, rlec)},
 483         {"rx_undersize_count", offsetof(struct ixgbe_hw_stats, ruc)},
 484         {"rx_oversize_count", offsetof(struct ixgbe_hw_stats, roc)},
 485         {"rx_fragment_count", offsetof(struct ixgbe_hw_stats, rfc)},
 486         {"rx_jabber_count", offsetof(struct ixgbe_hw_stats, rjc)},
 487         {"l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 488         {"mac_local_fault", offsetof(struct ixgbe_hw_stats, mlfc)},
 489         {"mac_remote_fault", offsetof(struct ixgbe_hw_stats, mrfc)},
 490         {"mac_short_pkt_discard", offsetof(struct ixgbe_hw_stats, mspdc)},
 491         {"fccrc_error", offsetof(struct ixgbe_hw_stats, fccrc)},
 492         {"fcoe_drop", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 493         {"fc_last_error", offsetof(struct ixgbe_hw_stats, fclast)},
 494         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 495         {"rx_phy_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 496         {"mgmt_pkts_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 497         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 498         {"fdir_match", offsetof(struct ixgbe_hw_stats, fdirmatch)},
 499         {"fdir_miss", offsetof(struct ixgbe_hw_stats, fdirmiss)},
 500         {"tx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxontxc)},
 501         {"rx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 502         {"tx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 503         {"rx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 504 };
 505
 506 #define IXGBE_NB_XSTATS (sizeof(rte_ixgbe_stats_strings) /      \
 507                 sizeof(rte_ixgbe_stats_strings[0]))
 508
 509 /**
 510  * Atomically reads the link status information from global
 511  * structure rte_eth_dev.
 512  *
 513  * @param dev
 514  *   - Pointer to the structure rte_eth_dev to read from.
 515  *   - Pointer to the buffer to be saved with the link status.
 516  *
 517  * @return
 518  *   - On success, zero.
 519  *   - On failure, negative value.
 520  */
 521 static inline int
 522 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 523                                 struct rte_eth_link *link)
 524 {
 525         struct rte_eth_link *dst = link;
 526         struct rte_eth_link *src = &(dev->data->dev_link);
 527
 528         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 529                                         *(uint64_t *)src) == 0)
 530                 return -1;
 531
 532         return 0;
 533 }
 534
 535 /**
 536  * Atomically writes the link status information into global
 537  * structure rte_eth_dev.
 538  *
 539  * @param dev
 540  *   - Pointer to the structure rte_eth_dev to read from.
 541  *   - Pointer to the buffer to be saved with the link status.
 542  *
 543  * @return
 544  *   - On success, zero.
 545  *   - On failure, negative value.
 546  */
 547 static inline int
 548 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 549                                 struct rte_eth_link *link)
 550 {
 551         struct rte_eth_link *dst = &(dev->data->dev_link);
 552         struct rte_eth_link *src = link;
 553
 554         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 555                                         *(uint64_t *)src) == 0)
 556                 return -1;
 557
 558         return 0;
 559 }
 560
 561 /*
 562  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 563  */
 564 static inline int
 565 ixgbe_is_sfp(struct ixgbe_hw *hw)
 566 {
 567         switch (hw->phy.type) {
 568         case ixgbe_phy_sfp_avago:
 569         case ixgbe_phy_sfp_ftl:
 570         case ixgbe_phy_sfp_intel:
 571         case ixgbe_phy_sfp_unknown:
 572         case ixgbe_phy_sfp_passive_tyco:
 573         case ixgbe_phy_sfp_passive_unknown:
 574                 return 1;
 575         default:
 576                 return 0;
 577         }
 578 }
 579
 580 static inline int32_t
 581 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 582 {
 583         uint32_t ctrl_ext;
 584         int32_t status;
 585
 586         status = ixgbe_reset_hw(hw);
 587
 588         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 589         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 590         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 591         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 592         IXGBE_WRITE_FLUSH(hw);
 593
 594         return status;
 595 }
 596
 597 static inline void
 598 ixgbe_enable_intr(struct rte_eth_dev *dev)
 599 {
 600         struct ixgbe_interrupt *intr =
 601                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 602         struct ixgbe_hw *hw =
 603                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 604
 605         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 606         IXGBE_WRITE_FLUSH(hw);
 607 }
 608
 609 /*
 610  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 611  */
 612 static void
 613 ixgbe_disable_intr(struct ixgbe_hw *hw)
 614 {
 615         PMD_INIT_FUNC_TRACE();
 616
 617         if (hw->mac.type == ixgbe_mac_82598EB) {
 618                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 619         } else {
 620                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 621                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 622                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 623         }
 624         IXGBE_WRITE_FLUSH(hw);
 625 }
 626
 627 /*
 628  * This function resets queue statistics mapping registers.
 629  * From Niantic datasheet, Initialization of Statistics section:
 630  * "...if software requires the queue counters, the RQSMR and TQSM registers
 631  * must be re-programmed following a device reset.
 632  */
 633 static void
 634 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 635 {
 636         uint32_t i;
 637
 638         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 639                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 640                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 641         }
 642 }
 643
 644
 645 static int
 646 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 647                                   uint16_t queue_id,
 648                                   uint8_t stat_idx,
 649                                   uint8_t is_rx)
 650 {
 651 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 652 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 653 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 654
 655         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 656         struct ixgbe_stat_mapping_registers *stat_mappings =
 657                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 658         uint32_t qsmr_mask = 0;
 659         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 660         uint32_t q_map;
 661         uint8_t n, offset;
 662
 663         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 664                 (hw->mac.type != ixgbe_mac_X540) &&
 665                 (hw->mac.type != ixgbe_mac_X550) &&
 666                 (hw->mac.type != ixgbe_mac_X550EM_x))
 667                 return -ENOSYS;
 668
 669         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 670                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 671                      queue_id, stat_idx);
 672
 673         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 674         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 675                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 676                 return -EIO;
 677         }
 678         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 679
 680         /* Now clear any previous stat_idx set */
 681         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 682         if (!is_rx)
 683                 stat_mappings->tqsm[n] &= ~clearing_mask;
 684         else
 685                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 686
 687         q_map = (uint32_t)stat_idx;
 688         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 689         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 690         if (!is_rx)
 691                 stat_mappings->tqsm[n] |= qsmr_mask;
 692         else
 693                 stat_mappings->rqsmr[n] |= qsmr_mask;
 694
 695         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 696                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 697                      queue_id, stat_idx);
 698         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 699                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 700
 701         /* Now write the mapping in the appropriate register */
 702         if (is_rx) {
 703                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 704                              stat_mappings->rqsmr[n], n);
 705                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 706         }
 707         else {
 708                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 709                              stat_mappings->tqsm[n], n);
 710                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 711         }
 712         return 0;
 713 }
 714
 715 static void
 716 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 717 {
 718         struct ixgbe_stat_mapping_registers *stat_mappings =
 719                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 721         int i;
 722
 723         /* write whatever was in stat mapping table to the NIC */
 724         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 725                 /* rx */
 726                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 727
 728                 /* tx */
 729                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 730         }
 731 }
 732
 733 static void
 734 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 735 {
 736         uint8_t i;
 737         struct ixgbe_dcb_tc_config *tc;
 738         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 739
 740         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 741         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 742         for (i = 0; i < dcb_max_tc; i++) {
 743                 tc = &dcb_config->tc_config[i];
 744                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 745                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 746                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 747                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 748                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 749                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 750                 tc->pfc = ixgbe_dcb_pfc_disabled;
 751         }
 752
 753         /* Initialize default user to priority mapping, UPx->TC0 */
 754         tc = &dcb_config->tc_config[0];
 755         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 756         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 757         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 758                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 759                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 760         }
 761         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 762         dcb_config->pfc_mode_enable = false;
 763         dcb_config->vt_mode = true;
 764         dcb_config->round_robin_enable = false;
 765         /* support all DCB capabilities in 82599 */
 766         dcb_config->support.capabilities = 0xFF;
 767
 768         /*we only support 4 Tcs for X540, X550 */
 769         if (hw->mac.type == ixgbe_mac_X540 ||
 770                 hw->mac.type == ixgbe_mac_X550 ||
 771                 hw->mac.type == ixgbe_mac_X550EM_x) {
 772                 dcb_config->num_tcs.pg_tcs = 4;
 773                 dcb_config->num_tcs.pfc_tcs = 4;
 774         }
 775 }
 776
 777 /*
 778  * Ensure that all locks are released before first NVM or PHY access
 779  */
 780 static void
 781 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 782 {
 783         uint16_t mask;
 784
 785         /*
 786          * Phy lock should not fail in this early stage. If this is the case,
 787          * it is due to an improper exit of the application.
 788          * So force the release of the faulty lock. Release of common lock
 789          * is done automatically by swfw_sync function.
 790          */
 791         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 792         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 793                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 794         }
 795         ixgbe_release_swfw_semaphore(hw, mask);
 796
 797         /*
 798          * These ones are more tricky since they are common to all ports; but
 799          * swfw_sync retries last long enough (1s) to be almost sure that if
 800          * lock can not be taken it is due to an improper lock of the
 801          * semaphore.
 802          */
 803         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 804         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 805                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 806         }
 807         ixgbe_release_swfw_semaphore(hw, mask);
 808 }
 809
 810 /*
 811  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 812  * It returns 0 on success.
 813  */
 814 static int
 815 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 816 {
 817         struct rte_pci_device *pci_dev;
 818         struct ixgbe_hw *hw =
 819                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 820         struct ixgbe_vfta * shadow_vfta =
 821                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 822         struct ixgbe_hwstrip *hwstrip =
 823                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 824         struct ixgbe_dcb_config *dcb_config =
 825                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 826         struct ixgbe_filter_info *filter_info =
 827                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 828         uint32_t ctrl_ext;
 829         uint16_t csum;
 830         int diag, i;
 831
 832         PMD_INIT_FUNC_TRACE();
 833
 834         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 835         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 836         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 837
 838         /*
 839          * For secondary processes, we don't initialise any further as primary
 840          * has already done this work. Only check we don't need a different
 841          * RX and TX function.
 842          */
 843         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 844                 struct ixgbe_tx_queue *txq;
 845                 /* TX queue function in primary, set by last queue initialized
 846                  * Tx queue may not initialized by primary process */
 847                 if (eth_dev->data->tx_queues) {
 848                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 849                         ixgbe_set_tx_function(eth_dev, txq);
 850                 } else {
 851                         /* Use default TX function if we get here */
 852                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 853                                            "Using default TX function.");
 854                 }
 855
 856                 ixgbe_set_rx_function(eth_dev);
 857
 858                 return 0;
 859         }
 860         pci_dev = eth_dev->pci_dev;
 861
 862         /* Vendor and Device ID need to be set before init of shared code */
 863         hw->device_id = pci_dev->id.device_id;
 864         hw->vendor_id = pci_dev->id.vendor_id;
 865         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 866         hw->allow_unsupported_sfp = 1;
 867
 868         /* Initialize the shared code (base driver) */
 869 #ifdef RTE_NIC_BYPASS
 870         diag = ixgbe_bypass_init_shared_code(hw);
 871 #else
 872         diag = ixgbe_init_shared_code(hw);
 873 #endif /* RTE_NIC_BYPASS */
 874
 875         if (diag != IXGBE_SUCCESS) {
 876                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 877                 return -EIO;
 878         }
 879
 880         /* pick up the PCI bus settings for reporting later */
 881         ixgbe_get_bus_info(hw);
 882
 883         /* Unlock any pending hardware semaphore */
 884         ixgbe_swfw_lock_reset(hw);
 885
 886         /* Initialize DCB configuration*/
 887         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 888         ixgbe_dcb_init(hw,dcb_config);
 889         /* Get Hardware Flow Control setting */
 890         hw->fc.requested_mode = ixgbe_fc_full;
 891         hw->fc.current_mode = ixgbe_fc_full;
 892         hw->fc.pause_time = IXGBE_FC_PAUSE;
 893         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 894                 hw->fc.low_water[i] = IXGBE_FC_LO;
 895                 hw->fc.high_water[i] = IXGBE_FC_HI;
 896         }
 897         hw->fc.send_xon = 1;
 898
 899         /* Make sure we have a good EEPROM before we read from it */
 900         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 901         if (diag != IXGBE_SUCCESS) {
 902                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 903                 return -EIO;
 904         }
 905
 906 #ifdef RTE_NIC_BYPASS
 907         diag = ixgbe_bypass_init_hw(hw);
 908 #else
 909         diag = ixgbe_init_hw(hw);
 910 #endif /* RTE_NIC_BYPASS */
 911
 912         /*
 913          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 914          * is called too soon after the kernel driver unbinding/binding occurs.
 915          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 916          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 917          * also called. See ixgbe_identify_phy_82599(). The reason for the
 918          * failure is not known, and only occuts when virtualisation features
 919          * are disabled in the bios. A delay of 100ms  was found to be enough by
 920          * trial-and-error, and is doubled to be safe.
 921          */
 922         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 923                 rte_delay_ms(200);
 924                 diag = ixgbe_init_hw(hw);
 925         }
 926
 927         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 928                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 929                     "LOM.  Please be aware there may be issues associated "
 930                     "with your hardware.");
 931                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 932                     "please contact your Intel or hardware representative "
 933                     "who provided you with this hardware.");
 934         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 935                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 936         if (diag) {
 937                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 938                 return -EIO;
 939         }
 940
 941         /* Reset the hw statistics */
 942         ixgbe_dev_stats_reset(eth_dev);
 943
 944         /* disable interrupt */
 945         ixgbe_disable_intr(hw);
 946
 947         /* reset mappings for queue statistics hw counters*/
 948         ixgbe_reset_qstat_mappings(hw);
 949
 950         /* Allocate memory for storing MAC addresses */
 951         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 952                         hw->mac.num_rar_entries, 0);
 953         if (eth_dev->data->mac_addrs == NULL) {
 954                 PMD_INIT_LOG(ERR,
 955                         "Failed to allocate %u bytes needed to store "
 956                         "MAC addresses",
 957                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 958                 return -ENOMEM;
 959         }
 960         /* Copy the permanent MAC address */
 961         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 962                         &eth_dev->data->mac_addrs[0]);
 963
 964         /* Allocate memory for storing hash filter MAC addresses */
 965         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 966                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 967         if (eth_dev->data->hash_mac_addrs == NULL) {
 968                 PMD_INIT_LOG(ERR,
 969                         "Failed to allocate %d bytes needed to store MAC addresses",
 970                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 971                 return -ENOMEM;
 972         }
 973
 974         /* initialize the vfta */
 975         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 976
 977         /* initialize the hw strip bitmap*/
 978         memset(hwstrip, 0, sizeof(*hwstrip));
 979
 980         /* initialize PF if max_vfs not zero */
 981         ixgbe_pf_host_init(eth_dev);
 982
 983         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 984         /* let hardware know driver is loaded */
 985         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 986         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 987         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 988         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 989         IXGBE_WRITE_FLUSH(hw);
 990
 991         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 992                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 993                              (int) hw->mac.type, (int) hw->phy.type,
 994                              (int) hw->phy.sfp_type);
 995         else
 996                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 997                              (int) hw->mac.type, (int) hw->phy.type);
 998
 999         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1000                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1001                         pci_dev->id.device_id);
1002
1003         rte_intr_callback_register(&(pci_dev->intr_handle),
1004                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1005
1006         /* enable uio intr after callback register */
1007         rte_intr_enable(&(pci_dev->intr_handle));
1008
1009         /* enable support intr */
1010         ixgbe_enable_intr(eth_dev);
1011
1012         /* initialize 5tuple filter list */
1013         TAILQ_INIT(&filter_info->fivetuple_list);
1014         memset(filter_info->fivetuple_mask, 0,
1015                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1016
1017         return 0;
1018 }
1019
1020 static int
1021 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1022 {
1023         struct rte_pci_device *pci_dev;
1024         struct ixgbe_hw *hw;
1025
1026         PMD_INIT_FUNC_TRACE();
1027
1028         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1029                 return -EPERM;
1030
1031         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1032         pci_dev = eth_dev->pci_dev;
1033
1034         if (hw->adapter_stopped == 0)
1035                 ixgbe_dev_close(eth_dev);
1036
1037         eth_dev->dev_ops = NULL;
1038         eth_dev->rx_pkt_burst = NULL;
1039         eth_dev->tx_pkt_burst = NULL;
1040
1041         /* Unlock any pending hardware semaphore */
1042         ixgbe_swfw_lock_reset(hw);
1043
1044         /* disable uio intr before callback unregister */
1045         rte_intr_disable(&(pci_dev->intr_handle));
1046         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1047                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1048
1049         /* uninitialize PF if max_vfs not zero */
1050         ixgbe_pf_host_uninit(eth_dev);
1051
1052         rte_free(eth_dev->data->mac_addrs);
1053         eth_dev->data->mac_addrs = NULL;
1054
1055         rte_free(eth_dev->data->hash_mac_addrs);
1056         eth_dev->data->hash_mac_addrs = NULL;
1057
1058         return 0;
1059 }
1060
1061 /*
1062  * Negotiate mailbox API version with the PF.
1063  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1064  * Then we try to negotiate starting with the most recent one.
1065  * If all negotiation attempts fail, then we will proceed with
1066  * the default one (ixgbe_mbox_api_10).
1067  */
1068 static void
1069 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1070 {
1071         int32_t i;
1072
1073         /* start with highest supported, proceed down */
1074         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1075                 ixgbe_mbox_api_11,
1076                 ixgbe_mbox_api_10,
1077         };
1078
1079         for (i = 0;
1080                         i != RTE_DIM(sup_ver) &&
1081                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1082                         i++)
1083                 ;
1084 }
1085
1086 static void
1087 generate_random_mac_addr(struct ether_addr *mac_addr)
1088 {
1089         uint64_t random;
1090
1091         /* Set Organizationally Unique Identifier (OUI) prefix. */
1092         mac_addr->addr_bytes[0] = 0x00;
1093         mac_addr->addr_bytes[1] = 0x09;
1094         mac_addr->addr_bytes[2] = 0xC0;
1095         /* Force indication of locally assigned MAC address. */
1096         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1097         /* Generate the last 3 bytes of the MAC address with a random number. */
1098         random = rte_rand();
1099         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1100 }
1101
1102 /*
1103  * Virtual Function device init
1104  */
1105 static int
1106 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1107 {
1108         int diag;
1109         uint32_t tc, tcs;
1110         struct rte_pci_device *pci_dev;
1111         struct ixgbe_hw *hw =
1112                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1113         struct ixgbe_vfta * shadow_vfta =
1114                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1115         struct ixgbe_hwstrip *hwstrip =
1116                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1117         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1118
1119         PMD_INIT_FUNC_TRACE();
1120
1121         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1122         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1123         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1124
1125         /* for secondary processes, we don't initialise any further as primary
1126          * has already done this work. Only check we don't need a different
1127          * RX function */
1128         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1129                 if (eth_dev->data->scattered_rx)
1130                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1131                 return 0;
1132         }
1133
1134         pci_dev = eth_dev->pci_dev;
1135
1136         hw->device_id = pci_dev->id.device_id;
1137         hw->vendor_id = pci_dev->id.vendor_id;
1138         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1139
1140         /* initialize the vfta */
1141         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1142
1143         /* initialize the hw strip bitmap*/
1144         memset(hwstrip, 0, sizeof(*hwstrip));
1145
1146         /* Initialize the shared code (base driver) */
1147         diag = ixgbe_init_shared_code(hw);
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1150                 return -EIO;
1151         }
1152
1153         /* init_mailbox_params */
1154         hw->mbx.ops.init_params(hw);
1155
1156         /* Reset the hw statistics */
1157         ixgbevf_dev_stats_reset(eth_dev);
1158
1159         /* Disable the interrupts for VF */
1160         ixgbevf_intr_disable(hw);
1161
1162         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1163         diag = hw->mac.ops.reset_hw(hw);
1164
1165         /*
1166          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1167          * the underlying PF driver has not assigned a MAC address to the VF.
1168          * In this case, assign a random MAC address.
1169          */
1170         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1171                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1172                 return (diag);
1173         }
1174
1175         /* negotiate mailbox API version to use with the PF. */
1176         ixgbevf_negotiate_api(hw);
1177
1178         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1179         ixgbevf_get_queues(hw, &tcs, &tc);
1180
1181         /* Allocate memory for storing MAC addresses */
1182         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1183                         hw->mac.num_rar_entries, 0);
1184         if (eth_dev->data->mac_addrs == NULL) {
1185                 PMD_INIT_LOG(ERR,
1186                         "Failed to allocate %u bytes needed to store "
1187                         "MAC addresses",
1188                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1189                 return -ENOMEM;
1190         }
1191
1192         /* Generate a random MAC address, if none was assigned by PF. */
1193         if (is_zero_ether_addr(perm_addr)) {
1194                 generate_random_mac_addr(perm_addr);
1195                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1196                 if (diag) {
1197                         rte_free(eth_dev->data->mac_addrs);
1198                         eth_dev->data->mac_addrs = NULL;
1199                         return diag;
1200                 }
1201                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1202                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1203                              "%02x:%02x:%02x:%02x:%02x:%02x",
1204                              perm_addr->addr_bytes[0],
1205                              perm_addr->addr_bytes[1],
1206                              perm_addr->addr_bytes[2],
1207                              perm_addr->addr_bytes[3],
1208                              perm_addr->addr_bytes[4],
1209                              perm_addr->addr_bytes[5]);
1210         }
1211
1212         /* Copy the permanent MAC address */
1213         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1214
1215         /* reset the hardware with the new settings */
1216         diag = hw->mac.ops.start_hw(hw);
1217         switch (diag) {
1218                 case  0:
1219                         break;
1220
1221                 default:
1222                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1223                         return (-EIO);
1224         }
1225
1226         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1227                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1228                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1229
1230         return 0;
1231 }
1232
1233 /* Virtual Function device uninit */
1234
1235 static int
1236 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1237 {
1238         struct ixgbe_hw *hw;
1239         unsigned i;
1240
1241         PMD_INIT_FUNC_TRACE();
1242
1243         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1244                 return -EPERM;
1245
1246         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1247
1248         if (hw->adapter_stopped == 0)
1249                 ixgbevf_dev_close(eth_dev);
1250
1251         eth_dev->dev_ops = NULL;
1252         eth_dev->rx_pkt_burst = NULL;
1253         eth_dev->tx_pkt_burst = NULL;
1254
1255         /* Disable the interrupts for VF */
1256         ixgbevf_intr_disable(hw);
1257
1258         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1259                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1260                 eth_dev->data->rx_queues[i] = NULL;
1261         }
1262         eth_dev->data->nb_rx_queues = 0;
1263
1264         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1265                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1266                 eth_dev->data->tx_queues[i] = NULL;
1267         }
1268         eth_dev->data->nb_tx_queues = 0;
1269
1270         rte_free(eth_dev->data->mac_addrs);
1271         eth_dev->data->mac_addrs = NULL;
1272
1273         return 0;
1274 }
1275
1276 static struct eth_driver rte_ixgbe_pmd = {
1277         .pci_drv = {
1278                 .name = "rte_ixgbe_pmd",
1279                 .id_table = pci_id_ixgbe_map,
1280                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1281                         RTE_PCI_DRV_DETACHABLE,
1282         },
1283         .eth_dev_init = eth_ixgbe_dev_init,
1284         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1285         .dev_private_size = sizeof(struct ixgbe_adapter),
1286 };
1287
1288 /*
1289  * virtual function driver struct
1290  */
1291 static struct eth_driver rte_ixgbevf_pmd = {
1292         .pci_drv = {
1293                 .name = "rte_ixgbevf_pmd",
1294                 .id_table = pci_id_ixgbevf_map,
1295                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1296         },
1297         .eth_dev_init = eth_ixgbevf_dev_init,
1298         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1299         .dev_private_size = sizeof(struct ixgbe_adapter),
1300 };
1301
1302 /*
1303  * Driver initialization routine.
1304  * Invoked once at EAL init time.
1305  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1306  */
1307 static int
1308 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1309 {
1310         PMD_INIT_FUNC_TRACE();
1311
1312         rte_eth_driver_register(&rte_ixgbe_pmd);
1313         return 0;
1314 }
1315
1316 /*
1317  * VF Driver initialization routine.
1318  * Invoked one at EAL init time.
1319  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1320  */
1321 static int
1322 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1323 {
1324         PMD_INIT_FUNC_TRACE();
1325
1326         rte_eth_driver_register(&rte_ixgbevf_pmd);
1327         return (0);
1328 }
1329
1330 static int
1331 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1332 {
1333         struct ixgbe_hw *hw =
1334                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1335         struct ixgbe_vfta * shadow_vfta =
1336                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1337         uint32_t vfta;
1338         uint32_t vid_idx;
1339         uint32_t vid_bit;
1340
1341         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1342         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1343         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1344         if (on)
1345                 vfta |= vid_bit;
1346         else
1347                 vfta &= ~vid_bit;
1348         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1349
1350         /* update local VFTA copy */
1351         shadow_vfta->vfta[vid_idx] = vfta;
1352
1353         return 0;
1354 }
1355
1356 static void
1357 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1358 {
1359         if (on)
1360                 ixgbe_vlan_hw_strip_enable(dev, queue);
1361         else
1362                 ixgbe_vlan_hw_strip_disable(dev, queue);
1363 }
1364
1365 static void
1366 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1367 {
1368         struct ixgbe_hw *hw =
1369                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1370
1371         /* Only the high 16-bits is valid */
1372         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1373 }
1374
1375 void
1376 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1377 {
1378         struct ixgbe_hw *hw =
1379                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380         uint32_t vlnctrl;
1381
1382         PMD_INIT_FUNC_TRACE();
1383
1384         /* Filter Table Disable */
1385         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1386         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1387
1388         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1389 }
1390
1391 void
1392 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1393 {
1394         struct ixgbe_hw *hw =
1395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396         struct ixgbe_vfta * shadow_vfta =
1397                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1398         uint32_t vlnctrl;
1399         uint16_t i;
1400
1401         PMD_INIT_FUNC_TRACE();
1402
1403         /* Filter Table Enable */
1404         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1405         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1406         vlnctrl |= IXGBE_VLNCTRL_VFE;
1407
1408         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1409
1410         /* write whatever is in local vfta copy */
1411         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1412                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1413 }
1414
1415 static void
1416 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1417 {
1418         struct ixgbe_hwstrip *hwstrip =
1419                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1420
1421         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1422                 return;
1423
1424         if (on)
1425                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1426         else
1427                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1428 }
1429
1430 static void
1431 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1432 {
1433         struct ixgbe_hw *hw =
1434                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1435         uint32_t ctrl;
1436
1437         PMD_INIT_FUNC_TRACE();
1438
1439         if (hw->mac.type == ixgbe_mac_82598EB) {
1440                 /* No queue level support */
1441                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1442                 return;
1443         }
1444         else {
1445                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1446                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1447                 ctrl &= ~IXGBE_RXDCTL_VME;
1448                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1449         }
1450         /* record those setting for HW strip per queue */
1451         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1452 }
1453
1454 static void
1455 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1456 {
1457         struct ixgbe_hw *hw =
1458                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1459         uint32_t ctrl;
1460
1461         PMD_INIT_FUNC_TRACE();
1462
1463         if (hw->mac.type == ixgbe_mac_82598EB) {
1464                 /* No queue level supported */
1465                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1466                 return;
1467         }
1468         else {
1469                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1470                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1471                 ctrl |= IXGBE_RXDCTL_VME;
1472                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1473         }
1474         /* record those setting for HW strip per queue */
1475         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1476 }
1477
1478 void
1479 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1480 {
1481         struct ixgbe_hw *hw =
1482                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1483         uint32_t ctrl;
1484         uint16_t i;
1485
1486         PMD_INIT_FUNC_TRACE();
1487
1488         if (hw->mac.type == ixgbe_mac_82598EB) {
1489                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1490                 ctrl &= ~IXGBE_VLNCTRL_VME;
1491                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1492         }
1493         else {
1494                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1495                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1496                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1497                         ctrl &= ~IXGBE_RXDCTL_VME;
1498                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1499
1500                         /* record those setting for HW strip per queue */
1501                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1502                 }
1503         }
1504 }
1505
1506 void
1507 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1508 {
1509         struct ixgbe_hw *hw =
1510                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1511         uint32_t ctrl;
1512         uint16_t i;
1513
1514         PMD_INIT_FUNC_TRACE();
1515
1516         if (hw->mac.type == ixgbe_mac_82598EB) {
1517                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1518                 ctrl |= IXGBE_VLNCTRL_VME;
1519                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1520         }
1521         else {
1522                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1523                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1524                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1525                         ctrl |= IXGBE_RXDCTL_VME;
1526                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1527
1528                         /* record those setting for HW strip per queue */
1529                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1530                 }
1531         }
1532 }
1533
1534 static void
1535 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1536 {
1537         struct ixgbe_hw *hw =
1538                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1539         uint32_t ctrl;
1540
1541         PMD_INIT_FUNC_TRACE();
1542
1543         /* DMATXCTRL: Geric Double VLAN Disable */
1544         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1545         ctrl &= ~IXGBE_DMATXCTL_GDV;
1546         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1547
1548         /* CTRL_EXT: Global Double VLAN Disable */
1549         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1550         ctrl &= ~IXGBE_EXTENDED_VLAN;
1551         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1552
1553 }
1554
1555 static void
1556 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1557 {
1558         struct ixgbe_hw *hw =
1559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560         uint32_t ctrl;
1561
1562         PMD_INIT_FUNC_TRACE();
1563
1564         /* DMATXCTRL: Geric Double VLAN Enable */
1565         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1566         ctrl |= IXGBE_DMATXCTL_GDV;
1567         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1568
1569         /* CTRL_EXT: Global Double VLAN Enable */
1570         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1571         ctrl |= IXGBE_EXTENDED_VLAN;
1572         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1573
1574         /*
1575          * VET EXT field in the EXVET register = 0x8100 by default
1576          * So no need to change. Same to VT field of DMATXCTL register
1577          */
1578 }
1579
1580 static void
1581 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1582 {
1583         if(mask & ETH_VLAN_STRIP_MASK){
1584                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1585                         ixgbe_vlan_hw_strip_enable_all(dev);
1586                 else
1587                         ixgbe_vlan_hw_strip_disable_all(dev);
1588         }
1589
1590         if(mask & ETH_VLAN_FILTER_MASK){
1591                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1592                         ixgbe_vlan_hw_filter_enable(dev);
1593                 else
1594                         ixgbe_vlan_hw_filter_disable(dev);
1595         }
1596
1597         if(mask & ETH_VLAN_EXTEND_MASK){
1598                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1599                         ixgbe_vlan_hw_extend_enable(dev);
1600                 else
1601                         ixgbe_vlan_hw_extend_disable(dev);
1602         }
1603 }
1604
1605 static void
1606 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1607 {
1608         struct ixgbe_hw *hw =
1609                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1611         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1612         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1613         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1614 }
1615
1616 static int
1617 ixgbe_dev_configure(struct rte_eth_dev *dev)
1618 {
1619         struct ixgbe_interrupt *intr =
1620                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1621         struct ixgbe_adapter *adapter =
1622                 (struct ixgbe_adapter *)dev->data->dev_private;
1623
1624         PMD_INIT_FUNC_TRACE();
1625
1626         /* set flag to update link status after init */
1627         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1628
1629         /*
1630          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1631          * allocation or vector Rx preconditions we will reset it.
1632          */
1633         adapter->rx_bulk_alloc_allowed = true;
1634         adapter->rx_vec_allowed = true;
1635
1636         return 0;
1637 }
1638
1639 /*
1640  * Configure device link speed and setup link.
1641  * It returns 0 on success.
1642  */
1643 static int
1644 ixgbe_dev_start(struct rte_eth_dev *dev)
1645 {
1646         struct ixgbe_hw *hw =
1647                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648         struct ixgbe_vf_info *vfinfo =
1649                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1650         int err, link_up = 0, negotiate = 0;
1651         uint32_t speed = 0;
1652         int mask = 0;
1653         int status;
1654         uint16_t vf, idx;
1655
1656         PMD_INIT_FUNC_TRACE();
1657
1658         /* IXGBE devices don't support half duplex */
1659         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1660                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1661                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1662                              dev->data->dev_conf.link_duplex,
1663                              dev->data->port_id);
1664                 return -EINVAL;
1665         }
1666
1667         /* stop adapter */
1668         hw->adapter_stopped = 0;
1669         ixgbe_stop_adapter(hw);
1670
1671         /* reinitialize adapter
1672          * this calls reset and start */
1673         status = ixgbe_pf_reset_hw(hw);
1674         if (status != 0)
1675                 return -1;
1676         hw->mac.ops.start_hw(hw);
1677         hw->mac.get_link_status = true;
1678
1679         /* configure PF module if SRIOV enabled */
1680         ixgbe_pf_host_configure(dev);
1681
1682         /* initialize transmission unit */
1683         ixgbe_dev_tx_init(dev);
1684
1685         /* This can fail when allocating mbufs for descriptor rings */
1686         err = ixgbe_dev_rx_init(dev);
1687         if (err) {
1688                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1689                 goto error;
1690         }
1691
1692         err = ixgbe_dev_rxtx_start(dev);
1693         if (err < 0) {
1694                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1695                 goto error;
1696         }
1697
1698         /* Skip link setup if loopback mode is enabled for 82599. */
1699         if (hw->mac.type == ixgbe_mac_82599EB &&
1700                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1701                 goto skip_link_setup;
1702
1703         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1704                 err = hw->mac.ops.setup_sfp(hw);
1705                 if (err)
1706                         goto error;
1707         }
1708
1709         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1710                 /* Turn on the copper */
1711                 ixgbe_set_phy_power(hw, true);
1712         } else {
1713                 /* Turn on the laser */
1714                 ixgbe_enable_tx_laser(hw);
1715         }
1716
1717         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1718         if (err)
1719                 goto error;
1720         dev->data->dev_link.link_status = link_up;
1721
1722         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1723         if (err)
1724                 goto error;
1725
1726         switch(dev->data->dev_conf.link_speed) {
1727         case ETH_LINK_SPEED_AUTONEG:
1728                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1729                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1730                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1731                 break;
1732         case ETH_LINK_SPEED_100:
1733                 /*
1734                  * Invalid for 82598 but error will be detected by
1735                  * ixgbe_setup_link()
1736                  */
1737                 speed = IXGBE_LINK_SPEED_100_FULL;
1738                 break;
1739         case ETH_LINK_SPEED_1000:
1740                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1741                 break;
1742         case ETH_LINK_SPEED_10000:
1743                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1744                 break;
1745         default:
1746                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1747                              dev->data->dev_conf.link_speed,
1748                              dev->data->port_id);
1749                 goto error;
1750         }
1751
1752         err = ixgbe_setup_link(hw, speed, link_up);
1753         if (err)
1754                 goto error;
1755
1756 skip_link_setup:
1757
1758         /* check if lsc interrupt is enabled */
1759         if (dev->data->dev_conf.intr_conf.lsc != 0)
1760                 ixgbe_dev_lsc_interrupt_setup(dev);
1761
1762         /* resume enabled intr since hw reset */
1763         ixgbe_enable_intr(dev);
1764
1765         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1766                 ETH_VLAN_EXTEND_MASK;
1767         ixgbe_vlan_offload_set(dev, mask);
1768
1769         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1770                 /* Enable vlan filtering for VMDq */
1771                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1772         }
1773
1774         /* Configure DCB hw */
1775         ixgbe_configure_dcb(dev);
1776
1777         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1778                 err = ixgbe_fdir_configure(dev);
1779                 if (err)
1780                         goto error;
1781         }
1782
1783         /* Restore vf rate limit */
1784         if (vfinfo != NULL) {
1785                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1786                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1787                                 if (vfinfo[vf].tx_rate[idx] != 0)
1788                                         ixgbe_set_vf_rate_limit(dev, vf,
1789                                                 vfinfo[vf].tx_rate[idx],
1790                                                 1 << idx);
1791         }
1792
1793         ixgbe_restore_statistics_mapping(dev);
1794
1795         return (0);
1796
1797 error:
1798         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1799         ixgbe_dev_clear_queues(dev);
1800         return -EIO;
1801 }
1802
1803 /*
1804  * Stop device: disable rx and tx functions to allow for reconfiguring.
1805  */
1806 static void
1807 ixgbe_dev_stop(struct rte_eth_dev *dev)
1808 {
1809         struct rte_eth_link link;
1810         struct ixgbe_hw *hw =
1811                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1812         struct ixgbe_vf_info *vfinfo =
1813                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1814         struct ixgbe_filter_info *filter_info =
1815                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1816         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1817         int vf;
1818
1819         PMD_INIT_FUNC_TRACE();
1820
1821         /* disable interrupts */
1822         ixgbe_disable_intr(hw);
1823
1824         /* reset the NIC */
1825         ixgbe_pf_reset_hw(hw);
1826         hw->adapter_stopped = 0;
1827
1828         /* stop adapter */
1829         ixgbe_stop_adapter(hw);
1830
1831         for (vf = 0; vfinfo != NULL &&
1832                      vf < dev->pci_dev->max_vfs; vf++)
1833                 vfinfo[vf].clear_to_send = false;
1834
1835         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1836                 /* Turn off the copper */
1837                 ixgbe_set_phy_power(hw, false);
1838         } else {
1839                 /* Turn off the laser */
1840                 ixgbe_disable_tx_laser(hw);
1841         }
1842
1843         ixgbe_dev_clear_queues(dev);
1844
1845         /* Clear stored conf */
1846         dev->data->scattered_rx = 0;
1847         dev->data->lro = 0;
1848
1849         /* Clear recorded link status */
1850         memset(&link, 0, sizeof(link));
1851         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1852
1853         /* Remove all ntuple filters of the device */
1854         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1855              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1856                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1857                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1858                              p_5tuple, entries);
1859                 rte_free(p_5tuple);
1860         }
1861         memset(filter_info->fivetuple_mask, 0,
1862                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1863
1864 }
1865
1866 /*
1867  * Set device link up: enable tx.
1868  */
1869 static int
1870 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1871 {
1872         struct ixgbe_hw *hw =
1873                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1874         if (hw->mac.type == ixgbe_mac_82599EB) {
1875 #ifdef RTE_NIC_BYPASS
1876                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1877                         /* Not suported in bypass mode */
1878                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1879                                      "by device id 0x%x", hw->device_id);
1880                         return -ENOTSUP;
1881                 }
1882 #endif
1883         }
1884
1885         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1886                 /* Turn on the copper */
1887                 ixgbe_set_phy_power(hw, true);
1888         } else {
1889                 /* Turn on the laser */
1890                 ixgbe_enable_tx_laser(hw);
1891         }
1892
1893         return 0;
1894 }
1895
1896 /*
1897  * Set device link down: disable tx.
1898  */
1899 static int
1900 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1901 {
1902         struct ixgbe_hw *hw =
1903                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904         if (hw->mac.type == ixgbe_mac_82599EB) {
1905 #ifdef RTE_NIC_BYPASS
1906                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1907                         /* Not suported in bypass mode */
1908                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1909                                      "by device id 0x%x", hw->device_id);
1910                         return -ENOTSUP;
1911                 }
1912 #endif
1913         }
1914
1915         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1916                 /* Turn off the copper */
1917                 ixgbe_set_phy_power(hw, false);
1918         } else {
1919                 /* Turn off the laser */
1920                 ixgbe_disable_tx_laser(hw);
1921         }
1922
1923         return 0;
1924 }
1925
1926 /*
1927  * Reest and stop device.
1928  */
1929 static void
1930 ixgbe_dev_close(struct rte_eth_dev *dev)
1931 {
1932         struct ixgbe_hw *hw =
1933                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934
1935         PMD_INIT_FUNC_TRACE();
1936
1937         ixgbe_pf_reset_hw(hw);
1938
1939         ixgbe_dev_stop(dev);
1940         hw->adapter_stopped = 1;
1941
1942         ixgbe_disable_pcie_master(hw);
1943
1944         /* reprogram the RAR[0] in case user changed it. */
1945         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1946 }
1947
1948 static void
1949 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
1950                                                    *hw_stats, uint64_t *total_missed_rx,
1951                                                    uint64_t *total_qbrc, uint64_t *total_qprc,
1952                                                    uint64_t *rxnfgpc, uint64_t *txdgpc,
1953                                                    uint64_t *total_qprdc)
1954 {
1955         uint32_t bprc, lxon, lxoff, total;
1956         unsigned i;
1957
1958         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1959         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1960         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1961         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1962
1963         for (i = 0; i < 8; i++) {
1964                 uint32_t mp;
1965                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1966                 /* global total per queue */
1967                 hw_stats->mpc[i] += mp;
1968                 /* Running comprehensive total for stats display */
1969                 *total_missed_rx += hw_stats->mpc[i];
1970                 if (hw->mac.type == ixgbe_mac_82598EB)
1971                         hw_stats->rnbc[i] +=
1972                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1973                 hw_stats->pxontxc[i] +=
1974                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1975                 hw_stats->pxonrxc[i] +=
1976                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1977                 hw_stats->pxofftxc[i] +=
1978                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1979                 hw_stats->pxoffrxc[i] +=
1980                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1981                 hw_stats->pxon2offc[i] +=
1982                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1983         }
1984         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1985                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1986                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1987                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1988                 hw_stats->qbrc[i] +=
1989                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1990                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1991                 hw_stats->qbtc[i] +=
1992                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1993                 *total_qprdc += hw_stats->qprdc[i] +=
1994                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1995
1996                 *total_qprc += hw_stats->qprc[i];
1997                 *total_qbrc += hw_stats->qbrc[i];
1998         }
1999         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2000         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2001         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2002
2003         /* Note that gprc counts missed packets */
2004         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2005         *rxnfgpc += IXGBE_READ_REG(hw, IXGBE_RXNFGPC);
2006         *txdgpc += IXGBE_READ_REG(hw, IXGBE_TXDGPC);
2007
2008         if (hw->mac.type != ixgbe_mac_82598EB) {
2009                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2010                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2011                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2012                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2013                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2014                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2015                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2016                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2017         } else {
2018                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2019                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2020                 /* 82598 only has a counter in the high register */
2021                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2022                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2023                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2024         }
2025
2026         /*
2027          * Workaround: mprc hardware is incorrectly counting
2028          * broadcasts, so for now we subtract those.
2029          */
2030         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2031         hw_stats->bprc += bprc;
2032         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2033         if (hw->mac.type == ixgbe_mac_82598EB)
2034                 hw_stats->mprc -= bprc;
2035
2036         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2037         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2038         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2039         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2040         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2041         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2042
2043         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2044         hw_stats->lxontxc += lxon;
2045         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2046         hw_stats->lxofftxc += lxoff;
2047         total = lxon + lxoff;
2048
2049         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2050         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2051         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2052         hw_stats->gptc -= total;
2053         hw_stats->mptc -= total;
2054         hw_stats->ptc64 -= total;
2055         hw_stats->gotc -= total * ETHER_MIN_LEN;
2056
2057         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2058         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2059         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2060         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2061         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2062         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2063         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2064         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2065         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2066         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2067         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2068         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2069         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2070         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2071         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2072         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2073         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2074         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2075         /* Only read FCOE on 82599 */
2076         if (hw->mac.type != ixgbe_mac_82598EB) {
2077                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2078                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2079                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2080                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2081                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2082         }
2083
2084         /* Flow Director Stats registers */
2085         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2086         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2087 }
2088
2089 /*
2090  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2091  */
2092 static void
2093 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2094 {
2095         struct ixgbe_hw *hw =
2096                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2097         struct ixgbe_hw_stats *hw_stats =
2098                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2099         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2100         uint64_t rxnfgpc, txdgpc;
2101         unsigned i;
2102
2103         total_missed_rx = 0;
2104         total_qbrc = 0;
2105         total_qprc = 0;
2106         total_qprdc = 0;
2107         rxnfgpc = 0;
2108         txdgpc = 0;
2109
2110         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2111                         &total_qprc, &rxnfgpc, &txdgpc, &total_qprdc);
2112
2113         if (stats == NULL)
2114                 return;
2115
2116         /* Fill out the rte_eth_stats statistics structure */
2117         stats->ipackets = total_qprc;
2118         stats->ibytes = total_qbrc;
2119         stats->opackets = hw_stats->gptc;
2120         stats->obytes = hw_stats->gotc;
2121
2122         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2123                 stats->q_ipackets[i] = hw_stats->qprc[i];
2124                 stats->q_opackets[i] = hw_stats->qptc[i];
2125                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2126                 stats->q_obytes[i] = hw_stats->qbtc[i];
2127                 stats->q_errors[i] = hw_stats->qprdc[i];
2128         }
2129
2130         /* Rx Errors */
2131         stats->ierrors  = hw_stats->crcerrs +
2132                           hw_stats->rlec +
2133                           hw_stats->ruc +
2134                           hw_stats->roc +
2135                           total_missed_rx +
2136                           hw_stats->illerrc +
2137                           hw_stats->errbc +
2138                           hw_stats->xec +
2139                           hw_stats->mlfc +
2140                           hw_stats->mrfc +
2141                           hw_stats->rfc +
2142                           hw_stats->rjc +
2143                           hw_stats->fccrc +
2144                           hw_stats->fclast +
2145                           (rxnfgpc - hw_stats->gprc); /* PHY Errors*/
2146
2147         /* Tx Errors */
2148         /*txdgpc: packets that are DMA'ed*/
2149         /*gptc: packets that are sent*/
2150         stats->oerrors  = txdgpc - hw_stats->gptc;
2151 }
2152
2153 static void
2154 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2155 {
2156         struct ixgbe_hw_stats *stats =
2157                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2158
2159         /* HW registers are cleared on read */
2160         ixgbe_dev_stats_get(dev, NULL);
2161
2162         /* Reset software totals */
2163         memset(stats, 0, sizeof(*stats));
2164 }
2165
2166 static int
2167 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2168                                          unsigned n)
2169 {
2170         struct ixgbe_hw *hw =
2171                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2172         struct ixgbe_hw_stats *hw_stats =
2173                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2174         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2175         uint64_t rxnfgpc, txdgpc;
2176         unsigned i, count = IXGBE_NB_XSTATS;
2177
2178         if (n < count)
2179                 return count;
2180
2181         total_missed_rx = 0;
2182         total_qbrc = 0;
2183         total_qprc = 0;
2184         total_qprdc = 0;
2185         rxnfgpc = 0;
2186         txdgpc = 0;
2187
2188         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2189                                                            &total_qprc, &rxnfgpc, &txdgpc, &total_qprdc);
2190
2191         /* If this is a reset xstats is NULL, and we have cleared the
2192          * registers by reading them.
2193          */
2194         if (!xstats)
2195                 return 0;
2196
2197         /* Extended stats */
2198         for (i = 0; i < IXGBE_NB_XSTATS; i++) {
2199                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2200                                 "%s", rte_ixgbe_stats_strings[i].name);
2201                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2202                                                         rte_ixgbe_stats_strings[i].offset);
2203         }
2204
2205         return count;
2206 }
2207
2208 static void
2209 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2210 {
2211         struct ixgbe_hw_stats *stats =
2212                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2213
2214         /* HW registers are cleared on read */
2215         ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2216
2217         /* Reset software totals */
2218         memset(stats, 0, sizeof(*stats));
2219 }
2220
2221 static void
2222 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2223 {
2224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2225         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2226                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2227
2228         /* Good Rx packet, include VF loopback */
2229         UPDATE_VF_STAT(IXGBE_VFGPRC,
2230             hw_stats->last_vfgprc, hw_stats->vfgprc);
2231
2232         /* Good Rx octets, include VF loopback */
2233         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2234             hw_stats->last_vfgorc, hw_stats->vfgorc);
2235
2236         /* Good Tx packet, include VF loopback */
2237         UPDATE_VF_STAT(IXGBE_VFGPTC,
2238             hw_stats->last_vfgptc, hw_stats->vfgptc);
2239
2240         /* Good Tx octets, include VF loopback */
2241         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2242             hw_stats->last_vfgotc, hw_stats->vfgotc);
2243
2244         /* Rx Multicst Packet */
2245         UPDATE_VF_STAT(IXGBE_VFMPRC,
2246             hw_stats->last_vfmprc, hw_stats->vfmprc);
2247
2248         if (stats == NULL)
2249                 return;
2250
2251         stats->ipackets = hw_stats->vfgprc;
2252         stats->ibytes = hw_stats->vfgorc;
2253         stats->opackets = hw_stats->vfgptc;
2254         stats->obytes = hw_stats->vfgotc;
2255         stats->imcasts = hw_stats->vfmprc;
2256         /* stats->imcasts should be removed as imcasts is deprecated */
2257 }
2258
2259 static void
2260 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2261 {
2262         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2263                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2264
2265         /* Sync HW register to the last stats */
2266         ixgbevf_dev_stats_get(dev, NULL);
2267
2268         /* reset HW current stats*/
2269         hw_stats->vfgprc = 0;
2270         hw_stats->vfgorc = 0;
2271         hw_stats->vfgptc = 0;
2272         hw_stats->vfgotc = 0;
2273         hw_stats->vfmprc = 0;
2274
2275 }
2276
2277 static void
2278 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2279 {
2280         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2281
2282         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2283         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2284         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2285         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2286         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2287         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2288         dev_info->max_vfs = dev->pci_dev->max_vfs;
2289         if (hw->mac.type == ixgbe_mac_82598EB)
2290                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2291         else
2292                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2293         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2294         dev_info->rx_offload_capa =
2295                 DEV_RX_OFFLOAD_VLAN_STRIP |
2296                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2297                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2298                 DEV_RX_OFFLOAD_TCP_CKSUM;
2299
2300         /*
2301          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2302          * mode.
2303          */
2304         if ((hw->mac.type == ixgbe_mac_82599EB ||
2305              hw->mac.type == ixgbe_mac_X540) &&
2306             !RTE_ETH_DEV_SRIOV(dev).active)
2307                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2308
2309         dev_info->tx_offload_capa =
2310                 DEV_TX_OFFLOAD_VLAN_INSERT |
2311                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2312                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2313                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2314                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2315                 DEV_TX_OFFLOAD_TCP_TSO;
2316
2317         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2318                 .rx_thresh = {
2319                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2320                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2321                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2322                 },
2323                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2324                 .rx_drop_en = 0,
2325         };
2326
2327         dev_info->default_txconf = (struct rte_eth_txconf) {
2328                 .tx_thresh = {
2329                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2330                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2331                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2332                 },
2333                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2334                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2335                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2336                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2337         };
2338         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2339         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2340         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2341 }
2342
2343 static void
2344 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2345                      struct rte_eth_dev_info *dev_info)
2346 {
2347         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2348
2349         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2350         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2351         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2352         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2353         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2354         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2355         dev_info->max_vfs = dev->pci_dev->max_vfs;
2356         if (hw->mac.type == ixgbe_mac_82598EB)
2357                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2358         else
2359                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2360         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2361                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2362                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2363                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2364         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2365                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2366                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2367                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2368                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2369
2370         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2371                 .rx_thresh = {
2372                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2373                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2374                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2375                 },
2376                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2377                 .rx_drop_en = 0,
2378         };
2379
2380         dev_info->default_txconf = (struct rte_eth_txconf) {
2381                 .tx_thresh = {
2382                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2383                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2384                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2385                 },
2386                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2387                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2388                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2389                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2390         };
2391 }
2392
2393 /* return 0 means link status changed, -1 means not changed */
2394 static int
2395 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2396 {
2397         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398         struct rte_eth_link link, old;
2399         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2400         int link_up;
2401         int diag;
2402
2403         link.link_status = 0;
2404         link.link_speed = 0;
2405         link.link_duplex = 0;
2406         memset(&old, 0, sizeof(old));
2407         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2408
2409         hw->mac.get_link_status = true;
2410
2411         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2412         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2413                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2414         else
2415                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2416
2417         if (diag != 0) {
2418                 link.link_speed = ETH_LINK_SPEED_100;
2419                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2420                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2421                 if (link.link_status == old.link_status)
2422                         return -1;
2423                 return 0;
2424         }
2425
2426         if (link_up == 0) {
2427                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2428                 if (link.link_status == old.link_status)
2429                         return -1;
2430                 return 0;
2431         }
2432         link.link_status = 1;
2433         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2434
2435         switch (link_speed) {
2436         default:
2437         case IXGBE_LINK_SPEED_UNKNOWN:
2438                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2439                 link.link_speed = ETH_LINK_SPEED_100;
2440                 break;
2441
2442         case IXGBE_LINK_SPEED_100_FULL:
2443                 link.link_speed = ETH_LINK_SPEED_100;
2444                 break;
2445
2446         case IXGBE_LINK_SPEED_1GB_FULL:
2447                 link.link_speed = ETH_LINK_SPEED_1000;
2448                 break;
2449
2450         case IXGBE_LINK_SPEED_10GB_FULL:
2451                 link.link_speed = ETH_LINK_SPEED_10000;
2452                 break;
2453         }
2454         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2455
2456         if (link.link_status == old.link_status)
2457                 return -1;
2458
2459         return 0;
2460 }
2461
2462 static void
2463 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2464 {
2465         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466         uint32_t fctrl;
2467
2468         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2469         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2470         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2471 }
2472
2473 static void
2474 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2475 {
2476         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477         uint32_t fctrl;
2478
2479         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2480         fctrl &= (~IXGBE_FCTRL_UPE);
2481         if (dev->data->all_multicast == 1)
2482                 fctrl |= IXGBE_FCTRL_MPE;
2483         else
2484                 fctrl &= (~IXGBE_FCTRL_MPE);
2485         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2486 }
2487
2488 static void
2489 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2490 {
2491         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492         uint32_t fctrl;
2493
2494         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2495         fctrl |= IXGBE_FCTRL_MPE;
2496         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2497 }
2498
2499 static void
2500 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2501 {
2502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2503         uint32_t fctrl;
2504
2505         if (dev->data->promiscuous == 1)
2506                 return; /* must remain in all_multicast mode */
2507
2508         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2509         fctrl &= (~IXGBE_FCTRL_MPE);
2510         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2511 }
2512
2513 /**
2514  * It clears the interrupt causes and enables the interrupt.
2515  * It will be called once only during nic initialized.
2516  *
2517  * @param dev
2518  *  Pointer to struct rte_eth_dev.
2519  *
2520  * @return
2521  *  - On success, zero.
2522  *  - On failure, a negative value.
2523  */
2524 static int
2525 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2526 {
2527         struct ixgbe_interrupt *intr =
2528                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2529
2530         ixgbe_dev_link_status_print(dev);
2531         intr->mask |= IXGBE_EICR_LSC;
2532
2533         return 0;
2534 }
2535
2536 /*
2537  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2538  *
2539  * @param dev
2540  *  Pointer to struct rte_eth_dev.
2541  *
2542  * @return
2543  *  - On success, zero.
2544  *  - On failure, a negative value.
2545  */
2546 static int
2547 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2548 {
2549         uint32_t eicr;
2550         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2551         struct ixgbe_interrupt *intr =
2552                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2553
2554         /* clear all cause mask */
2555         ixgbe_disable_intr(hw);
2556
2557         /* read-on-clear nic registers here */
2558         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2559         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2560
2561         intr->flags = 0;
2562         if (eicr & IXGBE_EICR_LSC) {
2563                 /* set flag for async link update */
2564                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2565         }
2566
2567         if (eicr & IXGBE_EICR_MAILBOX)
2568                 intr->flags |= IXGBE_FLAG_MAILBOX;
2569
2570         return 0;
2571 }
2572
2573 /**
2574  * It gets and then prints the link status.
2575  *
2576  * @param dev
2577  *  Pointer to struct rte_eth_dev.
2578  *
2579  * @return
2580  *  - On success, zero.
2581  *  - On failure, a negative value.
2582  */
2583 static void
2584 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2585 {
2586         struct rte_eth_link link;
2587
2588         memset(&link, 0, sizeof(link));
2589         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2590         if (link.link_status) {
2591                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2592                                         (int)(dev->data->port_id),
2593                                         (unsigned)link.link_speed,
2594                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2595                                         "full-duplex" : "half-duplex");
2596         } else {
2597                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2598                                 (int)(dev->data->port_id));
2599         }
2600         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2601                                 dev->pci_dev->addr.domain,
2602                                 dev->pci_dev->addr.bus,
2603                                 dev->pci_dev->addr.devid,
2604                                 dev->pci_dev->addr.function);
2605 }
2606
2607 /*
2608  * It executes link_update after knowing an interrupt occurred.
2609  *
2610  * @param dev
2611  *  Pointer to struct rte_eth_dev.
2612  *
2613  * @return
2614  *  - On success, zero.
2615  *  - On failure, a negative value.
2616  */
2617 static int
2618 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2619 {
2620         struct ixgbe_interrupt *intr =
2621                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2622         int64_t timeout;
2623         struct rte_eth_link link;
2624         int intr_enable_delay = false;
2625
2626         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2627
2628         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2629                 ixgbe_pf_mbx_process(dev);
2630                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2631         }
2632
2633         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2634                 /* get the link status before link update, for predicting later */
2635                 memset(&link, 0, sizeof(link));
2636                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2637
2638                 ixgbe_dev_link_update(dev, 0);
2639
2640                 /* likely to up */
2641                 if (!link.link_status)
2642                         /* handle it 1 sec later, wait it being stable */
2643                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2644                 /* likely to down */
2645                 else
2646                         /* handle it 4 sec later, wait it being stable */
2647                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2648
2649                 ixgbe_dev_link_status_print(dev);
2650
2651                 intr_enable_delay = true;
2652         }
2653
2654         if (intr_enable_delay) {
2655                 if (rte_eal_alarm_set(timeout * 1000,
2656                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2657                         PMD_DRV_LOG(ERR, "Error setting alarm");
2658         } else {
2659                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2660                 ixgbe_enable_intr(dev);
2661                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2662         }
2663
2664
2665         return 0;
2666 }
2667
2668 /**
2669  * Interrupt handler which shall be registered for alarm callback for delayed
2670  * handling specific interrupt to wait for the stable nic state. As the
2671  * NIC interrupt state is not stable for ixgbe after link is just down,
2672  * it needs to wait 4 seconds to get the stable status.
2673  *
2674  * @param handle
2675  *  Pointer to interrupt handle.
2676  * @param param
2677  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2678  *
2679  * @return
2680  *  void
2681  */
2682 static void
2683 ixgbe_dev_interrupt_delayed_handler(void *param)
2684 {
2685         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2686         struct ixgbe_interrupt *intr =
2687                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2688         struct ixgbe_hw *hw =
2689                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690         uint32_t eicr;
2691
2692         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2693         if (eicr & IXGBE_EICR_MAILBOX)
2694                 ixgbe_pf_mbx_process(dev);
2695
2696         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2697                 ixgbe_dev_link_update(dev, 0);
2698                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2699                 ixgbe_dev_link_status_print(dev);
2700                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2701         }
2702
2703         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2704         ixgbe_enable_intr(dev);
2705         rte_intr_enable(&(dev->pci_dev->intr_handle));
2706 }
2707
2708 /**
2709  * Interrupt handler triggered by NIC  for handling
2710  * specific interrupt.
2711  *
2712  * @param handle
2713  *  Pointer to interrupt handle.
2714  * @param param
2715  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2716  *
2717  * @return
2718  *  void
2719  */
2720 static void
2721 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2722                                                         void *param)
2723 {
2724         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2725         ixgbe_dev_interrupt_get_status(dev);
2726         ixgbe_dev_interrupt_action(dev);
2727 }
2728
2729 static int
2730 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2731 {
2732         struct ixgbe_hw *hw;
2733
2734         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2735         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2736 }
2737
2738 static int
2739 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2740 {
2741         struct ixgbe_hw *hw;
2742
2743         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2744         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2745 }
2746
2747 static int
2748 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2749 {
2750         struct ixgbe_hw *hw;
2751         uint32_t mflcn_reg;
2752         uint32_t fccfg_reg;
2753         int rx_pause;
2754         int tx_pause;
2755
2756         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757
2758         fc_conf->pause_time = hw->fc.pause_time;
2759         fc_conf->high_water = hw->fc.high_water[0];
2760         fc_conf->low_water = hw->fc.low_water[0];
2761         fc_conf->send_xon = hw->fc.send_xon;
2762         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2763
2764         /*
2765          * Return rx_pause status according to actual setting of
2766          * MFLCN register.
2767          */
2768         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2769         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2770                 rx_pause = 1;
2771         else
2772                 rx_pause = 0;
2773
2774         /*
2775          * Return tx_pause status according to actual setting of
2776          * FCCFG register.
2777          */
2778         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2779         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2780                 tx_pause = 1;
2781         else
2782                 tx_pause = 0;
2783
2784         if (rx_pause && tx_pause)
2785                 fc_conf->mode = RTE_FC_FULL;
2786         else if (rx_pause)
2787                 fc_conf->mode = RTE_FC_RX_PAUSE;
2788         else if (tx_pause)
2789                 fc_conf->mode = RTE_FC_TX_PAUSE;
2790         else
2791                 fc_conf->mode = RTE_FC_NONE;
2792
2793         return 0;
2794 }
2795
2796 static int
2797 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2798 {
2799         struct ixgbe_hw *hw;
2800         int err;
2801         uint32_t rx_buf_size;
2802         uint32_t max_high_water;
2803         uint32_t mflcn;
2804         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2805                 ixgbe_fc_none,
2806                 ixgbe_fc_rx_pause,
2807                 ixgbe_fc_tx_pause,
2808                 ixgbe_fc_full
2809         };
2810
2811         PMD_INIT_FUNC_TRACE();
2812
2813         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2814         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2815         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2816
2817         /*
2818          * At least reserve one Ethernet frame for watermark
2819          * high_water/low_water in kilo bytes for ixgbe
2820          */
2821         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2822         if ((fc_conf->high_water > max_high_water) ||
2823                 (fc_conf->high_water < fc_conf->low_water)) {
2824                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2825                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2826                 return (-EINVAL);
2827         }
2828
2829         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2830         hw->fc.pause_time     = fc_conf->pause_time;
2831         hw->fc.high_water[0]  = fc_conf->high_water;
2832         hw->fc.low_water[0]   = fc_conf->low_water;
2833         hw->fc.send_xon       = fc_conf->send_xon;
2834         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2835
2836         err = ixgbe_fc_enable(hw);
2837
2838         /* Not negotiated is not an error case */
2839         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2840
2841                 /* check if we want to forward MAC frames - driver doesn't have native
2842                  * capability to do that, so we'll write the registers ourselves */
2843
2844                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2845
2846                 /* set or clear MFLCN.PMCF bit depending on configuration */
2847                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2848                         mflcn |= IXGBE_MFLCN_PMCF;
2849                 else
2850                         mflcn &= ~IXGBE_MFLCN_PMCF;
2851
2852                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2853                 IXGBE_WRITE_FLUSH(hw);
2854
2855                 return 0;
2856         }
2857
2858         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2859         return -EIO;
2860 }
2861
2862 /**
2863  *  ixgbe_pfc_enable_generic - Enable flow control
2864  *  @hw: pointer to hardware structure
2865  *  @tc_num: traffic class number
2866  *  Enable flow control according to the current settings.
2867  */
2868 static int
2869 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2870 {
2871         int ret_val = 0;
2872         uint32_t mflcn_reg, fccfg_reg;
2873         uint32_t reg;
2874         uint32_t fcrtl, fcrth;
2875         uint8_t i;
2876         uint8_t nb_rx_en;
2877
2878         /* Validate the water mark configuration */
2879         if (!hw->fc.pause_time) {
2880                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2881                 goto out;
2882         }
2883
2884         /* Low water mark of zero causes XOFF floods */
2885         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2886                  /* High/Low water can not be 0 */
2887                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2888                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2889                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2890                         goto out;
2891                 }
2892
2893                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2894                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2895                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2896                         goto out;
2897                 }
2898         }
2899         /* Negotiate the fc mode to use */
2900         ixgbe_fc_autoneg(hw);
2901
2902         /* Disable any previous flow control settings */
2903         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2904         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2905
2906         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2907         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2908
2909         switch (hw->fc.current_mode) {
2910         case ixgbe_fc_none:
2911                 /*
2912                  * If the count of enabled RX Priority Flow control >1,
2913                  * and the TX pause can not be disabled
2914                  */
2915                 nb_rx_en = 0;
2916                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2917                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2918                         if (reg & IXGBE_FCRTH_FCEN)
2919                                 nb_rx_en++;
2920                 }
2921                 if (nb_rx_en > 1)
2922                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2923                 break;
2924         case ixgbe_fc_rx_pause:
2925                 /*
2926                  * Rx Flow control is enabled and Tx Flow control is
2927                  * disabled by software override. Since there really
2928                  * isn't a way to advertise that we are capable of RX
2929                  * Pause ONLY, we will advertise that we support both
2930                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2931                  * disable the adapter's ability to send PAUSE frames.
2932                  */
2933                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2934                 /*
2935                  * If the count of enabled RX Priority Flow control >1,
2936                  * and the TX pause can not be disabled
2937                  */
2938                 nb_rx_en = 0;
2939                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2940                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2941                         if (reg & IXGBE_FCRTH_FCEN)
2942                                 nb_rx_en++;
2943                 }
2944                 if (nb_rx_en > 1)
2945                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2946                 break;
2947         case ixgbe_fc_tx_pause:
2948                 /*
2949                  * Tx Flow control is enabled, and Rx Flow control is
2950                  * disabled by software override.
2951                  */
2952                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2953                 break;
2954         case ixgbe_fc_full:
2955                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2956                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2957                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2958                 break;
2959         default:
2960                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2961                 ret_val = IXGBE_ERR_CONFIG;
2962                 goto out;
2963                 break;
2964         }
2965
2966         /* Set 802.3x based flow control settings. */
2967         mflcn_reg |= IXGBE_MFLCN_DPF;
2968         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2969         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2970
2971         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2972         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2973                 hw->fc.high_water[tc_num]) {
2974                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2975                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2976                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2977         } else {
2978                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2979                 /*
2980                  * In order to prevent Tx hangs when the internal Tx
2981                  * switch is enabled we must set the high water mark
2982                  * to the maximum FCRTH value.  This allows the Tx
2983                  * switch to function even under heavy Rx workloads.
2984                  */
2985                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2986         }
2987         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2988
2989         /* Configure pause time (2 TCs per register) */
2990         reg = hw->fc.pause_time * 0x00010001;
2991         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2992                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2993
2994         /* Configure flow control refresh threshold value */
2995         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2996
2997 out:
2998         return ret_val;
2999 }
3000
3001 static int
3002 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3003 {
3004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3005         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3006
3007         if(hw->mac.type != ixgbe_mac_82598EB) {
3008                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3009         }
3010         return ret_val;
3011 }
3012
3013 static int
3014 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3015 {
3016         int err;
3017         uint32_t rx_buf_size;
3018         uint32_t max_high_water;
3019         uint8_t tc_num;
3020         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3021         struct ixgbe_hw *hw =
3022                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3023         struct ixgbe_dcb_config *dcb_config =
3024                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3025
3026         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3027                 ixgbe_fc_none,
3028                 ixgbe_fc_rx_pause,
3029                 ixgbe_fc_tx_pause,
3030                 ixgbe_fc_full
3031         };
3032
3033         PMD_INIT_FUNC_TRACE();
3034
3035         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3036         tc_num = map[pfc_conf->priority];
3037         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3038         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3039         /*
3040          * At least reserve one Ethernet frame for watermark
3041          * high_water/low_water in kilo bytes for ixgbe
3042          */
3043         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3044         if ((pfc_conf->fc.high_water > max_high_water) ||
3045             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3046                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3047                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3048                 return (-EINVAL);
3049         }
3050
3051         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3052         hw->fc.pause_time = pfc_conf->fc.pause_time;
3053         hw->fc.send_xon = pfc_conf->fc.send_xon;
3054         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3055         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3056
3057         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3058
3059         /* Not negotiated is not an error case */
3060         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3061                 return 0;
3062
3063         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3064         return -EIO;
3065 }
3066
3067 static int
3068 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3069                           struct rte_eth_rss_reta_entry64 *reta_conf,
3070                           uint16_t reta_size)
3071 {
3072         uint8_t i, j, mask;
3073         uint32_t reta, r;
3074         uint16_t idx, shift;
3075         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076
3077         PMD_INIT_FUNC_TRACE();
3078         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3079                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3080                         "(%d) doesn't match the number hardware can supported "
3081                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3082                 return -EINVAL;
3083         }
3084
3085         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3086                 idx = i / RTE_RETA_GROUP_SIZE;
3087                 shift = i % RTE_RETA_GROUP_SIZE;
3088                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3089                                                 IXGBE_4_BIT_MASK);
3090                 if (!mask)
3091                         continue;
3092                 if (mask == IXGBE_4_BIT_MASK)
3093                         r = 0;
3094                 else
3095                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
3096                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3097                         if (mask & (0x1 << j))
3098                                 reta |= reta_conf[idx].reta[shift + j] <<
3099                                                         (CHAR_BIT * j);
3100                         else
3101                                 reta |= r & (IXGBE_8_BIT_MASK <<
3102                                                 (CHAR_BIT * j));
3103                 }
3104                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3105         }
3106
3107         return 0;
3108 }
3109
3110 static int
3111 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3112                          struct rte_eth_rss_reta_entry64 *reta_conf,
3113                          uint16_t reta_size)
3114 {
3115         uint8_t i, j, mask;
3116         uint32_t reta;
3117         uint16_t idx, shift;
3118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3119
3120         PMD_INIT_FUNC_TRACE();
3121         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3122                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3123                         "(%d) doesn't match the number hardware can supported "
3124                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3125                 return -EINVAL;
3126         }
3127
3128         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
3129                 idx = i / RTE_RETA_GROUP_SIZE;
3130                 shift = i % RTE_RETA_GROUP_SIZE;
3131                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3132                                                 IXGBE_4_BIT_MASK);
3133                 if (!mask)
3134                         continue;
3135
3136                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
3137                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3138                         if (mask & (0x1 << j))
3139                                 reta_conf[idx].reta[shift + j] =
3140                                         ((reta >> (CHAR_BIT * j)) &
3141                                                 IXGBE_8_BIT_MASK);
3142                 }
3143         }
3144
3145         return 0;
3146 }
3147
3148 static void
3149 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3150                                 uint32_t index, uint32_t pool)
3151 {
3152         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3153         uint32_t enable_addr = 1;
3154
3155         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3156 }
3157
3158 static void
3159 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3160 {
3161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3162
3163         ixgbe_clear_rar(hw, index);
3164 }
3165
3166 static void
3167 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3168 {
3169         ixgbe_remove_rar(dev, 0);
3170
3171         ixgbe_add_rar(dev, addr, 0, 0);
3172 }
3173
3174 static int
3175 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3176 {
3177         uint32_t hlreg0;
3178         uint32_t maxfrs;
3179         struct ixgbe_hw *hw;
3180         struct rte_eth_dev_info dev_info;
3181         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3182
3183         ixgbe_dev_info_get(dev, &dev_info);
3184
3185         /* check that mtu is within the allowed range */
3186         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3187                 return -EINVAL;
3188
3189         /* refuse mtu that requires the support of scattered packets when this
3190          * feature has not been enabled before. */
3191         if (!dev->data->scattered_rx &&
3192             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3193              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3194                 return -EINVAL;
3195
3196         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3197         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3198
3199         /* switch to jumbo mode if needed */
3200         if (frame_size > ETHER_MAX_LEN) {
3201                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3202                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3203         } else {
3204                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3205                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3206         }
3207         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3208
3209         /* update max frame size */
3210         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3211
3212         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3213         maxfrs &= 0x0000FFFF;
3214         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3215         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3216
3217         return 0;
3218 }
3219
3220 /*
3221  * Virtual Function operations
3222  */
3223 static void
3224 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3225 {
3226         PMD_INIT_FUNC_TRACE();
3227
3228         /* Clear interrupt mask to stop from interrupts being generated */
3229         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3230
3231         IXGBE_WRITE_FLUSH(hw);
3232 }
3233
3234 static int
3235 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3236 {
3237         struct rte_eth_conf* conf = &dev->data->dev_conf;
3238         struct ixgbe_adapter *adapter =
3239                         (struct ixgbe_adapter *)dev->data->dev_private;
3240
3241         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3242                      dev->data->port_id);
3243
3244         /*
3245          * VF has no ability to enable/disable HW CRC
3246          * Keep the persistent behavior the same as Host PF
3247          */
3248 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3249         if (!conf->rxmode.hw_strip_crc) {
3250                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
3251                 conf->rxmode.hw_strip_crc = 1;
3252         }
3253 #else
3254         if (conf->rxmode.hw_strip_crc) {
3255                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
3256                 conf->rxmode.hw_strip_crc = 0;
3257         }
3258 #endif
3259
3260         /*
3261          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3262          * allocation or vector Rx preconditions we will reset it.
3263          */
3264         adapter->rx_bulk_alloc_allowed = true;
3265         adapter->rx_vec_allowed = true;
3266
3267         return 0;
3268 }
3269
3270 static int
3271 ixgbevf_dev_start(struct rte_eth_dev *dev)
3272 {
3273         struct ixgbe_hw *hw =
3274                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3275         int err, mask = 0;
3276
3277         PMD_INIT_FUNC_TRACE();
3278
3279         hw->mac.ops.reset_hw(hw);
3280         hw->mac.get_link_status = true;
3281
3282         /* negotiate mailbox API version to use with the PF. */
3283         ixgbevf_negotiate_api(hw);
3284
3285         ixgbevf_dev_tx_init(dev);
3286
3287         /* This can fail when allocating mbufs for descriptor rings */
3288         err = ixgbevf_dev_rx_init(dev);
3289         if (err) {
3290                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3291                 ixgbe_dev_clear_queues(dev);
3292                 return err;
3293         }
3294
3295         /* Set vfta */
3296         ixgbevf_set_vfta_all(dev,1);
3297
3298         /* Set HW strip */
3299         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3300                 ETH_VLAN_EXTEND_MASK;
3301         ixgbevf_vlan_offload_set(dev, mask);
3302
3303         ixgbevf_dev_rxtx_start(dev);
3304
3305         return 0;
3306 }
3307
3308 static void
3309 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3310 {
3311         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312
3313         PMD_INIT_FUNC_TRACE();
3314
3315         hw->adapter_stopped = 1;
3316         ixgbe_stop_adapter(hw);
3317
3318         /*
3319           * Clear what we set, but we still keep shadow_vfta to
3320           * restore after device starts
3321           */
3322         ixgbevf_set_vfta_all(dev,0);
3323
3324         /* Clear stored conf */
3325         dev->data->scattered_rx = 0;
3326
3327         ixgbe_dev_clear_queues(dev);
3328 }
3329
3330 static void
3331 ixgbevf_dev_close(struct rte_eth_dev *dev)
3332 {
3333         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3334
3335         PMD_INIT_FUNC_TRACE();
3336
3337         ixgbe_reset_hw(hw);
3338
3339         ixgbevf_dev_stop(dev);
3340
3341         /* reprogram the RAR[0] in case user changed it. */
3342         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3343 }
3344
3345 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3346 {
3347         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3348         struct ixgbe_vfta * shadow_vfta =
3349                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3350         int i = 0, j = 0, vfta = 0, mask = 1;
3351
3352         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3353                 vfta = shadow_vfta->vfta[i];
3354                 if(vfta){
3355                         mask = 1;
3356                         for (j = 0; j < 32; j++){
3357                                 if(vfta & mask)
3358                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3359                                 mask<<=1;
3360                         }
3361                 }
3362         }
3363
3364 }
3365
3366 static int
3367 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3368 {
3369         struct ixgbe_hw *hw =
3370                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3371         struct ixgbe_vfta * shadow_vfta =
3372                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3373         uint32_t vid_idx = 0;
3374         uint32_t vid_bit = 0;
3375         int ret = 0;
3376
3377         PMD_INIT_FUNC_TRACE();
3378
3379         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3380         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3381         if(ret){
3382                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3383                 return ret;
3384         }
3385         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3386         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3387
3388         /* Save what we set and retore it after device reset */
3389         if (on)
3390                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3391         else
3392                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3393
3394         return 0;
3395 }
3396
3397 static void
3398 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3399 {
3400         struct ixgbe_hw *hw =
3401                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3402         uint32_t ctrl;
3403
3404         PMD_INIT_FUNC_TRACE();
3405
3406         if(queue >= hw->mac.max_rx_queues)
3407                 return;
3408
3409         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3410         if(on)
3411                 ctrl |= IXGBE_RXDCTL_VME;
3412         else
3413                 ctrl &= ~IXGBE_RXDCTL_VME;
3414         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3415
3416         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3417 }
3418
3419 static void
3420 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3421 {
3422         struct ixgbe_hw *hw =
3423                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3424         uint16_t i;
3425         int on = 0;
3426
3427         /* VF function only support hw strip feature, others are not support */
3428         if(mask & ETH_VLAN_STRIP_MASK){
3429                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3430
3431                 for(i=0; i < hw->mac.max_rx_queues; i++)
3432                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3433         }
3434 }
3435
3436 static int
3437 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3438 {
3439         uint32_t reg_val;
3440
3441         /* we only need to do this if VMDq is enabled */
3442         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3443         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3444                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3445                 return (-1);
3446         }
3447
3448         return 0;
3449 }
3450
3451 static uint32_t
3452 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3453 {
3454         uint32_t vector = 0;
3455         switch (hw->mac.mc_filter_type) {
3456         case 0:   /* use bits [47:36] of the address */
3457                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3458                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3459                 break;
3460         case 1:   /* use bits [46:35] of the address */
3461                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3462                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3463                 break;
3464         case 2:   /* use bits [45:34] of the address */
3465                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3466                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3467                 break;
3468         case 3:   /* use bits [43:32] of the address */
3469                 vector = ((uc_addr->addr_bytes[4]) |
3470                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3471                 break;
3472         default:  /* Invalid mc_filter_type */
3473                 break;
3474         }
3475
3476         /* vector can only be 12-bits or boundary will be exceeded */
3477         vector &= 0xFFF;
3478         return vector;
3479 }
3480
3481 static int
3482 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3483                                uint8_t on)
3484 {
3485         uint32_t vector;
3486         uint32_t uta_idx;
3487         uint32_t reg_val;
3488         uint32_t uta_shift;
3489         uint32_t rc;
3490         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3491         const uint32_t ixgbe_uta_bit_shift = 5;
3492         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3493         const uint32_t bit1 = 0x1;
3494
3495         struct ixgbe_hw *hw =
3496                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3497         struct ixgbe_uta_info *uta_info =
3498                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3499
3500         /* The UTA table only exists on 82599 hardware and newer */
3501         if (hw->mac.type < ixgbe_mac_82599EB)
3502                 return (-ENOTSUP);
3503
3504         vector = ixgbe_uta_vector(hw,mac_addr);
3505         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3506         uta_shift = vector & ixgbe_uta_bit_mask;
3507
3508         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3509         if(rc == on)
3510                 return 0;
3511
3512         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3513         if (on) {
3514                 uta_info->uta_in_use++;
3515                 reg_val |= (bit1 << uta_shift);
3516                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3517         } else {
3518                 uta_info->uta_in_use--;
3519                 reg_val &= ~(bit1 << uta_shift);
3520                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3521         }
3522
3523         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3524
3525         if (uta_info->uta_in_use > 0)
3526                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3527                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3528         else
3529                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3530
3531         return 0;
3532 }
3533
3534 static int
3535 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3536 {
3537         int i;
3538         struct ixgbe_hw *hw =
3539                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3540         struct ixgbe_uta_info *uta_info =
3541                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3542
3543         /* The UTA table only exists on 82599 hardware and newer */
3544         if (hw->mac.type < ixgbe_mac_82599EB)
3545                 return (-ENOTSUP);
3546
3547         if(on) {
3548                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3549                         uta_info->uta_shadow[i] = ~0;
3550                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3551                 }
3552         } else {
3553                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3554                         uta_info->uta_shadow[i] = 0;
3555                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3556                 }
3557         }
3558         return 0;
3559
3560 }
3561
3562 uint32_t
3563 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3564 {
3565         uint32_t new_val = orig_val;
3566
3567         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3568                 new_val |= IXGBE_VMOLR_AUPE;
3569         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3570                 new_val |= IXGBE_VMOLR_ROMPE;
3571         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3572                 new_val |= IXGBE_VMOLR_ROPE;
3573         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3574                 new_val |= IXGBE_VMOLR_BAM;
3575         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3576                 new_val |= IXGBE_VMOLR_MPE;
3577
3578         return new_val;
3579 }
3580
3581 static int
3582 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3583                                uint16_t rx_mask, uint8_t on)
3584 {
3585         int val = 0;
3586
3587         struct ixgbe_hw *hw =
3588                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3589         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3590
3591         if (hw->mac.type == ixgbe_mac_82598EB) {
3592                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3593                              " on 82599 hardware and newer");
3594                 return (-ENOTSUP);
3595         }
3596         if (ixgbe_vmdq_mode_check(hw) < 0)
3597                 return (-ENOTSUP);
3598
3599         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3600
3601         if (on)
3602                 vmolr |= val;
3603         else
3604                 vmolr &= ~val;
3605
3606         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3607
3608         return 0;
3609 }
3610
3611 static int
3612 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3613 {
3614         uint32_t reg,addr;
3615         uint32_t val;
3616         const uint8_t bit1 = 0x1;
3617
3618         struct ixgbe_hw *hw =
3619                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3620
3621         if (ixgbe_vmdq_mode_check(hw) < 0)
3622                 return (-ENOTSUP);
3623
3624         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3625         reg = IXGBE_READ_REG(hw, addr);
3626         val = bit1 << pool;
3627
3628         if (on)
3629                 reg |= val;
3630         else
3631                 reg &= ~val;
3632
3633         IXGBE_WRITE_REG(hw, addr,reg);
3634
3635         return 0;
3636 }
3637
3638 static int
3639 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3640 {
3641         uint32_t reg,addr;
3642         uint32_t val;
3643         const uint8_t bit1 = 0x1;
3644
3645         struct ixgbe_hw *hw =
3646                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3647
3648         if (ixgbe_vmdq_mode_check(hw) < 0)
3649                 return (-ENOTSUP);
3650
3651         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3652         reg = IXGBE_READ_REG(hw, addr);
3653         val = bit1 << pool;
3654
3655         if (on)
3656                 reg |= val;
3657         else
3658                 reg &= ~val;
3659
3660         IXGBE_WRITE_REG(hw, addr,reg);
3661
3662         return 0;
3663 }
3664
3665 static int
3666 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3667                         uint64_t pool_mask, uint8_t vlan_on)
3668 {
3669         int ret = 0;
3670         uint16_t pool_idx;
3671         struct ixgbe_hw *hw =
3672                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3673
3674         if (ixgbe_vmdq_mode_check(hw) < 0)
3675                 return (-ENOTSUP);
3676         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3677                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3678                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3679                         if (ret < 0)
3680                                 return ret;
3681         }
3682
3683         return ret;
3684 }
3685
3686 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
3687 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
3688 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
3689 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
3690 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
3691         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
3692         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
3693
3694 static int
3695 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3696                         struct rte_eth_mirror_conf *mirror_conf,
3697                         uint8_t rule_id, uint8_t on)
3698 {
3699         uint32_t mr_ctl,vlvf;
3700         uint32_t mp_lsb = 0;
3701         uint32_t mv_msb = 0;
3702         uint32_t mv_lsb = 0;
3703         uint32_t mp_msb = 0;
3704         uint8_t i = 0;
3705         int reg_index = 0;
3706         uint64_t vlan_mask = 0;
3707
3708         const uint8_t pool_mask_offset = 32;
3709         const uint8_t vlan_mask_offset = 32;
3710         const uint8_t dst_pool_offset = 8;
3711         const uint8_t rule_mr_offset  = 4;
3712         const uint8_t mirror_rule_mask= 0x0F;
3713
3714         struct ixgbe_mirror_info *mr_info =
3715                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3716         struct ixgbe_hw *hw =
3717                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3718         uint8_t mirror_type = 0;
3719
3720         if (ixgbe_vmdq_mode_check(hw) < 0)
3721                 return -ENOTSUP;
3722
3723         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3724                 return -EINVAL;
3725
3726         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
3727                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
3728                         mirror_conf->rule_type);
3729                 return -EINVAL;
3730         }
3731
3732         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
3733                 mirror_type |= IXGBE_MRCTL_VLME;
3734                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3735                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3736                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3737                                 /* search vlan id related pool vlan filter index */
3738                                 reg_index = ixgbe_find_vlvf_slot(hw,
3739                                                 mirror_conf->vlan.vlan_id[i]);
3740                                 if(reg_index < 0)
3741                                         return -EINVAL;
3742                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3743                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3744                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
3745                                       mirror_conf->vlan.vlan_id[i]))
3746                                         vlan_mask |= (1ULL << reg_index);
3747                                 else
3748                                         return -EINVAL;
3749                         }
3750                 }
3751
3752                 if (on) {
3753                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3754                         mv_msb = vlan_mask >> vlan_mask_offset;
3755
3756                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3757                                                 mirror_conf->vlan.vlan_mask;
3758                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3759                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3760                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3761                                                 mirror_conf->vlan.vlan_id[i];
3762                         }
3763                 } else {
3764                         mv_lsb = 0;
3765                         mv_msb = 0;
3766                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3767                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3768                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3769                 }
3770         }
3771
3772         /*
3773          * if enable pool mirror, write related pool mask register,if disable
3774          * pool mirror, clear PFMRVM register
3775          */
3776         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
3777                 mirror_type |= IXGBE_MRCTL_VPME;
3778                 if (on) {
3779                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3780                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3781                         mr_info->mr_conf[rule_id].pool_mask =
3782                                         mirror_conf->pool_mask;
3783
3784                 } else {
3785                         mp_lsb = 0;
3786                         mp_msb = 0;
3787                         mr_info->mr_conf[rule_id].pool_mask = 0;
3788                 }
3789         }
3790         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
3791                 mirror_type |= IXGBE_MRCTL_UPME;
3792         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
3793                 mirror_type |= IXGBE_MRCTL_DPME;
3794
3795         /* read  mirror control register and recalculate it */
3796         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
3797
3798         if (on) {
3799                 mr_ctl |= mirror_type;
3800                 mr_ctl &= mirror_rule_mask;
3801                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3802         } else
3803                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
3804
3805         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
3806         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3807
3808         /* write mirrror control  register */
3809         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3810
3811         /* write pool mirrror control  register */
3812         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
3813                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3814                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3815                                 mp_msb);
3816         }
3817         /* write VLAN mirrror control  register */
3818         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
3819                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3820                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3821                                 mv_msb);
3822         }
3823
3824         return 0;
3825 }
3826
3827 static int
3828 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3829 {
3830         int mr_ctl = 0;
3831         uint32_t lsb_val = 0;
3832         uint32_t msb_val = 0;
3833         const uint8_t rule_mr_offset = 4;
3834
3835         struct ixgbe_hw *hw =
3836                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3837         struct ixgbe_mirror_info *mr_info =
3838                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3839
3840         if (ixgbe_vmdq_mode_check(hw) < 0)
3841                 return (-ENOTSUP);
3842
3843         memset(&mr_info->mr_conf[rule_id], 0,
3844                 sizeof(struct rte_eth_mirror_conf));
3845
3846         /* clear PFVMCTL register */
3847         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3848
3849         /* clear pool mask register */
3850         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3851         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3852
3853         /* clear vlan mask register */
3854         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3855         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3856
3857         return 0;
3858 }
3859
3860 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3861         uint16_t queue_idx, uint16_t tx_rate)
3862 {
3863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3864         uint32_t rf_dec, rf_int;
3865         uint32_t bcnrc_val;
3866         uint16_t link_speed = dev->data->dev_link.link_speed;
3867
3868         if (queue_idx >= hw->mac.max_tx_queues)
3869                 return -EINVAL;
3870
3871         if (tx_rate != 0) {
3872                 /* Calculate the rate factor values to set */
3873                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3874                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3875                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3876
3877                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3878                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3879                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3880                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3881         } else {
3882                 bcnrc_val = 0;
3883         }
3884
3885         /*
3886          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3887          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3888          * set as 0x4.
3889          */
3890         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3891                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3892                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3893                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3894                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3895         else
3896                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3897                         IXGBE_MMW_SIZE_DEFAULT);
3898
3899         /* Set RTTBCNRC of queue X */
3900         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3901         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3902         IXGBE_WRITE_FLUSH(hw);
3903
3904         return 0;
3905 }
3906
3907 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3908         uint16_t tx_rate, uint64_t q_msk)
3909 {
3910         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3911         struct ixgbe_vf_info *vfinfo =
3912                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3913         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3914         uint32_t queue_stride =
3915                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3916         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3917         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3918         uint16_t total_rate = 0;
3919
3920         if (queue_end >= hw->mac.max_tx_queues)
3921                 return -EINVAL;
3922
3923         if (vfinfo != NULL) {
3924                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3925                         if (vf_idx == vf)
3926                                 continue;
3927                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3928                                 idx++)
3929                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3930                 }
3931         } else
3932                 return -EINVAL;
3933
3934         /* Store tx_rate for this vf. */
3935         for (idx = 0; idx < nb_q_per_pool; idx++) {
3936                 if (((uint64_t)0x1 << idx) & q_msk) {
3937                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3938                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3939                         total_rate += tx_rate;
3940                 }
3941         }
3942
3943         if (total_rate > dev->data->dev_link.link_speed) {
3944                 /*
3945                  * Reset stored TX rate of the VF if it causes exceed
3946                  * link speed.
3947                  */
3948                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3949                 return -EINVAL;
3950         }
3951
3952         /* Set RTTBCNRC of each queue/pool for vf X  */
3953         for (; queue_idx <= queue_end; queue_idx++) {
3954                 if (0x1 & q_msk)
3955                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3956                 q_msk = q_msk >> 1;
3957         }
3958
3959         return 0;
3960 }
3961
3962 static void
3963 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3964                      __attribute__((unused)) uint32_t index,
3965                      __attribute__((unused)) uint32_t pool)
3966 {
3967         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3968         int diag;
3969
3970         /*
3971          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3972          * operation. Trap this case to avoid exhausting the [very limited]
3973          * set of PF resources used to store VF MAC addresses.
3974          */
3975         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3976                 return;
3977         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3978         if (diag == 0)
3979                 return;
3980         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3981 }
3982
3983 static void
3984 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3985 {
3986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3987         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3988         struct ether_addr *mac_addr;
3989         uint32_t i;
3990         int diag;
3991
3992         /*
3993          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3994          * not support the deletion of a given MAC address.
3995          * Instead, it imposes to delete all MAC addresses, then to add again
3996          * all MAC addresses with the exception of the one to be deleted.
3997          */
3998         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3999
4000         /*
4001          * Add again all MAC addresses, with the exception of the deleted one
4002          * and of the permanent MAC address.
4003          */
4004         for (i = 0, mac_addr = dev->data->mac_addrs;
4005              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4006                 /* Skip the deleted MAC address */
4007                 if (i == index)
4008                         continue;
4009                 /* Skip NULL MAC addresses */
4010                 if (is_zero_ether_addr(mac_addr))
4011                         continue;
4012                 /* Skip the permanent MAC address */
4013                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4014                         continue;
4015                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4016                 if (diag != 0)
4017                         PMD_DRV_LOG(ERR,
4018                                     "Adding again MAC address "
4019                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4020                                     "diag=%d",
4021                                     mac_addr->addr_bytes[0],
4022                                     mac_addr->addr_bytes[1],
4023                                     mac_addr->addr_bytes[2],
4024                                     mac_addr->addr_bytes[3],
4025                                     mac_addr->addr_bytes[4],
4026                                     mac_addr->addr_bytes[5],
4027                                     diag);
4028         }
4029 }
4030
4031 static void
4032 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4033 {
4034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4035
4036         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4037 }
4038
4039 #define MAC_TYPE_FILTER_SUP(type)    do {\
4040         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4041                 (type) != ixgbe_mac_X550)\
4042                 return -ENOTSUP;\
4043 } while (0)
4044
4045 static int
4046 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4047                         struct rte_eth_syn_filter *filter,
4048                         bool add)
4049 {
4050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4051         uint32_t synqf;
4052
4053         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4054                 return -EINVAL;
4055
4056         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4057
4058         if (add) {
4059                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4060                         return -EINVAL;
4061                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4062                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4063
4064                 if (filter->hig_pri)
4065                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4066                 else
4067                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4068         } else {
4069                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4070                         return -ENOENT;
4071                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4072         }
4073         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4074         IXGBE_WRITE_FLUSH(hw);
4075         return 0;
4076 }
4077
4078 static int
4079 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4080                         struct rte_eth_syn_filter *filter)
4081 {
4082         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4083         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4084
4085         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4086                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4087                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4088                 return 0;
4089         }
4090         return -ENOENT;
4091 }
4092
4093 static int
4094 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4095                         enum rte_filter_op filter_op,
4096                         void *arg)
4097 {
4098         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4099         int ret;
4100
4101         MAC_TYPE_FILTER_SUP(hw->mac.type);
4102
4103         if (filter_op == RTE_ETH_FILTER_NOP)
4104                 return 0;
4105
4106         if (arg == NULL) {
4107                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4108                             filter_op);
4109                 return -EINVAL;
4110         }
4111
4112         switch (filter_op) {
4113         case RTE_ETH_FILTER_ADD:
4114                 ret = ixgbe_syn_filter_set(dev,
4115                                 (struct rte_eth_syn_filter *)arg,
4116                                 TRUE);
4117                 break;
4118         case RTE_ETH_FILTER_DELETE:
4119                 ret = ixgbe_syn_filter_set(dev,
4120                                 (struct rte_eth_syn_filter *)arg,
4121                                 FALSE);
4122                 break;
4123         case RTE_ETH_FILTER_GET:
4124                 ret = ixgbe_syn_filter_get(dev,
4125                                 (struct rte_eth_syn_filter *)arg);
4126                 break;
4127         default:
4128                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4129                 ret = -EINVAL;
4130                 break;
4131         }
4132
4133         return ret;
4134 }
4135
4136
4137 static inline enum ixgbe_5tuple_protocol
4138 convert_protocol_type(uint8_t protocol_value)
4139 {
4140         if (protocol_value == IPPROTO_TCP)
4141                 return IXGBE_FILTER_PROTOCOL_TCP;
4142         else if (protocol_value == IPPROTO_UDP)
4143                 return IXGBE_FILTER_PROTOCOL_UDP;
4144         else if (protocol_value == IPPROTO_SCTP)
4145                 return IXGBE_FILTER_PROTOCOL_SCTP;
4146         else
4147                 return IXGBE_FILTER_PROTOCOL_NONE;
4148 }
4149
4150 /*
4151  * add a 5tuple filter
4152  *
4153  * @param
4154  * dev: Pointer to struct rte_eth_dev.
4155  * index: the index the filter allocates.
4156  * filter: ponter to the filter that will be added.
4157  * rx_queue: the queue id the filter assigned to.
4158  *
4159  * @return
4160  *    - On success, zero.
4161  *    - On failure, a negative value.
4162  */
4163 static int
4164 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4165                         struct ixgbe_5tuple_filter *filter)
4166 {
4167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4168         struct ixgbe_filter_info *filter_info =
4169                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4170         int i, idx, shift;
4171         uint32_t ftqf, sdpqf;
4172         uint32_t l34timir = 0;
4173         uint8_t mask = 0xff;
4174
4175         /*
4176          * look for an unused 5tuple filter index,
4177          * and insert the filter to list.
4178          */
4179         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
4180                 idx = i / (sizeof(uint32_t) * NBBY);
4181                 shift = i % (sizeof(uint32_t) * NBBY);
4182                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
4183                         filter_info->fivetuple_mask[idx] |= 1 << shift;
4184                         filter->index = i;
4185                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4186                                           filter,
4187                                           entries);
4188                         break;
4189                 }
4190         }
4191         if (i >= IXGBE_MAX_FTQF_FILTERS) {
4192                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4193                 return -ENOSYS;
4194         }
4195
4196         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
4197                                 IXGBE_SDPQF_DSTPORT_SHIFT);
4198         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
4199
4200         ftqf = (uint32_t)(filter->filter_info.proto &
4201                 IXGBE_FTQF_PROTOCOL_MASK);
4202         ftqf |= (uint32_t)((filter->filter_info.priority &
4203                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
4204         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
4205                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
4206         if (filter->filter_info.dst_ip_mask == 0)
4207                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
4208         if (filter->filter_info.src_port_mask == 0)
4209                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
4210         if (filter->filter_info.dst_port_mask == 0)
4211                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
4212         if (filter->filter_info.proto_mask == 0)
4213                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
4214         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
4215         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
4216         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
4217
4218         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
4219         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
4220         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
4221         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
4222
4223         l34timir |= IXGBE_L34T_IMIR_RESERVE;
4224         l34timir |= (uint32_t)(filter->queue <<
4225                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
4226         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
4227         return 0;
4228 }
4229
4230 /*
4231  * remove a 5tuple filter
4232  *
4233  * @param
4234  * dev: Pointer to struct rte_eth_dev.
4235  * filter: the pointer of the filter will be removed.
4236  */
4237 static void
4238 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
4239                         struct ixgbe_5tuple_filter *filter)
4240 {
4241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4242         struct ixgbe_filter_info *filter_info =
4243                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4244         uint16_t index = filter->index;
4245
4246         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
4247                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
4248         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4249         rte_free(filter);
4250
4251         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4252         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4253         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4254         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4255         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4256 }
4257
4258 static int
4259 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4260 {
4261         struct ixgbe_hw *hw;
4262         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4263
4264         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4265
4266         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4267                 return -EINVAL;
4268
4269         /* refuse mtu that requires the support of scattered packets when this
4270          * feature has not been enabled before. */
4271         if (!dev->data->scattered_rx &&
4272             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4273              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4274                 return -EINVAL;
4275
4276         /*
4277          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4278          * request of the version 2.0 of the mailbox API.
4279          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4280          * of the mailbox API.
4281          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4282          * prior to 3.11.33 which contains the following change:
4283          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4284          */
4285         ixgbevf_rlpml_set_vf(hw, max_frame);
4286
4287         /* update max frame size */
4288         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4289         return 0;
4290 }
4291
4292 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
4293         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4294                 return -ENOTSUP;\
4295 } while (0)
4296
4297 static inline struct ixgbe_5tuple_filter *
4298 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4299                         struct ixgbe_5tuple_filter_info *key)
4300 {
4301         struct ixgbe_5tuple_filter *it;
4302
4303         TAILQ_FOREACH(it, filter_list, entries) {
4304                 if (memcmp(key, &it->filter_info,
4305                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4306                         return it;
4307                 }
4308         }
4309         return NULL;
4310 }
4311
4312 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4313 static inline int
4314 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4315                         struct ixgbe_5tuple_filter_info *filter_info)
4316 {
4317         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4318                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4319                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4320                 return -EINVAL;
4321
4322         switch (filter->dst_ip_mask) {
4323         case UINT32_MAX:
4324                 filter_info->dst_ip_mask = 0;
4325                 filter_info->dst_ip = filter->dst_ip;
4326                 break;
4327         case 0:
4328                 filter_info->dst_ip_mask = 1;
4329                 break;
4330         default:
4331                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4332                 return -EINVAL;
4333         }
4334
4335         switch (filter->src_ip_mask) {
4336         case UINT32_MAX:
4337                 filter_info->src_ip_mask = 0;
4338                 filter_info->src_ip = filter->src_ip;
4339                 break;
4340         case 0:
4341                 filter_info->src_ip_mask = 1;
4342                 break;
4343         default:
4344                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4345                 return -EINVAL;
4346         }
4347
4348         switch (filter->dst_port_mask) {
4349         case UINT16_MAX:
4350                 filter_info->dst_port_mask = 0;
4351                 filter_info->dst_port = filter->dst_port;
4352                 break;
4353         case 0:
4354                 filter_info->dst_port_mask = 1;
4355                 break;
4356         default:
4357                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4358                 return -EINVAL;
4359         }
4360
4361         switch (filter->src_port_mask) {
4362         case UINT16_MAX:
4363                 filter_info->src_port_mask = 0;
4364                 filter_info->src_port = filter->src_port;
4365                 break;
4366         case 0:
4367                 filter_info->src_port_mask = 1;
4368                 break;
4369         default:
4370                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4371                 return -EINVAL;
4372         }
4373
4374         switch (filter->proto_mask) {
4375         case UINT8_MAX:
4376                 filter_info->proto_mask = 0;
4377                 filter_info->proto =
4378                         convert_protocol_type(filter->proto);
4379                 break;
4380         case 0:
4381                 filter_info->proto_mask = 1;
4382                 break;
4383         default:
4384                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4385                 return -EINVAL;
4386         }
4387
4388         filter_info->priority = (uint8_t)filter->priority;
4389         return 0;
4390 }
4391
4392 /*
4393  * add or delete a ntuple filter
4394  *
4395  * @param
4396  * dev: Pointer to struct rte_eth_dev.
4397  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4398  * add: if true, add filter, if false, remove filter
4399  *
4400  * @return
4401  *    - On success, zero.
4402  *    - On failure, a negative value.
4403  */
4404 static int
4405 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4406                         struct rte_eth_ntuple_filter *ntuple_filter,
4407                         bool add)
4408 {
4409         struct ixgbe_filter_info *filter_info =
4410                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4411         struct ixgbe_5tuple_filter_info filter_5tuple;
4412         struct ixgbe_5tuple_filter *filter;
4413         int ret;
4414
4415         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4416                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4417                 return -EINVAL;
4418         }
4419
4420         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4421         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4422         if (ret < 0)
4423                 return ret;
4424
4425         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4426                                          &filter_5tuple);
4427         if (filter != NULL && add) {
4428                 PMD_DRV_LOG(ERR, "filter exists.");
4429                 return -EEXIST;
4430         }
4431         if (filter == NULL && !add) {
4432                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4433                 return -ENOENT;
4434         }
4435
4436         if (add) {
4437                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4438                                 sizeof(struct ixgbe_5tuple_filter), 0);
4439                 if (filter == NULL)
4440                         return -ENOMEM;
4441                 (void)rte_memcpy(&filter->filter_info,
4442                                  &filter_5tuple,
4443                                  sizeof(struct ixgbe_5tuple_filter_info));
4444                 filter->queue = ntuple_filter->queue;
4445                 ret = ixgbe_add_5tuple_filter(dev, filter);
4446                 if (ret < 0) {
4447                         rte_free(filter);
4448                         return ret;
4449                 }
4450         } else
4451                 ixgbe_remove_5tuple_filter(dev, filter);
4452
4453         return 0;
4454 }
4455
4456 /*
4457  * get a ntuple filter
4458  *
4459  * @param
4460  * dev: Pointer to struct rte_eth_dev.
4461  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4462  *
4463  * @return
4464  *    - On success, zero.
4465  *    - On failure, a negative value.
4466  */
4467 static int
4468 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4469                         struct rte_eth_ntuple_filter *ntuple_filter)
4470 {
4471         struct ixgbe_filter_info *filter_info =
4472                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4473         struct ixgbe_5tuple_filter_info filter_5tuple;
4474         struct ixgbe_5tuple_filter *filter;
4475         int ret;
4476
4477         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4478                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4479                 return -EINVAL;
4480         }
4481
4482         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4483         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4484         if (ret < 0)
4485                 return ret;
4486
4487         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4488                                          &filter_5tuple);
4489         if (filter == NULL) {
4490                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4491                 return -ENOENT;
4492         }
4493         ntuple_filter->queue = filter->queue;
4494         return 0;
4495 }
4496
4497 /*
4498  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4499  * @dev: pointer to rte_eth_dev structure
4500  * @filter_op:operation will be taken.
4501  * @arg: a pointer to specific structure corresponding to the filter_op
4502  *
4503  * @return
4504  *    - On success, zero.
4505  *    - On failure, a negative value.
4506  */
4507 static int
4508 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4509                                 enum rte_filter_op filter_op,
4510                                 void *arg)
4511 {
4512         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4513         int ret;
4514
4515         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4516
4517         if (filter_op == RTE_ETH_FILTER_NOP)
4518                 return 0;
4519
4520         if (arg == NULL) {
4521                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4522                             filter_op);
4523                 return -EINVAL;
4524         }
4525
4526         switch (filter_op) {
4527         case RTE_ETH_FILTER_ADD:
4528                 ret = ixgbe_add_del_ntuple_filter(dev,
4529                         (struct rte_eth_ntuple_filter *)arg,
4530                         TRUE);
4531                 break;
4532         case RTE_ETH_FILTER_DELETE:
4533                 ret = ixgbe_add_del_ntuple_filter(dev,
4534                         (struct rte_eth_ntuple_filter *)arg,
4535                         FALSE);
4536                 break;
4537         case RTE_ETH_FILTER_GET:
4538                 ret = ixgbe_get_ntuple_filter(dev,
4539                         (struct rte_eth_ntuple_filter *)arg);
4540                 break;
4541         default:
4542                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4543                 ret = -EINVAL;
4544                 break;
4545         }
4546         return ret;
4547 }
4548
4549 static inline int
4550 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4551                         uint16_t ethertype)
4552 {
4553         int i;
4554
4555         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4556                 if (filter_info->ethertype_filters[i] == ethertype &&
4557                     (filter_info->ethertype_mask & (1 << i)))
4558                         return i;
4559         }
4560         return -1;
4561 }
4562
4563 static inline int
4564 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4565                         uint16_t ethertype)
4566 {
4567         int i;
4568
4569         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4570                 if (!(filter_info->ethertype_mask & (1 << i))) {
4571                         filter_info->ethertype_mask |= 1 << i;
4572                         filter_info->ethertype_filters[i] = ethertype;
4573                         return i;
4574                 }
4575         }
4576         return -1;
4577 }
4578
4579 static inline int
4580 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4581                         uint8_t idx)
4582 {
4583         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4584                 return -1;
4585         filter_info->ethertype_mask &= ~(1 << idx);
4586         filter_info->ethertype_filters[idx] = 0;
4587         return idx;
4588 }
4589
4590 static int
4591 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4592                         struct rte_eth_ethertype_filter *filter,
4593                         bool add)
4594 {
4595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4596         struct ixgbe_filter_info *filter_info =
4597                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4598         uint32_t etqf = 0;
4599         uint32_t etqs = 0;
4600         int ret;
4601
4602         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4603                 return -EINVAL;
4604
4605         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4606                 filter->ether_type == ETHER_TYPE_IPv6) {
4607                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4608                         " ethertype filter.", filter->ether_type);
4609                 return -EINVAL;
4610         }
4611
4612         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4613                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4614                 return -EINVAL;
4615         }
4616         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4617                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4618                 return -EINVAL;
4619         }
4620
4621         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4622         if (ret >= 0 && add) {
4623                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4624                             filter->ether_type);
4625                 return -EEXIST;
4626         }
4627         if (ret < 0 && !add) {
4628                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4629                             filter->ether_type);
4630                 return -ENOENT;
4631         }
4632
4633         if (add) {
4634                 ret = ixgbe_ethertype_filter_insert(filter_info,
4635                         filter->ether_type);
4636                 if (ret < 0) {
4637                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4638                         return -ENOSYS;
4639                 }
4640                 etqf = IXGBE_ETQF_FILTER_EN;
4641                 etqf |= (uint32_t)filter->ether_type;
4642                 etqs |= (uint32_t)((filter->queue <<
4643                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4644                                     IXGBE_ETQS_RX_QUEUE);
4645                 etqs |= IXGBE_ETQS_QUEUE_EN;
4646         } else {
4647                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4648                 if (ret < 0)
4649                         return -ENOSYS;
4650         }
4651         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4652         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4653         IXGBE_WRITE_FLUSH(hw);
4654
4655         return 0;
4656 }
4657
4658 static int
4659 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4660                         struct rte_eth_ethertype_filter *filter)
4661 {
4662         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663         struct ixgbe_filter_info *filter_info =
4664                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4665         uint32_t etqf, etqs;
4666         int ret;
4667
4668         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4669         if (ret < 0) {
4670                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4671                             filter->ether_type);
4672                 return -ENOENT;
4673         }
4674
4675         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4676         if (etqf & IXGBE_ETQF_FILTER_EN) {
4677                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4678                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4679                 filter->flags = 0;
4680                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4681                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4682                 return 0;
4683         }
4684         return -ENOENT;
4685 }
4686
4687 /*
4688  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4689  * @dev: pointer to rte_eth_dev structure
4690  * @filter_op:operation will be taken.
4691  * @arg: a pointer to specific structure corresponding to the filter_op
4692  */
4693 static int
4694 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4695                                 enum rte_filter_op filter_op,
4696                                 void *arg)
4697 {
4698         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4699         int ret;
4700
4701         MAC_TYPE_FILTER_SUP(hw->mac.type);
4702
4703         if (filter_op == RTE_ETH_FILTER_NOP)
4704                 return 0;
4705
4706         if (arg == NULL) {
4707                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4708                             filter_op);
4709                 return -EINVAL;
4710         }
4711
4712         switch (filter_op) {
4713         case RTE_ETH_FILTER_ADD:
4714                 ret = ixgbe_add_del_ethertype_filter(dev,
4715                         (struct rte_eth_ethertype_filter *)arg,
4716                         TRUE);
4717                 break;
4718         case RTE_ETH_FILTER_DELETE:
4719                 ret = ixgbe_add_del_ethertype_filter(dev,
4720                         (struct rte_eth_ethertype_filter *)arg,
4721                         FALSE);
4722                 break;
4723         case RTE_ETH_FILTER_GET:
4724                 ret = ixgbe_get_ethertype_filter(dev,
4725                         (struct rte_eth_ethertype_filter *)arg);
4726                 break;
4727         default:
4728                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4729                 ret = -EINVAL;
4730                 break;
4731         }
4732         return ret;
4733 }
4734
4735 static int
4736 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4737                      enum rte_filter_type filter_type,
4738                      enum rte_filter_op filter_op,
4739                      void *arg)
4740 {
4741         int ret = -EINVAL;
4742
4743         switch (filter_type) {
4744         case RTE_ETH_FILTER_NTUPLE:
4745                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4746                 break;
4747         case RTE_ETH_FILTER_ETHERTYPE:
4748                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4749                 break;
4750         case RTE_ETH_FILTER_SYN:
4751                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4752                 break;
4753         case RTE_ETH_FILTER_FDIR:
4754                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4755                 break;
4756         default:
4757                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4758                                                         filter_type);
4759                 break;
4760         }
4761
4762         return ret;
4763 }
4764
4765 static u8 *
4766 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
4767                         u8 **mc_addr_ptr, u32 *vmdq)
4768 {
4769         u8 *mc_addr;
4770
4771         *vmdq = 0;
4772         mc_addr = *mc_addr_ptr;
4773         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
4774         return mc_addr;
4775 }
4776
4777 static int
4778 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4779                           struct ether_addr *mc_addr_set,
4780                           uint32_t nb_mc_addr)
4781 {
4782         struct ixgbe_hw *hw;
4783         u8 *mc_addr_list;
4784
4785         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4786         mc_addr_list = (u8 *)mc_addr_set;
4787         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4788                                          ixgbe_dev_addr_list_itr, TRUE);
4789 }
4790
4791 static int
4792 ixgbe_timesync_enable(struct rte_eth_dev *dev)
4793 {
4794         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4795         uint32_t tsync_ctl;
4796         uint32_t tsauxc;
4797
4798         /* Enable system time for platforms where it isn't on by default. */
4799         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
4800         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
4801         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
4802
4803         /* Start incrementing the register used to timestamp PTP packets. */
4804         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
4805
4806         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4807         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
4808                         (ETHER_TYPE_1588 |
4809                          IXGBE_ETQF_FILTER_EN |
4810                          IXGBE_ETQF_1588));
4811
4812         /* Enable timestamping of received PTP packets. */
4813         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4814         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
4815         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
4816
4817         /* Enable timestamping of transmitted PTP packets. */
4818         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4819         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
4820         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
4821
4822         return 0;
4823 }
4824
4825 static int
4826 ixgbe_timesync_disable(struct rte_eth_dev *dev)
4827 {
4828         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829         uint32_t tsync_ctl;
4830
4831         /* Disable timestamping of transmitted PTP packets. */
4832         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4833         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
4834         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
4835
4836         /* Disable timestamping of received PTP packets. */
4837         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4838         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
4839         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
4840
4841         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4842         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
4843
4844         /* Stop incrementating the System Time registers. */
4845         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
4846
4847         return 0;
4848 }
4849
4850 static int
4851 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4852                                  struct timespec *timestamp,
4853                                  uint32_t flags __rte_unused)
4854 {
4855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4856         uint32_t tsync_rxctl;
4857         uint32_t rx_stmpl;
4858         uint32_t rx_stmph;
4859
4860         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4861         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
4862                 return -EINVAL;
4863
4864         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
4865         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
4866
4867         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
4868         timestamp->tv_nsec = 0;
4869
4870         return  0;
4871 }
4872
4873 static int
4874 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4875                                  struct timespec *timestamp)
4876 {
4877         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4878         uint32_t tsync_txctl;
4879         uint32_t tx_stmpl;
4880         uint32_t tx_stmph;
4881
4882         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4883         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
4884                 return -EINVAL;
4885
4886         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
4887         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
4888
4889         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
4890         timestamp->tv_nsec = 0;
4891
4892         return  0;
4893 }
4894
4895 static int
4896 ixgbe_get_reg_length(struct rte_eth_dev *dev)
4897 {
4898         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4899         int count = 0;
4900         int g_ind = 0;
4901         const struct reg_info *reg_group;
4902         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
4903                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
4904
4905         while ((reg_group = reg_set[g_ind++]))
4906                 count += ixgbe_regs_group_count(reg_group);
4907
4908         return count;
4909 }
4910
4911 static int
4912 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4913 {
4914         int count = 0;
4915         int g_ind = 0;
4916         const struct reg_info *reg_group;
4917
4918         while ((reg_group = ixgbevf_regs[g_ind++]))
4919                 count += ixgbe_regs_group_count(reg_group);
4920
4921         return count;
4922 }
4923
4924 static int
4925 ixgbe_get_regs(struct rte_eth_dev *dev,
4926               struct rte_dev_reg_info *regs)
4927 {
4928         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4929         uint32_t *data = regs->data;
4930         int g_ind = 0;
4931         int count = 0;
4932         const struct reg_info *reg_group;
4933         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
4934                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
4935
4936         /* Support only full register dump */
4937         if ((regs->length == 0) ||
4938             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
4939                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4940                         hw->device_id;
4941                 while ((reg_group = reg_set[g_ind++]))
4942                         count += ixgbe_read_regs_group(dev, &data[count],
4943                                 reg_group);
4944                 return 0;
4945         }
4946
4947         return -ENOTSUP;
4948 }
4949
4950 static int
4951 ixgbevf_get_regs(struct rte_eth_dev *dev,
4952                 struct rte_dev_reg_info *regs)
4953 {
4954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955         uint32_t *data = regs->data;
4956         int g_ind = 0;
4957         int count = 0;
4958         const struct reg_info *reg_group;
4959
4960         /* Support only full register dump */
4961         if ((regs->length == 0) ||
4962             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
4963                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4964                         hw->device_id;
4965                 while ((reg_group = ixgbevf_regs[g_ind++]))
4966                         count += ixgbe_read_regs_group(dev, &data[count],
4967                                                       reg_group);
4968                 return 0;
4969         }
4970
4971         return -ENOTSUP;
4972 }
4973
4974 static int
4975 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
4976 {
4977         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4978
4979         /* Return unit is byte count */
4980         return hw->eeprom.word_size * 2;
4981 }
4982
4983 static int
4984 ixgbe_get_eeprom(struct rte_eth_dev *dev,
4985                 struct rte_dev_eeprom_info *in_eeprom)
4986 {
4987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4988         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
4989         uint16_t *data = in_eeprom->data;
4990         int first, length;
4991
4992         first = in_eeprom->offset >> 1;
4993         length = in_eeprom->length >> 1;
4994         if ((first >= hw->eeprom.word_size) ||
4995             ((first + length) >= hw->eeprom.word_size))
4996                 return -EINVAL;
4997
4998         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4999
5000         return eeprom->ops.read_buffer(hw, first, length, data);
5001 }
5002
5003 static int
5004 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5005                 struct rte_dev_eeprom_info *in_eeprom)
5006 {
5007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5008         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5009         uint16_t *data = in_eeprom->data;
5010         int first, length;
5011
5012         first = in_eeprom->offset >> 1;
5013         length = in_eeprom->length >> 1;
5014         if ((first >= hw->eeprom.word_size) ||
5015             ((first + length) >= hw->eeprom.word_size))
5016                 return -EINVAL;
5017
5018         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5019
5020         return eeprom->ops.write_buffer(hw,  first, length, data);
5021 }
5022
5023 static struct rte_driver rte_ixgbe_driver = {
5024         .type = PMD_PDEV,
5025         .init = rte_ixgbe_pmd_init,
5026 };
5027
5028 static struct rte_driver rte_ixgbevf_driver = {
5029         .type = PMD_PDEV,
5030         .init = rte_ixgbevf_pmd_init,
5031 };
5032
5033 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5034 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);