drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64 #include <rte_hash_crc.h>
  65
  66 #include "ixgbe_logs.h"
  67 #include "base/ixgbe_api.h"
  68 #include "base/ixgbe_vf.h"
  69 #include "base/ixgbe_common.h"
  70 #include "ixgbe_ethdev.h"
  71 #include "ixgbe_bypass.h"
  72 #include "ixgbe_rxtx.h"
  73 #include "base/ixgbe_type.h"
  74 #include "base/ixgbe_phy.h"
  75 #include "ixgbe_regs.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 158 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 168 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 178                                 int wait_to_complete);
 179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 180                                 struct rte_eth_stats *stats);
 181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_xstat *xstats, unsigned n);
 183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 184                                   struct rte_eth_xstat *xstats, unsigned n);
 185 static int
 186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 187                 uint64_t *values, unsigned int n);
 188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names,
 192         __rte_unused unsigned int size);
 193 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 195 static int ixgbe_dev_xstats_get_names_by_id(
 196         __rte_unused struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names,
 198         const uint64_t *ids,
 199         unsigned int limit);
 200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 201                                              uint16_t queue_id,
 202                                              uint8_t stat_idx,
 203                                              uint8_t is_rx);
 204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 205                                  size_t fw_size);
 206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_dev_info *dev_info);
 208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 210                                  struct rte_eth_dev_info *dev_info);
 211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 212
 213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 214                 uint16_t vlan_id, int on);
 215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 216                                enum rte_vlan_type vlan_type,
 217                                uint16_t tpid_id);
 218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 219                 uint16_t queue, bool on);
 220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 221                 int on);
 222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 227
 228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 233                                struct rte_eth_fc_conf *fc_conf);
 234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 235                 struct rte_eth_pfc_conf *pfc_conf);
 236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 237                         struct rte_eth_rss_reta_entry64 *reta_conf,
 238                         uint16_t reta_size);
 239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 240                         struct rte_eth_rss_reta_entry64 *reta_conf,
 241                         uint16_t reta_size);
 242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 248                                       struct rte_intr_handle *handle);
 249 static void ixgbe_dev_interrupt_handler(void *param);
 250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 252                          uint32_t index, uint32_t pool);
 253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 255                                            struct ether_addr *mac_addr);
 256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 257 static bool is_device_supported(struct rte_eth_dev *dev,
 258                                 struct rte_pci_driver *drv);
 259
 260 /* For Virtual Function support */
 261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 263 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 264 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 267 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 268 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 269 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 270                 struct rte_eth_stats *stats);
 271 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 272 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 273                 uint16_t vlan_id, int on);
 274 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 275                 uint16_t queue, int on);
 276 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 277 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 278 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 279                                             uint16_t queue_id);
 280 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 281                                              uint16_t queue_id);
 282 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 283                                  uint8_t queue, uint8_t msix_vector);
 284 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 285 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 286 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 287
 288 /* For Eth VMDQ APIs support */
 289 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 290                 ether_addr * mac_addr, uint8_t on);
 291 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 292 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 293                 struct rte_eth_mirror_conf *mirror_conf,
 294                 uint8_t rule_id, uint8_t on);
 295 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 296                 uint8_t rule_id);
 297 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 298                                           uint16_t queue_id);
 299 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 300                                            uint16_t queue_id);
 301 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 302                                uint8_t queue, uint8_t msix_vector);
 303 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 304
 305 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 306                 uint16_t queue_idx, uint16_t tx_rate);
 307
 308 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 309                                 struct ether_addr *mac_addr,
 310                                 uint32_t index, uint32_t pool);
 311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 313                                              struct ether_addr *mac_addr);
 314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 315                         struct rte_eth_syn_filter *filter);
 316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 317                         enum rte_filter_op filter_op,
 318                         void *arg);
 319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 322                         struct ixgbe_5tuple_filter *filter);
 323 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ntuple_filter *filter);
 328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 332                         struct rte_eth_ethertype_filter *filter);
 333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 334                      enum rte_filter_type filter_type,
 335                      enum rte_filter_op filter_op,
 336                      void *arg);
 337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 338
 339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 340                                       struct ether_addr *mc_addr_set,
 341                                       uint32_t nb_mc_addr);
 342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 343                                    struct rte_eth_dcb_info *dcb_info);
 344
 345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 347                             struct rte_dev_reg_info *regs);
 348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353
 354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 356                                 struct rte_dev_reg_info *regs);
 357
 358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 361                                             struct timespec *timestamp,
 362                                             uint32_t flags);
 363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 364                                             struct timespec *timestamp);
 365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 367                                    struct timespec *timestamp);
 368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 369                                    const struct timespec *timestamp);
 370 static void ixgbevf_dev_interrupt_handler(void *param);
 371
 372 static int ixgbe_dev_l2_tunnel_eth_type_conf
 373         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 374 static int ixgbe_dev_l2_tunnel_offload_set
 375         (struct rte_eth_dev *dev,
 376          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 377          uint32_t mask,
 378          uint8_t en);
 379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 380                                              enum rte_filter_op filter_op,
 381                                              void *arg);
 382
 383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 384                                          struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 386                                          struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 389
 390 /*
 391  * Define VF Stats MACRO for Non "cleared on read" register
 392  */
 393 #define UPDATE_VF_STAT(reg, last, cur)                          \
 394 {                                                               \
 395         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 396         cur += (latest - last) & UINT_MAX;                      \
 397         last = latest;                                          \
 398 }
 399
 400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 401 {                                                                \
 402         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 403         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 404         u64 latest = ((new_msb << 32) | new_lsb);                \
 405         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 406         last = latest;                                           \
 407 }
 408
 409 #define IXGBE_SET_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] |= 1 << bit;\
 413         } while (0)
 414
 415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (h)->bitmap[idx] &= ~(1 << bit);\
 419         } while (0)
 420
 421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 422                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 423                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 424                 (r) = (h)->bitmap[idx] >> bit & 1;\
 425         } while (0)
 426
 427 /*
 428  * The set of PCI devices this driver supports
 429  */
 430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 484 #ifdef RTE_NIC_BYPASS
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 486 #endif
 487         { .vendor_id = 0, /* sentinel */ },
 488 };
 489
 490 /*
 491  * The set of PCI devices this driver supports (for 82599 VF)
 492  */
 493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 504         { .vendor_id = 0, /* sentinel */ },
 505 };
 506
 507 static const struct rte_eth_desc_lim rx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_RXD_ALIGN,
 511 };
 512
 513 static const struct rte_eth_desc_lim tx_desc_lim = {
 514         .nb_max = IXGBE_MAX_RING_DESC,
 515         .nb_min = IXGBE_MIN_RING_DESC,
 516         .nb_align = IXGBE_TXD_ALIGN,
 517         .nb_seg_max = IXGBE_TX_MAX_SEG,
 518         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 519 };
 520
 521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 522         .dev_configure        = ixgbe_dev_configure,
 523         .dev_start            = ixgbe_dev_start,
 524         .dev_stop             = ixgbe_dev_stop,
 525         .dev_set_link_up    = ixgbe_dev_set_link_up,
 526         .dev_set_link_down  = ixgbe_dev_set_link_down,
 527         .dev_close            = ixgbe_dev_close,
 528         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 529         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 530         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 531         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 532         .link_update          = ixgbe_dev_link_update,
 533         .stats_get            = ixgbe_dev_stats_get,
 534         .xstats_get           = ixgbe_dev_xstats_get,
 535         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 536         .stats_reset          = ixgbe_dev_stats_reset,
 537         .xstats_reset         = ixgbe_dev_xstats_reset,
 538         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 539         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 540         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 541         .fw_version_get       = ixgbe_fw_version_get,
 542         .dev_infos_get        = ixgbe_dev_info_get,
 543         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 544         .mtu_set              = ixgbe_dev_mtu_set,
 545         .vlan_filter_set      = ixgbe_vlan_filter_set,
 546         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 547         .vlan_offload_set     = ixgbe_vlan_offload_set,
 548         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 549         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 550         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 551         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 552         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 553         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 554         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 555         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 556         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 557         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 558         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 559         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 560         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 561         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 562         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 563         .dev_led_on           = ixgbe_dev_led_on,
 564         .dev_led_off          = ixgbe_dev_led_off,
 565         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 566         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 567         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 568         .mac_addr_add         = ixgbe_add_rar,
 569         .mac_addr_remove      = ixgbe_remove_rar,
 570         .mac_addr_set         = ixgbe_set_default_mac_addr,
 571         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 572         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 573         .mirror_rule_set      = ixgbe_mirror_rule_set,
 574         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 575         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 576         .reta_update          = ixgbe_dev_rss_reta_update,
 577         .reta_query           = ixgbe_dev_rss_reta_query,
 578 #ifdef RTE_NIC_BYPASS
 579         .bypass_init          = ixgbe_bypass_init,
 580         .bypass_state_set     = ixgbe_bypass_state_store,
 581         .bypass_state_show    = ixgbe_bypass_state_show,
 582         .bypass_event_set     = ixgbe_bypass_event_store,
 583         .bypass_event_show    = ixgbe_bypass_event_show,
 584         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 585         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 586         .bypass_ver_show      = ixgbe_bypass_ver_show,
 587         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 588 #endif /* RTE_NIC_BYPASS */
 589         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 590         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 591         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 592         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 593         .rxq_info_get         = ixgbe_rxq_info_get,
 594         .txq_info_get         = ixgbe_txq_info_get,
 595         .timesync_enable      = ixgbe_timesync_enable,
 596         .timesync_disable     = ixgbe_timesync_disable,
 597         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 598         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 599         .get_reg              = ixgbe_get_regs,
 600         .get_eeprom_length    = ixgbe_get_eeprom_length,
 601         .get_eeprom           = ixgbe_get_eeprom,
 602         .set_eeprom           = ixgbe_set_eeprom,
 603         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 604         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 605         .timesync_read_time   = ixgbe_timesync_read_time,
 606         .timesync_write_time  = ixgbe_timesync_write_time,
 607         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 608         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 609         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 610         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 611 };
 612
 613 /*
 614  * dev_ops for virtual function, bare necessities for basic vf
 615  * operation have been implemented
 616  */
 617 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 618         .dev_configure        = ixgbevf_dev_configure,
 619         .dev_start            = ixgbevf_dev_start,
 620         .dev_stop             = ixgbevf_dev_stop,
 621         .link_update          = ixgbe_dev_link_update,
 622         .stats_get            = ixgbevf_dev_stats_get,
 623         .xstats_get           = ixgbevf_dev_xstats_get,
 624         .stats_reset          = ixgbevf_dev_stats_reset,
 625         .xstats_reset         = ixgbevf_dev_stats_reset,
 626         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 627         .dev_close            = ixgbevf_dev_close,
 628         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 629         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 630         .dev_infos_get        = ixgbevf_dev_info_get,
 631         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 632         .mtu_set              = ixgbevf_dev_set_mtu,
 633         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 634         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 635         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 636         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 637         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 638         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 639         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 640         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 641         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 642         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 643         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 644         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 645         .mac_addr_add         = ixgbevf_add_mac_addr,
 646         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 647         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 648         .rxq_info_get         = ixgbe_rxq_info_get,
 649         .txq_info_get         = ixgbe_txq_info_get,
 650         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 651         .get_reg              = ixgbevf_get_regs,
 652         .reta_update          = ixgbe_dev_rss_reta_update,
 653         .reta_query           = ixgbe_dev_rss_reta_query,
 654         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 655         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 656 };
 657
 658 /* store statistics names and its offset in stats structure */
 659 struct rte_ixgbe_xstats_name_off {
 660         char name[RTE_ETH_XSTATS_NAME_SIZE];
 661         unsigned offset;
 662 };
 663
 664 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 665         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 666         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 667         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 668         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 669         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 670         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 671         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 672         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 673         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 674         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 675         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 676         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 677         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 678         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 679         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 680                 prc1023)},
 681         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 682                 prc1522)},
 683         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 684         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 685         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 686         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 687         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 688         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 689         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 690         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 691         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 692         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 693         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 694         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 695         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 696         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 697         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 698         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 699         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 700                 ptc1023)},
 701         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 702                 ptc1522)},
 703         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 704         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 705         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 706         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 707
 708         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 709                 fdirustat_add)},
 710         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirustat_remove)},
 712         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 713                 fdirfstat_fadd)},
 714         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 715                 fdirfstat_fremove)},
 716         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 717                 fdirmatch)},
 718         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 719                 fdirmiss)},
 720
 721         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 722         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 723         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 724                 fclast)},
 725         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 726         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 727         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 728         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 729         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 730                 fcoe_noddp)},
 731         {"rx_fcoe_no_direct_data_placement_ext_buff",
 732                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 733
 734         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 735                 lxontxc)},
 736         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxonrxc)},
 738         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxofftxc)},
 740         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxoffrxc)},
 742         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 743 };
 744
 745 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 746                            sizeof(rte_ixgbe_stats_strings[0]))
 747
 748 /* MACsec statistics */
 749 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 750         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 751                 out_pkts_untagged)},
 752         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 753                 out_pkts_encrypted)},
 754         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 755                 out_pkts_protected)},
 756         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 757                 out_octets_encrypted)},
 758         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 759                 out_octets_protected)},
 760         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_untagged)},
 762         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_badtag)},
 764         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_nosci)},
 766         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_unknownsci)},
 768         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 769                 in_octets_decrypted)},
 770         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 771                 in_octets_validated)},
 772         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_unchecked)},
 774         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_delayed)},
 776         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_late)},
 778         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_ok)},
 780         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 781                 in_pkts_invalid)},
 782         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 783                 in_pkts_notvalid)},
 784         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 785                 in_pkts_unusedsa)},
 786         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 787                 in_pkts_notusingsa)},
 788 };
 789
 790 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 791                            sizeof(rte_ixgbe_macsec_strings[0]))
 792
 793 /* Per-queue statistics */
 794 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 795         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 796         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 797         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 798         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 799 };
 800
 801 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 802                            sizeof(rte_ixgbe_rxq_strings[0]))
 803 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 804
 805 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 806         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 807         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 808         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 809                 pxon2offc)},
 810 };
 811
 812 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 813                            sizeof(rte_ixgbe_txq_strings[0]))
 814 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 815
 816 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 817         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 818 };
 819
 820 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 821                 sizeof(rte_ixgbevf_stats_strings[0]))
 822
 823 /**
 824  * Atomically reads the link status information from global
 825  * structure rte_eth_dev.
 826  *
 827  * @param dev
 828  *   - Pointer to the structure rte_eth_dev to read from.
 829  *   - Pointer to the buffer to be saved with the link status.
 830  *
 831  * @return
 832  *   - On success, zero.
 833  *   - On failure, negative value.
 834  */
 835 static inline int
 836 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 837                                 struct rte_eth_link *link)
 838 {
 839         struct rte_eth_link *dst = link;
 840         struct rte_eth_link *src = &(dev->data->dev_link);
 841
 842         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 843                                         *(uint64_t *)src) == 0)
 844                 return -1;
 845
 846         return 0;
 847 }
 848
 849 /**
 850  * Atomically writes the link status information into global
 851  * structure rte_eth_dev.
 852  *
 853  * @param dev
 854  *   - Pointer to the structure rte_eth_dev to read from.
 855  *   - Pointer to the buffer to be saved with the link status.
 856  *
 857  * @return
 858  *   - On success, zero.
 859  *   - On failure, negative value.
 860  */
 861 static inline int
 862 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 863                                 struct rte_eth_link *link)
 864 {
 865         struct rte_eth_link *dst = &(dev->data->dev_link);
 866         struct rte_eth_link *src = link;
 867
 868         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 869                                         *(uint64_t *)src) == 0)
 870                 return -1;
 871
 872         return 0;
 873 }
 874
 875 /*
 876  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 877  */
 878 static inline int
 879 ixgbe_is_sfp(struct ixgbe_hw *hw)
 880 {
 881         switch (hw->phy.type) {
 882         case ixgbe_phy_sfp_avago:
 883         case ixgbe_phy_sfp_ftl:
 884         case ixgbe_phy_sfp_intel:
 885         case ixgbe_phy_sfp_unknown:
 886         case ixgbe_phy_sfp_passive_tyco:
 887         case ixgbe_phy_sfp_passive_unknown:
 888                 return 1;
 889         default:
 890                 return 0;
 891         }
 892 }
 893
 894 static inline int32_t
 895 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 896 {
 897         uint32_t ctrl_ext;
 898         int32_t status;
 899
 900         status = ixgbe_reset_hw(hw);
 901
 902         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 903         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 904         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 905         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 906         IXGBE_WRITE_FLUSH(hw);
 907
 908         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 909                 status = IXGBE_SUCCESS;
 910         return status;
 911 }
 912
 913 static inline void
 914 ixgbe_enable_intr(struct rte_eth_dev *dev)
 915 {
 916         struct ixgbe_interrupt *intr =
 917                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 918         struct ixgbe_hw *hw =
 919                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 920
 921         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 922         IXGBE_WRITE_FLUSH(hw);
 923 }
 924
 925 /*
 926  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 927  */
 928 static void
 929 ixgbe_disable_intr(struct ixgbe_hw *hw)
 930 {
 931         PMD_INIT_FUNC_TRACE();
 932
 933         if (hw->mac.type == ixgbe_mac_82598EB) {
 934                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 935         } else {
 936                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 937                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 938                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 939         }
 940         IXGBE_WRITE_FLUSH(hw);
 941 }
 942
 943 /*
 944  * This function resets queue statistics mapping registers.
 945  * From Niantic datasheet, Initialization of Statistics section:
 946  * "...if software requires the queue counters, the RQSMR and TQSM registers
 947  * must be re-programmed following a device reset.
 948  */
 949 static void
 950 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 951 {
 952         uint32_t i;
 953
 954         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 956                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 957         }
 958 }
 959
 960
 961 static int
 962 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 963                                   uint16_t queue_id,
 964                                   uint8_t stat_idx,
 965                                   uint8_t is_rx)
 966 {
 967 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 968 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 969 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 970
 971         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 972         struct ixgbe_stat_mapping_registers *stat_mappings =
 973                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 974         uint32_t qsmr_mask = 0;
 975         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 976         uint32_t q_map;
 977         uint8_t n, offset;
 978
 979         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 980                 (hw->mac.type != ixgbe_mac_X540) &&
 981                 (hw->mac.type != ixgbe_mac_X550) &&
 982                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 983                 (hw->mac.type != ixgbe_mac_X550EM_a))
 984                 return -ENOSYS;
 985
 986         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 987                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 988                      queue_id, stat_idx);
 989
 990         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 991         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 992                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 993                 return -EIO;
 994         }
 995         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 996
 997         /* Now clear any previous stat_idx set */
 998         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 999         if (!is_rx)
1000                 stat_mappings->tqsm[n] &= ~clearing_mask;
1001         else
1002                 stat_mappings->rqsmr[n] &= ~clearing_mask;
1003
1004         q_map = (uint32_t)stat_idx;
1005         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1006         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1007         if (!is_rx)
1008                 stat_mappings->tqsm[n] |= qsmr_mask;
1009         else
1010                 stat_mappings->rqsmr[n] |= qsmr_mask;
1011
1012         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1013                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1014                      queue_id, stat_idx);
1015         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1016                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1017
1018         /* Now write the mapping in the appropriate register */
1019         if (is_rx) {
1020                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1021                              stat_mappings->rqsmr[n], n);
1022                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1023         } else {
1024                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1025                              stat_mappings->tqsm[n], n);
1026                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1027         }
1028         return 0;
1029 }
1030
1031 static void
1032 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1033 {
1034         struct ixgbe_stat_mapping_registers *stat_mappings =
1035                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         int i;
1038
1039         /* write whatever was in stat mapping table to the NIC */
1040         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1041                 /* rx */
1042                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1043
1044                 /* tx */
1045                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1046         }
1047 }
1048
1049 static void
1050 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1051 {
1052         uint8_t i;
1053         struct ixgbe_dcb_tc_config *tc;
1054         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1055
1056         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1057         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1058         for (i = 0; i < dcb_max_tc; i++) {
1059                 tc = &dcb_config->tc_config[i];
1060                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1061                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1062                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1063                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1064                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1065                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1066                 tc->pfc = ixgbe_dcb_pfc_disabled;
1067         }
1068
1069         /* Initialize default user to priority mapping, UPx->TC0 */
1070         tc = &dcb_config->tc_config[0];
1071         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1072         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1073         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1074                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1075                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1076         }
1077         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1078         dcb_config->pfc_mode_enable = false;
1079         dcb_config->vt_mode = true;
1080         dcb_config->round_robin_enable = false;
1081         /* support all DCB capabilities in 82599 */
1082         dcb_config->support.capabilities = 0xFF;
1083
1084         /*we only support 4 Tcs for X540, X550 */
1085         if (hw->mac.type == ixgbe_mac_X540 ||
1086                 hw->mac.type == ixgbe_mac_X550 ||
1087                 hw->mac.type == ixgbe_mac_X550EM_x ||
1088                 hw->mac.type == ixgbe_mac_X550EM_a) {
1089                 dcb_config->num_tcs.pg_tcs = 4;
1090                 dcb_config->num_tcs.pfc_tcs = 4;
1091         }
1092 }
1093
1094 /*
1095  * Ensure that all locks are released before first NVM or PHY access
1096  */
1097 static void
1098 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1099 {
1100         uint16_t mask;
1101
1102         /*
1103          * Phy lock should not fail in this early stage. If this is the case,
1104          * it is due to an improper exit of the application.
1105          * So force the release of the faulty lock. Release of common lock
1106          * is done automatically by swfw_sync function.
1107          */
1108         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1109         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1111         }
1112         ixgbe_release_swfw_semaphore(hw, mask);
1113
1114         /*
1115          * These ones are more tricky since they are common to all ports; but
1116          * swfw_sync retries last long enough (1s) to be almost sure that if
1117          * lock can not be taken it is due to an improper lock of the
1118          * semaphore.
1119          */
1120         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1121         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1122                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1123         }
1124         ixgbe_release_swfw_semaphore(hw, mask);
1125 }
1126
1127 /*
1128  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1129  * It returns 0 on success.
1130  */
1131 static int
1132 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1133 {
1134         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1135         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1136         struct ixgbe_hw *hw =
1137                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1138         struct ixgbe_vfta *shadow_vfta =
1139                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1140         struct ixgbe_hwstrip *hwstrip =
1141                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1142         struct ixgbe_dcb_config *dcb_config =
1143                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1144         struct ixgbe_filter_info *filter_info =
1145                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1146         struct ixgbe_bw_conf *bw_conf =
1147                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1148         uint32_t ctrl_ext;
1149         uint16_t csum;
1150         int diag, i;
1151
1152         PMD_INIT_FUNC_TRACE();
1153
1154         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1155         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1156         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1157         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1158
1159         /*
1160          * For secondary processes, we don't initialise any further as primary
1161          * has already done this work. Only check we don't need a different
1162          * RX and TX function.
1163          */
1164         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1165                 struct ixgbe_tx_queue *txq;
1166                 /* TX queue function in primary, set by last queue initialized
1167                  * Tx queue may not initialized by primary process
1168                  */
1169                 if (eth_dev->data->tx_queues) {
1170                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1171                         ixgbe_set_tx_function(eth_dev, txq);
1172                 } else {
1173                         /* Use default TX function if we get here */
1174                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1175                                      "Using default TX function.");
1176                 }
1177
1178                 ixgbe_set_rx_function(eth_dev);
1179
1180                 return 0;
1181         }
1182
1183         rte_eth_copy_pci_info(eth_dev, pci_dev);
1184         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1185
1186         /* Vendor and Device ID need to be set before init of shared code */
1187         hw->device_id = pci_dev->id.device_id;
1188         hw->vendor_id = pci_dev->id.vendor_id;
1189         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1190         hw->allow_unsupported_sfp = 1;
1191
1192         /* Initialize the shared code (base driver) */
1193 #ifdef RTE_NIC_BYPASS
1194         diag = ixgbe_bypass_init_shared_code(hw);
1195 #else
1196         diag = ixgbe_init_shared_code(hw);
1197 #endif /* RTE_NIC_BYPASS */
1198
1199         if (diag != IXGBE_SUCCESS) {
1200                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1201                 return -EIO;
1202         }
1203
1204         /* pick up the PCI bus settings for reporting later */
1205         ixgbe_get_bus_info(hw);
1206
1207         /* Unlock any pending hardware semaphore */
1208         ixgbe_swfw_lock_reset(hw);
1209
1210         /* Initialize DCB configuration*/
1211         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1212         ixgbe_dcb_init(hw, dcb_config);
1213         /* Get Hardware Flow Control setting */
1214         hw->fc.requested_mode = ixgbe_fc_full;
1215         hw->fc.current_mode = ixgbe_fc_full;
1216         hw->fc.pause_time = IXGBE_FC_PAUSE;
1217         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1218                 hw->fc.low_water[i] = IXGBE_FC_LO;
1219                 hw->fc.high_water[i] = IXGBE_FC_HI;
1220         }
1221         hw->fc.send_xon = 1;
1222
1223         /* Make sure we have a good EEPROM before we read from it */
1224         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1225         if (diag != IXGBE_SUCCESS) {
1226                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1227                 return -EIO;
1228         }
1229
1230 #ifdef RTE_NIC_BYPASS
1231         diag = ixgbe_bypass_init_hw(hw);
1232 #else
1233         diag = ixgbe_init_hw(hw);
1234 #endif /* RTE_NIC_BYPASS */
1235
1236         /*
1237          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1238          * is called too soon after the kernel driver unbinding/binding occurs.
1239          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1240          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1241          * also called. See ixgbe_identify_phy_82599(). The reason for the
1242          * failure is not known, and only occuts when virtualisation features
1243          * are disabled in the bios. A delay of 100ms  was found to be enough by
1244          * trial-and-error, and is doubled to be safe.
1245          */
1246         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1247                 rte_delay_ms(200);
1248                 diag = ixgbe_init_hw(hw);
1249         }
1250
1251         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1252                 diag = IXGBE_SUCCESS;
1253
1254         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1255                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1256                              "LOM.  Please be aware there may be issues associated "
1257                              "with your hardware.");
1258                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1259                              "please contact your Intel or hardware representative "
1260                              "who provided you with this hardware.");
1261         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1262                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1263         if (diag) {
1264                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1265                 return -EIO;
1266         }
1267
1268         /* Reset the hw statistics */
1269         ixgbe_dev_stats_reset(eth_dev);
1270
1271         /* disable interrupt */
1272         ixgbe_disable_intr(hw);
1273
1274         /* reset mappings for queue statistics hw counters*/
1275         ixgbe_reset_qstat_mappings(hw);
1276
1277         /* Allocate memory for storing MAC addresses */
1278         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1279                                                hw->mac.num_rar_entries, 0);
1280         if (eth_dev->data->mac_addrs == NULL) {
1281                 PMD_INIT_LOG(ERR,
1282                              "Failed to allocate %u bytes needed to store "
1283                              "MAC addresses",
1284                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1285                 return -ENOMEM;
1286         }
1287         /* Copy the permanent MAC address */
1288         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1289                         &eth_dev->data->mac_addrs[0]);
1290
1291         /* Allocate memory for storing hash filter MAC addresses */
1292         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1293                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1294         if (eth_dev->data->hash_mac_addrs == NULL) {
1295                 PMD_INIT_LOG(ERR,
1296                              "Failed to allocate %d bytes needed to store MAC addresses",
1297                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1298                 return -ENOMEM;
1299         }
1300
1301         /* initialize the vfta */
1302         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1303
1304         /* initialize the hw strip bitmap*/
1305         memset(hwstrip, 0, sizeof(*hwstrip));
1306
1307         /* initialize PF if max_vfs not zero */
1308         ixgbe_pf_host_init(eth_dev);
1309
1310         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1311         /* let hardware know driver is loaded */
1312         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1313         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1314         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1315         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1316         IXGBE_WRITE_FLUSH(hw);
1317
1318         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1319                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1320                              (int) hw->mac.type, (int) hw->phy.type,
1321                              (int) hw->phy.sfp_type);
1322         else
1323                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1324                              (int) hw->mac.type, (int) hw->phy.type);
1325
1326         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1327                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1328                      pci_dev->id.device_id);
1329
1330         rte_intr_callback_register(intr_handle,
1331                                    ixgbe_dev_interrupt_handler, eth_dev);
1332
1333         /* enable uio/vfio intr/eventfd mapping */
1334         rte_intr_enable(intr_handle);
1335
1336         /* enable support intr */
1337         ixgbe_enable_intr(eth_dev);
1338
1339         /* initialize filter info */
1340         memset(filter_info, 0,
1341                sizeof(struct ixgbe_filter_info));
1342
1343         /* initialize 5tuple filter list */
1344         TAILQ_INIT(&filter_info->fivetuple_list);
1345
1346         /* initialize flow director filter list & hash */
1347         ixgbe_fdir_filter_init(eth_dev);
1348
1349         /* initialize l2 tunnel filter list & hash */
1350         ixgbe_l2_tn_filter_init(eth_dev);
1351
1352         TAILQ_INIT(&filter_ntuple_list);
1353         TAILQ_INIT(&filter_ethertype_list);
1354         TAILQ_INIT(&filter_syn_list);
1355         TAILQ_INIT(&filter_fdir_list);
1356         TAILQ_INIT(&filter_l2_tunnel_list);
1357         TAILQ_INIT(&ixgbe_flow_list);
1358
1359         /* initialize bandwidth configuration info */
1360         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1361
1362         return 0;
1363 }
1364
1365 static int
1366 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1367 {
1368         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1369         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1370         struct ixgbe_hw *hw;
1371
1372         PMD_INIT_FUNC_TRACE();
1373
1374         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1375                 return -EPERM;
1376
1377         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1378
1379         if (hw->adapter_stopped == 0)
1380                 ixgbe_dev_close(eth_dev);
1381
1382         eth_dev->dev_ops = NULL;
1383         eth_dev->rx_pkt_burst = NULL;
1384         eth_dev->tx_pkt_burst = NULL;
1385
1386         /* Unlock any pending hardware semaphore */
1387         ixgbe_swfw_lock_reset(hw);
1388
1389         /* disable uio intr before callback unregister */
1390         rte_intr_disable(intr_handle);
1391         rte_intr_callback_unregister(intr_handle,
1392                                      ixgbe_dev_interrupt_handler, eth_dev);
1393
1394         /* uninitialize PF if max_vfs not zero */
1395         ixgbe_pf_host_uninit(eth_dev);
1396
1397         rte_free(eth_dev->data->mac_addrs);
1398         eth_dev->data->mac_addrs = NULL;
1399
1400         rte_free(eth_dev->data->hash_mac_addrs);
1401         eth_dev->data->hash_mac_addrs = NULL;
1402
1403         /* remove all the fdir filters & hash */
1404         ixgbe_fdir_filter_uninit(eth_dev);
1405
1406         /* remove all the L2 tunnel filters & hash */
1407         ixgbe_l2_tn_filter_uninit(eth_dev);
1408
1409         /* Remove all ntuple filters of the device */
1410         ixgbe_ntuple_filter_uninit(eth_dev);
1411
1412         /* clear all the filters list */
1413         ixgbe_filterlist_flush();
1414
1415         return 0;
1416 }
1417
1418 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1419 {
1420         struct ixgbe_filter_info *filter_info =
1421                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1422         struct ixgbe_5tuple_filter *p_5tuple;
1423
1424         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1425                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1426                              p_5tuple,
1427                              entries);
1428                 rte_free(p_5tuple);
1429         }
1430         memset(filter_info->fivetuple_mask, 0,
1431                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1432
1433         return 0;
1434 }
1435
1436 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1437 {
1438         struct ixgbe_hw_fdir_info *fdir_info =
1439                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1440         struct ixgbe_fdir_filter *fdir_filter;
1441
1442                 if (fdir_info->hash_map)
1443                 rte_free(fdir_info->hash_map);
1444         if (fdir_info->hash_handle)
1445                 rte_hash_free(fdir_info->hash_handle);
1446
1447         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1448                 TAILQ_REMOVE(&fdir_info->fdir_list,
1449                              fdir_filter,
1450                              entries);
1451                 rte_free(fdir_filter);
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1458 {
1459         struct ixgbe_l2_tn_info *l2_tn_info =
1460                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1461         struct ixgbe_l2_tn_filter *l2_tn_filter;
1462
1463         if (l2_tn_info->hash_map)
1464                 rte_free(l2_tn_info->hash_map);
1465         if (l2_tn_info->hash_handle)
1466                 rte_hash_free(l2_tn_info->hash_handle);
1467
1468         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1469                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1470                              l2_tn_filter,
1471                              entries);
1472                 rte_free(l2_tn_filter);
1473         }
1474
1475         return 0;
1476 }
1477
1478 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1479 {
1480         struct ixgbe_hw_fdir_info *fdir_info =
1481                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1482         char fdir_hash_name[RTE_HASH_NAMESIZE];
1483         struct rte_hash_parameters fdir_hash_params = {
1484                 .name = fdir_hash_name,
1485                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1486                 .key_len = sizeof(union ixgbe_atr_input),
1487                 .hash_func = rte_hash_crc,
1488                 .hash_func_init_val = 0,
1489                 .socket_id = rte_socket_id(),
1490         };
1491
1492         TAILQ_INIT(&fdir_info->fdir_list);
1493         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1494                  "fdir_%s", eth_dev->data->name);
1495         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1496         if (!fdir_info->hash_handle) {
1497                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1498                 return -EINVAL;
1499         }
1500         fdir_info->hash_map = rte_zmalloc("ixgbe",
1501                                           sizeof(struct ixgbe_fdir_filter *) *
1502                                           IXGBE_MAX_FDIR_FILTER_NUM,
1503                                           0);
1504         if (!fdir_info->hash_map) {
1505                 PMD_INIT_LOG(ERR,
1506                              "Failed to allocate memory for fdir hash map!");
1507                 return -ENOMEM;
1508         }
1509         fdir_info->mask_added = FALSE;
1510
1511         return 0;
1512 }
1513
1514 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1515 {
1516         struct ixgbe_l2_tn_info *l2_tn_info =
1517                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1518         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1519         struct rte_hash_parameters l2_tn_hash_params = {
1520                 .name = l2_tn_hash_name,
1521                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1522                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1523                 .hash_func = rte_hash_crc,
1524                 .hash_func_init_val = 0,
1525                 .socket_id = rte_socket_id(),
1526         };
1527
1528         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1529         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1530                  "l2_tn_%s", eth_dev->data->name);
1531         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1532         if (!l2_tn_info->hash_handle) {
1533                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1534                 return -EINVAL;
1535         }
1536         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1537                                    sizeof(struct ixgbe_l2_tn_filter *) *
1538                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1539                                    0);
1540         if (!l2_tn_info->hash_map) {
1541                 PMD_INIT_LOG(ERR,
1542                         "Failed to allocate memory for L2 TN hash map!");
1543                 return -ENOMEM;
1544         }
1545         l2_tn_info->e_tag_en = FALSE;
1546         l2_tn_info->e_tag_fwd_en = FALSE;
1547         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1548
1549         return 0;
1550 }
1551 /*
1552  * Negotiate mailbox API version with the PF.
1553  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1554  * Then we try to negotiate starting with the most recent one.
1555  * If all negotiation attempts fail, then we will proceed with
1556  * the default one (ixgbe_mbox_api_10).
1557  */
1558 static void
1559 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1560 {
1561         int32_t i;
1562
1563         /* start with highest supported, proceed down */
1564         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1565                 ixgbe_mbox_api_12,
1566                 ixgbe_mbox_api_11,
1567                 ixgbe_mbox_api_10,
1568         };
1569
1570         for (i = 0;
1571                         i != RTE_DIM(sup_ver) &&
1572                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1573                         i++)
1574                 ;
1575 }
1576
1577 static void
1578 generate_random_mac_addr(struct ether_addr *mac_addr)
1579 {
1580         uint64_t random;
1581
1582         /* Set Organizationally Unique Identifier (OUI) prefix. */
1583         mac_addr->addr_bytes[0] = 0x00;
1584         mac_addr->addr_bytes[1] = 0x09;
1585         mac_addr->addr_bytes[2] = 0xC0;
1586         /* Force indication of locally assigned MAC address. */
1587         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1588         /* Generate the last 3 bytes of the MAC address with a random number. */
1589         random = rte_rand();
1590         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1591 }
1592
1593 /*
1594  * Virtual Function device init
1595  */
1596 static int
1597 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1598 {
1599         int diag;
1600         uint32_t tc, tcs;
1601         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1602         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1603         struct ixgbe_hw *hw =
1604                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1605         struct ixgbe_vfta *shadow_vfta =
1606                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1607         struct ixgbe_hwstrip *hwstrip =
1608                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1609         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1610
1611         PMD_INIT_FUNC_TRACE();
1612
1613         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1614         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1615         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1616
1617         /* for secondary processes, we don't initialise any further as primary
1618          * has already done this work. Only check we don't need a different
1619          * RX function
1620          */
1621         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1622                 struct ixgbe_tx_queue *txq;
1623                 /* TX queue function in primary, set by last queue initialized
1624                  * Tx queue may not initialized by primary process
1625                  */
1626                 if (eth_dev->data->tx_queues) {
1627                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1628                         ixgbe_set_tx_function(eth_dev, txq);
1629                 } else {
1630                         /* Use default TX function if we get here */
1631                         PMD_INIT_LOG(NOTICE,
1632                                      "No TX queues configured yet. Using default TX function.");
1633                 }
1634
1635                 ixgbe_set_rx_function(eth_dev);
1636
1637                 return 0;
1638         }
1639
1640         rte_eth_copy_pci_info(eth_dev, pci_dev);
1641         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1642
1643         hw->device_id = pci_dev->id.device_id;
1644         hw->vendor_id = pci_dev->id.vendor_id;
1645         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1646
1647         /* initialize the vfta */
1648         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1649
1650         /* initialize the hw strip bitmap*/
1651         memset(hwstrip, 0, sizeof(*hwstrip));
1652
1653         /* Initialize the shared code (base driver) */
1654         diag = ixgbe_init_shared_code(hw);
1655         if (diag != IXGBE_SUCCESS) {
1656                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1657                 return -EIO;
1658         }
1659
1660         /* init_mailbox_params */
1661         hw->mbx.ops.init_params(hw);
1662
1663         /* Reset the hw statistics */
1664         ixgbevf_dev_stats_reset(eth_dev);
1665
1666         /* Disable the interrupts for VF */
1667         ixgbevf_intr_disable(hw);
1668
1669         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1670         diag = hw->mac.ops.reset_hw(hw);
1671
1672         /*
1673          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1674          * the underlying PF driver has not assigned a MAC address to the VF.
1675          * In this case, assign a random MAC address.
1676          */
1677         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1678                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1679                 return diag;
1680         }
1681
1682         /* negotiate mailbox API version to use with the PF. */
1683         ixgbevf_negotiate_api(hw);
1684
1685         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1686         ixgbevf_get_queues(hw, &tcs, &tc);
1687
1688         /* Allocate memory for storing MAC addresses */
1689         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1690                                                hw->mac.num_rar_entries, 0);
1691         if (eth_dev->data->mac_addrs == NULL) {
1692                 PMD_INIT_LOG(ERR,
1693                              "Failed to allocate %u bytes needed to store "
1694                              "MAC addresses",
1695                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1696                 return -ENOMEM;
1697         }
1698
1699         /* Generate a random MAC address, if none was assigned by PF. */
1700         if (is_zero_ether_addr(perm_addr)) {
1701                 generate_random_mac_addr(perm_addr);
1702                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1703                 if (diag) {
1704                         rte_free(eth_dev->data->mac_addrs);
1705                         eth_dev->data->mac_addrs = NULL;
1706                         return diag;
1707                 }
1708                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1709                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1710                              "%02x:%02x:%02x:%02x:%02x:%02x",
1711                              perm_addr->addr_bytes[0],
1712                              perm_addr->addr_bytes[1],
1713                              perm_addr->addr_bytes[2],
1714                              perm_addr->addr_bytes[3],
1715                              perm_addr->addr_bytes[4],
1716                              perm_addr->addr_bytes[5]);
1717         }
1718
1719         /* Copy the permanent MAC address */
1720         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1721
1722         /* reset the hardware with the new settings */
1723         diag = hw->mac.ops.start_hw(hw);
1724         switch (diag) {
1725         case  0:
1726                 break;
1727
1728         default:
1729                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1730                 return -EIO;
1731         }
1732
1733         rte_intr_callback_register(intr_handle,
1734                                    ixgbevf_dev_interrupt_handler, eth_dev);
1735         rte_intr_enable(intr_handle);
1736         ixgbevf_intr_enable(hw);
1737
1738         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1739                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1740                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1741
1742         return 0;
1743 }
1744
1745 /* Virtual Function device uninit */
1746
1747 static int
1748 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1749 {
1750         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1751         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1752         struct ixgbe_hw *hw;
1753
1754         PMD_INIT_FUNC_TRACE();
1755
1756         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1757                 return -EPERM;
1758
1759         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1760
1761         if (hw->adapter_stopped == 0)
1762                 ixgbevf_dev_close(eth_dev);
1763
1764         eth_dev->dev_ops = NULL;
1765         eth_dev->rx_pkt_burst = NULL;
1766         eth_dev->tx_pkt_burst = NULL;
1767
1768         /* Disable the interrupts for VF */
1769         ixgbevf_intr_disable(hw);
1770
1771         rte_free(eth_dev->data->mac_addrs);
1772         eth_dev->data->mac_addrs = NULL;
1773
1774         rte_intr_disable(intr_handle);
1775         rte_intr_callback_unregister(intr_handle,
1776                                      ixgbevf_dev_interrupt_handler, eth_dev);
1777
1778         return 0;
1779 }
1780
1781 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1782         struct rte_pci_device *pci_dev)
1783 {
1784         return rte_eth_dev_pci_generic_probe(pci_dev,
1785                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1786 }
1787
1788 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1789 {
1790         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1791 }
1792
1793 static struct rte_pci_driver rte_ixgbe_pmd = {
1794         .id_table = pci_id_ixgbe_map,
1795         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1796         .probe = eth_ixgbe_pci_probe,
1797         .remove = eth_ixgbe_pci_remove,
1798 };
1799
1800 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1801         struct rte_pci_device *pci_dev)
1802 {
1803         return rte_eth_dev_pci_generic_probe(pci_dev,
1804                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1805 }
1806
1807 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1808 {
1809         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1810 }
1811
1812 /*
1813  * virtual function driver struct
1814  */
1815 static struct rte_pci_driver rte_ixgbevf_pmd = {
1816         .id_table = pci_id_ixgbevf_map,
1817         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1818         .probe = eth_ixgbevf_pci_probe,
1819         .remove = eth_ixgbevf_pci_remove,
1820 };
1821
1822 static int
1823 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1824 {
1825         struct ixgbe_hw *hw =
1826                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827         struct ixgbe_vfta *shadow_vfta =
1828                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1829         uint32_t vfta;
1830         uint32_t vid_idx;
1831         uint32_t vid_bit;
1832
1833         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1834         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1835         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1836         if (on)
1837                 vfta |= vid_bit;
1838         else
1839                 vfta &= ~vid_bit;
1840         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1841
1842         /* update local VFTA copy */
1843         shadow_vfta->vfta[vid_idx] = vfta;
1844
1845         return 0;
1846 }
1847
1848 static void
1849 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1850 {
1851         if (on)
1852                 ixgbe_vlan_hw_strip_enable(dev, queue);
1853         else
1854                 ixgbe_vlan_hw_strip_disable(dev, queue);
1855 }
1856
1857 static int
1858 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1859                     enum rte_vlan_type vlan_type,
1860                     uint16_t tpid)
1861 {
1862         struct ixgbe_hw *hw =
1863                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864         int ret = 0;
1865         uint32_t reg;
1866         uint32_t qinq;
1867
1868         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1869         qinq &= IXGBE_DMATXCTL_GDV;
1870
1871         switch (vlan_type) {
1872         case ETH_VLAN_TYPE_INNER:
1873                 if (qinq) {
1874                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1875                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1876                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1877                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1878                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1879                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1880                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1881                 } else {
1882                         ret = -ENOTSUP;
1883                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1884                                     " by single VLAN");
1885                 }
1886                 break;
1887         case ETH_VLAN_TYPE_OUTER:
1888                 if (qinq) {
1889                         /* Only the high 16-bits is valid */
1890                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1891                                         IXGBE_EXVET_VET_EXT_SHIFT);
1892                 } else {
1893                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1894                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1895                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1896                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1897                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1898                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1899                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1900                 }
1901
1902                 break;
1903         default:
1904                 ret = -EINVAL;
1905                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1906                 break;
1907         }
1908
1909         return ret;
1910 }
1911
1912 void
1913 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1914 {
1915         struct ixgbe_hw *hw =
1916                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917         uint32_t vlnctrl;
1918
1919         PMD_INIT_FUNC_TRACE();
1920
1921         /* Filter Table Disable */
1922         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1923         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1924
1925         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1926 }
1927
1928 void
1929 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1930 {
1931         struct ixgbe_hw *hw =
1932                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933         struct ixgbe_vfta *shadow_vfta =
1934                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1935         uint32_t vlnctrl;
1936         uint16_t i;
1937
1938         PMD_INIT_FUNC_TRACE();
1939
1940         /* Filter Table Enable */
1941         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1942         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1943         vlnctrl |= IXGBE_VLNCTRL_VFE;
1944
1945         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1946
1947         /* write whatever is in local vfta copy */
1948         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1949                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1950 }
1951
1952 static void
1953 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1954 {
1955         struct ixgbe_hwstrip *hwstrip =
1956                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1957         struct ixgbe_rx_queue *rxq;
1958
1959         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1960                 return;
1961
1962         if (on)
1963                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1964         else
1965                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1966
1967         if (queue >= dev->data->nb_rx_queues)
1968                 return;
1969
1970         rxq = dev->data->rx_queues[queue];
1971
1972         if (on)
1973                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1974         else
1975                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1976 }
1977
1978 static void
1979 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1980 {
1981         struct ixgbe_hw *hw =
1982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983         uint32_t ctrl;
1984
1985         PMD_INIT_FUNC_TRACE();
1986
1987         if (hw->mac.type == ixgbe_mac_82598EB) {
1988                 /* No queue level support */
1989                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1990                 return;
1991         }
1992
1993         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1994         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1995         ctrl &= ~IXGBE_RXDCTL_VME;
1996         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1997
1998         /* record those setting for HW strip per queue */
1999         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2000 }
2001
2002 static void
2003 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2004 {
2005         struct ixgbe_hw *hw =
2006                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2007         uint32_t ctrl;
2008
2009         PMD_INIT_FUNC_TRACE();
2010
2011         if (hw->mac.type == ixgbe_mac_82598EB) {
2012                 /* No queue level supported */
2013                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2014                 return;
2015         }
2016
2017         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2018         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2019         ctrl |= IXGBE_RXDCTL_VME;
2020         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2021
2022         /* record those setting for HW strip per queue */
2023         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2024 }
2025
2026 void
2027 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2028 {
2029         struct ixgbe_hw *hw =
2030                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031         uint32_t ctrl;
2032         uint16_t i;
2033         struct ixgbe_rx_queue *rxq;
2034
2035         PMD_INIT_FUNC_TRACE();
2036
2037         if (hw->mac.type == ixgbe_mac_82598EB) {
2038                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2039                 ctrl &= ~IXGBE_VLNCTRL_VME;
2040                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2041         } else {
2042                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2043                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2044                         rxq = dev->data->rx_queues[i];
2045                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2046                         ctrl &= ~IXGBE_RXDCTL_VME;
2047                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2048
2049                         /* record those setting for HW strip per queue */
2050                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2051                 }
2052         }
2053 }
2054
2055 void
2056 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2057 {
2058         struct ixgbe_hw *hw =
2059                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060         uint32_t ctrl;
2061         uint16_t i;
2062         struct ixgbe_rx_queue *rxq;
2063
2064         PMD_INIT_FUNC_TRACE();
2065
2066         if (hw->mac.type == ixgbe_mac_82598EB) {
2067                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2068                 ctrl |= IXGBE_VLNCTRL_VME;
2069                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2070         } else {
2071                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2072                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2073                         rxq = dev->data->rx_queues[i];
2074                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2075                         ctrl |= IXGBE_RXDCTL_VME;
2076                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2077
2078                         /* record those setting for HW strip per queue */
2079                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2080                 }
2081         }
2082 }
2083
2084 static void
2085 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2086 {
2087         struct ixgbe_hw *hw =
2088                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089         uint32_t ctrl;
2090
2091         PMD_INIT_FUNC_TRACE();
2092
2093         /* DMATXCTRL: Geric Double VLAN Disable */
2094         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2095         ctrl &= ~IXGBE_DMATXCTL_GDV;
2096         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2097
2098         /* CTRL_EXT: Global Double VLAN Disable */
2099         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2100         ctrl &= ~IXGBE_EXTENDED_VLAN;
2101         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2102
2103 }
2104
2105 static void
2106 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2107 {
2108         struct ixgbe_hw *hw =
2109                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110         uint32_t ctrl;
2111
2112         PMD_INIT_FUNC_TRACE();
2113
2114         /* DMATXCTRL: Geric Double VLAN Enable */
2115         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2116         ctrl |= IXGBE_DMATXCTL_GDV;
2117         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2118
2119         /* CTRL_EXT: Global Double VLAN Enable */
2120         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2121         ctrl |= IXGBE_EXTENDED_VLAN;
2122         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2123
2124         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2125         if (hw->mac.type == ixgbe_mac_X550 ||
2126             hw->mac.type == ixgbe_mac_X550EM_x ||
2127             hw->mac.type == ixgbe_mac_X550EM_a) {
2128                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2129                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2130                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2131         }
2132
2133         /*
2134          * VET EXT field in the EXVET register = 0x8100 by default
2135          * So no need to change. Same to VT field of DMATXCTL register
2136          */
2137 }
2138
2139 static void
2140 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2141 {
2142         if (mask & ETH_VLAN_STRIP_MASK) {
2143                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2144                         ixgbe_vlan_hw_strip_enable_all(dev);
2145                 else
2146                         ixgbe_vlan_hw_strip_disable_all(dev);
2147         }
2148
2149         if (mask & ETH_VLAN_FILTER_MASK) {
2150                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2151                         ixgbe_vlan_hw_filter_enable(dev);
2152                 else
2153                         ixgbe_vlan_hw_filter_disable(dev);
2154         }
2155
2156         if (mask & ETH_VLAN_EXTEND_MASK) {
2157                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2158                         ixgbe_vlan_hw_extend_enable(dev);
2159                 else
2160                         ixgbe_vlan_hw_extend_disable(dev);
2161         }
2162 }
2163
2164 static void
2165 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2166 {
2167         struct ixgbe_hw *hw =
2168                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2170         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2171
2172         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2173         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2174 }
2175
2176 static int
2177 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2178 {
2179         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2180
2181         switch (nb_rx_q) {
2182         case 1:
2183         case 2:
2184                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2185                 break;
2186         case 4:
2187                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2188                 break;
2189         default:
2190                 return -EINVAL;
2191         }
2192
2193         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2194         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2195
2196         return 0;
2197 }
2198
2199 static int
2200 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2201 {
2202         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2205         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2206
2207         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2208                 /* check multi-queue mode */
2209                 switch (dev_conf->rxmode.mq_mode) {
2210                 case ETH_MQ_RX_VMDQ_DCB:
2211                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2212                         break;
2213                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2214                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2215                         PMD_INIT_LOG(ERR, "SRIOV active,"
2216                                         " unsupported mq_mode rx %d.",
2217                                         dev_conf->rxmode.mq_mode);
2218                         return -EINVAL;
2219                 case ETH_MQ_RX_RSS:
2220                 case ETH_MQ_RX_VMDQ_RSS:
2221                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2222                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2223                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2224                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2225                                                 " invalid queue number"
2226                                                 " for VMDQ RSS, allowed"
2227                                                 " value are 1, 2 or 4.");
2228                                         return -EINVAL;
2229                                 }
2230                         break;
2231                 case ETH_MQ_RX_VMDQ_ONLY:
2232                 case ETH_MQ_RX_NONE:
2233                         /* if nothing mq mode configure, use default scheme */
2234                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2235                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2236                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2237                         break;
2238                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2239                         /* SRIOV only works in VMDq enable mode */
2240                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2241                                         " wrong mq_mode rx %d.",
2242                                         dev_conf->rxmode.mq_mode);
2243                         return -EINVAL;
2244                 }
2245
2246                 switch (dev_conf->txmode.mq_mode) {
2247                 case ETH_MQ_TX_VMDQ_DCB:
2248                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2249                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2250                         break;
2251                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2252                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2253                         break;
2254                 }
2255
2256                 /* check valid queue number */
2257                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2258                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2259                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2260                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2261                                         " must be less than or equal to %d.",
2262                                         nb_rx_q, nb_tx_q,
2263                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2264                         return -EINVAL;
2265                 }
2266         } else {
2267                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2268                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2269                                           " not supported.");
2270                         return -EINVAL;
2271                 }
2272                 /* check configuration for vmdb+dcb mode */
2273                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2274                         const struct rte_eth_vmdq_dcb_conf *conf;
2275
2276                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2277                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2278                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2279                                 return -EINVAL;
2280                         }
2281                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2282                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2283                                conf->nb_queue_pools == ETH_32_POOLS)) {
2284                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2285                                                 " nb_queue_pools must be %d or %d.",
2286                                                 ETH_16_POOLS, ETH_32_POOLS);
2287                                 return -EINVAL;
2288                         }
2289                 }
2290                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2291                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2292
2293                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2294                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2295                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2296                                 return -EINVAL;
2297                         }
2298                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2299                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2300                                conf->nb_queue_pools == ETH_32_POOLS)) {
2301                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2302                                                 " nb_queue_pools != %d and"
2303                                                 " nb_queue_pools != %d.",
2304                                                 ETH_16_POOLS, ETH_32_POOLS);
2305                                 return -EINVAL;
2306                         }
2307                 }
2308
2309                 /* For DCB mode check our configuration before we go further */
2310                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2311                         const struct rte_eth_dcb_rx_conf *conf;
2312
2313                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2314                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2315                                                  IXGBE_DCB_NB_QUEUES);
2316                                 return -EINVAL;
2317                         }
2318                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2319                         if (!(conf->nb_tcs == ETH_4_TCS ||
2320                                conf->nb_tcs == ETH_8_TCS)) {
2321                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2322                                                 " and nb_tcs != %d.",
2323                                                 ETH_4_TCS, ETH_8_TCS);
2324                                 return -EINVAL;
2325                         }
2326                 }
2327
2328                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2329                         const struct rte_eth_dcb_tx_conf *conf;
2330
2331                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2332                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2333                                                  IXGBE_DCB_NB_QUEUES);
2334                                 return -EINVAL;
2335                         }
2336                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2337                         if (!(conf->nb_tcs == ETH_4_TCS ||
2338                                conf->nb_tcs == ETH_8_TCS)) {
2339                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2340                                                 " and nb_tcs != %d.",
2341                                                 ETH_4_TCS, ETH_8_TCS);
2342                                 return -EINVAL;
2343                         }
2344                 }
2345
2346                 /*
2347                  * When DCB/VT is off, maximum number of queues changes,
2348                  * except for 82598EB, which remains constant.
2349                  */
2350                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2351                                 hw->mac.type != ixgbe_mac_82598EB) {
2352                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2353                                 PMD_INIT_LOG(ERR,
2354                                              "Neither VT nor DCB are enabled, "
2355                                              "nb_tx_q > %d.",
2356                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2357                                 return -EINVAL;
2358                         }
2359                 }
2360         }
2361         return 0;
2362 }
2363
2364 static int
2365 ixgbe_dev_configure(struct rte_eth_dev *dev)
2366 {
2367         struct ixgbe_interrupt *intr =
2368                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2369         struct ixgbe_adapter *adapter =
2370                 (struct ixgbe_adapter *)dev->data->dev_private;
2371         int ret;
2372
2373         PMD_INIT_FUNC_TRACE();
2374         /* multipe queue mode checking */
2375         ret  = ixgbe_check_mq_mode(dev);
2376         if (ret != 0) {
2377                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2378                             ret);
2379                 return ret;
2380         }
2381
2382         /* set flag to update link status after init */
2383         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2384
2385         /*
2386          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2387          * allocation or vector Rx preconditions we will reset it.
2388          */
2389         adapter->rx_bulk_alloc_allowed = true;
2390         adapter->rx_vec_allowed = true;
2391
2392         return 0;
2393 }
2394
2395 static void
2396 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2397 {
2398         struct ixgbe_hw *hw =
2399                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400         struct ixgbe_interrupt *intr =
2401                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2402         uint32_t gpie;
2403
2404         /* only set up it on X550EM_X */
2405         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2406                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2407                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2408                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2409                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2410                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2411         }
2412 }
2413
2414 int
2415 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2416                         uint16_t tx_rate, uint64_t q_msk)
2417 {
2418         struct ixgbe_hw *hw;
2419         struct ixgbe_vf_info *vfinfo;
2420         struct rte_eth_link link;
2421         uint8_t  nb_q_per_pool;
2422         uint32_t queue_stride;
2423         uint32_t queue_idx, idx = 0, vf_idx;
2424         uint32_t queue_end;
2425         uint16_t total_rate = 0;
2426         struct rte_pci_device *pci_dev;
2427
2428         pci_dev = IXGBE_DEV_TO_PCI(dev);
2429         rte_eth_link_get_nowait(dev->data->port_id, &link);
2430
2431         if (vf >= pci_dev->max_vfs)
2432                 return -EINVAL;
2433
2434         if (tx_rate > link.link_speed)
2435                 return -EINVAL;
2436
2437         if (q_msk == 0)
2438                 return 0;
2439
2440         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2442         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2443         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2444         queue_idx = vf * queue_stride;
2445         queue_end = queue_idx + nb_q_per_pool - 1;
2446         if (queue_end >= hw->mac.max_tx_queues)
2447                 return -EINVAL;
2448
2449         if (vfinfo) {
2450                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2451                         if (vf_idx == vf)
2452                                 continue;
2453                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2454                                 idx++)
2455                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2456                 }
2457         } else {
2458                 return -EINVAL;
2459         }
2460
2461         /* Store tx_rate for this vf. */
2462         for (idx = 0; idx < nb_q_per_pool; idx++) {
2463                 if (((uint64_t)0x1 << idx) & q_msk) {
2464                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2465                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2466                         total_rate += tx_rate;
2467                 }
2468         }
2469
2470         if (total_rate > dev->data->dev_link.link_speed) {
2471                 /* Reset stored TX rate of the VF if it causes exceed
2472                  * link speed.
2473                  */
2474                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2475                 return -EINVAL;
2476         }
2477
2478         /* Set RTTBCNRC of each queue/pool for vf X  */
2479         for (; queue_idx <= queue_end; queue_idx++) {
2480                 if (0x1 & q_msk)
2481                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2482                 q_msk = q_msk >> 1;
2483         }
2484
2485         return 0;
2486 }
2487
2488 /*
2489  * Configure device link speed and setup link.
2490  * It returns 0 on success.
2491  */
2492 static int
2493 ixgbe_dev_start(struct rte_eth_dev *dev)
2494 {
2495         struct ixgbe_hw *hw =
2496                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2497         struct ixgbe_vf_info *vfinfo =
2498                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2499         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2500         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2501         uint32_t intr_vector = 0;
2502         int err, link_up = 0, negotiate = 0;
2503         uint32_t speed = 0;
2504         int mask = 0;
2505         int status;
2506         uint16_t vf, idx;
2507         uint32_t *link_speeds;
2508
2509         PMD_INIT_FUNC_TRACE();
2510
2511         /* IXGBE devices don't support:
2512         *    - half duplex (checked afterwards for valid speeds)
2513         *    - fixed speed: TODO implement
2514         */
2515         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2516                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2517                              dev->data->port_id);
2518                 return -EINVAL;
2519         }
2520
2521         /* disable uio/vfio intr/eventfd mapping */
2522         rte_intr_disable(intr_handle);
2523
2524         /* stop adapter */
2525         hw->adapter_stopped = 0;
2526         ixgbe_stop_adapter(hw);
2527
2528         /* reinitialize adapter
2529          * this calls reset and start
2530          */
2531         status = ixgbe_pf_reset_hw(hw);
2532         if (status != 0)
2533                 return -1;
2534         hw->mac.ops.start_hw(hw);
2535         hw->mac.get_link_status = true;
2536
2537         /* configure PF module if SRIOV enabled */
2538         ixgbe_pf_host_configure(dev);
2539
2540         ixgbe_dev_phy_intr_setup(dev);
2541
2542         /* check and configure queue intr-vector mapping */
2543         if ((rte_intr_cap_multiple(intr_handle) ||
2544              !RTE_ETH_DEV_SRIOV(dev).active) &&
2545             dev->data->dev_conf.intr_conf.rxq != 0) {
2546                 intr_vector = dev->data->nb_rx_queues;
2547                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2548                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2549                                         IXGBE_MAX_INTR_QUEUE_NUM);
2550                         return -ENOTSUP;
2551                 }
2552                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2553                         return -1;
2554         }
2555
2556         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2557                 intr_handle->intr_vec =
2558                         rte_zmalloc("intr_vec",
2559                                     dev->data->nb_rx_queues * sizeof(int), 0);
2560                 if (intr_handle->intr_vec == NULL) {
2561                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2562                                      " intr_vec", dev->data->nb_rx_queues);
2563                         return -ENOMEM;
2564                 }
2565         }
2566
2567         /* confiugre msix for sleep until rx interrupt */
2568         ixgbe_configure_msix(dev);
2569
2570         /* initialize transmission unit */
2571         ixgbe_dev_tx_init(dev);
2572
2573         /* This can fail when allocating mbufs for descriptor rings */
2574         err = ixgbe_dev_rx_init(dev);
2575         if (err) {
2576                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2577                 goto error;
2578         }
2579
2580     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2581                 ETH_VLAN_EXTEND_MASK;
2582         ixgbe_vlan_offload_set(dev, mask);
2583
2584         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2585                 /* Enable vlan filtering for VMDq */
2586                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2587         }
2588
2589         /* Configure DCB hw */
2590         ixgbe_configure_dcb(dev);
2591
2592         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2593                 err = ixgbe_fdir_configure(dev);
2594                 if (err)
2595                         goto error;
2596         }
2597
2598         /* Restore vf rate limit */
2599         if (vfinfo != NULL) {
2600                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2601                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2602                                 if (vfinfo[vf].tx_rate[idx] != 0)
2603                                         ixgbe_set_vf_rate_limit(
2604                                                 dev, vf,
2605                                                 vfinfo[vf].tx_rate[idx],
2606                                                 1 << idx);
2607         }
2608
2609         ixgbe_restore_statistics_mapping(dev);
2610
2611         err = ixgbe_dev_rxtx_start(dev);
2612         if (err < 0) {
2613                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2614                 goto error;
2615         }
2616
2617         /* Skip link setup if loopback mode is enabled for 82599. */
2618         if (hw->mac.type == ixgbe_mac_82599EB &&
2619                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2620                 goto skip_link_setup;
2621
2622         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2623                 err = hw->mac.ops.setup_sfp(hw);
2624                 if (err)
2625                         goto error;
2626         }
2627
2628         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2629                 /* Turn on the copper */
2630                 ixgbe_set_phy_power(hw, true);
2631         } else {
2632                 /* Turn on the laser */
2633                 ixgbe_enable_tx_laser(hw);
2634         }
2635
2636         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2637         if (err)
2638                 goto error;
2639         dev->data->dev_link.link_status = link_up;
2640
2641         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2642         if (err)
2643                 goto error;
2644
2645         link_speeds = &dev->data->dev_conf.link_speeds;
2646         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2647                         ETH_LINK_SPEED_10G)) {
2648                 PMD_INIT_LOG(ERR, "Invalid link setting");
2649                 goto error;
2650         }
2651
2652         speed = 0x0;
2653         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2654                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2655                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2656                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2657         } else {
2658                 if (*link_speeds & ETH_LINK_SPEED_10G)
2659                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2660                 if (*link_speeds & ETH_LINK_SPEED_1G)
2661                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2662                 if (*link_speeds & ETH_LINK_SPEED_100M)
2663                         speed |= IXGBE_LINK_SPEED_100_FULL;
2664         }
2665
2666         err = ixgbe_setup_link(hw, speed, link_up);
2667         if (err)
2668                 goto error;
2669
2670 skip_link_setup:
2671
2672         if (rte_intr_allow_others(intr_handle)) {
2673                 /* check if lsc interrupt is enabled */
2674                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2675                         ixgbe_dev_lsc_interrupt_setup(dev);
2676                 ixgbe_dev_macsec_interrupt_setup(dev);
2677         } else {
2678                 rte_intr_callback_unregister(intr_handle,
2679                                              ixgbe_dev_interrupt_handler, dev);
2680                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2681                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2682                                      " no intr multiplex");
2683         }
2684
2685         /* check if rxq interrupt is enabled */
2686         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2687             rte_intr_dp_is_en(intr_handle))
2688                 ixgbe_dev_rxq_interrupt_setup(dev);
2689
2690         /* enable uio/vfio intr/eventfd mapping */
2691         rte_intr_enable(intr_handle);
2692
2693         /* resume enabled intr since hw reset */
2694         ixgbe_enable_intr(dev);
2695         ixgbe_l2_tunnel_conf(dev);
2696         ixgbe_filter_restore(dev);
2697
2698         return 0;
2699
2700 error:
2701         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2702         ixgbe_dev_clear_queues(dev);
2703         return -EIO;
2704 }
2705
2706 /*
2707  * Stop device: disable rx and tx functions to allow for reconfiguring.
2708  */
2709 static void
2710 ixgbe_dev_stop(struct rte_eth_dev *dev)
2711 {
2712         struct rte_eth_link link;
2713         struct ixgbe_hw *hw =
2714                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2715         struct ixgbe_vf_info *vfinfo =
2716                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2717         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2718         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2719         int vf;
2720
2721         PMD_INIT_FUNC_TRACE();
2722
2723         /* disable interrupts */
2724         ixgbe_disable_intr(hw);
2725
2726         /* reset the NIC */
2727         ixgbe_pf_reset_hw(hw);
2728         hw->adapter_stopped = 0;
2729
2730         /* stop adapter */
2731         ixgbe_stop_adapter(hw);
2732
2733         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2734                 vfinfo[vf].clear_to_send = false;
2735
2736         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2737                 /* Turn off the copper */
2738                 ixgbe_set_phy_power(hw, false);
2739         } else {
2740                 /* Turn off the laser */
2741                 ixgbe_disable_tx_laser(hw);
2742         }
2743
2744         ixgbe_dev_clear_queues(dev);
2745
2746         /* Clear stored conf */
2747         dev->data->scattered_rx = 0;
2748         dev->data->lro = 0;
2749
2750         /* Clear recorded link status */
2751         memset(&link, 0, sizeof(link));
2752         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2753
2754         if (!rte_intr_allow_others(intr_handle))
2755                 /* resume to the default handler */
2756                 rte_intr_callback_register(intr_handle,
2757                                            ixgbe_dev_interrupt_handler,
2758                                            (void *)dev);
2759
2760         /* Clean datapath event and queue/vec mapping */
2761         rte_intr_efd_disable(intr_handle);
2762         if (intr_handle->intr_vec != NULL) {
2763                 rte_free(intr_handle->intr_vec);
2764                 intr_handle->intr_vec = NULL;
2765         }
2766 }
2767
2768 /*
2769  * Set device link up: enable tx.
2770  */
2771 static int
2772 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2773 {
2774         struct ixgbe_hw *hw =
2775                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2776         if (hw->mac.type == ixgbe_mac_82599EB) {
2777 #ifdef RTE_NIC_BYPASS
2778                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2779                         /* Not suported in bypass mode */
2780                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2781                                      "by device id 0x%x", hw->device_id);
2782                         return -ENOTSUP;
2783                 }
2784 #endif
2785         }
2786
2787         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2788                 /* Turn on the copper */
2789                 ixgbe_set_phy_power(hw, true);
2790         } else {
2791                 /* Turn on the laser */
2792                 ixgbe_enable_tx_laser(hw);
2793         }
2794
2795         return 0;
2796 }
2797
2798 /*
2799  * Set device link down: disable tx.
2800  */
2801 static int
2802 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2803 {
2804         struct ixgbe_hw *hw =
2805                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806         if (hw->mac.type == ixgbe_mac_82599EB) {
2807 #ifdef RTE_NIC_BYPASS
2808                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2809                         /* Not suported in bypass mode */
2810                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2811                                      "by device id 0x%x", hw->device_id);
2812                         return -ENOTSUP;
2813                 }
2814 #endif
2815         }
2816
2817         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2818                 /* Turn off the copper */
2819                 ixgbe_set_phy_power(hw, false);
2820         } else {
2821                 /* Turn off the laser */
2822                 ixgbe_disable_tx_laser(hw);
2823         }
2824
2825         return 0;
2826 }
2827
2828 /*
2829  * Reest and stop device.
2830  */
2831 static void
2832 ixgbe_dev_close(struct rte_eth_dev *dev)
2833 {
2834         struct ixgbe_hw *hw =
2835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836
2837         PMD_INIT_FUNC_TRACE();
2838
2839         ixgbe_pf_reset_hw(hw);
2840
2841         ixgbe_dev_stop(dev);
2842         hw->adapter_stopped = 1;
2843
2844         ixgbe_dev_free_queues(dev);
2845
2846         ixgbe_disable_pcie_master(hw);
2847
2848         /* reprogram the RAR[0] in case user changed it. */
2849         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2850 }
2851
2852 static void
2853 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2854                            struct ixgbe_hw_stats *hw_stats,
2855                            struct ixgbe_macsec_stats *macsec_stats,
2856                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2857                            uint64_t *total_qprc, uint64_t *total_qprdc)
2858 {
2859         uint32_t bprc, lxon, lxoff, total;
2860         uint32_t delta_gprc = 0;
2861         unsigned i;
2862         /* Workaround for RX byte count not including CRC bytes when CRC
2863          * strip is enabled. CRC bytes are removed from counters when crc_strip
2864          * is disabled.
2865          */
2866         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2867                         IXGBE_HLREG0_RXCRCSTRP);
2868
2869         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2870         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2871         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2872         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2873
2874         for (i = 0; i < 8; i++) {
2875                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2876
2877                 /* global total per queue */
2878                 hw_stats->mpc[i] += mp;
2879                 /* Running comprehensive total for stats display */
2880                 *total_missed_rx += hw_stats->mpc[i];
2881                 if (hw->mac.type == ixgbe_mac_82598EB) {
2882                         hw_stats->rnbc[i] +=
2883                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2884                         hw_stats->pxonrxc[i] +=
2885                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2886                         hw_stats->pxoffrxc[i] +=
2887                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2888                 } else {
2889                         hw_stats->pxonrxc[i] +=
2890                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2891                         hw_stats->pxoffrxc[i] +=
2892                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2893                         hw_stats->pxon2offc[i] +=
2894                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2895                 }
2896                 hw_stats->pxontxc[i] +=
2897                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2898                 hw_stats->pxofftxc[i] +=
2899                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2900         }
2901         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2902                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2903                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2904                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2905
2906                 delta_gprc += delta_qprc;
2907
2908                 hw_stats->qprc[i] += delta_qprc;
2909                 hw_stats->qptc[i] += delta_qptc;
2910
2911                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2912                 hw_stats->qbrc[i] +=
2913                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2914                 if (crc_strip == 0)
2915                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2916
2917                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2918                 hw_stats->qbtc[i] +=
2919                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2920
2921                 hw_stats->qprdc[i] += delta_qprdc;
2922                 *total_qprdc += hw_stats->qprdc[i];
2923
2924                 *total_qprc += hw_stats->qprc[i];
2925                 *total_qbrc += hw_stats->qbrc[i];
2926         }
2927         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2928         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2929         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2930
2931         /*
2932          * An errata states that gprc actually counts good + missed packets:
2933          * Workaround to set gprc to summated queue packet receives
2934          */
2935         hw_stats->gprc = *total_qprc;
2936
2937         if (hw->mac.type != ixgbe_mac_82598EB) {
2938                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2939                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2940                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2941                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2942                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2943                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2944                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2945                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2946         } else {
2947                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2948                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2949                 /* 82598 only has a counter in the high register */
2950                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2951                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2952                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2953         }
2954         uint64_t old_tpr = hw_stats->tpr;
2955
2956         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2957         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2958
2959         if (crc_strip == 0)
2960                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2961
2962         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2963         hw_stats->gptc += delta_gptc;
2964         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2965         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2966
2967         /*
2968          * Workaround: mprc hardware is incorrectly counting
2969          * broadcasts, so for now we subtract those.
2970          */
2971         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2972         hw_stats->bprc += bprc;
2973         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2974         if (hw->mac.type == ixgbe_mac_82598EB)
2975                 hw_stats->mprc -= bprc;
2976
2977         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2978         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2979         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2980         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2981         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2982         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2983
2984         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2985         hw_stats->lxontxc += lxon;
2986         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2987         hw_stats->lxofftxc += lxoff;
2988         total = lxon + lxoff;
2989
2990         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2991         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2992         hw_stats->gptc -= total;
2993         hw_stats->mptc -= total;
2994         hw_stats->ptc64 -= total;
2995         hw_stats->gotc -= total * ETHER_MIN_LEN;
2996
2997         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2998         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2999         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3000         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3001         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3002         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3003         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3004         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3005         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3006         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3007         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3008         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3009         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3010         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3011         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3012         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3013         /* Only read FCOE on 82599 */
3014         if (hw->mac.type != ixgbe_mac_82598EB) {
3015                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3016                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3017                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3018                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3019                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3020         }
3021
3022         /* Flow Director Stats registers */
3023         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3024         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3025
3026         /* MACsec Stats registers */
3027         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3028         macsec_stats->out_pkts_encrypted +=
3029                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3030         macsec_stats->out_pkts_protected +=
3031                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3032         macsec_stats->out_octets_encrypted +=
3033                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3034         macsec_stats->out_octets_protected +=
3035                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3036         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3037         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3038         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3039         macsec_stats->in_pkts_unknownsci +=
3040                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3041         macsec_stats->in_octets_decrypted +=
3042                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3043         macsec_stats->in_octets_validated +=
3044                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3045         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3046         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3047         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3048         for (i = 0; i < 2; i++) {
3049                 macsec_stats->in_pkts_ok +=
3050                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3051                 macsec_stats->in_pkts_invalid +=
3052                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3053                 macsec_stats->in_pkts_notvalid +=
3054                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3055         }
3056         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3057         macsec_stats->in_pkts_notusingsa +=
3058                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3059 }
3060
3061 /*
3062  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3063  */
3064 static void
3065 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3066 {
3067         struct ixgbe_hw *hw =
3068                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069         struct ixgbe_hw_stats *hw_stats =
3070                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3071         struct ixgbe_macsec_stats *macsec_stats =
3072                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3073                                 dev->data->dev_private);
3074         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3075         unsigned i;
3076
3077         total_missed_rx = 0;
3078         total_qbrc = 0;
3079         total_qprc = 0;
3080         total_qprdc = 0;
3081
3082         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3083                         &total_qbrc, &total_qprc, &total_qprdc);
3084
3085         if (stats == NULL)
3086                 return;
3087
3088         /* Fill out the rte_eth_stats statistics structure */
3089         stats->ipackets = total_qprc;
3090         stats->ibytes = total_qbrc;
3091         stats->opackets = hw_stats->gptc;
3092         stats->obytes = hw_stats->gotc;
3093
3094         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3095                 stats->q_ipackets[i] = hw_stats->qprc[i];
3096                 stats->q_opackets[i] = hw_stats->qptc[i];
3097                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3098                 stats->q_obytes[i] = hw_stats->qbtc[i];
3099                 stats->q_errors[i] = hw_stats->qprdc[i];
3100         }
3101
3102         /* Rx Errors */
3103         stats->imissed  = total_missed_rx;
3104         stats->ierrors  = hw_stats->crcerrs +
3105                           hw_stats->mspdc +
3106                           hw_stats->rlec +
3107                           hw_stats->ruc +
3108                           hw_stats->roc +
3109                           hw_stats->illerrc +
3110                           hw_stats->errbc +
3111                           hw_stats->rfc +
3112                           hw_stats->fccrc +
3113                           hw_stats->fclast;
3114
3115         /* Tx Errors */
3116         stats->oerrors  = 0;
3117 }
3118
3119 static void
3120 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3121 {
3122         struct ixgbe_hw_stats *stats =
3123                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3124
3125         /* HW registers are cleared on read */
3126         ixgbe_dev_stats_get(dev, NULL);
3127
3128         /* Reset software totals */
3129         memset(stats, 0, sizeof(*stats));
3130 }
3131
3132 /* This function calculates the number of xstats based on the current config */
3133 static unsigned
3134 ixgbe_xstats_calc_num(void) {
3135         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3136                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3137                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3138 }
3139
3140 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3141         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3142 {
3143         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3144         unsigned stat, i, count;
3145
3146         if (xstats_names != NULL) {
3147                 count = 0;
3148
3149                 /* Note: limit >= cnt_stats checked upstream
3150                  * in rte_eth_xstats_names()
3151                  */
3152
3153                 /* Extended stats from ixgbe_hw_stats */
3154                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3155                         snprintf(xstats_names[count].name,
3156                                 sizeof(xstats_names[count].name),
3157                                 "%s",
3158                                 rte_ixgbe_stats_strings[i].name);
3159                         count++;
3160                 }
3161
3162                 /* MACsec Stats */
3163                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3164                         snprintf(xstats_names[count].name,
3165                                 sizeof(xstats_names[count].name),
3166                                 "%s",
3167                                 rte_ixgbe_macsec_strings[i].name);
3168                         count++;
3169                 }
3170
3171                 /* RX Priority Stats */
3172                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3173                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3174                                 snprintf(xstats_names[count].name,
3175                                         sizeof(xstats_names[count].name),
3176                                         "rx_priority%u_%s", i,
3177                                         rte_ixgbe_rxq_strings[stat].name);
3178                                 count++;
3179                         }
3180                 }
3181
3182                 /* TX Priority Stats */
3183                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3184                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3185                                 snprintf(xstats_names[count].name,
3186                                         sizeof(xstats_names[count].name),
3187                                         "tx_priority%u_%s", i,
3188                                         rte_ixgbe_txq_strings[stat].name);
3189                                 count++;
3190                         }
3191                 }
3192         }
3193         return cnt_stats;
3194 }
3195
3196 static int ixgbe_dev_xstats_get_names_by_id(
3197         __rte_unused struct rte_eth_dev *dev,
3198         struct rte_eth_xstat_name *xstats_names,
3199         const uint64_t *ids,
3200         unsigned int limit)
3201 {
3202         if (!ids) {
3203                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3204                 unsigned int stat, i, count;
3205
3206                 if (xstats_names != NULL) {
3207                         count = 0;
3208
3209                         /* Note: limit >= cnt_stats checked upstream
3210                          * in rte_eth_xstats_names()
3211                          */
3212
3213                         /* Extended stats from ixgbe_hw_stats */
3214                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3215                                 snprintf(xstats_names[count].name,
3216                                         sizeof(xstats_names[count].name),
3217                                         "%s",
3218                                         rte_ixgbe_stats_strings[i].name);
3219                                 count++;
3220                         }
3221
3222                         /* MACsec Stats */
3223                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3224                                 snprintf(xstats_names[count].name,
3225                                         sizeof(xstats_names[count].name),
3226                                         "%s",
3227                                         rte_ixgbe_macsec_strings[i].name);
3228                                 count++;
3229                         }
3230
3231                         /* RX Priority Stats */
3232                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3233                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3234                                         snprintf(xstats_names[count].name,
3235                                             sizeof(xstats_names[count].name),
3236                                             "rx_priority%u_%s", i,
3237                                             rte_ixgbe_rxq_strings[stat].name);
3238                                         count++;
3239                                 }
3240                         }
3241
3242                         /* TX Priority Stats */
3243                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3244                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3245                                         snprintf(xstats_names[count].name,
3246                                             sizeof(xstats_names[count].name),
3247                                             "tx_priority%u_%s", i,
3248                                             rte_ixgbe_txq_strings[stat].name);
3249                                         count++;
3250                                 }
3251                         }
3252                 }
3253                 return cnt_stats;
3254         }
3255
3256         uint16_t i;
3257         uint16_t size = ixgbe_xstats_calc_num();
3258         struct rte_eth_xstat_name xstats_names_copy[size];
3259
3260         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3261                         size);
3262
3263         for (i = 0; i < limit; i++) {
3264                 if (ids[i] >= size) {
3265                         PMD_INIT_LOG(ERR, "id value isn't valid");
3266                         return -1;
3267                 }
3268                 strcpy(xstats_names[i].name,
3269                                 xstats_names_copy[ids[i]].name);
3270         }
3271         return limit;
3272 }
3273
3274 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3275         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3276 {
3277         unsigned i;
3278
3279         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3280                 return -ENOMEM;
3281
3282         if (xstats_names != NULL)
3283                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3284                         snprintf(xstats_names[i].name,
3285                                 sizeof(xstats_names[i].name),
3286                                 "%s", rte_ixgbevf_stats_strings[i].name);
3287         return IXGBEVF_NB_XSTATS;
3288 }
3289
3290 static int
3291 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3292                                          unsigned n)
3293 {
3294         struct ixgbe_hw *hw =
3295                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296         struct ixgbe_hw_stats *hw_stats =
3297                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3298         struct ixgbe_macsec_stats *macsec_stats =
3299                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3300                                 dev->data->dev_private);
3301         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3302         unsigned i, stat, count = 0;
3303
3304         count = ixgbe_xstats_calc_num();
3305
3306         if (n < count)
3307                 return count;
3308
3309         total_missed_rx = 0;
3310         total_qbrc = 0;
3311         total_qprc = 0;
3312         total_qprdc = 0;
3313
3314         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3315                         &total_qbrc, &total_qprc, &total_qprdc);
3316
3317         /* If this is a reset xstats is NULL, and we have cleared the
3318          * registers by reading them.
3319          */
3320         if (!xstats)
3321                 return 0;
3322
3323         /* Extended stats from ixgbe_hw_stats */
3324         count = 0;
3325         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3326                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3327                                 rte_ixgbe_stats_strings[i].offset);
3328                 xstats[count].id = count;
3329                 count++;
3330         }
3331
3332         /* MACsec Stats */
3333         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3334                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3335                                 rte_ixgbe_macsec_strings[i].offset);
3336                 xstats[count].id = count;
3337                 count++;
3338         }
3339
3340         /* RX Priority Stats */
3341         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3342                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3343                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3344                                         rte_ixgbe_rxq_strings[stat].offset +
3345                                         (sizeof(uint64_t) * i));
3346                         xstats[count].id = count;
3347                         count++;
3348                 }
3349         }
3350
3351         /* TX Priority Stats */
3352         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3353                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3354                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3355                                         rte_ixgbe_txq_strings[stat].offset +
3356                                         (sizeof(uint64_t) * i));
3357                         xstats[count].id = count;
3358                         count++;
3359                 }
3360         }
3361         return count;
3362 }
3363
3364 static int
3365 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3366                 uint64_t *values, unsigned int n)
3367 {
3368         if (!ids) {
3369                 struct ixgbe_hw *hw =
3370                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3371                 struct ixgbe_hw_stats *hw_stats =
3372                                 IXGBE_DEV_PRIVATE_TO_STATS(
3373                                                 dev->data->dev_private);
3374                 struct ixgbe_macsec_stats *macsec_stats =
3375                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3376                                         dev->data->dev_private);
3377                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3378                 unsigned int i, stat, count = 0;
3379
3380                 count = ixgbe_xstats_calc_num();
3381
3382                 if (!ids && n < count)
3383                         return count;
3384
3385                 total_missed_rx = 0;
3386                 total_qbrc = 0;
3387                 total_qprc = 0;
3388                 total_qprdc = 0;
3389
3390                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3391                                 &total_missed_rx, &total_qbrc, &total_qprc,
3392                                 &total_qprdc);
3393
3394                 /* If this is a reset xstats is NULL, and we have cleared the
3395                  * registers by reading them.
3396                  */
3397                 if (!ids && !values)
3398                         return 0;
3399
3400                 /* Extended stats from ixgbe_hw_stats */
3401                 count = 0;
3402                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3403                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3404                                         rte_ixgbe_stats_strings[i].offset);
3405                         count++;
3406                 }
3407
3408                 /* MACsec Stats */
3409                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3410                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3411                                         rte_ixgbe_macsec_strings[i].offset);
3412                         count++;
3413                 }
3414
3415                 /* RX Priority Stats */
3416                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3417                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3418                                 values[count] =
3419                                         *(uint64_t *)(((char *)hw_stats) +
3420                                         rte_ixgbe_rxq_strings[stat].offset +
3421                                         (sizeof(uint64_t) * i));
3422                                 count++;
3423                         }
3424                 }
3425
3426                 /* TX Priority Stats */
3427                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3428                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3429                                 values[count] =
3430                                         *(uint64_t *)(((char *)hw_stats) +
3431                                         rte_ixgbe_txq_strings[stat].offset +
3432                                         (sizeof(uint64_t) * i));
3433                                 count++;
3434                         }
3435                 }
3436                 return count;
3437         }
3438
3439         uint16_t i;
3440         uint16_t size = ixgbe_xstats_calc_num();
3441         uint64_t values_copy[size];
3442
3443         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3444
3445         for (i = 0; i < n; i++) {
3446                 if (ids[i] >= size) {
3447                         PMD_INIT_LOG(ERR, "id value isn't valid");
3448                         return -1;
3449                 }
3450                 values[i] = values_copy[ids[i]];
3451         }
3452         return n;
3453 }
3454
3455 static void
3456 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3457 {
3458         struct ixgbe_hw_stats *stats =
3459                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3460         struct ixgbe_macsec_stats *macsec_stats =
3461                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3462                                 dev->data->dev_private);
3463
3464         unsigned count = ixgbe_xstats_calc_num();
3465
3466         /* HW registers are cleared on read */
3467         ixgbe_dev_xstats_get(dev, NULL, count);
3468
3469         /* Reset software totals */
3470         memset(stats, 0, sizeof(*stats));
3471         memset(macsec_stats, 0, sizeof(*macsec_stats));
3472 }
3473
3474 static void
3475 ixgbevf_update_stats(struct rte_eth_dev *dev)
3476 {
3477         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3478         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3479                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3480
3481         /* Good Rx packet, include VF loopback */
3482         UPDATE_VF_STAT(IXGBE_VFGPRC,
3483             hw_stats->last_vfgprc, hw_stats->vfgprc);
3484
3485         /* Good Rx octets, include VF loopback */
3486         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3487             hw_stats->last_vfgorc, hw_stats->vfgorc);
3488
3489         /* Good Tx packet, include VF loopback */
3490         UPDATE_VF_STAT(IXGBE_VFGPTC,
3491             hw_stats->last_vfgptc, hw_stats->vfgptc);
3492
3493         /* Good Tx octets, include VF loopback */
3494         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3495             hw_stats->last_vfgotc, hw_stats->vfgotc);
3496
3497         /* Rx Multicst Packet */
3498         UPDATE_VF_STAT(IXGBE_VFMPRC,
3499             hw_stats->last_vfmprc, hw_stats->vfmprc);
3500 }
3501
3502 static int
3503 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3504                        unsigned n)
3505 {
3506         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3507                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3508         unsigned i;
3509
3510         if (n < IXGBEVF_NB_XSTATS)
3511                 return IXGBEVF_NB_XSTATS;
3512
3513         ixgbevf_update_stats(dev);
3514
3515         if (!xstats)
3516                 return 0;
3517
3518         /* Extended stats */
3519         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3520                 xstats[i].id = i;
3521                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3522                         rte_ixgbevf_stats_strings[i].offset);
3523         }
3524
3525         return IXGBEVF_NB_XSTATS;
3526 }
3527
3528 static void
3529 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3530 {
3531         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3532                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3533
3534         ixgbevf_update_stats(dev);
3535
3536         if (stats == NULL)
3537                 return;
3538
3539         stats->ipackets = hw_stats->vfgprc;
3540         stats->ibytes = hw_stats->vfgorc;
3541         stats->opackets = hw_stats->vfgptc;
3542         stats->obytes = hw_stats->vfgotc;
3543 }
3544
3545 static void
3546 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3547 {
3548         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3549                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3550
3551         /* Sync HW register to the last stats */
3552         ixgbevf_dev_stats_get(dev, NULL);
3553
3554         /* reset HW current stats*/
3555         hw_stats->vfgprc = 0;
3556         hw_stats->vfgorc = 0;
3557         hw_stats->vfgptc = 0;
3558         hw_stats->vfgotc = 0;
3559 }
3560
3561 static int
3562 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3563 {
3564         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565         u16 eeprom_verh, eeprom_verl;
3566         u32 etrack_id;
3567         int ret;
3568
3569         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3570         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3571
3572         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3573         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3574
3575         ret += 1; /* add the size of '\0' */
3576         if (fw_size < (u32)ret)
3577                 return ret;
3578         else
3579                 return 0;
3580 }
3581
3582 static void
3583 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3584 {
3585         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3588
3589         dev_info->pci_dev = pci_dev;
3590         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3591         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3592         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3593                 /*
3594                  * When DCB/VT is off, maximum number of queues changes,
3595                  * except for 82598EB, which remains constant.
3596                  */
3597                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3598                                 hw->mac.type != ixgbe_mac_82598EB)
3599                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3600         }
3601         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3602         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3603         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3604         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3605         dev_info->max_vfs = pci_dev->max_vfs;
3606         if (hw->mac.type == ixgbe_mac_82598EB)
3607                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3608         else
3609                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3610         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3611         dev_info->rx_offload_capa =
3612                 DEV_RX_OFFLOAD_VLAN_STRIP |
3613                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3614                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3615                 DEV_RX_OFFLOAD_TCP_CKSUM;
3616
3617         /*
3618          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3619          * mode.
3620          */
3621         if ((hw->mac.type == ixgbe_mac_82599EB ||
3622              hw->mac.type == ixgbe_mac_X540) &&
3623             !RTE_ETH_DEV_SRIOV(dev).active)
3624                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3625
3626         if (hw->mac.type == ixgbe_mac_82599EB ||
3627             hw->mac.type == ixgbe_mac_X540)
3628                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3629
3630         if (hw->mac.type == ixgbe_mac_X550 ||
3631             hw->mac.type == ixgbe_mac_X550EM_x ||
3632             hw->mac.type == ixgbe_mac_X550EM_a)
3633                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3634
3635         dev_info->tx_offload_capa =
3636                 DEV_TX_OFFLOAD_VLAN_INSERT |
3637                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3638                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3639                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3640                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3641                 DEV_TX_OFFLOAD_TCP_TSO;
3642
3643         if (hw->mac.type == ixgbe_mac_82599EB ||
3644             hw->mac.type == ixgbe_mac_X540)
3645                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3646
3647         if (hw->mac.type == ixgbe_mac_X550 ||
3648             hw->mac.type == ixgbe_mac_X550EM_x ||
3649             hw->mac.type == ixgbe_mac_X550EM_a)
3650                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3651
3652         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3653                 .rx_thresh = {
3654                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3655                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3656                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3657                 },
3658                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3659                 .rx_drop_en = 0,
3660         };
3661
3662         dev_info->default_txconf = (struct rte_eth_txconf) {
3663                 .tx_thresh = {
3664                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3665                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3666                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3667                 },
3668                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3669                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3670                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3671                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3672         };
3673
3674         dev_info->rx_desc_lim = rx_desc_lim;
3675         dev_info->tx_desc_lim = tx_desc_lim;
3676
3677         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3678         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3679         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3680
3681         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3682         if (hw->mac.type == ixgbe_mac_X540 ||
3683             hw->mac.type == ixgbe_mac_X540_vf ||
3684             hw->mac.type == ixgbe_mac_X550 ||
3685             hw->mac.type == ixgbe_mac_X550_vf) {
3686                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3687         }
3688 }
3689
3690 static const uint32_t *
3691 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3692 {
3693         static const uint32_t ptypes[] = {
3694                 /* For non-vec functions,
3695                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3696                  * for vec functions,
3697                  * refers to _recv_raw_pkts_vec().
3698                  */
3699                 RTE_PTYPE_L2_ETHER,
3700                 RTE_PTYPE_L3_IPV4,
3701                 RTE_PTYPE_L3_IPV4_EXT,
3702                 RTE_PTYPE_L3_IPV6,
3703                 RTE_PTYPE_L3_IPV6_EXT,
3704                 RTE_PTYPE_L4_SCTP,
3705                 RTE_PTYPE_L4_TCP,
3706                 RTE_PTYPE_L4_UDP,
3707                 RTE_PTYPE_TUNNEL_IP,
3708                 RTE_PTYPE_INNER_L3_IPV6,
3709                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3710                 RTE_PTYPE_INNER_L4_TCP,
3711                 RTE_PTYPE_INNER_L4_UDP,
3712                 RTE_PTYPE_UNKNOWN
3713         };
3714
3715         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3716             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3717             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3718             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3719                 return ptypes;
3720         return NULL;
3721 }
3722
3723 static void
3724 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3725                      struct rte_eth_dev_info *dev_info)
3726 {
3727         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3728         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3729
3730         dev_info->pci_dev = pci_dev;
3731         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3732         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3733         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3734         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3735         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3736         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3737         dev_info->max_vfs = pci_dev->max_vfs;
3738         if (hw->mac.type == ixgbe_mac_82598EB)
3739                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3740         else
3741                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3742         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3743                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3744                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3745                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3746         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3747                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3748                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3749                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3750                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3751                                 DEV_TX_OFFLOAD_TCP_TSO;
3752
3753         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3754                 .rx_thresh = {
3755                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3756                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3757                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3758                 },
3759                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3760                 .rx_drop_en = 0,
3761         };
3762
3763         dev_info->default_txconf = (struct rte_eth_txconf) {
3764                 .tx_thresh = {
3765                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3766                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3767                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3768                 },
3769                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3770                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3771                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3772                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3773         };
3774
3775         dev_info->rx_desc_lim = rx_desc_lim;
3776         dev_info->tx_desc_lim = tx_desc_lim;
3777 }
3778
3779 /* return 0 means link status changed, -1 means not changed */
3780 static int
3781 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3782 {
3783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3784         struct rte_eth_link link, old;
3785         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3786         struct ixgbe_interrupt *intr =
3787                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3788         int link_up;
3789         int diag;
3790         u32 speed = 0;
3791         bool autoneg = false;
3792
3793         link.link_status = ETH_LINK_DOWN;
3794         link.link_speed = 0;
3795         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3796         memset(&old, 0, sizeof(old));
3797         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3798
3799         hw->mac.get_link_status = true;
3800
3801         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3802                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3803                 speed = hw->phy.autoneg_advertised;
3804                 if (!speed)
3805                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3806                 ixgbe_setup_link(hw, speed, true);
3807         }
3808
3809         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3810         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3811                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3812         else
3813                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3814
3815         if (diag != 0) {
3816                 link.link_speed = ETH_SPEED_NUM_100M;
3817                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3818                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3819                 if (link.link_status == old.link_status)
3820                         return -1;
3821                 return 0;
3822         }
3823
3824         if (link_up == 0) {
3825                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3826                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3827                 if (link.link_status == old.link_status)
3828                         return -1;
3829                 return 0;
3830         }
3831         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3832         link.link_status = ETH_LINK_UP;
3833         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3834
3835         switch (link_speed) {
3836         default:
3837         case IXGBE_LINK_SPEED_UNKNOWN:
3838                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3839                 link.link_speed = ETH_SPEED_NUM_100M;
3840                 break;
3841
3842         case IXGBE_LINK_SPEED_100_FULL:
3843                 link.link_speed = ETH_SPEED_NUM_100M;
3844                 break;
3845
3846         case IXGBE_LINK_SPEED_1GB_FULL:
3847                 link.link_speed = ETH_SPEED_NUM_1G;
3848                 break;
3849
3850         case IXGBE_LINK_SPEED_10GB_FULL:
3851                 link.link_speed = ETH_SPEED_NUM_10G;
3852                 break;
3853         }
3854         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3855
3856         if (link.link_status == old.link_status)
3857                 return -1;
3858
3859         return 0;
3860 }
3861
3862 static void
3863 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3864 {
3865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3866         uint32_t fctrl;
3867
3868         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3869         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3870         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3871 }
3872
3873 static void
3874 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3875 {
3876         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3877         uint32_t fctrl;
3878
3879         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3880         fctrl &= (~IXGBE_FCTRL_UPE);
3881         if (dev->data->all_multicast == 1)
3882                 fctrl |= IXGBE_FCTRL_MPE;
3883         else
3884                 fctrl &= (~IXGBE_FCTRL_MPE);
3885         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3886 }
3887
3888 static void
3889 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3890 {
3891         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3892         uint32_t fctrl;
3893
3894         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3895         fctrl |= IXGBE_FCTRL_MPE;
3896         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3897 }
3898
3899 static void
3900 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3901 {
3902         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3903         uint32_t fctrl;
3904
3905         if (dev->data->promiscuous == 1)
3906                 return; /* must remain in all_multicast mode */
3907
3908         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3909         fctrl &= (~IXGBE_FCTRL_MPE);
3910         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3911 }
3912
3913 /**
3914  * It clears the interrupt causes and enables the interrupt.
3915  * It will be called once only during nic initialized.
3916  *
3917  * @param dev
3918  *  Pointer to struct rte_eth_dev.
3919  *
3920  * @return
3921  *  - On success, zero.
3922  *  - On failure, a negative value.
3923  */
3924 static int
3925 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3926 {
3927         struct ixgbe_interrupt *intr =
3928                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3929
3930         ixgbe_dev_link_status_print(dev);
3931         intr->mask |= IXGBE_EICR_LSC;
3932
3933         return 0;
3934 }
3935
3936 /**
3937  * It clears the interrupt causes and enables the interrupt.
3938  * It will be called once only during nic initialized.
3939  *
3940  * @param dev
3941  *  Pointer to struct rte_eth_dev.
3942  *
3943  * @return
3944  *  - On success, zero.
3945  *  - On failure, a negative value.
3946  */
3947 static int
3948 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3949 {
3950         struct ixgbe_interrupt *intr =
3951                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3952
3953         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3954
3955         return 0;
3956 }
3957
3958 /**
3959  * It clears the interrupt causes and enables the interrupt.
3960  * It will be called once only during nic initialized.
3961  *
3962  * @param dev
3963  *  Pointer to struct rte_eth_dev.
3964  *
3965  * @return
3966  *  - On success, zero.
3967  *  - On failure, a negative value.
3968  */
3969 static int
3970 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3971 {
3972         struct ixgbe_interrupt *intr =
3973                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3974
3975         intr->mask |= IXGBE_EICR_LINKSEC;
3976
3977         return 0;
3978 }
3979
3980 /*
3981  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3982  *
3983  * @param dev
3984  *  Pointer to struct rte_eth_dev.
3985  *
3986  * @return
3987  *  - On success, zero.
3988  *  - On failure, a negative value.
3989  */
3990 static int
3991 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3992 {
3993         uint32_t eicr;
3994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995         struct ixgbe_interrupt *intr =
3996                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3997
3998         /* clear all cause mask */
3999         ixgbe_disable_intr(hw);
4000
4001         /* read-on-clear nic registers here */
4002         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4003         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4004
4005         intr->flags = 0;
4006
4007         /* set flag for async link update */
4008         if (eicr & IXGBE_EICR_LSC)
4009                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4010
4011         if (eicr & IXGBE_EICR_MAILBOX)
4012                 intr->flags |= IXGBE_FLAG_MAILBOX;
4013
4014         if (eicr & IXGBE_EICR_LINKSEC)
4015                 intr->flags |= IXGBE_FLAG_MACSEC;
4016
4017         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4018             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4019             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4020                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4021
4022         return 0;
4023 }
4024
4025 /**
4026  * It gets and then prints the link status.
4027  *
4028  * @param dev
4029  *  Pointer to struct rte_eth_dev.
4030  *
4031  * @return
4032  *  - On success, zero.
4033  *  - On failure, a negative value.
4034  */
4035 static void
4036 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4037 {
4038         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4039         struct rte_eth_link link;
4040
4041         memset(&link, 0, sizeof(link));
4042         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4043         if (link.link_status) {
4044                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4045                                         (int)(dev->data->port_id),
4046                                         (unsigned)link.link_speed,
4047                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4048                                         "full-duplex" : "half-duplex");
4049         } else {
4050                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4051                                 (int)(dev->data->port_id));
4052         }
4053         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4054                                 pci_dev->addr.domain,
4055                                 pci_dev->addr.bus,
4056                                 pci_dev->addr.devid,
4057                                 pci_dev->addr.function);
4058 }
4059
4060 /*
4061  * It executes link_update after knowing an interrupt occurred.
4062  *
4063  * @param dev
4064  *  Pointer to struct rte_eth_dev.
4065  *
4066  * @return
4067  *  - On success, zero.
4068  *  - On failure, a negative value.
4069  */
4070 static int
4071 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4072                            struct rte_intr_handle *intr_handle)
4073 {
4074         struct ixgbe_interrupt *intr =
4075                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4076         int64_t timeout;
4077         struct rte_eth_link link;
4078         struct ixgbe_hw *hw =
4079                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4080
4081         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4082
4083         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4084                 ixgbe_pf_mbx_process(dev);
4085                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4086         }
4087
4088         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4089                 ixgbe_handle_lasi(hw);
4090                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4091         }
4092
4093         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4094                 /* get the link status before link update, for predicting later */
4095                 memset(&link, 0, sizeof(link));
4096                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4097
4098                 ixgbe_dev_link_update(dev, 0);
4099
4100                 /* likely to up */
4101                 if (!link.link_status)
4102                         /* handle it 1 sec later, wait it being stable */
4103                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4104                 /* likely to down */
4105                 else
4106                         /* handle it 4 sec later, wait it being stable */
4107                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4108
4109                 ixgbe_dev_link_status_print(dev);
4110                 intr->mask_original = intr->mask;
4111                 /* only disable lsc interrupt */
4112                 intr->mask &= ~IXGBE_EIMS_LSC;
4113                 if (rte_eal_alarm_set(timeout * 1000,
4114                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4115                         PMD_DRV_LOG(ERR, "Error setting alarm");
4116                 else
4117                         intr->mask = intr->mask_original;
4118         }
4119
4120         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4121         ixgbe_enable_intr(dev);
4122         rte_intr_enable(intr_handle);
4123
4124         return 0;
4125 }
4126
4127 /**
4128  * Interrupt handler which shall be registered for alarm callback for delayed
4129  * handling specific interrupt to wait for the stable nic state. As the
4130  * NIC interrupt state is not stable for ixgbe after link is just down,
4131  * it needs to wait 4 seconds to get the stable status.
4132  *
4133  * @param handle
4134  *  Pointer to interrupt handle.
4135  * @param param
4136  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4137  *
4138  * @return
4139  *  void
4140  */
4141 static void
4142 ixgbe_dev_interrupt_delayed_handler(void *param)
4143 {
4144         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4145         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4146         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4147         struct ixgbe_interrupt *intr =
4148                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4149         struct ixgbe_hw *hw =
4150                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4151         uint32_t eicr;
4152
4153         ixgbe_disable_intr(hw);
4154
4155         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4156         if (eicr & IXGBE_EICR_MAILBOX)
4157                 ixgbe_pf_mbx_process(dev);
4158
4159         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4160                 ixgbe_handle_lasi(hw);
4161                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4162         }
4163
4164         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4165                 ixgbe_dev_link_update(dev, 0);
4166                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4167                 ixgbe_dev_link_status_print(dev);
4168                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4169         }
4170
4171         if (intr->flags & IXGBE_FLAG_MACSEC) {
4172                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4173                                               NULL);
4174                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4175         }
4176
4177         /* restore original mask */
4178         intr->mask = intr->mask_original;
4179         intr->mask_original = 0;
4180
4181         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4182         ixgbe_enable_intr(dev);
4183         rte_intr_enable(intr_handle);
4184 }
4185
4186 /**
4187  * Interrupt handler triggered by NIC  for handling
4188  * specific interrupt.
4189  *
4190  * @param handle
4191  *  Pointer to interrupt handle.
4192  * @param param
4193  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4194  *
4195  * @return
4196  *  void
4197  */
4198 static void
4199 ixgbe_dev_interrupt_handler(void *param)
4200 {
4201         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4202
4203         ixgbe_dev_interrupt_get_status(dev);
4204         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4205 }
4206
4207 static int
4208 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4209 {
4210         struct ixgbe_hw *hw;
4211
4212         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4213         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4214 }
4215
4216 static int
4217 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4218 {
4219         struct ixgbe_hw *hw;
4220
4221         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4222         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4223 }
4224
4225 static int
4226 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4227 {
4228         struct ixgbe_hw *hw;
4229         uint32_t mflcn_reg;
4230         uint32_t fccfg_reg;
4231         int rx_pause;
4232         int tx_pause;
4233
4234         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235
4236         fc_conf->pause_time = hw->fc.pause_time;
4237         fc_conf->high_water = hw->fc.high_water[0];
4238         fc_conf->low_water = hw->fc.low_water[0];
4239         fc_conf->send_xon = hw->fc.send_xon;
4240         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4241
4242         /*
4243          * Return rx_pause status according to actual setting of
4244          * MFLCN register.
4245          */
4246         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4247         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4248                 rx_pause = 1;
4249         else
4250                 rx_pause = 0;
4251
4252         /*
4253          * Return tx_pause status according to actual setting of
4254          * FCCFG register.
4255          */
4256         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4257         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4258                 tx_pause = 1;
4259         else
4260                 tx_pause = 0;
4261
4262         if (rx_pause && tx_pause)
4263                 fc_conf->mode = RTE_FC_FULL;
4264         else if (rx_pause)
4265                 fc_conf->mode = RTE_FC_RX_PAUSE;
4266         else if (tx_pause)
4267                 fc_conf->mode = RTE_FC_TX_PAUSE;
4268         else
4269                 fc_conf->mode = RTE_FC_NONE;
4270
4271         return 0;
4272 }
4273
4274 static int
4275 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4276 {
4277         struct ixgbe_hw *hw;
4278         int err;
4279         uint32_t rx_buf_size;
4280         uint32_t max_high_water;
4281         uint32_t mflcn;
4282         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4283                 ixgbe_fc_none,
4284                 ixgbe_fc_rx_pause,
4285                 ixgbe_fc_tx_pause,
4286                 ixgbe_fc_full
4287         };
4288
4289         PMD_INIT_FUNC_TRACE();
4290
4291         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4292         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4293         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4294
4295         /*
4296          * At least reserve one Ethernet frame for watermark
4297          * high_water/low_water in kilo bytes for ixgbe
4298          */
4299         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4300         if ((fc_conf->high_water > max_high_water) ||
4301                 (fc_conf->high_water < fc_conf->low_water)) {
4302                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4303                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4304                 return -EINVAL;
4305         }
4306
4307         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4308         hw->fc.pause_time     = fc_conf->pause_time;
4309         hw->fc.high_water[0]  = fc_conf->high_water;
4310         hw->fc.low_water[0]   = fc_conf->low_water;
4311         hw->fc.send_xon       = fc_conf->send_xon;
4312         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4313
4314         err = ixgbe_fc_enable(hw);
4315
4316         /* Not negotiated is not an error case */
4317         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4318
4319                 /* check if we want to forward MAC frames - driver doesn't have native
4320                  * capability to do that, so we'll write the registers ourselves */
4321
4322                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4323
4324                 /* set or clear MFLCN.PMCF bit depending on configuration */
4325                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4326                         mflcn |= IXGBE_MFLCN_PMCF;
4327                 else
4328                         mflcn &= ~IXGBE_MFLCN_PMCF;
4329
4330                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4331                 IXGBE_WRITE_FLUSH(hw);
4332
4333                 return 0;
4334         }
4335
4336         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4337         return -EIO;
4338 }
4339
4340 /**
4341  *  ixgbe_pfc_enable_generic - Enable flow control
4342  *  @hw: pointer to hardware structure
4343  *  @tc_num: traffic class number
4344  *  Enable flow control according to the current settings.
4345  */
4346 static int
4347 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4348 {
4349         int ret_val = 0;
4350         uint32_t mflcn_reg, fccfg_reg;
4351         uint32_t reg;
4352         uint32_t fcrtl, fcrth;
4353         uint8_t i;
4354         uint8_t nb_rx_en;
4355
4356         /* Validate the water mark configuration */
4357         if (!hw->fc.pause_time) {
4358                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4359                 goto out;
4360         }
4361
4362         /* Low water mark of zero causes XOFF floods */
4363         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4364                  /* High/Low water can not be 0 */
4365                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4366                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4367                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4368                         goto out;
4369                 }
4370
4371                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4372                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4373                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4374                         goto out;
4375                 }
4376         }
4377         /* Negotiate the fc mode to use */
4378         ixgbe_fc_autoneg(hw);
4379
4380         /* Disable any previous flow control settings */
4381         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4382         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4383
4384         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4385         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4386
4387         switch (hw->fc.current_mode) {
4388         case ixgbe_fc_none:
4389                 /*
4390                  * If the count of enabled RX Priority Flow control >1,
4391                  * and the TX pause can not be disabled
4392                  */
4393                 nb_rx_en = 0;
4394                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4395                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4396                         if (reg & IXGBE_FCRTH_FCEN)
4397                                 nb_rx_en++;
4398                 }
4399                 if (nb_rx_en > 1)
4400                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4401                 break;
4402         case ixgbe_fc_rx_pause:
4403                 /*
4404                  * Rx Flow control is enabled and Tx Flow control is
4405                  * disabled by software override. Since there really
4406                  * isn't a way to advertise that we are capable of RX
4407                  * Pause ONLY, we will advertise that we support both
4408                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4409                  * disable the adapter's ability to send PAUSE frames.
4410                  */
4411                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4412                 /*
4413                  * If the count of enabled RX Priority Flow control >1,
4414                  * and the TX pause can not be disabled
4415                  */
4416                 nb_rx_en = 0;
4417                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4418                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4419                         if (reg & IXGBE_FCRTH_FCEN)
4420                                 nb_rx_en++;
4421                 }
4422                 if (nb_rx_en > 1)
4423                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4424                 break;
4425         case ixgbe_fc_tx_pause:
4426                 /*
4427                  * Tx Flow control is enabled, and Rx Flow control is
4428                  * disabled by software override.
4429                  */
4430                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4431                 break;
4432         case ixgbe_fc_full:
4433                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4434                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4435                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4436                 break;
4437         default:
4438                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4439                 ret_val = IXGBE_ERR_CONFIG;
4440                 goto out;
4441         }
4442
4443         /* Set 802.3x based flow control settings. */
4444         mflcn_reg |= IXGBE_MFLCN_DPF;
4445         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4446         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4447
4448         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4449         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4450                 hw->fc.high_water[tc_num]) {
4451                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4452                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4453                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4454         } else {
4455                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4456                 /*
4457                  * In order to prevent Tx hangs when the internal Tx
4458                  * switch is enabled we must set the high water mark
4459                  * to the maximum FCRTH value.  This allows the Tx
4460                  * switch to function even under heavy Rx workloads.
4461                  */
4462                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4463         }
4464         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4465
4466         /* Configure pause time (2 TCs per register) */
4467         reg = hw->fc.pause_time * 0x00010001;
4468         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4469                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4470
4471         /* Configure flow control refresh threshold value */
4472         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4473
4474 out:
4475         return ret_val;
4476 }
4477
4478 static int
4479 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4480 {
4481         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4482         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4483
4484         if (hw->mac.type != ixgbe_mac_82598EB) {
4485                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4486         }
4487         return ret_val;
4488 }
4489
4490 static int
4491 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4492 {
4493         int err;
4494         uint32_t rx_buf_size;
4495         uint32_t max_high_water;
4496         uint8_t tc_num;
4497         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4498         struct ixgbe_hw *hw =
4499                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4500         struct ixgbe_dcb_config *dcb_config =
4501                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4502
4503         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4504                 ixgbe_fc_none,
4505                 ixgbe_fc_rx_pause,
4506                 ixgbe_fc_tx_pause,
4507                 ixgbe_fc_full
4508         };
4509
4510         PMD_INIT_FUNC_TRACE();
4511
4512         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4513         tc_num = map[pfc_conf->priority];
4514         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4515         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4516         /*
4517          * At least reserve one Ethernet frame for watermark
4518          * high_water/low_water in kilo bytes for ixgbe
4519          */
4520         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4521         if ((pfc_conf->fc.high_water > max_high_water) ||
4522             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4523                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4524                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4525                 return -EINVAL;
4526         }
4527
4528         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4529         hw->fc.pause_time = pfc_conf->fc.pause_time;
4530         hw->fc.send_xon = pfc_conf->fc.send_xon;
4531         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4532         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4533
4534         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4535
4536         /* Not negotiated is not an error case */
4537         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4538                 return 0;
4539
4540         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4541         return -EIO;
4542 }
4543
4544 static int
4545 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4546                           struct rte_eth_rss_reta_entry64 *reta_conf,
4547                           uint16_t reta_size)
4548 {
4549         uint16_t i, sp_reta_size;
4550         uint8_t j, mask;
4551         uint32_t reta, r;
4552         uint16_t idx, shift;
4553         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4554         uint32_t reta_reg;
4555
4556         PMD_INIT_FUNC_TRACE();
4557
4558         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4559                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4560                         "NIC.");
4561                 return -ENOTSUP;
4562         }
4563
4564         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4565         if (reta_size != sp_reta_size) {
4566                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4567                         "(%d) doesn't match the number hardware can supported "
4568                         "(%d)", reta_size, sp_reta_size);
4569                 return -EINVAL;
4570         }
4571
4572         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4573                 idx = i / RTE_RETA_GROUP_SIZE;
4574                 shift = i % RTE_RETA_GROUP_SIZE;
4575                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4576                                                 IXGBE_4_BIT_MASK);
4577                 if (!mask)
4578                         continue;
4579                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4580                 if (mask == IXGBE_4_BIT_MASK)
4581                         r = 0;
4582                 else
4583                         r = IXGBE_READ_REG(hw, reta_reg);
4584                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4585                         if (mask & (0x1 << j))
4586                                 reta |= reta_conf[idx].reta[shift + j] <<
4587                                                         (CHAR_BIT * j);
4588                         else
4589                                 reta |= r & (IXGBE_8_BIT_MASK <<
4590                                                 (CHAR_BIT * j));
4591                 }
4592                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4593         }
4594
4595         return 0;
4596 }
4597
4598 static int
4599 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4600                          struct rte_eth_rss_reta_entry64 *reta_conf,
4601                          uint16_t reta_size)
4602 {
4603         uint16_t i, sp_reta_size;
4604         uint8_t j, mask;
4605         uint32_t reta;
4606         uint16_t idx, shift;
4607         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4608         uint32_t reta_reg;
4609
4610         PMD_INIT_FUNC_TRACE();
4611         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4612         if (reta_size != sp_reta_size) {
4613                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4614                         "(%d) doesn't match the number hardware can supported "
4615                         "(%d)", reta_size, sp_reta_size);
4616                 return -EINVAL;
4617         }
4618
4619         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4620                 idx = i / RTE_RETA_GROUP_SIZE;
4621                 shift = i % RTE_RETA_GROUP_SIZE;
4622                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4623                                                 IXGBE_4_BIT_MASK);
4624                 if (!mask)
4625                         continue;
4626
4627                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4628                 reta = IXGBE_READ_REG(hw, reta_reg);
4629                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4630                         if (mask & (0x1 << j))
4631                                 reta_conf[idx].reta[shift + j] =
4632                                         ((reta >> (CHAR_BIT * j)) &
4633                                                 IXGBE_8_BIT_MASK);
4634                 }
4635         }
4636
4637         return 0;
4638 }
4639
4640 static int
4641 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4642                                 uint32_t index, uint32_t pool)
4643 {
4644         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4645         uint32_t enable_addr = 1;
4646
4647         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4648                              pool, enable_addr);
4649 }
4650
4651 static void
4652 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4653 {
4654         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4655
4656         ixgbe_clear_rar(hw, index);
4657 }
4658
4659 static void
4660 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4661 {
4662         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4663
4664         ixgbe_remove_rar(dev, 0);
4665
4666         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4667 }
4668
4669 static bool
4670 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4671 {
4672         if (strcmp(dev->data->drv_name, drv->driver.name))
4673                 return false;
4674
4675         return true;
4676 }
4677
4678 bool
4679 is_ixgbe_supported(struct rte_eth_dev *dev)
4680 {
4681         return is_device_supported(dev, &rte_ixgbe_pmd);
4682 }
4683
4684 static int
4685 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4686 {
4687         uint32_t hlreg0;
4688         uint32_t maxfrs;
4689         struct ixgbe_hw *hw;
4690         struct rte_eth_dev_info dev_info;
4691         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4692         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4693
4694         ixgbe_dev_info_get(dev, &dev_info);
4695
4696         /* check that mtu is within the allowed range */
4697         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4698                 return -EINVAL;
4699
4700         /* refuse mtu that requires the support of scattered packets when this
4701          * feature has not been enabled before.
4702          */
4703         if (!rx_conf->enable_scatter &&
4704             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4705              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4706                 return -EINVAL;
4707
4708         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4709         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4710
4711         /* switch to jumbo mode if needed */
4712         if (frame_size > ETHER_MAX_LEN) {
4713                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4714                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4715         } else {
4716                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4717                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4718         }
4719         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4720
4721         /* update max frame size */
4722         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4723
4724         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4725         maxfrs &= 0x0000FFFF;
4726         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4727         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4728
4729         return 0;
4730 }
4731
4732 /*
4733  * Virtual Function operations
4734  */
4735 static void
4736 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4737 {
4738         PMD_INIT_FUNC_TRACE();
4739
4740         /* Clear interrupt mask to stop from interrupts being generated */
4741         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4742
4743         IXGBE_WRITE_FLUSH(hw);
4744 }
4745
4746 static void
4747 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4748 {
4749         PMD_INIT_FUNC_TRACE();
4750
4751         /* VF enable interrupt autoclean */
4752         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4753         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4754         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4755
4756         IXGBE_WRITE_FLUSH(hw);
4757 }
4758
4759 static int
4760 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4761 {
4762         struct rte_eth_conf *conf = &dev->data->dev_conf;
4763         struct ixgbe_adapter *adapter =
4764                         (struct ixgbe_adapter *)dev->data->dev_private;
4765
4766         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4767                      dev->data->port_id);
4768
4769         /*
4770          * VF has no ability to enable/disable HW CRC
4771          * Keep the persistent behavior the same as Host PF
4772          */
4773 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4774         if (!conf->rxmode.hw_strip_crc) {
4775                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4776                 conf->rxmode.hw_strip_crc = 1;
4777         }
4778 #else
4779         if (conf->rxmode.hw_strip_crc) {
4780                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4781                 conf->rxmode.hw_strip_crc = 0;
4782         }
4783 #endif
4784
4785         /*
4786          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4787          * allocation or vector Rx preconditions we will reset it.
4788          */
4789         adapter->rx_bulk_alloc_allowed = true;
4790         adapter->rx_vec_allowed = true;
4791
4792         return 0;
4793 }
4794
4795 static int
4796 ixgbevf_dev_start(struct rte_eth_dev *dev)
4797 {
4798         struct ixgbe_hw *hw =
4799                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4800         uint32_t intr_vector = 0;
4801         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4802         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4803
4804         int err, mask = 0;
4805
4806         PMD_INIT_FUNC_TRACE();
4807
4808         hw->mac.ops.reset_hw(hw);
4809         hw->mac.get_link_status = true;
4810
4811         /* negotiate mailbox API version to use with the PF. */
4812         ixgbevf_negotiate_api(hw);
4813
4814         ixgbevf_dev_tx_init(dev);
4815
4816         /* This can fail when allocating mbufs for descriptor rings */
4817         err = ixgbevf_dev_rx_init(dev);
4818         if (err) {
4819                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4820                 ixgbe_dev_clear_queues(dev);
4821                 return err;
4822         }
4823
4824         /* Set vfta */
4825         ixgbevf_set_vfta_all(dev, 1);
4826
4827         /* Set HW strip */
4828         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4829                 ETH_VLAN_EXTEND_MASK;
4830         ixgbevf_vlan_offload_set(dev, mask);
4831
4832         ixgbevf_dev_rxtx_start(dev);
4833
4834         /* check and configure queue intr-vector mapping */
4835         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4836                 intr_vector = dev->data->nb_rx_queues;
4837                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4838                         return -1;
4839         }
4840
4841         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4842                 intr_handle->intr_vec =
4843                         rte_zmalloc("intr_vec",
4844                                     dev->data->nb_rx_queues * sizeof(int), 0);
4845                 if (intr_handle->intr_vec == NULL) {
4846                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4847                                      " intr_vec", dev->data->nb_rx_queues);
4848                         return -ENOMEM;
4849                 }
4850         }
4851         ixgbevf_configure_msix(dev);
4852
4853         rte_intr_enable(intr_handle);
4854
4855         /* Re-enable interrupt for VF */
4856         ixgbevf_intr_enable(hw);
4857
4858         return 0;
4859 }
4860
4861 static void
4862 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4863 {
4864         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4865         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4866         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4867
4868         PMD_INIT_FUNC_TRACE();
4869
4870         ixgbevf_intr_disable(hw);
4871
4872         hw->adapter_stopped = 1;
4873         ixgbe_stop_adapter(hw);
4874
4875         /*
4876           * Clear what we set, but we still keep shadow_vfta to
4877           * restore after device starts
4878           */
4879         ixgbevf_set_vfta_all(dev, 0);
4880
4881         /* Clear stored conf */
4882         dev->data->scattered_rx = 0;
4883
4884         ixgbe_dev_clear_queues(dev);
4885
4886         /* Clean datapath event and queue/vec mapping */
4887         rte_intr_efd_disable(intr_handle);
4888         if (intr_handle->intr_vec != NULL) {
4889                 rte_free(intr_handle->intr_vec);
4890                 intr_handle->intr_vec = NULL;
4891         }
4892 }
4893
4894 static void
4895 ixgbevf_dev_close(struct rte_eth_dev *dev)
4896 {
4897         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4898
4899         PMD_INIT_FUNC_TRACE();
4900
4901         ixgbe_reset_hw(hw);
4902
4903         ixgbevf_dev_stop(dev);
4904
4905         ixgbe_dev_free_queues(dev);
4906
4907         /**
4908          * Remove the VF MAC address ro ensure
4909          * that the VF traffic goes to the PF
4910          * after stop, close and detach of the VF
4911          **/
4912         ixgbevf_remove_mac_addr(dev, 0);
4913 }
4914
4915 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4916 {
4917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4918         struct ixgbe_vfta *shadow_vfta =
4919                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4920         int i = 0, j = 0, vfta = 0, mask = 1;
4921
4922         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4923                 vfta = shadow_vfta->vfta[i];
4924                 if (vfta) {
4925                         mask = 1;
4926                         for (j = 0; j < 32; j++) {
4927                                 if (vfta & mask)
4928                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4929                                                        on, false);
4930                                 mask <<= 1;
4931                         }
4932                 }
4933         }
4934
4935 }
4936
4937 static int
4938 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4939 {
4940         struct ixgbe_hw *hw =
4941                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4942         struct ixgbe_vfta *shadow_vfta =
4943                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4944         uint32_t vid_idx = 0;
4945         uint32_t vid_bit = 0;
4946         int ret = 0;
4947
4948         PMD_INIT_FUNC_TRACE();
4949
4950         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4951         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4952         if (ret) {
4953                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4954                 return ret;
4955         }
4956         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4957         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4958
4959         /* Save what we set and retore it after device reset */
4960         if (on)
4961                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4962         else
4963                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4964
4965         return 0;
4966 }
4967
4968 static void
4969 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4970 {
4971         struct ixgbe_hw *hw =
4972                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4973         uint32_t ctrl;
4974
4975         PMD_INIT_FUNC_TRACE();
4976
4977         if (queue >= hw->mac.max_rx_queues)
4978                 return;
4979
4980         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4981         if (on)
4982                 ctrl |= IXGBE_RXDCTL_VME;
4983         else
4984                 ctrl &= ~IXGBE_RXDCTL_VME;
4985         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4986
4987         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4988 }
4989
4990 static void
4991 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4992 {
4993         struct ixgbe_hw *hw =
4994                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4995         uint16_t i;
4996         int on = 0;
4997
4998         /* VF function only support hw strip feature, others are not support */
4999         if (mask & ETH_VLAN_STRIP_MASK) {
5000                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5001
5002                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5003                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5004         }
5005 }
5006
5007 int
5008 ixgbe_vt_check(struct ixgbe_hw *hw)
5009 {
5010         uint32_t reg_val;
5011
5012         /* if Virtualization Technology is enabled */
5013         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5014         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5015                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5016                 return -1;
5017         }
5018
5019         return 0;
5020 }
5021
5022 static uint32_t
5023 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5024 {
5025         uint32_t vector = 0;
5026
5027         switch (hw->mac.mc_filter_type) {
5028         case 0:   /* use bits [47:36] of the address */
5029                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5030                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5031                 break;
5032         case 1:   /* use bits [46:35] of the address */
5033                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5034                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5035                 break;
5036         case 2:   /* use bits [45:34] of the address */
5037                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5038                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5039                 break;
5040         case 3:   /* use bits [43:32] of the address */
5041                 vector = ((uc_addr->addr_bytes[4]) |
5042                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5043                 break;
5044         default:  /* Invalid mc_filter_type */
5045                 break;
5046         }
5047
5048         /* vector can only be 12-bits or boundary will be exceeded */
5049         vector &= 0xFFF;
5050         return vector;
5051 }
5052
5053 static int
5054 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5055                         uint8_t on)
5056 {
5057         uint32_t vector;
5058         uint32_t uta_idx;
5059         uint32_t reg_val;
5060         uint32_t uta_shift;
5061         uint32_t rc;
5062         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5063         const uint32_t ixgbe_uta_bit_shift = 5;
5064         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5065         const uint32_t bit1 = 0x1;
5066
5067         struct ixgbe_hw *hw =
5068                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069         struct ixgbe_uta_info *uta_info =
5070                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5071
5072         /* The UTA table only exists on 82599 hardware and newer */
5073         if (hw->mac.type < ixgbe_mac_82599EB)
5074                 return -ENOTSUP;
5075
5076         vector = ixgbe_uta_vector(hw, mac_addr);
5077         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5078         uta_shift = vector & ixgbe_uta_bit_mask;
5079
5080         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5081         if (rc == on)
5082                 return 0;
5083
5084         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5085         if (on) {
5086                 uta_info->uta_in_use++;
5087                 reg_val |= (bit1 << uta_shift);
5088                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5089         } else {
5090                 uta_info->uta_in_use--;
5091                 reg_val &= ~(bit1 << uta_shift);
5092                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5093         }
5094
5095         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5096
5097         if (uta_info->uta_in_use > 0)
5098                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5099                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5100         else
5101                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5102
5103         return 0;
5104 }
5105
5106 static int
5107 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5108 {
5109         int i;
5110         struct ixgbe_hw *hw =
5111                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5112         struct ixgbe_uta_info *uta_info =
5113                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5114
5115         /* The UTA table only exists on 82599 hardware and newer */
5116         if (hw->mac.type < ixgbe_mac_82599EB)
5117                 return -ENOTSUP;
5118
5119         if (on) {
5120                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5121                         uta_info->uta_shadow[i] = ~0;
5122                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5123                 }
5124         } else {
5125                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5126                         uta_info->uta_shadow[i] = 0;
5127                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5128                 }
5129         }
5130         return 0;
5131
5132 }
5133
5134 uint32_t
5135 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5136 {
5137         uint32_t new_val = orig_val;
5138
5139         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5140                 new_val |= IXGBE_VMOLR_AUPE;
5141         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5142                 new_val |= IXGBE_VMOLR_ROMPE;
5143         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5144                 new_val |= IXGBE_VMOLR_ROPE;
5145         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5146                 new_val |= IXGBE_VMOLR_BAM;
5147         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5148                 new_val |= IXGBE_VMOLR_MPE;
5149
5150         return new_val;
5151 }
5152
5153 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5154 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5155 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5156 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5157 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5158         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5159         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5160
5161 static int
5162 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5163                       struct rte_eth_mirror_conf *mirror_conf,
5164                       uint8_t rule_id, uint8_t on)
5165 {
5166         uint32_t mr_ctl, vlvf;
5167         uint32_t mp_lsb = 0;
5168         uint32_t mv_msb = 0;
5169         uint32_t mv_lsb = 0;
5170         uint32_t mp_msb = 0;
5171         uint8_t i = 0;
5172         int reg_index = 0;
5173         uint64_t vlan_mask = 0;
5174
5175         const uint8_t pool_mask_offset = 32;
5176         const uint8_t vlan_mask_offset = 32;
5177         const uint8_t dst_pool_offset = 8;
5178         const uint8_t rule_mr_offset  = 4;
5179         const uint8_t mirror_rule_mask = 0x0F;
5180
5181         struct ixgbe_mirror_info *mr_info =
5182                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5183         struct ixgbe_hw *hw =
5184                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5185         uint8_t mirror_type = 0;
5186
5187         if (ixgbe_vt_check(hw) < 0)
5188                 return -ENOTSUP;
5189
5190         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5191                 return -EINVAL;
5192
5193         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5194                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5195                             mirror_conf->rule_type);
5196                 return -EINVAL;
5197         }
5198
5199         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5200                 mirror_type |= IXGBE_MRCTL_VLME;
5201                 /* Check if vlan id is valid and find conresponding VLAN ID
5202                  * index in VLVF
5203                  */
5204                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5205                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5206                                 /* search vlan id related pool vlan filter
5207                                  * index
5208                                  */
5209                                 reg_index = ixgbe_find_vlvf_slot(
5210                                                 hw,
5211                                                 mirror_conf->vlan.vlan_id[i],
5212                                                 false);
5213                                 if (reg_index < 0)
5214                                         return -EINVAL;
5215                                 vlvf = IXGBE_READ_REG(hw,
5216                                                       IXGBE_VLVF(reg_index));
5217                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5218                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5219                                       mirror_conf->vlan.vlan_id[i]))
5220                                         vlan_mask |= (1ULL << reg_index);
5221                                 else
5222                                         return -EINVAL;
5223                         }
5224                 }
5225
5226                 if (on) {
5227                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5228                         mv_msb = vlan_mask >> vlan_mask_offset;
5229
5230                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5231                                                 mirror_conf->vlan.vlan_mask;
5232                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5233                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5234                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5235                                                 mirror_conf->vlan.vlan_id[i];
5236                         }
5237                 } else {
5238                         mv_lsb = 0;
5239                         mv_msb = 0;
5240                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5241                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5242                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5243                 }
5244         }
5245
5246         /**
5247          * if enable pool mirror, write related pool mask register,if disable
5248          * pool mirror, clear PFMRVM register
5249          */
5250         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5251                 mirror_type |= IXGBE_MRCTL_VPME;
5252                 if (on) {
5253                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5254                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5255                         mr_info->mr_conf[rule_id].pool_mask =
5256                                         mirror_conf->pool_mask;
5257
5258                 } else {
5259                         mp_lsb = 0;
5260                         mp_msb = 0;
5261                         mr_info->mr_conf[rule_id].pool_mask = 0;
5262                 }
5263         }
5264         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5265                 mirror_type |= IXGBE_MRCTL_UPME;
5266         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5267                 mirror_type |= IXGBE_MRCTL_DPME;
5268
5269         /* read  mirror control register and recalculate it */
5270         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5271
5272         if (on) {
5273                 mr_ctl |= mirror_type;
5274                 mr_ctl &= mirror_rule_mask;
5275                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5276         } else {
5277                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5278         }
5279
5280         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5281         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5282
5283         /* write mirrror control  register */
5284         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5285
5286         /* write pool mirrror control  register */
5287         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5288                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5289                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5290                                 mp_msb);
5291         }
5292         /* write VLAN mirrror control  register */
5293         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5294                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5295                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5296                                 mv_msb);
5297         }
5298
5299         return 0;
5300 }
5301
5302 static int
5303 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5304 {
5305         int mr_ctl = 0;
5306         uint32_t lsb_val = 0;
5307         uint32_t msb_val = 0;
5308         const uint8_t rule_mr_offset = 4;
5309
5310         struct ixgbe_hw *hw =
5311                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5312         struct ixgbe_mirror_info *mr_info =
5313                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5314
5315         if (ixgbe_vt_check(hw) < 0)
5316                 return -ENOTSUP;
5317
5318         memset(&mr_info->mr_conf[rule_id], 0,
5319                sizeof(struct rte_eth_mirror_conf));
5320
5321         /* clear PFVMCTL register */
5322         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5323
5324         /* clear pool mask register */
5325         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5326         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5327
5328         /* clear vlan mask register */
5329         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5330         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5331
5332         return 0;
5333 }
5334
5335 static int
5336 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5337 {
5338         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5339         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5340         uint32_t mask;
5341         struct ixgbe_hw *hw =
5342                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5343
5344         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5345         mask |= (1 << IXGBE_MISC_VEC_ID);
5346         RTE_SET_USED(queue_id);
5347         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5348
5349         rte_intr_enable(intr_handle);
5350
5351         return 0;
5352 }
5353
5354 static int
5355 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5356 {
5357         uint32_t mask;
5358         struct ixgbe_hw *hw =
5359                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5360
5361         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5362         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5363         RTE_SET_USED(queue_id);
5364         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5365
5366         return 0;
5367 }
5368
5369 static int
5370 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5371 {
5372         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5373         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5374         uint32_t mask;
5375         struct ixgbe_hw *hw =
5376                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5377         struct ixgbe_interrupt *intr =
5378                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5379
5380         if (queue_id < 16) {
5381                 ixgbe_disable_intr(hw);
5382                 intr->mask |= (1 << queue_id);
5383                 ixgbe_enable_intr(dev);
5384         } else if (queue_id < 32) {
5385                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5386                 mask &= (1 << queue_id);
5387                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5388         } else if (queue_id < 64) {
5389                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5390                 mask &= (1 << (queue_id - 32));
5391                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5392         }
5393         rte_intr_enable(intr_handle);
5394
5395         return 0;
5396 }
5397
5398 static int
5399 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5400 {
5401         uint32_t mask;
5402         struct ixgbe_hw *hw =
5403                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5404         struct ixgbe_interrupt *intr =
5405                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5406
5407         if (queue_id < 16) {
5408                 ixgbe_disable_intr(hw);
5409                 intr->mask &= ~(1 << queue_id);
5410                 ixgbe_enable_intr(dev);
5411         } else if (queue_id < 32) {
5412                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5413                 mask &= ~(1 << queue_id);
5414                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5415         } else if (queue_id < 64) {
5416                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5417                 mask &= ~(1 << (queue_id - 32));
5418                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5419         }
5420
5421         return 0;
5422 }
5423
5424 static void
5425 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5426                      uint8_t queue, uint8_t msix_vector)
5427 {
5428         uint32_t tmp, idx;
5429
5430         if (direction == -1) {
5431                 /* other causes */
5432                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5433                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5434                 tmp &= ~0xFF;
5435                 tmp |= msix_vector;
5436                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5437         } else {
5438                 /* rx or tx cause */
5439                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5440                 idx = ((16 * (queue & 1)) + (8 * direction));
5441                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5442                 tmp &= ~(0xFF << idx);
5443                 tmp |= (msix_vector << idx);
5444                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5445         }
5446 }
5447
5448 /**
5449  * set the IVAR registers, mapping interrupt causes to vectors
5450  * @param hw
5451  *  pointer to ixgbe_hw struct
5452  * @direction
5453  *  0 for Rx, 1 for Tx, -1 for other causes
5454  * @queue
5455  *  queue to map the corresponding interrupt to
5456  * @msix_vector
5457  *  the vector to map to the corresponding queue
5458  */
5459 static void
5460 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5461                    uint8_t queue, uint8_t msix_vector)
5462 {
5463         uint32_t tmp, idx;
5464
5465         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5466         if (hw->mac.type == ixgbe_mac_82598EB) {
5467                 if (direction == -1)
5468                         direction = 0;
5469                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5470                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5471                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5472                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5473                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5474         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5475                         (hw->mac.type == ixgbe_mac_X540)) {
5476                 if (direction == -1) {
5477                         /* other causes */
5478                         idx = ((queue & 1) * 8);
5479                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5480                         tmp &= ~(0xFF << idx);
5481                         tmp |= (msix_vector << idx);
5482                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5483                 } else {
5484                         /* rx or tx causes */
5485                         idx = ((16 * (queue & 1)) + (8 * direction));
5486                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5487                         tmp &= ~(0xFF << idx);
5488                         tmp |= (msix_vector << idx);
5489                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5490                 }
5491         }
5492 }
5493
5494 static void
5495 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5496 {
5497         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5498         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5499         struct ixgbe_hw *hw =
5500                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5501         uint32_t q_idx;
5502         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5503
5504         /* Configure VF other cause ivar */
5505         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5506
5507         /* won't configure msix register if no mapping is done
5508          * between intr vector and event fd.
5509          */
5510         if (!rte_intr_dp_is_en(intr_handle))
5511                 return;
5512
5513         /* Configure all RX queues of VF */
5514         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5515                 /* Force all queue use vector 0,
5516                  * as IXGBE_VF_MAXMSIVECOTR = 1
5517                  */
5518                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5519                 intr_handle->intr_vec[q_idx] = vector_idx;
5520         }
5521 }
5522
5523 /**
5524  * Sets up the hardware to properly generate MSI-X interrupts
5525  * @hw
5526  *  board private structure
5527  */
5528 static void
5529 ixgbe_configure_msix(struct rte_eth_dev *dev)
5530 {
5531         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5532         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5533         struct ixgbe_hw *hw =
5534                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5535         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5536         uint32_t vec = IXGBE_MISC_VEC_ID;
5537         uint32_t mask;
5538         uint32_t gpie;
5539
5540         /* won't configure msix register if no mapping is done
5541          * between intr vector and event fd
5542          */
5543         if (!rte_intr_dp_is_en(intr_handle))
5544                 return;
5545
5546         if (rte_intr_allow_others(intr_handle))
5547                 vec = base = IXGBE_RX_VEC_START;
5548
5549         /* setup GPIE for MSI-x mode */
5550         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5551         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5552                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5553         /* auto clearing and auto setting corresponding bits in EIMS
5554          * when MSI-X interrupt is triggered
5555          */
5556         if (hw->mac.type == ixgbe_mac_82598EB) {
5557                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5558         } else {
5559                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5560                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5561         }
5562         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5563
5564         /* Populate the IVAR table and set the ITR values to the
5565          * corresponding register.
5566          */
5567         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5568              queue_id++) {
5569                 /* by default, 1:1 mapping */
5570                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5571                 intr_handle->intr_vec[queue_id] = vec;
5572                 if (vec < base + intr_handle->nb_efd - 1)
5573                         vec++;
5574         }
5575
5576         switch (hw->mac.type) {
5577         case ixgbe_mac_82598EB:
5578                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5579                                    IXGBE_MISC_VEC_ID);
5580                 break;
5581         case ixgbe_mac_82599EB:
5582         case ixgbe_mac_X540:
5583                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5584                 break;
5585         default:
5586                 break;
5587         }
5588         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5589                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5590
5591         /* set up to autoclear timer, and the vectors */
5592         mask = IXGBE_EIMS_ENABLE_MASK;
5593         mask &= ~(IXGBE_EIMS_OTHER |
5594                   IXGBE_EIMS_MAILBOX |
5595                   IXGBE_EIMS_LSC);
5596
5597         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5598 }
5599
5600 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5601         uint16_t queue_idx, uint16_t tx_rate)
5602 {
5603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5604         uint32_t rf_dec, rf_int;
5605         uint32_t bcnrc_val;
5606         uint16_t link_speed = dev->data->dev_link.link_speed;
5607
5608         if (queue_idx >= hw->mac.max_tx_queues)
5609                 return -EINVAL;
5610
5611         if (tx_rate != 0) {
5612                 /* Calculate the rate factor values to set */
5613                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5614                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5615                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5616
5617                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5618                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5619                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5620                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5621         } else {
5622                 bcnrc_val = 0;
5623         }
5624
5625         /*
5626          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5627          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5628          * set as 0x4.
5629          */
5630         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5631                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5632                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5633                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5634                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5635         else
5636                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5637                         IXGBE_MMW_SIZE_DEFAULT);
5638
5639         /* Set RTTBCNRC of queue X */
5640         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5641         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5642         IXGBE_WRITE_FLUSH(hw);
5643
5644         return 0;
5645 }
5646
5647 static int
5648 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5649                      __attribute__((unused)) uint32_t index,
5650                      __attribute__((unused)) uint32_t pool)
5651 {
5652         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5653         int diag;
5654
5655         /*
5656          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5657          * operation. Trap this case to avoid exhausting the [very limited]
5658          * set of PF resources used to store VF MAC addresses.
5659          */
5660         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5661                 return -1;
5662         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5663         if (diag != 0)
5664                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5665                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5666                             mac_addr->addr_bytes[0],
5667                             mac_addr->addr_bytes[1],
5668                             mac_addr->addr_bytes[2],
5669                             mac_addr->addr_bytes[3],
5670                             mac_addr->addr_bytes[4],
5671                             mac_addr->addr_bytes[5],
5672                             diag);
5673         return diag;
5674 }
5675
5676 static void
5677 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5678 {
5679         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5680         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5681         struct ether_addr *mac_addr;
5682         uint32_t i;
5683         int diag;
5684
5685         /*
5686          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5687          * not support the deletion of a given MAC address.
5688          * Instead, it imposes to delete all MAC addresses, then to add again
5689          * all MAC addresses with the exception of the one to be deleted.
5690          */
5691         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5692
5693         /*
5694          * Add again all MAC addresses, with the exception of the deleted one
5695          * and of the permanent MAC address.
5696          */
5697         for (i = 0, mac_addr = dev->data->mac_addrs;
5698              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5699                 /* Skip the deleted MAC address */
5700                 if (i == index)
5701                         continue;
5702                 /* Skip NULL MAC addresses */
5703                 if (is_zero_ether_addr(mac_addr))
5704                         continue;
5705                 /* Skip the permanent MAC address */
5706                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5707                         continue;
5708                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5709                 if (diag != 0)
5710                         PMD_DRV_LOG(ERR,
5711                                     "Adding again MAC address "
5712                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5713                                     "diag=%d",
5714                                     mac_addr->addr_bytes[0],
5715                                     mac_addr->addr_bytes[1],
5716                                     mac_addr->addr_bytes[2],
5717                                     mac_addr->addr_bytes[3],
5718                                     mac_addr->addr_bytes[4],
5719                                     mac_addr->addr_bytes[5],
5720                                     diag);
5721         }
5722 }
5723
5724 static void
5725 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5726 {
5727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5728
5729         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5730 }
5731
5732 int
5733 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5734                         struct rte_eth_syn_filter *filter,
5735                         bool add)
5736 {
5737         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5738         struct ixgbe_filter_info *filter_info =
5739                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5740         uint32_t syn_info;
5741         uint32_t synqf;
5742
5743         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5744                 return -EINVAL;
5745
5746         syn_info = filter_info->syn_info;
5747
5748         if (add) {
5749                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5750                         return -EINVAL;
5751                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5752                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5753
5754                 if (filter->hig_pri)
5755                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5756                 else
5757                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5758         } else {
5759                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5760                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5761                         return -ENOENT;
5762                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5763         }
5764
5765         filter_info->syn_info = synqf;
5766         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5767         IXGBE_WRITE_FLUSH(hw);
5768         return 0;
5769 }
5770
5771 static int
5772 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5773                         struct rte_eth_syn_filter *filter)
5774 {
5775         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5776         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5777
5778         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5779                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5780                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5781                 return 0;
5782         }
5783         return -ENOENT;
5784 }
5785
5786 static int
5787 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5788                         enum rte_filter_op filter_op,
5789                         void *arg)
5790 {
5791         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5792         int ret;
5793
5794         MAC_TYPE_FILTER_SUP(hw->mac.type);
5795
5796         if (filter_op == RTE_ETH_FILTER_NOP)
5797                 return 0;
5798
5799         if (arg == NULL) {
5800                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5801                             filter_op);
5802                 return -EINVAL;
5803         }
5804
5805         switch (filter_op) {
5806         case RTE_ETH_FILTER_ADD:
5807                 ret = ixgbe_syn_filter_set(dev,
5808                                 (struct rte_eth_syn_filter *)arg,
5809                                 TRUE);
5810                 break;
5811         case RTE_ETH_FILTER_DELETE:
5812                 ret = ixgbe_syn_filter_set(dev,
5813                                 (struct rte_eth_syn_filter *)arg,
5814                                 FALSE);
5815                 break;
5816         case RTE_ETH_FILTER_GET:
5817                 ret = ixgbe_syn_filter_get(dev,
5818                                 (struct rte_eth_syn_filter *)arg);
5819                 break;
5820         default:
5821                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5822                 ret = -EINVAL;
5823                 break;
5824         }
5825
5826         return ret;
5827 }
5828
5829
5830 static inline enum ixgbe_5tuple_protocol
5831 convert_protocol_type(uint8_t protocol_value)
5832 {
5833         if (protocol_value == IPPROTO_TCP)
5834                 return IXGBE_FILTER_PROTOCOL_TCP;
5835         else if (protocol_value == IPPROTO_UDP)
5836                 return IXGBE_FILTER_PROTOCOL_UDP;
5837         else if (protocol_value == IPPROTO_SCTP)
5838                 return IXGBE_FILTER_PROTOCOL_SCTP;
5839         else
5840                 return IXGBE_FILTER_PROTOCOL_NONE;
5841 }
5842
5843 /* inject a 5-tuple filter to HW */
5844 static inline void
5845 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5846                            struct ixgbe_5tuple_filter *filter)
5847 {
5848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5849         int i;
5850         uint32_t ftqf, sdpqf;
5851         uint32_t l34timir = 0;
5852         uint8_t mask = 0xff;
5853
5854         i = filter->index;
5855
5856         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5857                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5858         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5859
5860         ftqf = (uint32_t)(filter->filter_info.proto &
5861                 IXGBE_FTQF_PROTOCOL_MASK);
5862         ftqf |= (uint32_t)((filter->filter_info.priority &
5863                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5864         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5865                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5866         if (filter->filter_info.dst_ip_mask == 0)
5867                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5868         if (filter->filter_info.src_port_mask == 0)
5869                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5870         if (filter->filter_info.dst_port_mask == 0)
5871                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5872         if (filter->filter_info.proto_mask == 0)
5873                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5874         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5875         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5876         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5877
5878         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5879         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5880         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5881         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5882
5883         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5884         l34timir |= (uint32_t)(filter->queue <<
5885                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5886         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5887 }
5888
5889 /*
5890  * add a 5tuple filter
5891  *
5892  * @param
5893  * dev: Pointer to struct rte_eth_dev.
5894  * index: the index the filter allocates.
5895  * filter: ponter to the filter that will be added.
5896  * rx_queue: the queue id the filter assigned to.
5897  *
5898  * @return
5899  *    - On success, zero.
5900  *    - On failure, a negative value.
5901  */
5902 static int
5903 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5904                         struct ixgbe_5tuple_filter *filter)
5905 {
5906         struct ixgbe_filter_info *filter_info =
5907                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5908         int i, idx, shift;
5909
5910         /*
5911          * look for an unused 5tuple filter index,
5912          * and insert the filter to list.
5913          */
5914         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5915                 idx = i / (sizeof(uint32_t) * NBBY);
5916                 shift = i % (sizeof(uint32_t) * NBBY);
5917                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5918                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5919                         filter->index = i;
5920                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5921                                           filter,
5922                                           entries);
5923                         break;
5924                 }
5925         }
5926         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5927                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5928                 return -ENOSYS;
5929         }
5930
5931         ixgbe_inject_5tuple_filter(dev, filter);
5932
5933         return 0;
5934 }
5935
5936 /*
5937  * remove a 5tuple filter
5938  *
5939  * @param
5940  * dev: Pointer to struct rte_eth_dev.
5941  * filter: the pointer of the filter will be removed.
5942  */
5943 static void
5944 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5945                         struct ixgbe_5tuple_filter *filter)
5946 {
5947         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5948         struct ixgbe_filter_info *filter_info =
5949                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5950         uint16_t index = filter->index;
5951
5952         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5953                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5954         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5955         rte_free(filter);
5956
5957         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5958         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5959         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5960         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5961         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5962 }
5963
5964 static int
5965 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5966 {
5967         struct ixgbe_hw *hw;
5968         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5969         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
5970
5971         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5972
5973         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5974                 return -EINVAL;
5975
5976         /* refuse mtu that requires the support of scattered packets when this
5977          * feature has not been enabled before.
5978          */
5979         if (!rx_conf->enable_scatter &&
5980             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5981              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5982                 return -EINVAL;
5983
5984         /*
5985          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5986          * request of the version 2.0 of the mailbox API.
5987          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5988          * of the mailbox API.
5989          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5990          * prior to 3.11.33 which contains the following change:
5991          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5992          */
5993         ixgbevf_rlpml_set_vf(hw, max_frame);
5994
5995         /* update max frame size */
5996         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5997         return 0;
5998 }
5999
6000 static inline struct ixgbe_5tuple_filter *
6001 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6002                         struct ixgbe_5tuple_filter_info *key)
6003 {
6004         struct ixgbe_5tuple_filter *it;
6005
6006         TAILQ_FOREACH(it, filter_list, entries) {
6007                 if (memcmp(key, &it->filter_info,
6008                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6009                         return it;
6010                 }
6011         }
6012         return NULL;
6013 }
6014
6015 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6016 static inline int
6017 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6018                         struct ixgbe_5tuple_filter_info *filter_info)
6019 {
6020         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6021                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6022                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6023                 return -EINVAL;
6024
6025         switch (filter->dst_ip_mask) {
6026         case UINT32_MAX:
6027                 filter_info->dst_ip_mask = 0;
6028                 filter_info->dst_ip = filter->dst_ip;
6029                 break;
6030         case 0:
6031                 filter_info->dst_ip_mask = 1;
6032                 break;
6033         default:
6034                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6035                 return -EINVAL;
6036         }
6037
6038         switch (filter->src_ip_mask) {
6039         case UINT32_MAX:
6040                 filter_info->src_ip_mask = 0;
6041                 filter_info->src_ip = filter->src_ip;
6042                 break;
6043         case 0:
6044                 filter_info->src_ip_mask = 1;
6045                 break;
6046         default:
6047                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6048                 return -EINVAL;
6049         }
6050
6051         switch (filter->dst_port_mask) {
6052         case UINT16_MAX:
6053                 filter_info->dst_port_mask = 0;
6054                 filter_info->dst_port = filter->dst_port;
6055                 break;
6056         case 0:
6057                 filter_info->dst_port_mask = 1;
6058                 break;
6059         default:
6060                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6061                 return -EINVAL;
6062         }
6063
6064         switch (filter->src_port_mask) {
6065         case UINT16_MAX:
6066                 filter_info->src_port_mask = 0;
6067                 filter_info->src_port = filter->src_port;
6068                 break;
6069         case 0:
6070                 filter_info->src_port_mask = 1;
6071                 break;
6072         default:
6073                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6074                 return -EINVAL;
6075         }
6076
6077         switch (filter->proto_mask) {
6078         case UINT8_MAX:
6079                 filter_info->proto_mask = 0;
6080                 filter_info->proto =
6081                         convert_protocol_type(filter->proto);
6082                 break;
6083         case 0:
6084                 filter_info->proto_mask = 1;
6085                 break;
6086         default:
6087                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6088                 return -EINVAL;
6089         }
6090
6091         filter_info->priority = (uint8_t)filter->priority;
6092         return 0;
6093 }
6094
6095 /*
6096  * add or delete a ntuple filter
6097  *
6098  * @param
6099  * dev: Pointer to struct rte_eth_dev.
6100  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6101  * add: if true, add filter, if false, remove filter
6102  *
6103  * @return
6104  *    - On success, zero.
6105  *    - On failure, a negative value.
6106  */
6107 int
6108 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6109                         struct rte_eth_ntuple_filter *ntuple_filter,
6110                         bool add)
6111 {
6112         struct ixgbe_filter_info *filter_info =
6113                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6114         struct ixgbe_5tuple_filter_info filter_5tuple;
6115         struct ixgbe_5tuple_filter *filter;
6116         int ret;
6117
6118         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6119                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6120                 return -EINVAL;
6121         }
6122
6123         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6124         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6125         if (ret < 0)
6126                 return ret;
6127
6128         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6129                                          &filter_5tuple);
6130         if (filter != NULL && add) {
6131                 PMD_DRV_LOG(ERR, "filter exists.");
6132                 return -EEXIST;
6133         }
6134         if (filter == NULL && !add) {
6135                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6136                 return -ENOENT;
6137         }
6138
6139         if (add) {
6140                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6141                                 sizeof(struct ixgbe_5tuple_filter), 0);
6142                 if (filter == NULL)
6143                         return -ENOMEM;
6144                 (void)rte_memcpy(&filter->filter_info,
6145                                  &filter_5tuple,
6146                                  sizeof(struct ixgbe_5tuple_filter_info));
6147                 filter->queue = ntuple_filter->queue;
6148                 ret = ixgbe_add_5tuple_filter(dev, filter);
6149                 if (ret < 0) {
6150                         rte_free(filter);
6151                         return ret;
6152                 }
6153         } else
6154                 ixgbe_remove_5tuple_filter(dev, filter);
6155
6156         return 0;
6157 }
6158
6159 /*
6160  * get a ntuple filter
6161  *
6162  * @param
6163  * dev: Pointer to struct rte_eth_dev.
6164  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6165  *
6166  * @return
6167  *    - On success, zero.
6168  *    - On failure, a negative value.
6169  */
6170 static int
6171 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6172                         struct rte_eth_ntuple_filter *ntuple_filter)
6173 {
6174         struct ixgbe_filter_info *filter_info =
6175                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6176         struct ixgbe_5tuple_filter_info filter_5tuple;
6177         struct ixgbe_5tuple_filter *filter;
6178         int ret;
6179
6180         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6181                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6182                 return -EINVAL;
6183         }
6184
6185         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6186         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6187         if (ret < 0)
6188                 return ret;
6189
6190         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6191                                          &filter_5tuple);
6192         if (filter == NULL) {
6193                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6194                 return -ENOENT;
6195         }
6196         ntuple_filter->queue = filter->queue;
6197         return 0;
6198 }
6199
6200 /*
6201  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6202  * @dev: pointer to rte_eth_dev structure
6203  * @filter_op:operation will be taken.
6204  * @arg: a pointer to specific structure corresponding to the filter_op
6205  *
6206  * @return
6207  *    - On success, zero.
6208  *    - On failure, a negative value.
6209  */
6210 static int
6211 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6212                                 enum rte_filter_op filter_op,
6213                                 void *arg)
6214 {
6215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6216         int ret;
6217
6218         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6219
6220         if (filter_op == RTE_ETH_FILTER_NOP)
6221                 return 0;
6222
6223         if (arg == NULL) {
6224                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6225                             filter_op);
6226                 return -EINVAL;
6227         }
6228
6229         switch (filter_op) {
6230         case RTE_ETH_FILTER_ADD:
6231                 ret = ixgbe_add_del_ntuple_filter(dev,
6232                         (struct rte_eth_ntuple_filter *)arg,
6233                         TRUE);
6234                 break;
6235         case RTE_ETH_FILTER_DELETE:
6236                 ret = ixgbe_add_del_ntuple_filter(dev,
6237                         (struct rte_eth_ntuple_filter *)arg,
6238                         FALSE);
6239                 break;
6240         case RTE_ETH_FILTER_GET:
6241                 ret = ixgbe_get_ntuple_filter(dev,
6242                         (struct rte_eth_ntuple_filter *)arg);
6243                 break;
6244         default:
6245                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6246                 ret = -EINVAL;
6247                 break;
6248         }
6249         return ret;
6250 }
6251
6252 int
6253 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6254                         struct rte_eth_ethertype_filter *filter,
6255                         bool add)
6256 {
6257         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6258         struct ixgbe_filter_info *filter_info =
6259                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6260         uint32_t etqf = 0;
6261         uint32_t etqs = 0;
6262         int ret;
6263         struct ixgbe_ethertype_filter ethertype_filter;
6264
6265         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6266                 return -EINVAL;
6267
6268         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6269                 filter->ether_type == ETHER_TYPE_IPv6) {
6270                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6271                         " ethertype filter.", filter->ether_type);
6272                 return -EINVAL;
6273         }
6274
6275         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6276                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6277                 return -EINVAL;
6278         }
6279         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6280                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6281                 return -EINVAL;
6282         }
6283
6284         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6285         if (ret >= 0 && add) {
6286                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6287                             filter->ether_type);
6288                 return -EEXIST;
6289         }
6290         if (ret < 0 && !add) {
6291                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6292                             filter->ether_type);
6293                 return -ENOENT;
6294         }
6295
6296         if (add) {
6297                 etqf = IXGBE_ETQF_FILTER_EN;
6298                 etqf |= (uint32_t)filter->ether_type;
6299                 etqs |= (uint32_t)((filter->queue <<
6300                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6301                                     IXGBE_ETQS_RX_QUEUE);
6302                 etqs |= IXGBE_ETQS_QUEUE_EN;
6303
6304                 ethertype_filter.ethertype = filter->ether_type;
6305                 ethertype_filter.etqf = etqf;
6306                 ethertype_filter.etqs = etqs;
6307                 ethertype_filter.conf = FALSE;
6308                 ret = ixgbe_ethertype_filter_insert(filter_info,
6309                                                     &ethertype_filter);
6310                 if (ret < 0) {
6311                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6312                         return -ENOSPC;
6313                 }
6314         } else {
6315                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6316                 if (ret < 0)
6317                         return -ENOSYS;
6318         }
6319         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6320         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6321         IXGBE_WRITE_FLUSH(hw);
6322
6323         return 0;
6324 }
6325
6326 static int
6327 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6328                         struct rte_eth_ethertype_filter *filter)
6329 {
6330         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6331         struct ixgbe_filter_info *filter_info =
6332                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6333         uint32_t etqf, etqs;
6334         int ret;
6335
6336         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6337         if (ret < 0) {
6338                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6339                             filter->ether_type);
6340                 return -ENOENT;
6341         }
6342
6343         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6344         if (etqf & IXGBE_ETQF_FILTER_EN) {
6345                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6346                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6347                 filter->flags = 0;
6348                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6349                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6350                 return 0;
6351         }
6352         return -ENOENT;
6353 }
6354
6355 /*
6356  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6357  * @dev: pointer to rte_eth_dev structure
6358  * @filter_op:operation will be taken.
6359  * @arg: a pointer to specific structure corresponding to the filter_op
6360  */
6361 static int
6362 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6363                                 enum rte_filter_op filter_op,
6364                                 void *arg)
6365 {
6366         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6367         int ret;
6368
6369         MAC_TYPE_FILTER_SUP(hw->mac.type);
6370
6371         if (filter_op == RTE_ETH_FILTER_NOP)
6372                 return 0;
6373
6374         if (arg == NULL) {
6375                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6376                             filter_op);
6377                 return -EINVAL;
6378         }
6379
6380         switch (filter_op) {
6381         case RTE_ETH_FILTER_ADD:
6382                 ret = ixgbe_add_del_ethertype_filter(dev,
6383                         (struct rte_eth_ethertype_filter *)arg,
6384                         TRUE);
6385                 break;
6386         case RTE_ETH_FILTER_DELETE:
6387                 ret = ixgbe_add_del_ethertype_filter(dev,
6388                         (struct rte_eth_ethertype_filter *)arg,
6389                         FALSE);
6390                 break;
6391         case RTE_ETH_FILTER_GET:
6392                 ret = ixgbe_get_ethertype_filter(dev,
6393                         (struct rte_eth_ethertype_filter *)arg);
6394                 break;
6395         default:
6396                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6397                 ret = -EINVAL;
6398                 break;
6399         }
6400         return ret;
6401 }
6402
6403 static int
6404 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6405                      enum rte_filter_type filter_type,
6406                      enum rte_filter_op filter_op,
6407                      void *arg)
6408 {
6409         int ret = 0;
6410
6411         switch (filter_type) {
6412         case RTE_ETH_FILTER_NTUPLE:
6413                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6414                 break;
6415         case RTE_ETH_FILTER_ETHERTYPE:
6416                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6417                 break;
6418         case RTE_ETH_FILTER_SYN:
6419                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6420                 break;
6421         case RTE_ETH_FILTER_FDIR:
6422                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6423                 break;
6424         case RTE_ETH_FILTER_L2_TUNNEL:
6425                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6426                 break;
6427         case RTE_ETH_FILTER_GENERIC:
6428                 if (filter_op != RTE_ETH_FILTER_GET)
6429                         return -EINVAL;
6430                 *(const void **)arg = &ixgbe_flow_ops;
6431                 break;
6432         default:
6433                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6434                                                         filter_type);
6435                 ret = -EINVAL;
6436                 break;
6437         }
6438
6439         return ret;
6440 }
6441
6442 static u8 *
6443 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6444                         u8 **mc_addr_ptr, u32 *vmdq)
6445 {
6446         u8 *mc_addr;
6447
6448         *vmdq = 0;
6449         mc_addr = *mc_addr_ptr;
6450         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6451         return mc_addr;
6452 }
6453
6454 static int
6455 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6456                           struct ether_addr *mc_addr_set,
6457                           uint32_t nb_mc_addr)
6458 {
6459         struct ixgbe_hw *hw;
6460         u8 *mc_addr_list;
6461
6462         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6463         mc_addr_list = (u8 *)mc_addr_set;
6464         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6465                                          ixgbe_dev_addr_list_itr, TRUE);
6466 }
6467
6468 static uint64_t
6469 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6470 {
6471         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6472         uint64_t systime_cycles;
6473
6474         switch (hw->mac.type) {
6475         case ixgbe_mac_X550:
6476         case ixgbe_mac_X550EM_x:
6477         case ixgbe_mac_X550EM_a:
6478                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6479                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6480                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6481                                 * NSEC_PER_SEC;
6482                 break;
6483         default:
6484                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6485                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6486                                 << 32;
6487         }
6488
6489         return systime_cycles;
6490 }
6491
6492 static uint64_t
6493 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6494 {
6495         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6496         uint64_t rx_tstamp_cycles;
6497
6498         switch (hw->mac.type) {
6499         case ixgbe_mac_X550:
6500         case ixgbe_mac_X550EM_x:
6501         case ixgbe_mac_X550EM_a:
6502                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6503                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6504                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6505                                 * NSEC_PER_SEC;
6506                 break;
6507         default:
6508                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6509                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6510                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6511                                 << 32;
6512         }
6513
6514         return rx_tstamp_cycles;
6515 }
6516
6517 static uint64_t
6518 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6519 {
6520         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6521         uint64_t tx_tstamp_cycles;
6522
6523         switch (hw->mac.type) {
6524         case ixgbe_mac_X550:
6525         case ixgbe_mac_X550EM_x:
6526         case ixgbe_mac_X550EM_a:
6527                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6528                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6529                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6530                                 * NSEC_PER_SEC;
6531                 break;
6532         default:
6533                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6534                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6535                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6536                                 << 32;
6537         }
6538
6539         return tx_tstamp_cycles;
6540 }
6541
6542 static void
6543 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6544 {
6545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6546         struct ixgbe_adapter *adapter =
6547                 (struct ixgbe_adapter *)dev->data->dev_private;
6548         struct rte_eth_link link;
6549         uint32_t incval = 0;
6550         uint32_t shift = 0;
6551
6552         /* Get current link speed. */
6553         memset(&link, 0, sizeof(link));
6554         ixgbe_dev_link_update(dev, 1);
6555         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6556
6557         switch (link.link_speed) {
6558         case ETH_SPEED_NUM_100M:
6559                 incval = IXGBE_INCVAL_100;
6560                 shift = IXGBE_INCVAL_SHIFT_100;
6561                 break;
6562         case ETH_SPEED_NUM_1G:
6563                 incval = IXGBE_INCVAL_1GB;
6564                 shift = IXGBE_INCVAL_SHIFT_1GB;
6565                 break;
6566         case ETH_SPEED_NUM_10G:
6567         default:
6568                 incval = IXGBE_INCVAL_10GB;
6569                 shift = IXGBE_INCVAL_SHIFT_10GB;
6570                 break;
6571         }
6572
6573         switch (hw->mac.type) {
6574         case ixgbe_mac_X550:
6575         case ixgbe_mac_X550EM_x:
6576         case ixgbe_mac_X550EM_a:
6577                 /* Independent of link speed. */
6578                 incval = 1;
6579                 /* Cycles read will be interpreted as ns. */
6580                 shift = 0;
6581                 /* Fall-through */
6582         case ixgbe_mac_X540:
6583                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6584                 break;
6585         case ixgbe_mac_82599EB:
6586                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6587                 shift -= IXGBE_INCVAL_SHIFT_82599;
6588                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6589                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6590                 break;
6591         default:
6592                 /* Not supported. */
6593                 return;
6594         }
6595
6596         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6597         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6598         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6599
6600         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6601         adapter->systime_tc.cc_shift = shift;
6602         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6603
6604         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6605         adapter->rx_tstamp_tc.cc_shift = shift;
6606         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6607
6608         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6609         adapter->tx_tstamp_tc.cc_shift = shift;
6610         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6611 }
6612
6613 static int
6614 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6615 {
6616         struct ixgbe_adapter *adapter =
6617                         (struct ixgbe_adapter *)dev->data->dev_private;
6618
6619         adapter->systime_tc.nsec += delta;
6620         adapter->rx_tstamp_tc.nsec += delta;
6621         adapter->tx_tstamp_tc.nsec += delta;
6622
6623         return 0;
6624 }
6625
6626 static int
6627 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6628 {
6629         uint64_t ns;
6630         struct ixgbe_adapter *adapter =
6631                         (struct ixgbe_adapter *)dev->data->dev_private;
6632
6633         ns = rte_timespec_to_ns(ts);
6634         /* Set the timecounters to a new value. */
6635         adapter->systime_tc.nsec = ns;
6636         adapter->rx_tstamp_tc.nsec = ns;
6637         adapter->tx_tstamp_tc.nsec = ns;
6638
6639         return 0;
6640 }
6641
6642 static int
6643 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6644 {
6645         uint64_t ns, systime_cycles;
6646         struct ixgbe_adapter *adapter =
6647                         (struct ixgbe_adapter *)dev->data->dev_private;
6648
6649         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6650         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6651         *ts = rte_ns_to_timespec(ns);
6652
6653         return 0;
6654 }
6655
6656 static int
6657 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6658 {
6659         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6660         uint32_t tsync_ctl;
6661         uint32_t tsauxc;
6662
6663         /* Stop the timesync system time. */
6664         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6665         /* Reset the timesync system time value. */
6666         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6667         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6668
6669         /* Enable system time for platforms where it isn't on by default. */
6670         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6671         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6672         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6673
6674         ixgbe_start_timecounters(dev);
6675
6676         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6677         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6678                         (ETHER_TYPE_1588 |
6679                          IXGBE_ETQF_FILTER_EN |
6680                          IXGBE_ETQF_1588));
6681
6682         /* Enable timestamping of received PTP packets. */
6683         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6684         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6685         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6686
6687         /* Enable timestamping of transmitted PTP packets. */
6688         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6689         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6690         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6691
6692         IXGBE_WRITE_FLUSH(hw);
6693
6694         return 0;
6695 }
6696
6697 static int
6698 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6699 {
6700         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6701         uint32_t tsync_ctl;
6702
6703         /* Disable timestamping of transmitted PTP packets. */
6704         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6705         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6706         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6707
6708         /* Disable timestamping of received PTP packets. */
6709         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6710         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6711         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6712
6713         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6714         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6715
6716         /* Stop incrementating the System Time registers. */
6717         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6718
6719         return 0;
6720 }
6721
6722 static int
6723 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6724                                  struct timespec *timestamp,
6725                                  uint32_t flags __rte_unused)
6726 {
6727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6728         struct ixgbe_adapter *adapter =
6729                 (struct ixgbe_adapter *)dev->data->dev_private;
6730         uint32_t tsync_rxctl;
6731         uint64_t rx_tstamp_cycles;
6732         uint64_t ns;
6733
6734         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6735         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6736                 return -EINVAL;
6737
6738         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6739         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6740         *timestamp = rte_ns_to_timespec(ns);
6741
6742         return  0;
6743 }
6744
6745 static int
6746 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6747                                  struct timespec *timestamp)
6748 {
6749         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6750         struct ixgbe_adapter *adapter =
6751                 (struct ixgbe_adapter *)dev->data->dev_private;
6752         uint32_t tsync_txctl;
6753         uint64_t tx_tstamp_cycles;
6754         uint64_t ns;
6755
6756         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6757         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6758                 return -EINVAL;
6759
6760         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6761         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6762         *timestamp = rte_ns_to_timespec(ns);
6763
6764         return 0;
6765 }
6766
6767 static int
6768 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6769 {
6770         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6771         int count = 0;
6772         int g_ind = 0;
6773         const struct reg_info *reg_group;
6774         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6775                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6776
6777         while ((reg_group = reg_set[g_ind++]))
6778                 count += ixgbe_regs_group_count(reg_group);
6779
6780         return count;
6781 }
6782
6783 static int
6784 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6785 {
6786         int count = 0;
6787         int g_ind = 0;
6788         const struct reg_info *reg_group;
6789
6790         while ((reg_group = ixgbevf_regs[g_ind++]))
6791                 count += ixgbe_regs_group_count(reg_group);
6792
6793         return count;
6794 }
6795
6796 static int
6797 ixgbe_get_regs(struct rte_eth_dev *dev,
6798               struct rte_dev_reg_info *regs)
6799 {
6800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6801         uint32_t *data = regs->data;
6802         int g_ind = 0;
6803         int count = 0;
6804         const struct reg_info *reg_group;
6805         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6806                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6807
6808         if (data == NULL) {
6809                 regs->length = ixgbe_get_reg_length(dev);
6810                 regs->width = sizeof(uint32_t);
6811                 return 0;
6812         }
6813
6814         /* Support only full register dump */
6815         if ((regs->length == 0) ||
6816             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6817                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6818                         hw->device_id;
6819                 while ((reg_group = reg_set[g_ind++]))
6820                         count += ixgbe_read_regs_group(dev, &data[count],
6821                                 reg_group);
6822                 return 0;
6823         }
6824
6825         return -ENOTSUP;
6826 }
6827
6828 static int
6829 ixgbevf_get_regs(struct rte_eth_dev *dev,
6830                 struct rte_dev_reg_info *regs)
6831 {
6832         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6833         uint32_t *data = regs->data;
6834         int g_ind = 0;
6835         int count = 0;
6836         const struct reg_info *reg_group;
6837
6838         if (data == NULL) {
6839                 regs->length = ixgbevf_get_reg_length(dev);
6840                 regs->width = sizeof(uint32_t);
6841                 return 0;
6842         }
6843
6844         /* Support only full register dump */
6845         if ((regs->length == 0) ||
6846             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6847                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6848                         hw->device_id;
6849                 while ((reg_group = ixgbevf_regs[g_ind++]))
6850                         count += ixgbe_read_regs_group(dev, &data[count],
6851                                                       reg_group);
6852                 return 0;
6853         }
6854
6855         return -ENOTSUP;
6856 }
6857
6858 static int
6859 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6860 {
6861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6862
6863         /* Return unit is byte count */
6864         return hw->eeprom.word_size * 2;
6865 }
6866
6867 static int
6868 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6869                 struct rte_dev_eeprom_info *in_eeprom)
6870 {
6871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6872         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6873         uint16_t *data = in_eeprom->data;
6874         int first, length;
6875
6876         first = in_eeprom->offset >> 1;
6877         length = in_eeprom->length >> 1;
6878         if ((first > hw->eeprom.word_size) ||
6879             ((first + length) > hw->eeprom.word_size))
6880                 return -EINVAL;
6881
6882         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6883
6884         return eeprom->ops.read_buffer(hw, first, length, data);
6885 }
6886
6887 static int
6888 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6889                 struct rte_dev_eeprom_info *in_eeprom)
6890 {
6891         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6892         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6893         uint16_t *data = in_eeprom->data;
6894         int first, length;
6895
6896         first = in_eeprom->offset >> 1;
6897         length = in_eeprom->length >> 1;
6898         if ((first > hw->eeprom.word_size) ||
6899             ((first + length) > hw->eeprom.word_size))
6900                 return -EINVAL;
6901
6902         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6903
6904         return eeprom->ops.write_buffer(hw,  first, length, data);
6905 }
6906
6907 uint16_t
6908 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6909         switch (mac_type) {
6910         case ixgbe_mac_X550:
6911         case ixgbe_mac_X550EM_x:
6912         case ixgbe_mac_X550EM_a:
6913                 return ETH_RSS_RETA_SIZE_512;
6914         case ixgbe_mac_X550_vf:
6915         case ixgbe_mac_X550EM_x_vf:
6916         case ixgbe_mac_X550EM_a_vf:
6917                 return ETH_RSS_RETA_SIZE_64;
6918         default:
6919                 return ETH_RSS_RETA_SIZE_128;
6920         }
6921 }
6922
6923 uint32_t
6924 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6925         switch (mac_type) {
6926         case ixgbe_mac_X550:
6927         case ixgbe_mac_X550EM_x:
6928         case ixgbe_mac_X550EM_a:
6929                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6930                         return IXGBE_RETA(reta_idx >> 2);
6931                 else
6932                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6933         case ixgbe_mac_X550_vf:
6934         case ixgbe_mac_X550EM_x_vf:
6935         case ixgbe_mac_X550EM_a_vf:
6936                 return IXGBE_VFRETA(reta_idx >> 2);
6937         default:
6938                 return IXGBE_RETA(reta_idx >> 2);
6939         }
6940 }
6941
6942 uint32_t
6943 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6944         switch (mac_type) {
6945         case ixgbe_mac_X550_vf:
6946         case ixgbe_mac_X550EM_x_vf:
6947         case ixgbe_mac_X550EM_a_vf:
6948                 return IXGBE_VFMRQC;
6949         default:
6950                 return IXGBE_MRQC;
6951         }
6952 }
6953
6954 uint32_t
6955 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6956         switch (mac_type) {
6957         case ixgbe_mac_X550_vf:
6958         case ixgbe_mac_X550EM_x_vf:
6959         case ixgbe_mac_X550EM_a_vf:
6960                 return IXGBE_VFRSSRK(i);
6961         default:
6962                 return IXGBE_RSSRK(i);
6963         }
6964 }
6965
6966 bool
6967 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6968         switch (mac_type) {
6969         case ixgbe_mac_82599_vf:
6970         case ixgbe_mac_X540_vf:
6971                 return 0;
6972         default:
6973                 return 1;
6974         }
6975 }
6976
6977 static int
6978 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6979                         struct rte_eth_dcb_info *dcb_info)
6980 {
6981         struct ixgbe_dcb_config *dcb_config =
6982                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6983         struct ixgbe_dcb_tc_config *tc;
6984         uint8_t i, j;
6985
6986         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6987                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6988         else
6989                 dcb_info->nb_tcs = 1;
6990
6991         if (dcb_config->vt_mode) { /* vt is enabled*/
6992                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6993                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6994                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6995                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6996                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6997                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6998                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6999                                                 i * dcb_info->nb_tcs + j;
7000                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7001                                 dcb_info->tc_queue.tc_txq[i][j].base =
7002                                                 i * dcb_info->nb_tcs + j;
7003                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7004                         }
7005                 }
7006         } else { /* vt is disabled*/
7007                 struct rte_eth_dcb_rx_conf *rx_conf =
7008                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7009                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7010                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7011                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7012                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7013                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7014                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7015                         }
7016                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7017                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7018                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7019                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7020                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7021                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7022                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7023                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7024                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7025                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7026                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7027                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7028                         }
7029                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7030                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7031                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7032                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7033                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7034                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7035                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7036                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7037                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7038                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7039                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7040                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7041                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7042                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7043                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7044                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7045                 }
7046         }
7047         for (i = 0; i < dcb_info->nb_tcs; i++) {
7048                 tc = &dcb_config->tc_config[i];
7049                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7050         }
7051         return 0;
7052 }
7053
7054 /* Update e-tag ether type */
7055 static int
7056 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7057                             uint16_t ether_type)
7058 {
7059         uint32_t etag_etype;
7060
7061         if (hw->mac.type != ixgbe_mac_X550 &&
7062             hw->mac.type != ixgbe_mac_X550EM_x &&
7063             hw->mac.type != ixgbe_mac_X550EM_a) {
7064                 return -ENOTSUP;
7065         }
7066
7067         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7068         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7069         etag_etype |= ether_type;
7070         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7071         IXGBE_WRITE_FLUSH(hw);
7072
7073         return 0;
7074 }
7075
7076 /* Config l2 tunnel ether type */
7077 static int
7078 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7079                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7080 {
7081         int ret = 0;
7082         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7083         struct ixgbe_l2_tn_info *l2_tn_info =
7084                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7085
7086         if (l2_tunnel == NULL)
7087                 return -EINVAL;
7088
7089         switch (l2_tunnel->l2_tunnel_type) {
7090         case RTE_L2_TUNNEL_TYPE_E_TAG:
7091                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7092                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7093                 break;
7094         default:
7095                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7096                 ret = -EINVAL;
7097                 break;
7098         }
7099
7100         return ret;
7101 }
7102
7103 /* Enable e-tag tunnel */
7104 static int
7105 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7106 {
7107         uint32_t etag_etype;
7108
7109         if (hw->mac.type != ixgbe_mac_X550 &&
7110             hw->mac.type != ixgbe_mac_X550EM_x &&
7111             hw->mac.type != ixgbe_mac_X550EM_a) {
7112                 return -ENOTSUP;
7113         }
7114
7115         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7116         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7117         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7118         IXGBE_WRITE_FLUSH(hw);
7119
7120         return 0;
7121 }
7122
7123 /* Enable l2 tunnel */
7124 static int
7125 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7126                            enum rte_eth_tunnel_type l2_tunnel_type)
7127 {
7128         int ret = 0;
7129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7130         struct ixgbe_l2_tn_info *l2_tn_info =
7131                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7132
7133         switch (l2_tunnel_type) {
7134         case RTE_L2_TUNNEL_TYPE_E_TAG:
7135                 l2_tn_info->e_tag_en = TRUE;
7136                 ret = ixgbe_e_tag_enable(hw);
7137                 break;
7138         default:
7139                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7140                 ret = -EINVAL;
7141                 break;
7142         }
7143
7144         return ret;
7145 }
7146
7147 /* Disable e-tag tunnel */
7148 static int
7149 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7150 {
7151         uint32_t etag_etype;
7152
7153         if (hw->mac.type != ixgbe_mac_X550 &&
7154             hw->mac.type != ixgbe_mac_X550EM_x &&
7155             hw->mac.type != ixgbe_mac_X550EM_a) {
7156                 return -ENOTSUP;
7157         }
7158
7159         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7160         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7161         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7162         IXGBE_WRITE_FLUSH(hw);
7163
7164         return 0;
7165 }
7166
7167 /* Disable l2 tunnel */
7168 static int
7169 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7170                             enum rte_eth_tunnel_type l2_tunnel_type)
7171 {
7172         int ret = 0;
7173         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7174         struct ixgbe_l2_tn_info *l2_tn_info =
7175                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7176
7177         switch (l2_tunnel_type) {
7178         case RTE_L2_TUNNEL_TYPE_E_TAG:
7179                 l2_tn_info->e_tag_en = FALSE;
7180                 ret = ixgbe_e_tag_disable(hw);
7181                 break;
7182         default:
7183                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7184                 ret = -EINVAL;
7185                 break;
7186         }
7187
7188         return ret;
7189 }
7190
7191 static int
7192 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7193                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7194 {
7195         int ret = 0;
7196         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7197         uint32_t i, rar_entries;
7198         uint32_t rar_low, rar_high;
7199
7200         if (hw->mac.type != ixgbe_mac_X550 &&
7201             hw->mac.type != ixgbe_mac_X550EM_x &&
7202             hw->mac.type != ixgbe_mac_X550EM_a) {
7203                 return -ENOTSUP;
7204         }
7205
7206         rar_entries = ixgbe_get_num_rx_addrs(hw);
7207
7208         for (i = 1; i < rar_entries; i++) {
7209                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7210                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7211                 if ((rar_high & IXGBE_RAH_AV) &&
7212                     (rar_high & IXGBE_RAH_ADTYPE) &&
7213                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7214                      l2_tunnel->tunnel_id)) {
7215                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7216                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7217
7218                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7219
7220                         return ret;
7221                 }
7222         }
7223
7224         return ret;
7225 }
7226
7227 static int
7228 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7229                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7230 {
7231         int ret = 0;
7232         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7233         uint32_t i, rar_entries;
7234         uint32_t rar_low, rar_high;
7235
7236         if (hw->mac.type != ixgbe_mac_X550 &&
7237             hw->mac.type != ixgbe_mac_X550EM_x &&
7238             hw->mac.type != ixgbe_mac_X550EM_a) {
7239                 return -ENOTSUP;
7240         }
7241
7242         /* One entry for one tunnel. Try to remove potential existing entry. */
7243         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7244
7245         rar_entries = ixgbe_get_num_rx_addrs(hw);
7246
7247         for (i = 1; i < rar_entries; i++) {
7248                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7249                 if (rar_high & IXGBE_RAH_AV) {
7250                         continue;
7251                 } else {
7252                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7253                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7254                         rar_low = l2_tunnel->tunnel_id;
7255
7256                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7257                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7258
7259                         return ret;
7260                 }
7261         }
7262
7263         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7264                      " Please remove a rule before adding a new one.");
7265         return -EINVAL;
7266 }
7267
7268 static inline struct ixgbe_l2_tn_filter *
7269 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7270                           struct ixgbe_l2_tn_key *key)
7271 {
7272         int ret;
7273
7274         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7275         if (ret < 0)
7276                 return NULL;
7277
7278         return l2_tn_info->hash_map[ret];
7279 }
7280
7281 static inline int
7282 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7283                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7284 {
7285         int ret;
7286
7287         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7288                                &l2_tn_filter->key);
7289
7290         if (ret < 0) {
7291                 PMD_DRV_LOG(ERR,
7292                             "Failed to insert L2 tunnel filter"
7293                             " to hash table %d!",
7294                             ret);
7295                 return ret;
7296         }
7297
7298         l2_tn_info->hash_map[ret] = l2_tn_filter;
7299
7300         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7301
7302         return 0;
7303 }
7304
7305 static inline int
7306 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7307                           struct ixgbe_l2_tn_key *key)
7308 {
7309         int ret;
7310         struct ixgbe_l2_tn_filter *l2_tn_filter;
7311
7312         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7313
7314         if (ret < 0) {
7315                 PMD_DRV_LOG(ERR,
7316                             "No such L2 tunnel filter to delete %d!",
7317                             ret);
7318                 return ret;
7319         }
7320
7321         l2_tn_filter = l2_tn_info->hash_map[ret];
7322         l2_tn_info->hash_map[ret] = NULL;
7323
7324         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7325         rte_free(l2_tn_filter);
7326
7327         return 0;
7328 }
7329
7330 /* Add l2 tunnel filter */
7331 int
7332 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7333                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7334                                bool restore)
7335 {
7336         int ret;
7337         struct ixgbe_l2_tn_info *l2_tn_info =
7338                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7339         struct ixgbe_l2_tn_key key;
7340         struct ixgbe_l2_tn_filter *node;
7341
7342         if (!restore) {
7343                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7344                 key.tn_id = l2_tunnel->tunnel_id;
7345
7346                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7347
7348                 if (node) {
7349                         PMD_DRV_LOG(ERR,
7350                                     "The L2 tunnel filter already exists!");
7351                         return -EINVAL;
7352                 }
7353
7354                 node = rte_zmalloc("ixgbe_l2_tn",
7355                                    sizeof(struct ixgbe_l2_tn_filter),
7356                                    0);
7357                 if (!node)
7358                         return -ENOMEM;
7359
7360                 (void)rte_memcpy(&node->key,
7361                                  &key,
7362                                  sizeof(struct ixgbe_l2_tn_key));
7363                 node->pool = l2_tunnel->pool;
7364                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7365                 if (ret < 0) {
7366                         rte_free(node);
7367                         return ret;
7368                 }
7369         }
7370
7371         switch (l2_tunnel->l2_tunnel_type) {
7372         case RTE_L2_TUNNEL_TYPE_E_TAG:
7373                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7374                 break;
7375         default:
7376                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7377                 ret = -EINVAL;
7378                 break;
7379         }
7380
7381         if ((!restore) && (ret < 0))
7382                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7383
7384         return ret;
7385 }
7386
7387 /* Delete l2 tunnel filter */
7388 int
7389 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7390                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7391 {
7392         int ret;
7393         struct ixgbe_l2_tn_info *l2_tn_info =
7394                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7395         struct ixgbe_l2_tn_key key;
7396
7397         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7398         key.tn_id = l2_tunnel->tunnel_id;
7399         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7400         if (ret < 0)
7401                 return ret;
7402
7403         switch (l2_tunnel->l2_tunnel_type) {
7404         case RTE_L2_TUNNEL_TYPE_E_TAG:
7405                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7406                 break;
7407         default:
7408                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7409                 ret = -EINVAL;
7410                 break;
7411         }
7412
7413         return ret;
7414 }
7415
7416 /**
7417  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7418  * @dev: pointer to rte_eth_dev structure
7419  * @filter_op:operation will be taken.
7420  * @arg: a pointer to specific structure corresponding to the filter_op
7421  */
7422 static int
7423 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7424                                   enum rte_filter_op filter_op,
7425                                   void *arg)
7426 {
7427         int ret;
7428
7429         if (filter_op == RTE_ETH_FILTER_NOP)
7430                 return 0;
7431
7432         if (arg == NULL) {
7433                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7434                             filter_op);
7435                 return -EINVAL;
7436         }
7437
7438         switch (filter_op) {
7439         case RTE_ETH_FILTER_ADD:
7440                 ret = ixgbe_dev_l2_tunnel_filter_add
7441                         (dev,
7442                          (struct rte_eth_l2_tunnel_conf *)arg,
7443                          FALSE);
7444                 break;
7445         case RTE_ETH_FILTER_DELETE:
7446                 ret = ixgbe_dev_l2_tunnel_filter_del
7447                         (dev,
7448                          (struct rte_eth_l2_tunnel_conf *)arg);
7449                 break;
7450         default:
7451                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7452                 ret = -EINVAL;
7453                 break;
7454         }
7455         return ret;
7456 }
7457
7458 static int
7459 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7460 {
7461         int ret = 0;
7462         uint32_t ctrl;
7463         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7464
7465         if (hw->mac.type != ixgbe_mac_X550 &&
7466             hw->mac.type != ixgbe_mac_X550EM_x &&
7467             hw->mac.type != ixgbe_mac_X550EM_a) {
7468                 return -ENOTSUP;
7469         }
7470
7471         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7472         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7473         if (en)
7474                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7475         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7476
7477         return ret;
7478 }
7479
7480 /* Enable l2 tunnel forwarding */
7481 static int
7482 ixgbe_dev_l2_tunnel_forwarding_enable
7483         (struct rte_eth_dev *dev,
7484          enum rte_eth_tunnel_type l2_tunnel_type)
7485 {
7486         struct ixgbe_l2_tn_info *l2_tn_info =
7487                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7488         int ret = 0;
7489
7490         switch (l2_tunnel_type) {
7491         case RTE_L2_TUNNEL_TYPE_E_TAG:
7492                 l2_tn_info->e_tag_fwd_en = TRUE;
7493                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7494                 break;
7495         default:
7496                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7497                 ret = -EINVAL;
7498                 break;
7499         }
7500
7501         return ret;
7502 }
7503
7504 /* Disable l2 tunnel forwarding */
7505 static int
7506 ixgbe_dev_l2_tunnel_forwarding_disable
7507         (struct rte_eth_dev *dev,
7508          enum rte_eth_tunnel_type l2_tunnel_type)
7509 {
7510         struct ixgbe_l2_tn_info *l2_tn_info =
7511                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7512         int ret = 0;
7513
7514         switch (l2_tunnel_type) {
7515         case RTE_L2_TUNNEL_TYPE_E_TAG:
7516                 l2_tn_info->e_tag_fwd_en = FALSE;
7517                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7518                 break;
7519         default:
7520                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7521                 ret = -EINVAL;
7522                 break;
7523         }
7524
7525         return ret;
7526 }
7527
7528 static int
7529 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7530                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7531                              bool en)
7532 {
7533         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7534         int ret = 0;
7535         uint32_t vmtir, vmvir;
7536         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7537
7538         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7539                 PMD_DRV_LOG(ERR,
7540                             "VF id %u should be less than %u",
7541                             l2_tunnel->vf_id,
7542                             pci_dev->max_vfs);
7543                 return -EINVAL;
7544         }
7545
7546         if (hw->mac.type != ixgbe_mac_X550 &&
7547             hw->mac.type != ixgbe_mac_X550EM_x &&
7548             hw->mac.type != ixgbe_mac_X550EM_a) {
7549                 return -ENOTSUP;
7550         }
7551
7552         if (en)
7553                 vmtir = l2_tunnel->tunnel_id;
7554         else
7555                 vmtir = 0;
7556
7557         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7558
7559         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7560         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7561         if (en)
7562                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7563         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7564
7565         return ret;
7566 }
7567
7568 /* Enable l2 tunnel tag insertion */
7569 static int
7570 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7571                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7572 {
7573         int ret = 0;
7574
7575         switch (l2_tunnel->l2_tunnel_type) {
7576         case RTE_L2_TUNNEL_TYPE_E_TAG:
7577                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7578                 break;
7579         default:
7580                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7581                 ret = -EINVAL;
7582                 break;
7583         }
7584
7585         return ret;
7586 }
7587
7588 /* Disable l2 tunnel tag insertion */
7589 static int
7590 ixgbe_dev_l2_tunnel_insertion_disable
7591         (struct rte_eth_dev *dev,
7592          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7593 {
7594         int ret = 0;
7595
7596         switch (l2_tunnel->l2_tunnel_type) {
7597         case RTE_L2_TUNNEL_TYPE_E_TAG:
7598                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7599                 break;
7600         default:
7601                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7602                 ret = -EINVAL;
7603                 break;
7604         }
7605
7606         return ret;
7607 }
7608
7609 static int
7610 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7611                              bool en)
7612 {
7613         int ret = 0;
7614         uint32_t qde;
7615         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7616
7617         if (hw->mac.type != ixgbe_mac_X550 &&
7618             hw->mac.type != ixgbe_mac_X550EM_x &&
7619             hw->mac.type != ixgbe_mac_X550EM_a) {
7620                 return -ENOTSUP;
7621         }
7622
7623         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7624         if (en)
7625                 qde |= IXGBE_QDE_STRIP_TAG;
7626         else
7627                 qde &= ~IXGBE_QDE_STRIP_TAG;
7628         qde &= ~IXGBE_QDE_READ;
7629         qde |= IXGBE_QDE_WRITE;
7630         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7631
7632         return ret;
7633 }
7634
7635 /* Enable l2 tunnel tag stripping */
7636 static int
7637 ixgbe_dev_l2_tunnel_stripping_enable
7638         (struct rte_eth_dev *dev,
7639          enum rte_eth_tunnel_type l2_tunnel_type)
7640 {
7641         int ret = 0;
7642
7643         switch (l2_tunnel_type) {
7644         case RTE_L2_TUNNEL_TYPE_E_TAG:
7645                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7646                 break;
7647         default:
7648                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7649                 ret = -EINVAL;
7650                 break;
7651         }
7652
7653         return ret;
7654 }
7655
7656 /* Disable l2 tunnel tag stripping */
7657 static int
7658 ixgbe_dev_l2_tunnel_stripping_disable
7659         (struct rte_eth_dev *dev,
7660          enum rte_eth_tunnel_type l2_tunnel_type)
7661 {
7662         int ret = 0;
7663
7664         switch (l2_tunnel_type) {
7665         case RTE_L2_TUNNEL_TYPE_E_TAG:
7666                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7667                 break;
7668         default:
7669                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7670                 ret = -EINVAL;
7671                 break;
7672         }
7673
7674         return ret;
7675 }
7676
7677 /* Enable/disable l2 tunnel offload functions */
7678 static int
7679 ixgbe_dev_l2_tunnel_offload_set
7680         (struct rte_eth_dev *dev,
7681          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7682          uint32_t mask,
7683          uint8_t en)
7684 {
7685         int ret = 0;
7686
7687         if (l2_tunnel == NULL)
7688                 return -EINVAL;
7689
7690         ret = -EINVAL;
7691         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7692                 if (en)
7693                         ret = ixgbe_dev_l2_tunnel_enable(
7694                                 dev,
7695                                 l2_tunnel->l2_tunnel_type);
7696                 else
7697                         ret = ixgbe_dev_l2_tunnel_disable(
7698                                 dev,
7699                                 l2_tunnel->l2_tunnel_type);
7700         }
7701
7702         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7703                 if (en)
7704                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7705                                 dev,
7706                                 l2_tunnel);
7707                 else
7708                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7709                                 dev,
7710                                 l2_tunnel);
7711         }
7712
7713         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7714                 if (en)
7715                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7716                                 dev,
7717                                 l2_tunnel->l2_tunnel_type);
7718                 else
7719                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7720                                 dev,
7721                                 l2_tunnel->l2_tunnel_type);
7722         }
7723
7724         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7725                 if (en)
7726                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7727                                 dev,
7728                                 l2_tunnel->l2_tunnel_type);
7729                 else
7730                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7731                                 dev,
7732                                 l2_tunnel->l2_tunnel_type);
7733         }
7734
7735         return ret;
7736 }
7737
7738 static int
7739 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7740                         uint16_t port)
7741 {
7742         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7743         IXGBE_WRITE_FLUSH(hw);
7744
7745         return 0;
7746 }
7747
7748 /* There's only one register for VxLAN UDP port.
7749  * So, we cannot add several ports. Will update it.
7750  */
7751 static int
7752 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7753                      uint16_t port)
7754 {
7755         if (port == 0) {
7756                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7757                 return -EINVAL;
7758         }
7759
7760         return ixgbe_update_vxlan_port(hw, port);
7761 }
7762
7763 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7764  * UDP port, it must have a value.
7765  * So, will reset it to the original value 0.
7766  */
7767 static int
7768 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7769                      uint16_t port)
7770 {
7771         uint16_t cur_port;
7772
7773         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7774
7775         if (cur_port != port) {
7776                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7777                 return -EINVAL;
7778         }
7779
7780         return ixgbe_update_vxlan_port(hw, 0);
7781 }
7782
7783 /* Add UDP tunneling port */
7784 static int
7785 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7786                               struct rte_eth_udp_tunnel *udp_tunnel)
7787 {
7788         int ret = 0;
7789         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7790
7791         if (hw->mac.type != ixgbe_mac_X550 &&
7792             hw->mac.type != ixgbe_mac_X550EM_x &&
7793             hw->mac.type != ixgbe_mac_X550EM_a) {
7794                 return -ENOTSUP;
7795         }
7796
7797         if (udp_tunnel == NULL)
7798                 return -EINVAL;
7799
7800         switch (udp_tunnel->prot_type) {
7801         case RTE_TUNNEL_TYPE_VXLAN:
7802                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7803                 break;
7804
7805         case RTE_TUNNEL_TYPE_GENEVE:
7806         case RTE_TUNNEL_TYPE_TEREDO:
7807                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7808                 ret = -EINVAL;
7809                 break;
7810
7811         default:
7812                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7813                 ret = -EINVAL;
7814                 break;
7815         }
7816
7817         return ret;
7818 }
7819
7820 /* Remove UDP tunneling port */
7821 static int
7822 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7823                               struct rte_eth_udp_tunnel *udp_tunnel)
7824 {
7825         int ret = 0;
7826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7827
7828         if (hw->mac.type != ixgbe_mac_X550 &&
7829             hw->mac.type != ixgbe_mac_X550EM_x &&
7830             hw->mac.type != ixgbe_mac_X550EM_a) {
7831                 return -ENOTSUP;
7832         }
7833
7834         if (udp_tunnel == NULL)
7835                 return -EINVAL;
7836
7837         switch (udp_tunnel->prot_type) {
7838         case RTE_TUNNEL_TYPE_VXLAN:
7839                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7840                 break;
7841         case RTE_TUNNEL_TYPE_GENEVE:
7842         case RTE_TUNNEL_TYPE_TEREDO:
7843                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7844                 ret = -EINVAL;
7845                 break;
7846         default:
7847                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7848                 ret = -EINVAL;
7849                 break;
7850         }
7851
7852         return ret;
7853 }
7854
7855 static void
7856 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7857 {
7858         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7859
7860         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7861 }
7862
7863 static void
7864 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7865 {
7866         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7867
7868         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
7869 }
7870
7871 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7872 {
7873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7874         u32 in_msg = 0;
7875
7876         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7877                 return;
7878
7879         /* PF reset VF event */
7880         if (in_msg == IXGBE_PF_CONTROL_MSG)
7881                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7882 }
7883
7884 static int
7885 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7886 {
7887         uint32_t eicr;
7888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7889         struct ixgbe_interrupt *intr =
7890                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7891         ixgbevf_intr_disable(hw);
7892
7893         /* read-on-clear nic registers here */
7894         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7895         intr->flags = 0;
7896
7897         /* only one misc vector supported - mailbox */
7898         eicr &= IXGBE_VTEICR_MASK;
7899         if (eicr == IXGBE_MISC_VEC_ID)
7900                 intr->flags |= IXGBE_FLAG_MAILBOX;
7901
7902         return 0;
7903 }
7904
7905 static int
7906 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7907 {
7908         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7909         struct ixgbe_interrupt *intr =
7910                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7911
7912         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7913                 ixgbevf_mbx_process(dev);
7914                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7915         }
7916
7917         ixgbevf_intr_enable(hw);
7918
7919         return 0;
7920 }
7921
7922 static void
7923 ixgbevf_dev_interrupt_handler(void *param)
7924 {
7925         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7926
7927         ixgbevf_dev_interrupt_get_status(dev);
7928         ixgbevf_dev_interrupt_action(dev);
7929 }
7930
7931 /**
7932  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7933  *  @hw: pointer to hardware structure
7934  *
7935  *  Stops the transmit data path and waits for the HW to internally empty
7936  *  the Tx security block
7937  **/
7938 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7939 {
7940 #define IXGBE_MAX_SECTX_POLL 40
7941
7942         int i;
7943         int sectxreg;
7944
7945         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7946         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7947         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7948         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7949                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7950                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7951                         break;
7952                 /* Use interrupt-safe sleep just in case */
7953                 usec_delay(1000);
7954         }
7955
7956         /* For informational purposes only */
7957         if (i >= IXGBE_MAX_SECTX_POLL)
7958                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7959                          "path fully disabled.  Continuing with init.");
7960
7961         return IXGBE_SUCCESS;
7962 }
7963
7964 /**
7965  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7966  *  @hw: pointer to hardware structure
7967  *
7968  *  Enables the transmit data path.
7969  **/
7970 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7971 {
7972         uint32_t sectxreg;
7973
7974         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7975         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7976         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7977         IXGBE_WRITE_FLUSH(hw);
7978
7979         return IXGBE_SUCCESS;
7980 }
7981
7982 /* restore n-tuple filter */
7983 static inline void
7984 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
7985 {
7986         struct ixgbe_filter_info *filter_info =
7987                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7988         struct ixgbe_5tuple_filter *node;
7989
7990         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
7991                 ixgbe_inject_5tuple_filter(dev, node);
7992         }
7993 }
7994
7995 /* restore ethernet type filter */
7996 static inline void
7997 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
7998 {
7999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8000         struct ixgbe_filter_info *filter_info =
8001                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8002         int i;
8003
8004         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8005                 if (filter_info->ethertype_mask & (1 << i)) {
8006                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8007                                         filter_info->ethertype_filters[i].etqf);
8008                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8009                                         filter_info->ethertype_filters[i].etqs);
8010                         IXGBE_WRITE_FLUSH(hw);
8011                 }
8012         }
8013 }
8014
8015 /* restore SYN filter */
8016 static inline void
8017 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8018 {
8019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8020         struct ixgbe_filter_info *filter_info =
8021                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8022         uint32_t synqf;
8023
8024         synqf = filter_info->syn_info;
8025
8026         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8027                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8028                 IXGBE_WRITE_FLUSH(hw);
8029         }
8030 }
8031
8032 /* restore L2 tunnel filter */
8033 static inline void
8034 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8035 {
8036         struct ixgbe_l2_tn_info *l2_tn_info =
8037                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8038         struct ixgbe_l2_tn_filter *node;
8039         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8040
8041         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8042                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8043                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8044                 l2_tn_conf.pool           = node->pool;
8045                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8046         }
8047 }
8048
8049 static int
8050 ixgbe_filter_restore(struct rte_eth_dev *dev)
8051 {
8052         ixgbe_ntuple_filter_restore(dev);
8053         ixgbe_ethertype_filter_restore(dev);
8054         ixgbe_syn_filter_restore(dev);
8055         ixgbe_fdir_filter_restore(dev);
8056         ixgbe_l2_tn_filter_restore(dev);
8057
8058         return 0;
8059 }
8060
8061 static void
8062 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8063 {
8064         struct ixgbe_l2_tn_info *l2_tn_info =
8065                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8066         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8067
8068         if (l2_tn_info->e_tag_en)
8069                 (void)ixgbe_e_tag_enable(hw);
8070
8071         if (l2_tn_info->e_tag_fwd_en)
8072                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8073
8074         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8075 }
8076
8077 /* remove all the n-tuple filters */
8078 void
8079 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8080 {
8081         struct ixgbe_filter_info *filter_info =
8082                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8083         struct ixgbe_5tuple_filter *p_5tuple;
8084
8085         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8086                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8087 }
8088
8089 /* remove all the ether type filters */
8090 void
8091 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8092 {
8093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8094         struct ixgbe_filter_info *filter_info =
8095                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8096         int i;
8097
8098         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8099                 if (filter_info->ethertype_mask & (1 << i) &&
8100                     !filter_info->ethertype_filters[i].conf) {
8101                         (void)ixgbe_ethertype_filter_remove(filter_info,
8102                                                             (uint8_t)i);
8103                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8104                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8105                         IXGBE_WRITE_FLUSH(hw);
8106                 }
8107         }
8108 }
8109
8110 /* remove the SYN filter */
8111 void
8112 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8113 {
8114         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8115         struct ixgbe_filter_info *filter_info =
8116                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8117
8118         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8119                 filter_info->syn_info = 0;
8120
8121                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8122                 IXGBE_WRITE_FLUSH(hw);
8123         }
8124 }
8125
8126 /* remove all the L2 tunnel filters */
8127 int
8128 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8129 {
8130         struct ixgbe_l2_tn_info *l2_tn_info =
8131                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8132         struct ixgbe_l2_tn_filter *l2_tn_filter;
8133         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8134         int ret = 0;
8135
8136         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8137                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8138                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8139                 l2_tn_conf.pool           = l2_tn_filter->pool;
8140                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8141                 if (ret < 0)
8142                         return ret;
8143         }
8144
8145         return 0;
8146 }
8147
8148 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8149 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8150 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8151 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8152 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8153 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");