4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_hash_crc.h>
66 #include "ixgbe_logs.h"
67 #include "base/ixgbe_api.h"
68 #include "base/ixgbe_vf.h"
69 #include "base/ixgbe_common.h"
70 #include "ixgbe_ethdev.h"
71 #include "ixgbe_bypass.h"
72 #include "ixgbe_rxtx.h"
73 #include "base/ixgbe_type.h"
74 #include "base/ixgbe_phy.h"
75 #include "ixgbe_regs.h"
77 #include "rte_pmd_ixgbe.h"
80 * High threshold controlling when to start sending XOFF frames. Must be at
81 * least 8 bytes less than receive packet buffer size. This value is in units
84 #define IXGBE_FC_HI 0x80
87 * Low threshold controlling when to start sending XON frames. This value is
88 * in units of 1024 bytes.
90 #define IXGBE_FC_LO 0x40
92 /* Default minimum inter-interrupt interval for EITR configuration */
93 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
95 /* Timer value included in XOFF frames. */
96 #define IXGBE_FC_PAUSE 0x680
98 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
99 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
100 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
102 #define IXGBE_MMW_SIZE_DEFAULT 0x4
103 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
104 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
107 * Default values for RX/TX configuration
109 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
110 #define IXGBE_DEFAULT_RX_PTHRESH 8
111 #define IXGBE_DEFAULT_RX_HTHRESH 8
112 #define IXGBE_DEFAULT_RX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
115 #define IXGBE_DEFAULT_TX_PTHRESH 32
116 #define IXGBE_DEFAULT_TX_HTHRESH 0
117 #define IXGBE_DEFAULT_TX_WTHRESH 0
118 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
120 /* Bit shift and mask */
121 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
122 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
123 #define IXGBE_8_BIT_WIDTH CHAR_BIT
124 #define IXGBE_8_BIT_MASK UINT8_MAX
126 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
128 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
130 #define IXGBE_HKEY_MAX_INDEX 10
132 /* Additional timesync values. */
133 #define NSEC_PER_SEC 1000000000L
134 #define IXGBE_INCVAL_10GB 0x66666666
135 #define IXGBE_INCVAL_1GB 0x40000000
136 #define IXGBE_INCVAL_100 0x50000000
137 #define IXGBE_INCVAL_SHIFT_10GB 28
138 #define IXGBE_INCVAL_SHIFT_1GB 24
139 #define IXGBE_INCVAL_SHIFT_100 21
140 #define IXGBE_INCVAL_SHIFT_82599 7
141 #define IXGBE_INCPER_SHIFT_82599 24
143 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
145 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
146 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
147 #define DEFAULT_ETAG_ETYPE 0x893f
148 #define IXGBE_ETAG_ETYPE 0x00005084
149 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
150 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
151 #define IXGBE_RAH_ADTYPE 0x40000000
152 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
153 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
154 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
155 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
156 #define IXGBE_QDE_STRIP_TAG 0x00000004
157 #define IXGBE_VTEICR_MASK 0x07
159 #define IXGBE_EXVET_VET_EXT_SHIFT 16
160 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
162 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
163 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
164 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
165 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
167 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
168 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
169 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
170 static int ixgbe_dev_start(struct rte_eth_dev *dev);
171 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
172 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
173 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
174 static void ixgbe_dev_close(struct rte_eth_dev *dev);
175 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
177 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
178 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
179 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
180 int wait_to_complete);
181 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
182 struct rte_eth_stats *stats);
183 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
184 struct rte_eth_xstat *xstats, unsigned n);
185 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
186 struct rte_eth_xstat *xstats, unsigned n);
187 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
188 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
189 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
190 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
191 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
192 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
193 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
197 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
199 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
200 struct rte_eth_dev_info *dev_info);
201 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
202 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
203 struct rte_eth_dev_info *dev_info);
204 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
206 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
207 uint16_t vlan_id, int on);
208 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
209 enum rte_vlan_type vlan_type,
211 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
212 uint16_t queue, bool on);
213 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
215 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
216 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
217 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
218 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
219 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
221 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
222 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
223 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
224 struct rte_eth_fc_conf *fc_conf);
225 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
226 struct rte_eth_fc_conf *fc_conf);
227 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
228 struct rte_eth_pfc_conf *pfc_conf);
229 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
230 struct rte_eth_rss_reta_entry64 *reta_conf,
232 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
233 struct rte_eth_rss_reta_entry64 *reta_conf,
235 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
236 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
237 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
238 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
239 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
240 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
241 struct rte_intr_handle *handle);
242 static void ixgbe_dev_interrupt_handler(void *param);
243 static void ixgbe_dev_interrupt_delayed_handler(void *param);
244 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
245 uint32_t index, uint32_t pool);
246 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
247 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
248 struct ether_addr *mac_addr);
249 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
250 static bool is_device_supported(struct rte_eth_dev *dev,
251 struct rte_pci_driver *drv);
253 /* For Virtual Function support */
254 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
255 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
256 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
257 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
258 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
259 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
260 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
261 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
262 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
263 struct rte_eth_stats *stats);
264 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
265 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
266 uint16_t vlan_id, int on);
267 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
268 uint16_t queue, int on);
269 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
270 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
271 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
273 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
275 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
276 uint8_t queue, uint8_t msix_vector);
277 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
278 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
279 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
281 /* For Eth VMDQ APIs support */
282 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
283 ether_addr * mac_addr, uint8_t on);
284 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
285 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
286 struct rte_eth_mirror_conf *mirror_conf,
287 uint8_t rule_id, uint8_t on);
288 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
290 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
292 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
294 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
295 uint8_t queue, uint8_t msix_vector);
296 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
298 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
299 uint16_t queue_idx, uint16_t tx_rate);
301 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
302 struct ether_addr *mac_addr,
303 uint32_t index, uint32_t pool);
304 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
305 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
306 struct ether_addr *mac_addr);
307 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
308 struct rte_eth_syn_filter *filter);
309 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
310 enum rte_filter_op filter_op,
312 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
313 struct ixgbe_5tuple_filter *filter);
314 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
315 struct ixgbe_5tuple_filter *filter);
316 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
317 enum rte_filter_op filter_op,
319 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
320 struct rte_eth_ntuple_filter *filter);
321 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
322 enum rte_filter_op filter_op,
324 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
325 struct rte_eth_ethertype_filter *filter);
326 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
327 enum rte_filter_type filter_type,
328 enum rte_filter_op filter_op,
330 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
332 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
333 struct ether_addr *mc_addr_set,
334 uint32_t nb_mc_addr);
335 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
336 struct rte_eth_dcb_info *dcb_info);
338 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
339 static int ixgbe_get_regs(struct rte_eth_dev *dev,
340 struct rte_dev_reg_info *regs);
341 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
342 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
343 struct rte_dev_eeprom_info *eeprom);
344 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
345 struct rte_dev_eeprom_info *eeprom);
347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
349 struct rte_dev_reg_info *regs);
351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
354 struct timespec *timestamp,
356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
357 struct timespec *timestamp);
358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
360 struct timespec *timestamp);
361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
362 const struct timespec *timestamp);
363 static void ixgbevf_dev_interrupt_handler(void *param);
365 static int ixgbe_dev_l2_tunnel_eth_type_conf
366 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
367 static int ixgbe_dev_l2_tunnel_offload_set
368 (struct rte_eth_dev *dev,
369 struct rte_eth_l2_tunnel_conf *l2_tunnel,
372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
373 enum rte_filter_op filter_op,
376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
377 struct rte_eth_udp_tunnel *udp_tunnel);
378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
379 struct rte_eth_udp_tunnel *udp_tunnel);
380 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
381 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
384 * Define VF Stats MACRO for Non "cleared on read" register
386 #define UPDATE_VF_STAT(reg, last, cur) \
388 uint32_t latest = IXGBE_READ_REG(hw, reg); \
389 cur += (latest - last) & UINT_MAX; \
393 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
395 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
396 u64 new_msb = IXGBE_READ_REG(hw, msb); \
397 u64 latest = ((new_msb << 32) | new_lsb); \
398 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
402 #define IXGBE_SET_HWSTRIP(h, q) do {\
403 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
404 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
405 (h)->bitmap[idx] |= 1 << bit;\
408 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
409 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
410 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
411 (h)->bitmap[idx] &= ~(1 << bit);\
414 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
415 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
416 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
417 (r) = (h)->bitmap[idx] >> bit & 1;\
421 * The set of PCI devices this driver supports
423 static const struct rte_pci_id pci_id_ixgbe_map[] = {
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
477 #ifdef RTE_NIC_BYPASS
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
480 { .vendor_id = 0, /* sentinel */ },
484 * The set of PCI devices this driver supports (for 82599 VF)
486 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
497 { .vendor_id = 0, /* sentinel */ },
500 static const struct rte_eth_desc_lim rx_desc_lim = {
501 .nb_max = IXGBE_MAX_RING_DESC,
502 .nb_min = IXGBE_MIN_RING_DESC,
503 .nb_align = IXGBE_RXD_ALIGN,
506 static const struct rte_eth_desc_lim tx_desc_lim = {
507 .nb_max = IXGBE_MAX_RING_DESC,
508 .nb_min = IXGBE_MIN_RING_DESC,
509 .nb_align = IXGBE_TXD_ALIGN,
510 .nb_seg_max = IXGBE_TX_MAX_SEG,
511 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
514 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
515 .dev_configure = ixgbe_dev_configure,
516 .dev_start = ixgbe_dev_start,
517 .dev_stop = ixgbe_dev_stop,
518 .dev_set_link_up = ixgbe_dev_set_link_up,
519 .dev_set_link_down = ixgbe_dev_set_link_down,
520 .dev_close = ixgbe_dev_close,
521 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
522 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
523 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
524 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
525 .link_update = ixgbe_dev_link_update,
526 .stats_get = ixgbe_dev_stats_get,
527 .xstats_get = ixgbe_dev_xstats_get,
528 .stats_reset = ixgbe_dev_stats_reset,
529 .xstats_reset = ixgbe_dev_xstats_reset,
530 .xstats_get_names = ixgbe_dev_xstats_get_names,
531 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
532 .fw_version_get = ixgbe_fw_version_get,
533 .dev_infos_get = ixgbe_dev_info_get,
534 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
535 .mtu_set = ixgbe_dev_mtu_set,
536 .vlan_filter_set = ixgbe_vlan_filter_set,
537 .vlan_tpid_set = ixgbe_vlan_tpid_set,
538 .vlan_offload_set = ixgbe_vlan_offload_set,
539 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
540 .rx_queue_start = ixgbe_dev_rx_queue_start,
541 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
542 .tx_queue_start = ixgbe_dev_tx_queue_start,
543 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
544 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
545 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
546 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
547 .rx_queue_release = ixgbe_dev_rx_queue_release,
548 .rx_queue_count = ixgbe_dev_rx_queue_count,
549 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
550 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
551 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
552 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
553 .tx_queue_release = ixgbe_dev_tx_queue_release,
554 .dev_led_on = ixgbe_dev_led_on,
555 .dev_led_off = ixgbe_dev_led_off,
556 .flow_ctrl_get = ixgbe_flow_ctrl_get,
557 .flow_ctrl_set = ixgbe_flow_ctrl_set,
558 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
559 .mac_addr_add = ixgbe_add_rar,
560 .mac_addr_remove = ixgbe_remove_rar,
561 .mac_addr_set = ixgbe_set_default_mac_addr,
562 .uc_hash_table_set = ixgbe_uc_hash_table_set,
563 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
564 .mirror_rule_set = ixgbe_mirror_rule_set,
565 .mirror_rule_reset = ixgbe_mirror_rule_reset,
566 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
567 .reta_update = ixgbe_dev_rss_reta_update,
568 .reta_query = ixgbe_dev_rss_reta_query,
569 #ifdef RTE_NIC_BYPASS
570 .bypass_init = ixgbe_bypass_init,
571 .bypass_state_set = ixgbe_bypass_state_store,
572 .bypass_state_show = ixgbe_bypass_state_show,
573 .bypass_event_set = ixgbe_bypass_event_store,
574 .bypass_event_show = ixgbe_bypass_event_show,
575 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
576 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
577 .bypass_ver_show = ixgbe_bypass_ver_show,
578 .bypass_wd_reset = ixgbe_bypass_wd_reset,
579 #endif /* RTE_NIC_BYPASS */
580 .rss_hash_update = ixgbe_dev_rss_hash_update,
581 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
582 .filter_ctrl = ixgbe_dev_filter_ctrl,
583 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
584 .rxq_info_get = ixgbe_rxq_info_get,
585 .txq_info_get = ixgbe_txq_info_get,
586 .timesync_enable = ixgbe_timesync_enable,
587 .timesync_disable = ixgbe_timesync_disable,
588 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
589 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
590 .get_reg = ixgbe_get_regs,
591 .get_eeprom_length = ixgbe_get_eeprom_length,
592 .get_eeprom = ixgbe_get_eeprom,
593 .set_eeprom = ixgbe_set_eeprom,
594 .get_dcb_info = ixgbe_dev_get_dcb_info,
595 .timesync_adjust_time = ixgbe_timesync_adjust_time,
596 .timesync_read_time = ixgbe_timesync_read_time,
597 .timesync_write_time = ixgbe_timesync_write_time,
598 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
599 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
600 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
601 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
605 * dev_ops for virtual function, bare necessities for basic vf
606 * operation have been implemented
608 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
609 .dev_configure = ixgbevf_dev_configure,
610 .dev_start = ixgbevf_dev_start,
611 .dev_stop = ixgbevf_dev_stop,
612 .link_update = ixgbe_dev_link_update,
613 .stats_get = ixgbevf_dev_stats_get,
614 .xstats_get = ixgbevf_dev_xstats_get,
615 .stats_reset = ixgbevf_dev_stats_reset,
616 .xstats_reset = ixgbevf_dev_stats_reset,
617 .xstats_get_names = ixgbevf_dev_xstats_get_names,
618 .dev_close = ixgbevf_dev_close,
619 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
620 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
621 .dev_infos_get = ixgbevf_dev_info_get,
622 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
623 .mtu_set = ixgbevf_dev_set_mtu,
624 .vlan_filter_set = ixgbevf_vlan_filter_set,
625 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
626 .vlan_offload_set = ixgbevf_vlan_offload_set,
627 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
628 .rx_queue_release = ixgbe_dev_rx_queue_release,
629 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
630 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
631 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
632 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
633 .tx_queue_release = ixgbe_dev_tx_queue_release,
634 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
635 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
636 .mac_addr_add = ixgbevf_add_mac_addr,
637 .mac_addr_remove = ixgbevf_remove_mac_addr,
638 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
639 .rxq_info_get = ixgbe_rxq_info_get,
640 .txq_info_get = ixgbe_txq_info_get,
641 .mac_addr_set = ixgbevf_set_default_mac_addr,
642 .get_reg = ixgbevf_get_regs,
643 .reta_update = ixgbe_dev_rss_reta_update,
644 .reta_query = ixgbe_dev_rss_reta_query,
645 .rss_hash_update = ixgbe_dev_rss_hash_update,
646 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
649 /* store statistics names and its offset in stats structure */
650 struct rte_ixgbe_xstats_name_off {
651 char name[RTE_ETH_XSTATS_NAME_SIZE];
655 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
656 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
657 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
658 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
659 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
660 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
661 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
662 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
663 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
664 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
665 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
666 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
667 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
668 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
669 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
670 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
672 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
674 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
675 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
676 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
677 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
678 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
679 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
680 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
681 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
682 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
683 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
684 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
685 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
686 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
687 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
688 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
689 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
690 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
692 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
694 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
695 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
696 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
697 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
699 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
701 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
703 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
705 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
707 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
709 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
712 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
713 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
714 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
716 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
717 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
718 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
719 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
720 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
722 {"rx_fcoe_no_direct_data_placement_ext_buff",
723 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
725 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
727 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
729 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
731 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
733 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
736 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
737 sizeof(rte_ixgbe_stats_strings[0]))
739 /* MACsec statistics */
740 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
741 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
743 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
744 out_pkts_encrypted)},
745 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
746 out_pkts_protected)},
747 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
748 out_octets_encrypted)},
749 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
750 out_octets_protected)},
751 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
753 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
755 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
757 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
758 in_pkts_unknownsci)},
759 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
760 in_octets_decrypted)},
761 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
762 in_octets_validated)},
763 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
765 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
769 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
771 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
773 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
775 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
777 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
778 in_pkts_notusingsa)},
781 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
782 sizeof(rte_ixgbe_macsec_strings[0]))
784 /* Per-queue statistics */
785 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
786 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
787 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
788 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
789 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
792 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
793 sizeof(rte_ixgbe_rxq_strings[0]))
794 #define IXGBE_NB_RXQ_PRIO_VALUES 8
796 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
797 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
798 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
799 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
803 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
804 sizeof(rte_ixgbe_txq_strings[0]))
805 #define IXGBE_NB_TXQ_PRIO_VALUES 8
807 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
808 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
811 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
812 sizeof(rte_ixgbevf_stats_strings[0]))
815 * Atomically reads the link status information from global
816 * structure rte_eth_dev.
819 * - Pointer to the structure rte_eth_dev to read from.
820 * - Pointer to the buffer to be saved with the link status.
823 * - On success, zero.
824 * - On failure, negative value.
827 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
828 struct rte_eth_link *link)
830 struct rte_eth_link *dst = link;
831 struct rte_eth_link *src = &(dev->data->dev_link);
833 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
834 *(uint64_t *)src) == 0)
841 * Atomically writes the link status information into global
842 * structure rte_eth_dev.
845 * - Pointer to the structure rte_eth_dev to read from.
846 * - Pointer to the buffer to be saved with the link status.
849 * - On success, zero.
850 * - On failure, negative value.
853 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
854 struct rte_eth_link *link)
856 struct rte_eth_link *dst = &(dev->data->dev_link);
857 struct rte_eth_link *src = link;
859 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
860 *(uint64_t *)src) == 0)
867 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
870 ixgbe_is_sfp(struct ixgbe_hw *hw)
872 switch (hw->phy.type) {
873 case ixgbe_phy_sfp_avago:
874 case ixgbe_phy_sfp_ftl:
875 case ixgbe_phy_sfp_intel:
876 case ixgbe_phy_sfp_unknown:
877 case ixgbe_phy_sfp_passive_tyco:
878 case ixgbe_phy_sfp_passive_unknown:
885 static inline int32_t
886 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
891 status = ixgbe_reset_hw(hw);
893 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
894 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
895 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
896 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
897 IXGBE_WRITE_FLUSH(hw);
899 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
900 status = IXGBE_SUCCESS;
905 ixgbe_enable_intr(struct rte_eth_dev *dev)
907 struct ixgbe_interrupt *intr =
908 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
909 struct ixgbe_hw *hw =
910 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
912 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
913 IXGBE_WRITE_FLUSH(hw);
917 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
920 ixgbe_disable_intr(struct ixgbe_hw *hw)
922 PMD_INIT_FUNC_TRACE();
924 if (hw->mac.type == ixgbe_mac_82598EB) {
925 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
927 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
928 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
929 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
931 IXGBE_WRITE_FLUSH(hw);
935 * This function resets queue statistics mapping registers.
936 * From Niantic datasheet, Initialization of Statistics section:
937 * "...if software requires the queue counters, the RQSMR and TQSM registers
938 * must be re-programmed following a device reset.
941 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
945 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
946 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
947 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
953 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
958 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
959 #define NB_QMAP_FIELDS_PER_QSM_REG 4
960 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
962 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
963 struct ixgbe_stat_mapping_registers *stat_mappings =
964 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
965 uint32_t qsmr_mask = 0;
966 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
970 if ((hw->mac.type != ixgbe_mac_82599EB) &&
971 (hw->mac.type != ixgbe_mac_X540) &&
972 (hw->mac.type != ixgbe_mac_X550) &&
973 (hw->mac.type != ixgbe_mac_X550EM_x) &&
974 (hw->mac.type != ixgbe_mac_X550EM_a))
977 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
978 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
981 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
982 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
983 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
986 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
988 /* Now clear any previous stat_idx set */
989 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
991 stat_mappings->tqsm[n] &= ~clearing_mask;
993 stat_mappings->rqsmr[n] &= ~clearing_mask;
995 q_map = (uint32_t)stat_idx;
996 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
997 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
999 stat_mappings->tqsm[n] |= qsmr_mask;
1001 stat_mappings->rqsmr[n] |= qsmr_mask;
1003 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1004 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1005 queue_id, stat_idx);
1006 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1007 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1009 /* Now write the mapping in the appropriate register */
1011 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1012 stat_mappings->rqsmr[n], n);
1013 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1015 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1016 stat_mappings->tqsm[n], n);
1017 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1023 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1025 struct ixgbe_stat_mapping_registers *stat_mappings =
1026 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1027 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030 /* write whatever was in stat mapping table to the NIC */
1031 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1033 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1036 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1041 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1044 struct ixgbe_dcb_tc_config *tc;
1045 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1047 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1048 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1049 for (i = 0; i < dcb_max_tc; i++) {
1050 tc = &dcb_config->tc_config[i];
1051 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1052 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1053 (uint8_t)(100/dcb_max_tc + (i & 1));
1054 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1055 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1056 (uint8_t)(100/dcb_max_tc + (i & 1));
1057 tc->pfc = ixgbe_dcb_pfc_disabled;
1060 /* Initialize default user to priority mapping, UPx->TC0 */
1061 tc = &dcb_config->tc_config[0];
1062 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1063 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1064 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1065 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1066 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1068 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1069 dcb_config->pfc_mode_enable = false;
1070 dcb_config->vt_mode = true;
1071 dcb_config->round_robin_enable = false;
1072 /* support all DCB capabilities in 82599 */
1073 dcb_config->support.capabilities = 0xFF;
1075 /*we only support 4 Tcs for X540, X550 */
1076 if (hw->mac.type == ixgbe_mac_X540 ||
1077 hw->mac.type == ixgbe_mac_X550 ||
1078 hw->mac.type == ixgbe_mac_X550EM_x ||
1079 hw->mac.type == ixgbe_mac_X550EM_a) {
1080 dcb_config->num_tcs.pg_tcs = 4;
1081 dcb_config->num_tcs.pfc_tcs = 4;
1086 * Ensure that all locks are released before first NVM or PHY access
1089 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1094 * Phy lock should not fail in this early stage. If this is the case,
1095 * it is due to an improper exit of the application.
1096 * So force the release of the faulty lock. Release of common lock
1097 * is done automatically by swfw_sync function.
1099 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1100 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1101 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1103 ixgbe_release_swfw_semaphore(hw, mask);
1106 * These ones are more tricky since they are common to all ports; but
1107 * swfw_sync retries last long enough (1s) to be almost sure that if
1108 * lock can not be taken it is due to an improper lock of the
1111 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1112 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1113 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1115 ixgbe_release_swfw_semaphore(hw, mask);
1119 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1120 * It returns 0 on success.
1123 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1125 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1126 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1127 struct ixgbe_hw *hw =
1128 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1129 struct ixgbe_vfta *shadow_vfta =
1130 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1131 struct ixgbe_hwstrip *hwstrip =
1132 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1133 struct ixgbe_dcb_config *dcb_config =
1134 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1135 struct ixgbe_filter_info *filter_info =
1136 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1137 struct ixgbe_bw_conf *bw_conf =
1138 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1143 PMD_INIT_FUNC_TRACE();
1145 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1146 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1147 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1148 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1151 * For secondary processes, we don't initialise any further as primary
1152 * has already done this work. Only check we don't need a different
1153 * RX and TX function.
1155 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1156 struct ixgbe_tx_queue *txq;
1157 /* TX queue function in primary, set by last queue initialized
1158 * Tx queue may not initialized by primary process
1160 if (eth_dev->data->tx_queues) {
1161 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1162 ixgbe_set_tx_function(eth_dev, txq);
1164 /* Use default TX function if we get here */
1165 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1166 "Using default TX function.");
1169 ixgbe_set_rx_function(eth_dev);
1174 rte_eth_copy_pci_info(eth_dev, pci_dev);
1175 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1177 /* Vendor and Device ID need to be set before init of shared code */
1178 hw->device_id = pci_dev->id.device_id;
1179 hw->vendor_id = pci_dev->id.vendor_id;
1180 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1181 hw->allow_unsupported_sfp = 1;
1183 /* Initialize the shared code (base driver) */
1184 #ifdef RTE_NIC_BYPASS
1185 diag = ixgbe_bypass_init_shared_code(hw);
1187 diag = ixgbe_init_shared_code(hw);
1188 #endif /* RTE_NIC_BYPASS */
1190 if (diag != IXGBE_SUCCESS) {
1191 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1195 /* pick up the PCI bus settings for reporting later */
1196 ixgbe_get_bus_info(hw);
1198 /* Unlock any pending hardware semaphore */
1199 ixgbe_swfw_lock_reset(hw);
1201 /* Initialize DCB configuration*/
1202 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1203 ixgbe_dcb_init(hw, dcb_config);
1204 /* Get Hardware Flow Control setting */
1205 hw->fc.requested_mode = ixgbe_fc_full;
1206 hw->fc.current_mode = ixgbe_fc_full;
1207 hw->fc.pause_time = IXGBE_FC_PAUSE;
1208 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1209 hw->fc.low_water[i] = IXGBE_FC_LO;
1210 hw->fc.high_water[i] = IXGBE_FC_HI;
1212 hw->fc.send_xon = 1;
1214 /* Make sure we have a good EEPROM before we read from it */
1215 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1216 if (diag != IXGBE_SUCCESS) {
1217 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1221 #ifdef RTE_NIC_BYPASS
1222 diag = ixgbe_bypass_init_hw(hw);
1224 diag = ixgbe_init_hw(hw);
1225 #endif /* RTE_NIC_BYPASS */
1228 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1229 * is called too soon after the kernel driver unbinding/binding occurs.
1230 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1231 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1232 * also called. See ixgbe_identify_phy_82599(). The reason for the
1233 * failure is not known, and only occuts when virtualisation features
1234 * are disabled in the bios. A delay of 100ms was found to be enough by
1235 * trial-and-error, and is doubled to be safe.
1237 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1239 diag = ixgbe_init_hw(hw);
1242 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1243 diag = IXGBE_SUCCESS;
1245 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1246 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1247 "LOM. Please be aware there may be issues associated "
1248 "with your hardware.");
1249 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1250 "please contact your Intel or hardware representative "
1251 "who provided you with this hardware.");
1252 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1253 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1255 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1259 /* Reset the hw statistics */
1260 ixgbe_dev_stats_reset(eth_dev);
1262 /* disable interrupt */
1263 ixgbe_disable_intr(hw);
1265 /* reset mappings for queue statistics hw counters*/
1266 ixgbe_reset_qstat_mappings(hw);
1268 /* Allocate memory for storing MAC addresses */
1269 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1270 hw->mac.num_rar_entries, 0);
1271 if (eth_dev->data->mac_addrs == NULL) {
1273 "Failed to allocate %u bytes needed to store "
1275 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1278 /* Copy the permanent MAC address */
1279 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1280 ð_dev->data->mac_addrs[0]);
1282 /* Allocate memory for storing hash filter MAC addresses */
1283 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1284 IXGBE_VMDQ_NUM_UC_MAC, 0);
1285 if (eth_dev->data->hash_mac_addrs == NULL) {
1287 "Failed to allocate %d bytes needed to store MAC addresses",
1288 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1292 /* initialize the vfta */
1293 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1295 /* initialize the hw strip bitmap*/
1296 memset(hwstrip, 0, sizeof(*hwstrip));
1298 /* initialize PF if max_vfs not zero */
1299 ixgbe_pf_host_init(eth_dev);
1301 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1302 /* let hardware know driver is loaded */
1303 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1304 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1305 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1306 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1307 IXGBE_WRITE_FLUSH(hw);
1309 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1310 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1311 (int) hw->mac.type, (int) hw->phy.type,
1312 (int) hw->phy.sfp_type);
1314 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1315 (int) hw->mac.type, (int) hw->phy.type);
1317 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1318 eth_dev->data->port_id, pci_dev->id.vendor_id,
1319 pci_dev->id.device_id);
1321 rte_intr_callback_register(intr_handle,
1322 ixgbe_dev_interrupt_handler, eth_dev);
1324 /* enable uio/vfio intr/eventfd mapping */
1325 rte_intr_enable(intr_handle);
1327 /* enable support intr */
1328 ixgbe_enable_intr(eth_dev);
1330 /* initialize filter info */
1331 memset(filter_info, 0,
1332 sizeof(struct ixgbe_filter_info));
1334 /* initialize 5tuple filter list */
1335 TAILQ_INIT(&filter_info->fivetuple_list);
1337 /* initialize flow director filter list & hash */
1338 ixgbe_fdir_filter_init(eth_dev);
1340 /* initialize l2 tunnel filter list & hash */
1341 ixgbe_l2_tn_filter_init(eth_dev);
1343 TAILQ_INIT(&filter_ntuple_list);
1344 TAILQ_INIT(&filter_ethertype_list);
1345 TAILQ_INIT(&filter_syn_list);
1346 TAILQ_INIT(&filter_fdir_list);
1347 TAILQ_INIT(&filter_l2_tunnel_list);
1348 TAILQ_INIT(&ixgbe_flow_list);
1350 /* initialize bandwidth configuration info */
1351 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1357 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1359 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1360 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1361 struct ixgbe_hw *hw;
1363 PMD_INIT_FUNC_TRACE();
1365 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1368 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1370 if (hw->adapter_stopped == 0)
1371 ixgbe_dev_close(eth_dev);
1373 eth_dev->dev_ops = NULL;
1374 eth_dev->rx_pkt_burst = NULL;
1375 eth_dev->tx_pkt_burst = NULL;
1377 /* Unlock any pending hardware semaphore */
1378 ixgbe_swfw_lock_reset(hw);
1380 /* disable uio intr before callback unregister */
1381 rte_intr_disable(intr_handle);
1382 rte_intr_callback_unregister(intr_handle,
1383 ixgbe_dev_interrupt_handler, eth_dev);
1385 /* uninitialize PF if max_vfs not zero */
1386 ixgbe_pf_host_uninit(eth_dev);
1388 rte_free(eth_dev->data->mac_addrs);
1389 eth_dev->data->mac_addrs = NULL;
1391 rte_free(eth_dev->data->hash_mac_addrs);
1392 eth_dev->data->hash_mac_addrs = NULL;
1394 /* remove all the fdir filters & hash */
1395 ixgbe_fdir_filter_uninit(eth_dev);
1397 /* remove all the L2 tunnel filters & hash */
1398 ixgbe_l2_tn_filter_uninit(eth_dev);
1400 /* Remove all ntuple filters of the device */
1401 ixgbe_ntuple_filter_uninit(eth_dev);
1403 /* clear all the filters list */
1404 ixgbe_filterlist_flush();
1409 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1411 struct ixgbe_filter_info *filter_info =
1412 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1413 struct ixgbe_5tuple_filter *p_5tuple;
1415 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1416 TAILQ_REMOVE(&filter_info->fivetuple_list,
1421 memset(filter_info->fivetuple_mask, 0,
1422 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1427 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1429 struct ixgbe_hw_fdir_info *fdir_info =
1430 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1431 struct ixgbe_fdir_filter *fdir_filter;
1433 if (fdir_info->hash_map)
1434 rte_free(fdir_info->hash_map);
1435 if (fdir_info->hash_handle)
1436 rte_hash_free(fdir_info->hash_handle);
1438 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1439 TAILQ_REMOVE(&fdir_info->fdir_list,
1442 rte_free(fdir_filter);
1448 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1450 struct ixgbe_l2_tn_info *l2_tn_info =
1451 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1452 struct ixgbe_l2_tn_filter *l2_tn_filter;
1454 if (l2_tn_info->hash_map)
1455 rte_free(l2_tn_info->hash_map);
1456 if (l2_tn_info->hash_handle)
1457 rte_hash_free(l2_tn_info->hash_handle);
1459 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1460 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1463 rte_free(l2_tn_filter);
1469 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1471 struct ixgbe_hw_fdir_info *fdir_info =
1472 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1473 char fdir_hash_name[RTE_HASH_NAMESIZE];
1474 struct rte_hash_parameters fdir_hash_params = {
1475 .name = fdir_hash_name,
1476 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1477 .key_len = sizeof(union ixgbe_atr_input),
1478 .hash_func = rte_hash_crc,
1479 .hash_func_init_val = 0,
1480 .socket_id = rte_socket_id(),
1483 TAILQ_INIT(&fdir_info->fdir_list);
1484 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1485 "fdir_%s", eth_dev->data->name);
1486 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1487 if (!fdir_info->hash_handle) {
1488 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1491 fdir_info->hash_map = rte_zmalloc("ixgbe",
1492 sizeof(struct ixgbe_fdir_filter *) *
1493 IXGBE_MAX_FDIR_FILTER_NUM,
1495 if (!fdir_info->hash_map) {
1497 "Failed to allocate memory for fdir hash map!");
1500 fdir_info->mask_added = FALSE;
1505 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1507 struct ixgbe_l2_tn_info *l2_tn_info =
1508 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1509 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1510 struct rte_hash_parameters l2_tn_hash_params = {
1511 .name = l2_tn_hash_name,
1512 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1513 .key_len = sizeof(struct ixgbe_l2_tn_key),
1514 .hash_func = rte_hash_crc,
1515 .hash_func_init_val = 0,
1516 .socket_id = rte_socket_id(),
1519 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1520 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1521 "l2_tn_%s", eth_dev->data->name);
1522 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1523 if (!l2_tn_info->hash_handle) {
1524 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1527 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1528 sizeof(struct ixgbe_l2_tn_filter *) *
1529 IXGBE_MAX_L2_TN_FILTER_NUM,
1531 if (!l2_tn_info->hash_map) {
1533 "Failed to allocate memory for L2 TN hash map!");
1536 l2_tn_info->e_tag_en = FALSE;
1537 l2_tn_info->e_tag_fwd_en = FALSE;
1538 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1543 * Negotiate mailbox API version with the PF.
1544 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1545 * Then we try to negotiate starting with the most recent one.
1546 * If all negotiation attempts fail, then we will proceed with
1547 * the default one (ixgbe_mbox_api_10).
1550 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1554 /* start with highest supported, proceed down */
1555 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1562 i != RTE_DIM(sup_ver) &&
1563 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1569 generate_random_mac_addr(struct ether_addr *mac_addr)
1573 /* Set Organizationally Unique Identifier (OUI) prefix. */
1574 mac_addr->addr_bytes[0] = 0x00;
1575 mac_addr->addr_bytes[1] = 0x09;
1576 mac_addr->addr_bytes[2] = 0xC0;
1577 /* Force indication of locally assigned MAC address. */
1578 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1579 /* Generate the last 3 bytes of the MAC address with a random number. */
1580 random = rte_rand();
1581 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1585 * Virtual Function device init
1588 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1592 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1593 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1594 struct ixgbe_hw *hw =
1595 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1596 struct ixgbe_vfta *shadow_vfta =
1597 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1598 struct ixgbe_hwstrip *hwstrip =
1599 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1600 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1602 PMD_INIT_FUNC_TRACE();
1604 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1605 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1606 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1608 /* for secondary processes, we don't initialise any further as primary
1609 * has already done this work. Only check we don't need a different
1612 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1613 struct ixgbe_tx_queue *txq;
1614 /* TX queue function in primary, set by last queue initialized
1615 * Tx queue may not initialized by primary process
1617 if (eth_dev->data->tx_queues) {
1618 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1619 ixgbe_set_tx_function(eth_dev, txq);
1621 /* Use default TX function if we get here */
1622 PMD_INIT_LOG(NOTICE,
1623 "No TX queues configured yet. Using default TX function.");
1626 ixgbe_set_rx_function(eth_dev);
1631 rte_eth_copy_pci_info(eth_dev, pci_dev);
1632 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1634 hw->device_id = pci_dev->id.device_id;
1635 hw->vendor_id = pci_dev->id.vendor_id;
1636 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1638 /* initialize the vfta */
1639 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1641 /* initialize the hw strip bitmap*/
1642 memset(hwstrip, 0, sizeof(*hwstrip));
1644 /* Initialize the shared code (base driver) */
1645 diag = ixgbe_init_shared_code(hw);
1646 if (diag != IXGBE_SUCCESS) {
1647 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1651 /* init_mailbox_params */
1652 hw->mbx.ops.init_params(hw);
1654 /* Reset the hw statistics */
1655 ixgbevf_dev_stats_reset(eth_dev);
1657 /* Disable the interrupts for VF */
1658 ixgbevf_intr_disable(hw);
1660 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1661 diag = hw->mac.ops.reset_hw(hw);
1664 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1665 * the underlying PF driver has not assigned a MAC address to the VF.
1666 * In this case, assign a random MAC address.
1668 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1669 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1673 /* negotiate mailbox API version to use with the PF. */
1674 ixgbevf_negotiate_api(hw);
1676 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1677 ixgbevf_get_queues(hw, &tcs, &tc);
1679 /* Allocate memory for storing MAC addresses */
1680 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1681 hw->mac.num_rar_entries, 0);
1682 if (eth_dev->data->mac_addrs == NULL) {
1684 "Failed to allocate %u bytes needed to store "
1686 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1690 /* Generate a random MAC address, if none was assigned by PF. */
1691 if (is_zero_ether_addr(perm_addr)) {
1692 generate_random_mac_addr(perm_addr);
1693 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1695 rte_free(eth_dev->data->mac_addrs);
1696 eth_dev->data->mac_addrs = NULL;
1699 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1700 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1701 "%02x:%02x:%02x:%02x:%02x:%02x",
1702 perm_addr->addr_bytes[0],
1703 perm_addr->addr_bytes[1],
1704 perm_addr->addr_bytes[2],
1705 perm_addr->addr_bytes[3],
1706 perm_addr->addr_bytes[4],
1707 perm_addr->addr_bytes[5]);
1710 /* Copy the permanent MAC address */
1711 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1713 /* reset the hardware with the new settings */
1714 diag = hw->mac.ops.start_hw(hw);
1720 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1724 rte_intr_callback_register(intr_handle,
1725 ixgbevf_dev_interrupt_handler, eth_dev);
1726 rte_intr_enable(intr_handle);
1727 ixgbevf_intr_enable(hw);
1729 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1730 eth_dev->data->port_id, pci_dev->id.vendor_id,
1731 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1736 /* Virtual Function device uninit */
1739 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1741 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1742 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1743 struct ixgbe_hw *hw;
1745 PMD_INIT_FUNC_TRACE();
1747 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1750 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1752 if (hw->adapter_stopped == 0)
1753 ixgbevf_dev_close(eth_dev);
1755 eth_dev->dev_ops = NULL;
1756 eth_dev->rx_pkt_burst = NULL;
1757 eth_dev->tx_pkt_burst = NULL;
1759 /* Disable the interrupts for VF */
1760 ixgbevf_intr_disable(hw);
1762 rte_free(eth_dev->data->mac_addrs);
1763 eth_dev->data->mac_addrs = NULL;
1765 rte_intr_disable(intr_handle);
1766 rte_intr_callback_unregister(intr_handle,
1767 ixgbevf_dev_interrupt_handler, eth_dev);
1772 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1773 struct rte_pci_device *pci_dev)
1775 return rte_eth_dev_pci_generic_probe(pci_dev,
1776 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1779 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1781 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1784 static struct rte_pci_driver rte_ixgbe_pmd = {
1785 .id_table = pci_id_ixgbe_map,
1786 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1787 .probe = eth_ixgbe_pci_probe,
1788 .remove = eth_ixgbe_pci_remove,
1791 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1792 struct rte_pci_device *pci_dev)
1794 return rte_eth_dev_pci_generic_probe(pci_dev,
1795 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1798 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1800 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1804 * virtual function driver struct
1806 static struct rte_pci_driver rte_ixgbevf_pmd = {
1807 .id_table = pci_id_ixgbevf_map,
1808 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1809 .probe = eth_ixgbevf_pci_probe,
1810 .remove = eth_ixgbevf_pci_remove,
1814 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1816 struct ixgbe_hw *hw =
1817 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818 struct ixgbe_vfta *shadow_vfta =
1819 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1824 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1825 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1826 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1831 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1833 /* update local VFTA copy */
1834 shadow_vfta->vfta[vid_idx] = vfta;
1840 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1843 ixgbe_vlan_hw_strip_enable(dev, queue);
1845 ixgbe_vlan_hw_strip_disable(dev, queue);
1849 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1850 enum rte_vlan_type vlan_type,
1853 struct ixgbe_hw *hw =
1854 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1860 qinq &= IXGBE_DMATXCTL_GDV;
1862 switch (vlan_type) {
1863 case ETH_VLAN_TYPE_INNER:
1865 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1866 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1867 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1868 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1869 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1870 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1871 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1874 PMD_DRV_LOG(ERR, "Inner type is not supported"
1878 case ETH_VLAN_TYPE_OUTER:
1880 /* Only the high 16-bits is valid */
1881 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1882 IXGBE_EXVET_VET_EXT_SHIFT);
1884 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1885 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1886 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1887 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1888 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1889 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1890 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1896 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1904 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1906 struct ixgbe_hw *hw =
1907 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910 PMD_INIT_FUNC_TRACE();
1912 /* Filter Table Disable */
1913 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1914 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1916 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1920 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1922 struct ixgbe_hw *hw =
1923 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924 struct ixgbe_vfta *shadow_vfta =
1925 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1929 PMD_INIT_FUNC_TRACE();
1931 /* Filter Table Enable */
1932 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1933 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1934 vlnctrl |= IXGBE_VLNCTRL_VFE;
1936 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1938 /* write whatever is in local vfta copy */
1939 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1940 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1944 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1946 struct ixgbe_hwstrip *hwstrip =
1947 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1948 struct ixgbe_rx_queue *rxq;
1950 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1954 IXGBE_SET_HWSTRIP(hwstrip, queue);
1956 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1958 if (queue >= dev->data->nb_rx_queues)
1961 rxq = dev->data->rx_queues[queue];
1964 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1966 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1970 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1972 struct ixgbe_hw *hw =
1973 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1976 PMD_INIT_FUNC_TRACE();
1978 if (hw->mac.type == ixgbe_mac_82598EB) {
1979 /* No queue level support */
1980 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1984 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1985 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1986 ctrl &= ~IXGBE_RXDCTL_VME;
1987 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1989 /* record those setting for HW strip per queue */
1990 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1994 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1996 struct ixgbe_hw *hw =
1997 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2000 PMD_INIT_FUNC_TRACE();
2002 if (hw->mac.type == ixgbe_mac_82598EB) {
2003 /* No queue level supported */
2004 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2008 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2009 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2010 ctrl |= IXGBE_RXDCTL_VME;
2011 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2013 /* record those setting for HW strip per queue */
2014 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2018 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2020 struct ixgbe_hw *hw =
2021 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024 struct ixgbe_rx_queue *rxq;
2026 PMD_INIT_FUNC_TRACE();
2028 if (hw->mac.type == ixgbe_mac_82598EB) {
2029 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2030 ctrl &= ~IXGBE_VLNCTRL_VME;
2031 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2033 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2034 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2035 rxq = dev->data->rx_queues[i];
2036 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2037 ctrl &= ~IXGBE_RXDCTL_VME;
2038 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2040 /* record those setting for HW strip per queue */
2041 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2047 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2049 struct ixgbe_hw *hw =
2050 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 struct ixgbe_rx_queue *rxq;
2055 PMD_INIT_FUNC_TRACE();
2057 if (hw->mac.type == ixgbe_mac_82598EB) {
2058 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2059 ctrl |= IXGBE_VLNCTRL_VME;
2060 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2062 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2063 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2064 rxq = dev->data->rx_queues[i];
2065 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2066 ctrl |= IXGBE_RXDCTL_VME;
2067 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2069 /* record those setting for HW strip per queue */
2070 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2076 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2078 struct ixgbe_hw *hw =
2079 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082 PMD_INIT_FUNC_TRACE();
2084 /* DMATXCTRL: Geric Double VLAN Disable */
2085 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2086 ctrl &= ~IXGBE_DMATXCTL_GDV;
2087 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2089 /* CTRL_EXT: Global Double VLAN Disable */
2090 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2091 ctrl &= ~IXGBE_EXTENDED_VLAN;
2092 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2097 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2099 struct ixgbe_hw *hw =
2100 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103 PMD_INIT_FUNC_TRACE();
2105 /* DMATXCTRL: Geric Double VLAN Enable */
2106 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2107 ctrl |= IXGBE_DMATXCTL_GDV;
2108 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2110 /* CTRL_EXT: Global Double VLAN Enable */
2111 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2112 ctrl |= IXGBE_EXTENDED_VLAN;
2113 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2115 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2116 if (hw->mac.type == ixgbe_mac_X550 ||
2117 hw->mac.type == ixgbe_mac_X550EM_x ||
2118 hw->mac.type == ixgbe_mac_X550EM_a) {
2119 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2120 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2121 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2125 * VET EXT field in the EXVET register = 0x8100 by default
2126 * So no need to change. Same to VT field of DMATXCTL register
2131 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2133 if (mask & ETH_VLAN_STRIP_MASK) {
2134 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2135 ixgbe_vlan_hw_strip_enable_all(dev);
2137 ixgbe_vlan_hw_strip_disable_all(dev);
2140 if (mask & ETH_VLAN_FILTER_MASK) {
2141 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2142 ixgbe_vlan_hw_filter_enable(dev);
2144 ixgbe_vlan_hw_filter_disable(dev);
2147 if (mask & ETH_VLAN_EXTEND_MASK) {
2148 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2149 ixgbe_vlan_hw_extend_enable(dev);
2151 ixgbe_vlan_hw_extend_disable(dev);
2156 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2158 struct ixgbe_hw *hw =
2159 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2160 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2161 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2163 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2164 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2168 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2170 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2175 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2178 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2184 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2185 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2191 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2193 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2194 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2196 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2198 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2199 /* check multi-queue mode */
2200 switch (dev_conf->rxmode.mq_mode) {
2201 case ETH_MQ_RX_VMDQ_DCB:
2202 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2204 case ETH_MQ_RX_VMDQ_DCB_RSS:
2205 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2206 PMD_INIT_LOG(ERR, "SRIOV active,"
2207 " unsupported mq_mode rx %d.",
2208 dev_conf->rxmode.mq_mode);
2211 case ETH_MQ_RX_VMDQ_RSS:
2212 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2213 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2214 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2215 PMD_INIT_LOG(ERR, "SRIOV is active,"
2216 " invalid queue number"
2217 " for VMDQ RSS, allowed"
2218 " value are 1, 2 or 4.");
2222 case ETH_MQ_RX_VMDQ_ONLY:
2223 case ETH_MQ_RX_NONE:
2224 /* if nothing mq mode configure, use default scheme */
2225 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2226 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2227 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2229 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2230 /* SRIOV only works in VMDq enable mode */
2231 PMD_INIT_LOG(ERR, "SRIOV is active,"
2232 " wrong mq_mode rx %d.",
2233 dev_conf->rxmode.mq_mode);
2237 switch (dev_conf->txmode.mq_mode) {
2238 case ETH_MQ_TX_VMDQ_DCB:
2239 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2240 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2242 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2243 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2247 /* check valid queue number */
2248 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2249 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2250 PMD_INIT_LOG(ERR, "SRIOV is active,"
2251 " nb_rx_q=%d nb_tx_q=%d queue number"
2252 " must be less than or equal to %d.",
2254 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2258 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2259 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2263 /* check configuration for vmdb+dcb mode */
2264 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2265 const struct rte_eth_vmdq_dcb_conf *conf;
2267 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2268 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2269 IXGBE_VMDQ_DCB_NB_QUEUES);
2272 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2273 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2274 conf->nb_queue_pools == ETH_32_POOLS)) {
2275 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2276 " nb_queue_pools must be %d or %d.",
2277 ETH_16_POOLS, ETH_32_POOLS);
2281 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2282 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2284 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2285 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2286 IXGBE_VMDQ_DCB_NB_QUEUES);
2289 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2290 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2291 conf->nb_queue_pools == ETH_32_POOLS)) {
2292 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2293 " nb_queue_pools != %d and"
2294 " nb_queue_pools != %d.",
2295 ETH_16_POOLS, ETH_32_POOLS);
2300 /* For DCB mode check our configuration before we go further */
2301 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2302 const struct rte_eth_dcb_rx_conf *conf;
2304 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2305 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2306 IXGBE_DCB_NB_QUEUES);
2309 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2310 if (!(conf->nb_tcs == ETH_4_TCS ||
2311 conf->nb_tcs == ETH_8_TCS)) {
2312 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2313 " and nb_tcs != %d.",
2314 ETH_4_TCS, ETH_8_TCS);
2319 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2320 const struct rte_eth_dcb_tx_conf *conf;
2322 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2323 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2324 IXGBE_DCB_NB_QUEUES);
2327 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2328 if (!(conf->nb_tcs == ETH_4_TCS ||
2329 conf->nb_tcs == ETH_8_TCS)) {
2330 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2331 " and nb_tcs != %d.",
2332 ETH_4_TCS, ETH_8_TCS);
2338 * When DCB/VT is off, maximum number of queues changes,
2339 * except for 82598EB, which remains constant.
2341 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2342 hw->mac.type != ixgbe_mac_82598EB) {
2343 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2345 "Neither VT nor DCB are enabled, "
2347 IXGBE_NONE_MODE_TX_NB_QUEUES);
2356 ixgbe_dev_configure(struct rte_eth_dev *dev)
2358 struct ixgbe_interrupt *intr =
2359 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2360 struct ixgbe_adapter *adapter =
2361 (struct ixgbe_adapter *)dev->data->dev_private;
2364 PMD_INIT_FUNC_TRACE();
2365 /* multipe queue mode checking */
2366 ret = ixgbe_check_mq_mode(dev);
2368 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2373 /* set flag to update link status after init */
2374 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2377 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2378 * allocation or vector Rx preconditions we will reset it.
2380 adapter->rx_bulk_alloc_allowed = true;
2381 adapter->rx_vec_allowed = true;
2387 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2389 struct ixgbe_hw *hw =
2390 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391 struct ixgbe_interrupt *intr =
2392 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2395 /* only set up it on X550EM_X */
2396 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2397 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2398 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2399 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2400 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2401 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2406 * Configure device link speed and setup link.
2407 * It returns 0 on success.
2410 ixgbe_dev_start(struct rte_eth_dev *dev)
2412 struct ixgbe_hw *hw =
2413 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414 struct ixgbe_vf_info *vfinfo =
2415 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2416 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2417 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2418 uint32_t intr_vector = 0;
2419 int err, link_up = 0, negotiate = 0;
2424 uint32_t *link_speeds;
2426 PMD_INIT_FUNC_TRACE();
2428 /* IXGBE devices don't support:
2429 * - half duplex (checked afterwards for valid speeds)
2430 * - fixed speed: TODO implement
2432 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2433 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2434 dev->data->port_id);
2438 /* disable uio/vfio intr/eventfd mapping */
2439 rte_intr_disable(intr_handle);
2442 hw->adapter_stopped = 0;
2443 ixgbe_stop_adapter(hw);
2445 /* reinitialize adapter
2446 * this calls reset and start
2448 status = ixgbe_pf_reset_hw(hw);
2451 hw->mac.ops.start_hw(hw);
2452 hw->mac.get_link_status = true;
2454 /* configure PF module if SRIOV enabled */
2455 ixgbe_pf_host_configure(dev);
2457 ixgbe_dev_phy_intr_setup(dev);
2459 /* check and configure queue intr-vector mapping */
2460 if ((rte_intr_cap_multiple(intr_handle) ||
2461 !RTE_ETH_DEV_SRIOV(dev).active) &&
2462 dev->data->dev_conf.intr_conf.rxq != 0) {
2463 intr_vector = dev->data->nb_rx_queues;
2464 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2465 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2466 IXGBE_MAX_INTR_QUEUE_NUM);
2469 if (rte_intr_efd_enable(intr_handle, intr_vector))
2473 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2474 intr_handle->intr_vec =
2475 rte_zmalloc("intr_vec",
2476 dev->data->nb_rx_queues * sizeof(int), 0);
2477 if (intr_handle->intr_vec == NULL) {
2478 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2479 " intr_vec", dev->data->nb_rx_queues);
2484 /* confiugre msix for sleep until rx interrupt */
2485 ixgbe_configure_msix(dev);
2487 /* initialize transmission unit */
2488 ixgbe_dev_tx_init(dev);
2490 /* This can fail when allocating mbufs for descriptor rings */
2491 err = ixgbe_dev_rx_init(dev);
2493 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2497 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2498 ETH_VLAN_EXTEND_MASK;
2499 ixgbe_vlan_offload_set(dev, mask);
2501 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2502 /* Enable vlan filtering for VMDq */
2503 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2506 /* Configure DCB hw */
2507 ixgbe_configure_dcb(dev);
2509 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2510 err = ixgbe_fdir_configure(dev);
2515 /* Restore vf rate limit */
2516 if (vfinfo != NULL) {
2517 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2518 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2519 if (vfinfo[vf].tx_rate[idx] != 0)
2520 rte_pmd_ixgbe_set_vf_rate_limit(
2521 dev->data->port_id, vf,
2522 vfinfo[vf].tx_rate[idx],
2526 ixgbe_restore_statistics_mapping(dev);
2528 err = ixgbe_dev_rxtx_start(dev);
2530 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2534 /* Skip link setup if loopback mode is enabled for 82599. */
2535 if (hw->mac.type == ixgbe_mac_82599EB &&
2536 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2537 goto skip_link_setup;
2539 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2540 err = hw->mac.ops.setup_sfp(hw);
2545 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2546 /* Turn on the copper */
2547 ixgbe_set_phy_power(hw, true);
2549 /* Turn on the laser */
2550 ixgbe_enable_tx_laser(hw);
2553 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2556 dev->data->dev_link.link_status = link_up;
2558 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2562 link_speeds = &dev->data->dev_conf.link_speeds;
2563 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2564 ETH_LINK_SPEED_10G)) {
2565 PMD_INIT_LOG(ERR, "Invalid link setting");
2570 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2571 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2572 IXGBE_LINK_SPEED_82599_AUTONEG :
2573 IXGBE_LINK_SPEED_82598_AUTONEG;
2575 if (*link_speeds & ETH_LINK_SPEED_10G)
2576 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2577 if (*link_speeds & ETH_LINK_SPEED_1G)
2578 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2579 if (*link_speeds & ETH_LINK_SPEED_100M)
2580 speed |= IXGBE_LINK_SPEED_100_FULL;
2583 err = ixgbe_setup_link(hw, speed, link_up);
2589 if (rte_intr_allow_others(intr_handle)) {
2590 /* check if lsc interrupt is enabled */
2591 if (dev->data->dev_conf.intr_conf.lsc != 0)
2592 ixgbe_dev_lsc_interrupt_setup(dev);
2593 ixgbe_dev_macsec_interrupt_setup(dev);
2595 rte_intr_callback_unregister(intr_handle,
2596 ixgbe_dev_interrupt_handler, dev);
2597 if (dev->data->dev_conf.intr_conf.lsc != 0)
2598 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2599 " no intr multiplex");
2602 /* check if rxq interrupt is enabled */
2603 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2604 rte_intr_dp_is_en(intr_handle))
2605 ixgbe_dev_rxq_interrupt_setup(dev);
2607 /* enable uio/vfio intr/eventfd mapping */
2608 rte_intr_enable(intr_handle);
2610 /* resume enabled intr since hw reset */
2611 ixgbe_enable_intr(dev);
2612 ixgbe_l2_tunnel_conf(dev);
2613 ixgbe_filter_restore(dev);
2618 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2619 ixgbe_dev_clear_queues(dev);
2624 * Stop device: disable rx and tx functions to allow for reconfiguring.
2627 ixgbe_dev_stop(struct rte_eth_dev *dev)
2629 struct rte_eth_link link;
2630 struct ixgbe_hw *hw =
2631 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632 struct ixgbe_vf_info *vfinfo =
2633 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2634 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2635 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2638 PMD_INIT_FUNC_TRACE();
2640 /* disable interrupts */
2641 ixgbe_disable_intr(hw);
2644 ixgbe_pf_reset_hw(hw);
2645 hw->adapter_stopped = 0;
2648 ixgbe_stop_adapter(hw);
2650 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2651 vfinfo[vf].clear_to_send = false;
2653 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2654 /* Turn off the copper */
2655 ixgbe_set_phy_power(hw, false);
2657 /* Turn off the laser */
2658 ixgbe_disable_tx_laser(hw);
2661 ixgbe_dev_clear_queues(dev);
2663 /* Clear stored conf */
2664 dev->data->scattered_rx = 0;
2667 /* Clear recorded link status */
2668 memset(&link, 0, sizeof(link));
2669 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2671 if (!rte_intr_allow_others(intr_handle))
2672 /* resume to the default handler */
2673 rte_intr_callback_register(intr_handle,
2674 ixgbe_dev_interrupt_handler,
2677 /* Clean datapath event and queue/vec mapping */
2678 rte_intr_efd_disable(intr_handle);
2679 if (intr_handle->intr_vec != NULL) {
2680 rte_free(intr_handle->intr_vec);
2681 intr_handle->intr_vec = NULL;
2686 * Set device link up: enable tx.
2689 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2691 struct ixgbe_hw *hw =
2692 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2693 if (hw->mac.type == ixgbe_mac_82599EB) {
2694 #ifdef RTE_NIC_BYPASS
2695 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2696 /* Not suported in bypass mode */
2697 PMD_INIT_LOG(ERR, "Set link up is not supported "
2698 "by device id 0x%x", hw->device_id);
2704 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2705 /* Turn on the copper */
2706 ixgbe_set_phy_power(hw, true);
2708 /* Turn on the laser */
2709 ixgbe_enable_tx_laser(hw);
2716 * Set device link down: disable tx.
2719 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2721 struct ixgbe_hw *hw =
2722 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2723 if (hw->mac.type == ixgbe_mac_82599EB) {
2724 #ifdef RTE_NIC_BYPASS
2725 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2726 /* Not suported in bypass mode */
2727 PMD_INIT_LOG(ERR, "Set link down is not supported "
2728 "by device id 0x%x", hw->device_id);
2734 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2735 /* Turn off the copper */
2736 ixgbe_set_phy_power(hw, false);
2738 /* Turn off the laser */
2739 ixgbe_disable_tx_laser(hw);
2746 * Reest and stop device.
2749 ixgbe_dev_close(struct rte_eth_dev *dev)
2751 struct ixgbe_hw *hw =
2752 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2754 PMD_INIT_FUNC_TRACE();
2756 ixgbe_pf_reset_hw(hw);
2758 ixgbe_dev_stop(dev);
2759 hw->adapter_stopped = 1;
2761 ixgbe_dev_free_queues(dev);
2763 ixgbe_disable_pcie_master(hw);
2765 /* reprogram the RAR[0] in case user changed it. */
2766 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2770 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2771 struct ixgbe_hw_stats *hw_stats,
2772 struct ixgbe_macsec_stats *macsec_stats,
2773 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2774 uint64_t *total_qprc, uint64_t *total_qprdc)
2776 uint32_t bprc, lxon, lxoff, total;
2777 uint32_t delta_gprc = 0;
2779 /* Workaround for RX byte count not including CRC bytes when CRC
2780 * strip is enabled. CRC bytes are removed from counters when crc_strip
2783 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2784 IXGBE_HLREG0_RXCRCSTRP);
2786 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2787 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2788 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2789 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2791 for (i = 0; i < 8; i++) {
2792 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2794 /* global total per queue */
2795 hw_stats->mpc[i] += mp;
2796 /* Running comprehensive total for stats display */
2797 *total_missed_rx += hw_stats->mpc[i];
2798 if (hw->mac.type == ixgbe_mac_82598EB) {
2799 hw_stats->rnbc[i] +=
2800 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2801 hw_stats->pxonrxc[i] +=
2802 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2803 hw_stats->pxoffrxc[i] +=
2804 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2806 hw_stats->pxonrxc[i] +=
2807 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2808 hw_stats->pxoffrxc[i] +=
2809 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2810 hw_stats->pxon2offc[i] +=
2811 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2813 hw_stats->pxontxc[i] +=
2814 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2815 hw_stats->pxofftxc[i] +=
2816 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2818 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2819 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2820 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2821 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2823 delta_gprc += delta_qprc;
2825 hw_stats->qprc[i] += delta_qprc;
2826 hw_stats->qptc[i] += delta_qptc;
2828 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2829 hw_stats->qbrc[i] +=
2830 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2832 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2834 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2835 hw_stats->qbtc[i] +=
2836 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2838 hw_stats->qprdc[i] += delta_qprdc;
2839 *total_qprdc += hw_stats->qprdc[i];
2841 *total_qprc += hw_stats->qprc[i];
2842 *total_qbrc += hw_stats->qbrc[i];
2844 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2845 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2846 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2849 * An errata states that gprc actually counts good + missed packets:
2850 * Workaround to set gprc to summated queue packet receives
2852 hw_stats->gprc = *total_qprc;
2854 if (hw->mac.type != ixgbe_mac_82598EB) {
2855 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2856 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2857 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2858 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2859 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2860 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2861 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2862 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2864 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2865 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2866 /* 82598 only has a counter in the high register */
2867 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2868 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2869 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2871 uint64_t old_tpr = hw_stats->tpr;
2873 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2874 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2877 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2879 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2880 hw_stats->gptc += delta_gptc;
2881 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2882 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2885 * Workaround: mprc hardware is incorrectly counting
2886 * broadcasts, so for now we subtract those.
2888 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2889 hw_stats->bprc += bprc;
2890 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2891 if (hw->mac.type == ixgbe_mac_82598EB)
2892 hw_stats->mprc -= bprc;
2894 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2895 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2896 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2897 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2898 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2899 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2901 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2902 hw_stats->lxontxc += lxon;
2903 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2904 hw_stats->lxofftxc += lxoff;
2905 total = lxon + lxoff;
2907 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2908 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2909 hw_stats->gptc -= total;
2910 hw_stats->mptc -= total;
2911 hw_stats->ptc64 -= total;
2912 hw_stats->gotc -= total * ETHER_MIN_LEN;
2914 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2915 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2916 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2917 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2918 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2919 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2920 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2921 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2922 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2923 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2924 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2925 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2926 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2927 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2928 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2929 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2930 /* Only read FCOE on 82599 */
2931 if (hw->mac.type != ixgbe_mac_82598EB) {
2932 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2933 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2934 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2935 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2936 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2939 /* Flow Director Stats registers */
2940 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2941 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2943 /* MACsec Stats registers */
2944 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2945 macsec_stats->out_pkts_encrypted +=
2946 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2947 macsec_stats->out_pkts_protected +=
2948 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2949 macsec_stats->out_octets_encrypted +=
2950 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2951 macsec_stats->out_octets_protected +=
2952 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2953 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2954 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2955 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2956 macsec_stats->in_pkts_unknownsci +=
2957 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2958 macsec_stats->in_octets_decrypted +=
2959 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2960 macsec_stats->in_octets_validated +=
2961 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2962 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2963 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2964 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2965 for (i = 0; i < 2; i++) {
2966 macsec_stats->in_pkts_ok +=
2967 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2968 macsec_stats->in_pkts_invalid +=
2969 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2970 macsec_stats->in_pkts_notvalid +=
2971 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2973 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2974 macsec_stats->in_pkts_notusingsa +=
2975 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2979 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2982 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2984 struct ixgbe_hw *hw =
2985 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2986 struct ixgbe_hw_stats *hw_stats =
2987 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2988 struct ixgbe_macsec_stats *macsec_stats =
2989 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2990 dev->data->dev_private);
2991 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2994 total_missed_rx = 0;
2999 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3000 &total_qbrc, &total_qprc, &total_qprdc);
3005 /* Fill out the rte_eth_stats statistics structure */
3006 stats->ipackets = total_qprc;
3007 stats->ibytes = total_qbrc;
3008 stats->opackets = hw_stats->gptc;
3009 stats->obytes = hw_stats->gotc;
3011 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3012 stats->q_ipackets[i] = hw_stats->qprc[i];
3013 stats->q_opackets[i] = hw_stats->qptc[i];
3014 stats->q_ibytes[i] = hw_stats->qbrc[i];
3015 stats->q_obytes[i] = hw_stats->qbtc[i];
3016 stats->q_errors[i] = hw_stats->qprdc[i];
3020 stats->imissed = total_missed_rx;
3021 stats->ierrors = hw_stats->crcerrs +
3037 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3039 struct ixgbe_hw_stats *stats =
3040 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3042 /* HW registers are cleared on read */
3043 ixgbe_dev_stats_get(dev, NULL);
3045 /* Reset software totals */
3046 memset(stats, 0, sizeof(*stats));
3049 /* This function calculates the number of xstats based on the current config */
3051 ixgbe_xstats_calc_num(void) {
3052 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3053 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3054 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3057 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3058 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3060 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3061 unsigned stat, i, count;
3063 if (xstats_names != NULL) {
3066 /* Note: limit >= cnt_stats checked upstream
3067 * in rte_eth_xstats_names()
3070 /* Extended stats from ixgbe_hw_stats */
3071 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3072 snprintf(xstats_names[count].name,
3073 sizeof(xstats_names[count].name),
3075 rte_ixgbe_stats_strings[i].name);
3080 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3081 snprintf(xstats_names[count].name,
3082 sizeof(xstats_names[count].name),
3084 rte_ixgbe_macsec_strings[i].name);
3088 /* RX Priority Stats */
3089 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3090 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3091 snprintf(xstats_names[count].name,
3092 sizeof(xstats_names[count].name),
3093 "rx_priority%u_%s", i,
3094 rte_ixgbe_rxq_strings[stat].name);
3099 /* TX Priority Stats */
3100 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3101 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3102 snprintf(xstats_names[count].name,
3103 sizeof(xstats_names[count].name),
3104 "tx_priority%u_%s", i,
3105 rte_ixgbe_txq_strings[stat].name);
3113 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3114 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3118 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3121 if (xstats_names != NULL)
3122 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3123 snprintf(xstats_names[i].name,
3124 sizeof(xstats_names[i].name),
3125 "%s", rte_ixgbevf_stats_strings[i].name);
3126 return IXGBEVF_NB_XSTATS;
3130 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3133 struct ixgbe_hw *hw =
3134 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135 struct ixgbe_hw_stats *hw_stats =
3136 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3137 struct ixgbe_macsec_stats *macsec_stats =
3138 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3139 dev->data->dev_private);
3140 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3141 unsigned i, stat, count = 0;
3143 count = ixgbe_xstats_calc_num();
3148 total_missed_rx = 0;
3153 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3154 &total_qbrc, &total_qprc, &total_qprdc);
3156 /* If this is a reset xstats is NULL, and we have cleared the
3157 * registers by reading them.
3162 /* Extended stats from ixgbe_hw_stats */
3164 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3165 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3166 rte_ixgbe_stats_strings[i].offset);
3167 xstats[count].id = count;
3172 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3173 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3174 rte_ixgbe_macsec_strings[i].offset);
3175 xstats[count].id = count;
3179 /* RX Priority Stats */
3180 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3181 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3182 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3183 rte_ixgbe_rxq_strings[stat].offset +
3184 (sizeof(uint64_t) * i));
3185 xstats[count].id = count;
3190 /* TX Priority Stats */
3191 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3192 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3193 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3194 rte_ixgbe_txq_strings[stat].offset +
3195 (sizeof(uint64_t) * i));
3196 xstats[count].id = count;
3204 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3206 struct ixgbe_hw_stats *stats =
3207 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3208 struct ixgbe_macsec_stats *macsec_stats =
3209 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3210 dev->data->dev_private);
3212 unsigned count = ixgbe_xstats_calc_num();
3214 /* HW registers are cleared on read */
3215 ixgbe_dev_xstats_get(dev, NULL, count);
3217 /* Reset software totals */
3218 memset(stats, 0, sizeof(*stats));
3219 memset(macsec_stats, 0, sizeof(*macsec_stats));
3223 ixgbevf_update_stats(struct rte_eth_dev *dev)
3225 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3226 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3227 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3229 /* Good Rx packet, include VF loopback */
3230 UPDATE_VF_STAT(IXGBE_VFGPRC,
3231 hw_stats->last_vfgprc, hw_stats->vfgprc);
3233 /* Good Rx octets, include VF loopback */
3234 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3235 hw_stats->last_vfgorc, hw_stats->vfgorc);
3237 /* Good Tx packet, include VF loopback */
3238 UPDATE_VF_STAT(IXGBE_VFGPTC,
3239 hw_stats->last_vfgptc, hw_stats->vfgptc);
3241 /* Good Tx octets, include VF loopback */
3242 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3243 hw_stats->last_vfgotc, hw_stats->vfgotc);
3245 /* Rx Multicst Packet */
3246 UPDATE_VF_STAT(IXGBE_VFMPRC,
3247 hw_stats->last_vfmprc, hw_stats->vfmprc);
3251 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3254 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3255 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3258 if (n < IXGBEVF_NB_XSTATS)
3259 return IXGBEVF_NB_XSTATS;
3261 ixgbevf_update_stats(dev);
3266 /* Extended stats */
3267 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3269 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3270 rte_ixgbevf_stats_strings[i].offset);
3273 return IXGBEVF_NB_XSTATS;
3277 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3279 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3280 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3282 ixgbevf_update_stats(dev);
3287 stats->ipackets = hw_stats->vfgprc;
3288 stats->ibytes = hw_stats->vfgorc;
3289 stats->opackets = hw_stats->vfgptc;
3290 stats->obytes = hw_stats->vfgotc;
3294 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3296 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3297 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3299 /* Sync HW register to the last stats */
3300 ixgbevf_dev_stats_get(dev, NULL);
3302 /* reset HW current stats*/
3303 hw_stats->vfgprc = 0;
3304 hw_stats->vfgorc = 0;
3305 hw_stats->vfgptc = 0;
3306 hw_stats->vfgotc = 0;
3310 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3312 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313 u16 eeprom_verh, eeprom_verl;
3317 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3318 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3320 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3321 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3323 ret += 1; /* add the size of '\0' */
3324 if (fw_size < (u32)ret)
3331 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3333 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3334 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3335 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3337 dev_info->pci_dev = pci_dev;
3338 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3339 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3340 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3342 * When DCB/VT is off, maximum number of queues changes,
3343 * except for 82598EB, which remains constant.
3345 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3346 hw->mac.type != ixgbe_mac_82598EB)
3347 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3349 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3350 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3351 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3352 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3353 dev_info->max_vfs = pci_dev->max_vfs;
3354 if (hw->mac.type == ixgbe_mac_82598EB)
3355 dev_info->max_vmdq_pools = ETH_16_POOLS;
3357 dev_info->max_vmdq_pools = ETH_64_POOLS;
3358 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3359 dev_info->rx_offload_capa =
3360 DEV_RX_OFFLOAD_VLAN_STRIP |
3361 DEV_RX_OFFLOAD_IPV4_CKSUM |
3362 DEV_RX_OFFLOAD_UDP_CKSUM |
3363 DEV_RX_OFFLOAD_TCP_CKSUM;
3366 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3369 if ((hw->mac.type == ixgbe_mac_82599EB ||
3370 hw->mac.type == ixgbe_mac_X540) &&
3371 !RTE_ETH_DEV_SRIOV(dev).active)
3372 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3374 if (hw->mac.type == ixgbe_mac_82599EB ||
3375 hw->mac.type == ixgbe_mac_X540)
3376 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3378 if (hw->mac.type == ixgbe_mac_X550 ||
3379 hw->mac.type == ixgbe_mac_X550EM_x ||
3380 hw->mac.type == ixgbe_mac_X550EM_a)
3381 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3383 dev_info->tx_offload_capa =
3384 DEV_TX_OFFLOAD_VLAN_INSERT |
3385 DEV_TX_OFFLOAD_IPV4_CKSUM |
3386 DEV_TX_OFFLOAD_UDP_CKSUM |
3387 DEV_TX_OFFLOAD_TCP_CKSUM |
3388 DEV_TX_OFFLOAD_SCTP_CKSUM |
3389 DEV_TX_OFFLOAD_TCP_TSO;
3391 if (hw->mac.type == ixgbe_mac_82599EB ||
3392 hw->mac.type == ixgbe_mac_X540)
3393 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3395 if (hw->mac.type == ixgbe_mac_X550 ||
3396 hw->mac.type == ixgbe_mac_X550EM_x ||
3397 hw->mac.type == ixgbe_mac_X550EM_a)
3398 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3400 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3402 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3403 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3404 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3406 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3410 dev_info->default_txconf = (struct rte_eth_txconf) {
3412 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3413 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3414 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3416 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3417 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3418 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3419 ETH_TXQ_FLAGS_NOOFFLOADS,
3422 dev_info->rx_desc_lim = rx_desc_lim;
3423 dev_info->tx_desc_lim = tx_desc_lim;
3425 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3426 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3427 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3429 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3430 if (hw->mac.type == ixgbe_mac_X540 ||
3431 hw->mac.type == ixgbe_mac_X540_vf ||
3432 hw->mac.type == ixgbe_mac_X550 ||
3433 hw->mac.type == ixgbe_mac_X550_vf) {
3434 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3438 static const uint32_t *
3439 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3441 static const uint32_t ptypes[] = {
3442 /* For non-vec functions,
3443 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3444 * for vec functions,
3445 * refers to _recv_raw_pkts_vec().
3449 RTE_PTYPE_L3_IPV4_EXT,
3451 RTE_PTYPE_L3_IPV6_EXT,
3455 RTE_PTYPE_TUNNEL_IP,
3456 RTE_PTYPE_INNER_L3_IPV6,
3457 RTE_PTYPE_INNER_L3_IPV6_EXT,
3458 RTE_PTYPE_INNER_L4_TCP,
3459 RTE_PTYPE_INNER_L4_UDP,
3463 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3464 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3465 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3466 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3472 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3473 struct rte_eth_dev_info *dev_info)
3475 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3476 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3478 dev_info->pci_dev = pci_dev;
3479 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3480 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3481 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3482 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3483 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3484 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3485 dev_info->max_vfs = pci_dev->max_vfs;
3486 if (hw->mac.type == ixgbe_mac_82598EB)
3487 dev_info->max_vmdq_pools = ETH_16_POOLS;
3489 dev_info->max_vmdq_pools = ETH_64_POOLS;
3490 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3491 DEV_RX_OFFLOAD_IPV4_CKSUM |
3492 DEV_RX_OFFLOAD_UDP_CKSUM |
3493 DEV_RX_OFFLOAD_TCP_CKSUM;
3494 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3495 DEV_TX_OFFLOAD_IPV4_CKSUM |
3496 DEV_TX_OFFLOAD_UDP_CKSUM |
3497 DEV_TX_OFFLOAD_TCP_CKSUM |
3498 DEV_TX_OFFLOAD_SCTP_CKSUM |
3499 DEV_TX_OFFLOAD_TCP_TSO;
3501 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3503 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3504 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3505 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3507 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3511 dev_info->default_txconf = (struct rte_eth_txconf) {
3513 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3514 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3515 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3517 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3518 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3519 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3520 ETH_TXQ_FLAGS_NOOFFLOADS,
3523 dev_info->rx_desc_lim = rx_desc_lim;
3524 dev_info->tx_desc_lim = tx_desc_lim;
3527 /* return 0 means link status changed, -1 means not changed */
3529 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3531 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3532 struct rte_eth_link link, old;
3533 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3537 link.link_status = ETH_LINK_DOWN;
3538 link.link_speed = 0;
3539 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3540 memset(&old, 0, sizeof(old));
3541 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3543 hw->mac.get_link_status = true;
3545 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3546 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3547 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3549 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3552 link.link_speed = ETH_SPEED_NUM_100M;
3553 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3554 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3555 if (link.link_status == old.link_status)
3561 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3562 if (link.link_status == old.link_status)
3566 link.link_status = ETH_LINK_UP;
3567 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3569 switch (link_speed) {
3571 case IXGBE_LINK_SPEED_UNKNOWN:
3572 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3573 link.link_speed = ETH_SPEED_NUM_100M;
3576 case IXGBE_LINK_SPEED_100_FULL:
3577 link.link_speed = ETH_SPEED_NUM_100M;
3580 case IXGBE_LINK_SPEED_1GB_FULL:
3581 link.link_speed = ETH_SPEED_NUM_1G;
3584 case IXGBE_LINK_SPEED_10GB_FULL:
3585 link.link_speed = ETH_SPEED_NUM_10G;
3588 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3590 if (link.link_status == old.link_status)
3597 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3599 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3602 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3603 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3604 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3608 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3610 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3613 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3614 fctrl &= (~IXGBE_FCTRL_UPE);
3615 if (dev->data->all_multicast == 1)
3616 fctrl |= IXGBE_FCTRL_MPE;
3618 fctrl &= (~IXGBE_FCTRL_MPE);
3619 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3623 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3625 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3628 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3629 fctrl |= IXGBE_FCTRL_MPE;
3630 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3634 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3636 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639 if (dev->data->promiscuous == 1)
3640 return; /* must remain in all_multicast mode */
3642 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3643 fctrl &= (~IXGBE_FCTRL_MPE);
3644 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3648 * It clears the interrupt causes and enables the interrupt.
3649 * It will be called once only during nic initialized.
3652 * Pointer to struct rte_eth_dev.
3655 * - On success, zero.
3656 * - On failure, a negative value.
3659 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3661 struct ixgbe_interrupt *intr =
3662 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3664 ixgbe_dev_link_status_print(dev);
3665 intr->mask |= IXGBE_EICR_LSC;
3671 * It clears the interrupt causes and enables the interrupt.
3672 * It will be called once only during nic initialized.
3675 * Pointer to struct rte_eth_dev.
3678 * - On success, zero.
3679 * - On failure, a negative value.
3682 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3684 struct ixgbe_interrupt *intr =
3685 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3687 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3693 * It clears the interrupt causes and enables the interrupt.
3694 * It will be called once only during nic initialized.
3697 * Pointer to struct rte_eth_dev.
3700 * - On success, zero.
3701 * - On failure, a negative value.
3704 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3706 struct ixgbe_interrupt *intr =
3707 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3709 intr->mask |= IXGBE_EICR_LINKSEC;
3715 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3718 * Pointer to struct rte_eth_dev.
3721 * - On success, zero.
3722 * - On failure, a negative value.
3725 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3728 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3729 struct ixgbe_interrupt *intr =
3730 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3732 /* clear all cause mask */
3733 ixgbe_disable_intr(hw);
3735 /* read-on-clear nic registers here */
3736 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3737 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3741 /* set flag for async link update */
3742 if (eicr & IXGBE_EICR_LSC)
3743 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3745 if (eicr & IXGBE_EICR_MAILBOX)
3746 intr->flags |= IXGBE_FLAG_MAILBOX;
3748 if (eicr & IXGBE_EICR_LINKSEC)
3749 intr->flags |= IXGBE_FLAG_MACSEC;
3751 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3752 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3753 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3754 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3760 * It gets and then prints the link status.
3763 * Pointer to struct rte_eth_dev.
3766 * - On success, zero.
3767 * - On failure, a negative value.
3770 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3772 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3773 struct rte_eth_link link;
3775 memset(&link, 0, sizeof(link));
3776 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3777 if (link.link_status) {
3778 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3779 (int)(dev->data->port_id),
3780 (unsigned)link.link_speed,
3781 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3782 "full-duplex" : "half-duplex");
3784 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3785 (int)(dev->data->port_id));
3787 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3788 pci_dev->addr.domain,
3790 pci_dev->addr.devid,
3791 pci_dev->addr.function);
3795 * It executes link_update after knowing an interrupt occurred.
3798 * Pointer to struct rte_eth_dev.
3801 * - On success, zero.
3802 * - On failure, a negative value.
3805 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3806 struct rte_intr_handle *intr_handle)
3808 struct ixgbe_interrupt *intr =
3809 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3811 struct rte_eth_link link;
3812 struct ixgbe_hw *hw =
3813 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3815 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3817 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3818 ixgbe_pf_mbx_process(dev);
3819 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3822 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3823 ixgbe_handle_lasi(hw);
3824 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3827 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3828 /* get the link status before link update, for predicting later */
3829 memset(&link, 0, sizeof(link));
3830 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3832 ixgbe_dev_link_update(dev, 0);
3835 if (!link.link_status)
3836 /* handle it 1 sec later, wait it being stable */
3837 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3838 /* likely to down */
3840 /* handle it 4 sec later, wait it being stable */
3841 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3843 ixgbe_dev_link_status_print(dev);
3844 intr->mask_original = intr->mask;
3845 /* only disable lsc interrupt */
3846 intr->mask &= ~IXGBE_EIMS_LSC;
3847 if (rte_eal_alarm_set(timeout * 1000,
3848 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3849 PMD_DRV_LOG(ERR, "Error setting alarm");
3851 intr->mask = intr->mask_original;
3854 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3855 ixgbe_enable_intr(dev);
3856 rte_intr_enable(intr_handle);
3862 * Interrupt handler which shall be registered for alarm callback for delayed
3863 * handling specific interrupt to wait for the stable nic state. As the
3864 * NIC interrupt state is not stable for ixgbe after link is just down,
3865 * it needs to wait 4 seconds to get the stable status.
3868 * Pointer to interrupt handle.
3870 * The address of parameter (struct rte_eth_dev *) regsitered before.
3876 ixgbe_dev_interrupt_delayed_handler(void *param)
3878 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3879 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3880 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3881 struct ixgbe_interrupt *intr =
3882 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3883 struct ixgbe_hw *hw =
3884 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3887 ixgbe_disable_intr(hw);
3889 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3890 if (eicr & IXGBE_EICR_MAILBOX)
3891 ixgbe_pf_mbx_process(dev);
3893 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3894 ixgbe_handle_lasi(hw);
3895 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3898 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3899 ixgbe_dev_link_update(dev, 0);
3900 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3901 ixgbe_dev_link_status_print(dev);
3902 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3905 if (intr->flags & IXGBE_FLAG_MACSEC) {
3906 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3908 intr->flags &= ~IXGBE_FLAG_MACSEC;
3911 /* restore original mask */
3912 intr->mask = intr->mask_original;
3913 intr->mask_original = 0;
3915 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3916 ixgbe_enable_intr(dev);
3917 rte_intr_enable(intr_handle);
3921 * Interrupt handler triggered by NIC for handling
3922 * specific interrupt.
3925 * Pointer to interrupt handle.
3927 * The address of parameter (struct rte_eth_dev *) regsitered before.
3933 ixgbe_dev_interrupt_handler(void *param)
3935 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3937 ixgbe_dev_interrupt_get_status(dev);
3938 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
3942 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3944 struct ixgbe_hw *hw;
3946 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3947 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3951 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3953 struct ixgbe_hw *hw;
3955 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3956 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3960 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3962 struct ixgbe_hw *hw;
3968 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3970 fc_conf->pause_time = hw->fc.pause_time;
3971 fc_conf->high_water = hw->fc.high_water[0];
3972 fc_conf->low_water = hw->fc.low_water[0];
3973 fc_conf->send_xon = hw->fc.send_xon;
3974 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3977 * Return rx_pause status according to actual setting of
3980 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3981 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3987 * Return tx_pause status according to actual setting of
3990 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3991 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3996 if (rx_pause && tx_pause)
3997 fc_conf->mode = RTE_FC_FULL;
3999 fc_conf->mode = RTE_FC_RX_PAUSE;
4001 fc_conf->mode = RTE_FC_TX_PAUSE;
4003 fc_conf->mode = RTE_FC_NONE;
4009 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4011 struct ixgbe_hw *hw;
4013 uint32_t rx_buf_size;
4014 uint32_t max_high_water;
4016 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4023 PMD_INIT_FUNC_TRACE();
4025 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4026 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4027 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4030 * At least reserve one Ethernet frame for watermark
4031 * high_water/low_water in kilo bytes for ixgbe
4033 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4034 if ((fc_conf->high_water > max_high_water) ||
4035 (fc_conf->high_water < fc_conf->low_water)) {
4036 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4037 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4041 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4042 hw->fc.pause_time = fc_conf->pause_time;
4043 hw->fc.high_water[0] = fc_conf->high_water;
4044 hw->fc.low_water[0] = fc_conf->low_water;
4045 hw->fc.send_xon = fc_conf->send_xon;
4046 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4048 err = ixgbe_fc_enable(hw);
4050 /* Not negotiated is not an error case */
4051 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4053 /* check if we want to forward MAC frames - driver doesn't have native
4054 * capability to do that, so we'll write the registers ourselves */
4056 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4058 /* set or clear MFLCN.PMCF bit depending on configuration */
4059 if (fc_conf->mac_ctrl_frame_fwd != 0)
4060 mflcn |= IXGBE_MFLCN_PMCF;
4062 mflcn &= ~IXGBE_MFLCN_PMCF;
4064 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4065 IXGBE_WRITE_FLUSH(hw);
4070 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4075 * ixgbe_pfc_enable_generic - Enable flow control
4076 * @hw: pointer to hardware structure
4077 * @tc_num: traffic class number
4078 * Enable flow control according to the current settings.
4081 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4084 uint32_t mflcn_reg, fccfg_reg;
4086 uint32_t fcrtl, fcrth;
4090 /* Validate the water mark configuration */
4091 if (!hw->fc.pause_time) {
4092 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4096 /* Low water mark of zero causes XOFF floods */
4097 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4098 /* High/Low water can not be 0 */
4099 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4100 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4101 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4105 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4106 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4107 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4111 /* Negotiate the fc mode to use */
4112 ixgbe_fc_autoneg(hw);
4114 /* Disable any previous flow control settings */
4115 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4116 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4118 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4119 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4121 switch (hw->fc.current_mode) {
4124 * If the count of enabled RX Priority Flow control >1,
4125 * and the TX pause can not be disabled
4128 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4129 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4130 if (reg & IXGBE_FCRTH_FCEN)
4134 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4136 case ixgbe_fc_rx_pause:
4138 * Rx Flow control is enabled and Tx Flow control is
4139 * disabled by software override. Since there really
4140 * isn't a way to advertise that we are capable of RX
4141 * Pause ONLY, we will advertise that we support both
4142 * symmetric and asymmetric Rx PAUSE. Later, we will
4143 * disable the adapter's ability to send PAUSE frames.
4145 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4147 * If the count of enabled RX Priority Flow control >1,
4148 * and the TX pause can not be disabled
4151 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4152 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4153 if (reg & IXGBE_FCRTH_FCEN)
4157 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4159 case ixgbe_fc_tx_pause:
4161 * Tx Flow control is enabled, and Rx Flow control is
4162 * disabled by software override.
4164 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4167 /* Flow control (both Rx and Tx) is enabled by SW override. */
4168 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4169 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4172 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4173 ret_val = IXGBE_ERR_CONFIG;
4177 /* Set 802.3x based flow control settings. */
4178 mflcn_reg |= IXGBE_MFLCN_DPF;
4179 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4180 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4182 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4183 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4184 hw->fc.high_water[tc_num]) {
4185 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4186 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4187 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4189 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4191 * In order to prevent Tx hangs when the internal Tx
4192 * switch is enabled we must set the high water mark
4193 * to the maximum FCRTH value. This allows the Tx
4194 * switch to function even under heavy Rx workloads.
4196 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4198 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4200 /* Configure pause time (2 TCs per register) */
4201 reg = hw->fc.pause_time * 0x00010001;
4202 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4203 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4205 /* Configure flow control refresh threshold value */
4206 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4213 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4215 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4216 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4218 if (hw->mac.type != ixgbe_mac_82598EB) {
4219 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4225 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4228 uint32_t rx_buf_size;
4229 uint32_t max_high_water;
4231 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4232 struct ixgbe_hw *hw =
4233 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4234 struct ixgbe_dcb_config *dcb_config =
4235 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4237 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4244 PMD_INIT_FUNC_TRACE();
4246 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4247 tc_num = map[pfc_conf->priority];
4248 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4249 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4251 * At least reserve one Ethernet frame for watermark
4252 * high_water/low_water in kilo bytes for ixgbe
4254 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4255 if ((pfc_conf->fc.high_water > max_high_water) ||
4256 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4257 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4258 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4262 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4263 hw->fc.pause_time = pfc_conf->fc.pause_time;
4264 hw->fc.send_xon = pfc_conf->fc.send_xon;
4265 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4266 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4268 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4270 /* Not negotiated is not an error case */
4271 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4274 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4279 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4280 struct rte_eth_rss_reta_entry64 *reta_conf,
4283 uint16_t i, sp_reta_size;
4286 uint16_t idx, shift;
4287 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4290 PMD_INIT_FUNC_TRACE();
4292 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4293 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4298 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4299 if (reta_size != sp_reta_size) {
4300 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4301 "(%d) doesn't match the number hardware can supported "
4302 "(%d)", reta_size, sp_reta_size);
4306 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4307 idx = i / RTE_RETA_GROUP_SIZE;
4308 shift = i % RTE_RETA_GROUP_SIZE;
4309 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4313 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4314 if (mask == IXGBE_4_BIT_MASK)
4317 r = IXGBE_READ_REG(hw, reta_reg);
4318 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4319 if (mask & (0x1 << j))
4320 reta |= reta_conf[idx].reta[shift + j] <<
4323 reta |= r & (IXGBE_8_BIT_MASK <<
4326 IXGBE_WRITE_REG(hw, reta_reg, reta);
4333 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4334 struct rte_eth_rss_reta_entry64 *reta_conf,
4337 uint16_t i, sp_reta_size;
4340 uint16_t idx, shift;
4341 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4344 PMD_INIT_FUNC_TRACE();
4345 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4346 if (reta_size != sp_reta_size) {
4347 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4348 "(%d) doesn't match the number hardware can supported "
4349 "(%d)", reta_size, sp_reta_size);
4353 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4354 idx = i / RTE_RETA_GROUP_SIZE;
4355 shift = i % RTE_RETA_GROUP_SIZE;
4356 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4361 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4362 reta = IXGBE_READ_REG(hw, reta_reg);
4363 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4364 if (mask & (0x1 << j))
4365 reta_conf[idx].reta[shift + j] =
4366 ((reta >> (CHAR_BIT * j)) &
4375 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4376 uint32_t index, uint32_t pool)
4378 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4379 uint32_t enable_addr = 1;
4381 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4385 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4387 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4389 ixgbe_clear_rar(hw, index);
4393 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4395 ixgbe_remove_rar(dev, 0);
4397 ixgbe_add_rar(dev, addr, 0, 0);
4401 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4403 if (strcmp(dev->data->drv_name, drv->driver.name))
4410 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4411 struct ether_addr *mac_addr)
4413 struct ixgbe_hw *hw;
4414 struct ixgbe_vf_info *vfinfo;
4416 uint8_t *new_mac = (uint8_t *)(mac_addr);
4417 struct rte_eth_dev *dev;
4418 struct rte_pci_device *pci_dev;
4420 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4422 dev = &rte_eth_devices[port];
4423 pci_dev = IXGBE_DEV_TO_PCI(dev);
4425 if (!is_device_supported(dev, &rte_ixgbe_pmd))
4428 if (vf >= pci_dev->max_vfs)
4431 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4432 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4433 rar_entry = hw->mac.num_rar_entries - (vf + 1);
4435 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4436 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4438 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4445 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4449 struct ixgbe_hw *hw;
4450 struct rte_eth_dev_info dev_info;
4451 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4453 ixgbe_dev_info_get(dev, &dev_info);
4455 /* check that mtu is within the allowed range */
4456 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4459 /* refuse mtu that requires the support of scattered packets when this
4460 * feature has not been enabled before.
4462 if (!dev->data->scattered_rx &&
4463 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4464 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4467 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4468 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4470 /* switch to jumbo mode if needed */
4471 if (frame_size > ETHER_MAX_LEN) {
4472 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4473 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4475 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4476 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4478 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4480 /* update max frame size */
4481 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4483 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4484 maxfrs &= 0x0000FFFF;
4485 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4486 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4492 * Virtual Function operations
4495 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4497 PMD_INIT_FUNC_TRACE();
4499 /* Clear interrupt mask to stop from interrupts being generated */
4500 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4502 IXGBE_WRITE_FLUSH(hw);
4506 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4508 PMD_INIT_FUNC_TRACE();
4510 /* VF enable interrupt autoclean */
4511 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4512 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4513 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4515 IXGBE_WRITE_FLUSH(hw);
4519 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4521 struct rte_eth_conf *conf = &dev->data->dev_conf;
4522 struct ixgbe_adapter *adapter =
4523 (struct ixgbe_adapter *)dev->data->dev_private;
4525 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4526 dev->data->port_id);
4529 * VF has no ability to enable/disable HW CRC
4530 * Keep the persistent behavior the same as Host PF
4532 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4533 if (!conf->rxmode.hw_strip_crc) {
4534 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4535 conf->rxmode.hw_strip_crc = 1;
4538 if (conf->rxmode.hw_strip_crc) {
4539 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4540 conf->rxmode.hw_strip_crc = 0;
4545 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4546 * allocation or vector Rx preconditions we will reset it.
4548 adapter->rx_bulk_alloc_allowed = true;
4549 adapter->rx_vec_allowed = true;
4555 ixgbevf_dev_start(struct rte_eth_dev *dev)
4557 struct ixgbe_hw *hw =
4558 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4559 uint32_t intr_vector = 0;
4560 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4561 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4565 PMD_INIT_FUNC_TRACE();
4567 hw->mac.ops.reset_hw(hw);
4568 hw->mac.get_link_status = true;
4570 /* negotiate mailbox API version to use with the PF. */
4571 ixgbevf_negotiate_api(hw);
4573 ixgbevf_dev_tx_init(dev);
4575 /* This can fail when allocating mbufs for descriptor rings */
4576 err = ixgbevf_dev_rx_init(dev);
4578 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4579 ixgbe_dev_clear_queues(dev);
4584 ixgbevf_set_vfta_all(dev, 1);
4587 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4588 ETH_VLAN_EXTEND_MASK;
4589 ixgbevf_vlan_offload_set(dev, mask);
4591 ixgbevf_dev_rxtx_start(dev);
4593 /* check and configure queue intr-vector mapping */
4594 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4595 intr_vector = dev->data->nb_rx_queues;
4596 if (rte_intr_efd_enable(intr_handle, intr_vector))
4600 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4601 intr_handle->intr_vec =
4602 rte_zmalloc("intr_vec",
4603 dev->data->nb_rx_queues * sizeof(int), 0);
4604 if (intr_handle->intr_vec == NULL) {
4605 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4606 " intr_vec", dev->data->nb_rx_queues);
4610 ixgbevf_configure_msix(dev);
4612 rte_intr_enable(intr_handle);
4614 /* Re-enable interrupt for VF */
4615 ixgbevf_intr_enable(hw);
4621 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4623 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4624 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4625 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4627 PMD_INIT_FUNC_TRACE();
4629 ixgbevf_intr_disable(hw);
4631 hw->adapter_stopped = 1;
4632 ixgbe_stop_adapter(hw);
4635 * Clear what we set, but we still keep shadow_vfta to
4636 * restore after device starts
4638 ixgbevf_set_vfta_all(dev, 0);
4640 /* Clear stored conf */
4641 dev->data->scattered_rx = 0;
4643 ixgbe_dev_clear_queues(dev);
4645 /* Clean datapath event and queue/vec mapping */
4646 rte_intr_efd_disable(intr_handle);
4647 if (intr_handle->intr_vec != NULL) {
4648 rte_free(intr_handle->intr_vec);
4649 intr_handle->intr_vec = NULL;
4654 ixgbevf_dev_close(struct rte_eth_dev *dev)
4656 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4658 PMD_INIT_FUNC_TRACE();
4662 ixgbevf_dev_stop(dev);
4664 ixgbe_dev_free_queues(dev);
4667 * Remove the VF MAC address ro ensure
4668 * that the VF traffic goes to the PF
4669 * after stop, close and detach of the VF
4671 ixgbevf_remove_mac_addr(dev, 0);
4674 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4676 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677 struct ixgbe_vfta *shadow_vfta =
4678 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4679 int i = 0, j = 0, vfta = 0, mask = 1;
4681 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4682 vfta = shadow_vfta->vfta[i];
4685 for (j = 0; j < 32; j++) {
4687 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4697 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4699 struct ixgbe_hw *hw =
4700 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4701 struct ixgbe_vfta *shadow_vfta =
4702 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4703 uint32_t vid_idx = 0;
4704 uint32_t vid_bit = 0;
4707 PMD_INIT_FUNC_TRACE();
4709 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4710 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4712 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4715 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4716 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4718 /* Save what we set and retore it after device reset */
4720 shadow_vfta->vfta[vid_idx] |= vid_bit;
4722 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4728 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4730 struct ixgbe_hw *hw =
4731 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4734 PMD_INIT_FUNC_TRACE();
4736 if (queue >= hw->mac.max_rx_queues)
4739 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4741 ctrl |= IXGBE_RXDCTL_VME;
4743 ctrl &= ~IXGBE_RXDCTL_VME;
4744 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4746 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4750 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4752 struct ixgbe_hw *hw =
4753 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4757 /* VF function only support hw strip feature, others are not support */
4758 if (mask & ETH_VLAN_STRIP_MASK) {
4759 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4761 for (i = 0; i < hw->mac.max_rx_queues; i++)
4762 ixgbevf_vlan_strip_queue_set(dev, i, on);
4767 ixgbe_vt_check(struct ixgbe_hw *hw)
4771 /* if Virtualization Technology is enabled */
4772 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4773 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4774 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4782 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4784 uint32_t vector = 0;
4786 switch (hw->mac.mc_filter_type) {
4787 case 0: /* use bits [47:36] of the address */
4788 vector = ((uc_addr->addr_bytes[4] >> 4) |
4789 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4791 case 1: /* use bits [46:35] of the address */
4792 vector = ((uc_addr->addr_bytes[4] >> 3) |
4793 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4795 case 2: /* use bits [45:34] of the address */
4796 vector = ((uc_addr->addr_bytes[4] >> 2) |
4797 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4799 case 3: /* use bits [43:32] of the address */
4800 vector = ((uc_addr->addr_bytes[4]) |
4801 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4803 default: /* Invalid mc_filter_type */
4807 /* vector can only be 12-bits or boundary will be exceeded */
4813 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4821 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4822 const uint32_t ixgbe_uta_bit_shift = 5;
4823 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4824 const uint32_t bit1 = 0x1;
4826 struct ixgbe_hw *hw =
4827 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4828 struct ixgbe_uta_info *uta_info =
4829 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4831 /* The UTA table only exists on 82599 hardware and newer */
4832 if (hw->mac.type < ixgbe_mac_82599EB)
4835 vector = ixgbe_uta_vector(hw, mac_addr);
4836 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4837 uta_shift = vector & ixgbe_uta_bit_mask;
4839 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4843 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4845 uta_info->uta_in_use++;
4846 reg_val |= (bit1 << uta_shift);
4847 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4849 uta_info->uta_in_use--;
4850 reg_val &= ~(bit1 << uta_shift);
4851 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4854 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4856 if (uta_info->uta_in_use > 0)
4857 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4858 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4860 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4866 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4869 struct ixgbe_hw *hw =
4870 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4871 struct ixgbe_uta_info *uta_info =
4872 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4874 /* The UTA table only exists on 82599 hardware and newer */
4875 if (hw->mac.type < ixgbe_mac_82599EB)
4879 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4880 uta_info->uta_shadow[i] = ~0;
4881 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4884 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4885 uta_info->uta_shadow[i] = 0;
4886 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4894 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4896 uint32_t new_val = orig_val;
4898 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4899 new_val |= IXGBE_VMOLR_AUPE;
4900 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4901 new_val |= IXGBE_VMOLR_ROMPE;
4902 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4903 new_val |= IXGBE_VMOLR_ROPE;
4904 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4905 new_val |= IXGBE_VMOLR_BAM;
4906 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4907 new_val |= IXGBE_VMOLR_MPE;
4913 rte_pmd_ixgbe_ping_vf(uint8_t port, uint16_t vf)
4915 struct ixgbe_hw *hw;
4916 struct ixgbe_vf_info *vfinfo;
4917 struct rte_eth_dev *dev;
4918 struct rte_pci_device *pci_dev;
4921 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4923 dev = &rte_eth_devices[port];
4924 pci_dev = IXGBE_DEV_TO_PCI(dev);
4926 if (!is_device_supported(dev, &rte_ixgbe_pmd))
4929 if (vf >= pci_dev->max_vfs)
4932 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4933 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4935 ctrl = IXGBE_PF_CONTROL_MSG;
4936 if (vfinfo[vf].clear_to_send)
4937 ctrl |= IXGBE_VT_MSGTYPE_CTS;
4939 ixgbe_write_mbx(hw, &ctrl, 1, vf);
4945 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4947 struct ixgbe_hw *hw;
4948 struct ixgbe_mac_info *mac;
4949 struct rte_eth_dev *dev;
4950 struct rte_pci_device *pci_dev;
4952 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4954 dev = &rte_eth_devices[port];
4955 pci_dev = IXGBE_DEV_TO_PCI(dev);
4957 if (!is_device_supported(dev, &rte_ixgbe_pmd))
4960 if (vf >= pci_dev->max_vfs)
4966 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4969 mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4975 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4977 struct ixgbe_hw *hw;
4978 struct ixgbe_mac_info *mac;
4979 struct rte_eth_dev *dev;
4980 struct rte_pci_device *pci_dev;
4982 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4984 dev = &rte_eth_devices[port];
4985 pci_dev = IXGBE_DEV_TO_PCI(dev);
4987 if (!is_device_supported(dev, &rte_ixgbe_pmd))
4990 if (vf >= pci_dev->max_vfs)
4996 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4998 mac->ops.set_mac_anti_spoofing(hw, on, vf);
5004 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
5006 struct ixgbe_hw *hw;
5008 struct rte_eth_dev *dev;
5009 struct rte_pci_device *pci_dev;
5011 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5013 dev = &rte_eth_devices[port];
5014 pci_dev = IXGBE_DEV_TO_PCI(dev);
5016 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5019 if (vf >= pci_dev->max_vfs)
5022 if (vlan_id > ETHER_MAX_VLAN_ID)
5025 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5026 ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
5029 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
5034 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
5040 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
5042 struct ixgbe_hw *hw;
5044 struct rte_eth_dev *dev;
5046 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5048 dev = &rte_eth_devices[port];
5050 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5056 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057 ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5058 /* enable or disable VMDQ loopback */
5060 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5062 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5064 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5070 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5072 struct ixgbe_hw *hw;
5075 int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5076 struct rte_eth_dev *dev;
5078 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5080 dev = &rte_eth_devices[port];
5082 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5088 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5089 for (i = 0; i <= num_queues; i++) {
5090 reg_value = IXGBE_QDE_WRITE |
5091 (i << IXGBE_QDE_IDX_SHIFT) |
5092 (on & IXGBE_QDE_ENABLE);
5093 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5100 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5102 struct ixgbe_hw *hw;
5104 struct rte_eth_dev *dev;
5105 struct rte_pci_device *pci_dev;
5107 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5109 dev = &rte_eth_devices[port];
5110 pci_dev = IXGBE_DEV_TO_PCI(dev);
5112 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5115 /* only support VF's 0 to 63 */
5116 if ((vf >= pci_dev->max_vfs) || (vf > 63))
5122 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123 reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5125 reg_value |= IXGBE_SRRCTL_DROP_EN;
5127 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5129 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5135 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5137 struct rte_eth_dev *dev;
5138 struct rte_pci_device *pci_dev;
5139 struct ixgbe_hw *hw;
5140 uint16_t queues_per_pool;
5143 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5145 dev = &rte_eth_devices[port];
5146 pci_dev = IXGBE_DEV_TO_PCI(dev);
5147 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5149 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5152 if (vf >= pci_dev->max_vfs)
5158 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5160 /* The PF has 128 queue pairs and in SRIOV configuration
5161 * those queues will be assigned to VF's, so RXDCTL
5162 * registers will be dealing with queues which will be
5164 * Let's say we have SRIOV configured with 31 VF's then the
5165 * first 124 queues 0-123 will be allocated to VF's and only
5166 * the last 4 queues 123-127 will be assigned to the PF.
5168 if (hw->mac.type == ixgbe_mac_82598EB)
5169 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5172 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5175 for (q = 0; q < queues_per_pool; q++)
5176 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5177 q + vf * queues_per_pool, on);
5182 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5185 struct rte_eth_dev *dev;
5186 struct rte_pci_device *pci_dev;
5187 struct ixgbe_hw *hw;
5190 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5192 dev = &rte_eth_devices[port];
5193 pci_dev = IXGBE_DEV_TO_PCI(dev);
5195 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5198 if (vf >= pci_dev->max_vfs)
5204 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5207 if (hw->mac.type == ixgbe_mac_82598EB) {
5208 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5209 " on 82599 hardware and newer");
5212 if (ixgbe_vt_check(hw) < 0)
5215 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5222 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5228 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5230 struct rte_eth_dev *dev;
5231 struct rte_pci_device *pci_dev;
5234 const uint8_t bit1 = 0x1;
5235 struct ixgbe_hw *hw;
5237 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5239 dev = &rte_eth_devices[port];
5240 pci_dev = IXGBE_DEV_TO_PCI(dev);
5242 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5245 if (vf >= pci_dev->max_vfs)
5251 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5253 if (ixgbe_vt_check(hw) < 0)
5256 /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5258 addr = IXGBE_VFRE(1);
5259 val = bit1 << (vf - 32);
5261 addr = IXGBE_VFRE(0);
5265 reg = IXGBE_READ_REG(hw, addr);
5272 IXGBE_WRITE_REG(hw, addr, reg);
5278 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5280 struct rte_eth_dev *dev;
5281 struct rte_pci_device *pci_dev;
5284 const uint8_t bit1 = 0x1;
5286 struct ixgbe_hw *hw;
5288 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5290 dev = &rte_eth_devices[port];
5291 pci_dev = IXGBE_DEV_TO_PCI(dev);
5293 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5296 if (vf >= pci_dev->max_vfs)
5302 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303 if (ixgbe_vt_check(hw) < 0)
5306 /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5308 addr = IXGBE_VFTE(1);
5309 val = bit1 << (vf - 32);
5311 addr = IXGBE_VFTE(0);
5315 reg = IXGBE_READ_REG(hw, addr);
5322 IXGBE_WRITE_REG(hw, addr, reg);
5328 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5329 uint64_t vf_mask, uint8_t vlan_on)
5331 struct rte_eth_dev *dev;
5334 struct ixgbe_hw *hw;
5336 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5338 dev = &rte_eth_devices[port];
5340 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5343 if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5346 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5347 if (ixgbe_vt_check(hw) < 0)
5350 for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5351 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5352 ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5362 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5363 uint16_t tx_rate, uint64_t q_msk)
5365 struct rte_eth_dev *dev;
5366 struct ixgbe_hw *hw;
5367 struct ixgbe_vf_info *vfinfo;
5368 struct rte_eth_link link;
5369 uint8_t nb_q_per_pool;
5370 uint32_t queue_stride;
5371 uint32_t queue_idx, idx = 0, vf_idx;
5373 uint16_t total_rate = 0;
5374 struct rte_pci_device *pci_dev;
5376 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5378 dev = &rte_eth_devices[port];
5379 pci_dev = IXGBE_DEV_TO_PCI(dev);
5380 rte_eth_link_get_nowait(port, &link);
5382 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5385 if (vf >= pci_dev->max_vfs)
5388 if (tx_rate > link.link_speed)
5394 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5395 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5396 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5397 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5398 queue_idx = vf * queue_stride;
5399 queue_end = queue_idx + nb_q_per_pool - 1;
5400 if (queue_end >= hw->mac.max_tx_queues)
5404 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5407 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5409 total_rate += vfinfo[vf_idx].tx_rate[idx];
5415 /* Store tx_rate for this vf. */
5416 for (idx = 0; idx < nb_q_per_pool; idx++) {
5417 if (((uint64_t)0x1 << idx) & q_msk) {
5418 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5419 vfinfo[vf].tx_rate[idx] = tx_rate;
5420 total_rate += tx_rate;
5424 if (total_rate > dev->data->dev_link.link_speed) {
5425 /* Reset stored TX rate of the VF if it causes exceed
5428 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5432 /* Set RTTBCNRC of each queue/pool for vf X */
5433 for (; queue_idx <= queue_end; queue_idx++) {
5435 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5442 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5443 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5444 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5445 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5446 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5447 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5448 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5451 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5452 struct rte_eth_mirror_conf *mirror_conf,
5453 uint8_t rule_id, uint8_t on)
5455 uint32_t mr_ctl, vlvf;
5456 uint32_t mp_lsb = 0;
5457 uint32_t mv_msb = 0;
5458 uint32_t mv_lsb = 0;
5459 uint32_t mp_msb = 0;
5462 uint64_t vlan_mask = 0;
5464 const uint8_t pool_mask_offset = 32;
5465 const uint8_t vlan_mask_offset = 32;
5466 const uint8_t dst_pool_offset = 8;
5467 const uint8_t rule_mr_offset = 4;
5468 const uint8_t mirror_rule_mask = 0x0F;
5470 struct ixgbe_mirror_info *mr_info =
5471 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5472 struct ixgbe_hw *hw =
5473 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5474 uint8_t mirror_type = 0;
5476 if (ixgbe_vt_check(hw) < 0)
5479 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5482 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5483 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5484 mirror_conf->rule_type);
5488 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5489 mirror_type |= IXGBE_MRCTL_VLME;
5490 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5491 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5492 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5493 /* search vlan id related pool vlan filter index */
5494 reg_index = ixgbe_find_vlvf_slot(hw,
5495 mirror_conf->vlan.vlan_id[i],
5499 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5500 if ((vlvf & IXGBE_VLVF_VIEN) &&
5501 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5502 mirror_conf->vlan.vlan_id[i]))
5503 vlan_mask |= (1ULL << reg_index);
5510 mv_lsb = vlan_mask & 0xFFFFFFFF;
5511 mv_msb = vlan_mask >> vlan_mask_offset;
5513 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5514 mirror_conf->vlan.vlan_mask;
5515 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5516 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5517 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5518 mirror_conf->vlan.vlan_id[i];
5523 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5524 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5525 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5530 * if enable pool mirror, write related pool mask register,if disable
5531 * pool mirror, clear PFMRVM register
5533 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5534 mirror_type |= IXGBE_MRCTL_VPME;
5536 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5537 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5538 mr_info->mr_conf[rule_id].pool_mask =
5539 mirror_conf->pool_mask;
5544 mr_info->mr_conf[rule_id].pool_mask = 0;
5547 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5548 mirror_type |= IXGBE_MRCTL_UPME;
5549 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5550 mirror_type |= IXGBE_MRCTL_DPME;
5552 /* read mirror control register and recalculate it */
5553 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5556 mr_ctl |= mirror_type;
5557 mr_ctl &= mirror_rule_mask;
5558 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5560 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5562 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5563 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5565 /* write mirrror control register */
5566 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5568 /* write pool mirrror control register */
5569 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5570 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5571 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5574 /* write VLAN mirrror control register */
5575 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5576 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5577 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5585 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5588 uint32_t lsb_val = 0;
5589 uint32_t msb_val = 0;
5590 const uint8_t rule_mr_offset = 4;
5592 struct ixgbe_hw *hw =
5593 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5594 struct ixgbe_mirror_info *mr_info =
5595 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5597 if (ixgbe_vt_check(hw) < 0)
5600 memset(&mr_info->mr_conf[rule_id], 0,
5601 sizeof(struct rte_eth_mirror_conf));
5603 /* clear PFVMCTL register */
5604 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5606 /* clear pool mask register */
5607 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5608 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5610 /* clear vlan mask register */
5611 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5612 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5618 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5620 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5621 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5623 struct ixgbe_hw *hw =
5624 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5626 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5627 mask |= (1 << IXGBE_MISC_VEC_ID);
5628 RTE_SET_USED(queue_id);
5629 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5631 rte_intr_enable(intr_handle);
5637 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5640 struct ixgbe_hw *hw =
5641 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5643 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5644 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5645 RTE_SET_USED(queue_id);
5646 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5652 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5654 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5655 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5657 struct ixgbe_hw *hw =
5658 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5659 struct ixgbe_interrupt *intr =
5660 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5662 if (queue_id < 16) {
5663 ixgbe_disable_intr(hw);
5664 intr->mask |= (1 << queue_id);
5665 ixgbe_enable_intr(dev);
5666 } else if (queue_id < 32) {
5667 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5668 mask &= (1 << queue_id);
5669 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5670 } else if (queue_id < 64) {
5671 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5672 mask &= (1 << (queue_id - 32));
5673 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5675 rte_intr_enable(intr_handle);
5681 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5684 struct ixgbe_hw *hw =
5685 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5686 struct ixgbe_interrupt *intr =
5687 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5689 if (queue_id < 16) {
5690 ixgbe_disable_intr(hw);
5691 intr->mask &= ~(1 << queue_id);
5692 ixgbe_enable_intr(dev);
5693 } else if (queue_id < 32) {
5694 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5695 mask &= ~(1 << queue_id);
5696 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5697 } else if (queue_id < 64) {
5698 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5699 mask &= ~(1 << (queue_id - 32));
5700 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5707 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5708 uint8_t queue, uint8_t msix_vector)
5712 if (direction == -1) {
5714 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5715 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5718 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5720 /* rx or tx cause */
5721 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5722 idx = ((16 * (queue & 1)) + (8 * direction));
5723 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5724 tmp &= ~(0xFF << idx);
5725 tmp |= (msix_vector << idx);
5726 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5731 * set the IVAR registers, mapping interrupt causes to vectors
5733 * pointer to ixgbe_hw struct
5735 * 0 for Rx, 1 for Tx, -1 for other causes
5737 * queue to map the corresponding interrupt to
5739 * the vector to map to the corresponding queue
5742 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5743 uint8_t queue, uint8_t msix_vector)
5747 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5748 if (hw->mac.type == ixgbe_mac_82598EB) {
5749 if (direction == -1)
5751 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5752 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5753 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5754 tmp |= (msix_vector << (8 * (queue & 0x3)));
5755 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5756 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5757 (hw->mac.type == ixgbe_mac_X540)) {
5758 if (direction == -1) {
5760 idx = ((queue & 1) * 8);
5761 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5762 tmp &= ~(0xFF << idx);
5763 tmp |= (msix_vector << idx);
5764 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5766 /* rx or tx causes */
5767 idx = ((16 * (queue & 1)) + (8 * direction));
5768 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5769 tmp &= ~(0xFF << idx);
5770 tmp |= (msix_vector << idx);
5771 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5777 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5779 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5780 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5781 struct ixgbe_hw *hw =
5782 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5784 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5786 /* Configure VF other cause ivar */
5787 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5789 /* won't configure msix register if no mapping is done
5790 * between intr vector and event fd.
5792 if (!rte_intr_dp_is_en(intr_handle))
5795 /* Configure all RX queues of VF */
5796 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5797 /* Force all queue use vector 0,
5798 * as IXGBE_VF_MAXMSIVECOTR = 1
5800 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5801 intr_handle->intr_vec[q_idx] = vector_idx;
5806 * Sets up the hardware to properly generate MSI-X interrupts
5808 * board private structure
5811 ixgbe_configure_msix(struct rte_eth_dev *dev)
5813 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5814 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5815 struct ixgbe_hw *hw =
5816 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5817 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5818 uint32_t vec = IXGBE_MISC_VEC_ID;
5822 /* won't configure msix register if no mapping is done
5823 * between intr vector and event fd
5825 if (!rte_intr_dp_is_en(intr_handle))
5828 if (rte_intr_allow_others(intr_handle))
5829 vec = base = IXGBE_RX_VEC_START;
5831 /* setup GPIE for MSI-x mode */
5832 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5833 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5834 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5835 /* auto clearing and auto setting corresponding bits in EIMS
5836 * when MSI-X interrupt is triggered
5838 if (hw->mac.type == ixgbe_mac_82598EB) {
5839 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5841 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5842 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5844 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5846 /* Populate the IVAR table and set the ITR values to the
5847 * corresponding register.
5849 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5851 /* by default, 1:1 mapping */
5852 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5853 intr_handle->intr_vec[queue_id] = vec;
5854 if (vec < base + intr_handle->nb_efd - 1)
5858 switch (hw->mac.type) {
5859 case ixgbe_mac_82598EB:
5860 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5863 case ixgbe_mac_82599EB:
5864 case ixgbe_mac_X540:
5865 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5870 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5871 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5873 /* set up to autoclear timer, and the vectors */
5874 mask = IXGBE_EIMS_ENABLE_MASK;
5875 mask &= ~(IXGBE_EIMS_OTHER |
5876 IXGBE_EIMS_MAILBOX |
5879 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5882 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5883 uint16_t queue_idx, uint16_t tx_rate)
5885 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5886 uint32_t rf_dec, rf_int;
5888 uint16_t link_speed = dev->data->dev_link.link_speed;
5890 if (queue_idx >= hw->mac.max_tx_queues)
5894 /* Calculate the rate factor values to set */
5895 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5896 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5897 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5899 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5900 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5901 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5902 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5908 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5909 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5912 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5913 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5914 IXGBE_MAX_JUMBO_FRAME_SIZE))
5915 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5916 IXGBE_MMW_SIZE_JUMBO_FRAME);
5918 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5919 IXGBE_MMW_SIZE_DEFAULT);
5921 /* Set RTTBCNRC of queue X */
5922 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5923 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5924 IXGBE_WRITE_FLUSH(hw);
5930 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5931 __attribute__((unused)) uint32_t index,
5932 __attribute__((unused)) uint32_t pool)
5934 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5938 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5939 * operation. Trap this case to avoid exhausting the [very limited]
5940 * set of PF resources used to store VF MAC addresses.
5942 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5944 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5947 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5951 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5953 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5954 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5955 struct ether_addr *mac_addr;
5960 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5961 * not support the deletion of a given MAC address.
5962 * Instead, it imposes to delete all MAC addresses, then to add again
5963 * all MAC addresses with the exception of the one to be deleted.
5965 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5968 * Add again all MAC addresses, with the exception of the deleted one
5969 * and of the permanent MAC address.
5971 for (i = 0, mac_addr = dev->data->mac_addrs;
5972 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5973 /* Skip the deleted MAC address */
5976 /* Skip NULL MAC addresses */
5977 if (is_zero_ether_addr(mac_addr))
5979 /* Skip the permanent MAC address */
5980 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5982 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5985 "Adding again MAC address "
5986 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5988 mac_addr->addr_bytes[0],
5989 mac_addr->addr_bytes[1],
5990 mac_addr->addr_bytes[2],
5991 mac_addr->addr_bytes[3],
5992 mac_addr->addr_bytes[4],
5993 mac_addr->addr_bytes[5],
5999 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6001 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6003 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6007 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6008 struct rte_eth_syn_filter *filter,
6011 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6012 struct ixgbe_filter_info *filter_info =
6013 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6017 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6020 syn_info = filter_info->syn_info;
6023 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6025 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6026 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6028 if (filter->hig_pri)
6029 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6031 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6033 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6034 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6036 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6039 filter_info->syn_info = synqf;
6040 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6041 IXGBE_WRITE_FLUSH(hw);
6046 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6047 struct rte_eth_syn_filter *filter)
6049 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6050 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6052 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6053 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6054 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6061 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6062 enum rte_filter_op filter_op,
6065 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6068 MAC_TYPE_FILTER_SUP(hw->mac.type);
6070 if (filter_op == RTE_ETH_FILTER_NOP)
6074 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6079 switch (filter_op) {
6080 case RTE_ETH_FILTER_ADD:
6081 ret = ixgbe_syn_filter_set(dev,
6082 (struct rte_eth_syn_filter *)arg,
6085 case RTE_ETH_FILTER_DELETE:
6086 ret = ixgbe_syn_filter_set(dev,
6087 (struct rte_eth_syn_filter *)arg,
6090 case RTE_ETH_FILTER_GET:
6091 ret = ixgbe_syn_filter_get(dev,
6092 (struct rte_eth_syn_filter *)arg);
6095 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6104 static inline enum ixgbe_5tuple_protocol
6105 convert_protocol_type(uint8_t protocol_value)
6107 if (protocol_value == IPPROTO_TCP)
6108 return IXGBE_FILTER_PROTOCOL_TCP;
6109 else if (protocol_value == IPPROTO_UDP)
6110 return IXGBE_FILTER_PROTOCOL_UDP;
6111 else if (protocol_value == IPPROTO_SCTP)
6112 return IXGBE_FILTER_PROTOCOL_SCTP;
6114 return IXGBE_FILTER_PROTOCOL_NONE;
6117 /* inject a 5-tuple filter to HW */
6119 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6120 struct ixgbe_5tuple_filter *filter)
6122 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6124 uint32_t ftqf, sdpqf;
6125 uint32_t l34timir = 0;
6126 uint8_t mask = 0xff;
6130 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6131 IXGBE_SDPQF_DSTPORT_SHIFT);
6132 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6134 ftqf = (uint32_t)(filter->filter_info.proto &
6135 IXGBE_FTQF_PROTOCOL_MASK);
6136 ftqf |= (uint32_t)((filter->filter_info.priority &
6137 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6138 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6139 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6140 if (filter->filter_info.dst_ip_mask == 0)
6141 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6142 if (filter->filter_info.src_port_mask == 0)
6143 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6144 if (filter->filter_info.dst_port_mask == 0)
6145 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6146 if (filter->filter_info.proto_mask == 0)
6147 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6148 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6149 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6150 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6152 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6153 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6154 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6155 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6157 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6158 l34timir |= (uint32_t)(filter->queue <<
6159 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6160 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6164 * add a 5tuple filter
6167 * dev: Pointer to struct rte_eth_dev.
6168 * index: the index the filter allocates.
6169 * filter: ponter to the filter that will be added.
6170 * rx_queue: the queue id the filter assigned to.
6173 * - On success, zero.
6174 * - On failure, a negative value.
6177 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6178 struct ixgbe_5tuple_filter *filter)
6180 struct ixgbe_filter_info *filter_info =
6181 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6185 * look for an unused 5tuple filter index,
6186 * and insert the filter to list.
6188 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6189 idx = i / (sizeof(uint32_t) * NBBY);
6190 shift = i % (sizeof(uint32_t) * NBBY);
6191 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6192 filter_info->fivetuple_mask[idx] |= 1 << shift;
6194 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6200 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6201 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6205 ixgbe_inject_5tuple_filter(dev, filter);
6211 * remove a 5tuple filter
6214 * dev: Pointer to struct rte_eth_dev.
6215 * filter: the pointer of the filter will be removed.
6218 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6219 struct ixgbe_5tuple_filter *filter)
6221 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6222 struct ixgbe_filter_info *filter_info =
6223 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6224 uint16_t index = filter->index;
6226 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6227 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6228 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6231 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6232 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6233 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6234 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6235 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6239 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6241 struct ixgbe_hw *hw;
6242 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6244 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6246 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6249 /* refuse mtu that requires the support of scattered packets when this
6250 * feature has not been enabled before.
6252 if (!dev->data->scattered_rx &&
6253 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6254 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6258 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6259 * request of the version 2.0 of the mailbox API.
6260 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6261 * of the mailbox API.
6262 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6263 * prior to 3.11.33 which contains the following change:
6264 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6266 ixgbevf_rlpml_set_vf(hw, max_frame);
6268 /* update max frame size */
6269 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6273 static inline struct ixgbe_5tuple_filter *
6274 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6275 struct ixgbe_5tuple_filter_info *key)
6277 struct ixgbe_5tuple_filter *it;
6279 TAILQ_FOREACH(it, filter_list, entries) {
6280 if (memcmp(key, &it->filter_info,
6281 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6288 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6290 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6291 struct ixgbe_5tuple_filter_info *filter_info)
6293 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6294 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6295 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6298 switch (filter->dst_ip_mask) {
6300 filter_info->dst_ip_mask = 0;
6301 filter_info->dst_ip = filter->dst_ip;
6304 filter_info->dst_ip_mask = 1;
6307 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6311 switch (filter->src_ip_mask) {
6313 filter_info->src_ip_mask = 0;
6314 filter_info->src_ip = filter->src_ip;
6317 filter_info->src_ip_mask = 1;
6320 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6324 switch (filter->dst_port_mask) {
6326 filter_info->dst_port_mask = 0;
6327 filter_info->dst_port = filter->dst_port;
6330 filter_info->dst_port_mask = 1;
6333 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6337 switch (filter->src_port_mask) {
6339 filter_info->src_port_mask = 0;
6340 filter_info->src_port = filter->src_port;
6343 filter_info->src_port_mask = 1;
6346 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6350 switch (filter->proto_mask) {
6352 filter_info->proto_mask = 0;
6353 filter_info->proto =
6354 convert_protocol_type(filter->proto);
6357 filter_info->proto_mask = 1;
6360 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6364 filter_info->priority = (uint8_t)filter->priority;
6369 * add or delete a ntuple filter
6372 * dev: Pointer to struct rte_eth_dev.
6373 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6374 * add: if true, add filter, if false, remove filter
6377 * - On success, zero.
6378 * - On failure, a negative value.
6381 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6382 struct rte_eth_ntuple_filter *ntuple_filter,
6385 struct ixgbe_filter_info *filter_info =
6386 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6387 struct ixgbe_5tuple_filter_info filter_5tuple;
6388 struct ixgbe_5tuple_filter *filter;
6391 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6392 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6396 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6397 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6401 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6403 if (filter != NULL && add) {
6404 PMD_DRV_LOG(ERR, "filter exists.");
6407 if (filter == NULL && !add) {
6408 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6413 filter = rte_zmalloc("ixgbe_5tuple_filter",
6414 sizeof(struct ixgbe_5tuple_filter), 0);
6417 (void)rte_memcpy(&filter->filter_info,
6419 sizeof(struct ixgbe_5tuple_filter_info));
6420 filter->queue = ntuple_filter->queue;
6421 ret = ixgbe_add_5tuple_filter(dev, filter);
6427 ixgbe_remove_5tuple_filter(dev, filter);
6433 * get a ntuple filter
6436 * dev: Pointer to struct rte_eth_dev.
6437 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6440 * - On success, zero.
6441 * - On failure, a negative value.
6444 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6445 struct rte_eth_ntuple_filter *ntuple_filter)
6447 struct ixgbe_filter_info *filter_info =
6448 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6449 struct ixgbe_5tuple_filter_info filter_5tuple;
6450 struct ixgbe_5tuple_filter *filter;
6453 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6454 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6458 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6459 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6463 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6465 if (filter == NULL) {
6466 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6469 ntuple_filter->queue = filter->queue;
6474 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6475 * @dev: pointer to rte_eth_dev structure
6476 * @filter_op:operation will be taken.
6477 * @arg: a pointer to specific structure corresponding to the filter_op
6480 * - On success, zero.
6481 * - On failure, a negative value.
6484 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6485 enum rte_filter_op filter_op,
6488 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6491 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6493 if (filter_op == RTE_ETH_FILTER_NOP)
6497 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6502 switch (filter_op) {
6503 case RTE_ETH_FILTER_ADD:
6504 ret = ixgbe_add_del_ntuple_filter(dev,
6505 (struct rte_eth_ntuple_filter *)arg,
6508 case RTE_ETH_FILTER_DELETE:
6509 ret = ixgbe_add_del_ntuple_filter(dev,
6510 (struct rte_eth_ntuple_filter *)arg,
6513 case RTE_ETH_FILTER_GET:
6514 ret = ixgbe_get_ntuple_filter(dev,
6515 (struct rte_eth_ntuple_filter *)arg);
6518 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6526 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6527 struct rte_eth_ethertype_filter *filter,
6530 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6531 struct ixgbe_filter_info *filter_info =
6532 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6536 struct ixgbe_ethertype_filter ethertype_filter;
6538 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6541 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6542 filter->ether_type == ETHER_TYPE_IPv6) {
6543 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6544 " ethertype filter.", filter->ether_type);
6548 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6549 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6552 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6553 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6557 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6558 if (ret >= 0 && add) {
6559 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6560 filter->ether_type);
6563 if (ret < 0 && !add) {
6564 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6565 filter->ether_type);
6570 etqf = IXGBE_ETQF_FILTER_EN;
6571 etqf |= (uint32_t)filter->ether_type;
6572 etqs |= (uint32_t)((filter->queue <<
6573 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6574 IXGBE_ETQS_RX_QUEUE);
6575 etqs |= IXGBE_ETQS_QUEUE_EN;
6577 ethertype_filter.ethertype = filter->ether_type;
6578 ethertype_filter.etqf = etqf;
6579 ethertype_filter.etqs = etqs;
6580 ethertype_filter.conf = FALSE;
6581 ret = ixgbe_ethertype_filter_insert(filter_info,
6584 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6588 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6592 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6593 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6594 IXGBE_WRITE_FLUSH(hw);
6600 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6601 struct rte_eth_ethertype_filter *filter)
6603 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6604 struct ixgbe_filter_info *filter_info =
6605 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6606 uint32_t etqf, etqs;
6609 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6611 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6612 filter->ether_type);
6616 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6617 if (etqf & IXGBE_ETQF_FILTER_EN) {
6618 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6619 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6621 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6622 IXGBE_ETQS_RX_QUEUE_SHIFT;
6629 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6630 * @dev: pointer to rte_eth_dev structure
6631 * @filter_op:operation will be taken.
6632 * @arg: a pointer to specific structure corresponding to the filter_op
6635 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6636 enum rte_filter_op filter_op,
6639 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6642 MAC_TYPE_FILTER_SUP(hw->mac.type);
6644 if (filter_op == RTE_ETH_FILTER_NOP)
6648 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6653 switch (filter_op) {
6654 case RTE_ETH_FILTER_ADD:
6655 ret = ixgbe_add_del_ethertype_filter(dev,
6656 (struct rte_eth_ethertype_filter *)arg,
6659 case RTE_ETH_FILTER_DELETE:
6660 ret = ixgbe_add_del_ethertype_filter(dev,
6661 (struct rte_eth_ethertype_filter *)arg,
6664 case RTE_ETH_FILTER_GET:
6665 ret = ixgbe_get_ethertype_filter(dev,
6666 (struct rte_eth_ethertype_filter *)arg);
6669 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6677 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6678 enum rte_filter_type filter_type,
6679 enum rte_filter_op filter_op,
6684 switch (filter_type) {
6685 case RTE_ETH_FILTER_NTUPLE:
6686 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6688 case RTE_ETH_FILTER_ETHERTYPE:
6689 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6691 case RTE_ETH_FILTER_SYN:
6692 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6694 case RTE_ETH_FILTER_FDIR:
6695 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6697 case RTE_ETH_FILTER_L2_TUNNEL:
6698 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6700 case RTE_ETH_FILTER_GENERIC:
6701 if (filter_op != RTE_ETH_FILTER_GET)
6703 *(const void **)arg = &ixgbe_flow_ops;
6706 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6716 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6717 u8 **mc_addr_ptr, u32 *vmdq)
6722 mc_addr = *mc_addr_ptr;
6723 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6728 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6729 struct ether_addr *mc_addr_set,
6730 uint32_t nb_mc_addr)
6732 struct ixgbe_hw *hw;
6735 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6736 mc_addr_list = (u8 *)mc_addr_set;
6737 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6738 ixgbe_dev_addr_list_itr, TRUE);
6742 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6744 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6745 uint64_t systime_cycles;
6747 switch (hw->mac.type) {
6748 case ixgbe_mac_X550:
6749 case ixgbe_mac_X550EM_x:
6750 case ixgbe_mac_X550EM_a:
6751 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6752 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6753 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6757 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6758 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6762 return systime_cycles;
6766 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6768 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6769 uint64_t rx_tstamp_cycles;
6771 switch (hw->mac.type) {
6772 case ixgbe_mac_X550:
6773 case ixgbe_mac_X550EM_x:
6774 case ixgbe_mac_X550EM_a:
6775 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6776 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6777 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6781 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6782 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6783 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6787 return rx_tstamp_cycles;
6791 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6793 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6794 uint64_t tx_tstamp_cycles;
6796 switch (hw->mac.type) {
6797 case ixgbe_mac_X550:
6798 case ixgbe_mac_X550EM_x:
6799 case ixgbe_mac_X550EM_a:
6800 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6801 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6802 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6806 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6807 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6808 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6812 return tx_tstamp_cycles;
6816 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6818 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6819 struct ixgbe_adapter *adapter =
6820 (struct ixgbe_adapter *)dev->data->dev_private;
6821 struct rte_eth_link link;
6822 uint32_t incval = 0;
6825 /* Get current link speed. */
6826 memset(&link, 0, sizeof(link));
6827 ixgbe_dev_link_update(dev, 1);
6828 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6830 switch (link.link_speed) {
6831 case ETH_SPEED_NUM_100M:
6832 incval = IXGBE_INCVAL_100;
6833 shift = IXGBE_INCVAL_SHIFT_100;
6835 case ETH_SPEED_NUM_1G:
6836 incval = IXGBE_INCVAL_1GB;
6837 shift = IXGBE_INCVAL_SHIFT_1GB;
6839 case ETH_SPEED_NUM_10G:
6841 incval = IXGBE_INCVAL_10GB;
6842 shift = IXGBE_INCVAL_SHIFT_10GB;
6846 switch (hw->mac.type) {
6847 case ixgbe_mac_X550:
6848 case ixgbe_mac_X550EM_x:
6849 case ixgbe_mac_X550EM_a:
6850 /* Independent of link speed. */
6852 /* Cycles read will be interpreted as ns. */
6855 case ixgbe_mac_X540:
6856 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6858 case ixgbe_mac_82599EB:
6859 incval >>= IXGBE_INCVAL_SHIFT_82599;
6860 shift -= IXGBE_INCVAL_SHIFT_82599;
6861 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6862 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6865 /* Not supported. */
6869 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6870 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6871 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6873 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6874 adapter->systime_tc.cc_shift = shift;
6875 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6877 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6878 adapter->rx_tstamp_tc.cc_shift = shift;
6879 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6881 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6882 adapter->tx_tstamp_tc.cc_shift = shift;
6883 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6887 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6889 struct ixgbe_adapter *adapter =
6890 (struct ixgbe_adapter *)dev->data->dev_private;
6892 adapter->systime_tc.nsec += delta;
6893 adapter->rx_tstamp_tc.nsec += delta;
6894 adapter->tx_tstamp_tc.nsec += delta;
6900 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6903 struct ixgbe_adapter *adapter =
6904 (struct ixgbe_adapter *)dev->data->dev_private;
6906 ns = rte_timespec_to_ns(ts);
6907 /* Set the timecounters to a new value. */
6908 adapter->systime_tc.nsec = ns;
6909 adapter->rx_tstamp_tc.nsec = ns;
6910 adapter->tx_tstamp_tc.nsec = ns;
6916 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6918 uint64_t ns, systime_cycles;
6919 struct ixgbe_adapter *adapter =
6920 (struct ixgbe_adapter *)dev->data->dev_private;
6922 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6923 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6924 *ts = rte_ns_to_timespec(ns);
6930 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6932 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6936 /* Stop the timesync system time. */
6937 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6938 /* Reset the timesync system time value. */
6939 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6940 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6942 /* Enable system time for platforms where it isn't on by default. */
6943 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6944 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6945 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6947 ixgbe_start_timecounters(dev);
6949 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6950 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6952 IXGBE_ETQF_FILTER_EN |
6955 /* Enable timestamping of received PTP packets. */
6956 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6957 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6958 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6960 /* Enable timestamping of transmitted PTP packets. */
6961 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6962 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6963 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6965 IXGBE_WRITE_FLUSH(hw);
6971 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6973 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6976 /* Disable timestamping of transmitted PTP packets. */
6977 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6978 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6979 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6981 /* Disable timestamping of received PTP packets. */
6982 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6983 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6984 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6986 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6987 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6989 /* Stop incrementating the System Time registers. */
6990 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6996 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6997 struct timespec *timestamp,
6998 uint32_t flags __rte_unused)
7000 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7001 struct ixgbe_adapter *adapter =
7002 (struct ixgbe_adapter *)dev->data->dev_private;
7003 uint32_t tsync_rxctl;
7004 uint64_t rx_tstamp_cycles;
7007 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7008 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7011 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7012 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7013 *timestamp = rte_ns_to_timespec(ns);
7019 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7020 struct timespec *timestamp)
7022 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7023 struct ixgbe_adapter *adapter =
7024 (struct ixgbe_adapter *)dev->data->dev_private;
7025 uint32_t tsync_txctl;
7026 uint64_t tx_tstamp_cycles;
7029 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7030 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7033 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7034 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7035 *timestamp = rte_ns_to_timespec(ns);
7041 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7043 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7046 const struct reg_info *reg_group;
7047 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7048 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7050 while ((reg_group = reg_set[g_ind++]))
7051 count += ixgbe_regs_group_count(reg_group);
7057 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7061 const struct reg_info *reg_group;
7063 while ((reg_group = ixgbevf_regs[g_ind++]))
7064 count += ixgbe_regs_group_count(reg_group);
7070 ixgbe_get_regs(struct rte_eth_dev *dev,
7071 struct rte_dev_reg_info *regs)
7073 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7074 uint32_t *data = regs->data;
7077 const struct reg_info *reg_group;
7078 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7079 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7082 regs->length = ixgbe_get_reg_length(dev);
7083 regs->width = sizeof(uint32_t);
7087 /* Support only full register dump */
7088 if ((regs->length == 0) ||
7089 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7090 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7092 while ((reg_group = reg_set[g_ind++]))
7093 count += ixgbe_read_regs_group(dev, &data[count],
7102 ixgbevf_get_regs(struct rte_eth_dev *dev,
7103 struct rte_dev_reg_info *regs)
7105 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7106 uint32_t *data = regs->data;
7109 const struct reg_info *reg_group;
7112 regs->length = ixgbevf_get_reg_length(dev);
7113 regs->width = sizeof(uint32_t);
7117 /* Support only full register dump */
7118 if ((regs->length == 0) ||
7119 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7120 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7122 while ((reg_group = ixgbevf_regs[g_ind++]))
7123 count += ixgbe_read_regs_group(dev, &data[count],
7132 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7134 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7136 /* Return unit is byte count */
7137 return hw->eeprom.word_size * 2;
7141 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7142 struct rte_dev_eeprom_info *in_eeprom)
7144 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7145 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7146 uint16_t *data = in_eeprom->data;
7149 first = in_eeprom->offset >> 1;
7150 length = in_eeprom->length >> 1;
7151 if ((first > hw->eeprom.word_size) ||
7152 ((first + length) > hw->eeprom.word_size))
7155 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7157 return eeprom->ops.read_buffer(hw, first, length, data);
7161 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7162 struct rte_dev_eeprom_info *in_eeprom)
7164 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7165 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7166 uint16_t *data = in_eeprom->data;
7169 first = in_eeprom->offset >> 1;
7170 length = in_eeprom->length >> 1;
7171 if ((first > hw->eeprom.word_size) ||
7172 ((first + length) > hw->eeprom.word_size))
7175 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7177 return eeprom->ops.write_buffer(hw, first, length, data);
7181 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7183 case ixgbe_mac_X550:
7184 case ixgbe_mac_X550EM_x:
7185 case ixgbe_mac_X550EM_a:
7186 return ETH_RSS_RETA_SIZE_512;
7187 case ixgbe_mac_X550_vf:
7188 case ixgbe_mac_X550EM_x_vf:
7189 case ixgbe_mac_X550EM_a_vf:
7190 return ETH_RSS_RETA_SIZE_64;
7192 return ETH_RSS_RETA_SIZE_128;
7197 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7199 case ixgbe_mac_X550:
7200 case ixgbe_mac_X550EM_x:
7201 case ixgbe_mac_X550EM_a:
7202 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7203 return IXGBE_RETA(reta_idx >> 2);
7205 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7206 case ixgbe_mac_X550_vf:
7207 case ixgbe_mac_X550EM_x_vf:
7208 case ixgbe_mac_X550EM_a_vf:
7209 return IXGBE_VFRETA(reta_idx >> 2);
7211 return IXGBE_RETA(reta_idx >> 2);
7216 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7218 case ixgbe_mac_X550_vf:
7219 case ixgbe_mac_X550EM_x_vf:
7220 case ixgbe_mac_X550EM_a_vf:
7221 return IXGBE_VFMRQC;
7228 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7230 case ixgbe_mac_X550_vf:
7231 case ixgbe_mac_X550EM_x_vf:
7232 case ixgbe_mac_X550EM_a_vf:
7233 return IXGBE_VFRSSRK(i);
7235 return IXGBE_RSSRK(i);
7240 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7242 case ixgbe_mac_82599_vf:
7243 case ixgbe_mac_X540_vf:
7251 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7252 struct rte_eth_dcb_info *dcb_info)
7254 struct ixgbe_dcb_config *dcb_config =
7255 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7256 struct ixgbe_dcb_tc_config *tc;
7259 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7260 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7262 dcb_info->nb_tcs = 1;
7264 if (dcb_config->vt_mode) { /* vt is enabled*/
7265 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7266 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7267 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7268 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7269 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7270 for (j = 0; j < dcb_info->nb_tcs; j++) {
7271 dcb_info->tc_queue.tc_rxq[i][j].base =
7272 i * dcb_info->nb_tcs + j;
7273 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7274 dcb_info->tc_queue.tc_txq[i][j].base =
7275 i * dcb_info->nb_tcs + j;
7276 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7279 } else { /* vt is disabled*/
7280 struct rte_eth_dcb_rx_conf *rx_conf =
7281 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7282 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7283 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7284 if (dcb_info->nb_tcs == ETH_4_TCS) {
7285 for (i = 0; i < dcb_info->nb_tcs; i++) {
7286 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7287 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7289 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7290 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7291 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7292 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7293 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7294 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7295 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7296 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7297 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7298 for (i = 0; i < dcb_info->nb_tcs; i++) {
7299 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7300 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7302 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7303 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7304 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7305 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7306 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7307 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7308 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7309 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7310 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7311 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7312 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7313 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7314 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7315 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7316 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7317 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7320 for (i = 0; i < dcb_info->nb_tcs; i++) {
7321 tc = &dcb_config->tc_config[i];
7322 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7327 /* Update e-tag ether type */
7329 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7330 uint16_t ether_type)
7332 uint32_t etag_etype;
7334 if (hw->mac.type != ixgbe_mac_X550 &&
7335 hw->mac.type != ixgbe_mac_X550EM_x &&
7336 hw->mac.type != ixgbe_mac_X550EM_a) {
7340 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7341 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7342 etag_etype |= ether_type;
7343 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7344 IXGBE_WRITE_FLUSH(hw);
7349 /* Config l2 tunnel ether type */
7351 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7352 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7355 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7356 struct ixgbe_l2_tn_info *l2_tn_info =
7357 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7359 if (l2_tunnel == NULL)
7362 switch (l2_tunnel->l2_tunnel_type) {
7363 case RTE_L2_TUNNEL_TYPE_E_TAG:
7364 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7365 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7368 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7376 /* Enable e-tag tunnel */
7378 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7380 uint32_t etag_etype;
7382 if (hw->mac.type != ixgbe_mac_X550 &&
7383 hw->mac.type != ixgbe_mac_X550EM_x &&
7384 hw->mac.type != ixgbe_mac_X550EM_a) {
7388 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7389 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7390 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7391 IXGBE_WRITE_FLUSH(hw);
7396 /* Enable l2 tunnel */
7398 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7399 enum rte_eth_tunnel_type l2_tunnel_type)
7402 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7403 struct ixgbe_l2_tn_info *l2_tn_info =
7404 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7406 switch (l2_tunnel_type) {
7407 case RTE_L2_TUNNEL_TYPE_E_TAG:
7408 l2_tn_info->e_tag_en = TRUE;
7409 ret = ixgbe_e_tag_enable(hw);
7412 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7420 /* Disable e-tag tunnel */
7422 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7424 uint32_t etag_etype;
7426 if (hw->mac.type != ixgbe_mac_X550 &&
7427 hw->mac.type != ixgbe_mac_X550EM_x &&
7428 hw->mac.type != ixgbe_mac_X550EM_a) {
7432 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7433 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7434 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7435 IXGBE_WRITE_FLUSH(hw);
7440 /* Disable l2 tunnel */
7442 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7443 enum rte_eth_tunnel_type l2_tunnel_type)
7446 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7447 struct ixgbe_l2_tn_info *l2_tn_info =
7448 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7450 switch (l2_tunnel_type) {
7451 case RTE_L2_TUNNEL_TYPE_E_TAG:
7452 l2_tn_info->e_tag_en = FALSE;
7453 ret = ixgbe_e_tag_disable(hw);
7456 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7465 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7466 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7469 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7470 uint32_t i, rar_entries;
7471 uint32_t rar_low, rar_high;
7473 if (hw->mac.type != ixgbe_mac_X550 &&
7474 hw->mac.type != ixgbe_mac_X550EM_x &&
7475 hw->mac.type != ixgbe_mac_X550EM_a) {
7479 rar_entries = ixgbe_get_num_rx_addrs(hw);
7481 for (i = 1; i < rar_entries; i++) {
7482 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7483 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7484 if ((rar_high & IXGBE_RAH_AV) &&
7485 (rar_high & IXGBE_RAH_ADTYPE) &&
7486 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7487 l2_tunnel->tunnel_id)) {
7488 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7489 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7491 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7501 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7502 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7505 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7506 uint32_t i, rar_entries;
7507 uint32_t rar_low, rar_high;
7509 if (hw->mac.type != ixgbe_mac_X550 &&
7510 hw->mac.type != ixgbe_mac_X550EM_x &&
7511 hw->mac.type != ixgbe_mac_X550EM_a) {
7515 /* One entry for one tunnel. Try to remove potential existing entry. */
7516 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7518 rar_entries = ixgbe_get_num_rx_addrs(hw);
7520 for (i = 1; i < rar_entries; i++) {
7521 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7522 if (rar_high & IXGBE_RAH_AV) {
7525 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7526 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7527 rar_low = l2_tunnel->tunnel_id;
7529 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7530 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7536 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7537 " Please remove a rule before adding a new one.");
7541 static inline struct ixgbe_l2_tn_filter *
7542 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7543 struct ixgbe_l2_tn_key *key)
7547 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7551 return l2_tn_info->hash_map[ret];
7555 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7556 struct ixgbe_l2_tn_filter *l2_tn_filter)
7560 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7561 &l2_tn_filter->key);
7565 "Failed to insert L2 tunnel filter"
7566 " to hash table %d!",
7571 l2_tn_info->hash_map[ret] = l2_tn_filter;
7573 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7579 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7580 struct ixgbe_l2_tn_key *key)
7583 struct ixgbe_l2_tn_filter *l2_tn_filter;
7585 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7589 "No such L2 tunnel filter to delete %d!",
7594 l2_tn_filter = l2_tn_info->hash_map[ret];
7595 l2_tn_info->hash_map[ret] = NULL;
7597 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7598 rte_free(l2_tn_filter);
7603 /* Add l2 tunnel filter */
7605 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7606 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7610 struct ixgbe_l2_tn_info *l2_tn_info =
7611 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7612 struct ixgbe_l2_tn_key key;
7613 struct ixgbe_l2_tn_filter *node;
7616 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7617 key.tn_id = l2_tunnel->tunnel_id;
7619 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7623 "The L2 tunnel filter already exists!");
7627 node = rte_zmalloc("ixgbe_l2_tn",
7628 sizeof(struct ixgbe_l2_tn_filter),
7633 (void)rte_memcpy(&node->key,
7635 sizeof(struct ixgbe_l2_tn_key));
7636 node->pool = l2_tunnel->pool;
7637 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7644 switch (l2_tunnel->l2_tunnel_type) {
7645 case RTE_L2_TUNNEL_TYPE_E_TAG:
7646 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7649 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7654 if ((!restore) && (ret < 0))
7655 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7660 /* Delete l2 tunnel filter */
7662 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7663 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7666 struct ixgbe_l2_tn_info *l2_tn_info =
7667 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7668 struct ixgbe_l2_tn_key key;
7670 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7671 key.tn_id = l2_tunnel->tunnel_id;
7672 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7676 switch (l2_tunnel->l2_tunnel_type) {
7677 case RTE_L2_TUNNEL_TYPE_E_TAG:
7678 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7681 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7690 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7691 * @dev: pointer to rte_eth_dev structure
7692 * @filter_op:operation will be taken.
7693 * @arg: a pointer to specific structure corresponding to the filter_op
7696 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7697 enum rte_filter_op filter_op,
7702 if (filter_op == RTE_ETH_FILTER_NOP)
7706 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7711 switch (filter_op) {
7712 case RTE_ETH_FILTER_ADD:
7713 ret = ixgbe_dev_l2_tunnel_filter_add
7715 (struct rte_eth_l2_tunnel_conf *)arg,
7718 case RTE_ETH_FILTER_DELETE:
7719 ret = ixgbe_dev_l2_tunnel_filter_del
7721 (struct rte_eth_l2_tunnel_conf *)arg);
7724 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7732 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7736 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7738 if (hw->mac.type != ixgbe_mac_X550 &&
7739 hw->mac.type != ixgbe_mac_X550EM_x &&
7740 hw->mac.type != ixgbe_mac_X550EM_a) {
7744 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7745 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7747 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7748 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7753 /* Enable l2 tunnel forwarding */
7755 ixgbe_dev_l2_tunnel_forwarding_enable
7756 (struct rte_eth_dev *dev,
7757 enum rte_eth_tunnel_type l2_tunnel_type)
7759 struct ixgbe_l2_tn_info *l2_tn_info =
7760 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7763 switch (l2_tunnel_type) {
7764 case RTE_L2_TUNNEL_TYPE_E_TAG:
7765 l2_tn_info->e_tag_fwd_en = TRUE;
7766 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7769 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7777 /* Disable l2 tunnel forwarding */
7779 ixgbe_dev_l2_tunnel_forwarding_disable
7780 (struct rte_eth_dev *dev,
7781 enum rte_eth_tunnel_type l2_tunnel_type)
7783 struct ixgbe_l2_tn_info *l2_tn_info =
7784 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7787 switch (l2_tunnel_type) {
7788 case RTE_L2_TUNNEL_TYPE_E_TAG:
7789 l2_tn_info->e_tag_fwd_en = FALSE;
7790 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7793 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7802 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7803 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7806 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7808 uint32_t vmtir, vmvir;
7809 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7811 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7813 "VF id %u should be less than %u",
7819 if (hw->mac.type != ixgbe_mac_X550 &&
7820 hw->mac.type != ixgbe_mac_X550EM_x &&
7821 hw->mac.type != ixgbe_mac_X550EM_a) {
7826 vmtir = l2_tunnel->tunnel_id;
7830 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7832 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7833 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7835 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7836 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7841 /* Enable l2 tunnel tag insertion */
7843 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7844 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7848 switch (l2_tunnel->l2_tunnel_type) {
7849 case RTE_L2_TUNNEL_TYPE_E_TAG:
7850 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7853 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7861 /* Disable l2 tunnel tag insertion */
7863 ixgbe_dev_l2_tunnel_insertion_disable
7864 (struct rte_eth_dev *dev,
7865 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7869 switch (l2_tunnel->l2_tunnel_type) {
7870 case RTE_L2_TUNNEL_TYPE_E_TAG:
7871 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7874 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7883 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7888 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7890 if (hw->mac.type != ixgbe_mac_X550 &&
7891 hw->mac.type != ixgbe_mac_X550EM_x &&
7892 hw->mac.type != ixgbe_mac_X550EM_a) {
7896 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7898 qde |= IXGBE_QDE_STRIP_TAG;
7900 qde &= ~IXGBE_QDE_STRIP_TAG;
7901 qde &= ~IXGBE_QDE_READ;
7902 qde |= IXGBE_QDE_WRITE;
7903 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7908 /* Enable l2 tunnel tag stripping */
7910 ixgbe_dev_l2_tunnel_stripping_enable
7911 (struct rte_eth_dev *dev,
7912 enum rte_eth_tunnel_type l2_tunnel_type)
7916 switch (l2_tunnel_type) {
7917 case RTE_L2_TUNNEL_TYPE_E_TAG:
7918 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7921 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7929 /* Disable l2 tunnel tag stripping */
7931 ixgbe_dev_l2_tunnel_stripping_disable
7932 (struct rte_eth_dev *dev,
7933 enum rte_eth_tunnel_type l2_tunnel_type)
7937 switch (l2_tunnel_type) {
7938 case RTE_L2_TUNNEL_TYPE_E_TAG:
7939 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7942 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7950 /* Enable/disable l2 tunnel offload functions */
7952 ixgbe_dev_l2_tunnel_offload_set
7953 (struct rte_eth_dev *dev,
7954 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7960 if (l2_tunnel == NULL)
7964 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7966 ret = ixgbe_dev_l2_tunnel_enable(
7968 l2_tunnel->l2_tunnel_type);
7970 ret = ixgbe_dev_l2_tunnel_disable(
7972 l2_tunnel->l2_tunnel_type);
7975 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7977 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7981 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7986 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7988 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7990 l2_tunnel->l2_tunnel_type);
7992 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7994 l2_tunnel->l2_tunnel_type);
7997 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7999 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8001 l2_tunnel->l2_tunnel_type);
8003 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8005 l2_tunnel->l2_tunnel_type);
8012 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8015 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8016 IXGBE_WRITE_FLUSH(hw);
8021 /* There's only one register for VxLAN UDP port.
8022 * So, we cannot add several ports. Will update it.
8025 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8029 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8033 return ixgbe_update_vxlan_port(hw, port);
8036 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8037 * UDP port, it must have a value.
8038 * So, will reset it to the original value 0.
8041 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8046 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8048 if (cur_port != port) {
8049 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8053 return ixgbe_update_vxlan_port(hw, 0);
8056 /* Add UDP tunneling port */
8058 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8059 struct rte_eth_udp_tunnel *udp_tunnel)
8062 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8064 if (hw->mac.type != ixgbe_mac_X550 &&
8065 hw->mac.type != ixgbe_mac_X550EM_x &&
8066 hw->mac.type != ixgbe_mac_X550EM_a) {
8070 if (udp_tunnel == NULL)
8073 switch (udp_tunnel->prot_type) {
8074 case RTE_TUNNEL_TYPE_VXLAN:
8075 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8078 case RTE_TUNNEL_TYPE_GENEVE:
8079 case RTE_TUNNEL_TYPE_TEREDO:
8080 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8085 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8093 /* Remove UDP tunneling port */
8095 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8096 struct rte_eth_udp_tunnel *udp_tunnel)
8099 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8101 if (hw->mac.type != ixgbe_mac_X550 &&
8102 hw->mac.type != ixgbe_mac_X550EM_x &&
8103 hw->mac.type != ixgbe_mac_X550EM_a) {
8107 if (udp_tunnel == NULL)
8110 switch (udp_tunnel->prot_type) {
8111 case RTE_TUNNEL_TYPE_VXLAN:
8112 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8114 case RTE_TUNNEL_TYPE_GENEVE:
8115 case RTE_TUNNEL_TYPE_TEREDO:
8116 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8120 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8129 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8131 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8133 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8137 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8139 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8141 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8144 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8146 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8149 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8152 /* PF reset VF event */
8153 if (in_msg == IXGBE_PF_CONTROL_MSG)
8154 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8158 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8161 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8162 struct ixgbe_interrupt *intr =
8163 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8164 ixgbevf_intr_disable(hw);
8166 /* read-on-clear nic registers here */
8167 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8170 /* only one misc vector supported - mailbox */
8171 eicr &= IXGBE_VTEICR_MASK;
8172 if (eicr == IXGBE_MISC_VEC_ID)
8173 intr->flags |= IXGBE_FLAG_MAILBOX;
8179 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8181 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8182 struct ixgbe_interrupt *intr =
8183 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8185 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8186 ixgbevf_mbx_process(dev);
8187 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8190 ixgbevf_intr_enable(hw);
8196 ixgbevf_dev_interrupt_handler(void *param)
8198 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8200 ixgbevf_dev_interrupt_get_status(dev);
8201 ixgbevf_dev_interrupt_action(dev);
8205 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8206 * @hw: pointer to hardware structure
8208 * Stops the transmit data path and waits for the HW to internally empty
8209 * the Tx security block
8211 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8213 #define IXGBE_MAX_SECTX_POLL 40
8218 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8219 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8220 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8221 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8222 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8223 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8225 /* Use interrupt-safe sleep just in case */
8229 /* For informational purposes only */
8230 if (i >= IXGBE_MAX_SECTX_POLL)
8231 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8232 "path fully disabled. Continuing with init.");
8234 return IXGBE_SUCCESS;
8238 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8239 * @hw: pointer to hardware structure
8241 * Enables the transmit data path.
8243 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8247 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8248 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8249 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8250 IXGBE_WRITE_FLUSH(hw);
8252 return IXGBE_SUCCESS;
8256 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8258 struct ixgbe_hw *hw;
8259 struct rte_eth_dev *dev;
8262 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8264 dev = &rte_eth_devices[port];
8266 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8269 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8271 /* Stop the data paths */
8272 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8276 * As no ixgbe_disable_sec_rx_path equivalent is
8277 * implemented for tx in the base code, and we are
8278 * not allowed to modify the base code in DPDK, so
8279 * just call the hand-written one directly for now.
8280 * The hardware support has been checked by
8281 * ixgbe_disable_sec_rx_path().
8283 ixgbe_disable_sec_tx_path_generic(hw);
8285 /* Enable Ethernet CRC (required by MACsec offload) */
8286 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8287 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8288 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8290 /* Enable the TX and RX crypto engines */
8291 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8292 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8293 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8295 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8296 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8297 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8299 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8300 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8302 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8304 /* Enable SA lookup */
8305 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8306 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8307 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8308 IXGBE_LSECTXCTRL_AUTH;
8309 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8310 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8311 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8312 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8314 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8315 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8316 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8317 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8319 ctrl |= IXGBE_LSECRXCTRL_RP;
8321 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8322 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8324 /* Start the data paths */
8325 ixgbe_enable_sec_rx_path(hw);
8328 * As no ixgbe_enable_sec_rx_path equivalent is
8329 * implemented for tx in the base code, and we are
8330 * not allowed to modify the base code in DPDK, so
8331 * just call the hand-written one directly for now.
8333 ixgbe_enable_sec_tx_path_generic(hw);
8339 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8341 struct ixgbe_hw *hw;
8342 struct rte_eth_dev *dev;
8345 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8347 dev = &rte_eth_devices[port];
8349 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8352 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8354 /* Stop the data paths */
8355 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8359 * As no ixgbe_disable_sec_rx_path equivalent is
8360 * implemented for tx in the base code, and we are
8361 * not allowed to modify the base code in DPDK, so
8362 * just call the hand-written one directly for now.
8363 * The hardware support has been checked by
8364 * ixgbe_disable_sec_rx_path().
8366 ixgbe_disable_sec_tx_path_generic(hw);
8368 /* Disable the TX and RX crypto engines */
8369 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8370 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8371 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8373 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8374 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8375 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8377 /* Disable SA lookup */
8378 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8379 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8380 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8381 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8383 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8384 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8385 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8386 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8388 /* Start the data paths */
8389 ixgbe_enable_sec_rx_path(hw);
8392 * As no ixgbe_enable_sec_rx_path equivalent is
8393 * implemented for tx in the base code, and we are
8394 * not allowed to modify the base code in DPDK, so
8395 * just call the hand-written one directly for now.
8397 ixgbe_enable_sec_tx_path_generic(hw);
8403 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8405 struct ixgbe_hw *hw;
8406 struct rte_eth_dev *dev;
8409 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8411 dev = &rte_eth_devices[port];
8413 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8416 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8418 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8419 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8421 ctrl = mac[4] | (mac[5] << 8);
8422 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8428 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8430 struct ixgbe_hw *hw;
8431 struct rte_eth_dev *dev;
8434 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8436 dev = &rte_eth_devices[port];
8438 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8441 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8443 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8444 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8446 pi = rte_cpu_to_be_16(pi);
8447 ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8448 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8454 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8455 uint32_t pn, uint8_t *key)
8457 struct ixgbe_hw *hw;
8458 struct rte_eth_dev *dev;
8461 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8463 dev = &rte_eth_devices[port];
8465 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8468 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8470 if (idx != 0 && idx != 1)
8476 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8478 /* Set the PN and key */
8479 pn = rte_cpu_to_be_32(pn);
8481 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8483 for (i = 0; i < 4; i++) {
8484 ctrl = (key[i * 4 + 0] << 0) |
8485 (key[i * 4 + 1] << 8) |
8486 (key[i * 4 + 2] << 16) |
8487 (key[i * 4 + 3] << 24);
8488 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8491 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8493 for (i = 0; i < 4; i++) {
8494 ctrl = (key[i * 4 + 0] << 0) |
8495 (key[i * 4 + 1] << 8) |
8496 (key[i * 4 + 2] << 16) |
8497 (key[i * 4 + 3] << 24);
8498 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8502 /* Set AN and select the SA */
8503 ctrl = (an << idx * 2) | (idx << 4);
8504 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8510 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8511 uint32_t pn, uint8_t *key)
8513 struct ixgbe_hw *hw;
8514 struct rte_eth_dev *dev;
8517 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8519 dev = &rte_eth_devices[port];
8521 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8524 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8526 if (idx != 0 && idx != 1)
8533 pn = rte_cpu_to_be_32(pn);
8534 IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8537 for (i = 0; i < 4; i++) {
8538 ctrl = (key[i * 4 + 0] << 0) |
8539 (key[i * 4 + 1] << 8) |
8540 (key[i * 4 + 2] << 16) |
8541 (key[i * 4 + 3] << 24);
8542 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8545 /* Set the AN and validate the SA */
8546 ctrl = an | (1 << 2);
8547 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8552 /* restore n-tuple filter */
8554 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8556 struct ixgbe_filter_info *filter_info =
8557 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8558 struct ixgbe_5tuple_filter *node;
8560 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8561 ixgbe_inject_5tuple_filter(dev, node);
8565 /* restore ethernet type filter */
8567 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8569 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8570 struct ixgbe_filter_info *filter_info =
8571 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8574 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8575 if (filter_info->ethertype_mask & (1 << i)) {
8576 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8577 filter_info->ethertype_filters[i].etqf);
8578 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8579 filter_info->ethertype_filters[i].etqs);
8580 IXGBE_WRITE_FLUSH(hw);
8585 /* restore SYN filter */
8587 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8589 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8590 struct ixgbe_filter_info *filter_info =
8591 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8594 synqf = filter_info->syn_info;
8596 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8597 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8598 IXGBE_WRITE_FLUSH(hw);
8602 /* restore L2 tunnel filter */
8604 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8606 struct ixgbe_l2_tn_info *l2_tn_info =
8607 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8608 struct ixgbe_l2_tn_filter *node;
8609 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8611 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8612 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8613 l2_tn_conf.tunnel_id = node->key.tn_id;
8614 l2_tn_conf.pool = node->pool;
8615 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8620 ixgbe_filter_restore(struct rte_eth_dev *dev)
8622 ixgbe_ntuple_filter_restore(dev);
8623 ixgbe_ethertype_filter_restore(dev);
8624 ixgbe_syn_filter_restore(dev);
8625 ixgbe_fdir_filter_restore(dev);
8626 ixgbe_l2_tn_filter_restore(dev);
8632 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8634 struct ixgbe_l2_tn_info *l2_tn_info =
8635 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8636 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8638 if (l2_tn_info->e_tag_en)
8639 (void)ixgbe_e_tag_enable(hw);
8641 if (l2_tn_info->e_tag_fwd_en)
8642 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8644 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8647 /* remove all the n-tuple filters */
8649 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8651 struct ixgbe_filter_info *filter_info =
8652 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8653 struct ixgbe_5tuple_filter *p_5tuple;
8655 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8656 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8659 /* remove all the ether type filters */
8661 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8663 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8664 struct ixgbe_filter_info *filter_info =
8665 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8668 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8669 if (filter_info->ethertype_mask & (1 << i) &&
8670 !filter_info->ethertype_filters[i].conf) {
8671 (void)ixgbe_ethertype_filter_remove(filter_info,
8673 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8674 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8675 IXGBE_WRITE_FLUSH(hw);
8680 /* remove the SYN filter */
8682 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8684 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8685 struct ixgbe_filter_info *filter_info =
8686 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8688 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8689 filter_info->syn_info = 0;
8691 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8692 IXGBE_WRITE_FLUSH(hw);
8696 /* remove all the L2 tunnel filters */
8698 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8700 struct ixgbe_l2_tn_info *l2_tn_info =
8701 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8702 struct ixgbe_l2_tn_filter *l2_tn_filter;
8703 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8706 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8707 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8708 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8709 l2_tn_conf.pool = l2_tn_filter->pool;
8710 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8719 rte_pmd_ixgbe_set_tc_bw_alloc(uint8_t port,
8723 struct rte_eth_dev *dev;
8724 struct ixgbe_dcb_config *dcb_config;
8725 struct ixgbe_dcb_tc_config *tc;
8726 struct rte_eth_conf *eth_conf;
8727 struct ixgbe_bw_conf *bw_conf;
8732 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8734 dev = &rte_eth_devices[port];
8736 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8739 if (tc_num > IXGBE_DCB_MAX_TRAFFIC_CLASS) {
8740 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
8741 IXGBE_DCB_MAX_TRAFFIC_CLASS);
8745 dcb_config = IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
8746 bw_conf = IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
8747 eth_conf = &dev->data->dev_conf;
8749 if (eth_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
8750 nb_tcs = eth_conf->tx_adv_conf.dcb_tx_conf.nb_tcs;
8751 } else if (eth_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
8752 if (eth_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools ==
8761 if (nb_tcs != tc_num) {
8763 "Weight should be set for all %d enabled TCs.",
8769 for (i = 0; i < nb_tcs; i++)
8770 sum += bw_weight[i];
8773 "The summary of the TC weight should be 100.");
8777 for (i = 0; i < nb_tcs; i++) {
8778 tc = &dcb_config->tc_config[i];
8779 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = bw_weight[i];
8781 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
8782 tc = &dcb_config->tc_config[i];
8783 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
8786 bw_conf->tc_num = nb_tcs;
8791 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8792 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8793 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8794 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8795 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8796 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");