4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define IXGBE_TIMINCA_16NS_SHIFT 24
130 #define IXGBE_TIMINCA_INCVALUE 16000000
131 #define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
132 | IXGBE_TIMINCA_INCVALUE)
134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
147 int wait_to_complete);
148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
149 struct rte_eth_stats *stats);
150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
151 struct rte_eth_xstats *xstats, unsigned n);
152 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
153 struct rte_eth_xstats *xstats, unsigned n);
154 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
155 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
156 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
160 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
161 struct rte_eth_dev_info *dev_info);
162 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
163 struct rte_eth_dev_info *dev_info);
164 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
166 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
167 uint16_t vlan_id, int on);
168 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
169 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
170 uint16_t queue, bool on);
171 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
173 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
174 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
175 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
176 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
177 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
179 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
180 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
181 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
182 struct rte_eth_fc_conf *fc_conf);
183 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
184 struct rte_eth_fc_conf *fc_conf);
185 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
186 struct rte_eth_pfc_conf *pfc_conf);
187 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
188 struct rte_eth_rss_reta_entry64 *reta_conf,
190 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
191 struct rte_eth_rss_reta_entry64 *reta_conf,
193 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
194 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
195 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
196 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
197 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
198 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
200 static void ixgbe_dev_interrupt_delayed_handler(void *param);
201 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
202 uint32_t index, uint32_t pool);
203 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
204 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
205 struct ether_addr *mac_addr);
206 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
208 /* For Virtual Function support */
209 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
210 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
211 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
212 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
213 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
214 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
215 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
216 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
217 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
218 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
219 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
220 struct rte_eth_stats *stats);
221 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
222 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
223 uint16_t vlan_id, int on);
224 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
225 uint16_t queue, int on);
226 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
227 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
228 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
230 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
232 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
234 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
235 uint8_t queue, uint8_t msix_vector);
236 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
238 /* For Eth VMDQ APIs support */
239 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
240 ether_addr* mac_addr,uint8_t on);
241 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
242 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
243 uint16_t rx_mask, uint8_t on);
244 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
245 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
246 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
247 uint64_t pool_mask,uint8_t vlan_on);
248 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
249 struct rte_eth_mirror_conf *mirror_conf,
250 uint8_t rule_id, uint8_t on);
251 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
253 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
255 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
257 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
258 uint8_t queue, uint8_t msix_vector);
259 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
261 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
262 uint16_t queue_idx, uint16_t tx_rate);
263 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
264 uint16_t tx_rate, uint64_t q_msk);
266 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
267 struct ether_addr *mac_addr,
268 uint32_t index, uint32_t pool);
269 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
270 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
271 struct ether_addr *mac_addr);
272 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
273 struct rte_eth_syn_filter *filter,
275 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
276 struct rte_eth_syn_filter *filter);
277 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
278 enum rte_filter_op filter_op,
280 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
281 struct ixgbe_5tuple_filter *filter);
282 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
283 struct ixgbe_5tuple_filter *filter);
284 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
285 struct rte_eth_ntuple_filter *filter,
287 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
288 enum rte_filter_op filter_op,
290 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
291 struct rte_eth_ntuple_filter *filter);
292 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
293 struct rte_eth_ethertype_filter *filter,
295 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
296 enum rte_filter_op filter_op,
298 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
299 struct rte_eth_ethertype_filter *filter);
300 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
301 enum rte_filter_type filter_type,
302 enum rte_filter_op filter_op,
304 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
306 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
307 struct ether_addr *mc_addr_set,
308 uint32_t nb_mc_addr);
309 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
310 struct rte_eth_dcb_info *dcb_info);
312 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
313 static int ixgbe_get_regs(struct rte_eth_dev *dev,
314 struct rte_dev_reg_info *regs);
315 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
316 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
317 struct rte_dev_eeprom_info *eeprom);
318 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
319 struct rte_dev_eeprom_info *eeprom);
321 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
322 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
323 struct rte_dev_reg_info *regs);
325 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
326 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
327 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
328 struct timespec *timestamp,
330 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
331 struct timespec *timestamp);
334 * Define VF Stats MACRO for Non "cleared on read" register
336 #define UPDATE_VF_STAT(reg, last, cur) \
338 uint32_t latest = IXGBE_READ_REG(hw, reg); \
339 cur += (latest - last) & UINT_MAX; \
343 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
345 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
346 u64 new_msb = IXGBE_READ_REG(hw, msb); \
347 u64 latest = ((new_msb << 32) | new_lsb); \
348 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
352 #define IXGBE_SET_HWSTRIP(h, q) do{\
353 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
354 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
355 (h)->bitmap[idx] |= 1 << bit;\
358 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
359 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
360 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
361 (h)->bitmap[idx] &= ~(1 << bit);\
364 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
365 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
366 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
367 (r) = (h)->bitmap[idx] >> bit & 1;\
371 * The set of PCI devices this driver supports
373 static const struct rte_pci_id pci_id_ixgbe_map[] = {
375 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
376 #include "rte_pci_dev_ids.h"
378 { .vendor_id = 0, /* sentinel */ },
383 * The set of PCI devices this driver supports (for 82599 VF)
385 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
387 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
388 #include "rte_pci_dev_ids.h"
389 { .vendor_id = 0, /* sentinel */ },
393 static const struct rte_eth_desc_lim rx_desc_lim = {
394 .nb_max = IXGBE_MAX_RING_DESC,
395 .nb_min = IXGBE_MIN_RING_DESC,
396 .nb_align = IXGBE_RXD_ALIGN,
399 static const struct rte_eth_desc_lim tx_desc_lim = {
400 .nb_max = IXGBE_MAX_RING_DESC,
401 .nb_min = IXGBE_MIN_RING_DESC,
402 .nb_align = IXGBE_TXD_ALIGN,
405 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
406 .dev_configure = ixgbe_dev_configure,
407 .dev_start = ixgbe_dev_start,
408 .dev_stop = ixgbe_dev_stop,
409 .dev_set_link_up = ixgbe_dev_set_link_up,
410 .dev_set_link_down = ixgbe_dev_set_link_down,
411 .dev_close = ixgbe_dev_close,
412 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
413 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
414 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
415 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
416 .link_update = ixgbe_dev_link_update,
417 .stats_get = ixgbe_dev_stats_get,
418 .xstats_get = ixgbe_dev_xstats_get,
419 .stats_reset = ixgbe_dev_stats_reset,
420 .xstats_reset = ixgbe_dev_xstats_reset,
421 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
422 .dev_infos_get = ixgbe_dev_info_get,
423 .mtu_set = ixgbe_dev_mtu_set,
424 .vlan_filter_set = ixgbe_vlan_filter_set,
425 .vlan_tpid_set = ixgbe_vlan_tpid_set,
426 .vlan_offload_set = ixgbe_vlan_offload_set,
427 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
428 .rx_queue_start = ixgbe_dev_rx_queue_start,
429 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
430 .tx_queue_start = ixgbe_dev_tx_queue_start,
431 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
432 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
433 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
434 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
435 .rx_queue_release = ixgbe_dev_rx_queue_release,
436 .rx_queue_count = ixgbe_dev_rx_queue_count,
437 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
438 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
439 .tx_queue_release = ixgbe_dev_tx_queue_release,
440 .dev_led_on = ixgbe_dev_led_on,
441 .dev_led_off = ixgbe_dev_led_off,
442 .flow_ctrl_get = ixgbe_flow_ctrl_get,
443 .flow_ctrl_set = ixgbe_flow_ctrl_set,
444 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
445 .mac_addr_add = ixgbe_add_rar,
446 .mac_addr_remove = ixgbe_remove_rar,
447 .mac_addr_set = ixgbe_set_default_mac_addr,
448 .uc_hash_table_set = ixgbe_uc_hash_table_set,
449 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
450 .mirror_rule_set = ixgbe_mirror_rule_set,
451 .mirror_rule_reset = ixgbe_mirror_rule_reset,
452 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
453 .set_vf_rx = ixgbe_set_pool_rx,
454 .set_vf_tx = ixgbe_set_pool_tx,
455 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
456 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
457 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
458 .reta_update = ixgbe_dev_rss_reta_update,
459 .reta_query = ixgbe_dev_rss_reta_query,
460 #ifdef RTE_NIC_BYPASS
461 .bypass_init = ixgbe_bypass_init,
462 .bypass_state_set = ixgbe_bypass_state_store,
463 .bypass_state_show = ixgbe_bypass_state_show,
464 .bypass_event_set = ixgbe_bypass_event_store,
465 .bypass_event_show = ixgbe_bypass_event_show,
466 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
467 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
468 .bypass_ver_show = ixgbe_bypass_ver_show,
469 .bypass_wd_reset = ixgbe_bypass_wd_reset,
470 #endif /* RTE_NIC_BYPASS */
471 .rss_hash_update = ixgbe_dev_rss_hash_update,
472 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
473 .filter_ctrl = ixgbe_dev_filter_ctrl,
474 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
475 .rxq_info_get = ixgbe_rxq_info_get,
476 .txq_info_get = ixgbe_txq_info_get,
477 .timesync_enable = ixgbe_timesync_enable,
478 .timesync_disable = ixgbe_timesync_disable,
479 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
480 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
481 .get_reg_length = ixgbe_get_reg_length,
482 .get_reg = ixgbe_get_regs,
483 .get_eeprom_length = ixgbe_get_eeprom_length,
484 .get_eeprom = ixgbe_get_eeprom,
485 .set_eeprom = ixgbe_set_eeprom,
486 .get_dcb_info = ixgbe_dev_get_dcb_info,
490 * dev_ops for virtual function, bare necessities for basic vf
491 * operation have been implemented
493 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
494 .dev_configure = ixgbevf_dev_configure,
495 .dev_start = ixgbevf_dev_start,
496 .dev_stop = ixgbevf_dev_stop,
497 .link_update = ixgbe_dev_link_update,
498 .stats_get = ixgbevf_dev_stats_get,
499 .xstats_get = ixgbevf_dev_xstats_get,
500 .stats_reset = ixgbevf_dev_stats_reset,
501 .xstats_reset = ixgbevf_dev_stats_reset,
502 .dev_close = ixgbevf_dev_close,
503 .dev_infos_get = ixgbevf_dev_info_get,
504 .mtu_set = ixgbevf_dev_set_mtu,
505 .vlan_filter_set = ixgbevf_vlan_filter_set,
506 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
507 .vlan_offload_set = ixgbevf_vlan_offload_set,
508 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
509 .rx_queue_release = ixgbe_dev_rx_queue_release,
510 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
511 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
512 .tx_queue_release = ixgbe_dev_tx_queue_release,
513 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
514 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
515 .mac_addr_add = ixgbevf_add_mac_addr,
516 .mac_addr_remove = ixgbevf_remove_mac_addr,
517 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
518 .rxq_info_get = ixgbe_rxq_info_get,
519 .txq_info_get = ixgbe_txq_info_get,
520 .mac_addr_set = ixgbevf_set_default_mac_addr,
521 .get_reg_length = ixgbevf_get_reg_length,
522 .get_reg = ixgbevf_get_regs,
523 .reta_update = ixgbe_dev_rss_reta_update,
524 .reta_query = ixgbe_dev_rss_reta_query,
525 .rss_hash_update = ixgbe_dev_rss_hash_update,
526 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
529 /* store statistics names and its offset in stats structure */
530 struct rte_ixgbe_xstats_name_off {
531 char name[RTE_ETH_XSTATS_NAME_SIZE];
535 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
536 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
537 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
538 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
539 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
540 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
541 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
542 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
543 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
544 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
545 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
546 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
547 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
548 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
549 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
550 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
552 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
554 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
555 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
556 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
557 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
558 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
559 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
560 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
561 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
562 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
563 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
564 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
565 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
566 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
567 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
568 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
569 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
570 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
572 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
574 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
575 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
576 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
577 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
579 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
581 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
583 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
585 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
587 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
589 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
592 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
593 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
594 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
596 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
597 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
598 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
599 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
600 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
602 {"rx_fcoe_no_direct_data_placement_ext_buff",
603 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
605 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
607 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
609 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
611 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
613 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
616 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
617 sizeof(rte_ixgbe_stats_strings[0]))
619 /* Per-queue statistics */
620 #define IXBGE_NB_8_PER_Q_STATS (8 * 7)
621 #define IXBGE_NB_16_PER_Q_STATS (16 * 5)
622 #define IXGBE_NB_Q_STATS (IXBGE_NB_8_PER_Q_STATS + IXBGE_NB_16_PER_Q_STATS)
624 #define IXGBE_NB_XSTATS (IXGBE_NB_HW_STATS + IXGBE_NB_Q_STATS)
626 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
627 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
630 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
631 sizeof(rte_ixgbevf_stats_strings[0]))
634 * Atomically reads the link status information from global
635 * structure rte_eth_dev.
638 * - Pointer to the structure rte_eth_dev to read from.
639 * - Pointer to the buffer to be saved with the link status.
642 * - On success, zero.
643 * - On failure, negative value.
646 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
647 struct rte_eth_link *link)
649 struct rte_eth_link *dst = link;
650 struct rte_eth_link *src = &(dev->data->dev_link);
652 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
653 *(uint64_t *)src) == 0)
660 * Atomically writes the link status information into global
661 * structure rte_eth_dev.
664 * - Pointer to the structure rte_eth_dev to read from.
665 * - Pointer to the buffer to be saved with the link status.
668 * - On success, zero.
669 * - On failure, negative value.
672 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
673 struct rte_eth_link *link)
675 struct rte_eth_link *dst = &(dev->data->dev_link);
676 struct rte_eth_link *src = link;
678 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
679 *(uint64_t *)src) == 0)
686 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
689 ixgbe_is_sfp(struct ixgbe_hw *hw)
691 switch (hw->phy.type) {
692 case ixgbe_phy_sfp_avago:
693 case ixgbe_phy_sfp_ftl:
694 case ixgbe_phy_sfp_intel:
695 case ixgbe_phy_sfp_unknown:
696 case ixgbe_phy_sfp_passive_tyco:
697 case ixgbe_phy_sfp_passive_unknown:
704 static inline int32_t
705 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
710 status = ixgbe_reset_hw(hw);
712 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
713 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
714 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
715 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
716 IXGBE_WRITE_FLUSH(hw);
722 ixgbe_enable_intr(struct rte_eth_dev *dev)
724 struct ixgbe_interrupt *intr =
725 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
726 struct ixgbe_hw *hw =
727 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
729 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
730 IXGBE_WRITE_FLUSH(hw);
734 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
737 ixgbe_disable_intr(struct ixgbe_hw *hw)
739 PMD_INIT_FUNC_TRACE();
741 if (hw->mac.type == ixgbe_mac_82598EB) {
742 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
744 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
745 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
746 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
748 IXGBE_WRITE_FLUSH(hw);
752 * This function resets queue statistics mapping registers.
753 * From Niantic datasheet, Initialization of Statistics section:
754 * "...if software requires the queue counters, the RQSMR and TQSM registers
755 * must be re-programmed following a device reset.
758 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
762 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
763 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
764 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
770 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
775 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
776 #define NB_QMAP_FIELDS_PER_QSM_REG 4
777 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
779 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
780 struct ixgbe_stat_mapping_registers *stat_mappings =
781 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
782 uint32_t qsmr_mask = 0;
783 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
787 if ((hw->mac.type != ixgbe_mac_82599EB) &&
788 (hw->mac.type != ixgbe_mac_X540) &&
789 (hw->mac.type != ixgbe_mac_X550) &&
790 (hw->mac.type != ixgbe_mac_X550EM_x))
793 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
794 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
797 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
798 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
799 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
802 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
804 /* Now clear any previous stat_idx set */
805 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
807 stat_mappings->tqsm[n] &= ~clearing_mask;
809 stat_mappings->rqsmr[n] &= ~clearing_mask;
811 q_map = (uint32_t)stat_idx;
812 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
813 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
815 stat_mappings->tqsm[n] |= qsmr_mask;
817 stat_mappings->rqsmr[n] |= qsmr_mask;
819 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
820 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
822 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
823 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
825 /* Now write the mapping in the appropriate register */
827 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
828 stat_mappings->rqsmr[n], n);
829 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
832 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
833 stat_mappings->tqsm[n], n);
834 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
840 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
842 struct ixgbe_stat_mapping_registers *stat_mappings =
843 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
844 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
847 /* write whatever was in stat mapping table to the NIC */
848 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
850 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
853 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
858 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
861 struct ixgbe_dcb_tc_config *tc;
862 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
864 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
865 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
866 for (i = 0; i < dcb_max_tc; i++) {
867 tc = &dcb_config->tc_config[i];
868 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
869 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
870 (uint8_t)(100/dcb_max_tc + (i & 1));
871 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
872 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
873 (uint8_t)(100/dcb_max_tc + (i & 1));
874 tc->pfc = ixgbe_dcb_pfc_disabled;
877 /* Initialize default user to priority mapping, UPx->TC0 */
878 tc = &dcb_config->tc_config[0];
879 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
880 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
881 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
882 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
883 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
885 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
886 dcb_config->pfc_mode_enable = false;
887 dcb_config->vt_mode = true;
888 dcb_config->round_robin_enable = false;
889 /* support all DCB capabilities in 82599 */
890 dcb_config->support.capabilities = 0xFF;
892 /*we only support 4 Tcs for X540, X550 */
893 if (hw->mac.type == ixgbe_mac_X540 ||
894 hw->mac.type == ixgbe_mac_X550 ||
895 hw->mac.type == ixgbe_mac_X550EM_x) {
896 dcb_config->num_tcs.pg_tcs = 4;
897 dcb_config->num_tcs.pfc_tcs = 4;
902 * Ensure that all locks are released before first NVM or PHY access
905 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
910 * Phy lock should not fail in this early stage. If this is the case,
911 * it is due to an improper exit of the application.
912 * So force the release of the faulty lock. Release of common lock
913 * is done automatically by swfw_sync function.
915 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
916 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
917 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
919 ixgbe_release_swfw_semaphore(hw, mask);
922 * These ones are more tricky since they are common to all ports; but
923 * swfw_sync retries last long enough (1s) to be almost sure that if
924 * lock can not be taken it is due to an improper lock of the
927 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
928 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
929 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
931 ixgbe_release_swfw_semaphore(hw, mask);
935 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
936 * It returns 0 on success.
939 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
941 struct rte_pci_device *pci_dev;
942 struct ixgbe_hw *hw =
943 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
944 struct ixgbe_vfta * shadow_vfta =
945 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
946 struct ixgbe_hwstrip *hwstrip =
947 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
948 struct ixgbe_dcb_config *dcb_config =
949 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
950 struct ixgbe_filter_info *filter_info =
951 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
956 PMD_INIT_FUNC_TRACE();
958 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
959 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
960 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
963 * For secondary processes, we don't initialise any further as primary
964 * has already done this work. Only check we don't need a different
965 * RX and TX function.
967 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
968 struct ixgbe_tx_queue *txq;
969 /* TX queue function in primary, set by last queue initialized
970 * Tx queue may not initialized by primary process */
971 if (eth_dev->data->tx_queues) {
972 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
973 ixgbe_set_tx_function(eth_dev, txq);
975 /* Use default TX function if we get here */
976 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
977 "Using default TX function.");
980 ixgbe_set_rx_function(eth_dev);
984 pci_dev = eth_dev->pci_dev;
986 rte_eth_copy_pci_info(eth_dev, pci_dev);
988 /* Vendor and Device ID need to be set before init of shared code */
989 hw->device_id = pci_dev->id.device_id;
990 hw->vendor_id = pci_dev->id.vendor_id;
991 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
992 hw->allow_unsupported_sfp = 1;
994 /* Initialize the shared code (base driver) */
995 #ifdef RTE_NIC_BYPASS
996 diag = ixgbe_bypass_init_shared_code(hw);
998 diag = ixgbe_init_shared_code(hw);
999 #endif /* RTE_NIC_BYPASS */
1001 if (diag != IXGBE_SUCCESS) {
1002 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1006 /* pick up the PCI bus settings for reporting later */
1007 ixgbe_get_bus_info(hw);
1009 /* Unlock any pending hardware semaphore */
1010 ixgbe_swfw_lock_reset(hw);
1012 /* Initialize DCB configuration*/
1013 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1014 ixgbe_dcb_init(hw,dcb_config);
1015 /* Get Hardware Flow Control setting */
1016 hw->fc.requested_mode = ixgbe_fc_full;
1017 hw->fc.current_mode = ixgbe_fc_full;
1018 hw->fc.pause_time = IXGBE_FC_PAUSE;
1019 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1020 hw->fc.low_water[i] = IXGBE_FC_LO;
1021 hw->fc.high_water[i] = IXGBE_FC_HI;
1023 hw->fc.send_xon = 1;
1025 /* Make sure we have a good EEPROM before we read from it */
1026 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1027 if (diag != IXGBE_SUCCESS) {
1028 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1032 #ifdef RTE_NIC_BYPASS
1033 diag = ixgbe_bypass_init_hw(hw);
1035 diag = ixgbe_init_hw(hw);
1036 #endif /* RTE_NIC_BYPASS */
1039 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1040 * is called too soon after the kernel driver unbinding/binding occurs.
1041 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1042 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1043 * also called. See ixgbe_identify_phy_82599(). The reason for the
1044 * failure is not known, and only occuts when virtualisation features
1045 * are disabled in the bios. A delay of 100ms was found to be enough by
1046 * trial-and-error, and is doubled to be safe.
1048 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1050 diag = ixgbe_init_hw(hw);
1053 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1054 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1055 "LOM. Please be aware there may be issues associated "
1056 "with your hardware.");
1057 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1058 "please contact your Intel or hardware representative "
1059 "who provided you with this hardware.");
1060 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1061 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1063 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1067 /* Reset the hw statistics */
1068 ixgbe_dev_stats_reset(eth_dev);
1070 /* disable interrupt */
1071 ixgbe_disable_intr(hw);
1073 /* reset mappings for queue statistics hw counters*/
1074 ixgbe_reset_qstat_mappings(hw);
1076 /* Allocate memory for storing MAC addresses */
1077 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1078 hw->mac.num_rar_entries, 0);
1079 if (eth_dev->data->mac_addrs == NULL) {
1081 "Failed to allocate %u bytes needed to store "
1083 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1086 /* Copy the permanent MAC address */
1087 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1088 ð_dev->data->mac_addrs[0]);
1090 /* Allocate memory for storing hash filter MAC addresses */
1091 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1092 IXGBE_VMDQ_NUM_UC_MAC, 0);
1093 if (eth_dev->data->hash_mac_addrs == NULL) {
1095 "Failed to allocate %d bytes needed to store MAC addresses",
1096 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1100 /* initialize the vfta */
1101 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1103 /* initialize the hw strip bitmap*/
1104 memset(hwstrip, 0, sizeof(*hwstrip));
1106 /* initialize PF if max_vfs not zero */
1107 ixgbe_pf_host_init(eth_dev);
1109 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1110 /* let hardware know driver is loaded */
1111 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1112 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1113 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1114 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1115 IXGBE_WRITE_FLUSH(hw);
1117 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1118 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1119 (int) hw->mac.type, (int) hw->phy.type,
1120 (int) hw->phy.sfp_type);
1122 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1123 (int) hw->mac.type, (int) hw->phy.type);
1125 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1126 eth_dev->data->port_id, pci_dev->id.vendor_id,
1127 pci_dev->id.device_id);
1129 /* enable support intr */
1130 ixgbe_enable_intr(eth_dev);
1132 /* initialize 5tuple filter list */
1133 TAILQ_INIT(&filter_info->fivetuple_list);
1134 memset(filter_info->fivetuple_mask, 0,
1135 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1141 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1143 struct rte_pci_device *pci_dev;
1144 struct ixgbe_hw *hw;
1146 PMD_INIT_FUNC_TRACE();
1148 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1151 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1152 pci_dev = eth_dev->pci_dev;
1154 if (hw->adapter_stopped == 0)
1155 ixgbe_dev_close(eth_dev);
1157 eth_dev->dev_ops = NULL;
1158 eth_dev->rx_pkt_burst = NULL;
1159 eth_dev->tx_pkt_burst = NULL;
1161 /* Unlock any pending hardware semaphore */
1162 ixgbe_swfw_lock_reset(hw);
1164 /* disable uio intr before callback unregister */
1165 rte_intr_disable(&(pci_dev->intr_handle));
1166 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1167 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1169 /* uninitialize PF if max_vfs not zero */
1170 ixgbe_pf_host_uninit(eth_dev);
1172 rte_free(eth_dev->data->mac_addrs);
1173 eth_dev->data->mac_addrs = NULL;
1175 rte_free(eth_dev->data->hash_mac_addrs);
1176 eth_dev->data->hash_mac_addrs = NULL;
1182 * Negotiate mailbox API version with the PF.
1183 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1184 * Then we try to negotiate starting with the most recent one.
1185 * If all negotiation attempts fail, then we will proceed with
1186 * the default one (ixgbe_mbox_api_10).
1189 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1193 /* start with highest supported, proceed down */
1194 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1200 i != RTE_DIM(sup_ver) &&
1201 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1207 generate_random_mac_addr(struct ether_addr *mac_addr)
1211 /* Set Organizationally Unique Identifier (OUI) prefix. */
1212 mac_addr->addr_bytes[0] = 0x00;
1213 mac_addr->addr_bytes[1] = 0x09;
1214 mac_addr->addr_bytes[2] = 0xC0;
1215 /* Force indication of locally assigned MAC address. */
1216 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1217 /* Generate the last 3 bytes of the MAC address with a random number. */
1218 random = rte_rand();
1219 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1223 * Virtual Function device init
1226 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1230 struct rte_pci_device *pci_dev;
1231 struct ixgbe_hw *hw =
1232 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1233 struct ixgbe_vfta * shadow_vfta =
1234 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1235 struct ixgbe_hwstrip *hwstrip =
1236 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1237 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1239 PMD_INIT_FUNC_TRACE();
1241 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1242 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1243 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1245 /* for secondary processes, we don't initialise any further as primary
1246 * has already done this work. Only check we don't need a different
1248 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1249 if (eth_dev->data->scattered_rx)
1250 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1254 pci_dev = eth_dev->pci_dev;
1256 rte_eth_copy_pci_info(eth_dev, pci_dev);
1258 hw->device_id = pci_dev->id.device_id;
1259 hw->vendor_id = pci_dev->id.vendor_id;
1260 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1262 /* initialize the vfta */
1263 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1265 /* initialize the hw strip bitmap*/
1266 memset(hwstrip, 0, sizeof(*hwstrip));
1268 /* Initialize the shared code (base driver) */
1269 diag = ixgbe_init_shared_code(hw);
1270 if (diag != IXGBE_SUCCESS) {
1271 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1275 /* init_mailbox_params */
1276 hw->mbx.ops.init_params(hw);
1278 /* Reset the hw statistics */
1279 ixgbevf_dev_stats_reset(eth_dev);
1281 /* Disable the interrupts for VF */
1282 ixgbevf_intr_disable(hw);
1284 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1285 diag = hw->mac.ops.reset_hw(hw);
1288 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1289 * the underlying PF driver has not assigned a MAC address to the VF.
1290 * In this case, assign a random MAC address.
1292 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1293 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1297 /* negotiate mailbox API version to use with the PF. */
1298 ixgbevf_negotiate_api(hw);
1300 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1301 ixgbevf_get_queues(hw, &tcs, &tc);
1303 /* Allocate memory for storing MAC addresses */
1304 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1305 hw->mac.num_rar_entries, 0);
1306 if (eth_dev->data->mac_addrs == NULL) {
1308 "Failed to allocate %u bytes needed to store "
1310 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1314 /* Generate a random MAC address, if none was assigned by PF. */
1315 if (is_zero_ether_addr(perm_addr)) {
1316 generate_random_mac_addr(perm_addr);
1317 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1319 rte_free(eth_dev->data->mac_addrs);
1320 eth_dev->data->mac_addrs = NULL;
1323 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1324 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1325 "%02x:%02x:%02x:%02x:%02x:%02x",
1326 perm_addr->addr_bytes[0],
1327 perm_addr->addr_bytes[1],
1328 perm_addr->addr_bytes[2],
1329 perm_addr->addr_bytes[3],
1330 perm_addr->addr_bytes[4],
1331 perm_addr->addr_bytes[5]);
1334 /* Copy the permanent MAC address */
1335 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1337 /* reset the hardware with the new settings */
1338 diag = hw->mac.ops.start_hw(hw);
1344 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1348 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1349 eth_dev->data->port_id, pci_dev->id.vendor_id,
1350 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1355 /* Virtual Function device uninit */
1358 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1360 struct ixgbe_hw *hw;
1363 PMD_INIT_FUNC_TRACE();
1365 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1368 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1370 if (hw->adapter_stopped == 0)
1371 ixgbevf_dev_close(eth_dev);
1373 eth_dev->dev_ops = NULL;
1374 eth_dev->rx_pkt_burst = NULL;
1375 eth_dev->tx_pkt_burst = NULL;
1377 /* Disable the interrupts for VF */
1378 ixgbevf_intr_disable(hw);
1380 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1381 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1382 eth_dev->data->rx_queues[i] = NULL;
1384 eth_dev->data->nb_rx_queues = 0;
1386 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1387 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1388 eth_dev->data->tx_queues[i] = NULL;
1390 eth_dev->data->nb_tx_queues = 0;
1392 rte_free(eth_dev->data->mac_addrs);
1393 eth_dev->data->mac_addrs = NULL;
1398 static struct eth_driver rte_ixgbe_pmd = {
1400 .name = "rte_ixgbe_pmd",
1401 .id_table = pci_id_ixgbe_map,
1402 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1403 RTE_PCI_DRV_DETACHABLE,
1405 .eth_dev_init = eth_ixgbe_dev_init,
1406 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1407 .dev_private_size = sizeof(struct ixgbe_adapter),
1411 * virtual function driver struct
1413 static struct eth_driver rte_ixgbevf_pmd = {
1415 .name = "rte_ixgbevf_pmd",
1416 .id_table = pci_id_ixgbevf_map,
1417 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1419 .eth_dev_init = eth_ixgbevf_dev_init,
1420 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1421 .dev_private_size = sizeof(struct ixgbe_adapter),
1425 * Driver initialization routine.
1426 * Invoked once at EAL init time.
1427 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1430 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1432 PMD_INIT_FUNC_TRACE();
1434 rte_eth_driver_register(&rte_ixgbe_pmd);
1439 * VF Driver initialization routine.
1440 * Invoked one at EAL init time.
1441 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1444 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1446 PMD_INIT_FUNC_TRACE();
1448 rte_eth_driver_register(&rte_ixgbevf_pmd);
1453 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1455 struct ixgbe_hw *hw =
1456 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1457 struct ixgbe_vfta * shadow_vfta =
1458 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1463 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1464 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1465 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1470 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1472 /* update local VFTA copy */
1473 shadow_vfta->vfta[vid_idx] = vfta;
1479 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1482 ixgbe_vlan_hw_strip_enable(dev, queue);
1484 ixgbe_vlan_hw_strip_disable(dev, queue);
1488 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1490 struct ixgbe_hw *hw =
1491 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1493 /* Only the high 16-bits is valid */
1494 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1498 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1500 struct ixgbe_hw *hw =
1501 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504 PMD_INIT_FUNC_TRACE();
1506 /* Filter Table Disable */
1507 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1508 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1510 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1514 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1516 struct ixgbe_hw *hw =
1517 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518 struct ixgbe_vfta * shadow_vfta =
1519 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1523 PMD_INIT_FUNC_TRACE();
1525 /* Filter Table Enable */
1526 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1527 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1528 vlnctrl |= IXGBE_VLNCTRL_VFE;
1530 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1532 /* write whatever is in local vfta copy */
1533 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1534 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1538 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1540 struct ixgbe_hwstrip *hwstrip =
1541 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1543 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1547 IXGBE_SET_HWSTRIP(hwstrip, queue);
1549 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1553 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1555 struct ixgbe_hw *hw =
1556 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1559 PMD_INIT_FUNC_TRACE();
1561 if (hw->mac.type == ixgbe_mac_82598EB) {
1562 /* No queue level support */
1563 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1567 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1568 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1569 ctrl &= ~IXGBE_RXDCTL_VME;
1570 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1572 /* record those setting for HW strip per queue */
1573 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1577 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1579 struct ixgbe_hw *hw =
1580 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1583 PMD_INIT_FUNC_TRACE();
1585 if (hw->mac.type == ixgbe_mac_82598EB) {
1586 /* No queue level supported */
1587 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1591 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1592 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1593 ctrl |= IXGBE_RXDCTL_VME;
1594 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1596 /* record those setting for HW strip per queue */
1597 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1601 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1603 struct ixgbe_hw *hw =
1604 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608 PMD_INIT_FUNC_TRACE();
1610 if (hw->mac.type == ixgbe_mac_82598EB) {
1611 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1612 ctrl &= ~IXGBE_VLNCTRL_VME;
1613 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1616 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1617 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1618 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1619 ctrl &= ~IXGBE_RXDCTL_VME;
1620 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1622 /* record those setting for HW strip per queue */
1623 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1629 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1631 struct ixgbe_hw *hw =
1632 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636 PMD_INIT_FUNC_TRACE();
1638 if (hw->mac.type == ixgbe_mac_82598EB) {
1639 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1640 ctrl |= IXGBE_VLNCTRL_VME;
1641 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1644 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1645 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1646 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1647 ctrl |= IXGBE_RXDCTL_VME;
1648 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1650 /* record those setting for HW strip per queue */
1651 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1657 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1659 struct ixgbe_hw *hw =
1660 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663 PMD_INIT_FUNC_TRACE();
1665 /* DMATXCTRL: Geric Double VLAN Disable */
1666 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1667 ctrl &= ~IXGBE_DMATXCTL_GDV;
1668 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1670 /* CTRL_EXT: Global Double VLAN Disable */
1671 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1672 ctrl &= ~IXGBE_EXTENDED_VLAN;
1673 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1678 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1680 struct ixgbe_hw *hw =
1681 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684 PMD_INIT_FUNC_TRACE();
1686 /* DMATXCTRL: Geric Double VLAN Enable */
1687 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1688 ctrl |= IXGBE_DMATXCTL_GDV;
1689 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1691 /* CTRL_EXT: Global Double VLAN Enable */
1692 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1693 ctrl |= IXGBE_EXTENDED_VLAN;
1694 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1697 * VET EXT field in the EXVET register = 0x8100 by default
1698 * So no need to change. Same to VT field of DMATXCTL register
1703 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1705 if(mask & ETH_VLAN_STRIP_MASK){
1706 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1707 ixgbe_vlan_hw_strip_enable_all(dev);
1709 ixgbe_vlan_hw_strip_disable_all(dev);
1712 if(mask & ETH_VLAN_FILTER_MASK){
1713 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1714 ixgbe_vlan_hw_filter_enable(dev);
1716 ixgbe_vlan_hw_filter_disable(dev);
1719 if(mask & ETH_VLAN_EXTEND_MASK){
1720 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1721 ixgbe_vlan_hw_extend_enable(dev);
1723 ixgbe_vlan_hw_extend_disable(dev);
1728 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1730 struct ixgbe_hw *hw =
1731 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1733 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1734 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1735 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1739 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1744 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1747 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1753 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1754 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1760 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1762 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1763 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1764 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1766 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1767 /* check multi-queue mode */
1768 switch (dev_conf->rxmode.mq_mode) {
1769 case ETH_MQ_RX_VMDQ_DCB:
1770 case ETH_MQ_RX_VMDQ_DCB_RSS:
1771 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1772 PMD_INIT_LOG(ERR, "SRIOV active,"
1773 " unsupported mq_mode rx %d.",
1774 dev_conf->rxmode.mq_mode);
1777 case ETH_MQ_RX_VMDQ_RSS:
1778 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1779 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1780 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1781 PMD_INIT_LOG(ERR, "SRIOV is active,"
1782 " invalid queue number"
1783 " for VMDQ RSS, allowed"
1784 " value are 1, 2 or 4.");
1788 case ETH_MQ_RX_VMDQ_ONLY:
1789 case ETH_MQ_RX_NONE:
1790 /* if nothing mq mode configure, use default scheme */
1791 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1792 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1793 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1795 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1796 /* SRIOV only works in VMDq enable mode */
1797 PMD_INIT_LOG(ERR, "SRIOV is active,"
1798 " wrong mq_mode rx %d.",
1799 dev_conf->rxmode.mq_mode);
1803 switch (dev_conf->txmode.mq_mode) {
1804 case ETH_MQ_TX_VMDQ_DCB:
1805 /* DCB VMDQ in SRIOV mode, not implement yet */
1806 PMD_INIT_LOG(ERR, "SRIOV is active,"
1807 " unsupported VMDQ mq_mode tx %d.",
1808 dev_conf->txmode.mq_mode);
1810 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1811 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1815 /* check valid queue number */
1816 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1817 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1818 PMD_INIT_LOG(ERR, "SRIOV is active,"
1819 " queue number must less equal to %d.",
1820 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1824 /* check configuration for vmdb+dcb mode */
1825 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1826 const struct rte_eth_vmdq_dcb_conf *conf;
1828 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1829 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1830 IXGBE_VMDQ_DCB_NB_QUEUES);
1833 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1834 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1835 conf->nb_queue_pools == ETH_32_POOLS)) {
1836 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1837 " nb_queue_pools must be %d or %d.",
1838 ETH_16_POOLS, ETH_32_POOLS);
1842 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1843 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1845 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1846 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1847 IXGBE_VMDQ_DCB_NB_QUEUES);
1850 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1851 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1852 conf->nb_queue_pools == ETH_32_POOLS)) {
1853 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1854 " nb_queue_pools != %d and"
1855 " nb_queue_pools != %d.",
1856 ETH_16_POOLS, ETH_32_POOLS);
1861 /* For DCB mode check our configuration before we go further */
1862 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1863 const struct rte_eth_dcb_rx_conf *conf;
1865 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1866 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1867 IXGBE_DCB_NB_QUEUES);
1870 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1871 if (!(conf->nb_tcs == ETH_4_TCS ||
1872 conf->nb_tcs == ETH_8_TCS)) {
1873 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1874 " and nb_tcs != %d.",
1875 ETH_4_TCS, ETH_8_TCS);
1880 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1881 const struct rte_eth_dcb_tx_conf *conf;
1883 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1884 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1885 IXGBE_DCB_NB_QUEUES);
1888 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1889 if (!(conf->nb_tcs == ETH_4_TCS ||
1890 conf->nb_tcs == ETH_8_TCS)) {
1891 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1892 " and nb_tcs != %d.",
1893 ETH_4_TCS, ETH_8_TCS);
1902 ixgbe_dev_configure(struct rte_eth_dev *dev)
1904 struct ixgbe_interrupt *intr =
1905 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1906 struct ixgbe_adapter *adapter =
1907 (struct ixgbe_adapter *)dev->data->dev_private;
1910 PMD_INIT_FUNC_TRACE();
1911 /* multipe queue mode checking */
1912 ret = ixgbe_check_mq_mode(dev);
1914 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1919 /* set flag to update link status after init */
1920 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1923 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1924 * allocation or vector Rx preconditions we will reset it.
1926 adapter->rx_bulk_alloc_allowed = true;
1927 adapter->rx_vec_allowed = true;
1933 * Configure device link speed and setup link.
1934 * It returns 0 on success.
1937 ixgbe_dev_start(struct rte_eth_dev *dev)
1939 struct ixgbe_hw *hw =
1940 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941 struct ixgbe_vf_info *vfinfo =
1942 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1943 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1944 uint32_t intr_vector = 0;
1945 int err, link_up = 0, negotiate = 0;
1951 PMD_INIT_FUNC_TRACE();
1953 /* IXGBE devices don't support half duplex */
1954 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1955 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1956 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1957 dev->data->dev_conf.link_duplex,
1958 dev->data->port_id);
1963 hw->adapter_stopped = 0;
1964 ixgbe_stop_adapter(hw);
1966 /* reinitialize adapter
1967 * this calls reset and start */
1968 status = ixgbe_pf_reset_hw(hw);
1971 hw->mac.ops.start_hw(hw);
1972 hw->mac.get_link_status = true;
1974 /* configure PF module if SRIOV enabled */
1975 ixgbe_pf_host_configure(dev);
1977 /* check and configure queue intr-vector mapping */
1978 if (dev->data->dev_conf.intr_conf.rxq != 0) {
1979 intr_vector = dev->data->nb_rx_queues;
1980 if (rte_intr_efd_enable(intr_handle, intr_vector))
1984 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1985 intr_handle->intr_vec =
1986 rte_zmalloc("intr_vec",
1987 dev->data->nb_rx_queues * sizeof(int),
1989 if (intr_handle->intr_vec == NULL) {
1990 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1991 " intr_vec\n", dev->data->nb_rx_queues);
1996 /* confiugre msix for sleep until rx interrupt */
1997 ixgbe_configure_msix(dev);
1999 /* initialize transmission unit */
2000 ixgbe_dev_tx_init(dev);
2002 /* This can fail when allocating mbufs for descriptor rings */
2003 err = ixgbe_dev_rx_init(dev);
2005 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2009 err = ixgbe_dev_rxtx_start(dev);
2011 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2015 /* Skip link setup if loopback mode is enabled for 82599. */
2016 if (hw->mac.type == ixgbe_mac_82599EB &&
2017 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2018 goto skip_link_setup;
2020 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2021 err = hw->mac.ops.setup_sfp(hw);
2026 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2027 /* Turn on the copper */
2028 ixgbe_set_phy_power(hw, true);
2030 /* Turn on the laser */
2031 ixgbe_enable_tx_laser(hw);
2034 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2037 dev->data->dev_link.link_status = link_up;
2039 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2043 switch(dev->data->dev_conf.link_speed) {
2044 case ETH_LINK_SPEED_AUTONEG:
2045 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2046 IXGBE_LINK_SPEED_82599_AUTONEG :
2047 IXGBE_LINK_SPEED_82598_AUTONEG;
2049 case ETH_LINK_SPEED_100:
2051 * Invalid for 82598 but error will be detected by
2052 * ixgbe_setup_link()
2054 speed = IXGBE_LINK_SPEED_100_FULL;
2056 case ETH_LINK_SPEED_1000:
2057 speed = IXGBE_LINK_SPEED_1GB_FULL;
2059 case ETH_LINK_SPEED_10000:
2060 speed = IXGBE_LINK_SPEED_10GB_FULL;
2063 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2064 dev->data->dev_conf.link_speed,
2065 dev->data->port_id);
2069 err = ixgbe_setup_link(hw, speed, link_up);
2075 /* check if lsc interrupt is enabled */
2076 if (dev->data->dev_conf.intr_conf.lsc != 0) {
2077 if (rte_intr_allow_others(intr_handle)) {
2078 rte_intr_callback_register(intr_handle,
2079 ixgbe_dev_interrupt_handler,
2081 ixgbe_dev_lsc_interrupt_setup(dev);
2083 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2084 " no intr multiplex\n");
2087 /* check if rxq interrupt is enabled */
2088 if (dev->data->dev_conf.intr_conf.rxq != 0)
2089 ixgbe_dev_rxq_interrupt_setup(dev);
2091 /* enable uio/vfio intr/eventfd mapping */
2092 rte_intr_enable(intr_handle);
2094 /* resume enabled intr since hw reset */
2095 ixgbe_enable_intr(dev);
2097 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2098 ETH_VLAN_EXTEND_MASK;
2099 ixgbe_vlan_offload_set(dev, mask);
2101 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2102 /* Enable vlan filtering for VMDq */
2103 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2106 /* Configure DCB hw */
2107 ixgbe_configure_dcb(dev);
2109 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2110 err = ixgbe_fdir_configure(dev);
2115 /* Restore vf rate limit */
2116 if (vfinfo != NULL) {
2117 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2118 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2119 if (vfinfo[vf].tx_rate[idx] != 0)
2120 ixgbe_set_vf_rate_limit(dev, vf,
2121 vfinfo[vf].tx_rate[idx],
2125 ixgbe_restore_statistics_mapping(dev);
2130 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2131 ixgbe_dev_clear_queues(dev);
2136 * Stop device: disable rx and tx functions to allow for reconfiguring.
2139 ixgbe_dev_stop(struct rte_eth_dev *dev)
2141 struct rte_eth_link link;
2142 struct ixgbe_hw *hw =
2143 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144 struct ixgbe_vf_info *vfinfo =
2145 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2146 struct ixgbe_filter_info *filter_info =
2147 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2148 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2149 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2152 PMD_INIT_FUNC_TRACE();
2154 /* disable interrupts */
2155 ixgbe_disable_intr(hw);
2157 /* disable intr eventfd mapping */
2158 rte_intr_disable(intr_handle);
2161 ixgbe_pf_reset_hw(hw);
2162 hw->adapter_stopped = 0;
2165 ixgbe_stop_adapter(hw);
2167 for (vf = 0; vfinfo != NULL &&
2168 vf < dev->pci_dev->max_vfs; vf++)
2169 vfinfo[vf].clear_to_send = false;
2171 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2172 /* Turn off the copper */
2173 ixgbe_set_phy_power(hw, false);
2175 /* Turn off the laser */
2176 ixgbe_disable_tx_laser(hw);
2179 ixgbe_dev_clear_queues(dev);
2181 /* Clear stored conf */
2182 dev->data->scattered_rx = 0;
2185 /* Clear recorded link status */
2186 memset(&link, 0, sizeof(link));
2187 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2189 /* Remove all ntuple filters of the device */
2190 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2191 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2192 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2193 TAILQ_REMOVE(&filter_info->fivetuple_list,
2197 memset(filter_info->fivetuple_mask, 0,
2198 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2200 /* Clean datapath event and queue/vec mapping */
2201 rte_intr_efd_disable(intr_handle);
2202 if (intr_handle->intr_vec != NULL) {
2203 rte_free(intr_handle->intr_vec);
2204 intr_handle->intr_vec = NULL;
2209 * Set device link up: enable tx.
2212 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2214 struct ixgbe_hw *hw =
2215 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216 if (hw->mac.type == ixgbe_mac_82599EB) {
2217 #ifdef RTE_NIC_BYPASS
2218 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2219 /* Not suported in bypass mode */
2220 PMD_INIT_LOG(ERR, "Set link up is not supported "
2221 "by device id 0x%x", hw->device_id);
2227 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2228 /* Turn on the copper */
2229 ixgbe_set_phy_power(hw, true);
2231 /* Turn on the laser */
2232 ixgbe_enable_tx_laser(hw);
2239 * Set device link down: disable tx.
2242 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2244 struct ixgbe_hw *hw =
2245 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246 if (hw->mac.type == ixgbe_mac_82599EB) {
2247 #ifdef RTE_NIC_BYPASS
2248 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2249 /* Not suported in bypass mode */
2250 PMD_INIT_LOG(ERR, "Set link down is not supported "
2251 "by device id 0x%x", hw->device_id);
2257 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2258 /* Turn off the copper */
2259 ixgbe_set_phy_power(hw, false);
2261 /* Turn off the laser */
2262 ixgbe_disable_tx_laser(hw);
2269 * Reest and stop device.
2272 ixgbe_dev_close(struct rte_eth_dev *dev)
2274 struct ixgbe_hw *hw =
2275 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277 PMD_INIT_FUNC_TRACE();
2279 ixgbe_pf_reset_hw(hw);
2281 ixgbe_dev_stop(dev);
2282 hw->adapter_stopped = 1;
2284 ixgbe_dev_free_queues(dev);
2286 ixgbe_disable_pcie_master(hw);
2288 /* reprogram the RAR[0] in case user changed it. */
2289 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2293 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2294 *hw_stats, uint64_t *total_missed_rx,
2295 uint64_t *total_qbrc, uint64_t *total_qprc,
2296 uint64_t *total_qprdc)
2298 uint32_t bprc, lxon, lxoff, total;
2301 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2302 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2303 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2304 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2306 for (i = 0; i < 8; i++) {
2308 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2309 /* global total per queue */
2310 hw_stats->mpc[i] += mp;
2311 /* Running comprehensive total for stats display */
2312 *total_missed_rx += hw_stats->mpc[i];
2313 if (hw->mac.type == ixgbe_mac_82598EB) {
2314 hw_stats->rnbc[i] +=
2315 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2316 hw_stats->pxonrxc[i] +=
2317 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2318 hw_stats->pxoffrxc[i] +=
2319 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2321 hw_stats->pxonrxc[i] +=
2322 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2323 hw_stats->pxoffrxc[i] +=
2324 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2325 hw_stats->pxon2offc[i] +=
2326 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2328 hw_stats->pxontxc[i] +=
2329 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2330 hw_stats->pxofftxc[i] +=
2331 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2333 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2334 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2335 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2336 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2337 hw_stats->qbrc[i] +=
2338 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2339 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2340 hw_stats->qbtc[i] +=
2341 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2342 *total_qprdc += hw_stats->qprdc[i] +=
2343 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2345 *total_qprc += hw_stats->qprc[i];
2346 *total_qbrc += hw_stats->qbrc[i];
2348 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2349 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2350 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2352 /* Note that gprc counts missed packets */
2353 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2355 if (hw->mac.type != ixgbe_mac_82598EB) {
2356 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2357 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2358 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2359 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2360 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2361 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2362 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2363 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2365 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2366 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2367 /* 82598 only has a counter in the high register */
2368 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2369 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2370 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2374 * Workaround: mprc hardware is incorrectly counting
2375 * broadcasts, so for now we subtract those.
2377 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2378 hw_stats->bprc += bprc;
2379 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2380 if (hw->mac.type == ixgbe_mac_82598EB)
2381 hw_stats->mprc -= bprc;
2383 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2384 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2385 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2386 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2387 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2388 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2390 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2391 hw_stats->lxontxc += lxon;
2392 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2393 hw_stats->lxofftxc += lxoff;
2394 total = lxon + lxoff;
2396 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2397 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2398 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2399 hw_stats->gptc -= total;
2400 hw_stats->mptc -= total;
2401 hw_stats->ptc64 -= total;
2402 hw_stats->gotc -= total * ETHER_MIN_LEN;
2404 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2405 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2406 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2407 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2408 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2409 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2410 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2411 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2412 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2413 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2414 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2415 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2416 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2417 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2418 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2419 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2420 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2421 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2422 /* Only read FCOE on 82599 */
2423 if (hw->mac.type != ixgbe_mac_82598EB) {
2424 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2425 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2426 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2427 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2428 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2431 /* Flow Director Stats registers */
2432 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2433 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2437 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2440 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2442 struct ixgbe_hw *hw =
2443 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444 struct ixgbe_hw_stats *hw_stats =
2445 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2446 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2449 total_missed_rx = 0;
2454 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2455 &total_qprc, &total_qprdc);
2460 /* Fill out the rte_eth_stats statistics structure */
2461 stats->ipackets = total_qprc;
2462 stats->ibytes = total_qbrc;
2463 stats->opackets = hw_stats->gptc;
2464 stats->obytes = hw_stats->gotc;
2466 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2467 stats->q_ipackets[i] = hw_stats->qprc[i];
2468 stats->q_opackets[i] = hw_stats->qptc[i];
2469 stats->q_ibytes[i] = hw_stats->qbrc[i];
2470 stats->q_obytes[i] = hw_stats->qbtc[i];
2471 stats->q_errors[i] = hw_stats->qprdc[i];
2475 stats->ierrors = hw_stats->crcerrs +
2493 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2495 struct ixgbe_hw_stats *stats =
2496 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2498 /* HW registers are cleared on read */
2499 ixgbe_dev_stats_get(dev, NULL);
2501 /* Reset software totals */
2502 memset(stats, 0, sizeof(*stats));
2506 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2509 struct ixgbe_hw *hw =
2510 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511 struct ixgbe_hw_stats *hw_stats =
2512 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2513 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2514 unsigned i, count = IXGBE_NB_XSTATS;
2519 total_missed_rx = 0;
2524 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2525 &total_qprc, &total_qprdc);
2527 /* If this is a reset xstats is NULL, and we have cleared the
2528 * registers by reading them.
2533 /* Extended stats from ixgbe_hw_stats */
2535 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2536 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2537 rte_ixgbe_stats_strings[i].name);
2538 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2539 rte_ixgbe_stats_strings[i].offset);
2543 /* Per-Q stats, with 8 queues available */
2544 for (i = 0; i < 8; i++) {
2545 snprintf(xstats[count].name, sizeof(xstats[count].name),
2546 "rx_q%u_mbuf_allocation_errors", i);
2547 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2548 offsetof(struct ixgbe_hw_stats, rnbc[i]));
2551 snprintf(xstats[count].name, sizeof(xstats[count].name),
2552 "rx_q%u_missed_packets", i);
2553 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2554 offsetof(struct ixgbe_hw_stats, mpc[i]));
2557 snprintf(xstats[count].name, sizeof(xstats[count].name),
2558 "rx_q%u_xon_priority_packets", i);
2559 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2560 offsetof(struct ixgbe_hw_stats, pxonrxc[i]));
2563 snprintf(xstats[count].name, sizeof(xstats[count].name),
2564 "tx_q%u_xon_priority_packets", i);
2565 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2566 offsetof(struct ixgbe_hw_stats, pxontxc[i]));
2569 snprintf(xstats[count].name, sizeof(xstats[count].name),
2570 "rx_q%u_xoff_priority_packets", i);
2571 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2572 offsetof(struct ixgbe_hw_stats, pxoffrxc[i]));
2575 snprintf(xstats[count].name, sizeof(xstats[count].name),
2576 "tx_q%u_xoff_priority_packets", i);
2577 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2578 offsetof(struct ixgbe_hw_stats, pxofftxc[i]));
2581 snprintf(xstats[count].name, sizeof(xstats[count].name),
2582 "xx_q%u_xon_to_xoff_priority_packets", i);
2583 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2584 offsetof(struct ixgbe_hw_stats, pxon2offc[i]));
2588 for (i = 0; i < 16; i++) {
2589 snprintf(xstats[count].name, sizeof(xstats[count].name),
2590 "rx_q%u_packets", i);
2591 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2592 offsetof(struct ixgbe_hw_stats, qprc[i]));
2595 snprintf(xstats[count].name, sizeof(xstats[count].name),
2597 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2598 offsetof(struct ixgbe_hw_stats, qbrc[i]));
2601 snprintf(xstats[count].name, sizeof(xstats[count].name),
2602 "tx_q%u_packets", i);
2603 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2604 offsetof(struct ixgbe_hw_stats, qptc[i]));
2607 snprintf(xstats[count].name, sizeof(xstats[count].name),
2609 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2610 offsetof(struct ixgbe_hw_stats, qbtc[i]));
2613 snprintf(xstats[count].name, sizeof(xstats[count].name),
2614 "rx_q%u_dropped", i);
2615 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2616 offsetof(struct ixgbe_hw_stats, qprdc[i]));
2624 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2626 struct ixgbe_hw_stats *stats =
2627 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2629 /* HW registers are cleared on read */
2630 ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2632 /* Reset software totals */
2633 memset(stats, 0, sizeof(*stats));
2637 ixgbevf_update_stats(struct rte_eth_dev *dev)
2639 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2641 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2643 /* Good Rx packet, include VF loopback */
2644 UPDATE_VF_STAT(IXGBE_VFGPRC,
2645 hw_stats->last_vfgprc, hw_stats->vfgprc);
2647 /* Good Rx octets, include VF loopback */
2648 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2649 hw_stats->last_vfgorc, hw_stats->vfgorc);
2651 /* Good Tx packet, include VF loopback */
2652 UPDATE_VF_STAT(IXGBE_VFGPTC,
2653 hw_stats->last_vfgptc, hw_stats->vfgptc);
2655 /* Good Tx octets, include VF loopback */
2656 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2657 hw_stats->last_vfgotc, hw_stats->vfgotc);
2659 /* Rx Multicst Packet */
2660 UPDATE_VF_STAT(IXGBE_VFMPRC,
2661 hw_stats->last_vfmprc, hw_stats->vfmprc);
2665 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2668 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2669 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2672 if (n < IXGBEVF_NB_XSTATS)
2673 return IXGBEVF_NB_XSTATS;
2675 ixgbevf_update_stats(dev);
2680 /* Extended stats */
2681 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2682 snprintf(xstats[i].name, sizeof(xstats[i].name),
2683 "%s", rte_ixgbevf_stats_strings[i].name);
2684 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2685 rte_ixgbevf_stats_strings[i].offset);
2688 return IXGBEVF_NB_XSTATS;
2692 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2694 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2695 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2697 ixgbevf_update_stats(dev);
2702 stats->ipackets = hw_stats->vfgprc;
2703 stats->ibytes = hw_stats->vfgorc;
2704 stats->opackets = hw_stats->vfgptc;
2705 stats->obytes = hw_stats->vfgotc;
2706 stats->imcasts = hw_stats->vfmprc;
2707 /* stats->imcasts should be removed as imcasts is deprecated */
2711 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2713 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2714 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2716 /* Sync HW register to the last stats */
2717 ixgbevf_dev_stats_get(dev, NULL);
2719 /* reset HW current stats*/
2720 hw_stats->vfgprc = 0;
2721 hw_stats->vfgorc = 0;
2722 hw_stats->vfgptc = 0;
2723 hw_stats->vfgotc = 0;
2724 hw_stats->vfmprc = 0;
2729 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2731 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2733 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2734 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2735 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2736 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2737 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2738 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2739 dev_info->max_vfs = dev->pci_dev->max_vfs;
2740 if (hw->mac.type == ixgbe_mac_82598EB)
2741 dev_info->max_vmdq_pools = ETH_16_POOLS;
2743 dev_info->max_vmdq_pools = ETH_64_POOLS;
2744 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2745 dev_info->rx_offload_capa =
2746 DEV_RX_OFFLOAD_VLAN_STRIP |
2747 DEV_RX_OFFLOAD_IPV4_CKSUM |
2748 DEV_RX_OFFLOAD_UDP_CKSUM |
2749 DEV_RX_OFFLOAD_TCP_CKSUM;
2752 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2755 if ((hw->mac.type == ixgbe_mac_82599EB ||
2756 hw->mac.type == ixgbe_mac_X540) &&
2757 !RTE_ETH_DEV_SRIOV(dev).active)
2758 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2760 dev_info->tx_offload_capa =
2761 DEV_TX_OFFLOAD_VLAN_INSERT |
2762 DEV_TX_OFFLOAD_IPV4_CKSUM |
2763 DEV_TX_OFFLOAD_UDP_CKSUM |
2764 DEV_TX_OFFLOAD_TCP_CKSUM |
2765 DEV_TX_OFFLOAD_SCTP_CKSUM |
2766 DEV_TX_OFFLOAD_TCP_TSO;
2768 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2770 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2771 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2772 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2774 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2778 dev_info->default_txconf = (struct rte_eth_txconf) {
2780 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2781 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2782 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2784 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2785 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2786 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2787 ETH_TXQ_FLAGS_NOOFFLOADS,
2790 dev_info->rx_desc_lim = rx_desc_lim;
2791 dev_info->tx_desc_lim = tx_desc_lim;
2793 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2794 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2795 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2799 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2800 struct rte_eth_dev_info *dev_info)
2802 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2804 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2805 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2806 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2807 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2808 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2809 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2810 dev_info->max_vfs = dev->pci_dev->max_vfs;
2811 if (hw->mac.type == ixgbe_mac_82598EB)
2812 dev_info->max_vmdq_pools = ETH_16_POOLS;
2814 dev_info->max_vmdq_pools = ETH_64_POOLS;
2815 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2816 DEV_RX_OFFLOAD_IPV4_CKSUM |
2817 DEV_RX_OFFLOAD_UDP_CKSUM |
2818 DEV_RX_OFFLOAD_TCP_CKSUM;
2819 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2820 DEV_TX_OFFLOAD_IPV4_CKSUM |
2821 DEV_TX_OFFLOAD_UDP_CKSUM |
2822 DEV_TX_OFFLOAD_TCP_CKSUM |
2823 DEV_TX_OFFLOAD_SCTP_CKSUM |
2824 DEV_TX_OFFLOAD_TCP_TSO;
2826 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2828 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2829 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2830 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2832 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2836 dev_info->default_txconf = (struct rte_eth_txconf) {
2838 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2839 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2840 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2842 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2843 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2844 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2845 ETH_TXQ_FLAGS_NOOFFLOADS,
2848 dev_info->rx_desc_lim = rx_desc_lim;
2849 dev_info->tx_desc_lim = tx_desc_lim;
2852 /* return 0 means link status changed, -1 means not changed */
2854 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2856 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2857 struct rte_eth_link link, old;
2858 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2862 link.link_status = 0;
2863 link.link_speed = 0;
2864 link.link_duplex = 0;
2865 memset(&old, 0, sizeof(old));
2866 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2868 hw->mac.get_link_status = true;
2870 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2871 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2872 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2874 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2877 link.link_speed = ETH_LINK_SPEED_100;
2878 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2879 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2880 if (link.link_status == old.link_status)
2886 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2887 if (link.link_status == old.link_status)
2891 link.link_status = 1;
2892 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2894 switch (link_speed) {
2896 case IXGBE_LINK_SPEED_UNKNOWN:
2897 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2898 link.link_speed = ETH_LINK_SPEED_100;
2901 case IXGBE_LINK_SPEED_100_FULL:
2902 link.link_speed = ETH_LINK_SPEED_100;
2905 case IXGBE_LINK_SPEED_1GB_FULL:
2906 link.link_speed = ETH_LINK_SPEED_1000;
2909 case IXGBE_LINK_SPEED_10GB_FULL:
2910 link.link_speed = ETH_LINK_SPEED_10000;
2913 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2915 if (link.link_status == old.link_status)
2922 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2924 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2927 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2928 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2929 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2933 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2935 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2938 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2939 fctrl &= (~IXGBE_FCTRL_UPE);
2940 if (dev->data->all_multicast == 1)
2941 fctrl |= IXGBE_FCTRL_MPE;
2943 fctrl &= (~IXGBE_FCTRL_MPE);
2944 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2948 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2950 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2953 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2954 fctrl |= IXGBE_FCTRL_MPE;
2955 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2959 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2961 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964 if (dev->data->promiscuous == 1)
2965 return; /* must remain in all_multicast mode */
2967 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2968 fctrl &= (~IXGBE_FCTRL_MPE);
2969 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2973 * It clears the interrupt causes and enables the interrupt.
2974 * It will be called once only during nic initialized.
2977 * Pointer to struct rte_eth_dev.
2980 * - On success, zero.
2981 * - On failure, a negative value.
2984 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2986 struct ixgbe_interrupt *intr =
2987 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2989 ixgbe_dev_link_status_print(dev);
2990 intr->mask |= IXGBE_EICR_LSC;
2996 * It clears the interrupt causes and enables the interrupt.
2997 * It will be called once only during nic initialized.
3000 * Pointer to struct rte_eth_dev.
3003 * - On success, zero.
3004 * - On failure, a negative value.
3007 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3009 struct ixgbe_interrupt *intr =
3010 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3012 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3018 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3021 * Pointer to struct rte_eth_dev.
3024 * - On success, zero.
3025 * - On failure, a negative value.
3028 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3031 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3032 struct ixgbe_interrupt *intr =
3033 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3035 /* clear all cause mask */
3036 ixgbe_disable_intr(hw);
3038 /* read-on-clear nic registers here */
3039 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3040 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3044 /* set flag for async link update */
3045 if (eicr & IXGBE_EICR_LSC)
3046 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3048 if (eicr & IXGBE_EICR_MAILBOX)
3049 intr->flags |= IXGBE_FLAG_MAILBOX;
3055 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
3058 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3059 struct ixgbe_interrupt *intr =
3060 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3062 /* clear all cause mask */
3063 ixgbevf_intr_disable(hw);
3065 /* read-on-clear nic registers here */
3066 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
3067 PMD_DRV_LOG(INFO, "eicr %x", eicr);
3071 /* set flag for async link update */
3072 if (eicr & IXGBE_EICR_LSC)
3073 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3079 * It gets and then prints the link status.
3082 * Pointer to struct rte_eth_dev.
3085 * - On success, zero.
3086 * - On failure, a negative value.
3089 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3091 struct rte_eth_link link;
3093 memset(&link, 0, sizeof(link));
3094 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3095 if (link.link_status) {
3096 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3097 (int)(dev->data->port_id),
3098 (unsigned)link.link_speed,
3099 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3100 "full-duplex" : "half-duplex");
3102 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3103 (int)(dev->data->port_id));
3105 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3106 dev->pci_dev->addr.domain,
3107 dev->pci_dev->addr.bus,
3108 dev->pci_dev->addr.devid,
3109 dev->pci_dev->addr.function);
3113 * It executes link_update after knowing an interrupt occurred.
3116 * Pointer to struct rte_eth_dev.
3119 * - On success, zero.
3120 * - On failure, a negative value.
3123 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3125 struct ixgbe_interrupt *intr =
3126 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3128 struct rte_eth_link link;
3129 int intr_enable_delay = false;
3131 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3133 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3134 ixgbe_pf_mbx_process(dev);
3135 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3138 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3139 /* get the link status before link update, for predicting later */
3140 memset(&link, 0, sizeof(link));
3141 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3143 ixgbe_dev_link_update(dev, 0);
3146 if (!link.link_status)
3147 /* handle it 1 sec later, wait it being stable */
3148 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3149 /* likely to down */
3151 /* handle it 4 sec later, wait it being stable */
3152 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3154 ixgbe_dev_link_status_print(dev);
3156 intr_enable_delay = true;
3159 if (intr_enable_delay) {
3160 if (rte_eal_alarm_set(timeout * 1000,
3161 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3162 PMD_DRV_LOG(ERR, "Error setting alarm");
3164 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3165 ixgbe_enable_intr(dev);
3166 rte_intr_enable(&(dev->pci_dev->intr_handle));
3174 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
3176 struct ixgbe_hw *hw =
3177 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3179 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3180 ixgbevf_intr_enable(hw);
3181 rte_intr_enable(&dev->pci_dev->intr_handle);
3186 * Interrupt handler which shall be registered for alarm callback for delayed
3187 * handling specific interrupt to wait for the stable nic state. As the
3188 * NIC interrupt state is not stable for ixgbe after link is just down,
3189 * it needs to wait 4 seconds to get the stable status.
3192 * Pointer to interrupt handle.
3194 * The address of parameter (struct rte_eth_dev *) regsitered before.
3200 ixgbe_dev_interrupt_delayed_handler(void *param)
3202 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3203 struct ixgbe_interrupt *intr =
3204 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3205 struct ixgbe_hw *hw =
3206 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3209 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3210 if (eicr & IXGBE_EICR_MAILBOX)
3211 ixgbe_pf_mbx_process(dev);
3213 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3214 ixgbe_dev_link_update(dev, 0);
3215 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3216 ixgbe_dev_link_status_print(dev);
3217 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3220 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3221 ixgbe_enable_intr(dev);
3222 rte_intr_enable(&(dev->pci_dev->intr_handle));
3226 * Interrupt handler triggered by NIC for handling
3227 * specific interrupt.
3230 * Pointer to interrupt handle.
3232 * The address of parameter (struct rte_eth_dev *) regsitered before.
3238 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3241 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3243 ixgbe_dev_interrupt_get_status(dev);
3244 ixgbe_dev_interrupt_action(dev);
3248 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3251 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3253 ixgbevf_dev_interrupt_get_status(dev);
3254 ixgbevf_dev_interrupt_action(dev);
3258 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3260 struct ixgbe_hw *hw;
3262 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3263 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3267 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3269 struct ixgbe_hw *hw;
3271 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3272 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3276 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3278 struct ixgbe_hw *hw;
3284 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3286 fc_conf->pause_time = hw->fc.pause_time;
3287 fc_conf->high_water = hw->fc.high_water[0];
3288 fc_conf->low_water = hw->fc.low_water[0];
3289 fc_conf->send_xon = hw->fc.send_xon;
3290 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3293 * Return rx_pause status according to actual setting of
3296 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3297 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3303 * Return tx_pause status according to actual setting of
3306 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3307 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3312 if (rx_pause && tx_pause)
3313 fc_conf->mode = RTE_FC_FULL;
3315 fc_conf->mode = RTE_FC_RX_PAUSE;
3317 fc_conf->mode = RTE_FC_TX_PAUSE;
3319 fc_conf->mode = RTE_FC_NONE;
3325 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3327 struct ixgbe_hw *hw;
3329 uint32_t rx_buf_size;
3330 uint32_t max_high_water;
3332 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3339 PMD_INIT_FUNC_TRACE();
3341 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3342 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3343 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3346 * At least reserve one Ethernet frame for watermark
3347 * high_water/low_water in kilo bytes for ixgbe
3349 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3350 if ((fc_conf->high_water > max_high_water) ||
3351 (fc_conf->high_water < fc_conf->low_water)) {
3352 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3353 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3357 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3358 hw->fc.pause_time = fc_conf->pause_time;
3359 hw->fc.high_water[0] = fc_conf->high_water;
3360 hw->fc.low_water[0] = fc_conf->low_water;
3361 hw->fc.send_xon = fc_conf->send_xon;
3362 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3364 err = ixgbe_fc_enable(hw);
3366 /* Not negotiated is not an error case */
3367 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3369 /* check if we want to forward MAC frames - driver doesn't have native
3370 * capability to do that, so we'll write the registers ourselves */
3372 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3374 /* set or clear MFLCN.PMCF bit depending on configuration */
3375 if (fc_conf->mac_ctrl_frame_fwd != 0)
3376 mflcn |= IXGBE_MFLCN_PMCF;
3378 mflcn &= ~IXGBE_MFLCN_PMCF;
3380 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3381 IXGBE_WRITE_FLUSH(hw);
3386 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3391 * ixgbe_pfc_enable_generic - Enable flow control
3392 * @hw: pointer to hardware structure
3393 * @tc_num: traffic class number
3394 * Enable flow control according to the current settings.
3397 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3400 uint32_t mflcn_reg, fccfg_reg;
3402 uint32_t fcrtl, fcrth;
3406 /* Validate the water mark configuration */
3407 if (!hw->fc.pause_time) {
3408 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3412 /* Low water mark of zero causes XOFF floods */
3413 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3414 /* High/Low water can not be 0 */
3415 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3416 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3417 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3421 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3422 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3423 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3427 /* Negotiate the fc mode to use */
3428 ixgbe_fc_autoneg(hw);
3430 /* Disable any previous flow control settings */
3431 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3432 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3434 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3435 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3437 switch (hw->fc.current_mode) {
3440 * If the count of enabled RX Priority Flow control >1,
3441 * and the TX pause can not be disabled
3444 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3445 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3446 if (reg & IXGBE_FCRTH_FCEN)
3450 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3452 case ixgbe_fc_rx_pause:
3454 * Rx Flow control is enabled and Tx Flow control is
3455 * disabled by software override. Since there really
3456 * isn't a way to advertise that we are capable of RX
3457 * Pause ONLY, we will advertise that we support both
3458 * symmetric and asymmetric Rx PAUSE. Later, we will
3459 * disable the adapter's ability to send PAUSE frames.
3461 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3463 * If the count of enabled RX Priority Flow control >1,
3464 * and the TX pause can not be disabled
3467 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3468 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3469 if (reg & IXGBE_FCRTH_FCEN)
3473 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3475 case ixgbe_fc_tx_pause:
3477 * Tx Flow control is enabled, and Rx Flow control is
3478 * disabled by software override.
3480 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3483 /* Flow control (both Rx and Tx) is enabled by SW override. */
3484 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3485 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3488 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3489 ret_val = IXGBE_ERR_CONFIG;
3494 /* Set 802.3x based flow control settings. */
3495 mflcn_reg |= IXGBE_MFLCN_DPF;
3496 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3497 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3499 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3500 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3501 hw->fc.high_water[tc_num]) {
3502 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3503 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3504 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3506 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3508 * In order to prevent Tx hangs when the internal Tx
3509 * switch is enabled we must set the high water mark
3510 * to the maximum FCRTH value. This allows the Tx
3511 * switch to function even under heavy Rx workloads.
3513 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3515 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3517 /* Configure pause time (2 TCs per register) */
3518 reg = hw->fc.pause_time * 0x00010001;
3519 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3520 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3522 /* Configure flow control refresh threshold value */
3523 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3530 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3532 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3533 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3535 if(hw->mac.type != ixgbe_mac_82598EB) {
3536 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3542 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3545 uint32_t rx_buf_size;
3546 uint32_t max_high_water;
3548 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3549 struct ixgbe_hw *hw =
3550 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3551 struct ixgbe_dcb_config *dcb_config =
3552 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3554 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3561 PMD_INIT_FUNC_TRACE();
3563 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3564 tc_num = map[pfc_conf->priority];
3565 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3566 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3568 * At least reserve one Ethernet frame for watermark
3569 * high_water/low_water in kilo bytes for ixgbe
3571 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3572 if ((pfc_conf->fc.high_water > max_high_water) ||
3573 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3574 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3575 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3579 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3580 hw->fc.pause_time = pfc_conf->fc.pause_time;
3581 hw->fc.send_xon = pfc_conf->fc.send_xon;
3582 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3583 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3585 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3587 /* Not negotiated is not an error case */
3588 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3591 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3596 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3597 struct rte_eth_rss_reta_entry64 *reta_conf,
3602 uint16_t idx, shift;
3603 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3604 uint16_t sp_reta_size;
3607 PMD_INIT_FUNC_TRACE();
3609 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3610 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3615 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3616 if (reta_size != sp_reta_size) {
3617 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3618 "(%d) doesn't match the number hardware can supported "
3619 "(%d)\n", reta_size, sp_reta_size);
3623 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3624 idx = i / RTE_RETA_GROUP_SIZE;
3625 shift = i % RTE_RETA_GROUP_SIZE;
3626 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3630 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3631 if (mask == IXGBE_4_BIT_MASK)
3634 r = IXGBE_READ_REG(hw, reta_reg);
3635 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3636 if (mask & (0x1 << j))
3637 reta |= reta_conf[idx].reta[shift + j] <<
3640 reta |= r & (IXGBE_8_BIT_MASK <<
3643 IXGBE_WRITE_REG(hw, reta_reg, reta);
3650 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3651 struct rte_eth_rss_reta_entry64 *reta_conf,
3656 uint16_t idx, shift;
3657 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658 uint16_t sp_reta_size;
3661 PMD_INIT_FUNC_TRACE();
3662 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3663 if (reta_size != sp_reta_size) {
3664 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3665 "(%d) doesn't match the number hardware can supported "
3666 "(%d)\n", reta_size, sp_reta_size);
3670 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3671 idx = i / RTE_RETA_GROUP_SIZE;
3672 shift = i % RTE_RETA_GROUP_SIZE;
3673 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3678 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3679 reta = IXGBE_READ_REG(hw, reta_reg);
3680 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3681 if (mask & (0x1 << j))
3682 reta_conf[idx].reta[shift + j] =
3683 ((reta >> (CHAR_BIT * j)) &
3692 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3693 uint32_t index, uint32_t pool)
3695 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3696 uint32_t enable_addr = 1;
3698 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3702 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3704 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3706 ixgbe_clear_rar(hw, index);
3710 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3712 ixgbe_remove_rar(dev, 0);
3714 ixgbe_add_rar(dev, addr, 0, 0);
3718 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3722 struct ixgbe_hw *hw;
3723 struct rte_eth_dev_info dev_info;
3724 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3726 ixgbe_dev_info_get(dev, &dev_info);
3728 /* check that mtu is within the allowed range */
3729 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3732 /* refuse mtu that requires the support of scattered packets when this
3733 * feature has not been enabled before. */
3734 if (!dev->data->scattered_rx &&
3735 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3736 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3739 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3740 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3742 /* switch to jumbo mode if needed */
3743 if (frame_size > ETHER_MAX_LEN) {
3744 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3745 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3747 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3748 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3750 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3752 /* update max frame size */
3753 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3755 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3756 maxfrs &= 0x0000FFFF;
3757 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3758 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3764 * Virtual Function operations
3767 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3769 PMD_INIT_FUNC_TRACE();
3771 /* Clear interrupt mask to stop from interrupts being generated */
3772 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3774 IXGBE_WRITE_FLUSH(hw);
3778 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3780 PMD_INIT_FUNC_TRACE();
3782 /* VF enable interrupt autoclean */
3783 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3784 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3785 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3787 IXGBE_WRITE_FLUSH(hw);
3791 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3793 struct rte_eth_conf* conf = &dev->data->dev_conf;
3794 struct ixgbe_adapter *adapter =
3795 (struct ixgbe_adapter *)dev->data->dev_private;
3797 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3798 dev->data->port_id);
3801 * VF has no ability to enable/disable HW CRC
3802 * Keep the persistent behavior the same as Host PF
3804 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3805 if (!conf->rxmode.hw_strip_crc) {
3806 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3807 conf->rxmode.hw_strip_crc = 1;
3810 if (conf->rxmode.hw_strip_crc) {
3811 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3812 conf->rxmode.hw_strip_crc = 0;
3817 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3818 * allocation or vector Rx preconditions we will reset it.
3820 adapter->rx_bulk_alloc_allowed = true;
3821 adapter->rx_vec_allowed = true;
3827 ixgbevf_dev_start(struct rte_eth_dev *dev)
3829 struct ixgbe_hw *hw =
3830 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3831 uint32_t intr_vector = 0;
3832 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3836 PMD_INIT_FUNC_TRACE();
3838 hw->mac.ops.reset_hw(hw);
3839 hw->mac.get_link_status = true;
3841 /* negotiate mailbox API version to use with the PF. */
3842 ixgbevf_negotiate_api(hw);
3844 ixgbevf_dev_tx_init(dev);
3846 /* This can fail when allocating mbufs for descriptor rings */
3847 err = ixgbevf_dev_rx_init(dev);
3849 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3850 ixgbe_dev_clear_queues(dev);
3855 ixgbevf_set_vfta_all(dev,1);
3858 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3859 ETH_VLAN_EXTEND_MASK;
3860 ixgbevf_vlan_offload_set(dev, mask);
3862 ixgbevf_dev_rxtx_start(dev);
3864 /* check and configure queue intr-vector mapping */
3865 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3866 intr_vector = dev->data->nb_rx_queues;
3867 if (rte_intr_efd_enable(intr_handle, intr_vector))
3871 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3872 intr_handle->intr_vec =
3873 rte_zmalloc("intr_vec",
3874 dev->data->nb_rx_queues * sizeof(int), 0);
3875 if (intr_handle->intr_vec == NULL) {
3876 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3877 " intr_vec\n", dev->data->nb_rx_queues);
3881 ixgbevf_configure_msix(dev);
3883 if (dev->data->dev_conf.intr_conf.lsc != 0) {
3884 if (rte_intr_allow_others(intr_handle))
3885 rte_intr_callback_register(intr_handle,
3886 ixgbevf_dev_interrupt_handler,
3889 PMD_INIT_LOG(INFO, "lsc won't enable because of"
3890 " no intr multiplex\n");
3893 rte_intr_enable(intr_handle);
3895 /* Re-enable interrupt for VF */
3896 ixgbevf_intr_enable(hw);
3902 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3904 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3905 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3907 PMD_INIT_FUNC_TRACE();
3909 hw->adapter_stopped = 1;
3910 ixgbe_stop_adapter(hw);
3913 * Clear what we set, but we still keep shadow_vfta to
3914 * restore after device starts
3916 ixgbevf_set_vfta_all(dev,0);
3918 /* Clear stored conf */
3919 dev->data->scattered_rx = 0;
3921 ixgbe_dev_clear_queues(dev);
3923 /* disable intr eventfd mapping */
3924 rte_intr_disable(intr_handle);
3926 /* Clean datapath event and queue/vec mapping */
3927 rte_intr_efd_disable(intr_handle);
3928 if (intr_handle->intr_vec != NULL) {
3929 rte_free(intr_handle->intr_vec);
3930 intr_handle->intr_vec = NULL;
3935 ixgbevf_dev_close(struct rte_eth_dev *dev)
3937 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3938 struct rte_pci_device *pci_dev;
3940 PMD_INIT_FUNC_TRACE();
3944 ixgbevf_dev_stop(dev);
3946 ixgbe_dev_free_queues(dev);
3948 /* reprogram the RAR[0] in case user changed it. */
3949 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3951 pci_dev = dev->pci_dev;
3952 if (pci_dev->intr_handle.intr_vec) {
3953 rte_free(pci_dev->intr_handle.intr_vec);
3954 pci_dev->intr_handle.intr_vec = NULL;
3958 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3960 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3961 struct ixgbe_vfta * shadow_vfta =
3962 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3963 int i = 0, j = 0, vfta = 0, mask = 1;
3965 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3966 vfta = shadow_vfta->vfta[i];
3969 for (j = 0; j < 32; j++){
3971 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3980 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3982 struct ixgbe_hw *hw =
3983 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3984 struct ixgbe_vfta * shadow_vfta =
3985 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3986 uint32_t vid_idx = 0;
3987 uint32_t vid_bit = 0;
3990 PMD_INIT_FUNC_TRACE();
3992 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3993 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3995 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3998 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3999 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4001 /* Save what we set and retore it after device reset */
4003 shadow_vfta->vfta[vid_idx] |= vid_bit;
4005 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4011 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4013 struct ixgbe_hw *hw =
4014 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4017 PMD_INIT_FUNC_TRACE();
4019 if(queue >= hw->mac.max_rx_queues)
4022 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4024 ctrl |= IXGBE_RXDCTL_VME;
4026 ctrl &= ~IXGBE_RXDCTL_VME;
4027 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4029 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4033 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4035 struct ixgbe_hw *hw =
4036 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4040 /* VF function only support hw strip feature, others are not support */
4041 if(mask & ETH_VLAN_STRIP_MASK){
4042 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4044 for(i=0; i < hw->mac.max_rx_queues; i++)
4045 ixgbevf_vlan_strip_queue_set(dev,i,on);
4050 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4054 /* we only need to do this if VMDq is enabled */
4055 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4056 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4057 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4065 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4067 uint32_t vector = 0;
4068 switch (hw->mac.mc_filter_type) {
4069 case 0: /* use bits [47:36] of the address */
4070 vector = ((uc_addr->addr_bytes[4] >> 4) |
4071 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4073 case 1: /* use bits [46:35] of the address */
4074 vector = ((uc_addr->addr_bytes[4] >> 3) |
4075 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4077 case 2: /* use bits [45:34] of the address */
4078 vector = ((uc_addr->addr_bytes[4] >> 2) |
4079 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4081 case 3: /* use bits [43:32] of the address */
4082 vector = ((uc_addr->addr_bytes[4]) |
4083 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4085 default: /* Invalid mc_filter_type */
4089 /* vector can only be 12-bits or boundary will be exceeded */
4095 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4103 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4104 const uint32_t ixgbe_uta_bit_shift = 5;
4105 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4106 const uint32_t bit1 = 0x1;
4108 struct ixgbe_hw *hw =
4109 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4110 struct ixgbe_uta_info *uta_info =
4111 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4113 /* The UTA table only exists on 82599 hardware and newer */
4114 if (hw->mac.type < ixgbe_mac_82599EB)
4117 vector = ixgbe_uta_vector(hw,mac_addr);
4118 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4119 uta_shift = vector & ixgbe_uta_bit_mask;
4121 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4125 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4127 uta_info->uta_in_use++;
4128 reg_val |= (bit1 << uta_shift);
4129 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4131 uta_info->uta_in_use--;
4132 reg_val &= ~(bit1 << uta_shift);
4133 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4136 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4138 if (uta_info->uta_in_use > 0)
4139 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4140 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4142 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4148 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4151 struct ixgbe_hw *hw =
4152 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4153 struct ixgbe_uta_info *uta_info =
4154 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4156 /* The UTA table only exists on 82599 hardware and newer */
4157 if (hw->mac.type < ixgbe_mac_82599EB)
4161 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4162 uta_info->uta_shadow[i] = ~0;
4163 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4166 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4167 uta_info->uta_shadow[i] = 0;
4168 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4176 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4178 uint32_t new_val = orig_val;
4180 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4181 new_val |= IXGBE_VMOLR_AUPE;
4182 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4183 new_val |= IXGBE_VMOLR_ROMPE;
4184 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4185 new_val |= IXGBE_VMOLR_ROPE;
4186 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4187 new_val |= IXGBE_VMOLR_BAM;
4188 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4189 new_val |= IXGBE_VMOLR_MPE;
4195 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4196 uint16_t rx_mask, uint8_t on)
4200 struct ixgbe_hw *hw =
4201 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4204 if (hw->mac.type == ixgbe_mac_82598EB) {
4205 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4206 " on 82599 hardware and newer");
4209 if (ixgbe_vmdq_mode_check(hw) < 0)
4212 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4219 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4225 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4229 const uint8_t bit1 = 0x1;
4231 struct ixgbe_hw *hw =
4232 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4234 if (ixgbe_vmdq_mode_check(hw) < 0)
4237 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4238 reg = IXGBE_READ_REG(hw, addr);
4246 IXGBE_WRITE_REG(hw, addr,reg);
4252 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4256 const uint8_t bit1 = 0x1;
4258 struct ixgbe_hw *hw =
4259 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4261 if (ixgbe_vmdq_mode_check(hw) < 0)
4264 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4265 reg = IXGBE_READ_REG(hw, addr);
4273 IXGBE_WRITE_REG(hw, addr,reg);
4279 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4280 uint64_t pool_mask, uint8_t vlan_on)
4284 struct ixgbe_hw *hw =
4285 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4287 if (ixgbe_vmdq_mode_check(hw) < 0)
4289 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4290 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4291 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4299 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4300 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4301 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4302 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4303 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4304 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4305 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4308 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4309 struct rte_eth_mirror_conf *mirror_conf,
4310 uint8_t rule_id, uint8_t on)
4312 uint32_t mr_ctl,vlvf;
4313 uint32_t mp_lsb = 0;
4314 uint32_t mv_msb = 0;
4315 uint32_t mv_lsb = 0;
4316 uint32_t mp_msb = 0;
4319 uint64_t vlan_mask = 0;
4321 const uint8_t pool_mask_offset = 32;
4322 const uint8_t vlan_mask_offset = 32;
4323 const uint8_t dst_pool_offset = 8;
4324 const uint8_t rule_mr_offset = 4;
4325 const uint8_t mirror_rule_mask= 0x0F;
4327 struct ixgbe_mirror_info *mr_info =
4328 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4329 struct ixgbe_hw *hw =
4330 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4331 uint8_t mirror_type = 0;
4333 if (ixgbe_vmdq_mode_check(hw) < 0)
4336 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4339 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4340 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4341 mirror_conf->rule_type);
4345 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4346 mirror_type |= IXGBE_MRCTL_VLME;
4347 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4348 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4349 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4350 /* search vlan id related pool vlan filter index */
4351 reg_index = ixgbe_find_vlvf_slot(hw,
4352 mirror_conf->vlan.vlan_id[i]);
4355 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4356 if ((vlvf & IXGBE_VLVF_VIEN) &&
4357 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4358 mirror_conf->vlan.vlan_id[i]))
4359 vlan_mask |= (1ULL << reg_index);
4366 mv_lsb = vlan_mask & 0xFFFFFFFF;
4367 mv_msb = vlan_mask >> vlan_mask_offset;
4369 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4370 mirror_conf->vlan.vlan_mask;
4371 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4372 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4373 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4374 mirror_conf->vlan.vlan_id[i];
4379 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4380 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4381 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4386 * if enable pool mirror, write related pool mask register,if disable
4387 * pool mirror, clear PFMRVM register
4389 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4390 mirror_type |= IXGBE_MRCTL_VPME;
4392 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4393 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4394 mr_info->mr_conf[rule_id].pool_mask =
4395 mirror_conf->pool_mask;
4400 mr_info->mr_conf[rule_id].pool_mask = 0;
4403 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4404 mirror_type |= IXGBE_MRCTL_UPME;
4405 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4406 mirror_type |= IXGBE_MRCTL_DPME;
4408 /* read mirror control register and recalculate it */
4409 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4412 mr_ctl |= mirror_type;
4413 mr_ctl &= mirror_rule_mask;
4414 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4416 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4418 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4419 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4421 /* write mirrror control register */
4422 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4424 /* write pool mirrror control register */
4425 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4426 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4427 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4430 /* write VLAN mirrror control register */
4431 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4432 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4433 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4441 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4444 uint32_t lsb_val = 0;
4445 uint32_t msb_val = 0;
4446 const uint8_t rule_mr_offset = 4;
4448 struct ixgbe_hw *hw =
4449 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4450 struct ixgbe_mirror_info *mr_info =
4451 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4453 if (ixgbe_vmdq_mode_check(hw) < 0)
4456 memset(&mr_info->mr_conf[rule_id], 0,
4457 sizeof(struct rte_eth_mirror_conf));
4459 /* clear PFVMCTL register */
4460 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4462 /* clear pool mask register */
4463 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4464 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4466 /* clear vlan mask register */
4467 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4468 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4474 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4477 struct ixgbe_hw *hw =
4478 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4480 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4481 mask |= (1 << IXGBE_MISC_VEC_ID);
4482 RTE_SET_USED(queue_id);
4483 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4485 rte_intr_enable(&dev->pci_dev->intr_handle);
4491 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4494 struct ixgbe_hw *hw =
4495 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4497 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4498 mask &= ~(1 << IXGBE_MISC_VEC_ID);
4499 RTE_SET_USED(queue_id);
4500 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4506 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4509 struct ixgbe_hw *hw =
4510 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4511 struct ixgbe_interrupt *intr =
4512 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4514 if (queue_id < 16) {
4515 ixgbe_disable_intr(hw);
4516 intr->mask |= (1 << queue_id);
4517 ixgbe_enable_intr(dev);
4518 } else if (queue_id < 32) {
4519 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4520 mask &= (1 << queue_id);
4521 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4522 } else if (queue_id < 64) {
4523 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4524 mask &= (1 << (queue_id - 32));
4525 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4527 rte_intr_enable(&dev->pci_dev->intr_handle);
4533 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4536 struct ixgbe_hw *hw =
4537 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4538 struct ixgbe_interrupt *intr =
4539 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4541 if (queue_id < 16) {
4542 ixgbe_disable_intr(hw);
4543 intr->mask &= ~(1 << queue_id);
4544 ixgbe_enable_intr(dev);
4545 } else if (queue_id < 32) {
4546 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4547 mask &= ~(1 << queue_id);
4548 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4549 } else if (queue_id < 64) {
4550 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4551 mask &= ~(1 << (queue_id - 32));
4552 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4559 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4560 uint8_t queue, uint8_t msix_vector)
4564 if (direction == -1) {
4566 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4567 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4570 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4572 /* rx or tx cause */
4573 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4574 idx = ((16 * (queue & 1)) + (8 * direction));
4575 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4576 tmp &= ~(0xFF << idx);
4577 tmp |= (msix_vector << idx);
4578 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4583 * set the IVAR registers, mapping interrupt causes to vectors
4585 * pointer to ixgbe_hw struct
4587 * 0 for Rx, 1 for Tx, -1 for other causes
4589 * queue to map the corresponding interrupt to
4591 * the vector to map to the corresponding queue
4594 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4595 uint8_t queue, uint8_t msix_vector)
4599 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4600 if (hw->mac.type == ixgbe_mac_82598EB) {
4601 if (direction == -1)
4603 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4604 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4605 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4606 tmp |= (msix_vector << (8 * (queue & 0x3)));
4607 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4608 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4609 (hw->mac.type == ixgbe_mac_X540)) {
4610 if (direction == -1) {
4612 idx = ((queue & 1) * 8);
4613 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4614 tmp &= ~(0xFF << idx);
4615 tmp |= (msix_vector << idx);
4616 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4618 /* rx or tx causes */
4619 idx = ((16 * (queue & 1)) + (8 * direction));
4620 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4621 tmp &= ~(0xFF << idx);
4622 tmp |= (msix_vector << idx);
4623 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4629 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4631 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4632 struct ixgbe_hw *hw =
4633 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4635 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4637 /* won't configure msix register if no mapping is done
4638 * between intr vector and event fd.
4640 if (!rte_intr_dp_is_en(intr_handle))
4643 /* Configure all RX queues of VF */
4644 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4645 /* Force all queue use vector 0,
4646 * as IXGBE_VF_MAXMSIVECOTR = 1
4648 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4649 intr_handle->intr_vec[q_idx] = vector_idx;
4652 /* Configure VF Rx queue ivar */
4653 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4657 * Sets up the hardware to properly generate MSI-X interrupts
4659 * board private structure
4662 ixgbe_configure_msix(struct rte_eth_dev *dev)
4664 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4665 struct ixgbe_hw *hw =
4666 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4667 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4668 uint32_t vec = IXGBE_MISC_VEC_ID;
4672 /* won't configure msix register if no mapping is done
4673 * between intr vector and event fd
4675 if (!rte_intr_dp_is_en(intr_handle))
4678 if (rte_intr_allow_others(intr_handle))
4679 vec = base = IXGBE_RX_VEC_START;
4681 /* setup GPIE for MSI-x mode */
4682 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4683 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4684 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4685 /* auto clearing and auto setting corresponding bits in EIMS
4686 * when MSI-X interrupt is triggered
4688 if (hw->mac.type == ixgbe_mac_82598EB) {
4689 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4691 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4692 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4694 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4696 /* Populate the IVAR table and set the ITR values to the
4697 * corresponding register.
4699 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4701 /* by default, 1:1 mapping */
4702 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4703 intr_handle->intr_vec[queue_id] = vec;
4704 if (vec < base + intr_handle->nb_efd - 1)
4708 switch (hw->mac.type) {
4709 case ixgbe_mac_82598EB:
4710 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4713 case ixgbe_mac_82599EB:
4714 case ixgbe_mac_X540:
4715 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4720 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4721 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4723 /* set up to autoclear timer, and the vectors */
4724 mask = IXGBE_EIMS_ENABLE_MASK;
4725 mask &= ~(IXGBE_EIMS_OTHER |
4726 IXGBE_EIMS_MAILBOX |
4729 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4732 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4733 uint16_t queue_idx, uint16_t tx_rate)
4735 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4736 uint32_t rf_dec, rf_int;
4738 uint16_t link_speed = dev->data->dev_link.link_speed;
4740 if (queue_idx >= hw->mac.max_tx_queues)
4744 /* Calculate the rate factor values to set */
4745 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4746 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4747 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4749 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4750 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4751 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4752 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4758 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4759 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4762 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4763 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4764 IXGBE_MAX_JUMBO_FRAME_SIZE))
4765 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4766 IXGBE_MMW_SIZE_JUMBO_FRAME);
4768 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4769 IXGBE_MMW_SIZE_DEFAULT);
4771 /* Set RTTBCNRC of queue X */
4772 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4773 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4774 IXGBE_WRITE_FLUSH(hw);
4779 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4780 uint16_t tx_rate, uint64_t q_msk)
4782 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4783 struct ixgbe_vf_info *vfinfo =
4784 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4785 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4786 uint32_t queue_stride =
4787 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4788 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4789 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4790 uint16_t total_rate = 0;
4792 if (queue_end >= hw->mac.max_tx_queues)
4795 if (vfinfo != NULL) {
4796 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4799 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4801 total_rate += vfinfo[vf_idx].tx_rate[idx];
4806 /* Store tx_rate for this vf. */
4807 for (idx = 0; idx < nb_q_per_pool; idx++) {
4808 if (((uint64_t)0x1 << idx) & q_msk) {
4809 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4810 vfinfo[vf].tx_rate[idx] = tx_rate;
4811 total_rate += tx_rate;
4815 if (total_rate > dev->data->dev_link.link_speed) {
4817 * Reset stored TX rate of the VF if it causes exceed
4820 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4824 /* Set RTTBCNRC of each queue/pool for vf X */
4825 for (; queue_idx <= queue_end; queue_idx++) {
4827 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4835 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4836 __attribute__((unused)) uint32_t index,
4837 __attribute__((unused)) uint32_t pool)
4839 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4843 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4844 * operation. Trap this case to avoid exhausting the [very limited]
4845 * set of PF resources used to store VF MAC addresses.
4847 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4849 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4852 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4856 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4859 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4860 struct ether_addr *mac_addr;
4865 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4866 * not support the deletion of a given MAC address.
4867 * Instead, it imposes to delete all MAC addresses, then to add again
4868 * all MAC addresses with the exception of the one to be deleted.
4870 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4873 * Add again all MAC addresses, with the exception of the deleted one
4874 * and of the permanent MAC address.
4876 for (i = 0, mac_addr = dev->data->mac_addrs;
4877 i < hw->mac.num_rar_entries; i++, mac_addr++) {
4878 /* Skip the deleted MAC address */
4881 /* Skip NULL MAC addresses */
4882 if (is_zero_ether_addr(mac_addr))
4884 /* Skip the permanent MAC address */
4885 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4887 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4890 "Adding again MAC address "
4891 "%02x:%02x:%02x:%02x:%02x:%02x failed "
4893 mac_addr->addr_bytes[0],
4894 mac_addr->addr_bytes[1],
4895 mac_addr->addr_bytes[2],
4896 mac_addr->addr_bytes[3],
4897 mac_addr->addr_bytes[4],
4898 mac_addr->addr_bytes[5],
4904 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4906 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4908 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4911 #define MAC_TYPE_FILTER_SUP(type) do {\
4912 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4913 (type) != ixgbe_mac_X550)\
4918 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4919 struct rte_eth_syn_filter *filter,
4922 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4925 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4928 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4931 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4933 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4934 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4936 if (filter->hig_pri)
4937 synqf |= IXGBE_SYN_FILTER_SYNQFP;
4939 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4941 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4943 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4945 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4946 IXGBE_WRITE_FLUSH(hw);
4951 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4952 struct rte_eth_syn_filter *filter)
4954 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4957 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4958 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4959 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4966 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4967 enum rte_filter_op filter_op,
4970 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4973 MAC_TYPE_FILTER_SUP(hw->mac.type);
4975 if (filter_op == RTE_ETH_FILTER_NOP)
4979 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4984 switch (filter_op) {
4985 case RTE_ETH_FILTER_ADD:
4986 ret = ixgbe_syn_filter_set(dev,
4987 (struct rte_eth_syn_filter *)arg,
4990 case RTE_ETH_FILTER_DELETE:
4991 ret = ixgbe_syn_filter_set(dev,
4992 (struct rte_eth_syn_filter *)arg,
4995 case RTE_ETH_FILTER_GET:
4996 ret = ixgbe_syn_filter_get(dev,
4997 (struct rte_eth_syn_filter *)arg);
5000 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5009 static inline enum ixgbe_5tuple_protocol
5010 convert_protocol_type(uint8_t protocol_value)
5012 if (protocol_value == IPPROTO_TCP)
5013 return IXGBE_FILTER_PROTOCOL_TCP;
5014 else if (protocol_value == IPPROTO_UDP)
5015 return IXGBE_FILTER_PROTOCOL_UDP;
5016 else if (protocol_value == IPPROTO_SCTP)
5017 return IXGBE_FILTER_PROTOCOL_SCTP;
5019 return IXGBE_FILTER_PROTOCOL_NONE;
5023 * add a 5tuple filter
5026 * dev: Pointer to struct rte_eth_dev.
5027 * index: the index the filter allocates.
5028 * filter: ponter to the filter that will be added.
5029 * rx_queue: the queue id the filter assigned to.
5032 * - On success, zero.
5033 * - On failure, a negative value.
5036 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5037 struct ixgbe_5tuple_filter *filter)
5039 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5040 struct ixgbe_filter_info *filter_info =
5041 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5043 uint32_t ftqf, sdpqf;
5044 uint32_t l34timir = 0;
5045 uint8_t mask = 0xff;
5048 * look for an unused 5tuple filter index,
5049 * and insert the filter to list.
5051 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5052 idx = i / (sizeof(uint32_t) * NBBY);
5053 shift = i % (sizeof(uint32_t) * NBBY);
5054 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5055 filter_info->fivetuple_mask[idx] |= 1 << shift;
5057 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5063 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5064 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5068 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5069 IXGBE_SDPQF_DSTPORT_SHIFT);
5070 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5072 ftqf = (uint32_t)(filter->filter_info.proto &
5073 IXGBE_FTQF_PROTOCOL_MASK);
5074 ftqf |= (uint32_t)((filter->filter_info.priority &
5075 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5076 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5077 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5078 if (filter->filter_info.dst_ip_mask == 0)
5079 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5080 if (filter->filter_info.src_port_mask == 0)
5081 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5082 if (filter->filter_info.dst_port_mask == 0)
5083 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5084 if (filter->filter_info.proto_mask == 0)
5085 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5086 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5087 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5088 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5090 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5091 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5092 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5093 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5095 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5096 l34timir |= (uint32_t)(filter->queue <<
5097 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5098 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5103 * remove a 5tuple filter
5106 * dev: Pointer to struct rte_eth_dev.
5107 * filter: the pointer of the filter will be removed.
5110 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5111 struct ixgbe_5tuple_filter *filter)
5113 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5114 struct ixgbe_filter_info *filter_info =
5115 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5116 uint16_t index = filter->index;
5118 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5119 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5120 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5123 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5124 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5125 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5126 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5127 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5131 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5133 struct ixgbe_hw *hw;
5134 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5136 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5138 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5141 /* refuse mtu that requires the support of scattered packets when this
5142 * feature has not been enabled before. */
5143 if (!dev->data->scattered_rx &&
5144 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5145 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5149 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5150 * request of the version 2.0 of the mailbox API.
5151 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5152 * of the mailbox API.
5153 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5154 * prior to 3.11.33 which contains the following change:
5155 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5157 ixgbevf_rlpml_set_vf(hw, max_frame);
5159 /* update max frame size */
5160 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5164 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5165 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5169 static inline struct ixgbe_5tuple_filter *
5170 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5171 struct ixgbe_5tuple_filter_info *key)
5173 struct ixgbe_5tuple_filter *it;
5175 TAILQ_FOREACH(it, filter_list, entries) {
5176 if (memcmp(key, &it->filter_info,
5177 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5184 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5186 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5187 struct ixgbe_5tuple_filter_info *filter_info)
5189 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5190 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5191 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5194 switch (filter->dst_ip_mask) {
5196 filter_info->dst_ip_mask = 0;
5197 filter_info->dst_ip = filter->dst_ip;
5200 filter_info->dst_ip_mask = 1;
5203 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5207 switch (filter->src_ip_mask) {
5209 filter_info->src_ip_mask = 0;
5210 filter_info->src_ip = filter->src_ip;
5213 filter_info->src_ip_mask = 1;
5216 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5220 switch (filter->dst_port_mask) {
5222 filter_info->dst_port_mask = 0;
5223 filter_info->dst_port = filter->dst_port;
5226 filter_info->dst_port_mask = 1;
5229 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5233 switch (filter->src_port_mask) {
5235 filter_info->src_port_mask = 0;
5236 filter_info->src_port = filter->src_port;
5239 filter_info->src_port_mask = 1;
5242 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5246 switch (filter->proto_mask) {
5248 filter_info->proto_mask = 0;
5249 filter_info->proto =
5250 convert_protocol_type(filter->proto);
5253 filter_info->proto_mask = 1;
5256 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5260 filter_info->priority = (uint8_t)filter->priority;
5265 * add or delete a ntuple filter
5268 * dev: Pointer to struct rte_eth_dev.
5269 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5270 * add: if true, add filter, if false, remove filter
5273 * - On success, zero.
5274 * - On failure, a negative value.
5277 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5278 struct rte_eth_ntuple_filter *ntuple_filter,
5281 struct ixgbe_filter_info *filter_info =
5282 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5283 struct ixgbe_5tuple_filter_info filter_5tuple;
5284 struct ixgbe_5tuple_filter *filter;
5287 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5288 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5292 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5293 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5297 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5299 if (filter != NULL && add) {
5300 PMD_DRV_LOG(ERR, "filter exists.");
5303 if (filter == NULL && !add) {
5304 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5309 filter = rte_zmalloc("ixgbe_5tuple_filter",
5310 sizeof(struct ixgbe_5tuple_filter), 0);
5313 (void)rte_memcpy(&filter->filter_info,
5315 sizeof(struct ixgbe_5tuple_filter_info));
5316 filter->queue = ntuple_filter->queue;
5317 ret = ixgbe_add_5tuple_filter(dev, filter);
5323 ixgbe_remove_5tuple_filter(dev, filter);
5329 * get a ntuple filter
5332 * dev: Pointer to struct rte_eth_dev.
5333 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5336 * - On success, zero.
5337 * - On failure, a negative value.
5340 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5341 struct rte_eth_ntuple_filter *ntuple_filter)
5343 struct ixgbe_filter_info *filter_info =
5344 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5345 struct ixgbe_5tuple_filter_info filter_5tuple;
5346 struct ixgbe_5tuple_filter *filter;
5349 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5350 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5354 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5355 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5359 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5361 if (filter == NULL) {
5362 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5365 ntuple_filter->queue = filter->queue;
5370 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5371 * @dev: pointer to rte_eth_dev structure
5372 * @filter_op:operation will be taken.
5373 * @arg: a pointer to specific structure corresponding to the filter_op
5376 * - On success, zero.
5377 * - On failure, a negative value.
5380 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5381 enum rte_filter_op filter_op,
5384 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5387 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5389 if (filter_op == RTE_ETH_FILTER_NOP)
5393 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5398 switch (filter_op) {
5399 case RTE_ETH_FILTER_ADD:
5400 ret = ixgbe_add_del_ntuple_filter(dev,
5401 (struct rte_eth_ntuple_filter *)arg,
5404 case RTE_ETH_FILTER_DELETE:
5405 ret = ixgbe_add_del_ntuple_filter(dev,
5406 (struct rte_eth_ntuple_filter *)arg,
5409 case RTE_ETH_FILTER_GET:
5410 ret = ixgbe_get_ntuple_filter(dev,
5411 (struct rte_eth_ntuple_filter *)arg);
5414 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5422 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5427 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5428 if (filter_info->ethertype_filters[i] == ethertype &&
5429 (filter_info->ethertype_mask & (1 << i)))
5436 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5441 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5442 if (!(filter_info->ethertype_mask & (1 << i))) {
5443 filter_info->ethertype_mask |= 1 << i;
5444 filter_info->ethertype_filters[i] = ethertype;
5452 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5455 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5457 filter_info->ethertype_mask &= ~(1 << idx);
5458 filter_info->ethertype_filters[idx] = 0;
5463 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5464 struct rte_eth_ethertype_filter *filter,
5467 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5468 struct ixgbe_filter_info *filter_info =
5469 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5474 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5477 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5478 filter->ether_type == ETHER_TYPE_IPv6) {
5479 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5480 " ethertype filter.", filter->ether_type);
5484 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5485 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5488 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5489 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5493 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5494 if (ret >= 0 && add) {
5495 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5496 filter->ether_type);
5499 if (ret < 0 && !add) {
5500 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5501 filter->ether_type);
5506 ret = ixgbe_ethertype_filter_insert(filter_info,
5507 filter->ether_type);
5509 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5512 etqf = IXGBE_ETQF_FILTER_EN;
5513 etqf |= (uint32_t)filter->ether_type;
5514 etqs |= (uint32_t)((filter->queue <<
5515 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5516 IXGBE_ETQS_RX_QUEUE);
5517 etqs |= IXGBE_ETQS_QUEUE_EN;
5519 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5523 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5524 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5525 IXGBE_WRITE_FLUSH(hw);
5531 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5532 struct rte_eth_ethertype_filter *filter)
5534 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5535 struct ixgbe_filter_info *filter_info =
5536 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5537 uint32_t etqf, etqs;
5540 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5542 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5543 filter->ether_type);
5547 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5548 if (etqf & IXGBE_ETQF_FILTER_EN) {
5549 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5550 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5552 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5553 IXGBE_ETQS_RX_QUEUE_SHIFT;
5560 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5561 * @dev: pointer to rte_eth_dev structure
5562 * @filter_op:operation will be taken.
5563 * @arg: a pointer to specific structure corresponding to the filter_op
5566 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5567 enum rte_filter_op filter_op,
5570 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5573 MAC_TYPE_FILTER_SUP(hw->mac.type);
5575 if (filter_op == RTE_ETH_FILTER_NOP)
5579 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5584 switch (filter_op) {
5585 case RTE_ETH_FILTER_ADD:
5586 ret = ixgbe_add_del_ethertype_filter(dev,
5587 (struct rte_eth_ethertype_filter *)arg,
5590 case RTE_ETH_FILTER_DELETE:
5591 ret = ixgbe_add_del_ethertype_filter(dev,
5592 (struct rte_eth_ethertype_filter *)arg,
5595 case RTE_ETH_FILTER_GET:
5596 ret = ixgbe_get_ethertype_filter(dev,
5597 (struct rte_eth_ethertype_filter *)arg);
5600 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5608 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5609 enum rte_filter_type filter_type,
5610 enum rte_filter_op filter_op,
5615 switch (filter_type) {
5616 case RTE_ETH_FILTER_NTUPLE:
5617 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5619 case RTE_ETH_FILTER_ETHERTYPE:
5620 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5622 case RTE_ETH_FILTER_SYN:
5623 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5625 case RTE_ETH_FILTER_FDIR:
5626 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5629 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5638 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5639 u8 **mc_addr_ptr, u32 *vmdq)
5644 mc_addr = *mc_addr_ptr;
5645 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5650 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5651 struct ether_addr *mc_addr_set,
5652 uint32_t nb_mc_addr)
5654 struct ixgbe_hw *hw;
5657 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5658 mc_addr_list = (u8 *)mc_addr_set;
5659 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5660 ixgbe_dev_addr_list_itr, TRUE);
5664 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5666 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5670 /* Enable system time for platforms where it isn't on by default. */
5671 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5672 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5673 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5675 /* Start incrementing the register used to timestamp PTP packets. */
5676 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5678 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5679 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5681 IXGBE_ETQF_FILTER_EN |
5684 /* Enable timestamping of received PTP packets. */
5685 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5686 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5687 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5689 /* Enable timestamping of transmitted PTP packets. */
5690 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5691 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5692 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5698 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5700 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5703 /* Disable timestamping of transmitted PTP packets. */
5704 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5705 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5706 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5708 /* Disable timestamping of received PTP packets. */
5709 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5710 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5711 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5713 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5714 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5716 /* Stop incrementating the System Time registers. */
5717 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5723 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5724 struct timespec *timestamp,
5725 uint32_t flags __rte_unused)
5727 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5728 uint32_t tsync_rxctl;
5732 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5733 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5736 rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5737 rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5739 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5740 timestamp->tv_nsec = 0;
5746 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5747 struct timespec *timestamp)
5749 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5750 uint32_t tsync_txctl;
5754 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5755 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5758 tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5759 tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5761 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5762 timestamp->tv_nsec = 0;
5768 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5770 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5773 const struct reg_info *reg_group;
5774 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5775 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5777 while ((reg_group = reg_set[g_ind++]))
5778 count += ixgbe_regs_group_count(reg_group);
5784 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5788 const struct reg_info *reg_group;
5790 while ((reg_group = ixgbevf_regs[g_ind++]))
5791 count += ixgbe_regs_group_count(reg_group);
5797 ixgbe_get_regs(struct rte_eth_dev *dev,
5798 struct rte_dev_reg_info *regs)
5800 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5801 uint32_t *data = regs->data;
5804 const struct reg_info *reg_group;
5805 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5806 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5808 /* Support only full register dump */
5809 if ((regs->length == 0) ||
5810 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5811 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5813 while ((reg_group = reg_set[g_ind++]))
5814 count += ixgbe_read_regs_group(dev, &data[count],
5823 ixgbevf_get_regs(struct rte_eth_dev *dev,
5824 struct rte_dev_reg_info *regs)
5826 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5827 uint32_t *data = regs->data;
5830 const struct reg_info *reg_group;
5832 /* Support only full register dump */
5833 if ((regs->length == 0) ||
5834 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5835 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5837 while ((reg_group = ixgbevf_regs[g_ind++]))
5838 count += ixgbe_read_regs_group(dev, &data[count],
5847 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5849 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5851 /* Return unit is byte count */
5852 return hw->eeprom.word_size * 2;
5856 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5857 struct rte_dev_eeprom_info *in_eeprom)
5859 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5860 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5861 uint16_t *data = in_eeprom->data;
5864 first = in_eeprom->offset >> 1;
5865 length = in_eeprom->length >> 1;
5866 if ((first > hw->eeprom.word_size) ||
5867 ((first + length) > hw->eeprom.word_size))
5870 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5872 return eeprom->ops.read_buffer(hw, first, length, data);
5876 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5877 struct rte_dev_eeprom_info *in_eeprom)
5879 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5880 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5881 uint16_t *data = in_eeprom->data;
5884 first = in_eeprom->offset >> 1;
5885 length = in_eeprom->length >> 1;
5886 if ((first > hw->eeprom.word_size) ||
5887 ((first + length) > hw->eeprom.word_size))
5890 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5892 return eeprom->ops.write_buffer(hw, first, length, data);
5896 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5898 case ixgbe_mac_X550:
5899 case ixgbe_mac_X550EM_x:
5900 return ETH_RSS_RETA_SIZE_512;
5901 case ixgbe_mac_X550_vf:
5902 case ixgbe_mac_X550EM_x_vf:
5903 return ETH_RSS_RETA_SIZE_64;
5905 return ETH_RSS_RETA_SIZE_128;
5910 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5912 case ixgbe_mac_X550:
5913 case ixgbe_mac_X550EM_x:
5914 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5915 return IXGBE_RETA(reta_idx >> 2);
5917 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5918 case ixgbe_mac_X550_vf:
5919 case ixgbe_mac_X550EM_x_vf:
5920 return IXGBE_VFRETA(reta_idx >> 2);
5922 return IXGBE_RETA(reta_idx >> 2);
5927 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5929 case ixgbe_mac_X550_vf:
5930 case ixgbe_mac_X550EM_x_vf:
5931 return IXGBE_VFMRQC;
5938 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5940 case ixgbe_mac_X550_vf:
5941 case ixgbe_mac_X550EM_x_vf:
5942 return IXGBE_VFRSSRK(i);
5944 return IXGBE_RSSRK(i);
5949 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5951 case ixgbe_mac_82599_vf:
5952 case ixgbe_mac_X540_vf:
5960 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
5961 struct rte_eth_dcb_info *dcb_info)
5963 struct ixgbe_dcb_config *dcb_config =
5964 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
5965 struct ixgbe_dcb_tc_config *tc;
5968 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
5969 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
5971 dcb_info->nb_tcs = 1;
5973 if (dcb_config->vt_mode) { /* vt is enabled*/
5974 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
5975 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
5976 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5977 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
5978 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
5979 for (j = 0; j < dcb_info->nb_tcs; j++) {
5980 dcb_info->tc_queue.tc_rxq[i][j].base =
5981 i * dcb_info->nb_tcs + j;
5982 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
5983 dcb_info->tc_queue.tc_txq[i][j].base =
5984 i * dcb_info->nb_tcs + j;
5985 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
5988 } else { /* vt is disabled*/
5989 struct rte_eth_dcb_rx_conf *rx_conf =
5990 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
5991 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5992 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
5993 if (dcb_info->nb_tcs == ETH_4_TCS) {
5994 for (i = 0; i < dcb_info->nb_tcs; i++) {
5995 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
5996 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5998 dcb_info->tc_queue.tc_txq[0][0].base = 0;
5999 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6000 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6001 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6002 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6003 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6004 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6005 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6006 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6007 for (i = 0; i < dcb_info->nb_tcs; i++) {
6008 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6009 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6011 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6012 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6013 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6014 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6015 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6016 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6017 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6018 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6019 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6020 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6021 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6022 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6023 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6024 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6025 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6026 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6029 for (i = 0; i < dcb_info->nb_tcs; i++) {
6030 tc = &dcb_config->tc_config[i];
6031 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6036 static struct rte_driver rte_ixgbe_driver = {
6038 .init = rte_ixgbe_pmd_init,
6041 static struct rte_driver rte_ixgbevf_driver = {
6043 .init = rte_ixgbevf_pmd_init,
6046 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6047 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);